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-rw-r--r--arch/arm/mach-exynos/Makefile3
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.c (renamed from arch/arm/mach-exynos/clock.c)173
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.h (renamed from arch/arm/mach-exynos/include/mach/exynos4-clock.h)1
-rw-r--r--arch/arm/mach-exynos/clock-exynos4210.c2
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c2
5 files changed, 90 insertions, 91 deletions
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5fc202cdfdb6..995e7cc02bec 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -12,7 +12,8 @@ obj- :=
12 12
13# Core 13# Core
14 14
15obj-$(CONFIG_ARCH_EXYNOS4) += common.o clock.o 15obj-$(CONFIG_ARCH_EXYNOS) += common.o
16obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
16obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o 17obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
17obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o 18obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
18 19
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock-exynos4.c
index 200874e82dcd..962c95e00c00 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/mach-exynos4/clock.c 1/*
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
@@ -26,9 +25,9 @@
26#include <mach/map.h> 25#include <mach/map.h>
27#include <mach/regs-clock.h> 26#include <mach/regs-clock.h>
28#include <mach/sysmmu.h> 27#include <mach/sysmmu.h>
29#include <mach/exynos4-clock.h>
30 28
31#include "common.h" 29#include "common.h"
30#include "clock-exynos4.h"
32 31
33#ifdef CONFIG_PM_SLEEP 32#ifdef CONFIG_PM_SLEEP
34static struct sleep_save exynos4_clock_save[] = { 33static struct sleep_save exynos4_clock_save[] = {
@@ -215,8 +214,8 @@ static struct clksrc_clk clk_mout_apll = {
215 .clk = { 214 .clk = {
216 .name = "mout_apll", 215 .name = "mout_apll",
217 }, 216 },
218 .sources = &clk_src_apll, 217 .sources = &clk_src_apll,
219 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, 218 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
220}; 219};
221 220
222struct clksrc_clk clk_sclk_apll = { 221struct clksrc_clk clk_sclk_apll = {
@@ -224,22 +223,22 @@ struct clksrc_clk clk_sclk_apll = {
224 .name = "sclk_apll", 223 .name = "sclk_apll",
225 .parent = &clk_mout_apll.clk, 224 .parent = &clk_mout_apll.clk,
226 }, 225 },
227 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, 226 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
228}; 227};
229 228
230struct clksrc_clk clk_mout_epll = { 229struct clksrc_clk clk_mout_epll = {
231 .clk = { 230 .clk = {
232 .name = "mout_epll", 231 .name = "mout_epll",
233 }, 232 },
234 .sources = &clk_src_epll, 233 .sources = &clk_src_epll,
235 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, 234 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
236}; 235};
237 236
238struct clksrc_clk clk_mout_mpll = { 237struct clksrc_clk clk_mout_mpll = {
239 .clk = { 238 .clk = {
240 .name = "mout_mpll", 239 .name = "mout_mpll",
241 }, 240 },
242 .sources = &clk_src_mpll, 241 .sources = &clk_src_mpll,
243 242
244 /* reg_src will be added in each SoCs' clock */ 243 /* reg_src will be added in each SoCs' clock */
245}; 244};
@@ -258,8 +257,8 @@ static struct clksrc_clk clk_moutcore = {
258 .clk = { 257 .clk = {
259 .name = "moutcore", 258 .name = "moutcore",
260 }, 259 },
261 .sources = &clkset_moutcore, 260 .sources = &clkset_moutcore,
262 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 }, 261 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
263}; 262};
264 263
265static struct clksrc_clk clk_coreclk = { 264static struct clksrc_clk clk_coreclk = {
@@ -267,7 +266,7 @@ static struct clksrc_clk clk_coreclk = {
267 .name = "core_clk", 266 .name = "core_clk",
268 .parent = &clk_moutcore.clk, 267 .parent = &clk_moutcore.clk,
269 }, 268 },
270 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 }, 269 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
271}; 270};
272 271
273static struct clksrc_clk clk_armclk = { 272static struct clksrc_clk clk_armclk = {
@@ -282,7 +281,7 @@ static struct clksrc_clk clk_aclk_corem0 = {
282 .name = "aclk_corem0", 281 .name = "aclk_corem0",
283 .parent = &clk_coreclk.clk, 282 .parent = &clk_coreclk.clk,
284 }, 283 },
285 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, 284 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
286}; 285};
287 286
288static struct clksrc_clk clk_aclk_cores = { 287static struct clksrc_clk clk_aclk_cores = {
@@ -290,7 +289,7 @@ static struct clksrc_clk clk_aclk_cores = {
290 .name = "aclk_cores", 289 .name = "aclk_cores",
291 .parent = &clk_coreclk.clk, 290 .parent = &clk_coreclk.clk,
292 }, 291 },
293 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, 292 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
294}; 293};
295 294
296static struct clksrc_clk clk_aclk_corem1 = { 295static struct clksrc_clk clk_aclk_corem1 = {
@@ -298,7 +297,7 @@ static struct clksrc_clk clk_aclk_corem1 = {
298 .name = "aclk_corem1", 297 .name = "aclk_corem1",
299 .parent = &clk_coreclk.clk, 298 .parent = &clk_coreclk.clk,
300 }, 299 },
301 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 }, 300 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
302}; 301};
303 302
304static struct clksrc_clk clk_periphclk = { 303static struct clksrc_clk clk_periphclk = {
@@ -306,7 +305,7 @@ static struct clksrc_clk clk_periphclk = {
306 .name = "periphclk", 305 .name = "periphclk",
307 .parent = &clk_coreclk.clk, 306 .parent = &clk_coreclk.clk,
308 }, 307 },
309 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, 308 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
310}; 309};
311 310
312/* Core list of CMU_CORE side */ 311/* Core list of CMU_CORE side */
@@ -325,8 +324,8 @@ static struct clksrc_clk clk_mout_corebus = {
325 .clk = { 324 .clk = {
326 .name = "mout_corebus", 325 .name = "mout_corebus",
327 }, 326 },
328 .sources = &clkset_mout_corebus, 327 .sources = &clkset_mout_corebus,
329 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, 328 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
330}; 329};
331 330
332static struct clksrc_clk clk_sclk_dmc = { 331static struct clksrc_clk clk_sclk_dmc = {
@@ -334,7 +333,7 @@ static struct clksrc_clk clk_sclk_dmc = {
334 .name = "sclk_dmc", 333 .name = "sclk_dmc",
335 .parent = &clk_mout_corebus.clk, 334 .parent = &clk_mout_corebus.clk,
336 }, 335 },
337 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, 336 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
338}; 337};
339 338
340static struct clksrc_clk clk_aclk_cored = { 339static struct clksrc_clk clk_aclk_cored = {
@@ -342,7 +341,7 @@ static struct clksrc_clk clk_aclk_cored = {
342 .name = "aclk_cored", 341 .name = "aclk_cored",
343 .parent = &clk_sclk_dmc.clk, 342 .parent = &clk_sclk_dmc.clk,
344 }, 343 },
345 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, 344 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
346}; 345};
347 346
348static struct clksrc_clk clk_aclk_corep = { 347static struct clksrc_clk clk_aclk_corep = {
@@ -350,7 +349,7 @@ static struct clksrc_clk clk_aclk_corep = {
350 .name = "aclk_corep", 349 .name = "aclk_corep",
351 .parent = &clk_aclk_cored.clk, 350 .parent = &clk_aclk_cored.clk,
352 }, 351 },
353 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, 352 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
354}; 353};
355 354
356static struct clksrc_clk clk_aclk_acp = { 355static struct clksrc_clk clk_aclk_acp = {
@@ -358,7 +357,7 @@ static struct clksrc_clk clk_aclk_acp = {
358 .name = "aclk_acp", 357 .name = "aclk_acp",
359 .parent = &clk_mout_corebus.clk, 358 .parent = &clk_mout_corebus.clk,
360 }, 359 },
361 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, 360 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
362}; 361};
363 362
364static struct clksrc_clk clk_pclk_acp = { 363static struct clksrc_clk clk_pclk_acp = {
@@ -366,7 +365,7 @@ static struct clksrc_clk clk_pclk_acp = {
366 .name = "pclk_acp", 365 .name = "pclk_acp",
367 .parent = &clk_aclk_acp.clk, 366 .parent = &clk_aclk_acp.clk,
368 }, 367 },
369 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, 368 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
370}; 369};
371 370
372/* Core list of CMU_TOP side */ 371/* Core list of CMU_TOP side */
@@ -385,36 +384,36 @@ static struct clksrc_clk clk_aclk_200 = {
385 .clk = { 384 .clk = {
386 .name = "aclk_200", 385 .name = "aclk_200",
387 }, 386 },
388 .sources = &clkset_aclk, 387 .sources = &clkset_aclk,
389 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, 388 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
390 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 }, 389 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
391}; 390};
392 391
393static struct clksrc_clk clk_aclk_100 = { 392static struct clksrc_clk clk_aclk_100 = {
394 .clk = { 393 .clk = {
395 .name = "aclk_100", 394 .name = "aclk_100",
396 }, 395 },
397 .sources = &clkset_aclk, 396 .sources = &clkset_aclk,
398 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, 397 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
399 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 }, 398 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
400}; 399};
401 400
402static struct clksrc_clk clk_aclk_160 = { 401static struct clksrc_clk clk_aclk_160 = {
403 .clk = { 402 .clk = {
404 .name = "aclk_160", 403 .name = "aclk_160",
405 }, 404 },
406 .sources = &clkset_aclk, 405 .sources = &clkset_aclk,
407 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, 406 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
408 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 }, 407 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
409}; 408};
410 409
411struct clksrc_clk clk_aclk_133 = { 410struct clksrc_clk clk_aclk_133 = {
412 .clk = { 411 .clk = {
413 .name = "aclk_133", 412 .name = "aclk_133",
414 }, 413 },
415 .sources = &clkset_aclk, 414 .sources = &clkset_aclk,
416 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, 415 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
417 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 }, 416 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
418}; 417};
419 418
420static struct clk *clkset_vpllsrc_list[] = { 419static struct clk *clkset_vpllsrc_list[] = {
@@ -433,8 +432,8 @@ static struct clksrc_clk clk_vpllsrc = {
433 .enable = exynos4_clksrc_mask_top_ctrl, 432 .enable = exynos4_clksrc_mask_top_ctrl,
434 .ctrlbit = (1 << 0), 433 .ctrlbit = (1 << 0),
435 }, 434 },
436 .sources = &clkset_vpllsrc, 435 .sources = &clkset_vpllsrc,
437 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 }, 436 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
438}; 437};
439 438
440static struct clk *clkset_sclk_vpll_list[] = { 439static struct clk *clkset_sclk_vpll_list[] = {
@@ -451,8 +450,8 @@ struct clksrc_clk clk_sclk_vpll = {
451 .clk = { 450 .clk = {
452 .name = "sclk_vpll", 451 .name = "sclk_vpll",
453 }, 452 },
454 .sources = &clkset_sclk_vpll, 453 .sources = &clkset_sclk_vpll,
455 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, 454 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
456}; 455};
457 456
458static struct clk init_clocks_off[] = { 457static struct clk init_clocks_off[] = {
@@ -816,8 +815,8 @@ static struct clksrc_clk clk_mout_g2d0 = {
816 .clk = { 815 .clk = {
817 .name = "mout_g2d0", 816 .name = "mout_g2d0",
818 }, 817 },
819 .sources = &clkset_mout_g2d0, 818 .sources = &clkset_mout_g2d0,
820 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 }, 819 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
821}; 820};
822 821
823static struct clk *clkset_mout_g2d1_list[] = { 822static struct clk *clkset_mout_g2d1_list[] = {
@@ -834,8 +833,8 @@ static struct clksrc_clk clk_mout_g2d1 = {
834 .clk = { 833 .clk = {
835 .name = "mout_g2d1", 834 .name = "mout_g2d1",
836 }, 835 },
837 .sources = &clkset_mout_g2d1, 836 .sources = &clkset_mout_g2d1,
838 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 }, 837 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
839}; 838};
840 839
841static struct clk *clkset_mout_g2d_list[] = { 840static struct clk *clkset_mout_g2d_list[] = {
@@ -862,8 +861,8 @@ static struct clksrc_clk clk_mout_mfc0 = {
862 .clk = { 861 .clk = {
863 .name = "mout_mfc0", 862 .name = "mout_mfc0",
864 }, 863 },
865 .sources = &clkset_mout_mfc0, 864 .sources = &clkset_mout_mfc0,
866 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 }, 865 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
867}; 866};
868 867
869static struct clk *clkset_mout_mfc1_list[] = { 868static struct clk *clkset_mout_mfc1_list[] = {
@@ -880,8 +879,8 @@ static struct clksrc_clk clk_mout_mfc1 = {
880 .clk = { 879 .clk = {
881 .name = "mout_mfc1", 880 .name = "mout_mfc1",
882 }, 881 },
883 .sources = &clkset_mout_mfc1, 882 .sources = &clkset_mout_mfc1,
884 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 }, 883 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
885}; 884};
886 885
887static struct clk *clkset_mout_mfc_list[] = { 886static struct clk *clkset_mout_mfc_list[] = {
@@ -917,7 +916,7 @@ static struct clksrc_clk clk_sclk_dac = {
917static struct clksrc_clk clk_sclk_pixel = { 916static struct clksrc_clk clk_sclk_pixel = {
918 .clk = { 917 .clk = {
919 .name = "sclk_pixel", 918 .name = "sclk_pixel",
920 .parent = &clk_sclk_vpll.clk, 919 .parent = &clk_sclk_vpll.clk,
921 }, 920 },
922 .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 }, 921 .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
923}; 922};
@@ -953,7 +952,7 @@ static struct clksrc_sources clkset_sclk_mixer = {
953}; 952};
954 953
955static struct clksrc_clk clk_sclk_mixer = { 954static struct clksrc_clk clk_sclk_mixer = {
956 .clk = { 955 .clk = {
957 .name = "sclk_mixer", 956 .name = "sclk_mixer",
958 .enable = exynos4_clksrc_mask_tv_ctrl, 957 .enable = exynos4_clksrc_mask_tv_ctrl,
959 .ctrlbit = (1 << 4), 958 .ctrlbit = (1 << 4),
@@ -970,7 +969,7 @@ static struct clksrc_clk *sclk_tv[] = {
970}; 969};
971 970
972static struct clksrc_clk clk_dout_mmc0 = { 971static struct clksrc_clk clk_dout_mmc0 = {
973 .clk = { 972 .clk = {
974 .name = "dout_mmc0", 973 .name = "dout_mmc0",
975 }, 974 },
976 .sources = &clkset_group, 975 .sources = &clkset_group,
@@ -979,7 +978,7 @@ static struct clksrc_clk clk_dout_mmc0 = {
979}; 978};
980 979
981static struct clksrc_clk clk_dout_mmc1 = { 980static struct clksrc_clk clk_dout_mmc1 = {
982 .clk = { 981 .clk = {
983 .name = "dout_mmc1", 982 .name = "dout_mmc1",
984 }, 983 },
985 .sources = &clkset_group, 984 .sources = &clkset_group,
@@ -988,7 +987,7 @@ static struct clksrc_clk clk_dout_mmc1 = {
988}; 987};
989 988
990static struct clksrc_clk clk_dout_mmc2 = { 989static struct clksrc_clk clk_dout_mmc2 = {
991 .clk = { 990 .clk = {
992 .name = "dout_mmc2", 991 .name = "dout_mmc2",
993 }, 992 },
994 .sources = &clkset_group, 993 .sources = &clkset_group,
@@ -997,7 +996,7 @@ static struct clksrc_clk clk_dout_mmc2 = {
997}; 996};
998 997
999static struct clksrc_clk clk_dout_mmc3 = { 998static struct clksrc_clk clk_dout_mmc3 = {
1000 .clk = { 999 .clk = {
1001 .name = "dout_mmc3", 1000 .name = "dout_mmc3",
1002 }, 1001 },
1003 .sources = &clkset_group, 1002 .sources = &clkset_group,
@@ -1016,7 +1015,7 @@ static struct clksrc_clk clk_dout_mmc4 = {
1016 1015
1017static struct clksrc_clk clksrcs[] = { 1016static struct clksrc_clk clksrcs[] = {
1018 { 1017 {
1019 .clk = { 1018 .clk = {
1020 .name = "sclk_pwm", 1019 .name = "sclk_pwm",
1021 .enable = exynos4_clksrc_mask_peril0_ctrl, 1020 .enable = exynos4_clksrc_mask_peril0_ctrl,
1022 .ctrlbit = (1 << 24), 1021 .ctrlbit = (1 << 24),
@@ -1025,7 +1024,7 @@ static struct clksrc_clk clksrcs[] = {
1025 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 }, 1024 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1026 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 }, 1025 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1027 }, { 1026 }, {
1028 .clk = { 1027 .clk = {
1029 .name = "sclk_csis", 1028 .name = "sclk_csis",
1030 .devname = "s5p-mipi-csis.0", 1029 .devname = "s5p-mipi-csis.0",
1031 .enable = exynos4_clksrc_mask_cam_ctrl, 1030 .enable = exynos4_clksrc_mask_cam_ctrl,
@@ -1035,7 +1034,7 @@ static struct clksrc_clk clksrcs[] = {
1035 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 }, 1034 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
1036 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 }, 1035 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
1037 }, { 1036 }, {
1038 .clk = { 1037 .clk = {
1039 .name = "sclk_csis", 1038 .name = "sclk_csis",
1040 .devname = "s5p-mipi-csis.1", 1039 .devname = "s5p-mipi-csis.1",
1041 .enable = exynos4_clksrc_mask_cam_ctrl, 1040 .enable = exynos4_clksrc_mask_cam_ctrl,
@@ -1045,7 +1044,7 @@ static struct clksrc_clk clksrcs[] = {
1045 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 }, 1044 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
1046 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 }, 1045 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
1047 }, { 1046 }, {
1048 .clk = { 1047 .clk = {
1049 .name = "sclk_cam0", 1048 .name = "sclk_cam0",
1050 .enable = exynos4_clksrc_mask_cam_ctrl, 1049 .enable = exynos4_clksrc_mask_cam_ctrl,
1051 .ctrlbit = (1 << 16), 1050 .ctrlbit = (1 << 16),
@@ -1054,7 +1053,7 @@ static struct clksrc_clk clksrcs[] = {
1054 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 }, 1053 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
1055 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 }, 1054 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
1056 }, { 1055 }, {
1057 .clk = { 1056 .clk = {
1058 .name = "sclk_cam1", 1057 .name = "sclk_cam1",
1059 .enable = exynos4_clksrc_mask_cam_ctrl, 1058 .enable = exynos4_clksrc_mask_cam_ctrl,
1060 .ctrlbit = (1 << 20), 1059 .ctrlbit = (1 << 20),
@@ -1063,7 +1062,7 @@ static struct clksrc_clk clksrcs[] = {
1063 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 }, 1062 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
1064 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 }, 1063 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
1065 }, { 1064 }, {
1066 .clk = { 1065 .clk = {
1067 .name = "sclk_fimc", 1066 .name = "sclk_fimc",
1068 .devname = "exynos4-fimc.0", 1067 .devname = "exynos4-fimc.0",
1069 .enable = exynos4_clksrc_mask_cam_ctrl, 1068 .enable = exynos4_clksrc_mask_cam_ctrl,
@@ -1073,7 +1072,7 @@ static struct clksrc_clk clksrcs[] = {
1073 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 }, 1072 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
1074 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 }, 1073 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
1075 }, { 1074 }, {
1076 .clk = { 1075 .clk = {
1077 .name = "sclk_fimc", 1076 .name = "sclk_fimc",
1078 .devname = "exynos4-fimc.1", 1077 .devname = "exynos4-fimc.1",
1079 .enable = exynos4_clksrc_mask_cam_ctrl, 1078 .enable = exynos4_clksrc_mask_cam_ctrl,
@@ -1083,7 +1082,7 @@ static struct clksrc_clk clksrcs[] = {
1083 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 }, 1082 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
1084 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 }, 1083 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
1085 }, { 1084 }, {
1086 .clk = { 1085 .clk = {
1087 .name = "sclk_fimc", 1086 .name = "sclk_fimc",
1088 .devname = "exynos4-fimc.2", 1087 .devname = "exynos4-fimc.2",
1089 .enable = exynos4_clksrc_mask_cam_ctrl, 1088 .enable = exynos4_clksrc_mask_cam_ctrl,
@@ -1093,7 +1092,7 @@ static struct clksrc_clk clksrcs[] = {
1093 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 }, 1092 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
1094 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 }, 1093 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
1095 }, { 1094 }, {
1096 .clk = { 1095 .clk = {
1097 .name = "sclk_fimc", 1096 .name = "sclk_fimc",
1098 .devname = "exynos4-fimc.3", 1097 .devname = "exynos4-fimc.3",
1099 .enable = exynos4_clksrc_mask_cam_ctrl, 1098 .enable = exynos4_clksrc_mask_cam_ctrl,
@@ -1103,7 +1102,7 @@ static struct clksrc_clk clksrcs[] = {
1103 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 }, 1102 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
1104 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 }, 1103 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
1105 }, { 1104 }, {
1106 .clk = { 1105 .clk = {
1107 .name = "sclk_fimd", 1106 .name = "sclk_fimd",
1108 .devname = "exynos4-fb.0", 1107 .devname = "exynos4-fb.0",
1109 .enable = exynos4_clksrc_mask_lcd0_ctrl, 1108 .enable = exynos4_clksrc_mask_lcd0_ctrl,
@@ -1113,14 +1112,14 @@ static struct clksrc_clk clksrcs[] = {
1113 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 }, 1112 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
1114 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 }, 1113 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
1115 }, { 1114 }, {
1116 .clk = { 1115 .clk = {
1117 .name = "sclk_fimg2d", 1116 .name = "sclk_fimg2d",
1118 }, 1117 },
1119 .sources = &clkset_mout_g2d, 1118 .sources = &clkset_mout_g2d,
1120 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 }, 1119 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1121 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 }, 1120 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1122 }, { 1121 }, {
1123 .clk = { 1122 .clk = {
1124 .name = "sclk_mfc", 1123 .name = "sclk_mfc",
1125 .devname = "s5p-mfc", 1124 .devname = "s5p-mfc",
1126 }, 1125 },
@@ -1128,9 +1127,9 @@ static struct clksrc_clk clksrcs[] = {
1128 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 }, 1127 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1129 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, 1128 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1130 }, { 1129 }, {
1131 .clk = { 1130 .clk = {
1132 .name = "sclk_dwmmc", 1131 .name = "sclk_dwmmc",
1133 .parent = &clk_dout_mmc4.clk, 1132 .parent = &clk_dout_mmc4.clk,
1134 .enable = exynos4_clksrc_mask_fsys_ctrl, 1133 .enable = exynos4_clksrc_mask_fsys_ctrl,
1135 .ctrlbit = (1 << 16), 1134 .ctrlbit = (1 << 16),
1136 }, 1135 },
@@ -1151,7 +1150,7 @@ static struct clksrc_clk clk_sclk_uart0 = {
1151}; 1150};
1152 1151
1153static struct clksrc_clk clk_sclk_uart1 = { 1152static struct clksrc_clk clk_sclk_uart1 = {
1154 .clk = { 1153 .clk = {
1155 .name = "uclk1", 1154 .name = "uclk1",
1156 .devname = "exynos4210-uart.1", 1155 .devname = "exynos4210-uart.1",
1157 .enable = exynos4_clksrc_mask_peril0_ctrl, 1156 .enable = exynos4_clksrc_mask_peril0_ctrl,
@@ -1163,7 +1162,7 @@ static struct clksrc_clk clk_sclk_uart1 = {
1163}; 1162};
1164 1163
1165static struct clksrc_clk clk_sclk_uart2 = { 1164static struct clksrc_clk clk_sclk_uart2 = {
1166 .clk = { 1165 .clk = {
1167 .name = "uclk1", 1166 .name = "uclk1",
1168 .devname = "exynos4210-uart.2", 1167 .devname = "exynos4210-uart.2",
1169 .enable = exynos4_clksrc_mask_peril0_ctrl, 1168 .enable = exynos4_clksrc_mask_peril0_ctrl,
@@ -1175,7 +1174,7 @@ static struct clksrc_clk clk_sclk_uart2 = {
1175}; 1174};
1176 1175
1177static struct clksrc_clk clk_sclk_uart3 = { 1176static struct clksrc_clk clk_sclk_uart3 = {
1178 .clk = { 1177 .clk = {
1179 .name = "uclk1", 1178 .name = "uclk1",
1180 .devname = "exynos4210-uart.3", 1179 .devname = "exynos4210-uart.3",
1181 .enable = exynos4_clksrc_mask_peril0_ctrl, 1180 .enable = exynos4_clksrc_mask_peril0_ctrl,
@@ -1187,7 +1186,7 @@ static struct clksrc_clk clk_sclk_uart3 = {
1187}; 1186};
1188 1187
1189static struct clksrc_clk clk_sclk_mmc0 = { 1188static struct clksrc_clk clk_sclk_mmc0 = {
1190 .clk = { 1189 .clk = {
1191 .name = "sclk_mmc", 1190 .name = "sclk_mmc",
1192 .devname = "s3c-sdhci.0", 1191 .devname = "s3c-sdhci.0",
1193 .parent = &clk_dout_mmc0.clk, 1192 .parent = &clk_dout_mmc0.clk,
@@ -1198,10 +1197,10 @@ static struct clksrc_clk clk_sclk_mmc0 = {
1198}; 1197};
1199 1198
1200static struct clksrc_clk clk_sclk_mmc1 = { 1199static struct clksrc_clk clk_sclk_mmc1 = {
1201 .clk = { 1200 .clk = {
1202 .name = "sclk_mmc", 1201 .name = "sclk_mmc",
1203 .devname = "s3c-sdhci.1", 1202 .devname = "s3c-sdhci.1",
1204 .parent = &clk_dout_mmc1.clk, 1203 .parent = &clk_dout_mmc1.clk,
1205 .enable = exynos4_clksrc_mask_fsys_ctrl, 1204 .enable = exynos4_clksrc_mask_fsys_ctrl,
1206 .ctrlbit = (1 << 4), 1205 .ctrlbit = (1 << 4),
1207 }, 1206 },
@@ -1209,10 +1208,10 @@ static struct clksrc_clk clk_sclk_mmc1 = {
1209}; 1208};
1210 1209
1211static struct clksrc_clk clk_sclk_mmc2 = { 1210static struct clksrc_clk clk_sclk_mmc2 = {
1212 .clk = { 1211 .clk = {
1213 .name = "sclk_mmc", 1212 .name = "sclk_mmc",
1214 .devname = "s3c-sdhci.2", 1213 .devname = "s3c-sdhci.2",
1215 .parent = &clk_dout_mmc2.clk, 1214 .parent = &clk_dout_mmc2.clk,
1216 .enable = exynos4_clksrc_mask_fsys_ctrl, 1215 .enable = exynos4_clksrc_mask_fsys_ctrl,
1217 .ctrlbit = (1 << 8), 1216 .ctrlbit = (1 << 8),
1218 }, 1217 },
@@ -1220,10 +1219,10 @@ static struct clksrc_clk clk_sclk_mmc2 = {
1220}; 1219};
1221 1220
1222static struct clksrc_clk clk_sclk_mmc3 = { 1221static struct clksrc_clk clk_sclk_mmc3 = {
1223 .clk = { 1222 .clk = {
1224 .name = "sclk_mmc", 1223 .name = "sclk_mmc",
1225 .devname = "s3c-sdhci.3", 1224 .devname = "s3c-sdhci.3",
1226 .parent = &clk_dout_mmc3.clk, 1225 .parent = &clk_dout_mmc3.clk,
1227 .enable = exynos4_clksrc_mask_fsys_ctrl, 1226 .enable = exynos4_clksrc_mask_fsys_ctrl,
1228 .ctrlbit = (1 << 12), 1227 .ctrlbit = (1 << 12),
1229 }, 1228 },
@@ -1231,11 +1230,11 @@ static struct clksrc_clk clk_sclk_mmc3 = {
1231}; 1230};
1232 1231
1233static struct clksrc_clk clk_sclk_spi0 = { 1232static struct clksrc_clk clk_sclk_spi0 = {
1234 .clk = { 1233 .clk = {
1235 .name = "sclk_spi", 1234 .name = "sclk_spi",
1236 .devname = "s3c64xx-spi.0", 1235 .devname = "s3c64xx-spi.0",
1237 .enable = exynos4_clksrc_mask_peril1_ctrl, 1236 .enable = exynos4_clksrc_mask_peril1_ctrl,
1238 .ctrlbit = (1 << 16), 1237 .ctrlbit = (1 << 16),
1239 }, 1238 },
1240 .sources = &clkset_group, 1239 .sources = &clkset_group,
1241 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 }, 1240 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
@@ -1243,11 +1242,11 @@ static struct clksrc_clk clk_sclk_spi0 = {
1243}; 1242};
1244 1243
1245static struct clksrc_clk clk_sclk_spi1 = { 1244static struct clksrc_clk clk_sclk_spi1 = {
1246 .clk = { 1245 .clk = {
1247 .name = "sclk_spi", 1246 .name = "sclk_spi",
1248 .devname = "s3c64xx-spi.1", 1247 .devname = "s3c64xx-spi.1",
1249 .enable = exynos4_clksrc_mask_peril1_ctrl, 1248 .enable = exynos4_clksrc_mask_peril1_ctrl,
1250 .ctrlbit = (1 << 20), 1249 .ctrlbit = (1 << 20),
1251 }, 1250 },
1252 .sources = &clkset_group, 1251 .sources = &clkset_group,
1253 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 }, 1252 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
@@ -1255,11 +1254,11 @@ static struct clksrc_clk clk_sclk_spi1 = {
1255}; 1254};
1256 1255
1257static struct clksrc_clk clk_sclk_spi2 = { 1256static struct clksrc_clk clk_sclk_spi2 = {
1258 .clk = { 1257 .clk = {
1259 .name = "sclk_spi", 1258 .name = "sclk_spi",
1260 .devname = "s3c64xx-spi.2", 1259 .devname = "s3c64xx-spi.2",
1261 .enable = exynos4_clksrc_mask_peril1_ctrl, 1260 .enable = exynos4_clksrc_mask_peril1_ctrl,
1262 .ctrlbit = (1 << 24), 1261 .ctrlbit = (1 << 24),
1263 }, 1262 },
1264 .sources = &clkset_group, 1263 .sources = &clkset_group,
1265 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 }, 1264 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
diff --git a/arch/arm/mach-exynos/include/mach/exynos4-clock.h b/arch/arm/mach-exynos/clock-exynos4.h
index a07fcbf55251..f64e9f784a31 100644
--- a/arch/arm/mach-exynos/include/mach/exynos4-clock.h
+++ b/arch/arm/mach-exynos/clock-exynos4.h
@@ -1,5 +1,4 @@
1/* 1/*
2 * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
3 * 2 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com 4 * http://www.samsung.com
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index 54a92efcf5b1..904240109d94 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -28,9 +28,9 @@
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <mach/map.h> 29#include <mach/map.h>
30#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
31#include <mach/exynos4-clock.h>
32 31
33#include "common.h" 32#include "common.h"
33#include "clock-exynos4.h"
34 34
35#ifdef CONFIG_PM_SLEEP 35#ifdef CONFIG_PM_SLEEP
36static struct sleep_save exynos4210_clock_save[] = { 36static struct sleep_save exynos4210_clock_save[] = {
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 8e07ab13ff19..e93de7fc3cd9 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -28,9 +28,9 @@
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <mach/map.h> 29#include <mach/map.h>
30#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
31#include <mach/exynos4-clock.h>
32 31
33#include "common.h" 32#include "common.h"
33#include "clock-exynos4.h"
34 34
35#ifdef CONFIG_PM_SLEEP 35#ifdef CONFIG_PM_SLEEP
36static struct sleep_save exynos4212_clock_save[] = { 36static struct sleep_save exynos4212_clock_save[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-02 12:44:31 -0500