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-rw-r--r--arch/mips/Kconfig8
-rw-r--r--arch/mips/jmr3927/rbhma3100/irq.c48
-rw-r--r--arch/mips/jmr3927/rbhma3100/setup.c13
-rw-r--r--arch/mips/tx4927/common/tx4927_irq.c395
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c171
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c11
-rw-r--r--arch/mips/tx4938/common/irq.c279
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/irq.c2
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/setup.c9
-rw-r--r--include/asm-mips/jmr3927/jmr3927.h3
-rw-r--r--include/asm-mips/jmr3927/tx3927.h36
-rw-r--r--include/asm-mips/tx4927/toshiba_rbtx4927.h2
-rw-r--r--include/asm-mips/tx4927/tx4927.h49
-rw-r--r--include/asm-mips/tx4927/tx4927_pci.h23
-rw-r--r--include/asm-mips/tx4938/rbtx4938.h25
-rw-r--r--include/asm-mips/tx4938/tx4938.h41
16 files changed, 55 insertions, 1060 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cec0d8411269..4b02d8acc15b 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -528,6 +528,7 @@ config TOSHIBA_JMR3927
528 select DMA_NONCOHERENT 528 select DMA_NONCOHERENT
529 select HW_HAS_PCI 529 select HW_HAS_PCI
530 select MIPS_TX3927 530 select MIPS_TX3927
531 select IRQ_TXX9
531 select SWAP_IO_SPACE 532 select SWAP_IO_SPACE
532 select SYS_HAS_CPU_TX39XX 533 select SYS_HAS_CPU_TX39XX
533 select SYS_SUPPORTS_32BIT_KERNEL 534 select SYS_SUPPORTS_32BIT_KERNEL
@@ -540,7 +541,9 @@ config TOSHIBA_RBTX4927
540 select DMA_NONCOHERENT 541 select DMA_NONCOHERENT
541 select HAS_TXX9_SERIAL 542 select HAS_TXX9_SERIAL
542 select HW_HAS_PCI 543 select HW_HAS_PCI
543 select I8259 544 select IRQ_CPU
545 select IRQ_TXX9
546 select I8259 if TOSHIBA_FPCIB0
544 select SWAP_IO_SPACE 547 select SWAP_IO_SPACE
545 select SYS_HAS_CPU_TX49XX 548 select SYS_HAS_CPU_TX49XX
546 select SYS_SUPPORTS_32BIT_KERNEL 549 select SYS_SUPPORTS_32BIT_KERNEL
@@ -560,7 +563,8 @@ config TOSHIBA_RBTX4938
560 select GENERIC_ISA_DMA 563 select GENERIC_ISA_DMA
561 select HAS_TXX9_SERIAL 564 select HAS_TXX9_SERIAL
562 select HW_HAS_PCI 565 select HW_HAS_PCI
563 select I8259 566 select IRQ_CPU
567 select IRQ_TXX9
564 select SWAP_IO_SPACE 568 select SWAP_IO_SPACE
565 select SYS_HAS_CPU_TX49XX 569 select SYS_HAS_CPU_TX49XX
566 select SYS_SUPPORTS_32BIT_KERNEL 570 select SYS_SUPPORTS_32BIT_KERNEL
diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c
index 1187b44a3dd4..d9efe692e551 100644
--- a/arch/mips/jmr3927/rbhma3100/irq.c
+++ b/arch/mips/jmr3927/rbhma3100/irq.c
@@ -45,9 +45,6 @@
45#error JMR3927_IRQ_END > NR_IRQS 45#error JMR3927_IRQ_END > NR_IRQS
46#endif 46#endif
47 47
48#define irc_dlevel 0
49#define irc_elevel 1
50
51static unsigned char irc_level[TX3927_NUM_IR] = { 48static unsigned char irc_level[TX3927_NUM_IR] = {
52 5, 5, 5, 5, 5, 5, /* INT[5:0] */ 49 5, 5, 5, 5, 5, 5, /* INT[5:0] */
53 7, 7, /* SIO */ 50 7, 7, /* SIO */
@@ -80,34 +77,6 @@ static void unmask_irq_ioc(unsigned int irq)
80 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); 77 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
81} 78}
82 79
83static void mask_irq_irc(unsigned int irq)
84{
85 unsigned int irq_nr = irq - JMR3927_IRQ_IRC;
86 volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
87 if (irq_nr & 1)
88 *ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8);
89 else
90 *ilrp = (*ilrp & 0xff00) | irc_dlevel;
91 /* update IRCSR */
92 tx3927_ircptr->imr = 0;
93 tx3927_ircptr->imr = irc_elevel;
94 /* flush write buffer */
95 (void)tx3927_ircptr->ssr;
96}
97
98static void unmask_irq_irc(unsigned int irq)
99{
100 unsigned int irq_nr = irq - JMR3927_IRQ_IRC;
101 volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
102 if (irq_nr & 1)
103 *ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8);
104 else
105 *ilrp = (*ilrp & 0xff00) | irc_level[irq_nr];
106 /* update IRCSR */
107 tx3927_ircptr->imr = 0;
108 tx3927_ircptr->imr = irc_elevel;
109}
110
111asmlinkage void plat_irq_dispatch(void) 80asmlinkage void plat_irq_dispatch(void)
112{ 81{
113 unsigned long cp0_cause = read_c0_cause(); 82 unsigned long cp0_cause = read_c0_cause();
@@ -168,10 +137,6 @@ void __init arch_init_irq(void)
168 /* clear PCI Reset interrupts */ 137 /* clear PCI Reset interrupts */
169 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); 138 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
170 139
171 /* enable interrupt control */
172 tx3927_ircptr->cer = TX3927_IRCER_ICE;
173 tx3927_ircptr->imr = irc_elevel;
174
175 jmr3927_irq_init(); 140 jmr3927_irq_init();
176 141
177 /* setup IOC interrupt 1 (PCI, MODEM) */ 142 /* setup IOC interrupt 1 (PCI, MODEM) */
@@ -193,20 +158,13 @@ static struct irq_chip jmr3927_irq_ioc = {
193 .unmask = unmask_irq_ioc, 158 .unmask = unmask_irq_ioc,
194}; 159};
195 160
196static struct irq_chip jmr3927_irq_irc = {
197 .name = "jmr3927_irc",
198 .ack = mask_irq_irc,
199 .mask = mask_irq_irc,
200 .mask_ack = mask_irq_irc,
201 .unmask = unmask_irq_irc,
202};
203
204static void __init jmr3927_irq_init(void) 161static void __init jmr3927_irq_init(void)
205{ 162{
206 u32 i; 163 u32 i;
207 164
208 for (i = JMR3927_IRQ_IRC; i < JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC; i++) 165 txx9_irq_init(TX3927_IRC_REG);
209 set_irq_chip_and_handler(i, &jmr3927_irq_irc, handle_level_irq); 166 for (i = 0; i < TXx9_MAX_IR; i++)
167 txx9_irq_set_pri(i, irc_level[i]);
210 for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) 168 for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
211 set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq); 169 set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
212} 170}
diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c
index 8303001516d2..fde56e86c2ab 100644
--- a/arch/mips/jmr3927/rbhma3100/setup.c
+++ b/arch/mips/jmr3927/rbhma3100/setup.c
@@ -290,19 +290,6 @@ static void __init tx3927_setup(void)
290 tx3927_ccfgptr->crir, 290 tx3927_ccfgptr->crir,
291 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); 291 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
292 292
293 /* IRC */
294 /* disable interrupt control */
295 tx3927_ircptr->cer = 0;
296 /* mask all IRC interrupts */
297 tx3927_ircptr->imr = 0;
298 for (i = 0; i < TX3927_NUM_IR / 2; i++) {
299 tx3927_ircptr->ilr[i] = 0;
300 }
301 /* setup IRC interrupt mode (Low Active) */
302 for (i = 0; i < TX3927_NUM_IR / 8; i++) {
303 tx3927_ircptr->cr[i] = 0;
304 }
305
306 /* TMR */ 293 /* TMR */
307 /* disable all timers */ 294 /* disable all timers */
308 for (i = 0; i < TX3927_NR_TMR; i++) { 295 for (i = 0; i < TX3927_NR_TMR; i++) {
diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c
index 00b0b975f349..0aabd57fdad2 100644
--- a/arch/mips/tx4927/common/tx4927_irq.c
+++ b/arch/mips/tx4927/common/tx4927_irq.c
@@ -23,398 +23,20 @@
23 * with this program; if not, write to the Free Software Foundation, Inc., 23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */ 25 */
26#include <linux/errno.h>
27#include <linux/init.h> 26#include <linux/init.h>
28#include <linux/kernel_stat.h>
29#include <linux/module.h>
30#include <linux/signal.h>
31#include <linux/sched.h>
32#include <linux/types.h>
33#include <linux/interrupt.h> 27#include <linux/interrupt.h>
34#include <linux/ioport.h> 28#include <asm/irq_cpu.h>
35#include <linux/timex.h>
36#include <linux/slab.h>
37#include <linux/random.h>
38#include <linux/irq.h>
39#include <linux/bitops.h>
40#include <asm/bootinfo.h>
41#include <asm/io.h>
42#include <asm/irq.h>
43#include <asm/mipsregs.h> 29#include <asm/mipsregs.h>
44#include <asm/system.h>
45#include <asm/tx4927/tx4927.h> 30#include <asm/tx4927/tx4927.h>
46#ifdef CONFIG_TOSHIBA_RBTX4927 31#ifdef CONFIG_TOSHIBA_RBTX4927
47#include <asm/tx4927/toshiba_rbtx4927.h> 32#include <asm/tx4927/toshiba_rbtx4927.h>
48#endif 33#endif
49 34
50/*
51 * DEBUG
52 */
53
54#undef TX4927_IRQ_DEBUG
55
56#ifdef TX4927_IRQ_DEBUG
57#define TX4927_IRQ_NONE 0x00000000
58
59#define TX4927_IRQ_INFO ( 1 << 0 )
60#define TX4927_IRQ_WARN ( 1 << 1 )
61#define TX4927_IRQ_EROR ( 1 << 2 )
62
63#define TX4927_IRQ_INIT ( 1 << 5 )
64#define TX4927_IRQ_NEST1 ( 1 << 6 )
65#define TX4927_IRQ_NEST2 ( 1 << 7 )
66#define TX4927_IRQ_NEST3 ( 1 << 8 )
67#define TX4927_IRQ_NEST4 ( 1 << 9 )
68
69#define TX4927_IRQ_CP0_INIT ( 1 << 10 )
70#define TX4927_IRQ_CP0_ENABLE ( 1 << 13 )
71#define TX4927_IRQ_CP0_DISABLE ( 1 << 14 )
72
73#define TX4927_IRQ_PIC_INIT ( 1 << 20 )
74#define TX4927_IRQ_PIC_ENABLE ( 1 << 23 )
75#define TX4927_IRQ_PIC_DISABLE ( 1 << 24 )
76
77#define TX4927_IRQ_ALL 0xffffffff
78#endif
79
80#ifdef TX4927_IRQ_DEBUG
81static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE
82 | TX4927_IRQ_INFO
83 | TX4927_IRQ_WARN | TX4927_IRQ_EROR
84// | TX4927_IRQ_CP0_INIT
85// | TX4927_IRQ_CP0_ENABLE
86// | TX4927_IRQ_CP0_ENDIRQ
87// | TX4927_IRQ_PIC_INIT
88// | TX4927_IRQ_PIC_ENABLE
89// | TX4927_IRQ_PIC_DISABLE
90// | TX4927_IRQ_INIT
91// | TX4927_IRQ_NEST1
92// | TX4927_IRQ_NEST2
93// | TX4927_IRQ_NEST3
94// | TX4927_IRQ_NEST4
95 );
96#endif
97
98#ifdef TX4927_IRQ_DEBUG
99#define TX4927_IRQ_DPRINTK(flag,str...) \
100 if ( (tx4927_irq_debug_flag) & (flag) ) \
101 { \
102 char tmp[100]; \
103 sprintf( tmp, str ); \
104 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
105 }
106#else
107#define TX4927_IRQ_DPRINTK(flag,str...)
108#endif
109
110/*
111 * Forwad definitions for all pic's
112 */
113
114static void tx4927_irq_cp0_enable(unsigned int irq);
115static void tx4927_irq_cp0_disable(unsigned int irq);
116
117static void tx4927_irq_pic_enable(unsigned int irq);
118static void tx4927_irq_pic_disable(unsigned int irq);
119
120/*
121 * Kernel structs for all pic's
122 */
123
124#define TX4927_CP0_NAME "TX4927-CP0"
125static struct irq_chip tx4927_irq_cp0_type = {
126 .name = TX4927_CP0_NAME,
127 .ack = tx4927_irq_cp0_disable,
128 .mask = tx4927_irq_cp0_disable,
129 .mask_ack = tx4927_irq_cp0_disable,
130 .unmask = tx4927_irq_cp0_enable,
131};
132
133#define TX4927_PIC_NAME "TX4927-PIC"
134static struct irq_chip tx4927_irq_pic_type = {
135 .name = TX4927_PIC_NAME,
136 .ack = tx4927_irq_pic_disable,
137 .mask = tx4927_irq_pic_disable,
138 .mask_ack = tx4927_irq_pic_disable,
139 .unmask = tx4927_irq_pic_enable,
140};
141
142#define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
143static struct irqaction tx4927_irq_pic_action =
144TX4927_PIC_ACTION(TX4927_PIC_NAME);
145
146#define CCP0_STATUS 12
147#define CCP0_CAUSE 13
148
149/*
150 * Functions for cp0
151 */
152
153#define tx4927_irq_cp0_mask(irq) ( 1 << ( irq-TX4927_IRQ_CP0_BEG+8 ) )
154
155static void
156tx4927_irq_cp0_modify(unsigned cp0_reg, unsigned clr_bits, unsigned set_bits)
157{
158 unsigned long val = 0;
159
160 switch (cp0_reg) {
161 case CCP0_STATUS:
162 val = read_c0_status();
163 break;
164
165 case CCP0_CAUSE:
166 val = read_c0_cause();
167 break;
168
169 }
170
171 val &= (~clr_bits);
172 val |= (set_bits);
173
174 switch (cp0_reg) {
175 case CCP0_STATUS:{
176 write_c0_status(val);
177 break;
178 }
179 case CCP0_CAUSE:{
180 write_c0_cause(val);
181 break;
182 }
183 }
184}
185
186static void __init tx4927_irq_cp0_init(void)
187{
188 int i;
189
190 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_INIT, "beg=%d end=%d\n",
191 TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END);
192
193 for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++)
194 set_irq_chip_and_handler(i, &tx4927_irq_cp0_type,
195 handle_level_irq);
196}
197
198static void tx4927_irq_cp0_enable(unsigned int irq)
199{
200 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENABLE, "irq=%d \n", irq);
201
202 tx4927_irq_cp0_modify(CCP0_STATUS, 0, tx4927_irq_cp0_mask(irq));
203}
204
205static void tx4927_irq_cp0_disable(unsigned int irq)
206{
207 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_DISABLE, "irq=%d \n", irq);
208
209 tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0);
210}
211
212/*
213 * Functions for pic
214 */
215u32 tx4927_irq_pic_addr(int irq)
216{
217 /* MVMCP -- need to formulize this */
218 irq -= TX4927_IRQ_PIC_BEG;
219 switch (irq) {
220 case 17:
221 case 16:
222 case 1:
223 case 0:
224 return (0xff1ff610);
225
226 case 19:
227 case 18:
228 case 3:
229 case 2:
230 return (0xff1ff614);
231
232 case 21:
233 case 20:
234 case 5:
235 case 4:
236 return (0xff1ff618);
237
238 case 23:
239 case 22:
240 case 7:
241 case 6:
242 return (0xff1ff61c);
243
244 case 25:
245 case 24:
246 case 9:
247 case 8:
248 return (0xff1ff620);
249
250 case 27:
251 case 26:
252 case 11:
253 case 10:
254 return (0xff1ff624);
255
256 case 29:
257 case 28:
258 case 13:
259 case 12:
260 return (0xff1ff628);
261
262 case 31:
263 case 30:
264 case 15:
265 case 14:
266 return (0xff1ff62c);
267
268 }
269 return (0);
270}
271
272u32 tx4927_irq_pic_mask(int irq)
273{
274 /* MVMCP -- need to formulize this */
275 irq -= TX4927_IRQ_PIC_BEG;
276 switch (irq) {
277 case 31:
278 case 29:
279 case 27:
280 case 25:
281 case 23:
282 case 21:
283 case 19:
284 case 17:{
285 return (0x07000000);
286 }
287 case 30:
288 case 28:
289 case 26:
290 case 24:
291 case 22:
292 case 20:
293 case 18:
294 case 16:{
295 return (0x00070000);
296 }
297 case 15:
298 case 13:
299 case 11:
300 case 9:
301 case 7:
302 case 5:
303 case 3:
304 case 1:{
305 return (0x00000700);
306 }
307 case 14:
308 case 12:
309 case 10:
310 case 8:
311 case 6:
312 case 4:
313 case 2:
314 case 0:{
315 return (0x00000007);
316 }
317 }
318 return (0x00000000);
319}
320
321static void tx4927_irq_pic_modify(unsigned pic_reg, unsigned clr_bits,
322 unsigned set_bits)
323{
324 unsigned long val = 0;
325
326 val = TX4927_RD(pic_reg);
327 val &= (~clr_bits);
328 val |= (set_bits);
329 TX4927_WR(pic_reg, val);
330}
331
332static void __init tx4927_irq_pic_init(void)
333{
334 int i;
335
336 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_INIT, "beg=%d end=%d\n",
337 TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END);
338
339 for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++)
340 set_irq_chip_and_handler(i, &tx4927_irq_pic_type,
341 handle_level_irq);
342
343 setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action);
344
345 TX4927_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
346 TX4927_WR(0xff1ff600, TX4927_RD(0xff1ff600) | 0x1); /* irq enable */
347}
348
349static void tx4927_irq_pic_enable(unsigned int irq)
350{
351 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENABLE, "irq=%d\n", irq);
352
353 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 0,
354 tx4927_irq_pic_mask(irq));
355}
356
357static void tx4927_irq_pic_disable(unsigned int irq)
358{
359 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_DISABLE, "irq=%d\n", irq);
360
361 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq),
362 tx4927_irq_pic_mask(irq), 0);
363}
364
365/*
366 * Main init functions
367 */
368void __init tx4927_irq_init(void) 35void __init tx4927_irq_init(void)
369{ 36{
370 TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "-\n"); 37 mips_cpu_irq_init();
371 38 txx9_irq_init(TX4927_IRC_REG);
372 TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "=Calling tx4927_irq_cp0_init()\n"); 39 set_irq_chained_handler(TX4927_IRQ_NEST_PIC_ON_CP0, handle_simple_irq);
373 tx4927_irq_cp0_init();
374
375 TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "=Calling tx4927_irq_pic_init()\n");
376 tx4927_irq_pic_init();
377
378 TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "+\n");
379}
380
381static int tx4927_irq_nested(void)
382{
383 int sw_irq = 0;
384 u32 level2;
385
386 TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST1, "-\n");
387
388 level2 = TX4927_RD(0xff1ff6a0);
389 TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST2, "=level2a=0x%x\n", level2);
390
391 if ((level2 & 0x10000) == 0) {
392 level2 &= 0x1f;
393 TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST3, "=level2b=0x%x\n", level2);
394
395 sw_irq = TX4927_IRQ_PIC_BEG + level2;
396 TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST3, "=sw_irq=%d\n", sw_irq);
397
398 if (sw_irq == 27) {
399 TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST4, "=irq-%d\n",
400 sw_irq);
401
402#ifdef CONFIG_TOSHIBA_RBTX4927
403 {
404 sw_irq = toshiba_rbtx4927_irq_nested(sw_irq);
405 }
406#endif
407
408 TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST4, "=irq+%d\n",
409 sw_irq);
410 }
411 }
412
413 TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST2, "=sw_irq=%d\n", sw_irq);
414
415 TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST1, "+\n");
416
417 return (sw_irq);
418} 40}
419 41
420asmlinkage void plat_irq_dispatch(void) 42asmlinkage void plat_irq_dispatch(void)
@@ -424,9 +46,12 @@ asmlinkage void plat_irq_dispatch(void)
424 if (pending & STATUSF_IP7) /* cpu timer */ 46 if (pending & STATUSF_IP7) /* cpu timer */
425 do_IRQ(TX4927_IRQ_CPU_TIMER); 47 do_IRQ(TX4927_IRQ_CPU_TIMER);
426 else if (pending & STATUSF_IP2) { /* tx4927 pic */ 48 else if (pending & STATUSF_IP2) { /* tx4927 pic */
427 unsigned int irq = tx4927_irq_nested(); 49 int irq = txx9_irq();
428 50#ifdef CONFIG_TOSHIBA_RBTX4927
429 if (unlikely(irq == 0)) { 51 if (irq == TX4927_IRQ_NEST_EXT_ON_PIC)
52 irq = toshiba_rbtx4927_irq_nested(irq);
53#endif
54 if (unlikely(irq < 0)) {
430 spurious_interrupt(); 55 spurious_interrupt();
431 return; 56 return;
432 } 57 }
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
index e265fcd31b60..9607ad5e734a 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -133,6 +133,7 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
133#include <linux/bootmem.h> 133#include <linux/bootmem.h>
134#include <linux/blkdev.h> 134#include <linux/blkdev.h>
135#ifdef CONFIG_TOSHIBA_FPCIB0 135#ifdef CONFIG_TOSHIBA_FPCIB0
136#include <asm/i8259.h>
136#include <asm/tx4927/smsc_fdc37m81x.h> 137#include <asm/tx4927/smsc_fdc37m81x.h>
137#endif 138#endif
138#include <asm/tx4927/toshiba_rbtx4927.h> 139#include <asm/tx4927/toshiba_rbtx4927.h>
@@ -151,11 +152,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
151#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 ) 152#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 )
152#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 ) 153#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 )
153 154
154#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 )
155#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 )
156#define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 )
157#define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 )
158
159#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff 155#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
160#endif 156#endif
161 157
@@ -167,10 +163,6 @@ static const u32 toshiba_rbtx4927_irq_debug_flag =
167// | TOSHIBA_RBTX4927_IRQ_IOC_INIT 163// | TOSHIBA_RBTX4927_IRQ_IOC_INIT
168// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE 164// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
169// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE 165// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
170// | TOSHIBA_RBTX4927_IRQ_ISA_INIT
171// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
172// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
173// | TOSHIBA_RBTX4927_IRQ_ISA_MASK
174 ); 166 );
175#endif 167#endif
176 168
@@ -196,33 +188,14 @@ static const u32 toshiba_rbtx4927_irq_debug_flag =
196#define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */ 188#define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */
197#define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */ 189#define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */
198 190
199
200#define TOSHIBA_RBTX4927_IRQ_ISA_BEG MI8259_IRQ_ISA_BEG
201#define TOSHIBA_RBTX4927_IRQ_ISA_END MI8259_IRQ_ISA_END
202#define TOSHIBA_RBTX4927_IRQ_ISA_MID ((TOSHIBA_RBTX4927_IRQ_ISA_BEG+TOSHIBA_RBTX4927_IRQ_ISA_END+1)/2)
203
204
205#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC 191#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC
206#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2) 192#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2)
207#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA (TOSHIBA_RBTX4927_IRQ_ISA_BEG+2)
208 193
209extern int tx4927_using_backplane; 194extern int tx4927_using_backplane;
210 195
211#ifdef CONFIG_TOSHIBA_FPCIB0
212extern void enable_8259A_irq(unsigned int irq);
213extern void disable_8259A_irq(unsigned int irq);
214extern void mask_and_ack_8259A(unsigned int irq);
215#endif
216
217static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); 196static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
218static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); 197static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
219 198
220#ifdef CONFIG_TOSHIBA_FPCIB0
221static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
222static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq);
223static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq);
224#endif
225
226#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC" 199#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
227static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { 200static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
228 .name = TOSHIBA_RBTX4927_IOC_NAME, 201 .name = TOSHIBA_RBTX4927_IOC_NAME,
@@ -235,18 +208,6 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
235#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006 208#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
236 209
237 210
238#ifdef CONFIG_TOSHIBA_FPCIB0
239#define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA"
240static struct irq_chip toshiba_rbtx4927_irq_isa_type = {
241 .name = TOSHIBA_RBTX4927_ISA_NAME,
242 .ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
243 .mask = toshiba_rbtx4927_irq_isa_disable,
244 .mask_ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
245 .unmask = toshiba_rbtx4927_irq_isa_enable,
246};
247#endif
248
249
250u32 bit2num(u32 num) 211u32 bit2num(u32 num)
251{ 212{
252 u32 i; 213 u32 i;
@@ -271,31 +232,10 @@ int toshiba_rbtx4927_irq_nested(int sw_irq)
271 } 232 }
272 } 233 }
273#ifdef CONFIG_TOSHIBA_FPCIB0 234#ifdef CONFIG_TOSHIBA_FPCIB0
274 { 235 if (tx4927_using_backplane) {
275 if (tx4927_using_backplane) { 236 int irq = i8259_irq();
276 u32 level4; 237 if (irq >= 0)
277 u32 level5; 238 sw_irq = irq;
278 outb(0x0A, 0x20);
279 level4 = inb(0x20) & 0xff;
280 if (level4) {
281 sw_irq =
282 TOSHIBA_RBTX4927_IRQ_ISA_BEG +
283 bit2num(level4);
284 if (sw_irq !=
285 TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA) {
286 goto RETURN;
287 }
288 }
289
290 outb(0x0A, 0xA0);
291 level5 = inb(0xA0) & 0xff;
292 if (level5) {
293 sw_irq =
294 TOSHIBA_RBTX4927_IRQ_ISA_MID +
295 bit2num(level5);
296 goto RETURN;
297 }
298 }
299 } 239 }
300#endif 240#endif
301 241
@@ -307,12 +247,6 @@ int toshiba_rbtx4927_irq_nested(int sw_irq)
307#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, IRQF_SHARED, CPU_MASK_NONE, s, NULL, NULL } 247#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, IRQF_SHARED, CPU_MASK_NONE, s, NULL, NULL }
308static struct irqaction toshiba_rbtx4927_irq_ioc_action = 248static struct irqaction toshiba_rbtx4927_irq_ioc_action =
309TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME); 249TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME);
310#ifdef CONFIG_TOSHIBA_FPCIB0
311static struct irqaction toshiba_rbtx4927_irq_isa_master =
312TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/M");
313static struct irqaction toshiba_rbtx4927_irq_isa_slave =
314TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/S");
315#endif
316 250
317 251
318/**********************************************************************************/ 252/**********************************************************************************/
@@ -378,92 +312,6 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
378} 312}
379 313
380 314
381/**********************************************************************************/
382/* Functions for isa */
383/**********************************************************************************/
384
385
386#ifdef CONFIG_TOSHIBA_FPCIB0
387static void __init toshiba_rbtx4927_irq_isa_init(void)
388{
389 int i;
390
391 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_INIT,
392 "beg=%d end=%d\n",
393 TOSHIBA_RBTX4927_IRQ_ISA_BEG,
394 TOSHIBA_RBTX4927_IRQ_ISA_END);
395
396 for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG;
397 i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++)
398 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_isa_type,
399 handle_level_irq);
400
401 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
402 &toshiba_rbtx4927_irq_isa_master);
403 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA,
404 &toshiba_rbtx4927_irq_isa_slave);
405
406 /* make sure we are looking at IRR (not ISR) */
407 outb(0x0A, 0x20);
408 outb(0x0A, 0xA0);
409}
410#endif
411
412
413#ifdef CONFIG_TOSHIBA_FPCIB0
414static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq)
415{
416 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENABLE,
417 "irq=%d\n", irq);
418
419 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
420 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
421 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
422 "bad irq=%d\n", irq);
423 panic("\n");
424 }
425
426 enable_8259A_irq(irq);
427}
428#endif
429
430
431#ifdef CONFIG_TOSHIBA_FPCIB0
432static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq)
433{
434 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_DISABLE,
435 "irq=%d\n", irq);
436
437 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
438 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
439 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
440 "bad irq=%d\n", irq);
441 panic("\n");
442 }
443
444 disable_8259A_irq(irq);
445}
446#endif
447
448
449#ifdef CONFIG_TOSHIBA_FPCIB0
450static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq)
451{
452 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_MASK,
453 "irq=%d\n", irq);
454
455 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
456 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
457 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
458 "bad irq=%d\n", irq);
459 panic("\n");
460 }
461
462 mask_and_ack_8259A(irq);
463}
464#endif
465
466
467void __init arch_init_irq(void) 315void __init arch_init_irq(void)
468{ 316{
469 extern void tx4927_irq_init(void); 317 extern void tx4927_irq_init(void);
@@ -471,12 +319,11 @@ void __init arch_init_irq(void)
471 tx4927_irq_init(); 319 tx4927_irq_init();
472 toshiba_rbtx4927_irq_ioc_init(); 320 toshiba_rbtx4927_irq_ioc_init();
473#ifdef CONFIG_TOSHIBA_FPCIB0 321#ifdef CONFIG_TOSHIBA_FPCIB0
474 { 322 if (tx4927_using_backplane)
475 if (tx4927_using_backplane) { 323 init_i8259_irqs();
476 toshiba_rbtx4927_irq_isa_init();
477 }
478 }
479#endif 324#endif
325 /* Onboard 10M Ether: High Active */
326 set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);
480 327
481 wbflush(); 328 wbflush();
482} 329}
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
index ea5a70b252a0..3e84237abe63 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
@@ -151,7 +151,6 @@ unsigned long mips_memory_upper;
151static int tx4927_ccfg_toeon = 1; 151static int tx4927_ccfg_toeon = 1;
152static int tx4927_pcic_trdyto = 0; /* default: disabled */ 152static int tx4927_pcic_trdyto = 0; /* default: disabled */
153unsigned long tx4927_ce_base[8]; 153unsigned long tx4927_ce_base[8];
154void tx4927_pci_setup(void);
155void tx4927_reset_pci_pcic(void); 154void tx4927_reset_pci_pcic(void);
156int tx4927_pci66 = 0; /* 0:auto */ 155int tx4927_pci66 = 0; /* 0:auto */
157#endif 156#endif
@@ -442,7 +441,7 @@ arch_initcall(tx4927_pcibios_init);
442extern struct resource pci_io_resource; 441extern struct resource pci_io_resource;
443extern struct resource pci_mem_resource; 442extern struct resource pci_mem_resource;
444 443
445void tx4927_pci_setup(void) 444void __init tx4927_pci_setup(void)
446{ 445{
447 static int called = 0; 446 static int called = 0;
448 extern unsigned int tx4927_get_mem_size(void); 447 extern unsigned int tx4927_get_mem_size(void);
@@ -748,12 +747,6 @@ void __init toshiba_rbtx4927_setup(void)
748 } 747 }
749#endif 748#endif
750 749
751 /* setup irq stuff */
752 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
753 ":Setting up tx4927 pic.\n");
754 TX4927_WR(0xff1ff604, 0x00000400); /* irq trigger */
755 TX4927_WR(0xff1ff608, 0x00000000); /* irq trigger */
756
757 /* setup serial stuff */ 750 /* setup serial stuff */
758 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, 751 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
759 ":Setting up tx4927 sio.\n"); 752 ":Setting up tx4927 sio.\n");
@@ -915,7 +908,7 @@ void __init toshiba_rbtx4927_setup(void)
915 req.iotype = UPIO_MEM; 908 req.iotype = UPIO_MEM;
916 req.membase = (char *)(0xff1ff300 + i * 0x100); 909 req.membase = (char *)(0xff1ff300 + i * 0x100);
917 req.mapbase = 0xff1ff300 + i * 0x100; 910 req.mapbase = 0xff1ff300 + i * 0x100;
918 req.irq = 32 + i; 911 req.irq = TX4927_IRQ_PIC_BEG + 8 + i;
919 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; 912 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
920 req.uartclk = 50000000; 913 req.uartclk = 50000000;
921 early_serial_txx9_setup(&req); 914 early_serial_txx9_setup(&req);
diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c
index 3a2dbfc25014..c059b899d120 100644
--- a/arch/mips/tx4938/common/irq.c
+++ b/arch/mips/tx4938/common/irq.c
@@ -11,284 +11,21 @@
11 * 11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) 12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */ 13 */
14#include <linux/errno.h>
15#include <linux/init.h> 14#include <linux/init.h>
16#include <linux/kernel_stat.h>
17#include <linux/module.h>
18#include <linux/signal.h>
19#include <linux/sched.h>
20#include <linux/types.h>
21#include <linux/interrupt.h> 15#include <linux/interrupt.h>
22#include <linux/ioport.h> 16#include <asm/irq_cpu.h>
23#include <linux/timex.h>
24#include <linux/slab.h>
25#include <linux/random.h>
26#include <linux/irq.h>
27#include <asm/bitops.h>
28#include <asm/bootinfo.h>
29#include <asm/io.h>
30#include <asm/irq.h>
31#include <asm/mipsregs.h> 17#include <asm/mipsregs.h>
32#include <asm/system.h>
33#include <asm/wbflush.h>
34#include <asm/tx4938/rbtx4938.h> 18#include <asm/tx4938/rbtx4938.h>
35 19
36/**********************************************************************************/
37/* Forwad definitions for all pic's */
38/**********************************************************************************/
39
40static void tx4938_irq_cp0_enable(unsigned int irq);
41static void tx4938_irq_cp0_disable(unsigned int irq);
42
43static void tx4938_irq_pic_enable(unsigned int irq);
44static void tx4938_irq_pic_disable(unsigned int irq);
45
46/**********************************************************************************/
47/* Kernel structs for all pic's */
48/**********************************************************************************/
49
50#define TX4938_CP0_NAME "TX4938-CP0"
51static struct irq_chip tx4938_irq_cp0_type = {
52 .name = TX4938_CP0_NAME,
53 .ack = tx4938_irq_cp0_disable,
54 .mask = tx4938_irq_cp0_disable,
55 .mask_ack = tx4938_irq_cp0_disable,
56 .unmask = tx4938_irq_cp0_enable,
57};
58
59#define TX4938_PIC_NAME "TX4938-PIC"
60static struct irq_chip tx4938_irq_pic_type = {
61 .name = TX4938_PIC_NAME,
62 .ack = tx4938_irq_pic_disable,
63 .mask = tx4938_irq_pic_disable,
64 .mask_ack = tx4938_irq_pic_disable,
65 .unmask = tx4938_irq_pic_enable,
66};
67
68static struct irqaction tx4938_irq_pic_action = {
69 .handler = no_action,
70 .flags = 0,
71 .mask = CPU_MASK_NONE,
72 .name = TX4938_PIC_NAME
73};
74
75/**********************************************************************************/
76/* Functions for cp0 */
77/**********************************************************************************/
78
79#define tx4938_irq_cp0_mask(irq) ( 1 << ( irq-TX4938_IRQ_CP0_BEG+8 ) )
80
81static void __init
82tx4938_irq_cp0_init(void)
83{
84 int i;
85
86 for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++)
87 set_irq_chip_and_handler(i, &tx4938_irq_cp0_type,
88 handle_level_irq);
89}
90
91static void
92tx4938_irq_cp0_enable(unsigned int irq)
93{
94 set_c0_status(tx4938_irq_cp0_mask(irq));
95}
96
97static void
98tx4938_irq_cp0_disable(unsigned int irq)
99{
100 clear_c0_status(tx4938_irq_cp0_mask(irq));
101}
102
103/**********************************************************************************/
104/* Functions for pic */
105/**********************************************************************************/
106
107u32
108tx4938_irq_pic_addr(int irq)
109{
110 /* MVMCP -- need to formulize this */
111 irq -= TX4938_IRQ_PIC_BEG;
112
113 switch (irq) {
114 case 17:
115 case 16:
116 case 1:
117 case 0:{
118 return (TX4938_MKA(TX4938_IRC_IRLVL0));
119 }
120 case 19:
121 case 18:
122 case 3:
123 case 2:{
124 return (TX4938_MKA(TX4938_IRC_IRLVL1));
125 }
126 case 21:
127 case 20:
128 case 5:
129 case 4:{
130 return (TX4938_MKA(TX4938_IRC_IRLVL2));
131 }
132 case 23:
133 case 22:
134 case 7:
135 case 6:{
136 return (TX4938_MKA(TX4938_IRC_IRLVL3));
137 }
138 case 25:
139 case 24:
140 case 9:
141 case 8:{
142 return (TX4938_MKA(TX4938_IRC_IRLVL4));
143 }
144 case 27:
145 case 26:
146 case 11:
147 case 10:{
148 return (TX4938_MKA(TX4938_IRC_IRLVL5));
149 }
150 case 29:
151 case 28:
152 case 13:
153 case 12:{
154 return (TX4938_MKA(TX4938_IRC_IRLVL6));
155 }
156 case 31:
157 case 30:
158 case 15:
159 case 14:{
160 return (TX4938_MKA(TX4938_IRC_IRLVL7));
161 }
162 }
163
164 return 0;
165}
166
167u32
168tx4938_irq_pic_mask(int irq)
169{
170 /* MVMCP -- need to formulize this */
171 irq -= TX4938_IRQ_PIC_BEG;
172
173 switch (irq) {
174 case 31:
175 case 29:
176 case 27:
177 case 25:
178 case 23:
179 case 21:
180 case 19:
181 case 17:{
182 return (0x07000000);
183 }
184 case 30:
185 case 28:
186 case 26:
187 case 24:
188 case 22:
189 case 20:
190 case 18:
191 case 16:{
192 return (0x00070000);
193 }
194 case 15:
195 case 13:
196 case 11:
197 case 9:
198 case 7:
199 case 5:
200 case 3:
201 case 1:{
202 return (0x00000700);
203 }
204 case 14:
205 case 12:
206 case 10:
207 case 8:
208 case 6:
209 case 4:
210 case 2:
211 case 0:{
212 return (0x00000007);
213 }
214 }
215 return 0x00000000;
216}
217
218static void
219tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits)
220{
221 unsigned long val = 0;
222
223 val = TX4938_RD(pic_reg);
224 val &= (~clr_bits);
225 val |= (set_bits);
226 TX4938_WR(pic_reg, val);
227 mmiowb();
228 TX4938_RD(pic_reg);
229}
230
231static void __init
232tx4938_irq_pic_init(void)
233{
234 int i;
235
236 for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++)
237 set_irq_chip_and_handler(i, &tx4938_irq_pic_type,
238 handle_level_irq);
239
240 setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action);
241
242 TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
243 TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */
244}
245
246static void
247tx4938_irq_pic_enable(unsigned int irq)
248{
249 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0,
250 tx4938_irq_pic_mask(irq));
251}
252
253static void
254tx4938_irq_pic_disable(unsigned int irq)
255{
256 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq),
257 tx4938_irq_pic_mask(irq), 0);
258}
259
260/**********************************************************************************/
261/* Main init functions */
262/**********************************************************************************/
263
264void __init 20void __init
265tx4938_irq_init(void) 21tx4938_irq_init(void)
266{ 22{
267 tx4938_irq_cp0_init(); 23 mips_cpu_irq_init();
268 tx4938_irq_pic_init(); 24 txx9_irq_init(TX4938_IRC_REG);
25 set_irq_chained_handler(TX4938_IRQ_NEST_PIC_ON_CP0, handle_simple_irq);
269} 26}
270 27
271int 28int toshiba_rbtx4938_irq_nested(int irq);
272tx4938_irq_nested(void)
273{
274 int sw_irq = 0;
275 u32 level2;
276
277 level2 = TX4938_RD(0xff1ff6a0);
278 if ((level2 & 0x10000) == 0) {
279 level2 &= 0x1f;
280 sw_irq = TX4938_IRQ_PIC_BEG + level2;
281 if (sw_irq == 26) {
282 {
283 extern int toshiba_rbtx4938_irq_nested(int sw_irq);
284 sw_irq = toshiba_rbtx4938_irq_nested(sw_irq);
285 }
286 }
287 }
288
289 wbflush();
290 return sw_irq;
291}
292 29
293asmlinkage void plat_irq_dispatch(void) 30asmlinkage void plat_irq_dispatch(void)
294{ 31{
@@ -297,8 +34,10 @@ asmlinkage void plat_irq_dispatch(void)
297 if (pending & STATUSF_IP7) 34 if (pending & STATUSF_IP7)
298 do_IRQ(TX4938_IRQ_CPU_TIMER); 35 do_IRQ(TX4938_IRQ_CPU_TIMER);
299 else if (pending & STATUSF_IP2) { 36 else if (pending & STATUSF_IP2) {
300 int irq = tx4938_irq_nested(); 37 int irq = txx9_irq();
301 if (irq) 38 if (irq == TX4938_IRQ_PIC_BEG + TX4938_IR_INT(0))
39 irq = toshiba_rbtx4938_irq_nested(irq);
40 if (irq >= 0)
302 do_IRQ(irq); 41 do_IRQ(irq);
303 else 42 else
304 spurious_interrupt(); 43 spurious_interrupt();
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
index 91aea7aff515..f00185017e80 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
@@ -181,7 +181,7 @@ void __init arch_init_irq(void)
181 tx4938_irq_init(); 181 tx4938_irq_init();
182 toshiba_rbtx4938_irq_ioc_init(); 182 toshiba_rbtx4938_irq_ioc_init();
183 /* Onboard 10M Ether: High Active */ 183 /* Onboard 10M Ether: High Active */
184 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000040); 184 set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
185 185
186 wbflush(); 186 wbflush();
187} 187}
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
index f9ad482749e4..57f3c705d082 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
@@ -773,10 +773,6 @@ void __init tx4938_board_setup(void)
773 txboard_add_phys_region(base, size); 773 txboard_add_phys_region(base, size);
774 } 774 }
775 775
776 /* IRC */
777 /* disable interrupt control */
778 tx4938_ircptr->cer = 0;
779
780 /* TMR */ 776 /* TMR */
781 /* disable all timers */ 777 /* disable all timers */
782 for (i = 0; i < TX4938_NR_TMR; i++) { 778 for (i = 0; i < TX4938_NR_TMR; i++) {
@@ -875,9 +871,6 @@ void __init toshiba_rbtx4938_setup(void)
875 if (txx9_master_clock == 0) 871 if (txx9_master_clock == 0)
876 txx9_master_clock = 25000000; /* 25MHz */ 872 txx9_master_clock = 25000000; /* 25MHz */
877 tx4938_board_setup(); 873 tx4938_board_setup();
878 /* setup irq stuff */
879 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000000); /* irq trigger */
880 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM1), 0x00000000); /* irq trigger */
881 /* setup serial stuff */ 874 /* setup serial stuff */
882 TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */ 875 TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
883 TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */ 876 TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
@@ -897,7 +890,7 @@ void __init toshiba_rbtx4938_setup(void)
897 req.iotype = UPIO_MEM; 890 req.iotype = UPIO_MEM;
898 req.membase = (char *)(0xff1ff300 + i * 0x100); 891 req.membase = (char *)(0xff1ff300 + i * 0x100);
899 req.mapbase = 0xff1ff300 + i * 0x100; 892 req.mapbase = 0xff1ff300 + i * 0x100;
900 req.irq = 32 + i; 893 req.irq = RBTX4938_IRQ_IRC_SIO(i);
901 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; 894 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
902 req.uartclk = 50000000; 895 req.uartclk = 50000000;
903 early_serial_txx9_setup(&req); 896 early_serial_txx9_setup(&req);
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
index 958e29706e2d..b2dc35f56181 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/jmr3927/jmr3927.h
@@ -13,6 +13,7 @@
13#include <asm/jmr3927/tx3927.h> 13#include <asm/jmr3927/tx3927.h>
14#include <asm/addrspace.h> 14#include <asm/addrspace.h>
15#include <asm/system.h> 15#include <asm/system.h>
16#include <asm/txx9irq.h>
16 17
17/* CS */ 18/* CS */
18#define JMR3927_ROMCE0 0x1fc00000 /* 4M */ 19#define JMR3927_ROMCE0 0x1fc00000 /* 4M */
@@ -115,7 +116,7 @@
115#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ 116#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */
116#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ 117#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */
117 118
118#define JMR3927_IRQ_IRC 16 119#define JMR3927_IRQ_IRC TXX9_IRQ_BASE
119#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) 120#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
120#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) 121#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
121 122
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h
index 0b9073bfb759..4be2f25f70dd 100644
--- a/include/asm-mips/jmr3927/tx3927.h
+++ b/include/asm-mips/jmr3927/tx3927.h
@@ -50,21 +50,6 @@ struct tx3927_dma_reg {
50 volatile unsigned long unused0; 50 volatile unsigned long unused0;
51}; 51};
52 52
53struct tx3927_irc_reg {
54 volatile unsigned long cer;
55 volatile unsigned long cr[2];
56 volatile unsigned long unused0;
57 volatile unsigned long ilr[8];
58 volatile unsigned long unused1[4];
59 volatile unsigned long imr;
60 volatile unsigned long unused2[7];
61 volatile unsigned long scr;
62 volatile unsigned long unused3[7];
63 volatile unsigned long ssr;
64 volatile unsigned long unused4[7];
65 volatile unsigned long csr;
66};
67
68#include <asm/byteorder.h> 53#include <asm/byteorder.h>
69 54
70#ifdef __BIG_ENDIAN 55#ifdef __BIG_ENDIAN
@@ -225,26 +210,6 @@ struct tx3927_ccfg_reg {
225/* 210/*
226 * IRC 211 * IRC
227 */ 212 */
228#define TX3927_IR_MAX_LEVEL 7
229
230/* IRCER : Int. Control Enable */
231#define TX3927_IRCER_ICE 0x00000001
232
233/* IRCR : Int. Control */
234#define TX3927_IRCR_LOW 0x00000000
235#define TX3927_IRCR_HIGH 0x00000001
236#define TX3927_IRCR_DOWN 0x00000002
237#define TX3927_IRCR_UP 0x00000003
238
239/* IRSCR : Int. Status Control */
240#define TX3927_IRSCR_EIClrE 0x00000100
241#define TX3927_IRSCR_EIClr_MASK 0x0000000f
242
243/* IRCSR : Int. Current Status */
244#define TX3927_IRCSR_IF 0x00010000
245#define TX3927_IRCSR_ILV_MASK 0x00000700
246#define TX3927_IRCSR_IVL_MASK 0x0000001f
247
248#define TX3927_IR_INT0 0 213#define TX3927_IR_INT0 0
249#define TX3927_IR_INT1 1 214#define TX3927_IR_INT1 1
250#define TX3927_IR_INT2 2 215#define TX3927_IR_INT2 2
@@ -347,7 +312,6 @@ struct tx3927_ccfg_reg {
347#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG) 312#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
348#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG) 313#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
349#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) 314#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
350#define tx3927_ircptr ((struct tx3927_irc_reg *)TX3927_IRC_REG)
351#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) 315#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
352#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) 316#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
353#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch)) 317#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h
index 5dc40a867774..a60649569c2c 100644
--- a/include/asm-mips/tx4927/toshiba_rbtx4927.h
+++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h
@@ -50,7 +50,7 @@
50 50
51 51
52#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) 52#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
53#define RBTX4927_RTL_8019_IRQ (29) 53#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5)
54 54
55int toshiba_rbtx4927_irq_nested(int sw_irq); 55int toshiba_rbtx4927_irq_nested(int sw_irq);
56 56
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
index de85bd2245f7..4bd4368e188c 100644
--- a/include/asm-mips/tx4927/tx4927.h
+++ b/include/asm-mips/tx4927/tx4927.h
@@ -28,6 +28,7 @@
28#define __ASM_TX4927_TX4927_H 28#define __ASM_TX4927_TX4927_H
29 29
30#include <asm/tx4927/tx4927_mips.h> 30#include <asm/tx4927/tx4927_mips.h>
31#include <asm/txx9irq.h>
31 32
32/* 33/*
33 This register naming came from the integrated CPU/controller name TX4927 34 This register naming came from the integrated CPU/controller name TX4927
@@ -421,32 +422,6 @@
421#define TX4927_PIO_LIMIT 0xf50f 422#define TX4927_PIO_LIMIT 0xf50f
422 423
423 424
424/* TX4927 Interrupt Controller (32-bit registers) */
425#define TX4927_IRC_BASE 0xf510
426#define TX4927_IRC_IRFLAG0 0xf510
427#define TX4927_IRC_IRFLAG1 0xf514
428#define TX4927_IRC_IRPOL 0xf518
429#define TX4927_IRC_IRRCNT 0xf51c
430#define TX4927_IRC_IRMASKINT 0xf520
431#define TX4927_IRC_IRMASKEXT 0xf524
432#define TX4927_IRC_IRDEN 0xf600
433#define TX4927_IRC_IRDM0 0xf604
434#define TX4927_IRC_IRDM1 0xf608
435#define TX4927_IRC_IRLVL0 0xf610
436#define TX4927_IRC_IRLVL1 0xf614
437#define TX4927_IRC_IRLVL2 0xf618
438#define TX4927_IRC_IRLVL3 0xf61c
439#define TX4927_IRC_IRLVL4 0xf620
440#define TX4927_IRC_IRLVL5 0xf624
441#define TX4927_IRC_IRLVL6 0xf628
442#define TX4927_IRC_IRLVL7 0xf62c
443#define TX4927_IRC_IRMSK 0xf640
444#define TX4927_IRC_IREDC 0xf660
445#define TX4927_IRC_IRPND 0xf680
446#define TX4927_IRC_IRCS 0xf6a0
447#define TX4927_IRC_LIMIT 0xf6ff
448
449
450/* TX4927 AC-link controller (32-bit registers) */ 425/* TX4927 AC-link controller (32-bit registers) */
451#define TX4927_ACLC_BASE 0xf700 426#define TX4927_ACLC_BASE 0xf700
452#define TX4927_ACLC_ACCTLEN 0xf700 427#define TX4927_ACLC_ACCTLEN 0xf700
@@ -493,25 +468,11 @@
493#define TX4927_WR( reg, val ) TX4927_WR32( reg, val ) 468#define TX4927_WR( reg, val ) TX4927_WR32( reg, val )
494 469
495 470
471#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
472#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
496 473
497 474#define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE
498 475#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
499#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */
500#define MI8259_IRQ_ISA_RAW_END 15
501#define TX4927_IRQ_CP0_RAW_BEG 0 /* tx4927 cpu built-in cp0 */
502#define TX4927_IRQ_CP0_RAW_END 7
503#define TX4927_IRQ_PIC_RAW_BEG 0 /* tx4927 cpu build-in pic */
504#define TX4927_IRQ_PIC_RAW_END 31
505
506
507#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */
508#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */
509
510#define TX4927_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_BEG) /* 16 */
511#define TX4927_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_END) /* 23 */
512
513#define TX4927_IRQ_PIC_BEG ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_BEG) /* 24 */
514#define TX4927_IRQ_PIC_END ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_END) /* 55 */
515 476
516 477
517#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) 478#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0)
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
index 66c064690f41..f98b2bb719d5 100644
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ b/include/asm-mips/tx4927/tx4927_pci.h
@@ -48,7 +48,7 @@
48#define TX4927_PCI_CLK_ACK 0x04 48#define TX4927_PCI_CLK_ACK 0x04
49#define TX4927_PCI_CLK_ACE 0x02 49#define TX4927_PCI_CLK_ACE 0x02
50#define TX4927_PCI_CLK_ENDIAN 0x01 50#define TX4927_PCI_CLK_ENDIAN 0x01
51#define TX4927_NR_IRQ_LOCAL (8+16) 51#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG
52#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ 52#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */
53 53
54#define TX4927_IR_PCIC 16 54#define TX4927_IR_PCIC 16
@@ -99,21 +99,6 @@ struct tx4927_ccfg_reg {
99 volatile unsigned long long ramp; 99 volatile unsigned long long ramp;
100}; 100};
101 101
102struct tx4927_irc_reg {
103 volatile unsigned long cer;
104 volatile unsigned long cr[2];
105 volatile unsigned long unused0;
106 volatile unsigned long ilr[8];
107 volatile unsigned long unused1[4];
108 volatile unsigned long imr;
109 volatile unsigned long unused2[7];
110 volatile unsigned long scr;
111 volatile unsigned long unused3[7];
112 volatile unsigned long ssr;
113 volatile unsigned long unused4[7];
114 volatile unsigned long csr;
115};
116
117struct tx4927_pcic_reg { 102struct tx4927_pcic_reg {
118 volatile unsigned long pciid; 103 volatile unsigned long pciid;
119 volatile unsigned long pcistatus; 104 volatile unsigned long pcistatus;
@@ -182,11 +167,6 @@ struct tx4927_pcic_reg {
182 167
183#endif /* _LANGUAGE_ASSEMBLY */ 168#endif /* _LANGUAGE_ASSEMBLY */
184 169
185/* IRCSR : Int. Current Status */
186#define TX4927_IRCSR_IF 0x00010000
187#define TX4927_IRCSR_ILV_MASK 0x00000700
188#define TX4927_IRCSR_IVL_MASK 0x0000001f
189
190/* 170/*
191 * PCIC 171 * PCIC
192 */ 172 */
@@ -278,7 +258,6 @@ struct tx4927_pcic_reg {
278#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) 258#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
279#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) 259#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
280#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) 260#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
281#define tx4927_ircptr ((struct tx4927_irc_reg *)TX4927_IRC_REG)
282 261
283#endif /* _LANGUAGE_ASSEMBLY */ 262#endif /* _LANGUAGE_ASSEMBLY */
284 263
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h
index 74e7d8061e58..b14acb575be2 100644
--- a/include/asm-mips/tx4938/rbtx4938.h
+++ b/include/asm-mips/tx4938/rbtx4938.h
@@ -14,6 +14,7 @@
14 14
15#include <asm/addrspace.h> 15#include <asm/addrspace.h>
16#include <asm/tx4938/tx4938.h> 16#include <asm/tx4938/tx4938.h>
17#include <asm/txx9irq.h>
17 18
18/* CS */ 19/* CS */
19#define RBTX4938_CE0 0x1c000000 /* 64M */ 20#define RBTX4938_CE0 0x1c000000 /* 64M */
@@ -123,21 +124,11 @@
123#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */ 124#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */
124#define RBTX4938_NR_IRQ_IOC 8 125#define RBTX4938_NR_IRQ_IOC 8
125 126
126#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */ 127#define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
127#define MI8259_IRQ_ISA_RAW_END 15 128#define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
128#define TX4938_IRQ_CP0_RAW_BEG 0 /* tx4938 cpu built-in cp0 */
129#define TX4938_IRQ_CP0_RAW_END 7
130#define TX4938_IRQ_PIC_RAW_BEG 0 /* tx4938 cpu build-in pic */
131#define TX4938_IRQ_PIC_RAW_END 31
132 129
133#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */ 130#define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE
134#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */ 131#define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
135
136#define TX4938_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_BEG) /* 16 */
137#define TX4938_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_END) /* 23 */
138
139#define TX4938_IRQ_PIC_BEG ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_BEG) /* 24 */
140#define TX4938_IRQ_PIC_END ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_END) /* 55 */
141#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2) 132#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2)
142#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2) 133#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2)
143#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0) 134#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0)
@@ -192,10 +183,4 @@
192#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) 183#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
193#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) 184#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER)
194 185
195/* IRCR : Int. Control */
196#define TX4938_IRCR_LOW 0x00000000
197#define TX4938_IRCR_HIGH 0x00000001
198#define TX4938_IRCR_DOWN 0x00000002
199#define TX4938_IRCR_UP 0x00000003
200
201#endif /* __ASM_TX_BOARDS_RBTX4938_H */ 186#endif /* __ASM_TX_BOARDS_RBTX4938_H */
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h
index e25b1a0975cb..afdb19813ca1 100644
--- a/include/asm-mips/tx4938/tx4938.h
+++ b/include/asm-mips/tx4938/tx4938.h
@@ -272,20 +272,6 @@ struct tx4938_pio_reg {
272 volatile unsigned long maskcpu; 272 volatile unsigned long maskcpu;
273 volatile unsigned long maskext; 273 volatile unsigned long maskext;
274}; 274};
275struct tx4938_irc_reg {
276 volatile unsigned long cer;
277 volatile unsigned long cr[2];
278 volatile unsigned long unused0;
279 volatile unsigned long ilr[8];
280 volatile unsigned long unused1[4];
281 volatile unsigned long imr;
282 volatile unsigned long unused2[7];
283 volatile unsigned long scr;
284 volatile unsigned long unused3[7];
285 volatile unsigned long ssr;
286 volatile unsigned long unused4[7];
287 volatile unsigned long csr;
288};
289 275
290struct tx4938_ndfmc_reg { 276struct tx4938_ndfmc_reg {
291 endian_def_l2(unused0, dtr); 277 endian_def_l2(unused0, dtr);
@@ -646,39 +632,12 @@ struct tx4938_ccfg_reg {
646#define TX4938_DMA_CSR_DESERR 0x00000002 632#define TX4938_DMA_CSR_DESERR 0x00000002
647#define TX4938_DMA_CSR_SORERR 0x00000001 633#define TX4938_DMA_CSR_SORERR 0x00000001
648 634
649/* TX4938 Interrupt Controller (32-bit registers) */
650#define TX4938_IRC_BASE 0xf510
651#define TX4938_IRC_IRFLAG0 0xf510
652#define TX4938_IRC_IRFLAG1 0xf514
653#define TX4938_IRC_IRPOL 0xf518
654#define TX4938_IRC_IRRCNT 0xf51c
655#define TX4938_IRC_IRMASKINT 0xf520
656#define TX4938_IRC_IRMASKEXT 0xf524
657#define TX4938_IRC_IRDEN 0xf600
658#define TX4938_IRC_IRDM0 0xf604
659#define TX4938_IRC_IRDM1 0xf608
660#define TX4938_IRC_IRLVL0 0xf610
661#define TX4938_IRC_IRLVL1 0xf614
662#define TX4938_IRC_IRLVL2 0xf618
663#define TX4938_IRC_IRLVL3 0xf61c
664#define TX4938_IRC_IRLVL4 0xf620
665#define TX4938_IRC_IRLVL5 0xf624
666#define TX4938_IRC_IRLVL6 0xf628
667#define TX4938_IRC_IRLVL7 0xf62c
668#define TX4938_IRC_IRMSK 0xf640
669#define TX4938_IRC_IREDC 0xf660
670#define TX4938_IRC_IRPND 0xf680
671#define TX4938_IRC_IRCS 0xf6a0
672#define TX4938_IRC_LIMIT 0xf6ff
673
674
675#ifndef __ASSEMBLY__ 635#ifndef __ASSEMBLY__
676 636
677#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) 637#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
678#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) 638#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
679#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) 639#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
680#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) 640#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
681#define tx4938_ircptr ((struct tx4938_irc_reg *)TX4938_IRC_REG)
682#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) 641#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
683#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) 642#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
684#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) 643#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 06:29:28 -0500