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-rw-r--r--drivers/net/cxgb3/t3_hw.c13
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c
index e78d341cbd60..526e144b8b74 100644
--- a/drivers/net/cxgb3/t3_hw.c
+++ b/drivers/net/cxgb3/t3_hw.c
@@ -3465,7 +3465,7 @@ static void config_pcie(struct adapter *adap)
3465 {201, 321, 258, 450, 834, 1602} 3465 {201, 321, 258, 450, 834, 1602}
3466 }; 3466 };
3467 3467
3468 u16 val; 3468 u16 val, devid;
3469 unsigned int log2_width, pldsize; 3469 unsigned int log2_width, pldsize;
3470 unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt; 3470 unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt;
3471 3471
@@ -3473,6 +3473,17 @@ static void config_pcie(struct adapter *adap)
3473 adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL, 3473 adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL,
3474 &val); 3474 &val);
3475 pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5; 3475 pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
3476
3477 pci_read_config_word(adap->pdev, 0x2, &devid);
3478 if (devid == 0x37) {
3479 pci_write_config_word(adap->pdev,
3480 adap->params.pci.pcie_cap_addr +
3481 PCI_EXP_DEVCTL,
3482 val & ~PCI_EXP_DEVCTL_READRQ &
3483 ~PCI_EXP_DEVCTL_PAYLOAD);
3484 pldsize = 0;
3485 }
3486
3476 pci_read_config_word(adap->pdev, 3487 pci_read_config_word(adap->pdev,
3477 adap->params.pci.pcie_cap_addr + PCI_EXP_LNKCTL, 3488 adap->params.pci.pcie_cap_addr + PCI_EXP_LNKCTL,
3478 &val); 3489 &val);