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-rw-r--r--drivers/gpu/drm/radeon/r600.c24
-rw-r--r--drivers/gpu/drm/radeon/r600d.h1
-rw-r--r--drivers/gpu/drm/radeon/rv770.c5
-rw-r--r--drivers/gpu/drm/radeon/rv770d.h1
4 files changed, 28 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index e1e59e1b318d..28e39bc6768b 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -884,7 +884,17 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
884 u32 tmp; 884 u32 tmp;
885 885
886 /* flush hdp cache so updates hit vram */ 886 /* flush hdp cache so updates hit vram */
887 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 887 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
888 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
889 u32 tmp;
890
891 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
892 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
893 */
894 WREG32(HDP_DEBUG1, 0);
895 tmp = readl((void __iomem *)ptr);
896 } else
897 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
888 898
889 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 899 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
890 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 900 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
@@ -3527,5 +3537,15 @@ int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3527 */ 3537 */
3528void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) 3538void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3529{ 3539{
3530 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 3540 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
3541 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
3542 */
3543 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
3544 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
3545 u32 tmp;
3546
3547 WREG32(HDP_DEBUG1, 0);
3548 tmp = readl((void __iomem *)ptr);
3549 } else
3550 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3531} 3551}
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index b7318ac4f84a..858a1920c0d7 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -250,6 +250,7 @@
250#define HDP_NONSURFACE_SIZE 0x2C0C 250#define HDP_NONSURFACE_SIZE 0x2C0C
251#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 251#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
252#define HDP_TILING_CONFIG 0x2F3C 252#define HDP_TILING_CONFIG 0x2F3C
253#define HDP_DEBUG1 0x2F34
253 254
254#define MC_VM_AGP_TOP 0x2184 255#define MC_VM_AGP_TOP 0x2184
255#define MC_VM_AGP_BOT 0x2188 256#define MC_VM_AGP_BOT 0x2188
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 236fe6681922..f1c796810117 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -204,7 +204,10 @@ static void rv770_mc_program(struct radeon_device *rdev)
204 WREG32((0x2c20 + j), 0x00000000); 204 WREG32((0x2c20 + j), 0x00000000);
205 WREG32((0x2c24 + j), 0x00000000); 205 WREG32((0x2c24 + j), 0x00000000);
206 } 206 }
207 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 207 /* r7xx hw bug. Read from HDP_DEBUG1 rather
208 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
209 */
210 tmp = RREG32(HDP_DEBUG1);
208 211
209 rv515_mc_stop(rdev, &save); 212 rv515_mc_stop(rdev, &save);
210 if (r600_mc_wait_for_idle(rdev)) { 213 if (r600_mc_wait_for_idle(rdev)) {
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index fd733f268e3d..b7a5a20e81dc 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -133,6 +133,7 @@
133#define HDP_NONSURFACE_SIZE 0x2C0C 133#define HDP_NONSURFACE_SIZE 0x2C0C
134#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 134#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
135#define HDP_TILING_CONFIG 0x2F3C 135#define HDP_TILING_CONFIG 0x2F3C
136#define HDP_DEBUG1 0x2F34
136 137
137#define MC_SHARED_CHMAP 0x2004 138#define MC_SHARED_CHMAP 0x2004
138#define NOOFCHAN_SHIFT 12 139#define NOOFCHAN_SHIFT 12