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-rw-r--r--include/sound/wm5100.h59
-rw-r--r--sound/soc/codecs/Kconfig4
-rw-r--r--sound/soc/codecs/Makefile2
-rw-r--r--sound/soc/codecs/wm5100-tables.c1530
-rw-r--r--sound/soc/codecs/wm5100.c2560
-rw-r--r--sound/soc/codecs/wm5100.h5146
6 files changed, 9301 insertions, 0 deletions
diff --git a/include/sound/wm5100.h b/include/sound/wm5100.h
new file mode 100644
index 000000000000..617d0c4a159f
--- /dev/null
+++ b/include/sound/wm5100.h
@@ -0,0 +1,59 @@
1/*
2 * linux/sound/wm5100.h -- Platform data for WM5100
3 *
4 * Copyright 2011 Wolfson Microelectronics. PLC.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __LINUX_SND_WM5100_H
12#define __LINUX_SND_WM5100_H
13
14enum wm5100_in_mode {
15 WM5100_IN_SE = 0,
16 WM5100_IN_DIFF = 1,
17 WM5100_IN_DMIC = 2,
18};
19
20enum wm5100_dmic_sup {
21 WM5100_DMIC_SUP_MICVDD = 0,
22 WM5100_DMIC_SUP_MICBIAS1 = 1,
23 WM5100_DMIC_SUP_MICBIAS2 = 2,
24 WM5100_DMIC_SUP_MICBIAS3 = 3,
25};
26
27enum wm5100_micdet_bias {
28 WM5100_MICDET_MICBIAS1 = 0,
29 WM5100_MICDET_MICBIAS2 = 1,
30 WM5100_MICDET_MICBIAS3 = 2,
31};
32
33struct wm5100_jack_mode {
34 enum wm5100_micdet_bias bias;
35 int hp_pol;
36 int micd_src;
37};
38
39#define WM5100_GPIO_SET 0x10000
40
41struct wm5100_pdata {
42 int reset; /** GPIO controlling /RESET, if any */
43 int ldo_ena; /** GPIO controlling LODENA, if any */
44 int hp_pol; /** GPIO controlling headset polarity, if any */
45 int irq_flags;
46 int gpio_base;
47
48 struct wm5100_jack_mode jack_modes[2];
49
50 /* Input pin mode selection */
51 enum wm5100_in_mode in_mode[4];
52
53 /* DMIC supply selection */
54 enum wm5100_dmic_sup dmic_sup[4];
55
56 int gpio_defaults[6];
57};
58
59#endif
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 71b46c8f70d7..45c966c24a15 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -59,6 +59,7 @@ config SND_SOC_ALL_CODECS
59 select SND_SOC_WL1273 if MFD_WL1273_CORE 59 select SND_SOC_WL1273 if MFD_WL1273_CORE
60 select SND_SOC_WM1250_EV1 if I2C 60 select SND_SOC_WM1250_EV1 if I2C
61 select SND_SOC_WM2000 if I2C 61 select SND_SOC_WM2000 if I2C
62 select SND_SOC_WM5100 if I2C
62 select SND_SOC_WM8350 if MFD_WM8350 63 select SND_SOC_WM8350 if MFD_WM8350
63 select SND_SOC_WM8400 if MFD_WM8400 64 select SND_SOC_WM8400 if MFD_WM8400
64 select SND_SOC_WM8510 if SND_SOC_I2C_AND_SPI 65 select SND_SOC_WM8510 if SND_SOC_I2C_AND_SPI
@@ -273,6 +274,9 @@ config SND_SOC_WL1273
273config SND_SOC_WM1250_EV1 274config SND_SOC_WM1250_EV1
274 tristate 275 tristate
275 276
277config SND_SOC_WM5100
278 tristate
279
276config SND_SOC_WM8350 280config SND_SOC_WM8350
277 tristate 281 tristate
278 282
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 70c1769acd15..4f3ff24faa1f 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -44,6 +44,7 @@ snd-soc-uda134x-objs := uda134x.o
44snd-soc-uda1380-objs := uda1380.o 44snd-soc-uda1380-objs := uda1380.o
45snd-soc-wl1273-objs := wl1273.o 45snd-soc-wl1273-objs := wl1273.o
46snd-soc-wm1250-ev1-objs := wm1250-ev1.o 46snd-soc-wm1250-ev1-objs := wm1250-ev1.o
47snd-soc-wm5100-objs := wm5100.o wm5100-tables.o
47snd-soc-wm8350-objs := wm8350.o 48snd-soc-wm8350-objs := wm8350.o
48snd-soc-wm8400-objs := wm8400.o 49snd-soc-wm8400-objs := wm8400.o
49snd-soc-wm8510-objs := wm8510.o 50snd-soc-wm8510-objs := wm8510.o
@@ -142,6 +143,7 @@ obj-$(CONFIG_SND_SOC_UDA134X) += snd-soc-uda134x.o
142obj-$(CONFIG_SND_SOC_UDA1380) += snd-soc-uda1380.o 143obj-$(CONFIG_SND_SOC_UDA1380) += snd-soc-uda1380.o
143obj-$(CONFIG_SND_SOC_WL1273) += snd-soc-wl1273.o 144obj-$(CONFIG_SND_SOC_WL1273) += snd-soc-wl1273.o
144obj-$(CONFIG_SND_SOC_WM1250_EV1) += snd-soc-wm1250-ev1.o 145obj-$(CONFIG_SND_SOC_WM1250_EV1) += snd-soc-wm1250-ev1.o
146obj-$(CONFIG_SND_SOC_WM5100) += snd-soc-wm5100.o
145obj-$(CONFIG_SND_SOC_WM8350) += snd-soc-wm8350.o 147obj-$(CONFIG_SND_SOC_WM8350) += snd-soc-wm8350.o
146obj-$(CONFIG_SND_SOC_WM8400) += snd-soc-wm8400.o 148obj-$(CONFIG_SND_SOC_WM8400) += snd-soc-wm8400.o
147obj-$(CONFIG_SND_SOC_WM8510) += snd-soc-wm8510.o 149obj-$(CONFIG_SND_SOC_WM8510) += snd-soc-wm8510.o
diff --git a/sound/soc/codecs/wm5100-tables.c b/sound/soc/codecs/wm5100-tables.c
new file mode 100644
index 000000000000..960617bf72e3
--- /dev/null
+++ b/sound/soc/codecs/wm5100-tables.c
@@ -0,0 +1,1530 @@
1/*
2 * wm5100-tables.c -- WM5100 ALSA SoC Audio driver data
3 *
4 * Copyright 2011 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include "wm5100.h"
15
16int wm5100_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
17{
18 switch (reg) {
19 case WM5100_SOFTWARE_RESET:
20 case WM5100_DEVICE_REVISION:
21 case WM5100_FX_CTRL:
22 case WM5100_INTERRUPT_STATUS_1:
23 case WM5100_INTERRUPT_STATUS_2:
24 case WM5100_INTERRUPT_STATUS_3:
25 case WM5100_INTERRUPT_STATUS_4:
26 case WM5100_INTERRUPT_RAW_STATUS_2:
27 case WM5100_INTERRUPT_RAW_STATUS_3:
28 case WM5100_INTERRUPT_RAW_STATUS_4:
29 case WM5100_OUTPUT_STATUS_1:
30 case WM5100_OUTPUT_STATUS_2:
31 case WM5100_INPUT_ENABLES_STATUS:
32 case WM5100_MIC_DETECT_3:
33 return 1;
34 default:
35 return 0;
36 }
37}
38
39int wm5100_readable_register(struct snd_soc_codec *codec, unsigned int reg)
40{
41 switch (reg) {
42 case WM5100_SOFTWARE_RESET:
43 case WM5100_DEVICE_REVISION:
44 case WM5100_CTRL_IF_1:
45 case WM5100_TONE_GENERATOR_1:
46 case WM5100_PWM_DRIVE_1:
47 case WM5100_PWM_DRIVE_2:
48 case WM5100_PWM_DRIVE_3:
49 case WM5100_CLOCKING_1:
50 case WM5100_CLOCKING_3:
51 case WM5100_CLOCKING_4:
52 case WM5100_CLOCKING_5:
53 case WM5100_CLOCKING_6:
54 case WM5100_CLOCKING_7:
55 case WM5100_CLOCKING_8:
56 case WM5100_ASRC_ENABLE:
57 case WM5100_ASRC_STATUS:
58 case WM5100_ASRC_RATE1:
59 case WM5100_ISRC_1_CTRL_1:
60 case WM5100_ISRC_1_CTRL_2:
61 case WM5100_ISRC_2_CTRL1:
62 case WM5100_ISRC_2_CTRL_2:
63 case WM5100_FLL1_CONTROL_1:
64 case WM5100_FLL1_CONTROL_2:
65 case WM5100_FLL1_CONTROL_3:
66 case WM5100_FLL1_CONTROL_5:
67 case WM5100_FLL1_CONTROL_6:
68 case WM5100_FLL1_EFS_1:
69 case WM5100_FLL2_CONTROL_1:
70 case WM5100_FLL2_CONTROL_2:
71 case WM5100_FLL2_CONTROL_3:
72 case WM5100_FLL2_CONTROL_5:
73 case WM5100_FLL2_CONTROL_6:
74 case WM5100_FLL2_EFS_1:
75 case WM5100_MIC_CHARGE_PUMP_1:
76 case WM5100_MIC_CHARGE_PUMP_2:
77 case WM5100_HP_CHARGE_PUMP_1:
78 case WM5100_LDO1_CONTROL:
79 case WM5100_MIC_BIAS_CTRL_1:
80 case WM5100_MIC_BIAS_CTRL_2:
81 case WM5100_MIC_BIAS_CTRL_3:
82 case WM5100_ACCESSORY_DETECT_MODE_1:
83 case WM5100_HEADPHONE_DETECT_1:
84 case WM5100_HEADPHONE_DETECT_2:
85 case WM5100_MIC_DETECT_1:
86 case WM5100_MIC_DETECT_2:
87 case WM5100_MIC_DETECT_3:
88 case WM5100_INPUT_ENABLES:
89 case WM5100_INPUT_ENABLES_STATUS:
90 case WM5100_IN1L_CONTROL:
91 case WM5100_IN1R_CONTROL:
92 case WM5100_IN2L_CONTROL:
93 case WM5100_IN2R_CONTROL:
94 case WM5100_IN3L_CONTROL:
95 case WM5100_IN3R_CONTROL:
96 case WM5100_IN4L_CONTROL:
97 case WM5100_IN4R_CONTROL:
98 case WM5100_RXANC_SRC:
99 case WM5100_INPUT_VOLUME_RAMP:
100 case WM5100_ADC_DIGITAL_VOLUME_1L:
101 case WM5100_ADC_DIGITAL_VOLUME_1R:
102 case WM5100_ADC_DIGITAL_VOLUME_2L:
103 case WM5100_ADC_DIGITAL_VOLUME_2R:
104 case WM5100_ADC_DIGITAL_VOLUME_3L:
105 case WM5100_ADC_DIGITAL_VOLUME_3R:
106 case WM5100_ADC_DIGITAL_VOLUME_4L:
107 case WM5100_ADC_DIGITAL_VOLUME_4R:
108 case WM5100_OUTPUT_ENABLES_2:
109 case WM5100_OUTPUT_STATUS_1:
110 case WM5100_OUTPUT_STATUS_2:
111 case WM5100_CHANNEL_ENABLES_1:
112 case WM5100_OUT_VOLUME_1L:
113 case WM5100_OUT_VOLUME_1R:
114 case WM5100_DAC_VOLUME_LIMIT_1L:
115 case WM5100_DAC_VOLUME_LIMIT_1R:
116 case WM5100_OUT_VOLUME_2L:
117 case WM5100_OUT_VOLUME_2R:
118 case WM5100_DAC_VOLUME_LIMIT_2L:
119 case WM5100_DAC_VOLUME_LIMIT_2R:
120 case WM5100_OUT_VOLUME_3L:
121 case WM5100_OUT_VOLUME_3R:
122 case WM5100_DAC_VOLUME_LIMIT_3L:
123 case WM5100_DAC_VOLUME_LIMIT_3R:
124 case WM5100_OUT_VOLUME_4L:
125 case WM5100_OUT_VOLUME_4R:
126 case WM5100_DAC_VOLUME_LIMIT_5L:
127 case WM5100_DAC_VOLUME_LIMIT_5R:
128 case WM5100_DAC_VOLUME_LIMIT_6L:
129 case WM5100_DAC_VOLUME_LIMIT_6R:
130 case WM5100_DAC_AEC_CONTROL_1:
131 case WM5100_OUTPUT_VOLUME_RAMP:
132 case WM5100_DAC_DIGITAL_VOLUME_1L:
133 case WM5100_DAC_DIGITAL_VOLUME_1R:
134 case WM5100_DAC_DIGITAL_VOLUME_2L:
135 case WM5100_DAC_DIGITAL_VOLUME_2R:
136 case WM5100_DAC_DIGITAL_VOLUME_3L:
137 case WM5100_DAC_DIGITAL_VOLUME_3R:
138 case WM5100_DAC_DIGITAL_VOLUME_4L:
139 case WM5100_DAC_DIGITAL_VOLUME_4R:
140 case WM5100_DAC_DIGITAL_VOLUME_5L:
141 case WM5100_DAC_DIGITAL_VOLUME_5R:
142 case WM5100_DAC_DIGITAL_VOLUME_6L:
143 case WM5100_DAC_DIGITAL_VOLUME_6R:
144 case WM5100_PDM_SPK1_CTRL_1:
145 case WM5100_PDM_SPK1_CTRL_2:
146 case WM5100_PDM_SPK2_CTRL_1:
147 case WM5100_PDM_SPK2_CTRL_2:
148 case WM5100_AUDIO_IF_1_1:
149 case WM5100_AUDIO_IF_1_2:
150 case WM5100_AUDIO_IF_1_3:
151 case WM5100_AUDIO_IF_1_4:
152 case WM5100_AUDIO_IF_1_5:
153 case WM5100_AUDIO_IF_1_6:
154 case WM5100_AUDIO_IF_1_7:
155 case WM5100_AUDIO_IF_1_8:
156 case WM5100_AUDIO_IF_1_9:
157 case WM5100_AUDIO_IF_1_10:
158 case WM5100_AUDIO_IF_1_11:
159 case WM5100_AUDIO_IF_1_12:
160 case WM5100_AUDIO_IF_1_13:
161 case WM5100_AUDIO_IF_1_14:
162 case WM5100_AUDIO_IF_1_15:
163 case WM5100_AUDIO_IF_1_16:
164 case WM5100_AUDIO_IF_1_17:
165 case WM5100_AUDIO_IF_1_18:
166 case WM5100_AUDIO_IF_1_19:
167 case WM5100_AUDIO_IF_1_20:
168 case WM5100_AUDIO_IF_1_21:
169 case WM5100_AUDIO_IF_1_22:
170 case WM5100_AUDIO_IF_1_23:
171 case WM5100_AUDIO_IF_1_24:
172 case WM5100_AUDIO_IF_1_25:
173 case WM5100_AUDIO_IF_1_26:
174 case WM5100_AUDIO_IF_1_27:
175 case WM5100_AUDIO_IF_2_1:
176 case WM5100_AUDIO_IF_2_2:
177 case WM5100_AUDIO_IF_2_3:
178 case WM5100_AUDIO_IF_2_4:
179 case WM5100_AUDIO_IF_2_5:
180 case WM5100_AUDIO_IF_2_6:
181 case WM5100_AUDIO_IF_2_7:
182 case WM5100_AUDIO_IF_2_8:
183 case WM5100_AUDIO_IF_2_9:
184 case WM5100_AUDIO_IF_2_10:
185 case WM5100_AUDIO_IF_2_11:
186 case WM5100_AUDIO_IF_2_18:
187 case WM5100_AUDIO_IF_2_19:
188 case WM5100_AUDIO_IF_2_26:
189 case WM5100_AUDIO_IF_2_27:
190 case WM5100_AUDIO_IF_3_1:
191 case WM5100_AUDIO_IF_3_2:
192 case WM5100_AUDIO_IF_3_3:
193 case WM5100_AUDIO_IF_3_4:
194 case WM5100_AUDIO_IF_3_5:
195 case WM5100_AUDIO_IF_3_6:
196 case WM5100_AUDIO_IF_3_7:
197 case WM5100_AUDIO_IF_3_8:
198 case WM5100_AUDIO_IF_3_9:
199 case WM5100_AUDIO_IF_3_10:
200 case WM5100_AUDIO_IF_3_11:
201 case WM5100_AUDIO_IF_3_18:
202 case WM5100_AUDIO_IF_3_19:
203 case WM5100_AUDIO_IF_3_26:
204 case WM5100_AUDIO_IF_3_27:
205 case WM5100_PWM1MIX_INPUT_1_SOURCE:
206 case WM5100_PWM1MIX_INPUT_1_VOLUME:
207 case WM5100_PWM1MIX_INPUT_2_SOURCE:
208 case WM5100_PWM1MIX_INPUT_2_VOLUME:
209 case WM5100_PWM1MIX_INPUT_3_SOURCE:
210 case WM5100_PWM1MIX_INPUT_3_VOLUME:
211 case WM5100_PWM1MIX_INPUT_4_SOURCE:
212 case WM5100_PWM1MIX_INPUT_4_VOLUME:
213 case WM5100_PWM2MIX_INPUT_1_SOURCE:
214 case WM5100_PWM2MIX_INPUT_1_VOLUME:
215 case WM5100_PWM2MIX_INPUT_2_SOURCE:
216 case WM5100_PWM2MIX_INPUT_2_VOLUME:
217 case WM5100_PWM2MIX_INPUT_3_SOURCE:
218 case WM5100_PWM2MIX_INPUT_3_VOLUME:
219 case WM5100_PWM2MIX_INPUT_4_SOURCE:
220 case WM5100_PWM2MIX_INPUT_4_VOLUME:
221 case WM5100_OUT1LMIX_INPUT_1_SOURCE:
222 case WM5100_OUT1LMIX_INPUT_1_VOLUME:
223 case WM5100_OUT1LMIX_INPUT_2_SOURCE:
224 case WM5100_OUT1LMIX_INPUT_2_VOLUME:
225 case WM5100_OUT1LMIX_INPUT_3_SOURCE:
226 case WM5100_OUT1LMIX_INPUT_3_VOLUME:
227 case WM5100_OUT1LMIX_INPUT_4_SOURCE:
228 case WM5100_OUT1LMIX_INPUT_4_VOLUME:
229 case WM5100_OUT1RMIX_INPUT_1_SOURCE:
230 case WM5100_OUT1RMIX_INPUT_1_VOLUME:
231 case WM5100_OUT1RMIX_INPUT_2_SOURCE:
232 case WM5100_OUT1RMIX_INPUT_2_VOLUME:
233 case WM5100_OUT1RMIX_INPUT_3_SOURCE:
234 case WM5100_OUT1RMIX_INPUT_3_VOLUME:
235 case WM5100_OUT1RMIX_INPUT_4_SOURCE:
236 case WM5100_OUT1RMIX_INPUT_4_VOLUME:
237 case WM5100_OUT2LMIX_INPUT_1_SOURCE:
238 case WM5100_OUT2LMIX_INPUT_1_VOLUME:
239 case WM5100_OUT2LMIX_INPUT_2_SOURCE:
240 case WM5100_OUT2LMIX_INPUT_2_VOLUME:
241 case WM5100_OUT2LMIX_INPUT_3_SOURCE:
242 case WM5100_OUT2LMIX_INPUT_3_VOLUME:
243 case WM5100_OUT2LMIX_INPUT_4_SOURCE:
244 case WM5100_OUT2LMIX_INPUT_4_VOLUME:
245 case WM5100_OUT2RMIX_INPUT_1_SOURCE:
246 case WM5100_OUT2RMIX_INPUT_1_VOLUME:
247 case WM5100_OUT2RMIX_INPUT_2_SOURCE:
248 case WM5100_OUT2RMIX_INPUT_2_VOLUME:
249 case WM5100_OUT2RMIX_INPUT_3_SOURCE:
250 case WM5100_OUT2RMIX_INPUT_3_VOLUME:
251 case WM5100_OUT2RMIX_INPUT_4_SOURCE:
252 case WM5100_OUT2RMIX_INPUT_4_VOLUME:
253 case WM5100_OUT3LMIX_INPUT_1_SOURCE:
254 case WM5100_OUT3LMIX_INPUT_1_VOLUME:
255 case WM5100_OUT3LMIX_INPUT_2_SOURCE:
256 case WM5100_OUT3LMIX_INPUT_2_VOLUME:
257 case WM5100_OUT3LMIX_INPUT_3_SOURCE:
258 case WM5100_OUT3LMIX_INPUT_3_VOLUME:
259 case WM5100_OUT3LMIX_INPUT_4_SOURCE:
260 case WM5100_OUT3LMIX_INPUT_4_VOLUME:
261 case WM5100_OUT3RMIX_INPUT_1_SOURCE:
262 case WM5100_OUT3RMIX_INPUT_1_VOLUME:
263 case WM5100_OUT3RMIX_INPUT_2_SOURCE:
264 case WM5100_OUT3RMIX_INPUT_2_VOLUME:
265 case WM5100_OUT3RMIX_INPUT_3_SOURCE:
266 case WM5100_OUT3RMIX_INPUT_3_VOLUME:
267 case WM5100_OUT3RMIX_INPUT_4_SOURCE:
268 case WM5100_OUT3RMIX_INPUT_4_VOLUME:
269 case WM5100_OUT4LMIX_INPUT_1_SOURCE:
270 case WM5100_OUT4LMIX_INPUT_1_VOLUME:
271 case WM5100_OUT4LMIX_INPUT_2_SOURCE:
272 case WM5100_OUT4LMIX_INPUT_2_VOLUME:
273 case WM5100_OUT4LMIX_INPUT_3_SOURCE:
274 case WM5100_OUT4LMIX_INPUT_3_VOLUME:
275 case WM5100_OUT4LMIX_INPUT_4_SOURCE:
276 case WM5100_OUT4LMIX_INPUT_4_VOLUME:
277 case WM5100_OUT4RMIX_INPUT_1_SOURCE:
278 case WM5100_OUT4RMIX_INPUT_1_VOLUME:
279 case WM5100_OUT4RMIX_INPUT_2_SOURCE:
280 case WM5100_OUT4RMIX_INPUT_2_VOLUME:
281 case WM5100_OUT4RMIX_INPUT_3_SOURCE:
282 case WM5100_OUT4RMIX_INPUT_3_VOLUME:
283 case WM5100_OUT4RMIX_INPUT_4_SOURCE:
284 case WM5100_OUT4RMIX_INPUT_4_VOLUME:
285 case WM5100_OUT5LMIX_INPUT_1_SOURCE:
286 case WM5100_OUT5LMIX_INPUT_1_VOLUME:
287 case WM5100_OUT5LMIX_INPUT_2_SOURCE:
288 case WM5100_OUT5LMIX_INPUT_2_VOLUME:
289 case WM5100_OUT5LMIX_INPUT_3_SOURCE:
290 case WM5100_OUT5LMIX_INPUT_3_VOLUME:
291 case WM5100_OUT5LMIX_INPUT_4_SOURCE:
292 case WM5100_OUT5LMIX_INPUT_4_VOLUME:
293 case WM5100_OUT5RMIX_INPUT_1_SOURCE:
294 case WM5100_OUT5RMIX_INPUT_1_VOLUME:
295 case WM5100_OUT5RMIX_INPUT_2_SOURCE:
296 case WM5100_OUT5RMIX_INPUT_2_VOLUME:
297 case WM5100_OUT5RMIX_INPUT_3_SOURCE:
298 case WM5100_OUT5RMIX_INPUT_3_VOLUME:
299 case WM5100_OUT5RMIX_INPUT_4_SOURCE:
300 case WM5100_OUT5RMIX_INPUT_4_VOLUME:
301 case WM5100_OUT6LMIX_INPUT_1_SOURCE:
302 case WM5100_OUT6LMIX_INPUT_1_VOLUME:
303 case WM5100_OUT6LMIX_INPUT_2_SOURCE:
304 case WM5100_OUT6LMIX_INPUT_2_VOLUME:
305 case WM5100_OUT6LMIX_INPUT_3_SOURCE:
306 case WM5100_OUT6LMIX_INPUT_3_VOLUME:
307 case WM5100_OUT6LMIX_INPUT_4_SOURCE:
308 case WM5100_OUT6LMIX_INPUT_4_VOLUME:
309 case WM5100_OUT6RMIX_INPUT_1_SOURCE:
310 case WM5100_OUT6RMIX_INPUT_1_VOLUME:
311 case WM5100_OUT6RMIX_INPUT_2_SOURCE:
312 case WM5100_OUT6RMIX_INPUT_2_VOLUME:
313 case WM5100_OUT6RMIX_INPUT_3_SOURCE:
314 case WM5100_OUT6RMIX_INPUT_3_VOLUME:
315 case WM5100_OUT6RMIX_INPUT_4_SOURCE:
316 case WM5100_OUT6RMIX_INPUT_4_VOLUME:
317 case WM5100_AIF1TX1MIX_INPUT_1_SOURCE:
318 case WM5100_AIF1TX1MIX_INPUT_1_VOLUME:
319 case WM5100_AIF1TX1MIX_INPUT_2_SOURCE:
320 case WM5100_AIF1TX1MIX_INPUT_2_VOLUME:
321 case WM5100_AIF1TX1MIX_INPUT_3_SOURCE:
322 case WM5100_AIF1TX1MIX_INPUT_3_VOLUME:
323 case WM5100_AIF1TX1MIX_INPUT_4_SOURCE:
324 case WM5100_AIF1TX1MIX_INPUT_4_VOLUME:
325 case WM5100_AIF1TX2MIX_INPUT_1_SOURCE:
326 case WM5100_AIF1TX2MIX_INPUT_1_VOLUME:
327 case WM5100_AIF1TX2MIX_INPUT_2_SOURCE:
328 case WM5100_AIF1TX2MIX_INPUT_2_VOLUME:
329 case WM5100_AIF1TX2MIX_INPUT_3_SOURCE:
330 case WM5100_AIF1TX2MIX_INPUT_3_VOLUME:
331 case WM5100_AIF1TX2MIX_INPUT_4_SOURCE:
332 case WM5100_AIF1TX2MIX_INPUT_4_VOLUME:
333 case WM5100_AIF1TX3MIX_INPUT_1_SOURCE:
334 case WM5100_AIF1TX3MIX_INPUT_1_VOLUME:
335 case WM5100_AIF1TX3MIX_INPUT_2_SOURCE:
336 case WM5100_AIF1TX3MIX_INPUT_2_VOLUME:
337 case WM5100_AIF1TX3MIX_INPUT_3_SOURCE:
338 case WM5100_AIF1TX3MIX_INPUT_3_VOLUME:
339 case WM5100_AIF1TX3MIX_INPUT_4_SOURCE:
340 case WM5100_AIF1TX3MIX_INPUT_4_VOLUME:
341 case WM5100_AIF1TX4MIX_INPUT_1_SOURCE:
342 case WM5100_AIF1TX4MIX_INPUT_1_VOLUME:
343 case WM5100_AIF1TX4MIX_INPUT_2_SOURCE:
344 case WM5100_AIF1TX4MIX_INPUT_2_VOLUME:
345 case WM5100_AIF1TX4MIX_INPUT_3_SOURCE:
346 case WM5100_AIF1TX4MIX_INPUT_3_VOLUME:
347 case WM5100_AIF1TX4MIX_INPUT_4_SOURCE:
348 case WM5100_AIF1TX4MIX_INPUT_4_VOLUME:
349 case WM5100_AIF1TX5MIX_INPUT_1_SOURCE:
350 case WM5100_AIF1TX5MIX_INPUT_1_VOLUME:
351 case WM5100_AIF1TX5MIX_INPUT_2_SOURCE:
352 case WM5100_AIF1TX5MIX_INPUT_2_VOLUME:
353 case WM5100_AIF1TX5MIX_INPUT_3_SOURCE:
354 case WM5100_AIF1TX5MIX_INPUT_3_VOLUME:
355 case WM5100_AIF1TX5MIX_INPUT_4_SOURCE:
356 case WM5100_AIF1TX5MIX_INPUT_4_VOLUME:
357 case WM5100_AIF1TX6MIX_INPUT_1_SOURCE:
358 case WM5100_AIF1TX6MIX_INPUT_1_VOLUME:
359 case WM5100_AIF1TX6MIX_INPUT_2_SOURCE:
360 case WM5100_AIF1TX6MIX_INPUT_2_VOLUME:
361 case WM5100_AIF1TX6MIX_INPUT_3_SOURCE:
362 case WM5100_AIF1TX6MIX_INPUT_3_VOLUME:
363 case WM5100_AIF1TX6MIX_INPUT_4_SOURCE:
364 case WM5100_AIF1TX6MIX_INPUT_4_VOLUME:
365 case WM5100_AIF1TX7MIX_INPUT_1_SOURCE:
366 case WM5100_AIF1TX7MIX_INPUT_1_VOLUME:
367 case WM5100_AIF1TX7MIX_INPUT_2_SOURCE:
368 case WM5100_AIF1TX7MIX_INPUT_2_VOLUME:
369 case WM5100_AIF1TX7MIX_INPUT_3_SOURCE:
370 case WM5100_AIF1TX7MIX_INPUT_3_VOLUME:
371 case WM5100_AIF1TX7MIX_INPUT_4_SOURCE:
372 case WM5100_AIF1TX7MIX_INPUT_4_VOLUME:
373 case WM5100_AIF1TX8MIX_INPUT_1_SOURCE:
374 case WM5100_AIF1TX8MIX_INPUT_1_VOLUME:
375 case WM5100_AIF1TX8MIX_INPUT_2_SOURCE:
376 case WM5100_AIF1TX8MIX_INPUT_2_VOLUME:
377 case WM5100_AIF1TX8MIX_INPUT_3_SOURCE:
378 case WM5100_AIF1TX8MIX_INPUT_3_VOLUME:
379 case WM5100_AIF1TX8MIX_INPUT_4_SOURCE:
380 case WM5100_AIF1TX8MIX_INPUT_4_VOLUME:
381 case WM5100_AIF2TX1MIX_INPUT_1_SOURCE:
382 case WM5100_AIF2TX1MIX_INPUT_1_VOLUME:
383 case WM5100_AIF2TX1MIX_INPUT_2_SOURCE:
384 case WM5100_AIF2TX1MIX_INPUT_2_VOLUME:
385 case WM5100_AIF2TX1MIX_INPUT_3_SOURCE:
386 case WM5100_AIF2TX1MIX_INPUT_3_VOLUME:
387 case WM5100_AIF2TX1MIX_INPUT_4_SOURCE:
388 case WM5100_AIF2TX1MIX_INPUT_4_VOLUME:
389 case WM5100_AIF2TX2MIX_INPUT_1_SOURCE:
390 case WM5100_AIF2TX2MIX_INPUT_1_VOLUME:
391 case WM5100_AIF2TX2MIX_INPUT_2_SOURCE:
392 case WM5100_AIF2TX2MIX_INPUT_2_VOLUME:
393 case WM5100_AIF2TX2MIX_INPUT_3_SOURCE:
394 case WM5100_AIF2TX2MIX_INPUT_3_VOLUME:
395 case WM5100_AIF2TX2MIX_INPUT_4_SOURCE:
396 case WM5100_AIF2TX2MIX_INPUT_4_VOLUME:
397 case WM5100_AIF3TX1MIX_INPUT_1_SOURCE:
398 case WM5100_AIF3TX1MIX_INPUT_1_VOLUME:
399 case WM5100_AIF3TX1MIX_INPUT_2_SOURCE:
400 case WM5100_AIF3TX1MIX_INPUT_2_VOLUME:
401 case WM5100_AIF3TX1MIX_INPUT_3_SOURCE:
402 case WM5100_AIF3TX1MIX_INPUT_3_VOLUME:
403 case WM5100_AIF3TX1MIX_INPUT_4_SOURCE:
404 case WM5100_AIF3TX1MIX_INPUT_4_VOLUME:
405 case WM5100_AIF3TX2MIX_INPUT_1_SOURCE:
406 case WM5100_AIF3TX2MIX_INPUT_1_VOLUME:
407 case WM5100_AIF3TX2MIX_INPUT_2_SOURCE:
408 case WM5100_AIF3TX2MIX_INPUT_2_VOLUME:
409 case WM5100_AIF3TX2MIX_INPUT_3_SOURCE:
410 case WM5100_AIF3TX2MIX_INPUT_3_VOLUME:
411 case WM5100_AIF3TX2MIX_INPUT_4_SOURCE:
412 case WM5100_AIF3TX2MIX_INPUT_4_VOLUME:
413 case WM5100_EQ1MIX_INPUT_1_SOURCE:
414 case WM5100_EQ1MIX_INPUT_1_VOLUME:
415 case WM5100_EQ1MIX_INPUT_2_SOURCE:
416 case WM5100_EQ1MIX_INPUT_2_VOLUME:
417 case WM5100_EQ1MIX_INPUT_3_SOURCE:
418 case WM5100_EQ1MIX_INPUT_3_VOLUME:
419 case WM5100_EQ1MIX_INPUT_4_SOURCE:
420 case WM5100_EQ1MIX_INPUT_4_VOLUME:
421 case WM5100_EQ2MIX_INPUT_1_SOURCE:
422 case WM5100_EQ2MIX_INPUT_1_VOLUME:
423 case WM5100_EQ2MIX_INPUT_2_SOURCE:
424 case WM5100_EQ2MIX_INPUT_2_VOLUME:
425 case WM5100_EQ2MIX_INPUT_3_SOURCE:
426 case WM5100_EQ2MIX_INPUT_3_VOLUME:
427 case WM5100_EQ2MIX_INPUT_4_SOURCE:
428 case WM5100_EQ2MIX_INPUT_4_VOLUME:
429 case WM5100_EQ3MIX_INPUT_1_SOURCE:
430 case WM5100_EQ3MIX_INPUT_1_VOLUME:
431 case WM5100_EQ3MIX_INPUT_2_SOURCE:
432 case WM5100_EQ3MIX_INPUT_2_VOLUME:
433 case WM5100_EQ3MIX_INPUT_3_SOURCE:
434 case WM5100_EQ3MIX_INPUT_3_VOLUME:
435 case WM5100_EQ3MIX_INPUT_4_SOURCE:
436 case WM5100_EQ3MIX_INPUT_4_VOLUME:
437 case WM5100_EQ4MIX_INPUT_1_SOURCE:
438 case WM5100_EQ4MIX_INPUT_1_VOLUME:
439 case WM5100_EQ4MIX_INPUT_2_SOURCE:
440 case WM5100_EQ4MIX_INPUT_2_VOLUME:
441 case WM5100_EQ4MIX_INPUT_3_SOURCE:
442 case WM5100_EQ4MIX_INPUT_3_VOLUME:
443 case WM5100_EQ4MIX_INPUT_4_SOURCE:
444 case WM5100_EQ4MIX_INPUT_4_VOLUME:
445 case WM5100_DRC1LMIX_INPUT_1_SOURCE:
446 case WM5100_DRC1LMIX_INPUT_1_VOLUME:
447 case WM5100_DRC1LMIX_INPUT_2_SOURCE:
448 case WM5100_DRC1LMIX_INPUT_2_VOLUME:
449 case WM5100_DRC1LMIX_INPUT_3_SOURCE:
450 case WM5100_DRC1LMIX_INPUT_3_VOLUME:
451 case WM5100_DRC1LMIX_INPUT_4_SOURCE:
452 case WM5100_DRC1LMIX_INPUT_4_VOLUME:
453 case WM5100_DRC1RMIX_INPUT_1_SOURCE:
454 case WM5100_DRC1RMIX_INPUT_1_VOLUME:
455 case WM5100_DRC1RMIX_INPUT_2_SOURCE:
456 case WM5100_DRC1RMIX_INPUT_2_VOLUME:
457 case WM5100_DRC1RMIX_INPUT_3_SOURCE:
458 case WM5100_DRC1RMIX_INPUT_3_VOLUME:
459 case WM5100_DRC1RMIX_INPUT_4_SOURCE:
460 case WM5100_DRC1RMIX_INPUT_4_VOLUME:
461 case WM5100_HPLP1MIX_INPUT_1_SOURCE:
462 case WM5100_HPLP1MIX_INPUT_1_VOLUME:
463 case WM5100_HPLP1MIX_INPUT_2_SOURCE:
464 case WM5100_HPLP1MIX_INPUT_2_VOLUME:
465 case WM5100_HPLP1MIX_INPUT_3_SOURCE:
466 case WM5100_HPLP1MIX_INPUT_3_VOLUME:
467 case WM5100_HPLP1MIX_INPUT_4_SOURCE:
468 case WM5100_HPLP1MIX_INPUT_4_VOLUME:
469 case WM5100_HPLP2MIX_INPUT_1_SOURCE:
470 case WM5100_HPLP2MIX_INPUT_1_VOLUME:
471 case WM5100_HPLP2MIX_INPUT_2_SOURCE:
472 case WM5100_HPLP2MIX_INPUT_2_VOLUME:
473 case WM5100_HPLP2MIX_INPUT_3_SOURCE:
474 case WM5100_HPLP2MIX_INPUT_3_VOLUME:
475 case WM5100_HPLP2MIX_INPUT_4_SOURCE:
476 case WM5100_HPLP2MIX_INPUT_4_VOLUME:
477 case WM5100_HPLP3MIX_INPUT_1_SOURCE:
478 case WM5100_HPLP3MIX_INPUT_1_VOLUME:
479 case WM5100_HPLP3MIX_INPUT_2_SOURCE:
480 case WM5100_HPLP3MIX_INPUT_2_VOLUME:
481 case WM5100_HPLP3MIX_INPUT_3_SOURCE:
482 case WM5100_HPLP3MIX_INPUT_3_VOLUME:
483 case WM5100_HPLP3MIX_INPUT_4_SOURCE:
484 case WM5100_HPLP3MIX_INPUT_4_VOLUME:
485 case WM5100_HPLP4MIX_INPUT_1_SOURCE:
486 case WM5100_HPLP4MIX_INPUT_1_VOLUME:
487 case WM5100_HPLP4MIX_INPUT_2_SOURCE:
488 case WM5100_HPLP4MIX_INPUT_2_VOLUME:
489 case WM5100_HPLP4MIX_INPUT_3_SOURCE:
490 case WM5100_HPLP4MIX_INPUT_3_VOLUME:
491 case WM5100_HPLP4MIX_INPUT_4_SOURCE:
492 case WM5100_HPLP4MIX_INPUT_4_VOLUME:
493 case WM5100_DSP1LMIX_INPUT_1_SOURCE:
494 case WM5100_DSP1LMIX_INPUT_1_VOLUME:
495 case WM5100_DSP1LMIX_INPUT_2_SOURCE:
496 case WM5100_DSP1LMIX_INPUT_2_VOLUME:
497 case WM5100_DSP1LMIX_INPUT_3_SOURCE:
498 case WM5100_DSP1LMIX_INPUT_3_VOLUME:
499 case WM5100_DSP1LMIX_INPUT_4_SOURCE:
500 case WM5100_DSP1LMIX_INPUT_4_VOLUME:
501 case WM5100_DSP1RMIX_INPUT_1_SOURCE:
502 case WM5100_DSP1RMIX_INPUT_1_VOLUME:
503 case WM5100_DSP1RMIX_INPUT_2_SOURCE:
504 case WM5100_DSP1RMIX_INPUT_2_VOLUME:
505 case WM5100_DSP1RMIX_INPUT_3_SOURCE:
506 case WM5100_DSP1RMIX_INPUT_3_VOLUME:
507 case WM5100_DSP1RMIX_INPUT_4_SOURCE:
508 case WM5100_DSP1RMIX_INPUT_4_VOLUME:
509 case WM5100_DSP1AUX1MIX_INPUT_1_SOURCE:
510 case WM5100_DSP1AUX2MIX_INPUT_1_SOURCE:
511 case WM5100_DSP1AUX3MIX_INPUT_1_SOURCE:
512 case WM5100_DSP1AUX4MIX_INPUT_1_SOURCE:
513 case WM5100_DSP1AUX5MIX_INPUT_1_SOURCE:
514 case WM5100_DSP1AUX6MIX_INPUT_1_SOURCE:
515 case WM5100_DSP2LMIX_INPUT_1_SOURCE:
516 case WM5100_DSP2LMIX_INPUT_1_VOLUME:
517 case WM5100_DSP2LMIX_INPUT_2_SOURCE:
518 case WM5100_DSP2LMIX_INPUT_2_VOLUME:
519 case WM5100_DSP2LMIX_INPUT_3_SOURCE:
520 case WM5100_DSP2LMIX_INPUT_3_VOLUME:
521 case WM5100_DSP2LMIX_INPUT_4_SOURCE:
522 case WM5100_DSP2LMIX_INPUT_4_VOLUME:
523 case WM5100_DSP2RMIX_INPUT_1_SOURCE:
524 case WM5100_DSP2RMIX_INPUT_1_VOLUME:
525 case WM5100_DSP2RMIX_INPUT_2_SOURCE:
526 case WM5100_DSP2RMIX_INPUT_2_VOLUME:
527 case WM5100_DSP2RMIX_INPUT_3_SOURCE:
528 case WM5100_DSP2RMIX_INPUT_3_VOLUME:
529 case WM5100_DSP2RMIX_INPUT_4_SOURCE:
530 case WM5100_DSP2RMIX_INPUT_4_VOLUME:
531 case WM5100_DSP2AUX1MIX_INPUT_1_SOURCE:
532 case WM5100_DSP2AUX2MIX_INPUT_1_SOURCE:
533 case WM5100_DSP2AUX3MIX_INPUT_1_SOURCE:
534 case WM5100_DSP2AUX4MIX_INPUT_1_SOURCE:
535 case WM5100_DSP2AUX5MIX_INPUT_1_SOURCE:
536 case WM5100_DSP2AUX6MIX_INPUT_1_SOURCE:
537 case WM5100_DSP3LMIX_INPUT_1_SOURCE:
538 case WM5100_DSP3LMIX_INPUT_1_VOLUME:
539 case WM5100_DSP3LMIX_INPUT_2_SOURCE:
540 case WM5100_DSP3LMIX_INPUT_2_VOLUME:
541 case WM5100_DSP3LMIX_INPUT_3_SOURCE:
542 case WM5100_DSP3LMIX_INPUT_3_VOLUME:
543 case WM5100_DSP3LMIX_INPUT_4_SOURCE:
544 case WM5100_DSP3LMIX_INPUT_4_VOLUME:
545 case WM5100_DSP3RMIX_INPUT_1_SOURCE:
546 case WM5100_DSP3RMIX_INPUT_1_VOLUME:
547 case WM5100_DSP3RMIX_INPUT_2_SOURCE:
548 case WM5100_DSP3RMIX_INPUT_2_VOLUME:
549 case WM5100_DSP3RMIX_INPUT_3_SOURCE:
550 case WM5100_DSP3RMIX_INPUT_3_VOLUME:
551 case WM5100_DSP3RMIX_INPUT_4_SOURCE:
552 case WM5100_DSP3RMIX_INPUT_4_VOLUME:
553 case WM5100_DSP3AUX1MIX_INPUT_1_SOURCE:
554 case WM5100_DSP3AUX2MIX_INPUT_1_SOURCE:
555 case WM5100_DSP3AUX3MIX_INPUT_1_SOURCE:
556 case WM5100_DSP3AUX4MIX_INPUT_1_SOURCE:
557 case WM5100_DSP3AUX5MIX_INPUT_1_SOURCE:
558 case WM5100_DSP3AUX6MIX_INPUT_1_SOURCE:
559 case WM5100_ASRC1LMIX_INPUT_1_SOURCE:
560 case WM5100_ASRC1RMIX_INPUT_1_SOURCE:
561 case WM5100_ASRC2LMIX_INPUT_1_SOURCE:
562 case WM5100_ASRC2RMIX_INPUT_1_SOURCE:
563 case WM5100_ISRC1DEC1MIX_INPUT_1_SOURCE:
564 case WM5100_ISRC1DEC2MIX_INPUT_1_SOURCE:
565 case WM5100_ISRC1DEC3MIX_INPUT_1_SOURCE:
566 case WM5100_ISRC1DEC4MIX_INPUT_1_SOURCE:
567 case WM5100_ISRC1INT1MIX_INPUT_1_SOURCE:
568 case WM5100_ISRC1INT2MIX_INPUT_1_SOURCE:
569 case WM5100_ISRC1INT3MIX_INPUT_1_SOURCE:
570 case WM5100_ISRC1INT4MIX_INPUT_1_SOURCE:
571 case WM5100_ISRC2DEC1MIX_INPUT_1_SOURCE:
572 case WM5100_ISRC2DEC2MIX_INPUT_1_SOURCE:
573 case WM5100_ISRC2DEC3MIX_INPUT_1_SOURCE:
574 case WM5100_ISRC2DEC4MIX_INPUT_1_SOURCE:
575 case WM5100_ISRC2INT1MIX_INPUT_1_SOURCE:
576 case WM5100_ISRC2INT2MIX_INPUT_1_SOURCE:
577 case WM5100_ISRC2INT3MIX_INPUT_1_SOURCE:
578 case WM5100_ISRC2INT4MIX_INPUT_1_SOURCE:
579 case WM5100_GPIO_CTRL_1:
580 case WM5100_GPIO_CTRL_2:
581 case WM5100_GPIO_CTRL_3:
582 case WM5100_GPIO_CTRL_4:
583 case WM5100_GPIO_CTRL_5:
584 case WM5100_GPIO_CTRL_6:
585 case WM5100_MISC_PAD_CTRL_1:
586 case WM5100_MISC_PAD_CTRL_2:
587 case WM5100_MISC_PAD_CTRL_3:
588 case WM5100_MISC_PAD_CTRL_4:
589 case WM5100_MISC_PAD_CTRL_5:
590 case WM5100_MISC_GPIO_1:
591 case WM5100_INTERRUPT_STATUS_1:
592 case WM5100_INTERRUPT_STATUS_2:
593 case WM5100_INTERRUPT_STATUS_3:
594 case WM5100_INTERRUPT_STATUS_4:
595 case WM5100_INTERRUPT_RAW_STATUS_2:
596 case WM5100_INTERRUPT_RAW_STATUS_3:
597 case WM5100_INTERRUPT_RAW_STATUS_4:
598 case WM5100_INTERRUPT_STATUS_1_MASK:
599 case WM5100_INTERRUPT_STATUS_2_MASK:
600 case WM5100_INTERRUPT_STATUS_3_MASK:
601 case WM5100_INTERRUPT_STATUS_4_MASK:
602 case WM5100_INTERRUPT_CONTROL:
603 case WM5100_IRQ_DEBOUNCE_1:
604 case WM5100_IRQ_DEBOUNCE_2:
605 case WM5100_FX_CTRL:
606 case WM5100_EQ1_1:
607 case WM5100_EQ1_2:
608 case WM5100_EQ1_3:
609 case WM5100_EQ1_4:
610 case WM5100_EQ1_5:
611 case WM5100_EQ1_6:
612 case WM5100_EQ1_7:
613 case WM5100_EQ1_8:
614 case WM5100_EQ1_9:
615 case WM5100_EQ1_10:
616 case WM5100_EQ1_11:
617 case WM5100_EQ1_12:
618 case WM5100_EQ1_13:
619 case WM5100_EQ1_14:
620 case WM5100_EQ1_15:
621 case WM5100_EQ1_16:
622 case WM5100_EQ1_17:
623 case WM5100_EQ1_18:
624 case WM5100_EQ1_19:
625 case WM5100_EQ1_20:
626 case WM5100_EQ2_1:
627 case WM5100_EQ2_2:
628 case WM5100_EQ2_3:
629 case WM5100_EQ2_4:
630 case WM5100_EQ2_5:
631 case WM5100_EQ2_6:
632 case WM5100_EQ2_7:
633 case WM5100_EQ2_8:
634 case WM5100_EQ2_9:
635 case WM5100_EQ2_10:
636 case WM5100_EQ2_11:
637 case WM5100_EQ2_12:
638 case WM5100_EQ2_13:
639 case WM5100_EQ2_14:
640 case WM5100_EQ2_15:
641 case WM5100_EQ2_16:
642 case WM5100_EQ2_17:
643 case WM5100_EQ2_18:
644 case WM5100_EQ2_19:
645 case WM5100_EQ2_20:
646 case WM5100_EQ3_1:
647 case WM5100_EQ3_2:
648 case WM5100_EQ3_3:
649 case WM5100_EQ3_4:
650 case WM5100_EQ3_5:
651 case WM5100_EQ3_6:
652 case WM5100_EQ3_7:
653 case WM5100_EQ3_8:
654 case WM5100_EQ3_9:
655 case WM5100_EQ3_10:
656 case WM5100_EQ3_11:
657 case WM5100_EQ3_12:
658 case WM5100_EQ3_13:
659 case WM5100_EQ3_14:
660 case WM5100_EQ3_15:
661 case WM5100_EQ3_16:
662 case WM5100_EQ3_17:
663 case WM5100_EQ3_18:
664 case WM5100_EQ3_19:
665 case WM5100_EQ3_20:
666 case WM5100_EQ4_1:
667 case WM5100_EQ4_2:
668 case WM5100_EQ4_3:
669 case WM5100_EQ4_4:
670 case WM5100_EQ4_5:
671 case WM5100_EQ4_6:
672 case WM5100_EQ4_7:
673 case WM5100_EQ4_8:
674 case WM5100_EQ4_9:
675 case WM5100_EQ4_10:
676 case WM5100_EQ4_11:
677 case WM5100_EQ4_12:
678 case WM5100_EQ4_13:
679 case WM5100_EQ4_14:
680 case WM5100_EQ4_15:
681 case WM5100_EQ4_16:
682 case WM5100_EQ4_17:
683 case WM5100_EQ4_18:
684 case WM5100_EQ4_19:
685 case WM5100_EQ4_20:
686 case WM5100_DRC1_CTRL1:
687 case WM5100_DRC1_CTRL2:
688 case WM5100_DRC1_CTRL3:
689 case WM5100_DRC1_CTRL4:
690 case WM5100_DRC1_CTRL5:
691 case WM5100_HPLPF1_1:
692 case WM5100_HPLPF1_2:
693 case WM5100_HPLPF2_1:
694 case WM5100_HPLPF2_2:
695 case WM5100_HPLPF3_1:
696 case WM5100_HPLPF3_2:
697 case WM5100_HPLPF4_1:
698 case WM5100_HPLPF4_2:
699 case WM5100_DSP1_DM_0:
700 case WM5100_DSP1_DM_1:
701 case WM5100_DSP1_DM_2:
702 case WM5100_DSP1_DM_3:
703 case WM5100_DSP1_DM_508:
704 case WM5100_DSP1_DM_509:
705 case WM5100_DSP1_DM_510:
706 case WM5100_DSP1_DM_511:
707 case WM5100_DSP1_PM_0:
708 case WM5100_DSP1_PM_1:
709 case WM5100_DSP1_PM_2:
710 case WM5100_DSP1_PM_3:
711 case WM5100_DSP1_PM_4:
712 case WM5100_DSP1_PM_5:
713 case WM5100_DSP1_PM_1530:
714 case WM5100_DSP1_PM_1531:
715 case WM5100_DSP1_PM_1532:
716 case WM5100_DSP1_PM_1533:
717 case WM5100_DSP1_PM_1534:
718 case WM5100_DSP1_PM_1535:
719 case WM5100_DSP1_ZM_0:
720 case WM5100_DSP1_ZM_1:
721 case WM5100_DSP1_ZM_2:
722 case WM5100_DSP1_ZM_3:
723 case WM5100_DSP1_ZM_2044:
724 case WM5100_DSP1_ZM_2045:
725 case WM5100_DSP1_ZM_2046:
726 case WM5100_DSP1_ZM_2047:
727 case WM5100_DSP2_DM_0:
728 case WM5100_DSP2_DM_1:
729 case WM5100_DSP2_DM_2:
730 case WM5100_DSP2_DM_3:
731 case WM5100_DSP2_DM_508:
732 case WM5100_DSP2_DM_509:
733 case WM5100_DSP2_DM_510:
734 case WM5100_DSP2_DM_511:
735 case WM5100_DSP2_PM_0:
736 case WM5100_DSP2_PM_1:
737 case WM5100_DSP2_PM_2:
738 case WM5100_DSP2_PM_3:
739 case WM5100_DSP2_PM_4:
740 case WM5100_DSP2_PM_5:
741 case WM5100_DSP2_PM_1530:
742 case WM5100_DSP2_PM_1531:
743 case WM5100_DSP2_PM_1532:
744 case WM5100_DSP2_PM_1533:
745 case WM5100_DSP2_PM_1534:
746 case WM5100_DSP2_PM_1535:
747 case WM5100_DSP2_ZM_0:
748 case WM5100_DSP2_ZM_1:
749 case WM5100_DSP2_ZM_2:
750 case WM5100_DSP2_ZM_3:
751 case WM5100_DSP2_ZM_2044:
752 case WM5100_DSP2_ZM_2045:
753 case WM5100_DSP2_ZM_2046:
754 case WM5100_DSP2_ZM_2047:
755 case WM5100_DSP3_DM_0:
756 case WM5100_DSP3_DM_1:
757 case WM5100_DSP3_DM_2:
758 case WM5100_DSP3_DM_3:
759 case WM5100_DSP3_DM_508:
760 case WM5100_DSP3_DM_509:
761 case WM5100_DSP3_DM_510:
762 case WM5100_DSP3_DM_511:
763 case WM5100_DSP3_PM_0:
764 case WM5100_DSP3_PM_1:
765 case WM5100_DSP3_PM_2:
766 case WM5100_DSP3_PM_3:
767 case WM5100_DSP3_PM_4:
768 case WM5100_DSP3_PM_5:
769 case WM5100_DSP3_PM_1530:
770 case WM5100_DSP3_PM_1531:
771 case WM5100_DSP3_PM_1532:
772 case WM5100_DSP3_PM_1533:
773 case WM5100_DSP3_PM_1534:
774 case WM5100_DSP3_PM_1535:
775 case WM5100_DSP3_ZM_0:
776 case WM5100_DSP3_ZM_1:
777 case WM5100_DSP3_ZM_2:
778 case WM5100_DSP3_ZM_3:
779 case WM5100_DSP3_ZM_2044:
780 case WM5100_DSP3_ZM_2045:
781 case WM5100_DSP3_ZM_2046:
782 case WM5100_DSP3_ZM_2047:
783 return 1;
784 default:
785 return 0;
786 }
787}
788
789u16 wm5100_reg_defaults[WM5100_MAX_REGISTER + 1] = {
790 [0x0000] = 0x0000, /* R0 - software reset */
791 [0x0001] = 0x0000, /* R1 - Device Revision */
792 [0x0010] = 0x0801, /* R16 - Ctrl IF 1 */
793 [0x0020] = 0x0000, /* R32 - Tone Generator 1 */
794 [0x0030] = 0x0000, /* R48 - PWM Drive 1 */
795 [0x0031] = 0x0100, /* R49 - PWM Drive 2 */
796 [0x0032] = 0x0100, /* R50 - PWM Drive 3 */
797 [0x0101] = 0x0000, /* R257 - Clocking 3 */
798 [0x0102] = 0x0011, /* R258 - Clocking 4 */
799 [0x0103] = 0x0011, /* R259 - Clocking 5 */
800 [0x0104] = 0x0011, /* R260 - Clocking 6 */
801 [0x0107] = 0x0000, /* R263 - Clocking 7 */
802 [0x0108] = 0x0000, /* R264 - Clocking 8 */
803 [0x0120] = 0x0000, /* R288 - ASRC_ENABLE */
804 [0x0121] = 0x0000, /* R289 - ASRC_STATUS */
805 [0x0122] = 0x0000, /* R290 - ASRC_RATE1 */
806 [0x0141] = 0x8000, /* R321 - ISRC 1 CTRL 1 */
807 [0x0142] = 0x0000, /* R322 - ISRC 1 CTRL 2 */
808 [0x0143] = 0x8000, /* R323 - ISRC 2 CTRL1 */
809 [0x0144] = 0x0000, /* R324 - ISRC 2 CTRL 2 */
810 [0x0182] = 0x0000, /* R386 - FLL1 Control 1 */
811 [0x0183] = 0x0000, /* R387 - FLL1 Control 2 */
812 [0x0184] = 0x0000, /* R388 - FLL1 Control 3 */
813 [0x0186] = 0x0177, /* R390 - FLL1 Control 5 */
814 [0x0187] = 0x0001, /* R391 - FLL1 Control 6 */
815 [0x0188] = 0x0000, /* R392 - FLL1 EFS 1 */
816 [0x01A2] = 0x0000, /* R418 - FLL2 Control 1 */
817 [0x01A3] = 0x0000, /* R419 - FLL2 Control 2 */
818 [0x01A4] = 0x0000, /* R420 - FLL2 Control 3 */
819 [0x01A6] = 0x0177, /* R422 - FLL2 Control 5 */
820 [0x01A7] = 0x0001, /* R423 - FLL2 Control 6 */
821 [0x01A8] = 0x0000, /* R424 - FLL2 EFS 1 */
822 [0x0200] = 0x0020, /* R512 - Mic Charge Pump 1 */
823 [0x0201] = 0xB084, /* R513 - Mic Charge Pump 2 */
824 [0x0202] = 0xBBDE, /* R514 - HP Charge Pump 1 */
825 [0x0211] = 0x20D4, /* R529 - LDO1 Control */
826 [0x0215] = 0x0062, /* R533 - Mic Bias Ctrl 1 */
827 [0x0216] = 0x0062, /* R534 - Mic Bias Ctrl 2 */
828 [0x0217] = 0x0062, /* R535 - Mic Bias Ctrl 3 */
829 [0x0280] = 0x0004, /* R640 - Accessory Detect Mode 1 */
830 [0x0288] = 0x0020, /* R648 - Headphone Detect 1 */
831 [0x0289] = 0x0000, /* R649 - Headphone Detect 2 */
832 [0x0290] = 0x1100, /* R656 - Mic Detect 1 */
833 [0x0291] = 0x009F, /* R657 - Mic Detect 2 */
834 [0x0292] = 0x0000, /* R658 - Mic Detect 3 */
835 [0x0301] = 0x0000, /* R769 - Input Enables */
836 [0x0302] = 0x0000, /* R770 - Input Enables Status */
837 [0x0310] = 0x2280, /* R784 - Status */
838 [0x0311] = 0x0080, /* R785 - IN1R Control */
839 [0x0312] = 0x2280, /* R786 - IN2L Control */
840 [0x0313] = 0x0080, /* R787 - IN2R Control */
841 [0x0314] = 0x2280, /* R788 - IN3L Control */
842 [0x0315] = 0x0080, /* R789 - IN3R Control */
843 [0x0316] = 0x2280, /* R790 - IN4L Control */
844 [0x0317] = 0x0080, /* R791 - IN4R Control */
845 [0x0318] = 0x0000, /* R792 - RXANC_SRC */
846 [0x0319] = 0x0022, /* R793 - Input Volume Ramp */
847 [0x0320] = 0x0180, /* R800 - ADC Digital Volume 1L */
848 [0x0321] = 0x0180, /* R801 - ADC Digital Volume 1R */
849 [0x0322] = 0x0180, /* R802 - ADC Digital Volume 2L */
850 [0x0323] = 0x0180, /* R803 - ADC Digital Volume 2R */
851 [0x0324] = 0x0180, /* R804 - ADC Digital Volume 3L */
852 [0x0325] = 0x0180, /* R805 - ADC Digital Volume 3R */
853 [0x0326] = 0x0180, /* R806 - ADC Digital Volume 4L */
854 [0x0327] = 0x0180, /* R807 - ADC Digital Volume 4R */
855 [0x0401] = 0x0000, /* R1025 - Output Enables 2 */
856 [0x0402] = 0x0000, /* R1026 - Output Status 1 */
857 [0x0403] = 0x0000, /* R1027 - Output Status 2 */
858 [0x0408] = 0x0000, /* R1032 - Channel Enables 1 */
859 [0x0410] = 0x0080, /* R1040 - Out Volume 1L */
860 [0x0411] = 0x0080, /* R1041 - Out Volume 1R */
861 [0x0412] = 0x0080, /* R1042 - DAC Volume Limit 1L */
862 [0x0413] = 0x0080, /* R1043 - DAC Volume Limit 1R */
863 [0x0414] = 0x0080, /* R1044 - Out Volume 2L */
864 [0x0415] = 0x0080, /* R1045 - Out Volume 2R */
865 [0x0416] = 0x0080, /* R1046 - DAC Volume Limit 2L */
866 [0x0417] = 0x0080, /* R1047 - DAC Volume Limit 2R */
867 [0x0418] = 0x0080, /* R1048 - Out Volume 3L */
868 [0x0419] = 0x0080, /* R1049 - Out Volume 3R */
869 [0x041A] = 0x0080, /* R1050 - DAC Volume Limit 3L */
870 [0x041B] = 0x0080, /* R1051 - DAC Volume Limit 3R */
871 [0x041C] = 0x0080, /* R1052 - Out Volume 4L */
872 [0x041D] = 0x0080, /* R1053 - Out Volume 4R */
873 [0x041E] = 0x0080, /* R1054 - DAC Volume Limit 5L */
874 [0x041F] = 0x0080, /* R1055 - DAC Volume Limit 5R */
875 [0x0420] = 0x0080, /* R1056 - DAC Volume Limit 6L */
876 [0x0421] = 0x0080, /* R1057 - DAC Volume Limit 6R */
877 [0x0440] = 0x0000, /* R1088 - DAC AEC Control 1 */
878 [0x0441] = 0x0022, /* R1089 - Output Volume Ramp */
879 [0x0480] = 0x0180, /* R1152 - DAC Digital Volume 1L */
880 [0x0481] = 0x0180, /* R1153 - DAC Digital Volume 1R */
881 [0x0482] = 0x0180, /* R1154 - DAC Digital Volume 2L */
882 [0x0483] = 0x0180, /* R1155 - DAC Digital Volume 2R */
883 [0x0484] = 0x0180, /* R1156 - DAC Digital Volume 3L */
884 [0x0485] = 0x0180, /* R1157 - DAC Digital Volume 3R */
885 [0x0486] = 0x0180, /* R1158 - DAC Digital Volume 4L */
886 [0x0487] = 0x0180, /* R1159 - DAC Digital Volume 4R */
887 [0x0488] = 0x0180, /* R1160 - DAC Digital Volume 5L */
888 [0x0489] = 0x0180, /* R1161 - DAC Digital Volume 5R */
889 [0x048A] = 0x0180, /* R1162 - DAC Digital Volume 6L */
890 [0x048B] = 0x0180, /* R1163 - DAC Digital Volume 6R */
891 [0x04C0] = 0x0069, /* R1216 - PDM SPK1 CTRL 1 */
892 [0x04C1] = 0x0000, /* R1217 - PDM SPK1 CTRL 2 */
893 [0x04C2] = 0x0069, /* R1218 - PDM SPK2 CTRL 1 */
894 [0x04C3] = 0x0000, /* R1219 - PDM SPK2 CTRL 2 */
895 [0x0500] = 0x000C, /* R1280 - Audio IF 1_1 */
896 [0x0501] = 0x0008, /* R1281 - Audio IF 1_2 */
897 [0x0502] = 0x0000, /* R1282 - Audio IF 1_3 */
898 [0x0503] = 0x0000, /* R1283 - Audio IF 1_4 */
899 [0x0504] = 0x0000, /* R1284 - Audio IF 1_5 */
900 [0x0505] = 0x0300, /* R1285 - Audio IF 1_6 */
901 [0x0506] = 0x0300, /* R1286 - Audio IF 1_7 */
902 [0x0507] = 0x1820, /* R1287 - Audio IF 1_8 */
903 [0x0508] = 0x1820, /* R1288 - Audio IF 1_9 */
904 [0x0509] = 0x0000, /* R1289 - Audio IF 1_10 */
905 [0x050A] = 0x0001, /* R1290 - Audio IF 1_11 */
906 [0x050B] = 0x0002, /* R1291 - Audio IF 1_12 */
907 [0x050C] = 0x0003, /* R1292 - Audio IF 1_13 */
908 [0x050D] = 0x0004, /* R1293 - Audio IF 1_14 */
909 [0x050E] = 0x0005, /* R1294 - Audio IF 1_15 */
910 [0x050F] = 0x0006, /* R1295 - Audio IF 1_16 */
911 [0x0510] = 0x0007, /* R1296 - Audio IF 1_17 */
912 [0x0511] = 0x0000, /* R1297 - Audio IF 1_18 */
913 [0x0512] = 0x0001, /* R1298 - Audio IF 1_19 */
914 [0x0513] = 0x0002, /* R1299 - Audio IF 1_20 */
915 [0x0514] = 0x0003, /* R1300 - Audio IF 1_21 */
916 [0x0515] = 0x0004, /* R1301 - Audio IF 1_22 */
917 [0x0516] = 0x0005, /* R1302 - Audio IF 1_23 */
918 [0x0517] = 0x0006, /* R1303 - Audio IF 1_24 */
919 [0x0518] = 0x0007, /* R1304 - Audio IF 1_25 */
920 [0x0519] = 0x0000, /* R1305 - Audio IF 1_26 */
921 [0x051A] = 0x0000, /* R1306 - Audio IF 1_27 */
922 [0x0540] = 0x000C, /* R1344 - Audio IF 2_1 */
923 [0x0541] = 0x0008, /* R1345 - Audio IF 2_2 */
924 [0x0542] = 0x0000, /* R1346 - Audio IF 2_3 */
925 [0x0543] = 0x0000, /* R1347 - Audio IF 2_4 */
926 [0x0544] = 0x0000, /* R1348 - Audio IF 2_5 */
927 [0x0545] = 0x0300, /* R1349 - Audio IF 2_6 */
928 [0x0546] = 0x0300, /* R1350 - Audio IF 2_7 */
929 [0x0547] = 0x1820, /* R1351 - Audio IF 2_8 */
930 [0x0548] = 0x1820, /* R1352 - Audio IF 2_9 */
931 [0x0549] = 0x0000, /* R1353 - Audio IF 2_10 */
932 [0x054A] = 0x0001, /* R1354 - Audio IF 2_11 */
933 [0x0551] = 0x0000, /* R1361 - Audio IF 2_18 */
934 [0x0552] = 0x0001, /* R1362 - Audio IF 2_19 */
935 [0x0559] = 0x0000, /* R1369 - Audio IF 2_26 */
936 [0x055A] = 0x0000, /* R1370 - Audio IF 2_27 */
937 [0x0580] = 0x000C, /* R1408 - Audio IF 3_1 */
938 [0x0581] = 0x0008, /* R1409 - Audio IF 3_2 */
939 [0x0582] = 0x0000, /* R1410 - Audio IF 3_3 */
940 [0x0583] = 0x0000, /* R1411 - Audio IF 3_4 */
941 [0x0584] = 0x0000, /* R1412 - Audio IF 3_5 */
942 [0x0585] = 0x0300, /* R1413 - Audio IF 3_6 */
943 [0x0586] = 0x0300, /* R1414 - Audio IF 3_7 */
944 [0x0587] = 0x1820, /* R1415 - Audio IF 3_8 */
945 [0x0588] = 0x1820, /* R1416 - Audio IF 3_9 */
946 [0x0589] = 0x0000, /* R1417 - Audio IF 3_10 */
947 [0x058A] = 0x0001, /* R1418 - Audio IF 3_11 */
948 [0x0591] = 0x0000, /* R1425 - Audio IF 3_18 */
949 [0x0592] = 0x0001, /* R1426 - Audio IF 3_19 */
950 [0x0599] = 0x0000, /* R1433 - Audio IF 3_26 */
951 [0x059A] = 0x0000, /* R1434 - Audio IF 3_27 */
952 [0x0640] = 0x0000, /* R1600 - PWM1MIX Input 1 Source */
953 [0x0641] = 0x0080, /* R1601 - PWM1MIX Input 1 Volume */
954 [0x0642] = 0x0000, /* R1602 - PWM1MIX Input 2 Source */
955 [0x0643] = 0x0080, /* R1603 - PWM1MIX Input 2 Volume */
956 [0x0644] = 0x0000, /* R1604 - PWM1MIX Input 3 Source */
957 [0x0645] = 0x0080, /* R1605 - PWM1MIX Input 3 Volume */
958 [0x0646] = 0x0000, /* R1606 - PWM1MIX Input 4 Source */
959 [0x0647] = 0x0080, /* R1607 - PWM1MIX Input 4 Volume */
960 [0x0648] = 0x0000, /* R1608 - PWM2MIX Input 1 Source */
961 [0x0649] = 0x0080, /* R1609 - PWM2MIX Input 1 Volume */
962 [0x064A] = 0x0000, /* R1610 - PWM2MIX Input 2 Source */
963 [0x064B] = 0x0080, /* R1611 - PWM2MIX Input 2 Volume */
964 [0x064C] = 0x0000, /* R1612 - PWM2MIX Input 3 Source */
965 [0x064D] = 0x0080, /* R1613 - PWM2MIX Input 3 Volume */
966 [0x064E] = 0x0000, /* R1614 - PWM2MIX Input 4 Source */
967 [0x064F] = 0x0080, /* R1615 - PWM2MIX Input 4 Volume */
968 [0x0680] = 0x0000, /* R1664 - OUT1LMIX Input 1 Source */
969 [0x0681] = 0x0080, /* R1665 - OUT1LMIX Input 1 Volume */
970 [0x0682] = 0x0000, /* R1666 - OUT1LMIX Input 2 Source */
971 [0x0683] = 0x0080, /* R1667 - OUT1LMIX Input 2 Volume */
972 [0x0684] = 0x0000, /* R1668 - OUT1LMIX Input 3 Source */
973 [0x0685] = 0x0080, /* R1669 - OUT1LMIX Input 3 Volume */
974 [0x0686] = 0x0000, /* R1670 - OUT1LMIX Input 4 Source */
975 [0x0687] = 0x0080, /* R1671 - OUT1LMIX Input 4 Volume */
976 [0x0688] = 0x0000, /* R1672 - OUT1RMIX Input 1 Source */
977 [0x0689] = 0x0080, /* R1673 - OUT1RMIX Input 1 Volume */
978 [0x068A] = 0x0000, /* R1674 - OUT1RMIX Input 2 Source */
979 [0x068B] = 0x0080, /* R1675 - OUT1RMIX Input 2 Volume */
980 [0x068C] = 0x0000, /* R1676 - OUT1RMIX Input 3 Source */
981 [0x068D] = 0x0080, /* R1677 - OUT1RMIX Input 3 Volume */
982 [0x068E] = 0x0000, /* R1678 - OUT1RMIX Input 4 Source */
983 [0x068F] = 0x0080, /* R1679 - OUT1RMIX Input 4 Volume */
984 [0x0690] = 0x0000, /* R1680 - OUT2LMIX Input 1 Source */
985 [0x0691] = 0x0080, /* R1681 - OUT2LMIX Input 1 Volume */
986 [0x0692] = 0x0000, /* R1682 - OUT2LMIX Input 2 Source */
987 [0x0693] = 0x0080, /* R1683 - OUT2LMIX Input 2 Volume */
988 [0x0694] = 0x0000, /* R1684 - OUT2LMIX Input 3 Source */
989 [0x0695] = 0x0080, /* R1685 - OUT2LMIX Input 3 Volume */
990 [0x0696] = 0x0000, /* R1686 - OUT2LMIX Input 4 Source */
991 [0x0697] = 0x0080, /* R1687 - OUT2LMIX Input 4 Volume */
992 [0x0698] = 0x0000, /* R1688 - OUT2RMIX Input 1 Source */
993 [0x0699] = 0x0080, /* R1689 - OUT2RMIX Input 1 Volume */
994 [0x069A] = 0x0000, /* R1690 - OUT2RMIX Input 2 Source */
995 [0x069B] = 0x0080, /* R1691 - OUT2RMIX Input 2 Volume */
996 [0x069C] = 0x0000, /* R1692 - OUT2RMIX Input 3 Source */
997 [0x069D] = 0x0080, /* R1693 - OUT2RMIX Input 3 Volume */
998 [0x069E] = 0x0000, /* R1694 - OUT2RMIX Input 4 Source */
999 [0x069F] = 0x0080, /* R1695 - OUT2RMIX Input 4 Volume */
1000 [0x06A0] = 0x0000, /* R1696 - OUT3LMIX Input 1 Source */
1001 [0x06A1] = 0x0080, /* R1697 - OUT3LMIX Input 1 Volume */
1002 [0x06A2] = 0x0000, /* R1698 - OUT3LMIX Input 2 Source */
1003 [0x06A3] = 0x0080, /* R1699 - OUT3LMIX Input 2 Volume */
1004 [0x06A4] = 0x0000, /* R1700 - OUT3LMIX Input 3 Source */
1005 [0x06A5] = 0x0080, /* R1701 - OUT3LMIX Input 3 Volume */
1006 [0x06A6] = 0x0000, /* R1702 - OUT3LMIX Input 4 Source */
1007 [0x06A7] = 0x0080, /* R1703 - OUT3LMIX Input 4 Volume */
1008 [0x06A8] = 0x0000, /* R1704 - OUT3RMIX Input 1 Source */
1009 [0x06A9] = 0x0080, /* R1705 - OUT3RMIX Input 1 Volume */
1010 [0x06AA] = 0x0000, /* R1706 - OUT3RMIX Input 2 Source */
1011 [0x06AB] = 0x0080, /* R1707 - OUT3RMIX Input 2 Volume */
1012 [0x06AC] = 0x0000, /* R1708 - OUT3RMIX Input 3 Source */
1013 [0x06AD] = 0x0080, /* R1709 - OUT3RMIX Input 3 Volume */
1014 [0x06AE] = 0x0000, /* R1710 - OUT3RMIX Input 4 Source */
1015 [0x06AF] = 0x0080, /* R1711 - OUT3RMIX Input 4 Volume */
1016 [0x06B0] = 0x0000, /* R1712 - OUT4LMIX Input 1 Source */
1017 [0x06B1] = 0x0080, /* R1713 - OUT4LMIX Input 1 Volume */
1018 [0x06B2] = 0x0000, /* R1714 - OUT4LMIX Input 2 Source */
1019 [0x06B3] = 0x0080, /* R1715 - OUT4LMIX Input 2 Volume */
1020 [0x06B4] = 0x0000, /* R1716 - OUT4LMIX Input 3 Source */
1021 [0x06B5] = 0x0080, /* R1717 - OUT4LMIX Input 3 Volume */
1022 [0x06B6] = 0x0000, /* R1718 - OUT4LMIX Input 4 Source */
1023 [0x06B7] = 0x0080, /* R1719 - OUT4LMIX Input 4 Volume */
1024 [0x06B8] = 0x0000, /* R1720 - OUT4RMIX Input 1 Source */
1025 [0x06B9] = 0x0080, /* R1721 - OUT4RMIX Input 1 Volume */
1026 [0x06BA] = 0x0000, /* R1722 - OUT4RMIX Input 2 Source */
1027 [0x06BB] = 0x0080, /* R1723 - OUT4RMIX Input 2 Volume */
1028 [0x06BC] = 0x0000, /* R1724 - OUT4RMIX Input 3 Source */
1029 [0x06BD] = 0x0080, /* R1725 - OUT4RMIX Input 3 Volume */
1030 [0x06BE] = 0x0000, /* R1726 - OUT4RMIX Input 4 Source */
1031 [0x06BF] = 0x0080, /* R1727 - OUT4RMIX Input 4 Volume */
1032 [0x06C0] = 0x0000, /* R1728 - OUT5LMIX Input 1 Source */
1033 [0x06C1] = 0x0080, /* R1729 - OUT5LMIX Input 1 Volume */
1034 [0x06C2] = 0x0000, /* R1730 - OUT5LMIX Input 2 Source */
1035 [0x06C3] = 0x0080, /* R1731 - OUT5LMIX Input 2 Volume */
1036 [0x06C4] = 0x0000, /* R1732 - OUT5LMIX Input 3 Source */
1037 [0x06C5] = 0x0080, /* R1733 - OUT5LMIX Input 3 Volume */
1038 [0x06C6] = 0x0000, /* R1734 - OUT5LMIX Input 4 Source */
1039 [0x06C7] = 0x0080, /* R1735 - OUT5LMIX Input 4 Volume */
1040 [0x06C8] = 0x0000, /* R1736 - OUT5RMIX Input 1 Source */
1041 [0x06C9] = 0x0080, /* R1737 - OUT5RMIX Input 1 Volume */
1042 [0x06CA] = 0x0000, /* R1738 - OUT5RMIX Input 2 Source */
1043 [0x06CB] = 0x0080, /* R1739 - OUT5RMIX Input 2 Volume */
1044 [0x06CC] = 0x0000, /* R1740 - OUT5RMIX Input 3 Source */
1045 [0x06CD] = 0x0080, /* R1741 - OUT5RMIX Input 3 Volume */
1046 [0x06CE] = 0x0000, /* R1742 - OUT5RMIX Input 4 Source */
1047 [0x06CF] = 0x0080, /* R1743 - OUT5RMIX Input 4 Volume */
1048 [0x06D0] = 0x0000, /* R1744 - OUT6LMIX Input 1 Source */
1049 [0x06D1] = 0x0080, /* R1745 - OUT6LMIX Input 1 Volume */
1050 [0x06D2] = 0x0000, /* R1746 - OUT6LMIX Input 2 Source */
1051 [0x06D3] = 0x0080, /* R1747 - OUT6LMIX Input 2 Volume */
1052 [0x06D4] = 0x0000, /* R1748 - OUT6LMIX Input 3 Source */
1053 [0x06D5] = 0x0080, /* R1749 - OUT6LMIX Input 3 Volume */
1054 [0x06D6] = 0x0000, /* R1750 - OUT6LMIX Input 4 Source */
1055 [0x06D7] = 0x0080, /* R1751 - OUT6LMIX Input 4 Volume */
1056 [0x06D8] = 0x0000, /* R1752 - OUT6RMIX Input 1 Source */
1057 [0x06D9] = 0x0080, /* R1753 - OUT6RMIX Input 1 Volume */
1058 [0x06DA] = 0x0000, /* R1754 - OUT6RMIX Input 2 Source */
1059 [0x06DB] = 0x0080, /* R1755 - OUT6RMIX Input 2 Volume */
1060 [0x06DC] = 0x0000, /* R1756 - OUT6RMIX Input 3 Source */
1061 [0x06DD] = 0x0080, /* R1757 - OUT6RMIX Input 3 Volume */
1062 [0x06DE] = 0x0000, /* R1758 - OUT6RMIX Input 4 Source */
1063 [0x06DF] = 0x0080, /* R1759 - OUT6RMIX Input 4 Volume */
1064 [0x0700] = 0x0000, /* R1792 - AIF1TX1MIX Input 1 Source */
1065 [0x0701] = 0x0080, /* R1793 - AIF1TX1MIX Input 1 Volume */
1066 [0x0702] = 0x0000, /* R1794 - AIF1TX1MIX Input 2 Source */
1067 [0x0703] = 0x0080, /* R1795 - AIF1TX1MIX Input 2 Volume */
1068 [0x0704] = 0x0000, /* R1796 - AIF1TX1MIX Input 3 Source */
1069 [0x0705] = 0x0080, /* R1797 - AIF1TX1MIX Input 3 Volume */
1070 [0x0706] = 0x0000, /* R1798 - AIF1TX1MIX Input 4 Source */
1071 [0x0707] = 0x0080, /* R1799 - AIF1TX1MIX Input 4 Volume */
1072 [0x0708] = 0x0000, /* R1800 - AIF1TX2MIX Input 1 Source */
1073 [0x0709] = 0x0080, /* R1801 - AIF1TX2MIX Input 1 Volume */
1074 [0x070A] = 0x0000, /* R1802 - AIF1TX2MIX Input 2 Source */
1075 [0x070B] = 0x0080, /* R1803 - AIF1TX2MIX Input 2 Volume */
1076 [0x070C] = 0x0000, /* R1804 - AIF1TX2MIX Input 3 Source */
1077 [0x070D] = 0x0080, /* R1805 - AIF1TX2MIX Input 3 Volume */
1078 [0x070E] = 0x0000, /* R1806 - AIF1TX2MIX Input 4 Source */
1079 [0x070F] = 0x0080, /* R1807 - AIF1TX2MIX Input 4 Volume */
1080 [0x0710] = 0x0000, /* R1808 - AIF1TX3MIX Input 1 Source */
1081 [0x0711] = 0x0080, /* R1809 - AIF1TX3MIX Input 1 Volume */
1082 [0x0712] = 0x0000, /* R1810 - AIF1TX3MIX Input 2 Source */
1083 [0x0713] = 0x0080, /* R1811 - AIF1TX3MIX Input 2 Volume */
1084 [0x0714] = 0x0000, /* R1812 - AIF1TX3MIX Input 3 Source */
1085 [0x0715] = 0x0080, /* R1813 - AIF1TX3MIX Input 3 Volume */
1086 [0x0716] = 0x0000, /* R1814 - AIF1TX3MIX Input 4 Source */
1087 [0x0717] = 0x0080, /* R1815 - AIF1TX3MIX Input 4 Volume */
1088 [0x0718] = 0x0000, /* R1816 - AIF1TX4MIX Input 1 Source */
1089 [0x0719] = 0x0080, /* R1817 - AIF1TX4MIX Input 1 Volume */
1090 [0x071A] = 0x0000, /* R1818 - AIF1TX4MIX Input 2 Source */
1091 [0x071B] = 0x0080, /* R1819 - AIF1TX4MIX Input 2 Volume */
1092 [0x071C] = 0x0000, /* R1820 - AIF1TX4MIX Input 3 Source */
1093 [0x071D] = 0x0080, /* R1821 - AIF1TX4MIX Input 3 Volume */
1094 [0x071E] = 0x0000, /* R1822 - AIF1TX4MIX Input 4 Source */
1095 [0x071F] = 0x0080, /* R1823 - AIF1TX4MIX Input 4 Volume */
1096 [0x0720] = 0x0000, /* R1824 - AIF1TX5MIX Input 1 Source */
1097 [0x0721] = 0x0080, /* R1825 - AIF1TX5MIX Input 1 Volume */
1098 [0x0722] = 0x0000, /* R1826 - AIF1TX5MIX Input 2 Source */
1099 [0x0723] = 0x0080, /* R1827 - AIF1TX5MIX Input 2 Volume */
1100 [0x0724] = 0x0000, /* R1828 - AIF1TX5MIX Input 3 Source */
1101 [0x0725] = 0x0080, /* R1829 - AIF1TX5MIX Input 3 Volume */
1102 [0x0726] = 0x0000, /* R1830 - AIF1TX5MIX Input 4 Source */
1103 [0x0727] = 0x0080, /* R1831 - AIF1TX5MIX Input 4 Volume */
1104 [0x0728] = 0x0000, /* R1832 - AIF1TX6MIX Input 1 Source */
1105 [0x0729] = 0x0080, /* R1833 - AIF1TX6MIX Input 1 Volume */
1106 [0x072A] = 0x0000, /* R1834 - AIF1TX6MIX Input 2 Source */
1107 [0x072B] = 0x0080, /* R1835 - AIF1TX6MIX Input 2 Volume */
1108 [0x072C] = 0x0000, /* R1836 - AIF1TX6MIX Input 3 Source */
1109 [0x072D] = 0x0080, /* R1837 - AIF1TX6MIX Input 3 Volume */
1110 [0x072E] = 0x0000, /* R1838 - AIF1TX6MIX Input 4 Source */
1111 [0x072F] = 0x0080, /* R1839 - AIF1TX6MIX Input 4 Volume */
1112 [0x0730] = 0x0000, /* R1840 - AIF1TX7MIX Input 1 Source */
1113 [0x0731] = 0x0080, /* R1841 - AIF1TX7MIX Input 1 Volume */
1114 [0x0732] = 0x0000, /* R1842 - AIF1TX7MIX Input 2 Source */
1115 [0x0733] = 0x0080, /* R1843 - AIF1TX7MIX Input 2 Volume */
1116 [0x0734] = 0x0000, /* R1844 - AIF1TX7MIX Input 3 Source */
1117 [0x0735] = 0x0080, /* R1845 - AIF1TX7MIX Input 3 Volume */
1118 [0x0736] = 0x0000, /* R1846 - AIF1TX7MIX Input 4 Source */
1119 [0x0737] = 0x0080, /* R1847 - AIF1TX7MIX Input 4 Volume */
1120 [0x0738] = 0x0000, /* R1848 - AIF1TX8MIX Input 1 Source */
1121 [0x0739] = 0x0080, /* R1849 - AIF1TX8MIX Input 1 Volume */
1122 [0x073A] = 0x0000, /* R1850 - AIF1TX8MIX Input 2 Source */
1123 [0x073B] = 0x0080, /* R1851 - AIF1TX8MIX Input 2 Volume */
1124 [0x073C] = 0x0000, /* R1852 - AIF1TX8MIX Input 3 Source */
1125 [0x073D] = 0x0080, /* R1853 - AIF1TX8MIX Input 3 Volume */
1126 [0x073E] = 0x0000, /* R1854 - AIF1TX8MIX Input 4 Source */
1127 [0x073F] = 0x0080, /* R1855 - AIF1TX8MIX Input 4 Volume */
1128 [0x0740] = 0x0000, /* R1856 - AIF2TX1MIX Input 1 Source */
1129 [0x0741] = 0x0080, /* R1857 - AIF2TX1MIX Input 1 Volume */
1130 [0x0742] = 0x0000, /* R1858 - AIF2TX1MIX Input 2 Source */
1131 [0x0743] = 0x0080, /* R1859 - AIF2TX1MIX Input 2 Volume */
1132 [0x0744] = 0x0000, /* R1860 - AIF2TX1MIX Input 3 Source */
1133 [0x0745] = 0x0080, /* R1861 - AIF2TX1MIX Input 3 Volume */
1134 [0x0746] = 0x0000, /* R1862 - AIF2TX1MIX Input 4 Source */
1135 [0x0747] = 0x0080, /* R1863 - AIF2TX1MIX Input 4 Volume */
1136 [0x0748] = 0x0000, /* R1864 - AIF2TX2MIX Input 1 Source */
1137 [0x0749] = 0x0080, /* R1865 - AIF2TX2MIX Input 1 Volume */
1138 [0x074A] = 0x0000, /* R1866 - AIF2TX2MIX Input 2 Source */
1139 [0x074B] = 0x0080, /* R1867 - AIF2TX2MIX Input 2 Volume */
1140 [0x074C] = 0x0000, /* R1868 - AIF2TX2MIX Input 3 Source */
1141 [0x074D] = 0x0080, /* R1869 - AIF2TX2MIX Input 3 Volume */
1142 [0x074E] = 0x0000, /* R1870 - AIF2TX2MIX Input 4 Source */
1143 [0x074F] = 0x0080, /* R1871 - AIF2TX2MIX Input 4 Volume */
1144 [0x0780] = 0x0000, /* R1920 - AIF3TX1MIX Input 1 Source */
1145 [0x0781] = 0x0080, /* R1921 - AIF3TX1MIX Input 1 Volume */
1146 [0x0782] = 0x0000, /* R1922 - AIF3TX1MIX Input 2 Source */
1147 [0x0783] = 0x0080, /* R1923 - AIF3TX1MIX Input 2 Volume */
1148 [0x0784] = 0x0000, /* R1924 - AIF3TX1MIX Input 3 Source */
1149 [0x0785] = 0x0080, /* R1925 - AIF3TX1MIX Input 3 Volume */
1150 [0x0786] = 0x0000, /* R1926 - AIF3TX1MIX Input 4 Source */
1151 [0x0787] = 0x0080, /* R1927 - AIF3TX1MIX Input 4 Volume */
1152 [0x0788] = 0x0000, /* R1928 - AIF3TX2MIX Input 1 Source */
1153 [0x0789] = 0x0080, /* R1929 - AIF3TX2MIX Input 1 Volume */
1154 [0x078A] = 0x0000, /* R1930 - AIF3TX2MIX Input 2 Source */
1155 [0x078B] = 0x0080, /* R1931 - AIF3TX2MIX Input 2 Volume */
1156 [0x078C] = 0x0000, /* R1932 - AIF3TX2MIX Input 3 Source */
1157 [0x078D] = 0x0080, /* R1933 - AIF3TX2MIX Input 3 Volume */
1158 [0x078E] = 0x0000, /* R1934 - AIF3TX2MIX Input 4 Source */
1159 [0x078F] = 0x0080, /* R1935 - AIF3TX2MIX Input 4 Volume */
1160 [0x0880] = 0x0000, /* R2176 - EQ1MIX Input 1 Source */
1161 [0x0881] = 0x0080, /* R2177 - EQ1MIX Input 1 Volume */
1162 [0x0882] = 0x0000, /* R2178 - EQ1MIX Input 2 Source */
1163 [0x0883] = 0x0080, /* R2179 - EQ1MIX Input 2 Volume */
1164 [0x0884] = 0x0000, /* R2180 - EQ1MIX Input 3 Source */
1165 [0x0885] = 0x0080, /* R2181 - EQ1MIX Input 3 Volume */
1166 [0x0886] = 0x0000, /* R2182 - EQ1MIX Input 4 Source */
1167 [0x0887] = 0x0080, /* R2183 - EQ1MIX Input 4 Volume */
1168 [0x0888] = 0x0000, /* R2184 - EQ2MIX Input 1 Source */
1169 [0x0889] = 0x0080, /* R2185 - EQ2MIX Input 1 Volume */
1170 [0x088A] = 0x0000, /* R2186 - EQ2MIX Input 2 Source */
1171 [0x088B] = 0x0080, /* R2187 - EQ2MIX Input 2 Volume */
1172 [0x088C] = 0x0000, /* R2188 - EQ2MIX Input 3 Source */
1173 [0x088D] = 0x0080, /* R2189 - EQ2MIX Input 3 Volume */
1174 [0x088E] = 0x0000, /* R2190 - EQ2MIX Input 4 Source */
1175 [0x088F] = 0x0080, /* R2191 - EQ2MIX Input 4 Volume */
1176 [0x0890] = 0x0000, /* R2192 - EQ3MIX Input 1 Source */
1177 [0x0891] = 0x0080, /* R2193 - EQ3MIX Input 1 Volume */
1178 [0x0892] = 0x0000, /* R2194 - EQ3MIX Input 2 Source */
1179 [0x0893] = 0x0080, /* R2195 - EQ3MIX Input 2 Volume */
1180 [0x0894] = 0x0000, /* R2196 - EQ3MIX Input 3 Source */
1181 [0x0895] = 0x0080, /* R2197 - EQ3MIX Input 3 Volume */
1182 [0x0896] = 0x0000, /* R2198 - EQ3MIX Input 4 Source */
1183 [0x0897] = 0x0080, /* R2199 - EQ3MIX Input 4 Volume */
1184 [0x0898] = 0x0000, /* R2200 - EQ4MIX Input 1 Source */
1185 [0x0899] = 0x0080, /* R2201 - EQ4MIX Input 1 Volume */
1186 [0x089A] = 0x0000, /* R2202 - EQ4MIX Input 2 Source */
1187 [0x089B] = 0x0080, /* R2203 - EQ4MIX Input 2 Volume */
1188 [0x089C] = 0x0000, /* R2204 - EQ4MIX Input 3 Source */
1189 [0x089D] = 0x0080, /* R2205 - EQ4MIX Input 3 Volume */
1190 [0x089E] = 0x0000, /* R2206 - EQ4MIX Input 4 Source */
1191 [0x089F] = 0x0080, /* R2207 - EQ4MIX Input 4 Volume */
1192 [0x08C0] = 0x0000, /* R2240 - DRC1LMIX Input 1 Source */
1193 [0x08C1] = 0x0080, /* R2241 - DRC1LMIX Input 1 Volume */
1194 [0x08C2] = 0x0000, /* R2242 - DRC1LMIX Input 2 Source */
1195 [0x08C3] = 0x0080, /* R2243 - DRC1LMIX Input 2 Volume */
1196 [0x08C4] = 0x0000, /* R2244 - DRC1LMIX Input 3 Source */
1197 [0x08C5] = 0x0080, /* R2245 - DRC1LMIX Input 3 Volume */
1198 [0x08C6] = 0x0000, /* R2246 - DRC1LMIX Input 4 Source */
1199 [0x08C7] = 0x0080, /* R2247 - DRC1LMIX Input 4 Volume */
1200 [0x08C8] = 0x0000, /* R2248 - DRC1RMIX Input 1 Source */
1201 [0x08C9] = 0x0080, /* R2249 - DRC1RMIX Input 1 Volume */
1202 [0x08CA] = 0x0000, /* R2250 - DRC1RMIX Input 2 Source */
1203 [0x08CB] = 0x0080, /* R2251 - DRC1RMIX Input 2 Volume */
1204 [0x08CC] = 0x0000, /* R2252 - DRC1RMIX Input 3 Source */
1205 [0x08CD] = 0x0080, /* R2253 - DRC1RMIX Input 3 Volume */
1206 [0x08CE] = 0x0000, /* R2254 - DRC1RMIX Input 4 Source */
1207 [0x08CF] = 0x0080, /* R2255 - DRC1RMIX Input 4 Volume */
1208 [0x0900] = 0x0000, /* R2304 - HPLP1MIX Input 1 Source */
1209 [0x0901] = 0x0080, /* R2305 - HPLP1MIX Input 1 Volume */
1210 [0x0902] = 0x0000, /* R2306 - HPLP1MIX Input 2 Source */
1211 [0x0903] = 0x0080, /* R2307 - HPLP1MIX Input 2 Volume */
1212 [0x0904] = 0x0000, /* R2308 - HPLP1MIX Input 3 Source */
1213 [0x0905] = 0x0080, /* R2309 - HPLP1MIX Input 3 Volume */
1214 [0x0906] = 0x0000, /* R2310 - HPLP1MIX Input 4 Source */
1215 [0x0907] = 0x0080, /* R2311 - HPLP1MIX Input 4 Volume */
1216 [0x0908] = 0x0000, /* R2312 - HPLP2MIX Input 1 Source */
1217 [0x0909] = 0x0080, /* R2313 - HPLP2MIX Input 1 Volume */
1218 [0x090A] = 0x0000, /* R2314 - HPLP2MIX Input 2 Source */
1219 [0x090B] = 0x0080, /* R2315 - HPLP2MIX Input 2 Volume */
1220 [0x090C] = 0x0000, /* R2316 - HPLP2MIX Input 3 Source */
1221 [0x090D] = 0x0080, /* R2317 - HPLP2MIX Input 3 Volume */
1222 [0x090E] = 0x0000, /* R2318 - HPLP2MIX Input 4 Source */
1223 [0x090F] = 0x0080, /* R2319 - HPLP2MIX Input 4 Volume */
1224 [0x0910] = 0x0000, /* R2320 - HPLP3MIX Input 1 Source */
1225 [0x0911] = 0x0080, /* R2321 - HPLP3MIX Input 1 Volume */
1226 [0x0912] = 0x0000, /* R2322 - HPLP3MIX Input 2 Source */
1227 [0x0913] = 0x0080, /* R2323 - HPLP3MIX Input 2 Volume */
1228 [0x0914] = 0x0000, /* R2324 - HPLP3MIX Input 3 Source */
1229 [0x0915] = 0x0080, /* R2325 - HPLP3MIX Input 3 Volume */
1230 [0x0916] = 0x0000, /* R2326 - HPLP3MIX Input 4 Source */
1231 [0x0917] = 0x0080, /* R2327 - HPLP3MIX Input 4 Volume */
1232 [0x0918] = 0x0000, /* R2328 - HPLP4MIX Input 1 Source */
1233 [0x0919] = 0x0080, /* R2329 - HPLP4MIX Input 1 Volume */
1234 [0x091A] = 0x0000, /* R2330 - HPLP4MIX Input 2 Source */
1235 [0x091B] = 0x0080, /* R2331 - HPLP4MIX Input 2 Volume */
1236 [0x091C] = 0x0000, /* R2332 - HPLP4MIX Input 3 Source */
1237 [0x091D] = 0x0080, /* R2333 - HPLP4MIX Input 3 Volume */
1238 [0x091E] = 0x0000, /* R2334 - HPLP4MIX Input 4 Source */
1239 [0x091F] = 0x0080, /* R2335 - HPLP4MIX Input 4 Volume */
1240 [0x0940] = 0x0000, /* R2368 - DSP1LMIX Input 1 Source */
1241 [0x0941] = 0x0080, /* R2369 - DSP1LMIX Input 1 Volume */
1242 [0x0942] = 0x0000, /* R2370 - DSP1LMIX Input 2 Source */
1243 [0x0943] = 0x0080, /* R2371 - DSP1LMIX Input 2 Volume */
1244 [0x0944] = 0x0000, /* R2372 - DSP1LMIX Input 3 Source */
1245 [0x0945] = 0x0080, /* R2373 - DSP1LMIX Input 3 Volume */
1246 [0x0946] = 0x0000, /* R2374 - DSP1LMIX Input 4 Source */
1247 [0x0947] = 0x0080, /* R2375 - DSP1LMIX Input 4 Volume */
1248 [0x0948] = 0x0000, /* R2376 - DSP1RMIX Input 1 Source */
1249 [0x0949] = 0x0080, /* R2377 - DSP1RMIX Input 1 Volume */
1250 [0x094A] = 0x0000, /* R2378 - DSP1RMIX Input 2 Source */
1251 [0x094B] = 0x0080, /* R2379 - DSP1RMIX Input 2 Volume */
1252 [0x094C] = 0x0000, /* R2380 - DSP1RMIX Input 3 Source */
1253 [0x094D] = 0x0080, /* R2381 - DSP1RMIX Input 3 Volume */
1254 [0x094E] = 0x0000, /* R2382 - DSP1RMIX Input 4 Source */
1255 [0x094F] = 0x0080, /* R2383 - DSP1RMIX Input 4 Volume */
1256 [0x0950] = 0x0000, /* R2384 - DSP1AUX1MIX Input 1 Source */
1257 [0x0958] = 0x0000, /* R2392 - DSP1AUX2MIX Input 1 Source */
1258 [0x0960] = 0x0000, /* R2400 - DSP1AUX3MIX Input 1 Source */
1259 [0x0968] = 0x0000, /* R2408 - DSP1AUX4MIX Input 1 Source */
1260 [0x0970] = 0x0000, /* R2416 - DSP1AUX5MIX Input 1 Source */
1261 [0x0978] = 0x0000, /* R2424 - DSP1AUX6MIX Input 1 Source */
1262 [0x0980] = 0x0000, /* R2432 - DSP2LMIX Input 1 Source */
1263 [0x0981] = 0x0080, /* R2433 - DSP2LMIX Input 1 Volume */
1264 [0x0982] = 0x0000, /* R2434 - DSP2LMIX Input 2 Source */
1265 [0x0983] = 0x0080, /* R2435 - DSP2LMIX Input 2 Volume */
1266 [0x0984] = 0x0000, /* R2436 - DSP2LMIX Input 3 Source */
1267 [0x0985] = 0x0080, /* R2437 - DSP2LMIX Input 3 Volume */
1268 [0x0986] = 0x0000, /* R2438 - DSP2LMIX Input 4 Source */
1269 [0x0987] = 0x0080, /* R2439 - DSP2LMIX Input 4 Volume */
1270 [0x0988] = 0x0000, /* R2440 - DSP2RMIX Input 1 Source */
1271 [0x0989] = 0x0080, /* R2441 - DSP2RMIX Input 1 Volume */
1272 [0x098A] = 0x0000, /* R2442 - DSP2RMIX Input 2 Source */
1273 [0x098B] = 0x0080, /* R2443 - DSP2RMIX Input 2 Volume */
1274 [0x098C] = 0x0000, /* R2444 - DSP2RMIX Input 3 Source */
1275 [0x098D] = 0x0080, /* R2445 - DSP2RMIX Input 3 Volume */
1276 [0x098E] = 0x0000, /* R2446 - DSP2RMIX Input 4 Source */
1277 [0x098F] = 0x0080, /* R2447 - DSP2RMIX Input 4 Volume */
1278 [0x0990] = 0x0000, /* R2448 - DSP2AUX1MIX Input 1 Source */
1279 [0x0998] = 0x0000, /* R2456 - DSP2AUX2MIX Input 1 Source */
1280 [0x09A0] = 0x0000, /* R2464 - DSP2AUX3MIX Input 1 Source */
1281 [0x09A8] = 0x0000, /* R2472 - DSP2AUX4MIX Input 1 Source */
1282 [0x09B0] = 0x0000, /* R2480 - DSP2AUX5MIX Input 1 Source */
1283 [0x09B8] = 0x0000, /* R2488 - DSP2AUX6MIX Input 1 Source */
1284 [0x09C0] = 0x0000, /* R2496 - DSP3LMIX Input 1 Source */
1285 [0x09C1] = 0x0080, /* R2497 - DSP3LMIX Input 1 Volume */
1286 [0x09C2] = 0x0000, /* R2498 - DSP3LMIX Input 2 Source */
1287 [0x09C3] = 0x0080, /* R2499 - DSP3LMIX Input 2 Volume */
1288 [0x09C4] = 0x0000, /* R2500 - DSP3LMIX Input 3 Source */
1289 [0x09C5] = 0x0080, /* R2501 - DSP3LMIX Input 3 Volume */
1290 [0x09C6] = 0x0000, /* R2502 - DSP3LMIX Input 4 Source */
1291 [0x09C7] = 0x0080, /* R2503 - DSP3LMIX Input 4 Volume */
1292 [0x09C8] = 0x0000, /* R2504 - DSP3RMIX Input 1 Source */
1293 [0x09C9] = 0x0080, /* R2505 - DSP3RMIX Input 1 Volume */
1294 [0x09CA] = 0x0000, /* R2506 - DSP3RMIX Input 2 Source */
1295 [0x09CB] = 0x0080, /* R2507 - DSP3RMIX Input 2 Volume */
1296 [0x09CC] = 0x0000, /* R2508 - DSP3RMIX Input 3 Source */
1297 [0x09CD] = 0x0080, /* R2509 - DSP3RMIX Input 3 Volume */
1298 [0x09CE] = 0x0000, /* R2510 - DSP3RMIX Input 4 Source */
1299 [0x09CF] = 0x0080, /* R2511 - DSP3RMIX Input 4 Volume */
1300 [0x09D0] = 0x0000, /* R2512 - DSP3AUX1MIX Input 1 Source */
1301 [0x09D8] = 0x0000, /* R2520 - DSP3AUX2MIX Input 1 Source */
1302 [0x09E0] = 0x0000, /* R2528 - DSP3AUX3MIX Input 1 Source */
1303 [0x09E8] = 0x0000, /* R2536 - DSP3AUX4MIX Input 1 Source */
1304 [0x09F0] = 0x0000, /* R2544 - DSP3AUX5MIX Input 1 Source */
1305 [0x09F8] = 0x0000, /* R2552 - DSP3AUX6MIX Input 1 Source */
1306 [0x0A80] = 0x0000, /* R2688 - ASRC1LMIX Input 1 Source */
1307 [0x0A88] = 0x0000, /* R2696 - ASRC1RMIX Input 1 Source */
1308 [0x0A90] = 0x0000, /* R2704 - ASRC2LMIX Input 1 Source */
1309 [0x0A98] = 0x0000, /* R2712 - ASRC2RMIX Input 1 Source */
1310 [0x0B00] = 0x0000, /* R2816 - ISRC1DEC1MIX Input 1 Source */
1311 [0x0B08] = 0x0000, /* R2824 - ISRC1DEC2MIX Input 1 Source */
1312 [0x0B10] = 0x0000, /* R2832 - ISRC1DEC3MIX Input 1 Source */
1313 [0x0B18] = 0x0000, /* R2840 - ISRC1DEC4MIX Input 1 Source */
1314 [0x0B20] = 0x0000, /* R2848 - ISRC1INT1MIX Input 1 Source */
1315 [0x0B28] = 0x0000, /* R2856 - ISRC1INT2MIX Input 1 Source */
1316 [0x0B30] = 0x0000, /* R2864 - ISRC1INT3MIX Input 1 Source */
1317 [0x0B38] = 0x0000, /* R2872 - ISRC1INT4MIX Input 1 Source */
1318 [0x0B40] = 0x0000, /* R2880 - ISRC2DEC1MIX Input 1 Source */
1319 [0x0B48] = 0x0000, /* R2888 - ISRC2DEC2MIX Input 1 Source */
1320 [0x0B50] = 0x0000, /* R2896 - ISRC2DEC3MIX Input 1 Source */
1321 [0x0B58] = 0x0000, /* R2904 - ISRC2DEC4MIX Input 1 Source */
1322 [0x0B60] = 0x0000, /* R2912 - ISRC2INT1MIX Input 1 Source */
1323 [0x0B68] = 0x0000, /* R2920 - ISRC2INT2MIX Input 1 Source */
1324 [0x0B70] = 0x0000, /* R2928 - ISRC2INT3MIX Input 1 Source */
1325 [0x0B78] = 0x0000, /* R2936 - ISRC2INT4MIX Input 1 Source */
1326 [0x0C00] = 0xA001, /* R3072 - GPIO CTRL 1 */
1327 [0x0C01] = 0xA001, /* R3073 - GPIO CTRL 2 */
1328 [0x0C02] = 0xA001, /* R3074 - GPIO CTRL 3 */
1329 [0x0C03] = 0xA001, /* R3075 - GPIO CTRL 4 */
1330 [0x0C04] = 0xA001, /* R3076 - GPIO CTRL 5 */
1331 [0x0C05] = 0xA001, /* R3077 - GPIO CTRL 6 */
1332 [0x0C23] = 0x4003, /* R3107 - Misc Pad Ctrl 1 */
1333 [0x0C24] = 0x0000, /* R3108 - Misc Pad Ctrl 2 */
1334 [0x0C25] = 0x0000, /* R3109 - Misc Pad Ctrl 3 */
1335 [0x0C26] = 0x0000, /* R3110 - Misc Pad Ctrl 4 */
1336 [0x0C27] = 0x0000, /* R3111 - Misc Pad Ctrl 5 */
1337 [0x0C28] = 0x0000, /* R3112 - Misc GPIO 1 */
1338 [0x0D00] = 0x0000, /* R3328 - Interrupt Status 1 */
1339 [0x0D01] = 0x0000, /* R3329 - Interrupt Status 2 */
1340 [0x0D02] = 0x0000, /* R3330 - Interrupt Status 3 */
1341 [0x0D03] = 0x0000, /* R3331 - Interrupt Status 4 */
1342 [0x0D04] = 0x0000, /* R3332 - Interrupt Raw Status 2 */
1343 [0x0D05] = 0x0000, /* R3333 - Interrupt Raw Status 3 */
1344 [0x0D06] = 0x0000, /* R3334 - Interrupt Raw Status 4 */
1345 [0x0D07] = 0xFFFF, /* R3335 - Interrupt Status 1 Mask */
1346 [0x0D08] = 0xFFFF, /* R3336 - Interrupt Status 2 Mask */
1347 [0x0D09] = 0xFFFF, /* R3337 - Interrupt Status 3 Mask */
1348 [0x0D0A] = 0xFFFF, /* R3338 - Interrupt Status 4 Mask */
1349 [0x0D1F] = 0x0000, /* R3359 - Interrupt Control */
1350 [0x0D20] = 0xFFFF, /* R3360 - IRQ Debounce 1 */
1351 [0x0D21] = 0xFFFF, /* R3361 - IRQ Debounce 2 */
1352 [0x0E00] = 0x0000, /* R3584 - FX_Ctrl */
1353 [0x0E10] = 0x6318, /* R3600 - EQ1_1 */
1354 [0x0E11] = 0x6300, /* R3601 - EQ1_2 */
1355 [0x0E12] = 0x0FC8, /* R3602 - EQ1_3 */
1356 [0x0E13] = 0x03FE, /* R3603 - EQ1_4 */
1357 [0x0E14] = 0x00E0, /* R3604 - EQ1_5 */
1358 [0x0E15] = 0x1EC4, /* R3605 - EQ1_6 */
1359 [0x0E16] = 0xF136, /* R3606 - EQ1_7 */
1360 [0x0E17] = 0x0409, /* R3607 - EQ1_8 */
1361 [0x0E18] = 0x04CC, /* R3608 - EQ1_9 */
1362 [0x0E19] = 0x1C9B, /* R3609 - EQ1_10 */
1363 [0x0E1A] = 0xF337, /* R3610 - EQ1_11 */
1364 [0x0E1B] = 0x040B, /* R3611 - EQ1_12 */
1365 [0x0E1C] = 0x0CBB, /* R3612 - EQ1_13 */
1366 [0x0E1D] = 0x16F8, /* R3613 - EQ1_14 */
1367 [0x0E1E] = 0xF7D9, /* R3614 - EQ1_15 */
1368 [0x0E1F] = 0x040A, /* R3615 - EQ1_16 */
1369 [0x0E20] = 0x1F14, /* R3616 - EQ1_17 */
1370 [0x0E21] = 0x058C, /* R3617 - EQ1_18 */
1371 [0x0E22] = 0x0563, /* R3618 - EQ1_19 */
1372 [0x0E23] = 0x4000, /* R3619 - EQ1_20 */
1373 [0x0E26] = 0x6318, /* R3622 - EQ2_1 */
1374 [0x0E27] = 0x6300, /* R3623 - EQ2_2 */
1375 [0x0E28] = 0x0FC8, /* R3624 - EQ2_3 */
1376 [0x0E29] = 0x03FE, /* R3625 - EQ2_4 */
1377 [0x0E2A] = 0x00E0, /* R3626 - EQ2_5 */
1378 [0x0E2B] = 0x1EC4, /* R3627 - EQ2_6 */
1379 [0x0E2C] = 0xF136, /* R3628 - EQ2_7 */
1380 [0x0E2D] = 0x0409, /* R3629 - EQ2_8 */
1381 [0x0E2E] = 0x04CC, /* R3630 - EQ2_9 */
1382 [0x0E2F] = 0x1C9B, /* R3631 - EQ2_10 */
1383 [0x0E30] = 0xF337, /* R3632 - EQ2_11 */
1384 [0x0E31] = 0x040B, /* R3633 - EQ2_12 */
1385 [0x0E32] = 0x0CBB, /* R3634 - EQ2_13 */
1386 [0x0E33] = 0x16F8, /* R3635 - EQ2_14 */
1387 [0x0E34] = 0xF7D9, /* R3636 - EQ2_15 */
1388 [0x0E35] = 0x040A, /* R3637 - EQ2_16 */
1389 [0x0E36] = 0x1F14, /* R3638 - EQ2_17 */
1390 [0x0E37] = 0x058C, /* R3639 - EQ2_18 */
1391 [0x0E38] = 0x0563, /* R3640 - EQ2_19 */
1392 [0x0E39] = 0x4000, /* R3641 - EQ2_20 */
1393 [0x0E3C] = 0x6318, /* R3644 - EQ3_1 */
1394 [0x0E3D] = 0x6300, /* R3645 - EQ3_2 */
1395 [0x0E3E] = 0x0FC8, /* R3646 - EQ3_3 */
1396 [0x0E3F] = 0x03FE, /* R3647 - EQ3_4 */
1397 [0x0E40] = 0x00E0, /* R3648 - EQ3_5 */
1398 [0x0E41] = 0x1EC4, /* R3649 - EQ3_6 */
1399 [0x0E42] = 0xF136, /* R3650 - EQ3_7 */
1400 [0x0E43] = 0x0409, /* R3651 - EQ3_8 */
1401 [0x0E44] = 0x04CC, /* R3652 - EQ3_9 */
1402 [0x0E45] = 0x1C9B, /* R3653 - EQ3_10 */
1403 [0x0E46] = 0xF337, /* R3654 - EQ3_11 */
1404 [0x0E47] = 0x040B, /* R3655 - EQ3_12 */
1405 [0x0E48] = 0x0CBB, /* R3656 - EQ3_13 */
1406 [0x0E49] = 0x16F8, /* R3657 - EQ3_14 */
1407 [0x0E4A] = 0xF7D9, /* R3658 - EQ3_15 */
1408 [0x0E4B] = 0x040A, /* R3659 - EQ3_16 */
1409 [0x0E4C] = 0x1F14, /* R3660 - EQ3_17 */
1410 [0x0E4D] = 0x058C, /* R3661 - EQ3_18 */
1411 [0x0E4E] = 0x0563, /* R3662 - EQ3_19 */
1412 [0x0E4F] = 0x4000, /* R3663 - EQ3_20 */
1413 [0x0E52] = 0x6318, /* R3666 - EQ4_1 */
1414 [0x0E53] = 0x6300, /* R3667 - EQ4_2 */
1415 [0x0E54] = 0x0FC8, /* R3668 - EQ4_3 */
1416 [0x0E55] = 0x03FE, /* R3669 - EQ4_4 */
1417 [0x0E56] = 0x00E0, /* R3670 - EQ4_5 */
1418 [0x0E57] = 0x1EC4, /* R3671 - EQ4_6 */
1419 [0x0E58] = 0xF136, /* R3672 - EQ4_7 */
1420 [0x0E59] = 0x0409, /* R3673 - EQ4_8 */
1421 [0x0E5A] = 0x04CC, /* R3674 - EQ4_9 */
1422 [0x0E5B] = 0x1C9B, /* R3675 - EQ4_10 */
1423 [0x0E5C] = 0xF337, /* R3676 - EQ4_11 */
1424 [0x0E5D] = 0x040B, /* R3677 - EQ4_12 */
1425 [0x0E5E] = 0x0CBB, /* R3678 - EQ4_13 */
1426 [0x0E5F] = 0x16F8, /* R3679 - EQ4_14 */
1427 [0x0E60] = 0xF7D9, /* R3680 - EQ4_15 */
1428 [0x0E61] = 0x040A, /* R3681 - EQ4_16 */
1429 [0x0E62] = 0x1F14, /* R3682 - EQ4_17 */
1430 [0x0E63] = 0x058C, /* R3683 - EQ4_18 */
1431 [0x0E64] = 0x0563, /* R3684 - EQ4_19 */
1432 [0x0E65] = 0x4000, /* R3685 - EQ4_20 */
1433 [0x0E80] = 0x0018, /* R3712 - DRC1 ctrl1 */
1434 [0x0E81] = 0x0933, /* R3713 - DRC1 ctrl2 */
1435 [0x0E82] = 0x0018, /* R3714 - DRC1 ctrl3 */
1436 [0x0E83] = 0x0000, /* R3715 - DRC1 ctrl4 */
1437 [0x0E84] = 0x0000, /* R3716 - DRC1 ctrl5 */
1438 [0x0EC0] = 0x0000, /* R3776 - HPLPF1_1 */
1439 [0x0EC1] = 0x0000, /* R3777 - HPLPF1_2 */
1440 [0x0EC4] = 0x0000, /* R3780 - HPLPF2_1 */
1441 [0x0EC5] = 0x0000, /* R3781 - HPLPF2_2 */
1442 [0x0EC8] = 0x0000, /* R3784 - HPLPF3_1 */
1443 [0x0EC9] = 0x0000, /* R3785 - HPLPF3_2 */
1444 [0x0ECC] = 0x0000, /* R3788 - HPLPF4_1 */
1445 [0x0ECD] = 0x0000, /* R3789 - HPLPF4_2 */
1446 [0x4000] = 0x0000, /* R16384 - DSP1 DM 0 */
1447 [0x4001] = 0x0000, /* R16385 - DSP1 DM 1 */
1448 [0x4002] = 0x0000, /* R16386 - DSP1 DM 2 */
1449 [0x4003] = 0x0000, /* R16387 - DSP1 DM 3 */
1450 [0x41FC] = 0x0000, /* R16892 - DSP1 DM 508 */
1451 [0x41FD] = 0x0000, /* R16893 - DSP1 DM 509 */
1452 [0x41FE] = 0x0000, /* R16894 - DSP1 DM 510 */
1453 [0x41FF] = 0x0000, /* R16895 - DSP1 DM 511 */
1454 [0x4800] = 0x0000, /* R18432 - DSP1 PM 0 */
1455 [0x4801] = 0x0000, /* R18433 - DSP1 PM 1 */
1456 [0x4802] = 0x0000, /* R18434 - DSP1 PM 2 */
1457 [0x4803] = 0x0000, /* R18435 - DSP1 PM 3 */
1458 [0x4804] = 0x0000, /* R18436 - DSP1 PM 4 */
1459 [0x4805] = 0x0000, /* R18437 - DSP1 PM 5 */
1460 [0x4DFA] = 0x0000, /* R19962 - DSP1 PM 1530 */
1461 [0x4DFB] = 0x0000, /* R19963 - DSP1 PM 1531 */
1462 [0x4DFC] = 0x0000, /* R19964 - DSP1 PM 1532 */
1463 [0x4DFD] = 0x0000, /* R19965 - DSP1 PM 1533 */
1464 [0x4DFE] = 0x0000, /* R19966 - DSP1 PM 1534 */
1465 [0x4DFF] = 0x0000, /* R19967 - DSP1 PM 1535 */
1466 [0x5000] = 0x0000, /* R20480 - DSP1 ZM 0 */
1467 [0x5001] = 0x0000, /* R20481 - DSP1 ZM 1 */
1468 [0x5002] = 0x0000, /* R20482 - DSP1 ZM 2 */
1469 [0x5003] = 0x0000, /* R20483 - DSP1 ZM 3 */
1470 [0x57FC] = 0x0000, /* R22524 - DSP1 ZM 2044 */
1471 [0x57FD] = 0x0000, /* R22525 - DSP1 ZM 2045 */
1472 [0x57FE] = 0x0000, /* R22526 - DSP1 ZM 2046 */
1473 [0x57FF] = 0x0000, /* R22527 - DSP1 ZM 2047 */
1474 [0x6000] = 0x0000, /* R24576 - DSP2 DM 0 */
1475 [0x6001] = 0x0000, /* R24577 - DSP2 DM 1 */
1476 [0x6002] = 0x0000, /* R24578 - DSP2 DM 2 */
1477 [0x6003] = 0x0000, /* R24579 - DSP2 DM 3 */
1478 [0x61FC] = 0x0000, /* R25084 - DSP2 DM 508 */
1479 [0x61FD] = 0x0000, /* R25085 - DSP2 DM 509 */
1480 [0x61FE] = 0x0000, /* R25086 - DSP2 DM 510 */
1481 [0x61FF] = 0x0000, /* R25087 - DSP2 DM 511 */
1482 [0x6800] = 0x0000, /* R26624 - DSP2 PM 0 */
1483 [0x6801] = 0x0000, /* R26625 - DSP2 PM 1 */
1484 [0x6802] = 0x0000, /* R26626 - DSP2 PM 2 */
1485 [0x6803] = 0x0000, /* R26627 - DSP2 PM 3 */
1486 [0x6804] = 0x0000, /* R26628 - DSP2 PM 4 */
1487 [0x6805] = 0x0000, /* R26629 - DSP2 PM 5 */
1488 [0x6DFA] = 0x0000, /* R28154 - DSP2 PM 1530 */
1489 [0x6DFB] = 0x0000, /* R28155 - DSP2 PM 1531 */
1490 [0x6DFC] = 0x0000, /* R28156 - DSP2 PM 1532 */
1491 [0x6DFD] = 0x0000, /* R28157 - DSP2 PM 1533 */
1492 [0x6DFE] = 0x0000, /* R28158 - DSP2 PM 1534 */
1493 [0x6DFF] = 0x0000, /* R28159 - DSP2 PM 1535 */
1494 [0x7000] = 0x0000, /* R28672 - DSP2 ZM 0 */
1495 [0x7001] = 0x0000, /* R28673 - DSP2 ZM 1 */
1496 [0x7002] = 0x0000, /* R28674 - DSP2 ZM 2 */
1497 [0x7003] = 0x0000, /* R28675 - DSP2 ZM 3 */
1498 [0x77FC] = 0x0000, /* R30716 - DSP2 ZM 2044 */
1499 [0x77FD] = 0x0000, /* R30717 - DSP2 ZM 2045 */
1500 [0x77FE] = 0x0000, /* R30718 - DSP2 ZM 2046 */
1501 [0x77FF] = 0x0000, /* R30719 - DSP2 ZM 2047 */
1502 [0x8000] = 0x0000, /* R32768 - DSP3 DM 0 */
1503 [0x8001] = 0x0000, /* R32769 - DSP3 DM 1 */
1504 [0x8002] = 0x0000, /* R32770 - DSP3 DM 2 */
1505 [0x8003] = 0x0000, /* R32771 - DSP3 DM 3 */
1506 [0x81FC] = 0x0000, /* R33276 - DSP3 DM 508 */
1507 [0x81FD] = 0x0000, /* R33277 - DSP3 DM 509 */
1508 [0x81FE] = 0x0000, /* R33278 - DSP3 DM 510 */
1509 [0x81FF] = 0x0000, /* R33279 - DSP3 DM 511 */
1510 [0x8800] = 0x0000, /* R34816 - DSP3 PM 0 */
1511 [0x8801] = 0x0000, /* R34817 - DSP3 PM 1 */
1512 [0x8802] = 0x0000, /* R34818 - DSP3 PM 2 */
1513 [0x8803] = 0x0000, /* R34819 - DSP3 PM 3 */
1514 [0x8804] = 0x0000, /* R34820 - DSP3 PM 4 */
1515 [0x8805] = 0x0000, /* R34821 - DSP3 PM 5 */
1516 [0x8DFA] = 0x0000, /* R36346 - DSP3 PM 1530 */
1517 [0x8DFB] = 0x0000, /* R36347 - DSP3 PM 1531 */
1518 [0x8DFC] = 0x0000, /* R36348 - DSP3 PM 1532 */
1519 [0x8DFD] = 0x0000, /* R36349 - DSP3 PM 1533 */
1520 [0x8DFE] = 0x0000, /* R36350 - DSP3 PM 1534 */
1521 [0x8DFF] = 0x0000, /* R36351 - DSP3 PM 1535 */
1522 [0x9000] = 0x0000, /* R36864 - DSP3 ZM 0 */
1523 [0x9001] = 0x0000, /* R36865 - DSP3 ZM 1 */
1524 [0x9002] = 0x0000, /* R36866 - DSP3 ZM 2 */
1525 [0x9003] = 0x0000, /* R36867 - DSP3 ZM 3 */
1526 [0x97FC] = 0x0000, /* R38908 - DSP3 ZM 2044 */
1527 [0x97FD] = 0x0000, /* R38909 - DSP3 ZM 2045 */
1528 [0x97FE] = 0x0000, /* R38910 - DSP3 ZM 2046 */
1529 [0x97FF] = 0x0000 /* R38911 - DSP3 ZM 2047 */
1530};
diff --git a/sound/soc/codecs/wm5100.c b/sound/soc/codecs/wm5100.c
new file mode 100644
index 000000000000..576081a2de10
--- /dev/null
+++ b/sound/soc/codecs/wm5100.c
@@ -0,0 +1,2560 @@
1/*
2 * wm5100.c -- WM5100 ALSA SoC Audio driver
3 *
4 * Copyright 2011 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/gcd.h>
19#include <linux/gpio.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
22#include <linux/regulator/consumer.h>
23#include <linux/regulator/fixed.h>
24#include <linux/slab.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31#include <sound/wm5100.h>
32
33#include "wm5100.h"
34
35#define WM5100_NUM_CORE_SUPPLIES 2
36static const char *wm5100_core_supply_names[WM5100_NUM_CORE_SUPPLIES] = {
37 "DBVDD1",
38 "LDOVDD", /* If DCVDD is supplied externally specify as LDOVDD */
39};
40
41#define WM5100_AIFS 3
42#define WM5100_SYNC_SRS 3
43
44struct wm5100_fll {
45 int fref;
46 int fout;
47 int src;
48 struct completion lock;
49};
50
51/* codec private data */
52struct wm5100_priv {
53 struct snd_soc_codec *codec;
54
55 struct regulator_bulk_data core_supplies[WM5100_NUM_CORE_SUPPLIES];
56 struct regulator *cpvdd;
57
58 int rev;
59
60 int sysclk;
61 int asyncclk;
62
63 bool aif_async[WM5100_AIFS];
64 bool aif_symmetric[WM5100_AIFS];
65 int sr_ref[WM5100_SYNC_SRS];
66
67 bool out_ena[2];
68
69 struct wm5100_fll fll[2];
70
71 struct wm5100_pdata pdata;
72
73#ifdef CONFIG_GPIOLIB
74 struct gpio_chip gpio_chip;
75#endif
76};
77
78static int wm5100_sr_code[] = {
79 0,
80 12000,
81 24000,
82 48000,
83 96000,
84 192000,
85 384000,
86 768000,
87 0,
88 11025,
89 22050,
90 44100,
91 88200,
92 176400,
93 352800,
94 705600,
95 4000,
96 8000,
97 16000,
98 32000,
99 64000,
100 128000,
101 256000,
102 512000,
103};
104
105static int wm5100_sr_regs[WM5100_SYNC_SRS] = {
106 WM5100_CLOCKING_4,
107 WM5100_CLOCKING_5,
108 WM5100_CLOCKING_6,
109};
110
111static int wm5100_alloc_sr(struct snd_soc_codec *codec, int rate)
112{
113 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
114 int sr_code, sr_free, i;
115
116 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
117 if (wm5100_sr_code[i] == rate)
118 break;
119 if (i == ARRAY_SIZE(wm5100_sr_code)) {
120 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
121 return -EINVAL;
122 }
123 sr_code = i;
124
125 if ((wm5100->sysclk % rate) == 0) {
126 /* Is this rate already in use? */
127 sr_free = -1;
128 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
129 if (!wm5100->sr_ref[i] && sr_free == -1) {
130 sr_free = i;
131 continue;
132 }
133 if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
134 WM5100_SAMPLE_RATE_1_MASK) == sr_code)
135 break;
136 }
137
138 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
139 wm5100->sr_ref[i]++;
140 dev_dbg(codec->dev, "SR %dHz, slot %d, ref %d\n",
141 rate, i, wm5100->sr_ref[i]);
142 return i;
143 }
144
145 if (sr_free == -1) {
146 dev_err(codec->dev, "All SR slots already in use\n");
147 return -EBUSY;
148 }
149
150 dev_dbg(codec->dev, "Allocating SR slot %d for %dHz\n",
151 sr_free, rate);
152 wm5100->sr_ref[sr_free]++;
153 snd_soc_update_bits(codec, wm5100_sr_regs[sr_free],
154 WM5100_SAMPLE_RATE_1_MASK,
155 sr_code);
156
157 return sr_free;
158
159 } else {
160 dev_err(codec->dev,
161 "SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n",
162 rate, wm5100->sysclk, wm5100->asyncclk);
163 return -EINVAL;
164 }
165}
166
167static void wm5100_free_sr(struct snd_soc_codec *codec, int rate)
168{
169 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
170 int i, sr_code;
171
172 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
173 if (wm5100_sr_code[i] == rate)
174 break;
175 if (i == ARRAY_SIZE(wm5100_sr_code)) {
176 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
177 return;
178 }
179 sr_code = wm5100_sr_code[i];
180
181 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
182 if (!wm5100->sr_ref[i])
183 continue;
184
185 if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
186 WM5100_SAMPLE_RATE_1_MASK) == sr_code)
187 break;
188 }
189 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
190 wm5100->sr_ref[i]--;
191 dev_dbg(codec->dev, "Dereference SR %dHz, count now %d\n",
192 rate, wm5100->sr_ref[i]);
193 } else {
194 dev_warn(codec->dev, "Freeing unreferenced sample rate %dHz\n",
195 rate);
196 }
197}
198
199static int wm5100_reset(struct snd_soc_codec *codec)
200{
201 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
202
203 if (wm5100->pdata.reset) {
204 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
205 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
206
207 return 0;
208 } else {
209 return snd_soc_write(codec, WM5100_SOFTWARE_RESET, 0);
210 }
211}
212
213static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
214static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
215static DECLARE_TLV_DB_SCALE(mixer_tlv, -3200, 100, 0);
216static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
217static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
218
219static const char *wm5100_mixer_texts[] = {
220 "None",
221 "Tone Generator 1",
222 "Tone Generator 2",
223 "AEC loopback",
224 "IN1L",
225 "IN1R",
226 "IN2L",
227 "IN2R",
228 "IN3L",
229 "IN3R",
230 "IN4L",
231 "IN4R",
232 "AIF1RX1",
233 "AIF1RX2",
234 "AIF1RX3",
235 "AIF1RX4",
236 "AIF1RX5",
237 "AIF1RX6",
238 "AIF1RX7",
239 "AIF1RX8",
240 "AIF2RX1",
241 "AIF2RX2",
242 "AIF3RX1",
243 "AIF3RX2",
244 "EQ1",
245 "EQ2",
246 "EQ3",
247 "EQ4",
248 "DRC1L",
249 "DRC1R",
250 "LHPF1",
251 "LHPF2",
252 "LHPF3",
253 "LHPF4",
254 "DSP1.1",
255 "DSP1.2",
256 "DSP1.3",
257 "DSP1.4",
258 "DSP1.5",
259 "DSP1.6",
260 "DSP2.1",
261 "DSP2.2",
262 "DSP2.3",
263 "DSP2.4",
264 "DSP2.5",
265 "DSP2.6",
266 "DSP3.1",
267 "DSP3.2",
268 "DSP3.3",
269 "DSP3.4",
270 "DSP3.5",
271 "DSP3.6",
272 "ASRC1L",
273 "ASRC1R",
274 "ASRC2L",
275 "ASRC2R",
276 "ISRC1INT1",
277 "ISRC1INT2",
278 "ISRC1INT3",
279 "ISRC1INT4",
280 "ISRC2INT1",
281 "ISRC2INT2",
282 "ISRC2INT3",
283 "ISRC2INT4",
284 "ISRC1DEC1",
285 "ISRC1DEC2",
286 "ISRC1DEC3",
287 "ISRC1DEC4",
288 "ISRC2DEC1",
289 "ISRC2DEC2",
290 "ISRC2DEC3",
291 "ISRC2DEC4",
292};
293
294static int wm5100_mixer_values[] = {
295 0x00,
296 0x04, /* Tone */
297 0x05,
298 0x08, /* AEC */
299 0x10, /* Input */
300 0x11,
301 0x12,
302 0x13,
303 0x14,
304 0x15,
305 0x16,
306 0x17,
307 0x20, /* AIF */
308 0x21,
309 0x22,
310 0x23,
311 0x24,
312 0x25,
313 0x26,
314 0x27,
315 0x28,
316 0x29,
317 0x30, /* AIF3 - check */
318 0x31,
319 0x50, /* EQ */
320 0x51,
321 0x52,
322 0x53,
323 0x54,
324 0x58, /* DRC */
325 0x59,
326 0x60, /* LHPF1 */
327 0x61, /* LHPF2 */
328 0x62, /* LHPF3 */
329 0x63, /* LHPF4 */
330 0x68, /* DSP1 */
331 0x69,
332 0x6a,
333 0x6b,
334 0x6c,
335 0x6d,
336 0x70, /* DSP2 */
337 0x71,
338 0x72,
339 0x73,
340 0x74,
341 0x75,
342 0x78, /* DSP3 */
343 0x79,
344 0x7a,
345 0x7b,
346 0x7c,
347 0x7d,
348 0x90, /* ASRC1 */
349 0x91,
350 0x92, /* ASRC2 */
351 0x93,
352 0xa0, /* ISRC1DEC1 */
353 0xa1,
354 0xa2,
355 0xa3,
356 0xa4, /* ISRC1INT1 */
357 0xa5,
358 0xa6,
359 0xa7,
360 0xa8, /* ISRC2DEC1 */
361 0xa9,
362 0xaa,
363 0xab,
364 0xac, /* ISRC2INT1 */
365 0xad,
366 0xae,
367 0xaf,
368};
369
370#define WM5100_MIXER_CONTROLS(name, base) \
371 SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
372 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
373 SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
374 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
375 SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
376 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
377 SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
378 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
379
380#define WM5100_MUX_ENUM_DECL(name, reg) \
381 SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \
382 wm5100_mixer_texts, wm5100_mixer_values)
383
384#define WM5100_MUX_CTL_DECL(name) \
385 const struct snd_kcontrol_new name##_mux = \
386 SOC_DAPM_VALUE_ENUM("Route", name##_enum)
387
388#define WM5100_MIXER_ENUMS(name, base_reg) \
389 static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg); \
390 static WM5100_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2); \
391 static WM5100_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4); \
392 static WM5100_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6); \
393 static WM5100_MUX_CTL_DECL(name##_in1); \
394 static WM5100_MUX_CTL_DECL(name##_in2); \
395 static WM5100_MUX_CTL_DECL(name##_in3); \
396 static WM5100_MUX_CTL_DECL(name##_in4)
397
398WM5100_MIXER_ENUMS(HPOUT1L, WM5100_OUT1LMIX_INPUT_1_SOURCE);
399WM5100_MIXER_ENUMS(HPOUT1R, WM5100_OUT1RMIX_INPUT_1_SOURCE);
400WM5100_MIXER_ENUMS(HPOUT2L, WM5100_OUT2LMIX_INPUT_1_SOURCE);
401WM5100_MIXER_ENUMS(HPOUT2R, WM5100_OUT2RMIX_INPUT_1_SOURCE);
402WM5100_MIXER_ENUMS(HPOUT3L, WM5100_OUT3LMIX_INPUT_1_SOURCE);
403WM5100_MIXER_ENUMS(HPOUT3R, WM5100_OUT3RMIX_INPUT_1_SOURCE);
404
405WM5100_MIXER_ENUMS(SPKOUTL, WM5100_OUT4LMIX_INPUT_1_SOURCE);
406WM5100_MIXER_ENUMS(SPKOUTR, WM5100_OUT4RMIX_INPUT_1_SOURCE);
407WM5100_MIXER_ENUMS(SPKDAT1L, WM5100_OUT5LMIX_INPUT_1_SOURCE);
408WM5100_MIXER_ENUMS(SPKDAT1R, WM5100_OUT5RMIX_INPUT_1_SOURCE);
409WM5100_MIXER_ENUMS(SPKDAT2L, WM5100_OUT6LMIX_INPUT_1_SOURCE);
410WM5100_MIXER_ENUMS(SPKDAT2R, WM5100_OUT6RMIX_INPUT_1_SOURCE);
411
412WM5100_MIXER_ENUMS(PWM1, WM5100_PWM1MIX_INPUT_1_SOURCE);
413WM5100_MIXER_ENUMS(PWM2, WM5100_PWM1MIX_INPUT_1_SOURCE);
414
415WM5100_MIXER_ENUMS(AIF1TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
416WM5100_MIXER_ENUMS(AIF1TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
417WM5100_MIXER_ENUMS(AIF1TX3, WM5100_AIF1TX3MIX_INPUT_1_SOURCE);
418WM5100_MIXER_ENUMS(AIF1TX4, WM5100_AIF1TX4MIX_INPUT_1_SOURCE);
419WM5100_MIXER_ENUMS(AIF1TX5, WM5100_AIF1TX5MIX_INPUT_1_SOURCE);
420WM5100_MIXER_ENUMS(AIF1TX6, WM5100_AIF1TX6MIX_INPUT_1_SOURCE);
421WM5100_MIXER_ENUMS(AIF1TX7, WM5100_AIF1TX7MIX_INPUT_1_SOURCE);
422WM5100_MIXER_ENUMS(AIF1TX8, WM5100_AIF1TX8MIX_INPUT_1_SOURCE);
423
424WM5100_MIXER_ENUMS(AIF2TX1, WM5100_AIF2TX1MIX_INPUT_1_SOURCE);
425WM5100_MIXER_ENUMS(AIF2TX2, WM5100_AIF2TX2MIX_INPUT_1_SOURCE);
426
427WM5100_MIXER_ENUMS(AIF3TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
428WM5100_MIXER_ENUMS(AIF3TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
429
430WM5100_MIXER_ENUMS(EQ1, WM5100_EQ1MIX_INPUT_1_SOURCE);
431WM5100_MIXER_ENUMS(EQ2, WM5100_EQ2MIX_INPUT_1_SOURCE);
432WM5100_MIXER_ENUMS(EQ3, WM5100_EQ3MIX_INPUT_1_SOURCE);
433WM5100_MIXER_ENUMS(EQ4, WM5100_EQ4MIX_INPUT_1_SOURCE);
434
435WM5100_MIXER_ENUMS(DRC1L, WM5100_DRC1LMIX_INPUT_1_SOURCE);
436WM5100_MIXER_ENUMS(DRC1R, WM5100_DRC1RMIX_INPUT_1_SOURCE);
437
438WM5100_MIXER_ENUMS(LHPF1, WM5100_HPLP1MIX_INPUT_1_SOURCE);
439WM5100_MIXER_ENUMS(LHPF2, WM5100_HPLP2MIX_INPUT_1_SOURCE);
440WM5100_MIXER_ENUMS(LHPF3, WM5100_HPLP3MIX_INPUT_1_SOURCE);
441WM5100_MIXER_ENUMS(LHPF4, WM5100_HPLP4MIX_INPUT_1_SOURCE);
442
443#define WM5100_MUX(name, ctrl) \
444 SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
445
446#define WM5100_MIXER_WIDGETS(name, name_str) \
447 WM5100_MUX(name_str " Input 1", &name##_in1_mux), \
448 WM5100_MUX(name_str " Input 2", &name##_in2_mux), \
449 WM5100_MUX(name_str " Input 3", &name##_in3_mux), \
450 WM5100_MUX(name_str " Input 4", &name##_in4_mux), \
451 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
452
453#define WM5100_MIXER_INPUT_ROUTES(name) \
454 { name, "Tone Generator 1", "Tone Generator 1" }, \
455 { name, "Tone Generator 2", "Tone Generator 2" }, \
456 { name, "IN1L", "IN1L PGA" }, \
457 { name, "IN1R", "IN1R PGA" }, \
458 { name, "IN2L", "IN2L PGA" }, \
459 { name, "IN2R", "IN2R PGA" }, \
460 { name, "IN3L", "IN3L PGA" }, \
461 { name, "IN3R", "IN3R PGA" }, \
462 { name, "IN4L", "IN4L PGA" }, \
463 { name, "IN4R", "IN4R PGA" }, \
464 { name, "AIF1RX1", "AIF1RX1" }, \
465 { name, "AIF1RX2", "AIF1RX2" }, \
466 { name, "AIF1RX3", "AIF1RX3" }, \
467 { name, "AIF1RX4", "AIF1RX4" }, \
468 { name, "AIF1RX5", "AIF1RX5" }, \
469 { name, "AIF1RX6", "AIF1RX6" }, \
470 { name, "AIF1RX7", "AIF1RX7" }, \
471 { name, "AIF1RX8", "AIF1RX8" }, \
472 { name, "AIF2RX1", "AIF2RX1" }, \
473 { name, "AIF2RX2", "AIF2RX2" }, \
474 { name, "AIF3RX1", "AIF3RX1" }, \
475 { name, "AIF3RX2", "AIF3RX2" }, \
476 { name, "EQ1", "EQ1" }, \
477 { name, "EQ2", "EQ2" }, \
478 { name, "EQ3", "EQ3" }, \
479 { name, "EQ4", "EQ4" }, \
480 { name, "DRC1L", "DRC1L" }, \
481 { name, "DRC1R", "DRC1R" }, \
482 { name, "LHPF1", "LHPF1" }, \
483 { name, "LHPF2", "LHPF2" }, \
484 { name, "LHPF3", "LHPF3" }, \
485 { name, "LHPF4", "LHPF4" }
486
487#define WM5100_MIXER_ROUTES(widget, name) \
488 { widget, NULL, name " Mixer" }, \
489 { name " Mixer", NULL, name " Input 1" }, \
490 { name " Mixer", NULL, name " Input 2" }, \
491 { name " Mixer", NULL, name " Input 3" }, \
492 { name " Mixer", NULL, name " Input 4" }, \
493 WM5100_MIXER_INPUT_ROUTES(name " Input 1"), \
494 WM5100_MIXER_INPUT_ROUTES(name " Input 2"), \
495 WM5100_MIXER_INPUT_ROUTES(name " Input 3"), \
496 WM5100_MIXER_INPUT_ROUTES(name " Input 4")
497
498static const char *wm5100_lhpf_mode_text[] = {
499 "Low-pass", "High-pass"
500};
501
502static const struct soc_enum wm5100_lhpf1_mode =
503 SOC_ENUM_SINGLE(WM5100_HPLPF1_1, WM5100_LHPF1_MODE_SHIFT, 2,
504 wm5100_lhpf_mode_text);
505
506static const struct soc_enum wm5100_lhpf2_mode =
507 SOC_ENUM_SINGLE(WM5100_HPLPF2_1, WM5100_LHPF2_MODE_SHIFT, 2,
508 wm5100_lhpf_mode_text);
509
510static const struct soc_enum wm5100_lhpf3_mode =
511 SOC_ENUM_SINGLE(WM5100_HPLPF3_1, WM5100_LHPF3_MODE_SHIFT, 2,
512 wm5100_lhpf_mode_text);
513
514static const struct soc_enum wm5100_lhpf4_mode =
515 SOC_ENUM_SINGLE(WM5100_HPLPF4_1, WM5100_LHPF4_MODE_SHIFT, 2,
516 wm5100_lhpf_mode_text);
517
518static const struct snd_kcontrol_new wm5100_snd_controls[] = {
519SOC_SINGLE("IN1 High Performance Switch", WM5100_IN1L_CONTROL,
520 WM5100_IN1_OSR_SHIFT, 1, 0),
521SOC_SINGLE("IN2 High Performance Switch", WM5100_IN2L_CONTROL,
522 WM5100_IN2_OSR_SHIFT, 1, 0),
523SOC_SINGLE("IN3 High Performance Switch", WM5100_IN3L_CONTROL,
524 WM5100_IN3_OSR_SHIFT, 1, 0),
525SOC_SINGLE("IN4 High Performance Switch", WM5100_IN4L_CONTROL,
526 WM5100_IN4_OSR_SHIFT, 1, 0),
527
528/* Only applicable for analogue inputs */
529SOC_DOUBLE_R_TLV("IN1 Volume", WM5100_IN1L_CONTROL, WM5100_IN1R_CONTROL,
530 WM5100_IN1L_PGA_VOL_SHIFT, 94, 0, in_tlv),
531SOC_DOUBLE_R_TLV("IN2 Volume", WM5100_IN2L_CONTROL, WM5100_IN2R_CONTROL,
532 WM5100_IN2L_PGA_VOL_SHIFT, 94, 0, in_tlv),
533SOC_DOUBLE_R_TLV("IN3 Volume", WM5100_IN3L_CONTROL, WM5100_IN3R_CONTROL,
534 WM5100_IN3L_PGA_VOL_SHIFT, 94, 0, in_tlv),
535SOC_DOUBLE_R_TLV("IN4 Volume", WM5100_IN4L_CONTROL, WM5100_IN4R_CONTROL,
536 WM5100_IN4L_PGA_VOL_SHIFT, 94, 0, in_tlv),
537
538SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_1L,
539 WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_VOL_SHIFT, 191,
540 0, digital_tlv),
541SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_2L,
542 WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_VOL_SHIFT, 191,
543 0, digital_tlv),
544SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_3L,
545 WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_VOL_SHIFT, 191,
546 0, digital_tlv),
547SOC_DOUBLE_R_TLV("IN4 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_4L,
548 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_VOL_SHIFT, 191,
549 0, digital_tlv),
550
551SOC_DOUBLE_R("IN1 Switch", WM5100_ADC_DIGITAL_VOLUME_1L,
552 WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_MUTE_SHIFT, 1, 1),
553SOC_DOUBLE_R("IN2 Switch", WM5100_ADC_DIGITAL_VOLUME_2L,
554 WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_MUTE_SHIFT, 1, 1),
555SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L,
556 WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_MUTE_SHIFT, 1, 1),
557SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L,
558 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1),
559
560SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L,
561 WM5100_OUT1_OSR_SHIFT, 1, 0),
562SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L,
563 WM5100_OUT2_OSR_SHIFT, 1, 0),
564SOC_SINGLE("HPOUT3 High Performance Switch", WM5100_OUT_VOLUME_3L,
565 WM5100_OUT3_OSR_SHIFT, 1, 0),
566SOC_SINGLE("SPKOUT High Performance Switch", WM5100_OUT_VOLUME_4L,
567 WM5100_OUT4_OSR_SHIFT, 1, 0),
568SOC_SINGLE("SPKDAT1 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_5L,
569 WM5100_OUT5_OSR_SHIFT, 1, 0),
570SOC_SINGLE("SPKDAT2 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_6L,
571 WM5100_OUT6_OSR_SHIFT, 1, 0),
572
573SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_1L,
574 WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_VOL_SHIFT, 159, 0,
575 digital_tlv),
576SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_2L,
577 WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_VOL_SHIFT, 159, 0,
578 digital_tlv),
579SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_3L,
580 WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_VOL_SHIFT, 159, 0,
581 digital_tlv),
582SOC_DOUBLE_R_TLV("SPKOUT Digital Volume", WM5100_DAC_DIGITAL_VOLUME_4L,
583 WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_VOL_SHIFT, 159, 0,
584 digital_tlv),
585SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_5L,
586 WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_VOL_SHIFT, 159, 0,
587 digital_tlv),
588SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_6L,
589 WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_VOL_SHIFT, 159, 0,
590 digital_tlv),
591
592SOC_DOUBLE_R("HPOUT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_1L,
593 WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_MUTE_SHIFT, 1, 1),
594SOC_DOUBLE_R("HPOUT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_2L,
595 WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_MUTE_SHIFT, 1, 1),
596SOC_DOUBLE_R("HPOUT3 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_3L,
597 WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_MUTE_SHIFT, 1, 1),
598SOC_DOUBLE_R("SPKOUT Digital Switch", WM5100_DAC_DIGITAL_VOLUME_4L,
599 WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_MUTE_SHIFT, 1, 1),
600SOC_DOUBLE_R("SPKDAT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_5L,
601 WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_MUTE_SHIFT, 1, 1),
602SOC_DOUBLE_R("SPKDAT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_6L,
603 WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_MUTE_SHIFT, 1, 1),
604
605/* FIXME: Only valid from -12dB to 0dB (52-64) */
606SOC_DOUBLE_R_TLV("HPOUT1 Volume", WM5100_OUT_VOLUME_1L, WM5100_OUT_VOLUME_1R,
607 WM5100_OUT1L_PGA_VOL_SHIFT, 64, 0, out_tlv),
608SOC_DOUBLE_R_TLV("HPOUT2 Volume", WM5100_OUT_VOLUME_2L, WM5100_OUT_VOLUME_2R,
609 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
610SOC_DOUBLE_R_TLV("HPOUT3 Volume", WM5100_OUT_VOLUME_3L, WM5100_OUT_VOLUME_3R,
611 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
612
613SOC_DOUBLE("SPKDAT1 Switch", WM5100_PDM_SPK1_CTRL_1, WM5100_SPK1L_MUTE_SHIFT,
614 WM5100_SPK1R_MUTE_SHIFT, 1, 1),
615SOC_DOUBLE("SPKDAT2 Switch", WM5100_PDM_SPK2_CTRL_1, WM5100_SPK2L_MUTE_SHIFT,
616 WM5100_SPK2R_MUTE_SHIFT, 1, 1),
617
618SOC_SINGLE_TLV("EQ1 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ1_B1_GAIN_SHIFT,
619 24, 0, eq_tlv),
620SOC_SINGLE_TLV("EQ1 Band 2 Volume", WM5100_EQ1_1, WM5100_EQ1_B2_GAIN_SHIFT,
621 24, 0, eq_tlv),
622SOC_SINGLE_TLV("EQ1 Band 3 Volume", WM5100_EQ1_1, WM5100_EQ1_B3_GAIN_SHIFT,
623 24, 0, eq_tlv),
624SOC_SINGLE_TLV("EQ1 Band 4 Volume", WM5100_EQ1_2, WM5100_EQ1_B4_GAIN_SHIFT,
625 24, 0, eq_tlv),
626SOC_SINGLE_TLV("EQ1 Band 5 Volume", WM5100_EQ1_2, WM5100_EQ1_B5_GAIN_SHIFT,
627 24, 0, eq_tlv),
628
629SOC_SINGLE_TLV("EQ2 Band 1 Volume", WM5100_EQ2_1, WM5100_EQ2_B1_GAIN_SHIFT,
630 24, 0, eq_tlv),
631SOC_SINGLE_TLV("EQ2 Band 2 Volume", WM5100_EQ2_1, WM5100_EQ2_B2_GAIN_SHIFT,
632 24, 0, eq_tlv),
633SOC_SINGLE_TLV("EQ2 Band 3 Volume", WM5100_EQ2_1, WM5100_EQ2_B3_GAIN_SHIFT,
634 24, 0, eq_tlv),
635SOC_SINGLE_TLV("EQ2 Band 4 Volume", WM5100_EQ2_2, WM5100_EQ2_B4_GAIN_SHIFT,
636 24, 0, eq_tlv),
637SOC_SINGLE_TLV("EQ2 Band 5 Volume", WM5100_EQ2_2, WM5100_EQ2_B5_GAIN_SHIFT,
638 24, 0, eq_tlv),
639
640SOC_SINGLE_TLV("EQ3 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ3_B1_GAIN_SHIFT,
641 24, 0, eq_tlv),
642SOC_SINGLE_TLV("EQ3 Band 2 Volume", WM5100_EQ3_1, WM5100_EQ3_B2_GAIN_SHIFT,
643 24, 0, eq_tlv),
644SOC_SINGLE_TLV("EQ3 Band 3 Volume", WM5100_EQ3_1, WM5100_EQ3_B3_GAIN_SHIFT,
645 24, 0, eq_tlv),
646SOC_SINGLE_TLV("EQ3 Band 4 Volume", WM5100_EQ3_2, WM5100_EQ3_B4_GAIN_SHIFT,
647 24, 0, eq_tlv),
648SOC_SINGLE_TLV("EQ3 Band 5 Volume", WM5100_EQ3_2, WM5100_EQ3_B5_GAIN_SHIFT,
649 24, 0, eq_tlv),
650
651SOC_SINGLE_TLV("EQ4 Band 1 Volume", WM5100_EQ4_1, WM5100_EQ4_B1_GAIN_SHIFT,
652 24, 0, eq_tlv),
653SOC_SINGLE_TLV("EQ4 Band 2 Volume", WM5100_EQ4_1, WM5100_EQ4_B2_GAIN_SHIFT,
654 24, 0, eq_tlv),
655SOC_SINGLE_TLV("EQ4 Band 3 Volume", WM5100_EQ4_1, WM5100_EQ4_B3_GAIN_SHIFT,
656 24, 0, eq_tlv),
657SOC_SINGLE_TLV("EQ4 Band 4 Volume", WM5100_EQ4_2, WM5100_EQ4_B4_GAIN_SHIFT,
658 24, 0, eq_tlv),
659SOC_SINGLE_TLV("EQ4 Band 5 Volume", WM5100_EQ4_2, WM5100_EQ4_B5_GAIN_SHIFT,
660 24, 0, eq_tlv),
661
662SOC_ENUM("LHPF1 Mode", wm5100_lhpf1_mode),
663SOC_ENUM("LHPF2 Mode", wm5100_lhpf2_mode),
664SOC_ENUM("LHPF3 Mode", wm5100_lhpf3_mode),
665SOC_ENUM("LHPF4 Mode", wm5100_lhpf4_mode),
666
667WM5100_MIXER_CONTROLS("HPOUT1L", WM5100_OUT1LMIX_INPUT_1_SOURCE),
668WM5100_MIXER_CONTROLS("HPOUT1R", WM5100_OUT1RMIX_INPUT_1_SOURCE),
669WM5100_MIXER_CONTROLS("HPOUT2L", WM5100_OUT2LMIX_INPUT_1_SOURCE),
670WM5100_MIXER_CONTROLS("HPOUT2R", WM5100_OUT2RMIX_INPUT_1_SOURCE),
671WM5100_MIXER_CONTROLS("HPOUT3L", WM5100_OUT3LMIX_INPUT_1_SOURCE),
672WM5100_MIXER_CONTROLS("HPOUT3R", WM5100_OUT3RMIX_INPUT_1_SOURCE),
673
674WM5100_MIXER_CONTROLS("SPKOUTL", WM5100_OUT4LMIX_INPUT_1_SOURCE),
675WM5100_MIXER_CONTROLS("SPKOUTR", WM5100_OUT4RMIX_INPUT_1_SOURCE),
676WM5100_MIXER_CONTROLS("SPKDAT1L", WM5100_OUT5LMIX_INPUT_1_SOURCE),
677WM5100_MIXER_CONTROLS("SPKDAT1R", WM5100_OUT5RMIX_INPUT_1_SOURCE),
678WM5100_MIXER_CONTROLS("SPKDAT2L", WM5100_OUT6LMIX_INPUT_1_SOURCE),
679WM5100_MIXER_CONTROLS("SPKDAT2R", WM5100_OUT6RMIX_INPUT_1_SOURCE),
680
681WM5100_MIXER_CONTROLS("PWM1", WM5100_PWM1MIX_INPUT_1_SOURCE),
682WM5100_MIXER_CONTROLS("PWM2", WM5100_PWM2MIX_INPUT_1_SOURCE),
683
684WM5100_MIXER_CONTROLS("AIF1TX1", WM5100_AIF1TX1MIX_INPUT_1_SOURCE),
685WM5100_MIXER_CONTROLS("AIF1TX2", WM5100_AIF1TX2MIX_INPUT_1_SOURCE),
686WM5100_MIXER_CONTROLS("AIF1TX3", WM5100_AIF1TX3MIX_INPUT_1_SOURCE),
687WM5100_MIXER_CONTROLS("AIF1TX4", WM5100_AIF1TX4MIX_INPUT_1_SOURCE),
688WM5100_MIXER_CONTROLS("AIF1TX5", WM5100_AIF1TX5MIX_INPUT_1_SOURCE),
689WM5100_MIXER_CONTROLS("AIF1TX6", WM5100_AIF1TX6MIX_INPUT_1_SOURCE),
690WM5100_MIXER_CONTROLS("AIF1TX7", WM5100_AIF1TX7MIX_INPUT_1_SOURCE),
691WM5100_MIXER_CONTROLS("AIF1TX8", WM5100_AIF1TX8MIX_INPUT_1_SOURCE),
692
693WM5100_MIXER_CONTROLS("AIF2TX1", WM5100_AIF2TX1MIX_INPUT_1_SOURCE),
694WM5100_MIXER_CONTROLS("AIF2TX2", WM5100_AIF2TX2MIX_INPUT_1_SOURCE),
695
696WM5100_MIXER_CONTROLS("AIF3TX1", WM5100_AIF3TX1MIX_INPUT_1_SOURCE),
697WM5100_MIXER_CONTROLS("AIF3TX2", WM5100_AIF3TX2MIX_INPUT_1_SOURCE),
698
699WM5100_MIXER_CONTROLS("EQ1", WM5100_EQ1MIX_INPUT_1_SOURCE),
700WM5100_MIXER_CONTROLS("EQ2", WM5100_EQ2MIX_INPUT_1_SOURCE),
701WM5100_MIXER_CONTROLS("EQ3", WM5100_EQ3MIX_INPUT_1_SOURCE),
702WM5100_MIXER_CONTROLS("EQ4", WM5100_EQ4MIX_INPUT_1_SOURCE),
703
704WM5100_MIXER_CONTROLS("DRC1L", WM5100_DRC1LMIX_INPUT_1_SOURCE),
705WM5100_MIXER_CONTROLS("DRC1R", WM5100_DRC1RMIX_INPUT_1_SOURCE),
706
707WM5100_MIXER_CONTROLS("LHPF1", WM5100_HPLP1MIX_INPUT_1_SOURCE),
708WM5100_MIXER_CONTROLS("LHPF2", WM5100_HPLP2MIX_INPUT_1_SOURCE),
709WM5100_MIXER_CONTROLS("LHPF3", WM5100_HPLP3MIX_INPUT_1_SOURCE),
710WM5100_MIXER_CONTROLS("LHPF4", WM5100_HPLP4MIX_INPUT_1_SOURCE),
711};
712
713static void wm5100_seq_notifier(struct snd_soc_dapm_context *dapm,
714 enum snd_soc_dapm_type event, int subseq)
715{
716 struct snd_soc_codec *codec = container_of(dapm,
717 struct snd_soc_codec, dapm);
718 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
719 u16 val, expect, i;
720
721 /* Wait for the outputs to flag themselves as enabled */
722 if (wm5100->out_ena[0]) {
723 expect = snd_soc_read(codec, WM5100_CHANNEL_ENABLES_1);
724 for (i = 0; i < 200; i++) {
725 val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_1);
726 if (val == expect) {
727 wm5100->out_ena[0] = false;
728 break;
729 }
730 }
731 if (i == 200) {
732 dev_err(codec->dev, "Timeout waiting for OUTPUT1 %x\n",
733 expect);
734 }
735 }
736
737 if (wm5100->out_ena[1]) {
738 expect = snd_soc_read(codec, WM5100_OUTPUT_ENABLES_2);
739 for (i = 0; i < 200; i++) {
740 val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_2);
741 if (val == expect) {
742 wm5100->out_ena[1] = false;
743 break;
744 }
745 }
746 if (i == 200) {
747 dev_err(codec->dev, "Timeout waiting for OUTPUT2 %x\n",
748 expect);
749 }
750 }
751}
752
753static int wm5100_out_ev(struct snd_soc_dapm_widget *w,
754 struct snd_kcontrol *kcontrol,
755 int event)
756{
757 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(w->codec);
758
759 switch (w->reg) {
760 case WM5100_CHANNEL_ENABLES_1:
761 wm5100->out_ena[0] = true;
762 break;
763 case WM5100_OUTPUT_ENABLES_2:
764 wm5100->out_ena[0] = true;
765 break;
766 default:
767 break;
768 }
769
770 return 0;
771}
772
773static int wm5100_cp_ev(struct snd_soc_dapm_widget *w,
774 struct snd_kcontrol *kcontrol,
775 int event)
776{
777 struct snd_soc_codec *codec = w->codec;
778 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
779 int ret;
780
781 switch (event) {
782 case SND_SOC_DAPM_PRE_PMU:
783 ret = regulator_enable(wm5100->cpvdd);
784 if (ret != 0) {
785 dev_err(codec->dev, "Failed to enable CPVDD: %d\n",
786 ret);
787 return ret;
788 }
789 return ret;
790
791 case SND_SOC_DAPM_POST_PMD:
792 ret = regulator_disable_deferred(wm5100->cpvdd, 20);
793 if (ret != 0) {
794 dev_err(codec->dev, "Failed to disable CPVDD: %d\n",
795 ret);
796 return ret;
797 }
798 return ret;
799
800 default:
801 BUG();
802 return 0;
803 }
804}
805
806static void wm5100_log_status3(struct snd_soc_codec *codec, int val)
807{
808 if (val & WM5100_SPK_SHUTDOWN_WARN_EINT)
809 dev_crit(codec->dev, "Speaker shutdown warning\n");
810 if (val & WM5100_SPK_SHUTDOWN_EINT)
811 dev_crit(codec->dev, "Speaker shutdown\n");
812 if (val & WM5100_CLKGEN_ERR_EINT)
813 dev_crit(codec->dev, "SYSCLK underclocked\n");
814 if (val & WM5100_CLKGEN_ERR_ASYNC_EINT)
815 dev_crit(codec->dev, "ASYNCCLK underclocked\n");
816}
817
818static void wm5100_log_status4(struct snd_soc_codec *codec, int val)
819{
820 if (val & WM5100_AIF3_ERR_EINT)
821 dev_err(codec->dev, "AIF3 configuration error\n");
822 if (val & WM5100_AIF2_ERR_EINT)
823 dev_err(codec->dev, "AIF2 configuration error\n");
824 if (val & WM5100_AIF1_ERR_EINT)
825 dev_err(codec->dev, "AIF1 configuration error\n");
826 if (val & WM5100_CTRLIF_ERR_EINT)
827 dev_err(codec->dev, "Control interface error\n");
828 if (val & WM5100_ISRC2_UNDERCLOCKED_EINT)
829 dev_err(codec->dev, "ISRC2 underclocked\n");
830 if (val & WM5100_ISRC1_UNDERCLOCKED_EINT)
831 dev_err(codec->dev, "ISRC1 underclocked\n");
832 if (val & WM5100_FX_UNDERCLOCKED_EINT)
833 dev_err(codec->dev, "FX underclocked\n");
834 if (val & WM5100_AIF3_UNDERCLOCKED_EINT)
835 dev_err(codec->dev, "AIF3 underclocked\n");
836 if (val & WM5100_AIF2_UNDERCLOCKED_EINT)
837 dev_err(codec->dev, "AIF2 underclocked\n");
838 if (val & WM5100_AIF1_UNDERCLOCKED_EINT)
839 dev_err(codec->dev, "AIF1 underclocked\n");
840 if (val & WM5100_ASRC_UNDERCLOCKED_EINT)
841 dev_err(codec->dev, "ASRC underclocked\n");
842 if (val & WM5100_DAC_UNDERCLOCKED_EINT)
843 dev_err(codec->dev, "DAC underclocked\n");
844 if (val & WM5100_ADC_UNDERCLOCKED_EINT)
845 dev_err(codec->dev, "ADC underclocked\n");
846 if (val & WM5100_MIXER_UNDERCLOCKED_EINT)
847 dev_err(codec->dev, "Mixer underclocked\n");
848}
849
850static int wm5100_post_ev(struct snd_soc_dapm_widget *w,
851 struct snd_kcontrol *kcontrol,
852 int event)
853{
854 struct snd_soc_codec *codec = w->codec;
855 int ret;
856
857 ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_3);
858 ret &= WM5100_SPK_SHUTDOWN_WARN_STS |
859 WM5100_SPK_SHUTDOWN_STS | WM5100_CLKGEN_ERR_STS |
860 WM5100_CLKGEN_ERR_ASYNC_STS;
861 wm5100_log_status3(codec, ret);
862
863 ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_4);
864 wm5100_log_status4(codec, ret);
865
866 return 0;
867}
868
869static const struct snd_soc_dapm_widget wm5100_dapm_widgets[] = {
870SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3, WM5100_SYSCLK_ENA_SHIFT, 0,
871 NULL, 0),
872SND_SOC_DAPM_SUPPLY("ASYNCCLK", WM5100_CLOCKING_6, WM5100_ASYNC_CLK_ENA_SHIFT,
873 0, NULL, 0),
874
875SND_SOC_DAPM_SUPPLY("CP1", WM5100_HP_CHARGE_PUMP_1, WM5100_CP1_ENA_SHIFT, 0,
876 wm5100_cp_ev,
877 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
878SND_SOC_DAPM_SUPPLY("CP2", WM5100_MIC_CHARGE_PUMP_1, WM5100_CP2_ENA_SHIFT, 0,
879 NULL, 0),
880SND_SOC_DAPM_SUPPLY("CP2 Active", WM5100_MIC_CHARGE_PUMP_1,
881 WM5100_CP2_BYPASS_SHIFT, 1, wm5100_cp_ev,
882 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
883
884SND_SOC_DAPM_SUPPLY("MICBIAS1", WM5100_MIC_BIAS_CTRL_1, WM5100_MICB1_ENA_SHIFT,
885 0, NULL, 0),
886SND_SOC_DAPM_SUPPLY("MICBIAS2", WM5100_MIC_BIAS_CTRL_2, WM5100_MICB2_ENA_SHIFT,
887 0, NULL, 0),
888SND_SOC_DAPM_SUPPLY("MICBIAS3", WM5100_MIC_BIAS_CTRL_3, WM5100_MICB3_ENA_SHIFT,
889 0, NULL, 0),
890
891SND_SOC_DAPM_INPUT("IN1L"),
892SND_SOC_DAPM_INPUT("IN1R"),
893SND_SOC_DAPM_INPUT("IN2L"),
894SND_SOC_DAPM_INPUT("IN2R"),
895SND_SOC_DAPM_INPUT("IN3L"),
896SND_SOC_DAPM_INPUT("IN3R"),
897SND_SOC_DAPM_INPUT("IN4L"),
898SND_SOC_DAPM_INPUT("IN4R"),
899SND_SOC_DAPM_INPUT("TONE"),
900
901SND_SOC_DAPM_PGA_E("IN1L PGA", WM5100_INPUT_ENABLES, WM5100_IN1L_ENA_SHIFT, 0,
902 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
903SND_SOC_DAPM_PGA_E("IN1R PGA", WM5100_INPUT_ENABLES, WM5100_IN1R_ENA_SHIFT, 0,
904 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
905SND_SOC_DAPM_PGA_E("IN2L PGA", WM5100_INPUT_ENABLES, WM5100_IN2L_ENA_SHIFT, 0,
906 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
907SND_SOC_DAPM_PGA_E("IN2R PGA", WM5100_INPUT_ENABLES, WM5100_IN2R_ENA_SHIFT, 0,
908 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
909SND_SOC_DAPM_PGA_E("IN3L PGA", WM5100_INPUT_ENABLES, WM5100_IN3L_ENA_SHIFT, 0,
910 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
911SND_SOC_DAPM_PGA_E("IN3R PGA", WM5100_INPUT_ENABLES, WM5100_IN3R_ENA_SHIFT, 0,
912 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
913SND_SOC_DAPM_PGA_E("IN4L PGA", WM5100_INPUT_ENABLES, WM5100_IN4L_ENA_SHIFT, 0,
914 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
915SND_SOC_DAPM_PGA_E("IN4R PGA", WM5100_INPUT_ENABLES, WM5100_IN4R_ENA_SHIFT, 0,
916 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
917
918SND_SOC_DAPM_PGA("Tone Generator 1", WM5100_TONE_GENERATOR_1,
919 WM5100_TONE1_ENA_SHIFT, 0, NULL, 0),
920SND_SOC_DAPM_PGA("Tone Generator 2", WM5100_TONE_GENERATOR_1,
921 WM5100_TONE2_ENA_SHIFT, 0, NULL, 0),
922
923SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 0,
924 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX1_ENA_SHIFT, 0),
925SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 1,
926 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX2_ENA_SHIFT, 0),
927SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 2,
928 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX3_ENA_SHIFT, 0),
929SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 3,
930 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX4_ENA_SHIFT, 0),
931SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 4,
932 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX5_ENA_SHIFT, 0),
933SND_SOC_DAPM_AIF_IN("AIF1RX6", "AIF1 Playback", 5,
934 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX6_ENA_SHIFT, 0),
935SND_SOC_DAPM_AIF_IN("AIF1RX7", "AIF1 Playback", 6,
936 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX7_ENA_SHIFT, 0),
937SND_SOC_DAPM_AIF_IN("AIF1RX8", "AIF1 Playback", 7,
938 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX8_ENA_SHIFT, 0),
939
940SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
941 WM5100_AUDIO_IF_2_27, WM5100_AIF2RX1_ENA_SHIFT, 0),
942SND_SOC_DAPM_AIF_IN("AIF2RX2", "AIF2 Playback", 1,
943 WM5100_AUDIO_IF_2_27, WM5100_AIF2RX2_ENA_SHIFT, 0),
944
945SND_SOC_DAPM_AIF_IN("AIF3RX1", "AIF3 Playback", 0,
946 WM5100_AUDIO_IF_3_27, WM5100_AIF3RX1_ENA_SHIFT, 0),
947SND_SOC_DAPM_AIF_IN("AIF3RX2", "AIF3 Playback", 1,
948 WM5100_AUDIO_IF_3_27, WM5100_AIF3RX2_ENA_SHIFT, 0),
949
950SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 0,
951 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX1_ENA_SHIFT, 0),
952SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 1,
953 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX2_ENA_SHIFT, 0),
954SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 2,
955 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX3_ENA_SHIFT, 0),
956SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 3,
957 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX4_ENA_SHIFT, 0),
958SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 4,
959 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX5_ENA_SHIFT, 0),
960SND_SOC_DAPM_AIF_OUT("AIF1TX6", "AIF1 Capture", 5,
961 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX6_ENA_SHIFT, 0),
962SND_SOC_DAPM_AIF_OUT("AIF1TX7", "AIF1 Capture", 6,
963 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX7_ENA_SHIFT, 0),
964SND_SOC_DAPM_AIF_OUT("AIF1TX8", "AIF1 Capture", 7,
965 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX8_ENA_SHIFT, 0),
966
967SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
968 WM5100_AUDIO_IF_2_26, WM5100_AIF2TX1_ENA_SHIFT, 0),
969SND_SOC_DAPM_AIF_OUT("AIF2TX2", "AIF2 Capture", 1,
970 WM5100_AUDIO_IF_2_26, WM5100_AIF2TX2_ENA_SHIFT, 0),
971
972SND_SOC_DAPM_AIF_OUT("AIF3TX1", "AIF3 Capture", 0,
973 WM5100_AUDIO_IF_3_26, WM5100_AIF3TX1_ENA_SHIFT, 0),
974SND_SOC_DAPM_AIF_OUT("AIF3TX2", "AIF3 Capture", 1,
975 WM5100_AUDIO_IF_3_26, WM5100_AIF3TX2_ENA_SHIFT, 0),
976
977SND_SOC_DAPM_PGA_E("OUT6L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6L_ENA_SHIFT, 0,
978 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
979SND_SOC_DAPM_PGA_E("OUT6R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6R_ENA_SHIFT, 0,
980 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
981SND_SOC_DAPM_PGA_E("OUT5L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5L_ENA_SHIFT, 0,
982 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
983SND_SOC_DAPM_PGA_E("OUT5R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5R_ENA_SHIFT, 0,
984 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
985SND_SOC_DAPM_PGA_E("OUT4L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4L_ENA_SHIFT, 0,
986 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
987SND_SOC_DAPM_PGA_E("OUT4R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4R_ENA_SHIFT, 0,
988 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
989SND_SOC_DAPM_PGA_E("OUT3L", WM5100_CHANNEL_ENABLES_1, WM5100_HP3L_ENA_SHIFT, 0,
990 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
991SND_SOC_DAPM_PGA_E("OUT3R", WM5100_CHANNEL_ENABLES_1, WM5100_HP3R_ENA_SHIFT, 0,
992 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
993SND_SOC_DAPM_PGA_E("OUT2L", WM5100_CHANNEL_ENABLES_1, WM5100_HP2L_ENA_SHIFT, 0,
994 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
995SND_SOC_DAPM_PGA_E("OUT2R", WM5100_CHANNEL_ENABLES_1, WM5100_HP2R_ENA_SHIFT, 0,
996 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
997SND_SOC_DAPM_PGA_E("OUT1L", WM5100_CHANNEL_ENABLES_1, WM5100_HP1L_ENA_SHIFT, 0,
998 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
999SND_SOC_DAPM_PGA_E("OUT1R", WM5100_CHANNEL_ENABLES_1, WM5100_HP1R_ENA_SHIFT, 0,
1000 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1001SND_SOC_DAPM_PGA_E("PWM1 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM1_ENA_SHIFT, 0,
1002 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1003SND_SOC_DAPM_PGA_E("PWM2 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM2_ENA_SHIFT, 0,
1004 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1005
1006SND_SOC_DAPM_PGA("EQ1", WM5100_EQ1_1, WM5100_EQ1_ENA_SHIFT, 0, NULL, 0),
1007SND_SOC_DAPM_PGA("EQ2", WM5100_EQ2_1, WM5100_EQ2_ENA_SHIFT, 0, NULL, 0),
1008SND_SOC_DAPM_PGA("EQ3", WM5100_EQ3_1, WM5100_EQ3_ENA_SHIFT, 0, NULL, 0),
1009SND_SOC_DAPM_PGA("EQ4", WM5100_EQ4_1, WM5100_EQ4_ENA_SHIFT, 0, NULL, 0),
1010
1011SND_SOC_DAPM_PGA("DRC1L", WM5100_DRC1_CTRL1, WM5100_DRCL_ENA_SHIFT, 0,
1012 NULL, 0),
1013SND_SOC_DAPM_PGA("DRC1R", WM5100_DRC1_CTRL1, WM5100_DRCR_ENA_SHIFT, 0,
1014 NULL, 0),
1015
1016SND_SOC_DAPM_PGA("LHPF1", WM5100_HPLPF1_1, WM5100_LHPF1_ENA_SHIFT, 0,
1017 NULL, 0),
1018SND_SOC_DAPM_PGA("LHPF2", WM5100_HPLPF2_1, WM5100_LHPF2_ENA_SHIFT, 0,
1019 NULL, 0),
1020SND_SOC_DAPM_PGA("LHPF3", WM5100_HPLPF3_1, WM5100_LHPF3_ENA_SHIFT, 0,
1021 NULL, 0),
1022SND_SOC_DAPM_PGA("LHPF4", WM5100_HPLPF4_1, WM5100_LHPF4_ENA_SHIFT, 0,
1023 NULL, 0),
1024
1025WM5100_MIXER_WIDGETS(EQ1, "EQ1"),
1026WM5100_MIXER_WIDGETS(EQ2, "EQ2"),
1027WM5100_MIXER_WIDGETS(EQ3, "EQ3"),
1028WM5100_MIXER_WIDGETS(EQ4, "EQ4"),
1029
1030WM5100_MIXER_WIDGETS(DRC1L, "DRC1L"),
1031WM5100_MIXER_WIDGETS(DRC1R, "DRC1R"),
1032
1033WM5100_MIXER_WIDGETS(LHPF1, "LHPF1"),
1034WM5100_MIXER_WIDGETS(LHPF2, "LHPF2"),
1035WM5100_MIXER_WIDGETS(LHPF3, "LHPF3"),
1036WM5100_MIXER_WIDGETS(LHPF4, "LHPF4"),
1037
1038WM5100_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1039WM5100_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1040WM5100_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1041WM5100_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1042WM5100_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1043WM5100_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1044WM5100_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
1045WM5100_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
1046
1047WM5100_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
1048WM5100_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
1049
1050WM5100_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
1051WM5100_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
1052
1053WM5100_MIXER_WIDGETS(HPOUT1L, "HPOUT1L"),
1054WM5100_MIXER_WIDGETS(HPOUT1R, "HPOUT1R"),
1055WM5100_MIXER_WIDGETS(HPOUT2L, "HPOUT2L"),
1056WM5100_MIXER_WIDGETS(HPOUT2R, "HPOUT2R"),
1057WM5100_MIXER_WIDGETS(HPOUT3L, "HPOUT3L"),
1058WM5100_MIXER_WIDGETS(HPOUT3R, "HPOUT3R"),
1059
1060WM5100_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
1061WM5100_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
1062WM5100_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
1063WM5100_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
1064WM5100_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"),
1065WM5100_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"),
1066
1067WM5100_MIXER_WIDGETS(PWM1, "PWM1"),
1068WM5100_MIXER_WIDGETS(PWM2, "PWM2"),
1069
1070SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1071SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1072SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1073SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1074SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1075SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1076SND_SOC_DAPM_OUTPUT("SPKOUTL"),
1077SND_SOC_DAPM_OUTPUT("SPKOUTR"),
1078SND_SOC_DAPM_OUTPUT("SPKDAT1"),
1079SND_SOC_DAPM_OUTPUT("SPKDAT2"),
1080SND_SOC_DAPM_OUTPUT("PWM1"),
1081SND_SOC_DAPM_OUTPUT("PWM2"),
1082};
1083
1084/* We register a _POST event if we don't have IRQ support so we can
1085 * look at the error status from the CODEC - if we've got the IRQ
1086 * hooked up then we will get prompted to look by an interrupt.
1087 */
1088static const struct snd_soc_dapm_widget wm5100_dapm_widgets_noirq[] = {
1089SND_SOC_DAPM_POST("Post", wm5100_post_ev),
1090};
1091
1092static const struct snd_soc_dapm_route wm5100_dapm_routes[] = {
1093 { "IN1L", NULL, "SYSCLK" },
1094 { "IN1R", NULL, "SYSCLK" },
1095 { "IN2L", NULL, "SYSCLK" },
1096 { "IN2R", NULL, "SYSCLK" },
1097 { "IN3L", NULL, "SYSCLK" },
1098 { "IN3R", NULL, "SYSCLK" },
1099 { "IN4L", NULL, "SYSCLK" },
1100 { "IN4R", NULL, "SYSCLK" },
1101
1102 { "OUT1L", NULL, "SYSCLK" },
1103 { "OUT1R", NULL, "SYSCLK" },
1104 { "OUT2L", NULL, "SYSCLK" },
1105 { "OUT2R", NULL, "SYSCLK" },
1106 { "OUT3L", NULL, "SYSCLK" },
1107 { "OUT3R", NULL, "SYSCLK" },
1108 { "OUT4L", NULL, "SYSCLK" },
1109 { "OUT4R", NULL, "SYSCLK" },
1110 { "OUT5L", NULL, "SYSCLK" },
1111 { "OUT5R", NULL, "SYSCLK" },
1112 { "OUT6L", NULL, "SYSCLK" },
1113 { "OUT6R", NULL, "SYSCLK" },
1114
1115 { "AIF1RX1", NULL, "SYSCLK" },
1116 { "AIF1RX2", NULL, "SYSCLK" },
1117 { "AIF1RX3", NULL, "SYSCLK" },
1118 { "AIF1RX4", NULL, "SYSCLK" },
1119 { "AIF1RX5", NULL, "SYSCLK" },
1120 { "AIF1RX6", NULL, "SYSCLK" },
1121 { "AIF1RX7", NULL, "SYSCLK" },
1122 { "AIF1RX8", NULL, "SYSCLK" },
1123
1124 { "AIF2RX1", NULL, "SYSCLK" },
1125 { "AIF2RX2", NULL, "SYSCLK" },
1126
1127 { "AIF3RX1", NULL, "SYSCLK" },
1128 { "AIF3RX2", NULL, "SYSCLK" },
1129
1130 { "AIF1TX1", NULL, "SYSCLK" },
1131 { "AIF1TX2", NULL, "SYSCLK" },
1132 { "AIF1TX3", NULL, "SYSCLK" },
1133 { "AIF1TX4", NULL, "SYSCLK" },
1134 { "AIF1TX5", NULL, "SYSCLK" },
1135 { "AIF1TX6", NULL, "SYSCLK" },
1136 { "AIF1TX7", NULL, "SYSCLK" },
1137 { "AIF1TX8", NULL, "SYSCLK" },
1138
1139 { "AIF2TX1", NULL, "SYSCLK" },
1140 { "AIF2TX2", NULL, "SYSCLK" },
1141
1142 { "AIF3TX1", NULL, "SYSCLK" },
1143 { "AIF3TX2", NULL, "SYSCLK" },
1144
1145 { "MICBIAS1", NULL, "CP2" },
1146 { "MICBIAS2", NULL, "CP2" },
1147 { "MICBIAS3", NULL, "CP2" },
1148
1149 { "IN1L PGA", NULL, "CP2" },
1150 { "IN1R PGA", NULL, "CP2" },
1151 { "IN2L PGA", NULL, "CP2" },
1152 { "IN2R PGA", NULL, "CP2" },
1153 { "IN3L PGA", NULL, "CP2" },
1154 { "IN3R PGA", NULL, "CP2" },
1155 { "IN4L PGA", NULL, "CP2" },
1156 { "IN4R PGA", NULL, "CP2" },
1157
1158 { "IN1L PGA", NULL, "CP2 Active" },
1159 { "IN1R PGA", NULL, "CP2 Active" },
1160 { "IN2L PGA", NULL, "CP2 Active" },
1161 { "IN2R PGA", NULL, "CP2 Active" },
1162 { "IN3L PGA", NULL, "CP2 Active" },
1163 { "IN3R PGA", NULL, "CP2 Active" },
1164 { "IN4L PGA", NULL, "CP2 Active" },
1165 { "IN4R PGA", NULL, "CP2 Active" },
1166
1167 { "OUT1L", NULL, "CP1" },
1168 { "OUT1R", NULL, "CP1" },
1169 { "OUT2L", NULL, "CP1" },
1170 { "OUT2R", NULL, "CP1" },
1171 { "OUT3L", NULL, "CP1" },
1172 { "OUT3R", NULL, "CP1" },
1173
1174 { "Tone Generator 1", NULL, "TONE" },
1175 { "Tone Generator 2", NULL, "TONE" },
1176
1177 { "IN1L PGA", NULL, "IN1L" },
1178 { "IN1R PGA", NULL, "IN1R" },
1179 { "IN2L PGA", NULL, "IN2L" },
1180 { "IN2R PGA", NULL, "IN2R" },
1181 { "IN3L PGA", NULL, "IN3L" },
1182 { "IN3R PGA", NULL, "IN3R" },
1183 { "IN4L PGA", NULL, "IN4L" },
1184 { "IN4R PGA", NULL, "IN4R" },
1185
1186 WM5100_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1187 WM5100_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1188 WM5100_MIXER_ROUTES("OUT2L", "HPOUT2L"),
1189 WM5100_MIXER_ROUTES("OUT2R", "HPOUT2R"),
1190 WM5100_MIXER_ROUTES("OUT3L", "HPOUT3L"),
1191 WM5100_MIXER_ROUTES("OUT3R", "HPOUT3R"),
1192
1193 WM5100_MIXER_ROUTES("OUT4L", "SPKOUTL"),
1194 WM5100_MIXER_ROUTES("OUT4R", "SPKOUTR"),
1195 WM5100_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1196 WM5100_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1197 WM5100_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
1198 WM5100_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
1199
1200 WM5100_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1201 WM5100_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1202
1203 WM5100_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1204 WM5100_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1205 WM5100_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1206 WM5100_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1207 WM5100_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1208 WM5100_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1209 WM5100_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
1210 WM5100_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
1211
1212 WM5100_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1213 WM5100_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1214
1215 WM5100_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1216 WM5100_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1217
1218 WM5100_MIXER_ROUTES("EQ1", "EQ1"),
1219 WM5100_MIXER_ROUTES("EQ2", "EQ2"),
1220 WM5100_MIXER_ROUTES("EQ3", "EQ3"),
1221 WM5100_MIXER_ROUTES("EQ4", "EQ4"),
1222
1223 WM5100_MIXER_ROUTES("DRC1L", "DRC1L"),
1224 WM5100_MIXER_ROUTES("DRC1R", "DRC1R"),
1225
1226 WM5100_MIXER_ROUTES("LHPF1", "LHPF1"),
1227 WM5100_MIXER_ROUTES("LHPF2", "LHPF2"),
1228 WM5100_MIXER_ROUTES("LHPF3", "LHPF3"),
1229 WM5100_MIXER_ROUTES("LHPF4", "LHPF4"),
1230
1231 { "HPOUT1L", NULL, "OUT1L" },
1232 { "HPOUT1R", NULL, "OUT1R" },
1233 { "HPOUT2L", NULL, "OUT2L" },
1234 { "HPOUT2R", NULL, "OUT2R" },
1235 { "HPOUT3L", NULL, "OUT3L" },
1236 { "HPOUT3R", NULL, "OUT3R" },
1237 { "SPKOUTL", NULL, "OUT4L" },
1238 { "SPKOUTR", NULL, "OUT4R" },
1239 { "SPKDAT1", NULL, "OUT5L" },
1240 { "SPKDAT1", NULL, "OUT5R" },
1241 { "SPKDAT2", NULL, "OUT6L" },
1242 { "SPKDAT2", NULL, "OUT6R" },
1243 { "PWM1", NULL, "PWM1 Driver" },
1244 { "PWM2", NULL, "PWM2 Driver" },
1245};
1246
1247static struct {
1248 int reg;
1249 int val;
1250} wm5100_reva_patches[] = {
1251 { WM5100_AUDIO_IF_1_10, 0 },
1252 { WM5100_AUDIO_IF_1_11, 1 },
1253 { WM5100_AUDIO_IF_1_12, 2 },
1254 { WM5100_AUDIO_IF_1_13, 3 },
1255 { WM5100_AUDIO_IF_1_14, 4 },
1256 { WM5100_AUDIO_IF_1_15, 5 },
1257 { WM5100_AUDIO_IF_1_16, 6 },
1258 { WM5100_AUDIO_IF_1_17, 7 },
1259
1260 { WM5100_AUDIO_IF_1_18, 0 },
1261 { WM5100_AUDIO_IF_1_19, 1 },
1262 { WM5100_AUDIO_IF_1_20, 2 },
1263 { WM5100_AUDIO_IF_1_21, 3 },
1264 { WM5100_AUDIO_IF_1_22, 4 },
1265 { WM5100_AUDIO_IF_1_23, 5 },
1266 { WM5100_AUDIO_IF_1_24, 6 },
1267 { WM5100_AUDIO_IF_1_25, 7 },
1268
1269 { WM5100_AUDIO_IF_2_10, 0 },
1270 { WM5100_AUDIO_IF_2_11, 1 },
1271
1272 { WM5100_AUDIO_IF_2_18, 0 },
1273 { WM5100_AUDIO_IF_2_19, 1 },
1274
1275 { WM5100_AUDIO_IF_3_10, 0 },
1276 { WM5100_AUDIO_IF_3_11, 1 },
1277
1278 { WM5100_AUDIO_IF_3_18, 0 },
1279 { WM5100_AUDIO_IF_3_19, 1 },
1280};
1281
1282static int wm5100_set_bias_level(struct snd_soc_codec *codec,
1283 enum snd_soc_bias_level level)
1284{
1285 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1286 int ret, i;
1287
1288 switch (level) {
1289 case SND_SOC_BIAS_ON:
1290 break;
1291
1292 case SND_SOC_BIAS_PREPARE:
1293 break;
1294
1295 case SND_SOC_BIAS_STANDBY:
1296 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1297 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
1298 wm5100->core_supplies);
1299 if (ret != 0) {
1300 dev_err(codec->dev,
1301 "Failed to enable supplies: %d\n",
1302 ret);
1303 return ret;
1304 }
1305
1306 if (wm5100->pdata.ldo_ena) {
1307 gpio_set_value_cansleep(wm5100->pdata.ldo_ena,
1308 1);
1309 msleep(2);
1310 }
1311
1312 codec->cache_only = false;
1313
1314 switch (wm5100->rev) {
1315 case 0:
1316 snd_soc_write(codec, 0x11, 0x3);
1317 snd_soc_write(codec, 0x203, 0xc);
1318 snd_soc_write(codec, 0x206, 0);
1319 snd_soc_write(codec, 0x207, 0xf0);
1320 snd_soc_write(codec, 0x208, 0x3c);
1321 snd_soc_write(codec, 0x209, 0);
1322 snd_soc_write(codec, 0x211, 0x20d8);
1323 snd_soc_write(codec, 0x11, 0);
1324
1325 for (i = 0;
1326 i < ARRAY_SIZE(wm5100_reva_patches);
1327 i++)
1328 snd_soc_write(codec,
1329 wm5100_reva_patches[i].reg,
1330 wm5100_reva_patches[i].val);
1331 break;
1332 default:
1333 break;
1334 }
1335
1336 snd_soc_cache_sync(codec);
1337 }
1338 break;
1339
1340 case SND_SOC_BIAS_OFF:
1341 if (wm5100->pdata.ldo_ena)
1342 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
1343 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
1344 wm5100->core_supplies);
1345 break;
1346 }
1347 codec->dapm.bias_level = level;
1348
1349 return 0;
1350}
1351
1352static int wm5100_dai_to_base(struct snd_soc_dai *dai)
1353{
1354 switch (dai->id) {
1355 case 0:
1356 return WM5100_AUDIO_IF_1_1 - 1;
1357 case 1:
1358 return WM5100_AUDIO_IF_2_1 - 1;
1359 case 2:
1360 return WM5100_AUDIO_IF_3_1 - 1;
1361 default:
1362 BUG();
1363 return -EINVAL;
1364 }
1365}
1366
1367static int wm5100_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1368{
1369 struct snd_soc_codec *codec = dai->codec;
1370 int lrclk, bclk, mask, base;
1371
1372 base = wm5100_dai_to_base(dai);
1373 if (base < 0)
1374 return base;
1375
1376 lrclk = 0;
1377 bclk = 0;
1378
1379 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1380 case SND_SOC_DAIFMT_DSP_A:
1381 mask = 0;
1382 break;
1383 case SND_SOC_DAIFMT_DSP_B:
1384 mask = 1;
1385 break;
1386 case SND_SOC_DAIFMT_I2S:
1387 mask = 2;
1388 break;
1389 case SND_SOC_DAIFMT_LEFT_J:
1390 mask = 3;
1391 break;
1392 default:
1393 dev_err(codec->dev, "Unsupported DAI format %d\n",
1394 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1395 return -EINVAL;
1396 }
1397
1398 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1399 case SND_SOC_DAIFMT_CBS_CFS:
1400 break;
1401 case SND_SOC_DAIFMT_CBS_CFM:
1402 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1403 break;
1404 case SND_SOC_DAIFMT_CBM_CFS:
1405 bclk |= WM5100_AIF1_BCLK_MSTR;
1406 break;
1407 case SND_SOC_DAIFMT_CBM_CFM:
1408 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1409 bclk |= WM5100_AIF1_BCLK_MSTR;
1410 break;
1411 default:
1412 dev_err(codec->dev, "Unsupported master mode %d\n",
1413 fmt & SND_SOC_DAIFMT_MASTER_MASK);
1414 return -EINVAL;
1415 }
1416
1417 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1418 case SND_SOC_DAIFMT_NB_NF:
1419 break;
1420 case SND_SOC_DAIFMT_IB_IF:
1421 bclk |= WM5100_AIF1_BCLK_INV;
1422 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1423 break;
1424 case SND_SOC_DAIFMT_IB_NF:
1425 bclk |= WM5100_AIF1_BCLK_INV;
1426 break;
1427 case SND_SOC_DAIFMT_NB_IF:
1428 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1429 break;
1430 default:
1431 return -EINVAL;
1432 }
1433
1434 snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_MSTR |
1435 WM5100_AIF1_BCLK_INV, bclk);
1436 snd_soc_update_bits(codec, base + 2, WM5100_AIF1TX_LRCLK_MSTR |
1437 WM5100_AIF1TX_LRCLK_INV, lrclk);
1438 snd_soc_update_bits(codec, base + 3, WM5100_AIF1TX_LRCLK_MSTR |
1439 WM5100_AIF1TX_LRCLK_INV, lrclk);
1440 snd_soc_update_bits(codec, base + 5, WM5100_AIF1_FMT_MASK, mask);
1441
1442 return 0;
1443}
1444
1445#define WM5100_NUM_BCLK_RATES 19
1446
1447static int wm5100_bclk_rates_dat[WM5100_NUM_BCLK_RATES] = {
1448 32000,
1449 48000,
1450 64000,
1451 96000,
1452 128000,
1453 192000,
1454 384000,
1455 512000,
1456 768000,
1457 1024000,
1458 1536000,
1459 2048000,
1460 3072000,
1461 4096000,
1462 6144000,
1463 8192000,
1464 12288000,
1465 24576000,
1466};
1467
1468static int wm5100_bclk_rates_cd[WM5100_NUM_BCLK_RATES] = {
1469 29400,
1470 44100,
1471 58800,
1472 88200,
1473 117600,
1474 176400,
1475 235200,
1476 352800,
1477 470400,
1478 705600,
1479 940800,
1480 1411200,
1481 1881600,
1482 2882400,
1483 3763200,
1484 5644800,
1485 7526400,
1486 11289600,
1487 22579600,
1488};
1489
1490static int wm5100_hw_params(struct snd_pcm_substream *substream,
1491 struct snd_pcm_hw_params *params,
1492 struct snd_soc_dai *dai)
1493{
1494 struct snd_soc_codec *codec = dai->codec;
1495 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1496 bool async = wm5100->aif_async[dai->id];
1497 int i, base, bclk, aif_rate, lrclk, wl, fl, sr;
1498 int *bclk_rates;
1499
1500 base = wm5100_dai_to_base(dai);
1501 if (base < 0)
1502 return base;
1503
1504 /* Data sizes if not using TDM */
1505 wl = snd_pcm_format_width(params_format(params));
1506 if (wl < 0)
1507 return wl;
1508 fl = snd_soc_params_to_frame_size(params);
1509 if (fl < 0)
1510 return fl;
1511
1512 dev_dbg(codec->dev, "Word length %d bits, frame length %d bits\n",
1513 wl, fl);
1514
1515 /* Target BCLK rate */
1516 bclk = snd_soc_params_to_bclk(params);
1517 if (bclk < 0)
1518 return bclk;
1519
1520 /* Root for BCLK depends on SYS/ASYNCCLK */
1521 if (!async) {
1522 aif_rate = wm5100->sysclk;
1523 sr = wm5100_alloc_sr(codec, params_rate(params));
1524 if (sr < 0)
1525 return sr;
1526 } else {
1527 /* If we're in ASYNCCLK set the ASYNC sample rate */
1528 aif_rate = wm5100->asyncclk;
1529 sr = 3;
1530
1531 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
1532 if (params_rate(params) == wm5100_sr_code[i])
1533 break;
1534 if (i == ARRAY_SIZE(wm5100_sr_code)) {
1535 dev_err(codec->dev, "Invalid rate %dHzn",
1536 params_rate(params));
1537 return -EINVAL;
1538 }
1539
1540 /* TODO: We should really check for symmetry */
1541 snd_soc_update_bits(codec, WM5100_CLOCKING_8,
1542 WM5100_ASYNC_SAMPLE_RATE_MASK, i);
1543 }
1544
1545 if (!aif_rate) {
1546 dev_err(codec->dev, "%s has no rate set\n",
1547 async ? "ASYNCCLK" : "SYSCLK");
1548 return -EINVAL;
1549 }
1550
1551 dev_dbg(codec->dev, "Target BCLK is %dHz, using %dHz %s\n",
1552 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1553
1554 if (aif_rate % 4000)
1555 bclk_rates = wm5100_bclk_rates_cd;
1556 else
1557 bclk_rates = wm5100_bclk_rates_dat;
1558
1559 for (i = 0; i < WM5100_NUM_BCLK_RATES; i++)
1560 if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
1561 break;
1562 if (i == WM5100_NUM_BCLK_RATES) {
1563 dev_err(codec->dev,
1564 "No valid BCLK for %dHz found from %dHz %s\n",
1565 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1566 return -EINVAL;
1567 }
1568
1569 bclk = i;
1570 dev_dbg(codec->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1571 snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk);
1572
1573 lrclk = bclk_rates[bclk] / params_rate(params);
1574 dev_dbg(codec->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
1575 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1576 wm5100->aif_symmetric[dai->id])
1577 snd_soc_update_bits(codec, base + 7,
1578 WM5100_AIF1RX_BCPF_MASK, lrclk);
1579 else
1580 snd_soc_update_bits(codec, base + 6,
1581 WM5100_AIF1TX_BCPF_MASK, lrclk);
1582
1583 i = (wl << WM5100_AIF1TX_WL_SHIFT) | fl;
1584 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1585 snd_soc_update_bits(codec, base + 9,
1586 WM5100_AIF1RX_WL_MASK |
1587 WM5100_AIF1RX_SLOT_LEN_MASK, i);
1588 else
1589 snd_soc_update_bits(codec, base + 8,
1590 WM5100_AIF1TX_WL_MASK |
1591 WM5100_AIF1TX_SLOT_LEN_MASK, i);
1592
1593 snd_soc_update_bits(codec, base + 4, WM5100_AIF1_RATE_MASK, sr);
1594
1595 return 0;
1596}
1597
1598static struct snd_soc_dai_ops wm5100_dai_ops = {
1599 .set_fmt = wm5100_set_fmt,
1600 .hw_params = wm5100_hw_params,
1601};
1602
1603static int wm5100_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1604 int source, unsigned int freq, int dir)
1605{
1606 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1607 int *rate_store;
1608 int fval, audio_rate, ret, reg;
1609
1610 switch (clk_id) {
1611 case WM5100_CLK_SYSCLK:
1612 reg = WM5100_CLOCKING_3;
1613 rate_store = &wm5100->sysclk;
1614 break;
1615 case WM5100_CLK_ASYNCCLK:
1616 reg = WM5100_CLOCKING_7;
1617 rate_store = &wm5100->asyncclk;
1618 break;
1619 case WM5100_CLK_32KHZ:
1620 /* The 32kHz clock is slightly different to the others */
1621 switch (source) {
1622 case WM5100_CLKSRC_MCLK1:
1623 case WM5100_CLKSRC_MCLK2:
1624 case WM5100_CLKSRC_SYSCLK:
1625 snd_soc_update_bits(codec, WM5100_CLOCKING_1,
1626 WM5100_CLK_32K_SRC_MASK,
1627 source);
1628 break;
1629 default:
1630 return -EINVAL;
1631 }
1632 return 0;
1633
1634 case WM5100_CLK_AIF1:
1635 case WM5100_CLK_AIF2:
1636 case WM5100_CLK_AIF3:
1637 /* Not real clocks, record which clock domain they're in */
1638 switch (source) {
1639 case WM5100_CLKSRC_SYSCLK:
1640 wm5100->aif_async[clk_id - 1] = false;
1641 break;
1642 case WM5100_CLKSRC_ASYNCCLK:
1643 wm5100->aif_async[clk_id - 1] = true;
1644 break;
1645 default:
1646 dev_err(codec->dev, "Invalid source %d\n", source);
1647 return -EINVAL;
1648 }
1649 return 0;
1650
1651 case WM5100_CLK_OPCLK:
1652 switch (freq) {
1653 case 5644800:
1654 case 6144000:
1655 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1656 WM5100_OPCLK_SEL_MASK, 0);
1657 break;
1658 case 11289600:
1659 case 12288000:
1660 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1661 WM5100_OPCLK_SEL_MASK, 0);
1662 break;
1663 case 22579200:
1664 case 24576000:
1665 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1666 WM5100_OPCLK_SEL_MASK, 0);
1667 break;
1668 default:
1669 dev_err(codec->dev, "Unsupported OPCLK %dHz\n",
1670 freq);
1671 return -EINVAL;
1672 }
1673 return 0;
1674
1675 default:
1676 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
1677 return -EINVAL;
1678 }
1679
1680 switch (source) {
1681 case WM5100_CLKSRC_SYSCLK:
1682 case WM5100_CLKSRC_ASYNCCLK:
1683 dev_err(codec->dev, "Invalid source %d\n", source);
1684 return -EINVAL;
1685 }
1686
1687 switch (freq) {
1688 case 5644800:
1689 case 6144000:
1690 fval = 0;
1691 break;
1692 case 11289600:
1693 case 12288000:
1694 fval = 1;
1695 break;
1696 case 22579200:
1697 case 2457600:
1698 fval = 2;
1699 break;
1700 default:
1701 dev_err(codec->dev, "Invalid clock rate: %d\n", freq);
1702 return -EINVAL;
1703 }
1704
1705 switch (freq) {
1706 case 5644800:
1707 case 11289600:
1708 case 22579200:
1709 audio_rate = 44100;
1710 break;
1711
1712 case 6144000:
1713 case 12288000:
1714 case 2457600:
1715 audio_rate = 48000;
1716 break;
1717
1718 default:
1719 BUG();
1720 audio_rate = 0;
1721 break;
1722 }
1723
1724 /* TODO: Check if MCLKs are in use and enable/disable pulls to
1725 * match.
1726 */
1727
1728 snd_soc_update_bits(codec, reg, WM5100_SYSCLK_FREQ_MASK |
1729 WM5100_SYSCLK_SRC_MASK,
1730 fval << WM5100_SYSCLK_FREQ_SHIFT | source);
1731
1732 /* If this is SYSCLK then configure the clock rate for the
1733 * internal audio functions to the natural sample rate for
1734 * this clock rate.
1735 */
1736 if (clk_id == WM5100_CLK_SYSCLK) {
1737 dev_dbg(codec->dev, "Setting primary audio rate to %dHz",
1738 audio_rate);
1739 if (0 && *rate_store)
1740 wm5100_free_sr(codec, audio_rate);
1741 ret = wm5100_alloc_sr(codec, audio_rate);
1742 if (ret != 0)
1743 dev_warn(codec->dev, "Primary audio slot is %d\n",
1744 ret);
1745 }
1746
1747 *rate_store = freq;
1748
1749 return 0;
1750}
1751
1752struct _fll_div {
1753 u16 fll_fratio;
1754 u16 fll_outdiv;
1755 u16 fll_refclk_div;
1756 u16 n;
1757 u16 theta;
1758 u16 lambda;
1759};
1760
1761static struct {
1762 unsigned int min;
1763 unsigned int max;
1764 u16 fll_fratio;
1765 int ratio;
1766} fll_fratios[] = {
1767 { 0, 64000, 4, 16 },
1768 { 64000, 128000, 3, 8 },
1769 { 128000, 256000, 2, 4 },
1770 { 256000, 1000000, 1, 2 },
1771 { 1000000, 13500000, 0, 1 },
1772};
1773
1774static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1775 unsigned int Fout)
1776{
1777 unsigned int target;
1778 unsigned int div;
1779 unsigned int fratio, gcd_fll;
1780 int i;
1781
1782 /* Fref must be <=13.5MHz */
1783 div = 1;
1784 fll_div->fll_refclk_div = 0;
1785 while ((Fref / div) > 13500000) {
1786 div *= 2;
1787 fll_div->fll_refclk_div++;
1788
1789 if (div > 8) {
1790 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1791 Fref);
1792 return -EINVAL;
1793 }
1794 }
1795
1796 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1797
1798 /* Apply the division for our remaining calculations */
1799 Fref /= div;
1800
1801 /* Fvco should be 90-100MHz; don't check the upper bound */
1802 div = 2;
1803 while (Fout * div < 90000000) {
1804 div++;
1805 if (div > 64) {
1806 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1807 Fout);
1808 return -EINVAL;
1809 }
1810 }
1811 target = Fout * div;
1812 fll_div->fll_outdiv = div - 1;
1813
1814 pr_debug("FLL Fvco=%dHz\n", target);
1815
1816 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1817 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1818 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1819 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1820 fratio = fll_fratios[i].ratio;
1821 break;
1822 }
1823 }
1824 if (i == ARRAY_SIZE(fll_fratios)) {
1825 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1826 return -EINVAL;
1827 }
1828
1829 fll_div->n = target / (fratio * Fref);
1830
1831 if (target % Fref == 0) {
1832 fll_div->theta = 0;
1833 fll_div->lambda = 0;
1834 } else {
1835 gcd_fll = gcd(target, fratio * Fref);
1836
1837 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1838 / gcd_fll;
1839 fll_div->lambda = (fratio * Fref) / gcd_fll;
1840 }
1841
1842 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1843 fll_div->n, fll_div->theta, fll_div->lambda);
1844 pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1845 fll_div->fll_fratio, fratio, fll_div->fll_outdiv,
1846 fll_div->fll_refclk_div);
1847
1848 return 0;
1849}
1850
1851static int wm5100_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
1852 unsigned int Fref, unsigned int Fout)
1853{
1854 struct i2c_client *i2c = to_i2c_client(codec->dev);
1855 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1856 struct _fll_div factors;
1857 struct wm5100_fll *fll;
1858 int ret, base, lock, i, timeout;
1859
1860 switch (fll_id) {
1861 case WM5100_FLL1:
1862 fll = &wm5100->fll[0];
1863 base = WM5100_FLL1_CONTROL_1 - 1;
1864 lock = WM5100_FLL1_LOCK_STS;
1865 break;
1866 case WM5100_FLL2:
1867 fll = &wm5100->fll[1];
1868 base = WM5100_FLL2_CONTROL_2 - 1;
1869 lock = WM5100_FLL2_LOCK_STS;
1870 break;
1871 default:
1872 dev_err(codec->dev, "Unknown FLL %d\n",fll_id);
1873 return -EINVAL;
1874 }
1875
1876 if (!Fout) {
1877 dev_dbg(codec->dev, "FLL%d disabled", fll_id);
1878 fll->fout = 0;
1879 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1880 return 0;
1881 }
1882
1883 switch (source) {
1884 case WM5100_FLL_SRC_MCLK1:
1885 case WM5100_FLL_SRC_MCLK2:
1886 case WM5100_FLL_SRC_FLL1:
1887 case WM5100_FLL_SRC_FLL2:
1888 case WM5100_FLL_SRC_AIF1BCLK:
1889 case WM5100_FLL_SRC_AIF2BCLK:
1890 case WM5100_FLL_SRC_AIF3BCLK:
1891 break;
1892 default:
1893 dev_err(codec->dev, "Invalid FLL source %d\n", source);
1894 return -EINVAL;
1895 }
1896
1897 ret = fll_factors(&factors, Fref, Fout);
1898 if (ret < 0)
1899 return ret;
1900
1901 /* Disable the FLL while we reconfigure */
1902 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1903
1904 snd_soc_update_bits(codec, base + 2,
1905 WM5100_FLL1_OUTDIV_MASK | WM5100_FLL1_FRATIO_MASK,
1906 (factors.fll_outdiv << WM5100_FLL1_OUTDIV_SHIFT) |
1907 factors.fll_fratio);
1908 snd_soc_update_bits(codec, base + 3, WM5100_FLL1_THETA_MASK,
1909 factors.theta);
1910 snd_soc_update_bits(codec, base + 5, WM5100_FLL1_N_MASK, factors.n);
1911 snd_soc_update_bits(codec, base + 6,
1912 WM5100_FLL1_REFCLK_DIV_MASK |
1913 WM5100_FLL1_REFCLK_SRC_MASK,
1914 (factors.fll_refclk_div
1915 << WM5100_FLL1_REFCLK_DIV_SHIFT) | source);
1916 snd_soc_update_bits(codec, base + 7, WM5100_FLL1_LAMBDA_MASK,
1917 factors.lambda);
1918
1919 /* Clear any pending completions */
1920 try_wait_for_completion(&fll->lock);
1921
1922 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, WM5100_FLL1_ENA);
1923
1924 if (i2c->irq)
1925 timeout = 2;
1926 else
1927 timeout = 50;
1928
1929 /* Poll for the lock; will use interrupt when we can test */
1930 for (i = 0; i < timeout; i++) {
1931 if (i2c->irq) {
1932 ret = wait_for_completion_timeout(&fll->lock,
1933 msecs_to_jiffies(25));
1934 if (ret > 0)
1935 break;
1936 } else {
1937 msleep(1);
1938 }
1939
1940 ret = snd_soc_read(codec,
1941 WM5100_INTERRUPT_RAW_STATUS_3);
1942 if (ret < 0) {
1943 dev_err(codec->dev,
1944 "Failed to read FLL status: %d\n",
1945 ret);
1946 continue;
1947 }
1948 if (ret & lock)
1949 break;
1950 }
1951 if (i == timeout) {
1952 dev_err(codec->dev, "FLL%d lock timed out\n", fll_id);
1953 return -ETIMEDOUT;
1954 }
1955
1956 fll->src = source;
1957 fll->fref = Fref;
1958 fll->fout = Fout;
1959
1960 dev_dbg(codec->dev, "FLL%d running %dHz->%dHz\n", fll_id,
1961 Fref, Fout);
1962
1963 return 0;
1964}
1965
1966/* Actually go much higher */
1967#define WM5100_RATES SNDRV_PCM_RATE_8000_192000
1968
1969#define WM5100_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1970 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1971
1972static struct snd_soc_dai_driver wm5100_dai[] = {
1973 {
1974 .name = "wm5100-aif1",
1975 .playback = {
1976 .stream_name = "AIF1 Playback",
1977 .channels_min = 2,
1978 .channels_max = 2,
1979 .rates = WM5100_RATES,
1980 .formats = WM5100_FORMATS,
1981 },
1982 .capture = {
1983 .stream_name = "AIF1 Capture",
1984 .channels_min = 2,
1985 .channels_max = 2,
1986 .rates = WM5100_RATES,
1987 .formats = WM5100_FORMATS,
1988 },
1989 .ops = &wm5100_dai_ops,
1990 },
1991 {
1992 .name = "wm5100-aif2",
1993 .id = 1,
1994 .playback = {
1995 .stream_name = "AIF2 Playback",
1996 .channels_min = 2,
1997 .channels_max = 2,
1998 .rates = WM5100_RATES,
1999 .formats = WM5100_FORMATS,
2000 },
2001 .capture = {
2002 .stream_name = "AIF2 Capture",
2003 .channels_min = 2,
2004 .channels_max = 2,
2005 .rates = WM5100_RATES,
2006 .formats = WM5100_FORMATS,
2007 },
2008 .ops = &wm5100_dai_ops,
2009 },
2010 {
2011 .name = "wm5100-aif3",
2012 .id = 2,
2013 .playback = {
2014 .stream_name = "AIF3 Playback",
2015 .channels_min = 2,
2016 .channels_max = 2,
2017 .rates = WM5100_RATES,
2018 .formats = WM5100_FORMATS,
2019 },
2020 .capture = {
2021 .stream_name = "AIF3 Capture",
2022 .channels_min = 2,
2023 .channels_max = 2,
2024 .rates = WM5100_RATES,
2025 .formats = WM5100_FORMATS,
2026 },
2027 .ops = &wm5100_dai_ops,
2028 },
2029};
2030
2031static int wm5100_dig_vu[] = {
2032 WM5100_ADC_DIGITAL_VOLUME_1L,
2033 WM5100_ADC_DIGITAL_VOLUME_1R,
2034 WM5100_ADC_DIGITAL_VOLUME_2L,
2035 WM5100_ADC_DIGITAL_VOLUME_2R,
2036 WM5100_ADC_DIGITAL_VOLUME_3L,
2037 WM5100_ADC_DIGITAL_VOLUME_3R,
2038 WM5100_ADC_DIGITAL_VOLUME_4L,
2039 WM5100_ADC_DIGITAL_VOLUME_4R,
2040
2041 WM5100_DAC_DIGITAL_VOLUME_1L,
2042 WM5100_DAC_DIGITAL_VOLUME_1R,
2043 WM5100_DAC_DIGITAL_VOLUME_2L,
2044 WM5100_DAC_DIGITAL_VOLUME_2R,
2045 WM5100_DAC_DIGITAL_VOLUME_3L,
2046 WM5100_DAC_DIGITAL_VOLUME_3R,
2047 WM5100_DAC_DIGITAL_VOLUME_4L,
2048 WM5100_DAC_DIGITAL_VOLUME_4R,
2049 WM5100_DAC_DIGITAL_VOLUME_5L,
2050 WM5100_DAC_DIGITAL_VOLUME_5R,
2051 WM5100_DAC_DIGITAL_VOLUME_6L,
2052 WM5100_DAC_DIGITAL_VOLUME_6R,
2053};
2054
2055static irqreturn_t wm5100_irq(int irq, void *data)
2056{
2057 struct snd_soc_codec *codec = data;
2058 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2059 irqreturn_t status = IRQ_NONE;
2060 int irq_val;
2061
2062 irq_val = snd_soc_read(codec, WM5100_INTERRUPT_STATUS_3);
2063 if (irq_val < 0) {
2064 dev_err(codec->dev, "Failed to read IRQ status 3: %d\n",
2065 irq_val);
2066 irq_val = 0;
2067 }
2068 irq_val &= ~snd_soc_read(codec, WM5100_INTERRUPT_STATUS_3_MASK);
2069
2070 snd_soc_write(codec, WM5100_INTERRUPT_STATUS_3, irq_val);
2071
2072 if (irq_val)
2073 status = IRQ_HANDLED;
2074
2075 wm5100_log_status3(codec, irq_val);
2076
2077 if (irq_val & WM5100_FLL1_LOCK_EINT) {
2078 dev_dbg(codec->dev, "FLL1 locked\n");
2079 complete(&wm5100->fll[0].lock);
2080 }
2081 if (irq_val & WM5100_FLL2_LOCK_EINT) {
2082 dev_dbg(codec->dev, "FLL2 locked\n");
2083 complete(&wm5100->fll[1].lock);
2084 }
2085
2086 irq_val = snd_soc_read(codec, WM5100_INTERRUPT_STATUS_4);
2087 if (irq_val < 0) {
2088 dev_err(codec->dev, "Failed to read IRQ status 4: %d\n",
2089 irq_val);
2090 irq_val = 0;
2091 }
2092 irq_val &= ~snd_soc_read(codec, WM5100_INTERRUPT_STATUS_4_MASK);
2093
2094 if (irq_val)
2095 status = IRQ_HANDLED;
2096
2097 snd_soc_write(codec, WM5100_INTERRUPT_STATUS_4, irq_val);
2098
2099 wm5100_log_status4(codec, irq_val);
2100
2101 return status;
2102}
2103
2104static irqreturn_t wm5100_edge_irq(int irq, void *data)
2105{
2106 irqreturn_t ret = IRQ_NONE;
2107 irqreturn_t val;
2108
2109 do {
2110 val = wm5100_irq(irq, data);
2111 if (val != IRQ_NONE)
2112 ret = val;
2113 } while (val != IRQ_NONE);
2114
2115 return ret;
2116}
2117
2118#ifdef CONFIG_GPIOLIB
2119static inline struct wm5100_priv *gpio_to_wm5100(struct gpio_chip *chip)
2120{
2121 return container_of(chip, struct wm5100_priv, gpio_chip);
2122}
2123
2124static void wm5100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2125{
2126 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2127 struct snd_soc_codec *codec = wm5100->codec;
2128
2129 snd_soc_update_bits(codec, WM5100_GPIO_CTRL_1 + offset,
2130 WM5100_GP1_LVL, !!value << WM5100_GP1_LVL_SHIFT);
2131}
2132
2133static int wm5100_gpio_direction_out(struct gpio_chip *chip,
2134 unsigned offset, int value)
2135{
2136 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2137 struct snd_soc_codec *codec = wm5100->codec;
2138 int val;
2139
2140 val = (1 << WM5100_GP1_FN_SHIFT) | (!!value << WM5100_GP1_LVL_SHIFT);
2141
2142 return snd_soc_update_bits(codec, WM5100_GPIO_CTRL_1 + offset,
2143 WM5100_GP1_FN_MASK | WM5100_GP1_DIR |
2144 WM5100_GP1_LVL, val);
2145}
2146
2147static int wm5100_gpio_get(struct gpio_chip *chip, unsigned offset)
2148{
2149 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2150 struct snd_soc_codec *codec = wm5100->codec;
2151 int ret;
2152
2153 ret = snd_soc_read(codec, WM5100_GPIO_CTRL_1 + offset);
2154 if (ret < 0)
2155 return ret;
2156
2157 return (ret & WM5100_GP1_LVL) != 0;
2158}
2159
2160static int wm5100_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2161{
2162 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2163 struct snd_soc_codec *codec = wm5100->codec;
2164
2165 return snd_soc_update_bits(codec, WM5100_GPIO_CTRL_1 + offset,
2166 WM5100_GP1_FN_MASK | WM5100_GP1_DIR,
2167 (1 << WM5100_GP1_FN_SHIFT) |
2168 (1 << WM5100_GP1_DIR_SHIFT));
2169}
2170
2171static struct gpio_chip wm5100_template_chip = {
2172 .label = "wm5100",
2173 .owner = THIS_MODULE,
2174 .direction_output = wm5100_gpio_direction_out,
2175 .set = wm5100_gpio_set,
2176 .direction_input = wm5100_gpio_direction_in,
2177 .get = wm5100_gpio_get,
2178 .can_sleep = 1,
2179};
2180
2181static void wm5100_init_gpio(struct snd_soc_codec *codec)
2182{
2183 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2184 int ret;
2185
2186 wm5100->gpio_chip = wm5100_template_chip;
2187 wm5100->gpio_chip.ngpio = 6;
2188 wm5100->gpio_chip.dev = codec->dev;
2189
2190 if (wm5100->pdata.gpio_base)
2191 wm5100->gpio_chip.base = wm5100->pdata.gpio_base;
2192 else
2193 wm5100->gpio_chip.base = -1;
2194
2195 ret = gpiochip_add(&wm5100->gpio_chip);
2196 if (ret != 0)
2197 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
2198}
2199
2200static void wm5100_free_gpio(struct snd_soc_codec *codec)
2201{
2202 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2203 int ret;
2204
2205 ret = gpiochip_remove(&wm5100->gpio_chip);
2206 if (ret != 0)
2207 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
2208}
2209#else
2210static void wm5100_init_gpio(struct snd_soc_codec *codec)
2211{
2212}
2213
2214static void wm5100_free_gpio(struct snd_soc_codec *codec)
2215{
2216}
2217#endif
2218
2219static int wm5100_probe(struct snd_soc_codec *codec)
2220{
2221 struct i2c_client *i2c = to_i2c_client(codec->dev);
2222 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2223 int ret, i, irq_flags;
2224
2225 wm5100->codec = codec;
2226
2227 codec->dapm.bias_level = SND_SOC_BIAS_OFF;
2228
2229 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
2230 if (ret != 0) {
2231 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2232 return ret;
2233 }
2234
2235 for (i = 0; i < ARRAY_SIZE(wm5100->core_supplies); i++)
2236 wm5100->core_supplies[i].supply = wm5100_core_supply_names[i];
2237
2238 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm5100->core_supplies),
2239 wm5100->core_supplies);
2240 if (ret != 0) {
2241 dev_err(codec->dev, "Failed to request core supplies: %d\n",
2242 ret);
2243 return ret;
2244 }
2245
2246 wm5100->cpvdd = regulator_get(&i2c->dev, "CPVDD");
2247 if (IS_ERR(wm5100->cpvdd)) {
2248 ret = PTR_ERR(wm5100->cpvdd);
2249 dev_err(&i2c->dev, "Failed to get CPVDD: %d\n", ret);
2250 goto err_core;
2251 }
2252
2253 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2254 wm5100->core_supplies);
2255 if (ret != 0) {
2256 dev_err(codec->dev, "Failed to enable core supplies: %d\n",
2257 ret);
2258 goto err_cpvdd;
2259 }
2260
2261 if (wm5100->pdata.ldo_ena) {
2262 ret = gpio_request_one(wm5100->pdata.ldo_ena,
2263 GPIOF_OUT_INIT_HIGH, "WM5100 LDOENA");
2264 if (ret < 0) {
2265 dev_err(&i2c->dev, "Failed to request LDOENA %d: %d\n",
2266 wm5100->pdata.ldo_ena, ret);
2267 goto err_enable;
2268 }
2269 msleep(2);
2270 }
2271
2272 if (wm5100->pdata.reset) {
2273 ret = gpio_request_one(wm5100->pdata.reset,
2274 GPIOF_OUT_INIT_HIGH, "WM5100 /RESET");
2275 if (ret < 0) {
2276 dev_err(&i2c->dev, "Failed to request /RESET %d: %d\n",
2277 wm5100->pdata.reset, ret);
2278 goto err_ldo;
2279 }
2280 }
2281
2282 ret = snd_soc_read(codec, WM5100_SOFTWARE_RESET);
2283 if (ret < 0) {
2284 dev_err(codec->dev, "Failed to read ID register\n");
2285 goto err_reset;
2286 }
2287 switch (ret) {
2288 case 0x8997:
2289 case 0x5100:
2290 break;
2291
2292 default:
2293 dev_err(codec->dev, "Device is not a WM5100, ID is %x\n", ret);
2294 ret = -EINVAL;
2295 goto err_reset;
2296 }
2297
2298 ret = snd_soc_read(codec, WM5100_DEVICE_REVISION);
2299 if (ret < 0) {
2300 dev_err(codec->dev, "Failed to read revision register\n");
2301 goto err_reset;
2302 }
2303 wm5100->rev = ret & WM5100_DEVICE_REVISION_MASK;
2304
2305 dev_info(codec->dev, "revision %c\n", wm5100->rev + 'A');
2306
2307 ret = wm5100_reset(codec);
2308 if (ret < 0) {
2309 dev_err(codec->dev, "Failed to issue reset\n");
2310 goto err_reset;
2311 }
2312
2313 codec->cache_only = true;
2314
2315 wm5100_init_gpio(codec);
2316
2317 for (i = 0; i < ARRAY_SIZE(wm5100_dig_vu); i++)
2318 snd_soc_update_bits(codec, wm5100_dig_vu[i], WM5100_OUT_VU,
2319 WM5100_OUT_VU);
2320
2321 for (i = 0; i < ARRAY_SIZE(wm5100->pdata.in_mode); i++) {
2322 snd_soc_update_bits(codec, WM5100_IN1L_CONTROL,
2323 WM5100_IN1_MODE_MASK |
2324 WM5100_IN1_DMIC_SUP_MASK,
2325 (wm5100->pdata.in_mode[i] <<
2326 WM5100_IN1_MODE_SHIFT) |
2327 (wm5100->pdata.dmic_sup[i] <<
2328 WM5100_IN1_DMIC_SUP_SHIFT));
2329 }
2330
2331 for (i = 0; i < ARRAY_SIZE(wm5100->pdata.gpio_defaults); i++) {
2332 if (!wm5100->pdata.gpio_defaults[i])
2333 continue;
2334
2335 snd_soc_write(codec, WM5100_GPIO_CTRL_1 + i,
2336 wm5100->pdata.gpio_defaults[i]);
2337 }
2338
2339 /* Don't debounce interrupts to support use of SYSCLK only */
2340 snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_1, 0);
2341 snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_2, 0);
2342
2343 /* TODO: check if we're symmetric */
2344
2345 if (i2c->irq) {
2346 if (wm5100->pdata.irq_flags)
2347 irq_flags = wm5100->pdata.irq_flags;
2348 else
2349 irq_flags = IRQF_TRIGGER_LOW;
2350
2351 irq_flags |= IRQF_ONESHOT;
2352
2353 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2354 ret = request_threaded_irq(i2c->irq, NULL,
2355 wm5100_edge_irq,
2356 irq_flags, "wm5100", codec);
2357 else
2358 ret = request_threaded_irq(i2c->irq, NULL, wm5100_irq,
2359 irq_flags, "wm5100", codec);
2360
2361 if (ret != 0) {
2362 dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
2363 i2c->irq, ret);
2364 } else {
2365 /* Enable default interrupts */
2366 snd_soc_update_bits(codec,
2367 WM5100_INTERRUPT_STATUS_3_MASK,
2368 WM5100_IM_SPK_SHUTDOWN_WARN_EINT |
2369 WM5100_IM_SPK_SHUTDOWN_EINT |
2370 WM5100_IM_ASRC2_LOCK_EINT |
2371 WM5100_IM_ASRC1_LOCK_EINT |
2372 WM5100_IM_FLL2_LOCK_EINT |
2373 WM5100_IM_FLL1_LOCK_EINT |
2374 WM5100_CLKGEN_ERR_EINT |
2375 WM5100_CLKGEN_ERR_ASYNC_EINT, 0);
2376
2377 snd_soc_update_bits(codec,
2378 WM5100_INTERRUPT_STATUS_4_MASK,
2379 WM5100_AIF3_ERR_EINT |
2380 WM5100_AIF2_ERR_EINT |
2381 WM5100_AIF1_ERR_EINT |
2382 WM5100_CTRLIF_ERR_EINT |
2383 WM5100_ISRC2_UNDERCLOCKED_EINT |
2384 WM5100_ISRC1_UNDERCLOCKED_EINT |
2385 WM5100_FX_UNDERCLOCKED_EINT |
2386 WM5100_AIF3_UNDERCLOCKED_EINT |
2387 WM5100_AIF2_UNDERCLOCKED_EINT |
2388 WM5100_AIF1_UNDERCLOCKED_EINT |
2389 WM5100_ASRC_UNDERCLOCKED_EINT |
2390 WM5100_DAC_UNDERCLOCKED_EINT |
2391 WM5100_ADC_UNDERCLOCKED_EINT |
2392 WM5100_MIXER_UNDERCLOCKED_EINT, 0);
2393 }
2394 } else {
2395 snd_soc_dapm_new_controls(&codec->dapm,
2396 wm5100_dapm_widgets_noirq,
2397 ARRAY_SIZE(wm5100_dapm_widgets_noirq));
2398 }
2399
2400 if (wm5100->pdata.hp_pol) {
2401 ret = gpio_request_one(wm5100->pdata.hp_pol,
2402 GPIOF_OUT_INIT_HIGH, "WM5100 HP_POL");
2403 if (ret < 0) {
2404 dev_err(&i2c->dev, "Failed to request HP_POL %d: %d\n",
2405 wm5100->pdata.hp_pol, ret);
2406 goto err_gpio;
2407 }
2408 }
2409
2410 /* We'll get woken up again when the system has something useful
2411 * for us to do.
2412 */
2413 if (wm5100->pdata.ldo_ena)
2414 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2415 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2416 wm5100->core_supplies);
2417
2418 return 0;
2419
2420err_gpio:
2421 wm5100_free_gpio(codec);
2422err_reset:
2423 if (wm5100->pdata.reset) {
2424 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
2425 gpio_free(wm5100->pdata.reset);
2426 }
2427err_ldo:
2428 if (wm5100->pdata.ldo_ena) {
2429 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2430 gpio_free(wm5100->pdata.ldo_ena);
2431 }
2432err_enable:
2433 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2434 wm5100->core_supplies);
2435err_cpvdd:
2436 regulator_put(wm5100->cpvdd);
2437err_core:
2438 regulator_bulk_free(ARRAY_SIZE(wm5100->core_supplies),
2439 wm5100->core_supplies);
2440
2441 return ret;
2442}
2443
2444static int wm5100_remove(struct snd_soc_codec *codec)
2445{
2446 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2447
2448 wm5100_set_bias_level(codec, SND_SOC_BIAS_OFF);
2449 if (wm5100->pdata.hp_pol) {
2450 gpio_free(wm5100->pdata.hp_pol);
2451 }
2452 wm5100_free_gpio(codec);
2453 if (wm5100->pdata.reset) {
2454 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
2455 gpio_free(wm5100->pdata.reset);
2456 }
2457 if (wm5100->pdata.ldo_ena) {
2458 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2459 gpio_free(wm5100->pdata.ldo_ena);
2460 }
2461 regulator_put(wm5100->cpvdd);
2462 regulator_bulk_free(ARRAY_SIZE(wm5100->core_supplies),
2463 wm5100->core_supplies);
2464 return 0;
2465}
2466
2467static struct snd_soc_codec_driver soc_codec_dev_wm5100 = {
2468 .probe = wm5100_probe,
2469 .remove = wm5100_remove,
2470
2471 .set_sysclk = wm5100_set_sysclk,
2472 .set_pll = wm5100_set_fll,
2473 .set_bias_level = wm5100_set_bias_level,
2474 .idle_bias_off = 1,
2475
2476 .seq_notifier = wm5100_seq_notifier,
2477 .controls = wm5100_snd_controls,
2478 .num_controls = ARRAY_SIZE(wm5100_snd_controls),
2479 .dapm_widgets = wm5100_dapm_widgets,
2480 .num_dapm_widgets = ARRAY_SIZE(wm5100_dapm_widgets),
2481 .dapm_routes = wm5100_dapm_routes,
2482 .num_dapm_routes = ARRAY_SIZE(wm5100_dapm_routes),
2483
2484 .reg_cache_size = ARRAY_SIZE(wm5100_reg_defaults),
2485 .reg_word_size = sizeof(u16),
2486 .compress_type = SND_SOC_RBTREE_COMPRESSION,
2487 .reg_cache_default = wm5100_reg_defaults,
2488
2489 .volatile_register = wm5100_volatile_register,
2490 .readable_register = wm5100_readable_register,
2491};
2492
2493static __devinit int wm5100_i2c_probe(struct i2c_client *i2c,
2494 const struct i2c_device_id *id)
2495{
2496 struct wm5100_pdata *pdata = dev_get_platdata(&i2c->dev);
2497 struct wm5100_priv *wm5100;
2498 int ret, i;
2499
2500 wm5100 = kzalloc(sizeof(struct wm5100_priv), GFP_KERNEL);
2501 if (wm5100 == NULL)
2502 return -ENOMEM;
2503
2504 for (i = 0; i < ARRAY_SIZE(wm5100->fll); i++)
2505 init_completion(&wm5100->fll[i].lock);
2506
2507 if (pdata)
2508 wm5100->pdata = *pdata;
2509
2510 i2c_set_clientdata(i2c, wm5100);
2511
2512 ret = snd_soc_register_codec(&i2c->dev,
2513 &soc_codec_dev_wm5100, wm5100_dai,
2514 ARRAY_SIZE(wm5100_dai));
2515 if (ret < 0) {
2516 dev_err(&i2c->dev, "Failed to register WM5100: %d\n", ret);
2517 kfree(wm5100);
2518 }
2519
2520 return ret;
2521}
2522
2523static __devexit int wm5100_i2c_remove(struct i2c_client *client)
2524{
2525 snd_soc_unregister_codec(&client->dev);
2526 kfree(i2c_get_clientdata(client));
2527 return 0;
2528}
2529
2530static const struct i2c_device_id wm5100_i2c_id[] = {
2531 { "wm5100", 0 },
2532 { }
2533};
2534MODULE_DEVICE_TABLE(i2c, wm5100_i2c_id);
2535
2536static struct i2c_driver wm5100_i2c_driver = {
2537 .driver = {
2538 .name = "wm5100",
2539 .owner = THIS_MODULE,
2540 },
2541 .probe = wm5100_i2c_probe,
2542 .remove = __devexit_p(wm5100_i2c_remove),
2543 .id_table = wm5100_i2c_id,
2544};
2545
2546static int __init wm5100_modinit(void)
2547{
2548 return i2c_add_driver(&wm5100_i2c_driver);
2549}
2550module_init(wm5100_modinit);
2551
2552static void __exit wm5100_exit(void)
2553{
2554 i2c_del_driver(&wm5100_i2c_driver);
2555}
2556module_exit(wm5100_exit);
2557
2558MODULE_DESCRIPTION("ASoC WM5100 driver");
2559MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2560MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm5100.h b/sound/soc/codecs/wm5100.h
new file mode 100644
index 000000000000..345b3cffe6fa
--- /dev/null
+++ b/sound/soc/codecs/wm5100.h
@@ -0,0 +1,5146 @@
1/*
2 * wm5100.h -- WM5100 ALSA SoC Audio driver
3 *
4 * Copyright 2011 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef WM5100_ASOC_H
15#define WM5100_ASOC_H
16
17#include <sound/soc.h>
18
19#define WM5100_CLK_AIF1 1
20#define WM5100_CLK_AIF2 2
21#define WM5100_CLK_AIF3 3
22#define WM5100_CLK_SYSCLK 4
23#define WM5100_CLK_ASYNCCLK 5
24#define WM5100_CLK_32KHZ 6
25#define WM5100_CLK_OPCLK 7
26
27#define WM5100_CLKSRC_MCLK1 0
28#define WM5100_CLKSRC_MCLK2 1
29#define WM5100_CLKSRC_SYSCLK 2
30#define WM5100_CLKSRC_FLL1 4
31#define WM5100_CLKSRC_FLL2 5
32#define WM5100_CLKSRC_AIF1BCLK 8
33#define WM5100_CLKSRC_AIF2BCLK 9
34#define WM5100_CLKSRC_AIF3BCLK 10
35#define WM5100_CLKSRC_ASYNCCLK 0x100
36
37#define WM5100_FLL1 1
38#define WM5100_FLL2 2
39
40#define WM5100_FLL_SRC_MCLK1 0x0
41#define WM5100_FLL_SRC_MCLK2 0x1
42#define WM5100_FLL_SRC_FLL1 0x4
43#define WM5100_FLL_SRC_FLL2 0x5
44#define WM5100_FLL_SRC_AIF1BCLK 0x8
45#define WM5100_FLL_SRC_AIF2BCLK 0x9
46#define WM5100_FLL_SRC_AIF3BCLK 0xa
47
48/*
49 * Register values.
50 */
51#define WM5100_SOFTWARE_RESET 0x00
52#define WM5100_DEVICE_REVISION 0x01
53#define WM5100_CTRL_IF_1 0x10
54#define WM5100_TONE_GENERATOR_1 0x20
55#define WM5100_PWM_DRIVE_1 0x30
56#define WM5100_PWM_DRIVE_2 0x31
57#define WM5100_PWM_DRIVE_3 0x32
58#define WM5100_CLOCKING_1 0x100
59#define WM5100_CLOCKING_3 0x101
60#define WM5100_CLOCKING_4 0x102
61#define WM5100_CLOCKING_5 0x103
62#define WM5100_CLOCKING_6 0x104
63#define WM5100_CLOCKING_7 0x107
64#define WM5100_CLOCKING_8 0x108
65#define WM5100_ASRC_ENABLE 0x120
66#define WM5100_ASRC_STATUS 0x121
67#define WM5100_ASRC_RATE1 0x122
68#define WM5100_ISRC_1_CTRL_1 0x141
69#define WM5100_ISRC_1_CTRL_2 0x142
70#define WM5100_ISRC_2_CTRL1 0x143
71#define WM5100_ISRC_2_CTRL_2 0x144
72#define WM5100_FLL1_CONTROL_1 0x182
73#define WM5100_FLL1_CONTROL_2 0x183
74#define WM5100_FLL1_CONTROL_3 0x184
75#define WM5100_FLL1_CONTROL_5 0x186
76#define WM5100_FLL1_CONTROL_6 0x187
77#define WM5100_FLL1_EFS_1 0x188
78#define WM5100_FLL2_CONTROL_1 0x1A2
79#define WM5100_FLL2_CONTROL_2 0x1A3
80#define WM5100_FLL2_CONTROL_3 0x1A4
81#define WM5100_FLL2_CONTROL_5 0x1A6
82#define WM5100_FLL2_CONTROL_6 0x1A7
83#define WM5100_FLL2_EFS_1 0x1A8
84#define WM5100_MIC_CHARGE_PUMP_1 0x200
85#define WM5100_MIC_CHARGE_PUMP_2 0x201
86#define WM5100_HP_CHARGE_PUMP_1 0x202
87#define WM5100_LDO1_CONTROL 0x211
88#define WM5100_MIC_BIAS_CTRL_1 0x215
89#define WM5100_MIC_BIAS_CTRL_2 0x216
90#define WM5100_MIC_BIAS_CTRL_3 0x217
91#define WM5100_ACCESSORY_DETECT_MODE_1 0x280
92#define WM5100_HEADPHONE_DETECT_1 0x288
93#define WM5100_HEADPHONE_DETECT_2 0x289
94#define WM5100_MIC_DETECT_1 0x290
95#define WM5100_MIC_DETECT_2 0x291
96#define WM5100_MIC_DETECT_3 0x292
97#define WM5100_INPUT_ENABLES 0x301
98#define WM5100_INPUT_ENABLES_STATUS 0x302
99#define WM5100_IN1L_CONTROL 0x310
100#define WM5100_IN1R_CONTROL 0x311
101#define WM5100_IN2L_CONTROL 0x312
102#define WM5100_IN2R_CONTROL 0x313
103#define WM5100_IN3L_CONTROL 0x314
104#define WM5100_IN3R_CONTROL 0x315
105#define WM5100_IN4L_CONTROL 0x316
106#define WM5100_IN4R_CONTROL 0x317
107#define WM5100_RXANC_SRC 0x318
108#define WM5100_INPUT_VOLUME_RAMP 0x319
109#define WM5100_ADC_DIGITAL_VOLUME_1L 0x320
110#define WM5100_ADC_DIGITAL_VOLUME_1R 0x321
111#define WM5100_ADC_DIGITAL_VOLUME_2L 0x322
112#define WM5100_ADC_DIGITAL_VOLUME_2R 0x323
113#define WM5100_ADC_DIGITAL_VOLUME_3L 0x324
114#define WM5100_ADC_DIGITAL_VOLUME_3R 0x325
115#define WM5100_ADC_DIGITAL_VOLUME_4L 0x326
116#define WM5100_ADC_DIGITAL_VOLUME_4R 0x327
117#define WM5100_OUTPUT_ENABLES_2 0x401
118#define WM5100_OUTPUT_STATUS_1 0x402
119#define WM5100_OUTPUT_STATUS_2 0x403
120#define WM5100_CHANNEL_ENABLES_1 0x408
121#define WM5100_OUT_VOLUME_1L 0x410
122#define WM5100_OUT_VOLUME_1R 0x411
123#define WM5100_DAC_VOLUME_LIMIT_1L 0x412
124#define WM5100_DAC_VOLUME_LIMIT_1R 0x413
125#define WM5100_OUT_VOLUME_2L 0x414
126#define WM5100_OUT_VOLUME_2R 0x415
127#define WM5100_DAC_VOLUME_LIMIT_2L 0x416
128#define WM5100_DAC_VOLUME_LIMIT_2R 0x417
129#define WM5100_OUT_VOLUME_3L 0x418
130#define WM5100_OUT_VOLUME_3R 0x419
131#define WM5100_DAC_VOLUME_LIMIT_3L 0x41A
132#define WM5100_DAC_VOLUME_LIMIT_3R 0x41B
133#define WM5100_OUT_VOLUME_4L 0x41C
134#define WM5100_OUT_VOLUME_4R 0x41D
135#define WM5100_DAC_VOLUME_LIMIT_5L 0x41E
136#define WM5100_DAC_VOLUME_LIMIT_5R 0x41F
137#define WM5100_DAC_VOLUME_LIMIT_6L 0x420
138#define WM5100_DAC_VOLUME_LIMIT_6R 0x421
139#define WM5100_DAC_AEC_CONTROL_1 0x440
140#define WM5100_OUTPUT_VOLUME_RAMP 0x441
141#define WM5100_DAC_DIGITAL_VOLUME_1L 0x480
142#define WM5100_DAC_DIGITAL_VOLUME_1R 0x481
143#define WM5100_DAC_DIGITAL_VOLUME_2L 0x482
144#define WM5100_DAC_DIGITAL_VOLUME_2R 0x483
145#define WM5100_DAC_DIGITAL_VOLUME_3L 0x484
146#define WM5100_DAC_DIGITAL_VOLUME_3R 0x485
147#define WM5100_DAC_DIGITAL_VOLUME_4L 0x486
148#define WM5100_DAC_DIGITAL_VOLUME_4R 0x487
149#define WM5100_DAC_DIGITAL_VOLUME_5L 0x488
150#define WM5100_DAC_DIGITAL_VOLUME_5R 0x489
151#define WM5100_DAC_DIGITAL_VOLUME_6L 0x48A
152#define WM5100_DAC_DIGITAL_VOLUME_6R 0x48B
153#define WM5100_PDM_SPK1_CTRL_1 0x4C0
154#define WM5100_PDM_SPK1_CTRL_2 0x4C1
155#define WM5100_PDM_SPK2_CTRL_1 0x4C2
156#define WM5100_PDM_SPK2_CTRL_2 0x4C3
157#define WM5100_AUDIO_IF_1_1 0x500
158#define WM5100_AUDIO_IF_1_2 0x501
159#define WM5100_AUDIO_IF_1_3 0x502
160#define WM5100_AUDIO_IF_1_4 0x503
161#define WM5100_AUDIO_IF_1_5 0x504
162#define WM5100_AUDIO_IF_1_6 0x505
163#define WM5100_AUDIO_IF_1_7 0x506
164#define WM5100_AUDIO_IF_1_8 0x507
165#define WM5100_AUDIO_IF_1_9 0x508
166#define WM5100_AUDIO_IF_1_10 0x509
167#define WM5100_AUDIO_IF_1_11 0x50A
168#define WM5100_AUDIO_IF_1_12 0x50B
169#define WM5100_AUDIO_IF_1_13 0x50C
170#define WM5100_AUDIO_IF_1_14 0x50D
171#define WM5100_AUDIO_IF_1_15 0x50E
172#define WM5100_AUDIO_IF_1_16 0x50F
173#define WM5100_AUDIO_IF_1_17 0x510
174#define WM5100_AUDIO_IF_1_18 0x511
175#define WM5100_AUDIO_IF_1_19 0x512
176#define WM5100_AUDIO_IF_1_20 0x513
177#define WM5100_AUDIO_IF_1_21 0x514
178#define WM5100_AUDIO_IF_1_22 0x515
179#define WM5100_AUDIO_IF_1_23 0x516
180#define WM5100_AUDIO_IF_1_24 0x517
181#define WM5100_AUDIO_IF_1_25 0x518
182#define WM5100_AUDIO_IF_1_26 0x519
183#define WM5100_AUDIO_IF_1_27 0x51A
184#define WM5100_AUDIO_IF_2_1 0x540
185#define WM5100_AUDIO_IF_2_2 0x541
186#define WM5100_AUDIO_IF_2_3 0x542
187#define WM5100_AUDIO_IF_2_4 0x543
188#define WM5100_AUDIO_IF_2_5 0x544
189#define WM5100_AUDIO_IF_2_6 0x545
190#define WM5100_AUDIO_IF_2_7 0x546
191#define WM5100_AUDIO_IF_2_8 0x547
192#define WM5100_AUDIO_IF_2_9 0x548
193#define WM5100_AUDIO_IF_2_10 0x549
194#define WM5100_AUDIO_IF_2_11 0x54A
195#define WM5100_AUDIO_IF_2_18 0x551
196#define WM5100_AUDIO_IF_2_19 0x552
197#define WM5100_AUDIO_IF_2_26 0x559
198#define WM5100_AUDIO_IF_2_27 0x55A
199#define WM5100_AUDIO_IF_3_1 0x580
200#define WM5100_AUDIO_IF_3_2 0x581
201#define WM5100_AUDIO_IF_3_3 0x582
202#define WM5100_AUDIO_IF_3_4 0x583
203#define WM5100_AUDIO_IF_3_5 0x584
204#define WM5100_AUDIO_IF_3_6 0x585
205#define WM5100_AUDIO_IF_3_7 0x586
206#define WM5100_AUDIO_IF_3_8 0x587
207#define WM5100_AUDIO_IF_3_9 0x588
208#define WM5100_AUDIO_IF_3_10 0x589
209#define WM5100_AUDIO_IF_3_11 0x58A
210#define WM5100_AUDIO_IF_3_18 0x591
211#define WM5100_AUDIO_IF_3_19 0x592
212#define WM5100_AUDIO_IF_3_26 0x599
213#define WM5100_AUDIO_IF_3_27 0x59A
214#define WM5100_PWM1MIX_INPUT_1_SOURCE 0x640
215#define WM5100_PWM1MIX_INPUT_1_VOLUME 0x641
216#define WM5100_PWM1MIX_INPUT_2_SOURCE 0x642
217#define WM5100_PWM1MIX_INPUT_2_VOLUME 0x643
218#define WM5100_PWM1MIX_INPUT_3_SOURCE 0x644
219#define WM5100_PWM1MIX_INPUT_3_VOLUME 0x645
220#define WM5100_PWM1MIX_INPUT_4_SOURCE 0x646
221#define WM5100_PWM1MIX_INPUT_4_VOLUME 0x647
222#define WM5100_PWM2MIX_INPUT_1_SOURCE 0x648
223#define WM5100_PWM2MIX_INPUT_1_VOLUME 0x649
224#define WM5100_PWM2MIX_INPUT_2_SOURCE 0x64A
225#define WM5100_PWM2MIX_INPUT_2_VOLUME 0x64B
226#define WM5100_PWM2MIX_INPUT_3_SOURCE 0x64C
227#define WM5100_PWM2MIX_INPUT_3_VOLUME 0x64D
228#define WM5100_PWM2MIX_INPUT_4_SOURCE 0x64E
229#define WM5100_PWM2MIX_INPUT_4_VOLUME 0x64F
230#define WM5100_OUT1LMIX_INPUT_1_SOURCE 0x680
231#define WM5100_OUT1LMIX_INPUT_1_VOLUME 0x681
232#define WM5100_OUT1LMIX_INPUT_2_SOURCE 0x682
233#define WM5100_OUT1LMIX_INPUT_2_VOLUME 0x683
234#define WM5100_OUT1LMIX_INPUT_3_SOURCE 0x684
235#define WM5100_OUT1LMIX_INPUT_3_VOLUME 0x685
236#define WM5100_OUT1LMIX_INPUT_4_SOURCE 0x686
237#define WM5100_OUT1LMIX_INPUT_4_VOLUME 0x687
238#define WM5100_OUT1RMIX_INPUT_1_SOURCE 0x688
239#define WM5100_OUT1RMIX_INPUT_1_VOLUME 0x689
240#define WM5100_OUT1RMIX_INPUT_2_SOURCE 0x68A
241#define WM5100_OUT1RMIX_INPUT_2_VOLUME 0x68B
242#define WM5100_OUT1RMIX_INPUT_3_SOURCE 0x68C
243#define WM5100_OUT1RMIX_INPUT_3_VOLUME 0x68D
244#define WM5100_OUT1RMIX_INPUT_4_SOURCE 0x68E
245#define WM5100_OUT1RMIX_INPUT_4_VOLUME 0x68F
246#define WM5100_OUT2LMIX_INPUT_1_SOURCE 0x690
247#define WM5100_OUT2LMIX_INPUT_1_VOLUME 0x691
248#define WM5100_OUT2LMIX_INPUT_2_SOURCE 0x692
249#define WM5100_OUT2LMIX_INPUT_2_VOLUME 0x693
250#define WM5100_OUT2LMIX_INPUT_3_SOURCE 0x694
251#define WM5100_OUT2LMIX_INPUT_3_VOLUME 0x695
252#define WM5100_OUT2LMIX_INPUT_4_SOURCE 0x696
253#define WM5100_OUT2LMIX_INPUT_4_VOLUME 0x697
254#define WM5100_OUT2RMIX_INPUT_1_SOURCE 0x698
255#define WM5100_OUT2RMIX_INPUT_1_VOLUME 0x699
256#define WM5100_OUT2RMIX_INPUT_2_SOURCE 0x69A
257#define WM5100_OUT2RMIX_INPUT_2_VOLUME 0x69B
258#define WM5100_OUT2RMIX_INPUT_3_SOURCE 0x69C
259#define WM5100_OUT2RMIX_INPUT_3_VOLUME 0x69D
260#define WM5100_OUT2RMIX_INPUT_4_SOURCE 0x69E
261#define WM5100_OUT2RMIX_INPUT_4_VOLUME 0x69F
262#define WM5100_OUT3LMIX_INPUT_1_SOURCE 0x6A0
263#define WM5100_OUT3LMIX_INPUT_1_VOLUME 0x6A1
264#define WM5100_OUT3LMIX_INPUT_2_SOURCE 0x6A2
265#define WM5100_OUT3LMIX_INPUT_2_VOLUME 0x6A3
266#define WM5100_OUT3LMIX_INPUT_3_SOURCE 0x6A4
267#define WM5100_OUT3LMIX_INPUT_3_VOLUME 0x6A5
268#define WM5100_OUT3LMIX_INPUT_4_SOURCE 0x6A6
269#define WM5100_OUT3LMIX_INPUT_4_VOLUME 0x6A7
270#define WM5100_OUT3RMIX_INPUT_1_SOURCE 0x6A8
271#define WM5100_OUT3RMIX_INPUT_1_VOLUME 0x6A9
272#define WM5100_OUT3RMIX_INPUT_2_SOURCE 0x6AA
273#define WM5100_OUT3RMIX_INPUT_2_VOLUME 0x6AB
274#define WM5100_OUT3RMIX_INPUT_3_SOURCE 0x6AC
275#define WM5100_OUT3RMIX_INPUT_3_VOLUME 0x6AD
276#define WM5100_OUT3RMIX_INPUT_4_SOURCE 0x6AE
277#define WM5100_OUT3RMIX_INPUT_4_VOLUME 0x6AF
278#define WM5100_OUT4LMIX_INPUT_1_SOURCE 0x6B0
279#define WM5100_OUT4LMIX_INPUT_1_VOLUME 0x6B1
280#define WM5100_OUT4LMIX_INPUT_2_SOURCE 0x6B2
281#define WM5100_OUT4LMIX_INPUT_2_VOLUME 0x6B3
282#define WM5100_OUT4LMIX_INPUT_3_SOURCE 0x6B4
283#define WM5100_OUT4LMIX_INPUT_3_VOLUME 0x6B5
284#define WM5100_OUT4LMIX_INPUT_4_SOURCE 0x6B6
285#define WM5100_OUT4LMIX_INPUT_4_VOLUME 0x6B7
286#define WM5100_OUT4RMIX_INPUT_1_SOURCE 0x6B8
287#define WM5100_OUT4RMIX_INPUT_1_VOLUME 0x6B9
288#define WM5100_OUT4RMIX_INPUT_2_SOURCE 0x6BA
289#define WM5100_OUT4RMIX_INPUT_2_VOLUME 0x6BB
290#define WM5100_OUT4RMIX_INPUT_3_SOURCE 0x6BC
291#define WM5100_OUT4RMIX_INPUT_3_VOLUME 0x6BD
292#define WM5100_OUT4RMIX_INPUT_4_SOURCE 0x6BE
293#define WM5100_OUT4RMIX_INPUT_4_VOLUME 0x6BF
294#define WM5100_OUT5LMIX_INPUT_1_SOURCE 0x6C0
295#define WM5100_OUT5LMIX_INPUT_1_VOLUME 0x6C1
296#define WM5100_OUT5LMIX_INPUT_2_SOURCE 0x6C2
297#define WM5100_OUT5LMIX_INPUT_2_VOLUME 0x6C3
298#define WM5100_OUT5LMIX_INPUT_3_SOURCE 0x6C4
299#define WM5100_OUT5LMIX_INPUT_3_VOLUME 0x6C5
300#define WM5100_OUT5LMIX_INPUT_4_SOURCE 0x6C6
301#define WM5100_OUT5LMIX_INPUT_4_VOLUME 0x6C7
302#define WM5100_OUT5RMIX_INPUT_1_SOURCE 0x6C8
303#define WM5100_OUT5RMIX_INPUT_1_VOLUME 0x6C9
304#define WM5100_OUT5RMIX_INPUT_2_SOURCE 0x6CA
305#define WM5100_OUT5RMIX_INPUT_2_VOLUME 0x6CB
306#define WM5100_OUT5RMIX_INPUT_3_SOURCE 0x6CC
307#define WM5100_OUT5RMIX_INPUT_3_VOLUME 0x6CD
308#define WM5100_OUT5RMIX_INPUT_4_SOURCE 0x6CE
309#define WM5100_OUT5RMIX_INPUT_4_VOLUME 0x6CF
310#define WM5100_OUT6LMIX_INPUT_1_SOURCE 0x6D0
311#define WM5100_OUT6LMIX_INPUT_1_VOLUME 0x6D1
312#define WM5100_OUT6LMIX_INPUT_2_SOURCE 0x6D2
313#define WM5100_OUT6LMIX_INPUT_2_VOLUME 0x6D3
314#define WM5100_OUT6LMIX_INPUT_3_SOURCE 0x6D4
315#define WM5100_OUT6LMIX_INPUT_3_VOLUME 0x6D5
316#define WM5100_OUT6LMIX_INPUT_4_SOURCE 0x6D6
317#define WM5100_OUT6LMIX_INPUT_4_VOLUME 0x6D7
318#define WM5100_OUT6RMIX_INPUT_1_SOURCE 0x6D8
319#define WM5100_OUT6RMIX_INPUT_1_VOLUME 0x6D9
320#define WM5100_OUT6RMIX_INPUT_2_SOURCE 0x6DA
321#define WM5100_OUT6RMIX_INPUT_2_VOLUME 0x6DB
322#define WM5100_OUT6RMIX_INPUT_3_SOURCE 0x6DC
323#define WM5100_OUT6RMIX_INPUT_3_VOLUME 0x6DD
324#define WM5100_OUT6RMIX_INPUT_4_SOURCE 0x6DE
325#define WM5100_OUT6RMIX_INPUT_4_VOLUME 0x6DF
326#define WM5100_AIF1TX1MIX_INPUT_1_SOURCE 0x700
327#define WM5100_AIF1TX1MIX_INPUT_1_VOLUME 0x701
328#define WM5100_AIF1TX1MIX_INPUT_2_SOURCE 0x702
329#define WM5100_AIF1TX1MIX_INPUT_2_VOLUME 0x703
330#define WM5100_AIF1TX1MIX_INPUT_3_SOURCE 0x704
331#define WM5100_AIF1TX1MIX_INPUT_3_VOLUME 0x705
332#define WM5100_AIF1TX1MIX_INPUT_4_SOURCE 0x706
333#define WM5100_AIF1TX1MIX_INPUT_4_VOLUME 0x707
334#define WM5100_AIF1TX2MIX_INPUT_1_SOURCE 0x708
335#define WM5100_AIF1TX2MIX_INPUT_1_VOLUME 0x709
336#define WM5100_AIF1TX2MIX_INPUT_2_SOURCE 0x70A
337#define WM5100_AIF1TX2MIX_INPUT_2_VOLUME 0x70B
338#define WM5100_AIF1TX2MIX_INPUT_3_SOURCE 0x70C
339#define WM5100_AIF1TX2MIX_INPUT_3_VOLUME 0x70D
340#define WM5100_AIF1TX2MIX_INPUT_4_SOURCE 0x70E
341#define WM5100_AIF1TX2MIX_INPUT_4_VOLUME 0x70F
342#define WM5100_AIF1TX3MIX_INPUT_1_SOURCE 0x710
343#define WM5100_AIF1TX3MIX_INPUT_1_VOLUME 0x711
344#define WM5100_AIF1TX3MIX_INPUT_2_SOURCE 0x712
345#define WM5100_AIF1TX3MIX_INPUT_2_VOLUME 0x713
346#define WM5100_AIF1TX3MIX_INPUT_3_SOURCE 0x714
347#define WM5100_AIF1TX3MIX_INPUT_3_VOLUME 0x715
348#define WM5100_AIF1TX3MIX_INPUT_4_SOURCE 0x716
349#define WM5100_AIF1TX3MIX_INPUT_4_VOLUME 0x717
350#define WM5100_AIF1TX4MIX_INPUT_1_SOURCE 0x718
351#define WM5100_AIF1TX4MIX_INPUT_1_VOLUME 0x719
352#define WM5100_AIF1TX4MIX_INPUT_2_SOURCE 0x71A
353#define WM5100_AIF1TX4MIX_INPUT_2_VOLUME 0x71B
354#define WM5100_AIF1TX4MIX_INPUT_3_SOURCE 0x71C
355#define WM5100_AIF1TX4MIX_INPUT_3_VOLUME 0x71D
356#define WM5100_AIF1TX4MIX_INPUT_4_SOURCE 0x71E
357#define WM5100_AIF1TX4MIX_INPUT_4_VOLUME 0x71F
358#define WM5100_AIF1TX5MIX_INPUT_1_SOURCE 0x720
359#define WM5100_AIF1TX5MIX_INPUT_1_VOLUME 0x721
360#define WM5100_AIF1TX5MIX_INPUT_2_SOURCE 0x722
361#define WM5100_AIF1TX5MIX_INPUT_2_VOLUME 0x723
362#define WM5100_AIF1TX5MIX_INPUT_3_SOURCE 0x724
363#define WM5100_AIF1TX5MIX_INPUT_3_VOLUME 0x725
364#define WM5100_AIF1TX5MIX_INPUT_4_SOURCE 0x726
365#define WM5100_AIF1TX5MIX_INPUT_4_VOLUME 0x727
366#define WM5100_AIF1TX6MIX_INPUT_1_SOURCE 0x728
367#define WM5100_AIF1TX6MIX_INPUT_1_VOLUME 0x729
368#define WM5100_AIF1TX6MIX_INPUT_2_SOURCE 0x72A
369#define WM5100_AIF1TX6MIX_INPUT_2_VOLUME 0x72B
370#define WM5100_AIF1TX6MIX_INPUT_3_SOURCE 0x72C
371#define WM5100_AIF1TX6MIX_INPUT_3_VOLUME 0x72D
372#define WM5100_AIF1TX6MIX_INPUT_4_SOURCE 0x72E
373#define WM5100_AIF1TX6MIX_INPUT_4_VOLUME 0x72F
374#define WM5100_AIF1TX7MIX_INPUT_1_SOURCE 0x730
375#define WM5100_AIF1TX7MIX_INPUT_1_VOLUME 0x731
376#define WM5100_AIF1TX7MIX_INPUT_2_SOURCE 0x732
377#define WM5100_AIF1TX7MIX_INPUT_2_VOLUME 0x733
378#define WM5100_AIF1TX7MIX_INPUT_3_SOURCE 0x734
379#define WM5100_AIF1TX7MIX_INPUT_3_VOLUME 0x735
380#define WM5100_AIF1TX7MIX_INPUT_4_SOURCE 0x736
381#define WM5100_AIF1TX7MIX_INPUT_4_VOLUME 0x737
382#define WM5100_AIF1TX8MIX_INPUT_1_SOURCE 0x738
383#define WM5100_AIF1TX8MIX_INPUT_1_VOLUME 0x739
384#define WM5100_AIF1TX8MIX_INPUT_2_SOURCE 0x73A
385#define WM5100_AIF1TX8MIX_INPUT_2_VOLUME 0x73B
386#define WM5100_AIF1TX8MIX_INPUT_3_SOURCE 0x73C
387#define WM5100_AIF1TX8MIX_INPUT_3_VOLUME 0x73D
388#define WM5100_AIF1TX8MIX_INPUT_4_SOURCE 0x73E
389#define WM5100_AIF1TX8MIX_INPUT_4_VOLUME 0x73F
390#define WM5100_AIF2TX1MIX_INPUT_1_SOURCE 0x740
391#define WM5100_AIF2TX1MIX_INPUT_1_VOLUME 0x741
392#define WM5100_AIF2TX1MIX_INPUT_2_SOURCE 0x742
393#define WM5100_AIF2TX1MIX_INPUT_2_VOLUME 0x743
394#define WM5100_AIF2TX1MIX_INPUT_3_SOURCE 0x744
395#define WM5100_AIF2TX1MIX_INPUT_3_VOLUME 0x745
396#define WM5100_AIF2TX1MIX_INPUT_4_SOURCE 0x746
397#define WM5100_AIF2TX1MIX_INPUT_4_VOLUME 0x747
398#define WM5100_AIF2TX2MIX_INPUT_1_SOURCE 0x748
399#define WM5100_AIF2TX2MIX_INPUT_1_VOLUME 0x749
400#define WM5100_AIF2TX2MIX_INPUT_2_SOURCE 0x74A
401#define WM5100_AIF2TX2MIX_INPUT_2_VOLUME 0x74B
402#define WM5100_AIF2TX2MIX_INPUT_3_SOURCE 0x74C
403#define WM5100_AIF2TX2MIX_INPUT_3_VOLUME 0x74D
404#define WM5100_AIF2TX2MIX_INPUT_4_SOURCE 0x74E
405#define WM5100_AIF2TX2MIX_INPUT_4_VOLUME 0x74F
406#define WM5100_AIF3TX1MIX_INPUT_1_SOURCE 0x780
407#define WM5100_AIF3TX1MIX_INPUT_1_VOLUME 0x781
408#define WM5100_AIF3TX1MIX_INPUT_2_SOURCE 0x782
409#define WM5100_AIF3TX1MIX_INPUT_2_VOLUME 0x783
410#define WM5100_AIF3TX1MIX_INPUT_3_SOURCE 0x784
411#define WM5100_AIF3TX1MIX_INPUT_3_VOLUME 0x785
412#define WM5100_AIF3TX1MIX_INPUT_4_SOURCE 0x786
413#define WM5100_AIF3TX1MIX_INPUT_4_VOLUME 0x787
414#define WM5100_AIF3TX2MIX_INPUT_1_SOURCE 0x788
415#define WM5100_AIF3TX2MIX_INPUT_1_VOLUME 0x789
416#define WM5100_AIF3TX2MIX_INPUT_2_SOURCE 0x78A
417#define WM5100_AIF3TX2MIX_INPUT_2_VOLUME 0x78B
418#define WM5100_AIF3TX2MIX_INPUT_3_SOURCE 0x78C
419#define WM5100_AIF3TX2MIX_INPUT_3_VOLUME 0x78D
420#define WM5100_AIF3TX2MIX_INPUT_4_SOURCE 0x78E
421#define WM5100_AIF3TX2MIX_INPUT_4_VOLUME 0x78F
422#define WM5100_EQ1MIX_INPUT_1_SOURCE 0x880
423#define WM5100_EQ1MIX_INPUT_1_VOLUME 0x881
424#define WM5100_EQ1MIX_INPUT_2_SOURCE 0x882
425#define WM5100_EQ1MIX_INPUT_2_VOLUME 0x883
426#define WM5100_EQ1MIX_INPUT_3_SOURCE 0x884
427#define WM5100_EQ1MIX_INPUT_3_VOLUME 0x885
428#define WM5100_EQ1MIX_INPUT_4_SOURCE 0x886
429#define WM5100_EQ1MIX_INPUT_4_VOLUME 0x887
430#define WM5100_EQ2MIX_INPUT_1_SOURCE 0x888
431#define WM5100_EQ2MIX_INPUT_1_VOLUME 0x889
432#define WM5100_EQ2MIX_INPUT_2_SOURCE 0x88A
433#define WM5100_EQ2MIX_INPUT_2_VOLUME 0x88B
434#define WM5100_EQ2MIX_INPUT_3_SOURCE 0x88C
435#define WM5100_EQ2MIX_INPUT_3_VOLUME 0x88D
436#define WM5100_EQ2MIX_INPUT_4_SOURCE 0x88E
437#define WM5100_EQ2MIX_INPUT_4_VOLUME 0x88F
438#define WM5100_EQ3MIX_INPUT_1_SOURCE 0x890
439#define WM5100_EQ3MIX_INPUT_1_VOLUME 0x891
440#define WM5100_EQ3MIX_INPUT_2_SOURCE 0x892
441#define WM5100_EQ3MIX_INPUT_2_VOLUME 0x893
442#define WM5100_EQ3MIX_INPUT_3_SOURCE 0x894
443#define WM5100_EQ3MIX_INPUT_3_VOLUME 0x895
444#define WM5100_EQ3MIX_INPUT_4_SOURCE 0x896
445#define WM5100_EQ3MIX_INPUT_4_VOLUME 0x897
446#define WM5100_EQ4MIX_INPUT_1_SOURCE 0x898
447#define WM5100_EQ4MIX_INPUT_1_VOLUME 0x899
448#define WM5100_EQ4MIX_INPUT_2_SOURCE 0x89A
449#define WM5100_EQ4MIX_INPUT_2_VOLUME 0x89B
450#define WM5100_EQ4MIX_INPUT_3_SOURCE 0x89C
451#define WM5100_EQ4MIX_INPUT_3_VOLUME 0x89D
452#define WM5100_EQ4MIX_INPUT_4_SOURCE 0x89E
453#define WM5100_EQ4MIX_INPUT_4_VOLUME 0x89F
454#define WM5100_DRC1LMIX_INPUT_1_SOURCE 0x8C0
455#define WM5100_DRC1LMIX_INPUT_1_VOLUME 0x8C1
456#define WM5100_DRC1LMIX_INPUT_2_SOURCE 0x8C2
457#define WM5100_DRC1LMIX_INPUT_2_VOLUME 0x8C3
458#define WM5100_DRC1LMIX_INPUT_3_SOURCE 0x8C4
459#define WM5100_DRC1LMIX_INPUT_3_VOLUME 0x8C5
460#define WM5100_DRC1LMIX_INPUT_4_SOURCE 0x8C6
461#define WM5100_DRC1LMIX_INPUT_4_VOLUME 0x8C7
462#define WM5100_DRC1RMIX_INPUT_1_SOURCE 0x8C8
463#define WM5100_DRC1RMIX_INPUT_1_VOLUME 0x8C9
464#define WM5100_DRC1RMIX_INPUT_2_SOURCE 0x8CA
465#define WM5100_DRC1RMIX_INPUT_2_VOLUME 0x8CB
466#define WM5100_DRC1RMIX_INPUT_3_SOURCE 0x8CC
467#define WM5100_DRC1RMIX_INPUT_3_VOLUME 0x8CD
468#define WM5100_DRC1RMIX_INPUT_4_SOURCE 0x8CE
469#define WM5100_DRC1RMIX_INPUT_4_VOLUME 0x8CF
470#define WM5100_HPLP1MIX_INPUT_1_SOURCE 0x900
471#define WM5100_HPLP1MIX_INPUT_1_VOLUME 0x901
472#define WM5100_HPLP1MIX_INPUT_2_SOURCE 0x902
473#define WM5100_HPLP1MIX_INPUT_2_VOLUME 0x903
474#define WM5100_HPLP1MIX_INPUT_3_SOURCE 0x904
475#define WM5100_HPLP1MIX_INPUT_3_VOLUME 0x905
476#define WM5100_HPLP1MIX_INPUT_4_SOURCE 0x906
477#define WM5100_HPLP1MIX_INPUT_4_VOLUME 0x907
478#define WM5100_HPLP2MIX_INPUT_1_SOURCE 0x908
479#define WM5100_HPLP2MIX_INPUT_1_VOLUME 0x909
480#define WM5100_HPLP2MIX_INPUT_2_SOURCE 0x90A
481#define WM5100_HPLP2MIX_INPUT_2_VOLUME 0x90B
482#define WM5100_HPLP2MIX_INPUT_3_SOURCE 0x90C
483#define WM5100_HPLP2MIX_INPUT_3_VOLUME 0x90D
484#define WM5100_HPLP2MIX_INPUT_4_SOURCE 0x90E
485#define WM5100_HPLP2MIX_INPUT_4_VOLUME 0x90F
486#define WM5100_HPLP3MIX_INPUT_1_SOURCE 0x910
487#define WM5100_HPLP3MIX_INPUT_1_VOLUME 0x911
488#define WM5100_HPLP3MIX_INPUT_2_SOURCE 0x912
489#define WM5100_HPLP3MIX_INPUT_2_VOLUME 0x913
490#define WM5100_HPLP3MIX_INPUT_3_SOURCE 0x914
491#define WM5100_HPLP3MIX_INPUT_3_VOLUME 0x915
492#define WM5100_HPLP3MIX_INPUT_4_SOURCE 0x916
493#define WM5100_HPLP3MIX_INPUT_4_VOLUME 0x917
494#define WM5100_HPLP4MIX_INPUT_1_SOURCE 0x918
495#define WM5100_HPLP4MIX_INPUT_1_VOLUME 0x919
496#define WM5100_HPLP4MIX_INPUT_2_SOURCE 0x91A
497#define WM5100_HPLP4MIX_INPUT_2_VOLUME 0x91B
498#define WM5100_HPLP4MIX_INPUT_3_SOURCE 0x91C
499#define WM5100_HPLP4MIX_INPUT_3_VOLUME 0x91D
500#define WM5100_HPLP4MIX_INPUT_4_SOURCE 0x91E
501#define WM5100_HPLP4MIX_INPUT_4_VOLUME 0x91F
502#define WM5100_DSP1LMIX_INPUT_1_SOURCE 0x940
503#define WM5100_DSP1LMIX_INPUT_1_VOLUME 0x941
504#define WM5100_DSP1LMIX_INPUT_2_SOURCE 0x942
505#define WM5100_DSP1LMIX_INPUT_2_VOLUME 0x943
506#define WM5100_DSP1LMIX_INPUT_3_SOURCE 0x944
507#define WM5100_DSP1LMIX_INPUT_3_VOLUME 0x945
508#define WM5100_DSP1LMIX_INPUT_4_SOURCE 0x946
509#define WM5100_DSP1LMIX_INPUT_4_VOLUME 0x947
510#define WM5100_DSP1RMIX_INPUT_1_SOURCE 0x948
511#define WM5100_DSP1RMIX_INPUT_1_VOLUME 0x949
512#define WM5100_DSP1RMIX_INPUT_2_SOURCE 0x94A
513#define WM5100_DSP1RMIX_INPUT_2_VOLUME 0x94B
514#define WM5100_DSP1RMIX_INPUT_3_SOURCE 0x94C
515#define WM5100_DSP1RMIX_INPUT_3_VOLUME 0x94D
516#define WM5100_DSP1RMIX_INPUT_4_SOURCE 0x94E
517#define WM5100_DSP1RMIX_INPUT_4_VOLUME 0x94F
518#define WM5100_DSP1AUX1MIX_INPUT_1_SOURCE 0x950
519#define WM5100_DSP1AUX2MIX_INPUT_1_SOURCE 0x958
520#define WM5100_DSP1AUX3MIX_INPUT_1_SOURCE 0x960
521#define WM5100_DSP1AUX4MIX_INPUT_1_SOURCE 0x968
522#define WM5100_DSP1AUX5MIX_INPUT_1_SOURCE 0x970
523#define WM5100_DSP1AUX6MIX_INPUT_1_SOURCE 0x978
524#define WM5100_DSP2LMIX_INPUT_1_SOURCE 0x980
525#define WM5100_DSP2LMIX_INPUT_1_VOLUME 0x981
526#define WM5100_DSP2LMIX_INPUT_2_SOURCE 0x982
527#define WM5100_DSP2LMIX_INPUT_2_VOLUME 0x983
528#define WM5100_DSP2LMIX_INPUT_3_SOURCE 0x984
529#define WM5100_DSP2LMIX_INPUT_3_VOLUME 0x985
530#define WM5100_DSP2LMIX_INPUT_4_SOURCE 0x986
531#define WM5100_DSP2LMIX_INPUT_4_VOLUME 0x987
532#define WM5100_DSP2RMIX_INPUT_1_SOURCE 0x988
533#define WM5100_DSP2RMIX_INPUT_1_VOLUME 0x989
534#define WM5100_DSP2RMIX_INPUT_2_SOURCE 0x98A
535#define WM5100_DSP2RMIX_INPUT_2_VOLUME 0x98B
536#define WM5100_DSP2RMIX_INPUT_3_SOURCE 0x98C
537#define WM5100_DSP2RMIX_INPUT_3_VOLUME 0x98D
538#define WM5100_DSP2RMIX_INPUT_4_SOURCE 0x98E
539#define WM5100_DSP2RMIX_INPUT_4_VOLUME 0x98F
540#define WM5100_DSP2AUX1MIX_INPUT_1_SOURCE 0x990
541#define WM5100_DSP2AUX2MIX_INPUT_1_SOURCE 0x998
542#define WM5100_DSP2AUX3MIX_INPUT_1_SOURCE 0x9A0
543#define WM5100_DSP2AUX4MIX_INPUT_1_SOURCE 0x9A8
544#define WM5100_DSP2AUX5MIX_INPUT_1_SOURCE 0x9B0
545#define WM5100_DSP2AUX6MIX_INPUT_1_SOURCE 0x9B8
546#define WM5100_DSP3LMIX_INPUT_1_SOURCE 0x9C0
547#define WM5100_DSP3LMIX_INPUT_1_VOLUME 0x9C1
548#define WM5100_DSP3LMIX_INPUT_2_SOURCE 0x9C2
549#define WM5100_DSP3LMIX_INPUT_2_VOLUME 0x9C3
550#define WM5100_DSP3LMIX_INPUT_3_SOURCE 0x9C4
551#define WM5100_DSP3LMIX_INPUT_3_VOLUME 0x9C5
552#define WM5100_DSP3LMIX_INPUT_4_SOURCE 0x9C6
553#define WM5100_DSP3LMIX_INPUT_4_VOLUME 0x9C7
554#define WM5100_DSP3RMIX_INPUT_1_SOURCE 0x9C8
555#define WM5100_DSP3RMIX_INPUT_1_VOLUME 0x9C9
556#define WM5100_DSP3RMIX_INPUT_2_SOURCE 0x9CA
557#define WM5100_DSP3RMIX_INPUT_2_VOLUME 0x9CB
558#define WM5100_DSP3RMIX_INPUT_3_SOURCE 0x9CC
559#define WM5100_DSP3RMIX_INPUT_3_VOLUME 0x9CD
560#define WM5100_DSP3RMIX_INPUT_4_SOURCE 0x9CE
561#define WM5100_DSP3RMIX_INPUT_4_VOLUME 0x9CF
562#define WM5100_DSP3AUX1MIX_INPUT_1_SOURCE 0x9D0
563#define WM5100_DSP3AUX2MIX_INPUT_1_SOURCE 0x9D8
564#define WM5100_DSP3AUX3MIX_INPUT_1_SOURCE 0x9E0
565#define WM5100_DSP3AUX4MIX_INPUT_1_SOURCE 0x9E8
566#define WM5100_DSP3AUX5MIX_INPUT_1_SOURCE 0x9F0
567#define WM5100_DSP3AUX6MIX_INPUT_1_SOURCE 0x9F8
568#define WM5100_ASRC1LMIX_INPUT_1_SOURCE 0xA80
569#define WM5100_ASRC1RMIX_INPUT_1_SOURCE 0xA88
570#define WM5100_ASRC2LMIX_INPUT_1_SOURCE 0xA90
571#define WM5100_ASRC2RMIX_INPUT_1_SOURCE 0xA98
572#define WM5100_ISRC1DEC1MIX_INPUT_1_SOURCE 0xB00
573#define WM5100_ISRC1DEC2MIX_INPUT_1_SOURCE 0xB08
574#define WM5100_ISRC1DEC3MIX_INPUT_1_SOURCE 0xB10
575#define WM5100_ISRC1DEC4MIX_INPUT_1_SOURCE 0xB18
576#define WM5100_ISRC1INT1MIX_INPUT_1_SOURCE 0xB20
577#define WM5100_ISRC1INT2MIX_INPUT_1_SOURCE 0xB28
578#define WM5100_ISRC1INT3MIX_INPUT_1_SOURCE 0xB30
579#define WM5100_ISRC1INT4MIX_INPUT_1_SOURCE 0xB38
580#define WM5100_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40
581#define WM5100_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48
582#define WM5100_ISRC2DEC3MIX_INPUT_1_SOURCE 0xB50
583#define WM5100_ISRC2DEC4MIX_INPUT_1_SOURCE 0xB58
584#define WM5100_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60
585#define WM5100_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68
586#define WM5100_ISRC2INT3MIX_INPUT_1_SOURCE 0xB70
587#define WM5100_ISRC2INT4MIX_INPUT_1_SOURCE 0xB78
588#define WM5100_GPIO_CTRL_1 0xC00
589#define WM5100_GPIO_CTRL_2 0xC01
590#define WM5100_GPIO_CTRL_3 0xC02
591#define WM5100_GPIO_CTRL_4 0xC03
592#define WM5100_GPIO_CTRL_5 0xC04
593#define WM5100_GPIO_CTRL_6 0xC05
594#define WM5100_MISC_PAD_CTRL_1 0xC23
595#define WM5100_MISC_PAD_CTRL_2 0xC24
596#define WM5100_MISC_PAD_CTRL_3 0xC25
597#define WM5100_MISC_PAD_CTRL_4 0xC26
598#define WM5100_MISC_PAD_CTRL_5 0xC27
599#define WM5100_MISC_GPIO_1 0xC28
600#define WM5100_INTERRUPT_STATUS_1 0xD00
601#define WM5100_INTERRUPT_STATUS_2 0xD01
602#define WM5100_INTERRUPT_STATUS_3 0xD02
603#define WM5100_INTERRUPT_STATUS_4 0xD03
604#define WM5100_INTERRUPT_RAW_STATUS_2 0xD04
605#define WM5100_INTERRUPT_RAW_STATUS_3 0xD05
606#define WM5100_INTERRUPT_RAW_STATUS_4 0xD06
607#define WM5100_INTERRUPT_STATUS_1_MASK 0xD07
608#define WM5100_INTERRUPT_STATUS_2_MASK 0xD08
609#define WM5100_INTERRUPT_STATUS_3_MASK 0xD09
610#define WM5100_INTERRUPT_STATUS_4_MASK 0xD0A
611#define WM5100_INTERRUPT_CONTROL 0xD1F
612#define WM5100_IRQ_DEBOUNCE_1 0xD20
613#define WM5100_IRQ_DEBOUNCE_2 0xD21
614#define WM5100_FX_CTRL 0xE00
615#define WM5100_EQ1_1 0xE10
616#define WM5100_EQ1_2 0xE11
617#define WM5100_EQ1_3 0xE12
618#define WM5100_EQ1_4 0xE13
619#define WM5100_EQ1_5 0xE14
620#define WM5100_EQ1_6 0xE15
621#define WM5100_EQ1_7 0xE16
622#define WM5100_EQ1_8 0xE17
623#define WM5100_EQ1_9 0xE18
624#define WM5100_EQ1_10 0xE19
625#define WM5100_EQ1_11 0xE1A
626#define WM5100_EQ1_12 0xE1B
627#define WM5100_EQ1_13 0xE1C
628#define WM5100_EQ1_14 0xE1D
629#define WM5100_EQ1_15 0xE1E
630#define WM5100_EQ1_16 0xE1F
631#define WM5100_EQ1_17 0xE20
632#define WM5100_EQ1_18 0xE21
633#define WM5100_EQ1_19 0xE22
634#define WM5100_EQ1_20 0xE23
635#define WM5100_EQ2_1 0xE26
636#define WM5100_EQ2_2 0xE27
637#define WM5100_EQ2_3 0xE28
638#define WM5100_EQ2_4 0xE29
639#define WM5100_EQ2_5 0xE2A
640#define WM5100_EQ2_6 0xE2B
641#define WM5100_EQ2_7 0xE2C
642#define WM5100_EQ2_8 0xE2D
643#define WM5100_EQ2_9 0xE2E
644#define WM5100_EQ2_10 0xE2F
645#define WM5100_EQ2_11 0xE30
646#define WM5100_EQ2_12 0xE31
647#define WM5100_EQ2_13 0xE32
648#define WM5100_EQ2_14 0xE33
649#define WM5100_EQ2_15 0xE34
650#define WM5100_EQ2_16 0xE35
651#define WM5100_EQ2_17 0xE36
652#define WM5100_EQ2_18 0xE37
653#define WM5100_EQ2_19 0xE38
654#define WM5100_EQ2_20 0xE39
655#define WM5100_EQ3_1 0xE3C
656#define WM5100_EQ3_2 0xE3D
657#define WM5100_EQ3_3 0xE3E
658#define WM5100_EQ3_4 0xE3F
659#define WM5100_EQ3_5 0xE40
660#define WM5100_EQ3_6 0xE41
661#define WM5100_EQ3_7 0xE42
662#define WM5100_EQ3_8 0xE43
663#define WM5100_EQ3_9 0xE44
664#define WM5100_EQ3_10 0xE45
665#define WM5100_EQ3_11 0xE46
666#define WM5100_EQ3_12 0xE47
667#define WM5100_EQ3_13 0xE48
668#define WM5100_EQ3_14 0xE49
669#define WM5100_EQ3_15 0xE4A
670#define WM5100_EQ3_16 0xE4B
671#define WM5100_EQ3_17 0xE4C
672#define WM5100_EQ3_18 0xE4D
673#define WM5100_EQ3_19 0xE4E
674#define WM5100_EQ3_20 0xE4F
675#define WM5100_EQ4_1 0xE52
676#define WM5100_EQ4_2 0xE53
677#define WM5100_EQ4_3 0xE54
678#define WM5100_EQ4_4 0xE55
679#define WM5100_EQ4_5 0xE56
680#define WM5100_EQ4_6 0xE57
681#define WM5100_EQ4_7 0xE58
682#define WM5100_EQ4_8 0xE59
683#define WM5100_EQ4_9 0xE5A
684#define WM5100_EQ4_10 0xE5B
685#define WM5100_EQ4_11 0xE5C
686#define WM5100_EQ4_12 0xE5D
687#define WM5100_EQ4_13 0xE5E
688#define WM5100_EQ4_14 0xE5F
689#define WM5100_EQ4_15 0xE60
690#define WM5100_EQ4_16 0xE61
691#define WM5100_EQ4_17 0xE62
692#define WM5100_EQ4_18 0xE63
693#define WM5100_EQ4_19 0xE64
694#define WM5100_EQ4_20 0xE65
695#define WM5100_DRC1_CTRL1 0xE80
696#define WM5100_DRC1_CTRL2 0xE81
697#define WM5100_DRC1_CTRL3 0xE82
698#define WM5100_DRC1_CTRL4 0xE83
699#define WM5100_DRC1_CTRL5 0xE84
700#define WM5100_HPLPF1_1 0xEC0
701#define WM5100_HPLPF1_2 0xEC1
702#define WM5100_HPLPF2_1 0xEC4
703#define WM5100_HPLPF2_2 0xEC5
704#define WM5100_HPLPF3_1 0xEC8
705#define WM5100_HPLPF3_2 0xEC9
706#define WM5100_HPLPF4_1 0xECC
707#define WM5100_HPLPF4_2 0xECD
708#define WM5100_DSP1_DM_0 0x4000
709#define WM5100_DSP1_DM_1 0x4001
710#define WM5100_DSP1_DM_2 0x4002
711#define WM5100_DSP1_DM_3 0x4003
712#define WM5100_DSP1_DM_508 0x41FC
713#define WM5100_DSP1_DM_509 0x41FD
714#define WM5100_DSP1_DM_510 0x41FE
715#define WM5100_DSP1_DM_511 0x41FF
716#define WM5100_DSP1_PM_0 0x4800
717#define WM5100_DSP1_PM_1 0x4801
718#define WM5100_DSP1_PM_2 0x4802
719#define WM5100_DSP1_PM_3 0x4803
720#define WM5100_DSP1_PM_4 0x4804
721#define WM5100_DSP1_PM_5 0x4805
722#define WM5100_DSP1_PM_1530 0x4DFA
723#define WM5100_DSP1_PM_1531 0x4DFB
724#define WM5100_DSP1_PM_1532 0x4DFC
725#define WM5100_DSP1_PM_1533 0x4DFD
726#define WM5100_DSP1_PM_1534 0x4DFE
727#define WM5100_DSP1_PM_1535 0x4DFF
728#define WM5100_DSP1_ZM_0 0x5000
729#define WM5100_DSP1_ZM_1 0x5001
730#define WM5100_DSP1_ZM_2 0x5002
731#define WM5100_DSP1_ZM_3 0x5003
732#define WM5100_DSP1_ZM_2044 0x57FC
733#define WM5100_DSP1_ZM_2045 0x57FD
734#define WM5100_DSP1_ZM_2046 0x57FE
735#define WM5100_DSP1_ZM_2047 0x57FF
736#define WM5100_DSP2_DM_0 0x6000
737#define WM5100_DSP2_DM_1 0x6001
738#define WM5100_DSP2_DM_2 0x6002
739#define WM5100_DSP2_DM_3 0x6003
740#define WM5100_DSP2_DM_508 0x61FC
741#define WM5100_DSP2_DM_509 0x61FD
742#define WM5100_DSP2_DM_510 0x61FE
743#define WM5100_DSP2_DM_511 0x61FF
744#define WM5100_DSP2_PM_0 0x6800
745#define WM5100_DSP2_PM_1 0x6801
746#define WM5100_DSP2_PM_2 0x6802
747#define WM5100_DSP2_PM_3 0x6803
748#define WM5100_DSP2_PM_4 0x6804
749#define WM5100_DSP2_PM_5 0x6805
750#define WM5100_DSP2_PM_1530 0x6DFA
751#define WM5100_DSP2_PM_1531 0x6DFB
752#define WM5100_DSP2_PM_1532 0x6DFC
753#define WM5100_DSP2_PM_1533 0x6DFD
754#define WM5100_DSP2_PM_1534 0x6DFE
755#define WM5100_DSP2_PM_1535 0x6DFF
756#define WM5100_DSP2_ZM_0 0x7000
757#define WM5100_DSP2_ZM_1 0x7001
758#define WM5100_DSP2_ZM_2 0x7002
759#define WM5100_DSP2_ZM_3 0x7003
760#define WM5100_DSP2_ZM_2044 0x77FC
761#define WM5100_DSP2_ZM_2045 0x77FD
762#define WM5100_DSP2_ZM_2046 0x77FE
763#define WM5100_DSP2_ZM_2047 0x77FF
764#define WM5100_DSP3_DM_0 0x8000
765#define WM5100_DSP3_DM_1 0x8001
766#define WM5100_DSP3_DM_2 0x8002
767#define WM5100_DSP3_DM_3 0x8003
768#define WM5100_DSP3_DM_508 0x81FC
769#define WM5100_DSP3_DM_509 0x81FD
770#define WM5100_DSP3_DM_510 0x81FE
771#define WM5100_DSP3_DM_511 0x81FF
772#define WM5100_DSP3_PM_0 0x8800
773#define WM5100_DSP3_PM_1 0x8801
774#define WM5100_DSP3_PM_2 0x8802
775#define WM5100_DSP3_PM_3 0x8803
776#define WM5100_DSP3_PM_4 0x8804
777#define WM5100_DSP3_PM_5 0x8805
778#define WM5100_DSP3_PM_1530 0x8DFA
779#define WM5100_DSP3_PM_1531 0x8DFB
780#define WM5100_DSP3_PM_1532 0x8DFC
781#define WM5100_DSP3_PM_1533 0x8DFD
782#define WM5100_DSP3_PM_1534 0x8DFE
783#define WM5100_DSP3_PM_1535 0x8DFF
784#define WM5100_DSP3_ZM_0 0x9000
785#define WM5100_DSP3_ZM_1 0x9001
786#define WM5100_DSP3_ZM_2 0x9002
787#define WM5100_DSP3_ZM_3 0x9003
788#define WM5100_DSP3_ZM_2044 0x97FC
789#define WM5100_DSP3_ZM_2045 0x97FD
790#define WM5100_DSP3_ZM_2046 0x97FE
791#define WM5100_DSP3_ZM_2047 0x97FF
792
793#define WM5100_REGISTER_COUNT 1435
794#define WM5100_MAX_REGISTER 0x97FF
795
796/*
797 * Field Definitions.
798 */
799
800/*
801 * R0 (0x00) - software reset
802 */
803#define WM5100_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
804#define WM5100_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
805#define WM5100_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
806
807/*
808 * R1 (0x01) - Device Revision
809 */
810#define WM5100_DEVICE_REVISION_MASK 0x000F /* DEVICE_REVISION - [3:0] */
811#define WM5100_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [3:0] */
812#define WM5100_DEVICE_REVISION_WIDTH 4 /* DEVICE_REVISION - [3:0] */
813
814/*
815 * R16 (0x10) - Ctrl IF 1
816 */
817#define WM5100_AUTO_INC 0x0001 /* AUTO_INC */
818#define WM5100_AUTO_INC_MASK 0x0001 /* AUTO_INC */
819#define WM5100_AUTO_INC_SHIFT 0 /* AUTO_INC */
820#define WM5100_AUTO_INC_WIDTH 1 /* AUTO_INC */
821
822/*
823 * R32 (0x20) - Tone Generator 1
824 */
825#define WM5100_TONE_RATE_MASK 0x3000 /* TONE_RATE - [13:12] */
826#define WM5100_TONE_RATE_SHIFT 12 /* TONE_RATE - [13:12] */
827#define WM5100_TONE_RATE_WIDTH 2 /* TONE_RATE - [13:12] */
828#define WM5100_TONE_OFFSET_MASK 0x0300 /* TONE_OFFSET - [9:8] */
829#define WM5100_TONE_OFFSET_SHIFT 8 /* TONE_OFFSET - [9:8] */
830#define WM5100_TONE_OFFSET_WIDTH 2 /* TONE_OFFSET - [9:8] */
831#define WM5100_TONE2_ENA 0x0002 /* TONE2_ENA */
832#define WM5100_TONE2_ENA_MASK 0x0002 /* TONE2_ENA */
833#define WM5100_TONE2_ENA_SHIFT 1 /* TONE2_ENA */
834#define WM5100_TONE2_ENA_WIDTH 1 /* TONE2_ENA */
835#define WM5100_TONE1_ENA 0x0001 /* TONE1_ENA */
836#define WM5100_TONE1_ENA_MASK 0x0001 /* TONE1_ENA */
837#define WM5100_TONE1_ENA_SHIFT 0 /* TONE1_ENA */
838#define WM5100_TONE1_ENA_WIDTH 1 /* TONE1_ENA */
839
840/*
841 * R48 (0x30) - PWM Drive 1
842 */
843#define WM5100_PWM_RATE_MASK 0x3000 /* PWM_RATE - [13:12] */
844#define WM5100_PWM_RATE_SHIFT 12 /* PWM_RATE - [13:12] */
845#define WM5100_PWM_RATE_WIDTH 2 /* PWM_RATE - [13:12] */
846#define WM5100_PWM_CLK_SEL_MASK 0x0300 /* PWM_CLK_SEL - [9:8] */
847#define WM5100_PWM_CLK_SEL_SHIFT 8 /* PWM_CLK_SEL - [9:8] */
848#define WM5100_PWM_CLK_SEL_WIDTH 2 /* PWM_CLK_SEL - [9:8] */
849#define WM5100_PWM2_OVD 0x0020 /* PWM2_OVD */
850#define WM5100_PWM2_OVD_MASK 0x0020 /* PWM2_OVD */
851#define WM5100_PWM2_OVD_SHIFT 5 /* PWM2_OVD */
852#define WM5100_PWM2_OVD_WIDTH 1 /* PWM2_OVD */
853#define WM5100_PWM1_OVD 0x0010 /* PWM1_OVD */
854#define WM5100_PWM1_OVD_MASK 0x0010 /* PWM1_OVD */
855#define WM5100_PWM1_OVD_SHIFT 4 /* PWM1_OVD */
856#define WM5100_PWM1_OVD_WIDTH 1 /* PWM1_OVD */
857#define WM5100_PWM2_ENA 0x0002 /* PWM2_ENA */
858#define WM5100_PWM2_ENA_MASK 0x0002 /* PWM2_ENA */
859#define WM5100_PWM2_ENA_SHIFT 1 /* PWM2_ENA */
860#define WM5100_PWM2_ENA_WIDTH 1 /* PWM2_ENA */
861#define WM5100_PWM1_ENA 0x0001 /* PWM1_ENA */
862#define WM5100_PWM1_ENA_MASK 0x0001 /* PWM1_ENA */
863#define WM5100_PWM1_ENA_SHIFT 0 /* PWM1_ENA */
864#define WM5100_PWM1_ENA_WIDTH 1 /* PWM1_ENA */
865
866/*
867 * R49 (0x31) - PWM Drive 2
868 */
869#define WM5100_PWM1_LVL_MASK 0x03FF /* PWM1_LVL - [9:0] */
870#define WM5100_PWM1_LVL_SHIFT 0 /* PWM1_LVL - [9:0] */
871#define WM5100_PWM1_LVL_WIDTH 10 /* PWM1_LVL - [9:0] */
872
873/*
874 * R50 (0x32) - PWM Drive 3
875 */
876#define WM5100_PWM2_LVL_MASK 0x03FF /* PWM2_LVL - [9:0] */
877#define WM5100_PWM2_LVL_SHIFT 0 /* PWM2_LVL - [9:0] */
878#define WM5100_PWM2_LVL_WIDTH 10 /* PWM2_LVL - [9:0] */
879
880/*
881 * R256 (0x100) - Clocking 1
882 */
883#define WM5100_CLK_32K_SRC_MASK 0x000F /* CLK_32K_SRC - [3:0] */
884#define WM5100_CLK_32K_SRC_SHIFT 0 /* CLK_32K_SRC - [3:0] */
885#define WM5100_CLK_32K_SRC_WIDTH 4 /* CLK_32K_SRC - [3:0] */
886
887/*
888 * R257 (0x101) - Clocking 3
889 */
890#define WM5100_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */
891#define WM5100_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */
892#define WM5100_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */
893#define WM5100_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */
894#define WM5100_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */
895#define WM5100_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */
896#define WM5100_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */
897#define WM5100_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */
898#define WM5100_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */
899#define WM5100_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */
900
901/*
902 * R258 (0x102) - Clocking 4
903 */
904#define WM5100_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */
905#define WM5100_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */
906#define WM5100_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */
907
908/*
909 * R259 (0x103) - Clocking 5
910 */
911#define WM5100_SAMPLE_RATE_2_MASK 0x001F /* SAMPLE_RATE_2 - [4:0] */
912#define WM5100_SAMPLE_RATE_2_SHIFT 0 /* SAMPLE_RATE_2 - [4:0] */
913#define WM5100_SAMPLE_RATE_2_WIDTH 5 /* SAMPLE_RATE_2 - [4:0] */
914
915/*
916 * R260 (0x104) - Clocking 6
917 */
918#define WM5100_SAMPLE_RATE_3_MASK 0x001F /* SAMPLE_RATE_3 - [4:0] */
919#define WM5100_SAMPLE_RATE_3_SHIFT 0 /* SAMPLE_RATE_3 - [4:0] */
920#define WM5100_SAMPLE_RATE_3_WIDTH 5 /* SAMPLE_RATE_3 - [4:0] */
921
922/*
923 * R263 (0x107) - Clocking 7
924 */
925#define WM5100_ASYNC_CLK_FREQ_MASK 0x0700 /* ASYNC_CLK_FREQ - [10:8] */
926#define WM5100_ASYNC_CLK_FREQ_SHIFT 8 /* ASYNC_CLK_FREQ - [10:8] */
927#define WM5100_ASYNC_CLK_FREQ_WIDTH 3 /* ASYNC_CLK_FREQ - [10:8] */
928#define WM5100_ASYNC_CLK_ENA 0x0040 /* ASYNC_CLK_ENA */
929#define WM5100_ASYNC_CLK_ENA_MASK 0x0040 /* ASYNC_CLK_ENA */
930#define WM5100_ASYNC_CLK_ENA_SHIFT 6 /* ASYNC_CLK_ENA */
931#define WM5100_ASYNC_CLK_ENA_WIDTH 1 /* ASYNC_CLK_ENA */
932#define WM5100_ASYNC_CLK_SRC_MASK 0x000F /* ASYNC_CLK_SRC - [3:0] */
933#define WM5100_ASYNC_CLK_SRC_SHIFT 0 /* ASYNC_CLK_SRC - [3:0] */
934#define WM5100_ASYNC_CLK_SRC_WIDTH 4 /* ASYNC_CLK_SRC - [3:0] */
935
936/*
937 * R264 (0x108) - Clocking 8
938 */
939#define WM5100_ASYNC_SAMPLE_RATE_MASK 0x001F /* ASYNC_SAMPLE_RATE - [4:0] */
940#define WM5100_ASYNC_SAMPLE_RATE_SHIFT 0 /* ASYNC_SAMPLE_RATE - [4:0] */
941#define WM5100_ASYNC_SAMPLE_RATE_WIDTH 5 /* ASYNC_SAMPLE_RATE - [4:0] */
942
943/*
944 * R288 (0x120) - ASRC_ENABLE
945 */
946#define WM5100_ASRC2L_ENA 0x0008 /* ASRC2L_ENA */
947#define WM5100_ASRC2L_ENA_MASK 0x0008 /* ASRC2L_ENA */
948#define WM5100_ASRC2L_ENA_SHIFT 3 /* ASRC2L_ENA */
949#define WM5100_ASRC2L_ENA_WIDTH 1 /* ASRC2L_ENA */
950#define WM5100_ASRC2R_ENA 0x0004 /* ASRC2R_ENA */
951#define WM5100_ASRC2R_ENA_MASK 0x0004 /* ASRC2R_ENA */
952#define WM5100_ASRC2R_ENA_SHIFT 2 /* ASRC2R_ENA */
953#define WM5100_ASRC2R_ENA_WIDTH 1 /* ASRC2R_ENA */
954#define WM5100_ASRC1L_ENA 0x0002 /* ASRC1L_ENA */
955#define WM5100_ASRC1L_ENA_MASK 0x0002 /* ASRC1L_ENA */
956#define WM5100_ASRC1L_ENA_SHIFT 1 /* ASRC1L_ENA */
957#define WM5100_ASRC1L_ENA_WIDTH 1 /* ASRC1L_ENA */
958#define WM5100_ASRC1R_ENA 0x0001 /* ASRC1R_ENA */
959#define WM5100_ASRC1R_ENA_MASK 0x0001 /* ASRC1R_ENA */
960#define WM5100_ASRC1R_ENA_SHIFT 0 /* ASRC1R_ENA */
961#define WM5100_ASRC1R_ENA_WIDTH 1 /* ASRC1R_ENA */
962
963/*
964 * R289 (0x121) - ASRC_STATUS
965 */
966#define WM5100_ASRC2L_ENA_STS 0x0008 /* ASRC2L_ENA_STS */
967#define WM5100_ASRC2L_ENA_STS_MASK 0x0008 /* ASRC2L_ENA_STS */
968#define WM5100_ASRC2L_ENA_STS_SHIFT 3 /* ASRC2L_ENA_STS */
969#define WM5100_ASRC2L_ENA_STS_WIDTH 1 /* ASRC2L_ENA_STS */
970#define WM5100_ASRC2R_ENA_STS 0x0004 /* ASRC2R_ENA_STS */
971#define WM5100_ASRC2R_ENA_STS_MASK 0x0004 /* ASRC2R_ENA_STS */
972#define WM5100_ASRC2R_ENA_STS_SHIFT 2 /* ASRC2R_ENA_STS */
973#define WM5100_ASRC2R_ENA_STS_WIDTH 1 /* ASRC2R_ENA_STS */
974#define WM5100_ASRC1L_ENA_STS 0x0002 /* ASRC1L_ENA_STS */
975#define WM5100_ASRC1L_ENA_STS_MASK 0x0002 /* ASRC1L_ENA_STS */
976#define WM5100_ASRC1L_ENA_STS_SHIFT 1 /* ASRC1L_ENA_STS */
977#define WM5100_ASRC1L_ENA_STS_WIDTH 1 /* ASRC1L_ENA_STS */
978#define WM5100_ASRC1R_ENA_STS 0x0001 /* ASRC1R_ENA_STS */
979#define WM5100_ASRC1R_ENA_STS_MASK 0x0001 /* ASRC1R_ENA_STS */
980#define WM5100_ASRC1R_ENA_STS_SHIFT 0 /* ASRC1R_ENA_STS */
981#define WM5100_ASRC1R_ENA_STS_WIDTH 1 /* ASRC1R_ENA_STS */
982
983/*
984 * R290 (0x122) - ASRC_RATE1
985 */
986#define WM5100_ASRC_RATE1_MASK 0x0006 /* ASRC_RATE1 - [2:1] */
987#define WM5100_ASRC_RATE1_SHIFT 1 /* ASRC_RATE1 - [2:1] */
988#define WM5100_ASRC_RATE1_WIDTH 2 /* ASRC_RATE1 - [2:1] */
989
990/*
991 * R321 (0x141) - ISRC 1 CTRL 1
992 */
993#define WM5100_ISRC1_DFS_ENA 0x2000 /* ISRC1_DFS_ENA */
994#define WM5100_ISRC1_DFS_ENA_MASK 0x2000 /* ISRC1_DFS_ENA */
995#define WM5100_ISRC1_DFS_ENA_SHIFT 13 /* ISRC1_DFS_ENA */
996#define WM5100_ISRC1_DFS_ENA_WIDTH 1 /* ISRC1_DFS_ENA */
997#define WM5100_ISRC1_CLK_SEL_MASK 0x0300 /* ISRC1_CLK_SEL - [9:8] */
998#define WM5100_ISRC1_CLK_SEL_SHIFT 8 /* ISRC1_CLK_SEL - [9:8] */
999#define WM5100_ISRC1_CLK_SEL_WIDTH 2 /* ISRC1_CLK_SEL - [9:8] */
1000#define WM5100_ISRC1_FSH_MASK 0x000C /* ISRC1_FSH - [3:2] */
1001#define WM5100_ISRC1_FSH_SHIFT 2 /* ISRC1_FSH - [3:2] */
1002#define WM5100_ISRC1_FSH_WIDTH 2 /* ISRC1_FSH - [3:2] */
1003#define WM5100_ISRC1_FSL_MASK 0x0003 /* ISRC1_FSL - [1:0] */
1004#define WM5100_ISRC1_FSL_SHIFT 0 /* ISRC1_FSL - [1:0] */
1005#define WM5100_ISRC1_FSL_WIDTH 2 /* ISRC1_FSL - [1:0] */
1006
1007/*
1008 * R322 (0x142) - ISRC 1 CTRL 2
1009 */
1010#define WM5100_ISRC1_INT1_ENA 0x8000 /* ISRC1_INT1_ENA */
1011#define WM5100_ISRC1_INT1_ENA_MASK 0x8000 /* ISRC1_INT1_ENA */
1012#define WM5100_ISRC1_INT1_ENA_SHIFT 15 /* ISRC1_INT1_ENA */
1013#define WM5100_ISRC1_INT1_ENA_WIDTH 1 /* ISRC1_INT1_ENA */
1014#define WM5100_ISRC1_INT2_ENA 0x4000 /* ISRC1_INT2_ENA */
1015#define WM5100_ISRC1_INT2_ENA_MASK 0x4000 /* ISRC1_INT2_ENA */
1016#define WM5100_ISRC1_INT2_ENA_SHIFT 14 /* ISRC1_INT2_ENA */
1017#define WM5100_ISRC1_INT2_ENA_WIDTH 1 /* ISRC1_INT2_ENA */
1018#define WM5100_ISRC1_INT3_ENA 0x2000 /* ISRC1_INT3_ENA */
1019#define WM5100_ISRC1_INT3_ENA_MASK 0x2000 /* ISRC1_INT3_ENA */
1020#define WM5100_ISRC1_INT3_ENA_SHIFT 13 /* ISRC1_INT3_ENA */
1021#define WM5100_ISRC1_INT3_ENA_WIDTH 1 /* ISRC1_INT3_ENA */
1022#define WM5100_ISRC1_INT4_ENA 0x1000 /* ISRC1_INT4_ENA */
1023#define WM5100_ISRC1_INT4_ENA_MASK 0x1000 /* ISRC1_INT4_ENA */
1024#define WM5100_ISRC1_INT4_ENA_SHIFT 12 /* ISRC1_INT4_ENA */
1025#define WM5100_ISRC1_INT4_ENA_WIDTH 1 /* ISRC1_INT4_ENA */
1026#define WM5100_ISRC1_DEC1_ENA 0x0200 /* ISRC1_DEC1_ENA */
1027#define WM5100_ISRC1_DEC1_ENA_MASK 0x0200 /* ISRC1_DEC1_ENA */
1028#define WM5100_ISRC1_DEC1_ENA_SHIFT 9 /* ISRC1_DEC1_ENA */
1029#define WM5100_ISRC1_DEC1_ENA_WIDTH 1 /* ISRC1_DEC1_ENA */
1030#define WM5100_ISRC1_DEC2_ENA 0x0100 /* ISRC1_DEC2_ENA */
1031#define WM5100_ISRC1_DEC2_ENA_MASK 0x0100 /* ISRC1_DEC2_ENA */
1032#define WM5100_ISRC1_DEC2_ENA_SHIFT 8 /* ISRC1_DEC2_ENA */
1033#define WM5100_ISRC1_DEC2_ENA_WIDTH 1 /* ISRC1_DEC2_ENA */
1034#define WM5100_ISRC1_DEC3_ENA 0x0080 /* ISRC1_DEC3_ENA */
1035#define WM5100_ISRC1_DEC3_ENA_MASK 0x0080 /* ISRC1_DEC3_ENA */
1036#define WM5100_ISRC1_DEC3_ENA_SHIFT 7 /* ISRC1_DEC3_ENA */
1037#define WM5100_ISRC1_DEC3_ENA_WIDTH 1 /* ISRC1_DEC3_ENA */
1038#define WM5100_ISRC1_DEC4_ENA 0x0040 /* ISRC1_DEC4_ENA */
1039#define WM5100_ISRC1_DEC4_ENA_MASK 0x0040 /* ISRC1_DEC4_ENA */
1040#define WM5100_ISRC1_DEC4_ENA_SHIFT 6 /* ISRC1_DEC4_ENA */
1041#define WM5100_ISRC1_DEC4_ENA_WIDTH 1 /* ISRC1_DEC4_ENA */
1042#define WM5100_ISRC1_NOTCH_ENA 0x0001 /* ISRC1_NOTCH_ENA */
1043#define WM5100_ISRC1_NOTCH_ENA_MASK 0x0001 /* ISRC1_NOTCH_ENA */
1044#define WM5100_ISRC1_NOTCH_ENA_SHIFT 0 /* ISRC1_NOTCH_ENA */
1045#define WM5100_ISRC1_NOTCH_ENA_WIDTH 1 /* ISRC1_NOTCH_ENA */
1046
1047/*
1048 * R323 (0x143) - ISRC 2 CTRL1
1049 */
1050#define WM5100_ISRC2_DFS_ENA 0x2000 /* ISRC2_DFS_ENA */
1051#define WM5100_ISRC2_DFS_ENA_MASK 0x2000 /* ISRC2_DFS_ENA */
1052#define WM5100_ISRC2_DFS_ENA_SHIFT 13 /* ISRC2_DFS_ENA */
1053#define WM5100_ISRC2_DFS_ENA_WIDTH 1 /* ISRC2_DFS_ENA */
1054#define WM5100_ISRC2_CLK_SEL_MASK 0x0300 /* ISRC2_CLK_SEL - [9:8] */
1055#define WM5100_ISRC2_CLK_SEL_SHIFT 8 /* ISRC2_CLK_SEL - [9:8] */
1056#define WM5100_ISRC2_CLK_SEL_WIDTH 2 /* ISRC2_CLK_SEL - [9:8] */
1057#define WM5100_ISRC2_FSH_MASK 0x000C /* ISRC2_FSH - [3:2] */
1058#define WM5100_ISRC2_FSH_SHIFT 2 /* ISRC2_FSH - [3:2] */
1059#define WM5100_ISRC2_FSH_WIDTH 2 /* ISRC2_FSH - [3:2] */
1060#define WM5100_ISRC2_FSL_MASK 0x0003 /* ISRC2_FSL - [1:0] */
1061#define WM5100_ISRC2_FSL_SHIFT 0 /* ISRC2_FSL - [1:0] */
1062#define WM5100_ISRC2_FSL_WIDTH 2 /* ISRC2_FSL - [1:0] */
1063
1064/*
1065 * R324 (0x144) - ISRC 2 CTRL 2
1066 */
1067#define WM5100_ISRC2_INT1_ENA 0x8000 /* ISRC2_INT1_ENA */
1068#define WM5100_ISRC2_INT1_ENA_MASK 0x8000 /* ISRC2_INT1_ENA */
1069#define WM5100_ISRC2_INT1_ENA_SHIFT 15 /* ISRC2_INT1_ENA */
1070#define WM5100_ISRC2_INT1_ENA_WIDTH 1 /* ISRC2_INT1_ENA */
1071#define WM5100_ISRC2_INT2_ENA 0x4000 /* ISRC2_INT2_ENA */
1072#define WM5100_ISRC2_INT2_ENA_MASK 0x4000 /* ISRC2_INT2_ENA */
1073#define WM5100_ISRC2_INT2_ENA_SHIFT 14 /* ISRC2_INT2_ENA */
1074#define WM5100_ISRC2_INT2_ENA_WIDTH 1 /* ISRC2_INT2_ENA */
1075#define WM5100_ISRC2_INT3_ENA 0x2000 /* ISRC2_INT3_ENA */
1076#define WM5100_ISRC2_INT3_ENA_MASK 0x2000 /* ISRC2_INT3_ENA */
1077#define WM5100_ISRC2_INT3_ENA_SHIFT 13 /* ISRC2_INT3_ENA */
1078#define WM5100_ISRC2_INT3_ENA_WIDTH 1 /* ISRC2_INT3_ENA */
1079#define WM5100_ISRC2_INT4_ENA 0x1000 /* ISRC2_INT4_ENA */
1080#define WM5100_ISRC2_INT4_ENA_MASK 0x1000 /* ISRC2_INT4_ENA */
1081#define WM5100_ISRC2_INT4_ENA_SHIFT 12 /* ISRC2_INT4_ENA */
1082#define WM5100_ISRC2_INT4_ENA_WIDTH 1 /* ISRC2_INT4_ENA */
1083#define WM5100_ISRC2_DEC1_ENA 0x0200 /* ISRC2_DEC1_ENA */
1084#define WM5100_ISRC2_DEC1_ENA_MASK 0x0200 /* ISRC2_DEC1_ENA */
1085#define WM5100_ISRC2_DEC1_ENA_SHIFT 9 /* ISRC2_DEC1_ENA */
1086#define WM5100_ISRC2_DEC1_ENA_WIDTH 1 /* ISRC2_DEC1_ENA */
1087#define WM5100_ISRC2_DEC2_ENA 0x0100 /* ISRC2_DEC2_ENA */
1088#define WM5100_ISRC2_DEC2_ENA_MASK 0x0100 /* ISRC2_DEC2_ENA */
1089#define WM5100_ISRC2_DEC2_ENA_SHIFT 8 /* ISRC2_DEC2_ENA */
1090#define WM5100_ISRC2_DEC2_ENA_WIDTH 1 /* ISRC2_DEC2_ENA */
1091#define WM5100_ISRC2_DEC3_ENA 0x0080 /* ISRC2_DEC3_ENA */
1092#define WM5100_ISRC2_DEC3_ENA_MASK 0x0080 /* ISRC2_DEC3_ENA */
1093#define WM5100_ISRC2_DEC3_ENA_SHIFT 7 /* ISRC2_DEC3_ENA */
1094#define WM5100_ISRC2_DEC3_ENA_WIDTH 1 /* ISRC2_DEC3_ENA */
1095#define WM5100_ISRC2_DEC4_ENA 0x0040 /* ISRC2_DEC4_ENA */
1096#define WM5100_ISRC2_DEC4_ENA_MASK 0x0040 /* ISRC2_DEC4_ENA */
1097#define WM5100_ISRC2_DEC4_ENA_SHIFT 6 /* ISRC2_DEC4_ENA */
1098#define WM5100_ISRC2_DEC4_ENA_WIDTH 1 /* ISRC2_DEC4_ENA */
1099#define WM5100_ISRC2_NOTCH_ENA 0x0001 /* ISRC2_NOTCH_ENA */
1100#define WM5100_ISRC2_NOTCH_ENA_MASK 0x0001 /* ISRC2_NOTCH_ENA */
1101#define WM5100_ISRC2_NOTCH_ENA_SHIFT 0 /* ISRC2_NOTCH_ENA */
1102#define WM5100_ISRC2_NOTCH_ENA_WIDTH 1 /* ISRC2_NOTCH_ENA */
1103
1104/*
1105 * R386 (0x182) - FLL1 Control 1
1106 */
1107#define WM5100_FLL1_ENA 0x0001 /* FLL1_ENA */
1108#define WM5100_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */
1109#define WM5100_FLL1_ENA_SHIFT 0 /* FLL1_ENA */
1110#define WM5100_FLL1_ENA_WIDTH 1 /* FLL1_ENA */
1111
1112/*
1113 * R387 (0x183) - FLL1 Control 2
1114 */
1115#define WM5100_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */
1116#define WM5100_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */
1117#define WM5100_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */
1118#define WM5100_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */
1119#define WM5100_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */
1120#define WM5100_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */
1121
1122/*
1123 * R388 (0x184) - FLL1 Control 3
1124 */
1125#define WM5100_FLL1_THETA_MASK 0xFFFF /* FLL1_THETA - [15:0] */
1126#define WM5100_FLL1_THETA_SHIFT 0 /* FLL1_THETA - [15:0] */
1127#define WM5100_FLL1_THETA_WIDTH 16 /* FLL1_THETA - [15:0] */
1128
1129/*
1130 * R390 (0x186) - FLL1 Control 5
1131 */
1132#define WM5100_FLL1_N_MASK 0x03FF /* FLL1_N - [9:0] */
1133#define WM5100_FLL1_N_SHIFT 0 /* FLL1_N - [9:0] */
1134#define WM5100_FLL1_N_WIDTH 10 /* FLL1_N - [9:0] */
1135
1136/*
1137 * R391 (0x187) - FLL1 Control 6
1138 */
1139#define WM5100_FLL1_REFCLK_DIV_MASK 0x00C0 /* FLL1_REFCLK_DIV - [7:6] */
1140#define WM5100_FLL1_REFCLK_DIV_SHIFT 6 /* FLL1_REFCLK_DIV - [7:6] */
1141#define WM5100_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [7:6] */
1142#define WM5100_FLL1_REFCLK_SRC_MASK 0x000F /* FLL1_REFCLK_SRC - [3:0] */
1143#define WM5100_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [3:0] */
1144#define WM5100_FLL1_REFCLK_SRC_WIDTH 4 /* FLL1_REFCLK_SRC - [3:0] */
1145
1146/*
1147 * R392 (0x188) - FLL1 EFS 1
1148 */
1149#define WM5100_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */
1150#define WM5100_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */
1151#define WM5100_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */
1152
1153/*
1154 * R418 (0x1A2) - FLL2 Control 1
1155 */
1156#define WM5100_FLL2_ENA 0x0001 /* FLL2_ENA */
1157#define WM5100_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */
1158#define WM5100_FLL2_ENA_SHIFT 0 /* FLL2_ENA */
1159#define WM5100_FLL2_ENA_WIDTH 1 /* FLL2_ENA */
1160
1161/*
1162 * R419 (0x1A3) - FLL2 Control 2
1163 */
1164#define WM5100_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */
1165#define WM5100_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */
1166#define WM5100_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */
1167#define WM5100_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */
1168#define WM5100_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */
1169#define WM5100_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */
1170
1171/*
1172 * R420 (0x1A4) - FLL2 Control 3
1173 */
1174#define WM5100_FLL2_THETA_MASK 0xFFFF /* FLL2_THETA - [15:0] */
1175#define WM5100_FLL2_THETA_SHIFT 0 /* FLL2_THETA - [15:0] */
1176#define WM5100_FLL2_THETA_WIDTH 16 /* FLL2_THETA - [15:0] */
1177
1178/*
1179 * R422 (0x1A6) - FLL2 Control 5
1180 */
1181#define WM5100_FLL2_N_MASK 0x03FF /* FLL2_N - [9:0] */
1182#define WM5100_FLL2_N_SHIFT 0 /* FLL2_N - [9:0] */
1183#define WM5100_FLL2_N_WIDTH 10 /* FLL2_N - [9:0] */
1184
1185/*
1186 * R423 (0x1A7) - FLL2 Control 6
1187 */
1188#define WM5100_FLL2_REFCLK_DIV_MASK 0x00C0 /* FLL2_REFCLK_DIV - [7:6] */
1189#define WM5100_FLL2_REFCLK_DIV_SHIFT 6 /* FLL2_REFCLK_DIV - [7:6] */
1190#define WM5100_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [7:6] */
1191#define WM5100_FLL2_REFCLK_SRC_MASK 0x000F /* FLL2_REFCLK_SRC - [3:0] */
1192#define WM5100_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [3:0] */
1193#define WM5100_FLL2_REFCLK_SRC_WIDTH 4 /* FLL2_REFCLK_SRC - [3:0] */
1194
1195/*
1196 * R424 (0x1A8) - FLL2 EFS 1
1197 */
1198#define WM5100_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */
1199#define WM5100_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */
1200#define WM5100_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */
1201
1202/*
1203 * R512 (0x200) - Mic Charge Pump 1
1204 */
1205#define WM5100_CP2_BYPASS 0x0020 /* CP2_BYPASS */
1206#define WM5100_CP2_BYPASS_MASK 0x0020 /* CP2_BYPASS */
1207#define WM5100_CP2_BYPASS_SHIFT 5 /* CP2_BYPASS */
1208#define WM5100_CP2_BYPASS_WIDTH 1 /* CP2_BYPASS */
1209#define WM5100_CP2_ENA 0x0001 /* CP2_ENA */
1210#define WM5100_CP2_ENA_MASK 0x0001 /* CP2_ENA */
1211#define WM5100_CP2_ENA_SHIFT 0 /* CP2_ENA */
1212#define WM5100_CP2_ENA_WIDTH 1 /* CP2_ENA */
1213
1214/*
1215 * R513 (0x201) - Mic Charge Pump 2
1216 */
1217#define WM5100_LDO2_VSEL_MASK 0xF800 /* LDO2_VSEL - [15:11] */
1218#define WM5100_LDO2_VSEL_SHIFT 11 /* LDO2_VSEL - [15:11] */
1219#define WM5100_LDO2_VSEL_WIDTH 5 /* LDO2_VSEL - [15:11] */
1220
1221/*
1222 * R514 (0x202) - HP Charge Pump 1
1223 */
1224#define WM5100_CP1_ENA 0x0001 /* CP1_ENA */
1225#define WM5100_CP1_ENA_MASK 0x0001 /* CP1_ENA */
1226#define WM5100_CP1_ENA_SHIFT 0 /* CP1_ENA */
1227#define WM5100_CP1_ENA_WIDTH 1 /* CP1_ENA */
1228
1229/*
1230 * R529 (0x211) - LDO1 Control
1231 */
1232#define WM5100_LDO1_BYPASS 0x0002 /* LDO1_BYPASS */
1233#define WM5100_LDO1_BYPASS_MASK 0x0002 /* LDO1_BYPASS */
1234#define WM5100_LDO1_BYPASS_SHIFT 1 /* LDO1_BYPASS */
1235#define WM5100_LDO1_BYPASS_WIDTH 1 /* LDO1_BYPASS */
1236
1237/*
1238 * R533 (0x215) - Mic Bias Ctrl 1
1239 */
1240#define WM5100_MICB1_DISCH 0x0040 /* MICB1_DISCH */
1241#define WM5100_MICB1_DISCH_MASK 0x0040 /* MICB1_DISCH */
1242#define WM5100_MICB1_DISCH_SHIFT 6 /* MICB1_DISCH */
1243#define WM5100_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
1244#define WM5100_MICB1_RATE 0x0020 /* MICB1_RATE */
1245#define WM5100_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */
1246#define WM5100_MICB1_RATE_SHIFT 5 /* MICB1_RATE */
1247#define WM5100_MICB1_RATE_WIDTH 1 /* MICB1_RATE */
1248#define WM5100_MICB1_LVL_MASK 0x001C /* MICB1_LVL - [4:2] */
1249#define WM5100_MICB1_LVL_SHIFT 2 /* MICB1_LVL - [4:2] */
1250#define WM5100_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [4:2] */
1251#define WM5100_MICB1_BYPASS 0x0002 /* MICB1_BYPASS */
1252#define WM5100_MICB1_BYPASS_MASK 0x0002 /* MICB1_BYPASS */
1253#define WM5100_MICB1_BYPASS_SHIFT 1 /* MICB1_BYPASS */
1254#define WM5100_MICB1_BYPASS_WIDTH 1 /* MICB1_BYPASS */
1255#define WM5100_MICB1_ENA 0x0001 /* MICB1_ENA */
1256#define WM5100_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */
1257#define WM5100_MICB1_ENA_SHIFT 0 /* MICB1_ENA */
1258#define WM5100_MICB1_ENA_WIDTH 1 /* MICB1_ENA */
1259
1260/*
1261 * R534 (0x216) - Mic Bias Ctrl 2
1262 */
1263#define WM5100_MICB2_DISCH 0x0040 /* MICB2_DISCH */
1264#define WM5100_MICB2_DISCH_MASK 0x0040 /* MICB2_DISCH */
1265#define WM5100_MICB2_DISCH_SHIFT 6 /* MICB2_DISCH */
1266#define WM5100_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
1267#define WM5100_MICB2_RATE 0x0020 /* MICB2_RATE */
1268#define WM5100_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */
1269#define WM5100_MICB2_RATE_SHIFT 5 /* MICB2_RATE */
1270#define WM5100_MICB2_RATE_WIDTH 1 /* MICB2_RATE */
1271#define WM5100_MICB2_LVL_MASK 0x001C /* MICB2_LVL - [4:2] */
1272#define WM5100_MICB2_LVL_SHIFT 2 /* MICB2_LVL - [4:2] */
1273#define WM5100_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [4:2] */
1274#define WM5100_MICB2_BYPASS 0x0002 /* MICB2_BYPASS */
1275#define WM5100_MICB2_BYPASS_MASK 0x0002 /* MICB2_BYPASS */
1276#define WM5100_MICB2_BYPASS_SHIFT 1 /* MICB2_BYPASS */
1277#define WM5100_MICB2_BYPASS_WIDTH 1 /* MICB2_BYPASS */
1278#define WM5100_MICB2_ENA 0x0001 /* MICB2_ENA */
1279#define WM5100_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */
1280#define WM5100_MICB2_ENA_SHIFT 0 /* MICB2_ENA */
1281#define WM5100_MICB2_ENA_WIDTH 1 /* MICB2_ENA */
1282
1283/*
1284 * R535 (0x217) - Mic Bias Ctrl 3
1285 */
1286#define WM5100_MICB3_DISCH 0x0040 /* MICB3_DISCH */
1287#define WM5100_MICB3_DISCH_MASK 0x0040 /* MICB3_DISCH */
1288#define WM5100_MICB3_DISCH_SHIFT 6 /* MICB3_DISCH */
1289#define WM5100_MICB3_DISCH_WIDTH 1 /* MICB3_DISCH */
1290#define WM5100_MICB3_RATE 0x0020 /* MICB3_RATE */
1291#define WM5100_MICB3_RATE_MASK 0x0020 /* MICB3_RATE */
1292#define WM5100_MICB3_RATE_SHIFT 5 /* MICB3_RATE */
1293#define WM5100_MICB3_RATE_WIDTH 1 /* MICB3_RATE */
1294#define WM5100_MICB3_LVL_MASK 0x001C /* MICB3_LVL - [4:2] */
1295#define WM5100_MICB3_LVL_SHIFT 2 /* MICB3_LVL - [4:2] */
1296#define WM5100_MICB3_LVL_WIDTH 3 /* MICB3_LVL - [4:2] */
1297#define WM5100_MICB3_BYPASS 0x0002 /* MICB3_BYPASS */
1298#define WM5100_MICB3_BYPASS_MASK 0x0002 /* MICB3_BYPASS */
1299#define WM5100_MICB3_BYPASS_SHIFT 1 /* MICB3_BYPASS */
1300#define WM5100_MICB3_BYPASS_WIDTH 1 /* MICB3_BYPASS */
1301#define WM5100_MICB3_ENA 0x0001 /* MICB3_ENA */
1302#define WM5100_MICB3_ENA_MASK 0x0001 /* MICB3_ENA */
1303#define WM5100_MICB3_ENA_SHIFT 0 /* MICB3_ENA */
1304#define WM5100_MICB3_ENA_WIDTH 1 /* MICB3_ENA */
1305
1306/*
1307 * R640 (0x280) - Accessory Detect Mode 1
1308 */
1309#define WM5100_ACCDET_BIAS_SRC_MASK 0xC000 /* ACCDET_BIAS_SRC - [15:14] */
1310#define WM5100_ACCDET_BIAS_SRC_SHIFT 14 /* ACCDET_BIAS_SRC - [15:14] */
1311#define WM5100_ACCDET_BIAS_SRC_WIDTH 2 /* ACCDET_BIAS_SRC - [15:14] */
1312#define WM5100_ACCDET_SRC 0x2000 /* ACCDET_SRC */
1313#define WM5100_ACCDET_SRC_MASK 0x2000 /* ACCDET_SRC */
1314#define WM5100_ACCDET_SRC_SHIFT 13 /* ACCDET_SRC */
1315#define WM5100_ACCDET_SRC_WIDTH 1 /* ACCDET_SRC */
1316#define WM5100_ACCDET_MODE_MASK 0x0003 /* ACCDET_MODE - [1:0] */
1317#define WM5100_ACCDET_MODE_SHIFT 0 /* ACCDET_MODE - [1:0] */
1318#define WM5100_ACCDET_MODE_WIDTH 2 /* ACCDET_MODE - [1:0] */
1319
1320/*
1321 * R648 (0x288) - Headphone Detect 1
1322 */
1323#define WM5100_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */
1324#define WM5100_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */
1325#define WM5100_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */
1326#define WM5100_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */
1327#define WM5100_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */
1328#define WM5100_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */
1329#define WM5100_HP_STEP_SIZE 0x0002 /* HP_STEP_SIZE */
1330#define WM5100_HP_STEP_SIZE_MASK 0x0002 /* HP_STEP_SIZE */
1331#define WM5100_HP_STEP_SIZE_SHIFT 1 /* HP_STEP_SIZE */
1332#define WM5100_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */
1333#define WM5100_HP_POLL 0x0001 /* HP_POLL */
1334#define WM5100_HP_POLL_MASK 0x0001 /* HP_POLL */
1335#define WM5100_HP_POLL_SHIFT 0 /* HP_POLL */
1336#define WM5100_HP_POLL_WIDTH 1 /* HP_POLL */
1337
1338/*
1339 * R649 (0x289) - Headphone Detect 2
1340 */
1341#define WM5100_HP_DONE 0x0080 /* HP_DONE */
1342#define WM5100_HP_DONE_MASK 0x0080 /* HP_DONE */
1343#define WM5100_HP_DONE_SHIFT 7 /* HP_DONE */
1344#define WM5100_HP_DONE_WIDTH 1 /* HP_DONE */
1345#define WM5100_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */
1346#define WM5100_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */
1347#define WM5100_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */
1348
1349/*
1350 * R656 (0x290) - Mic Detect 1
1351 */
1352#define WM5100_ACCDET_BIAS_STARTTIME_MASK 0xF000 /* ACCDET_BIAS_STARTTIME - [15:12] */
1353#define WM5100_ACCDET_BIAS_STARTTIME_SHIFT 12 /* ACCDET_BIAS_STARTTIME - [15:12] */
1354#define WM5100_ACCDET_BIAS_STARTTIME_WIDTH 4 /* ACCDET_BIAS_STARTTIME - [15:12] */
1355#define WM5100_ACCDET_RATE_MASK 0x0F00 /* ACCDET_RATE - [11:8] */
1356#define WM5100_ACCDET_RATE_SHIFT 8 /* ACCDET_RATE - [11:8] */
1357#define WM5100_ACCDET_RATE_WIDTH 4 /* ACCDET_RATE - [11:8] */
1358#define WM5100_ACCDET_DBTIME 0x0002 /* ACCDET_DBTIME */
1359#define WM5100_ACCDET_DBTIME_MASK 0x0002 /* ACCDET_DBTIME */
1360#define WM5100_ACCDET_DBTIME_SHIFT 1 /* ACCDET_DBTIME */
1361#define WM5100_ACCDET_DBTIME_WIDTH 1 /* ACCDET_DBTIME */
1362#define WM5100_ACCDET_ENA 0x0001 /* ACCDET_ENA */
1363#define WM5100_ACCDET_ENA_MASK 0x0001 /* ACCDET_ENA */
1364#define WM5100_ACCDET_ENA_SHIFT 0 /* ACCDET_ENA */
1365#define WM5100_ACCDET_ENA_WIDTH 1 /* ACCDET_ENA */
1366
1367/*
1368 * R657 (0x291) - Mic Detect 2
1369 */
1370#define WM5100_ACCDET_LVL_SEL_MASK 0x00FF /* ACCDET_LVL_SEL - [7:0] */
1371#define WM5100_ACCDET_LVL_SEL_SHIFT 0 /* ACCDET_LVL_SEL - [7:0] */
1372#define WM5100_ACCDET_LVL_SEL_WIDTH 8 /* ACCDET_LVL_SEL - [7:0] */
1373
1374/*
1375 * R658 (0x292) - Mic Detect 3
1376 */
1377#define WM5100_ACCDET_LVL_MASK 0x07FC /* ACCDET_LVL - [10:2] */
1378#define WM5100_ACCDET_LVL_SHIFT 2 /* ACCDET_LVL - [10:2] */
1379#define WM5100_ACCDET_LVL_WIDTH 9 /* ACCDET_LVL - [10:2] */
1380#define WM5100_ACCDET_VALID 0x0002 /* ACCDET_VALID */
1381#define WM5100_ACCDET_VALID_MASK 0x0002 /* ACCDET_VALID */
1382#define WM5100_ACCDET_VALID_SHIFT 1 /* ACCDET_VALID */
1383#define WM5100_ACCDET_VALID_WIDTH 1 /* ACCDET_VALID */
1384#define WM5100_ACCDET_STS 0x0001 /* ACCDET_STS */
1385#define WM5100_ACCDET_STS_MASK 0x0001 /* ACCDET_STS */
1386#define WM5100_ACCDET_STS_SHIFT 0 /* ACCDET_STS */
1387#define WM5100_ACCDET_STS_WIDTH 1 /* ACCDET_STS */
1388
1389/*
1390 * R769 (0x301) - Input Enables
1391 */
1392#define WM5100_IN4L_ENA 0x0080 /* IN4L_ENA */
1393#define WM5100_IN4L_ENA_MASK 0x0080 /* IN4L_ENA */
1394#define WM5100_IN4L_ENA_SHIFT 7 /* IN4L_ENA */
1395#define WM5100_IN4L_ENA_WIDTH 1 /* IN4L_ENA */
1396#define WM5100_IN4R_ENA 0x0040 /* IN4R_ENA */
1397#define WM5100_IN4R_ENA_MASK 0x0040 /* IN4R_ENA */
1398#define WM5100_IN4R_ENA_SHIFT 6 /* IN4R_ENA */
1399#define WM5100_IN4R_ENA_WIDTH 1 /* IN4R_ENA */
1400#define WM5100_IN3L_ENA 0x0020 /* IN3L_ENA */
1401#define WM5100_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */
1402#define WM5100_IN3L_ENA_SHIFT 5 /* IN3L_ENA */
1403#define WM5100_IN3L_ENA_WIDTH 1 /* IN3L_ENA */
1404#define WM5100_IN3R_ENA 0x0010 /* IN3R_ENA */
1405#define WM5100_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */
1406#define WM5100_IN3R_ENA_SHIFT 4 /* IN3R_ENA */
1407#define WM5100_IN3R_ENA_WIDTH 1 /* IN3R_ENA */
1408#define WM5100_IN2L_ENA 0x0008 /* IN2L_ENA */
1409#define WM5100_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */
1410#define WM5100_IN2L_ENA_SHIFT 3 /* IN2L_ENA */
1411#define WM5100_IN2L_ENA_WIDTH 1 /* IN2L_ENA */
1412#define WM5100_IN2R_ENA 0x0004 /* IN2R_ENA */
1413#define WM5100_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */
1414#define WM5100_IN2R_ENA_SHIFT 2 /* IN2R_ENA */
1415#define WM5100_IN2R_ENA_WIDTH 1 /* IN2R_ENA */
1416#define WM5100_IN1L_ENA 0x0002 /* IN1L_ENA */
1417#define WM5100_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */
1418#define WM5100_IN1L_ENA_SHIFT 1 /* IN1L_ENA */
1419#define WM5100_IN1L_ENA_WIDTH 1 /* IN1L_ENA */
1420#define WM5100_IN1R_ENA 0x0001 /* IN1R_ENA */
1421#define WM5100_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */
1422#define WM5100_IN1R_ENA_SHIFT 0 /* IN1R_ENA */
1423#define WM5100_IN1R_ENA_WIDTH 1 /* IN1R_ENA */
1424
1425/*
1426 * R770 (0x302) - Input Enables Status
1427 */
1428#define WM5100_IN4L_ENA_STS 0x0080 /* IN4L_ENA_STS */
1429#define WM5100_IN4L_ENA_STS_MASK 0x0080 /* IN4L_ENA_STS */
1430#define WM5100_IN4L_ENA_STS_SHIFT 7 /* IN4L_ENA_STS */
1431#define WM5100_IN4L_ENA_STS_WIDTH 1 /* IN4L_ENA_STS */
1432#define WM5100_IN4R_ENA_STS 0x0040 /* IN4R_ENA_STS */
1433#define WM5100_IN4R_ENA_STS_MASK 0x0040 /* IN4R_ENA_STS */
1434#define WM5100_IN4R_ENA_STS_SHIFT 6 /* IN4R_ENA_STS */
1435#define WM5100_IN4R_ENA_STS_WIDTH 1 /* IN4R_ENA_STS */
1436#define WM5100_IN3L_ENA_STS 0x0020 /* IN3L_ENA_STS */
1437#define WM5100_IN3L_ENA_STS_MASK 0x0020 /* IN3L_ENA_STS */
1438#define WM5100_IN3L_ENA_STS_SHIFT 5 /* IN3L_ENA_STS */
1439#define WM5100_IN3L_ENA_STS_WIDTH 1 /* IN3L_ENA_STS */
1440#define WM5100_IN3R_ENA_STS 0x0010 /* IN3R_ENA_STS */
1441#define WM5100_IN3R_ENA_STS_MASK 0x0010 /* IN3R_ENA_STS */
1442#define WM5100_IN3R_ENA_STS_SHIFT 4 /* IN3R_ENA_STS */
1443#define WM5100_IN3R_ENA_STS_WIDTH 1 /* IN3R_ENA_STS */
1444#define WM5100_IN2L_ENA_STS 0x0008 /* IN2L_ENA_STS */
1445#define WM5100_IN2L_ENA_STS_MASK 0x0008 /* IN2L_ENA_STS */
1446#define WM5100_IN2L_ENA_STS_SHIFT 3 /* IN2L_ENA_STS */
1447#define WM5100_IN2L_ENA_STS_WIDTH 1 /* IN2L_ENA_STS */
1448#define WM5100_IN2R_ENA_STS 0x0004 /* IN2R_ENA_STS */
1449#define WM5100_IN2R_ENA_STS_MASK 0x0004 /* IN2R_ENA_STS */
1450#define WM5100_IN2R_ENA_STS_SHIFT 2 /* IN2R_ENA_STS */
1451#define WM5100_IN2R_ENA_STS_WIDTH 1 /* IN2R_ENA_STS */
1452#define WM5100_IN1L_ENA_STS 0x0002 /* IN1L_ENA_STS */
1453#define WM5100_IN1L_ENA_STS_MASK 0x0002 /* IN1L_ENA_STS */
1454#define WM5100_IN1L_ENA_STS_SHIFT 1 /* IN1L_ENA_STS */
1455#define WM5100_IN1L_ENA_STS_WIDTH 1 /* IN1L_ENA_STS */
1456#define WM5100_IN1R_ENA_STS 0x0001 /* IN1R_ENA_STS */
1457#define WM5100_IN1R_ENA_STS_MASK 0x0001 /* IN1R_ENA_STS */
1458#define WM5100_IN1R_ENA_STS_SHIFT 0 /* IN1R_ENA_STS */
1459#define WM5100_IN1R_ENA_STS_WIDTH 1 /* IN1R_ENA_STS */
1460
1461/*
1462 * R784 (0x310) - IN1L Control
1463 */
1464#define WM5100_IN_RATE_MASK 0xC000 /* IN_RATE - [15:14] */
1465#define WM5100_IN_RATE_SHIFT 14 /* IN_RATE - [15:14] */
1466#define WM5100_IN_RATE_WIDTH 2 /* IN_RATE - [15:14] */
1467#define WM5100_IN1_OSR 0x2000 /* IN1_OSR */
1468#define WM5100_IN1_OSR_MASK 0x2000 /* IN1_OSR */
1469#define WM5100_IN1_OSR_SHIFT 13 /* IN1_OSR */
1470#define WM5100_IN1_OSR_WIDTH 1 /* IN1_OSR */
1471#define WM5100_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */
1472#define WM5100_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */
1473#define WM5100_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */
1474#define WM5100_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */
1475#define WM5100_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */
1476#define WM5100_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */
1477#define WM5100_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */
1478#define WM5100_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */
1479#define WM5100_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */
1480
1481/*
1482 * R785 (0x311) - IN1R Control
1483 */
1484#define WM5100_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */
1485#define WM5100_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */
1486#define WM5100_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */
1487
1488/*
1489 * R786 (0x312) - IN2L Control
1490 */
1491#define WM5100_IN2_OSR 0x2000 /* IN2_OSR */
1492#define WM5100_IN2_OSR_MASK 0x2000 /* IN2_OSR */
1493#define WM5100_IN2_OSR_SHIFT 13 /* IN2_OSR */
1494#define WM5100_IN2_OSR_WIDTH 1 /* IN2_OSR */
1495#define WM5100_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */
1496#define WM5100_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */
1497#define WM5100_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */
1498#define WM5100_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */
1499#define WM5100_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */
1500#define WM5100_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */
1501#define WM5100_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */
1502#define WM5100_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */
1503#define WM5100_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */
1504
1505/*
1506 * R787 (0x313) - IN2R Control
1507 */
1508#define WM5100_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */
1509#define WM5100_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */
1510#define WM5100_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */
1511
1512/*
1513 * R788 (0x314) - IN3L Control
1514 */
1515#define WM5100_IN3_OSR 0x2000 /* IN3_OSR */
1516#define WM5100_IN3_OSR_MASK 0x2000 /* IN3_OSR */
1517#define WM5100_IN3_OSR_SHIFT 13 /* IN3_OSR */
1518#define WM5100_IN3_OSR_WIDTH 1 /* IN3_OSR */
1519#define WM5100_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */
1520#define WM5100_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */
1521#define WM5100_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */
1522#define WM5100_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */
1523#define WM5100_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */
1524#define WM5100_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */
1525#define WM5100_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */
1526#define WM5100_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */
1527#define WM5100_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */
1528
1529/*
1530 * R789 (0x315) - IN3R Control
1531 */
1532#define WM5100_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */
1533#define WM5100_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */
1534#define WM5100_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */
1535
1536/*
1537 * R790 (0x316) - IN4L Control
1538 */
1539#define WM5100_IN4_OSR 0x2000 /* IN4_OSR */
1540#define WM5100_IN4_OSR_MASK 0x2000 /* IN4_OSR */
1541#define WM5100_IN4_OSR_SHIFT 13 /* IN4_OSR */
1542#define WM5100_IN4_OSR_WIDTH 1 /* IN4_OSR */
1543#define WM5100_IN4_DMIC_SUP_MASK 0x1800 /* IN4_DMIC_SUP - [12:11] */
1544#define WM5100_IN4_DMIC_SUP_SHIFT 11 /* IN4_DMIC_SUP - [12:11] */
1545#define WM5100_IN4_DMIC_SUP_WIDTH 2 /* IN4_DMIC_SUP - [12:11] */
1546#define WM5100_IN4_MODE_MASK 0x0600 /* IN4_MODE - [10:9] */
1547#define WM5100_IN4_MODE_SHIFT 9 /* IN4_MODE - [10:9] */
1548#define WM5100_IN4_MODE_WIDTH 2 /* IN4_MODE - [10:9] */
1549#define WM5100_IN4L_PGA_VOL_MASK 0x00FE /* IN4L_PGA_VOL - [7:1] */
1550#define WM5100_IN4L_PGA_VOL_SHIFT 1 /* IN4L_PGA_VOL - [7:1] */
1551#define WM5100_IN4L_PGA_VOL_WIDTH 7 /* IN4L_PGA_VOL - [7:1] */
1552
1553/*
1554 * R791 (0x317) - IN4R Control
1555 */
1556#define WM5100_IN4R_PGA_VOL_MASK 0x00FE /* IN4R_PGA_VOL - [7:1] */
1557#define WM5100_IN4R_PGA_VOL_SHIFT 1 /* IN4R_PGA_VOL - [7:1] */
1558#define WM5100_IN4R_PGA_VOL_WIDTH 7 /* IN4R_PGA_VOL - [7:1] */
1559
1560/*
1561 * R792 (0x318) - RXANC_SRC
1562 */
1563#define WM5100_IN_RXANC_SEL_MASK 0x0007 /* IN_RXANC_SEL - [2:0] */
1564#define WM5100_IN_RXANC_SEL_SHIFT 0 /* IN_RXANC_SEL - [2:0] */
1565#define WM5100_IN_RXANC_SEL_WIDTH 3 /* IN_RXANC_SEL - [2:0] */
1566
1567/*
1568 * R793 (0x319) - Input Volume Ramp
1569 */
1570#define WM5100_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */
1571#define WM5100_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */
1572#define WM5100_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */
1573#define WM5100_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */
1574#define WM5100_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */
1575#define WM5100_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */
1576
1577/*
1578 * R800 (0x320) - ADC Digital Volume 1L
1579 */
1580#define WM5100_IN_VU 0x0200 /* IN_VU */
1581#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */
1582#define WM5100_IN_VU_SHIFT 9 /* IN_VU */
1583#define WM5100_IN_VU_WIDTH 1 /* IN_VU */
1584#define WM5100_IN1L_MUTE 0x0100 /* IN1L_MUTE */
1585#define WM5100_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */
1586#define WM5100_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */
1587#define WM5100_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */
1588#define WM5100_IN1L_VOL_MASK 0x00FF /* IN1L_VOL - [7:0] */
1589#define WM5100_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [7:0] */
1590#define WM5100_IN1L_VOL_WIDTH 8 /* IN1L_VOL - [7:0] */
1591
1592/*
1593 * R801 (0x321) - ADC Digital Volume 1R
1594 */
1595#define WM5100_IN_VU 0x0200 /* IN_VU */
1596#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */
1597#define WM5100_IN_VU_SHIFT 9 /* IN_VU */
1598#define WM5100_IN_VU_WIDTH 1 /* IN_VU */
1599#define WM5100_IN1R_MUTE 0x0100 /* IN1R_MUTE */
1600#define WM5100_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */
1601#define WM5100_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */
1602#define WM5100_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */
1603#define WM5100_IN1R_VOL_MASK 0x00FF /* IN1R_VOL - [7:0] */
1604#define WM5100_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [7:0] */
1605#define WM5100_IN1R_VOL_WIDTH 8 /* IN1R_VOL - [7:0] */
1606
1607/*
1608 * R802 (0x322) - ADC Digital Volume 2L
1609 */
1610#define WM5100_IN_VU 0x0200 /* IN_VU */
1611#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */
1612#define WM5100_IN_VU_SHIFT 9 /* IN_VU */
1613#define WM5100_IN_VU_WIDTH 1 /* IN_VU */
1614#define WM5100_IN2L_MUTE 0x0100 /* IN2L_MUTE */
1615#define WM5100_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */
1616#define WM5100_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */
1617#define WM5100_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */
1618#define WM5100_IN2L_VOL_MASK 0x00FF /* IN2L_VOL - [7:0] */
1619#define WM5100_IN2L_VOL_SHIFT 0 /* IN2L_VOL - [7:0] */
1620#define WM5100_IN2L_VOL_WIDTH 8 /* IN2L_VOL - [7:0] */
1621
1622/*
1623 * R803 (0x323) - ADC Digital Volume 2R
1624 */
1625#define WM5100_IN_VU 0x0200 /* IN_VU */
1626#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */
1627#define WM5100_IN_VU_SHIFT 9 /* IN_VU */
1628#define WM5100_IN_VU_WIDTH 1 /* IN_VU */
1629#define WM5100_IN2R_MUTE 0x0100 /* IN2R_MUTE */
1630#define WM5100_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */
1631#define WM5100_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */
1632#define WM5100_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */
1633#define WM5100_IN2R_VOL_MASK 0x00FF /* IN2R_VOL - [7:0] */
1634#define WM5100_IN2R_VOL_SHIFT 0 /* IN2R_VOL - [7:0] */
1635#define WM5100_IN2R_VOL_WIDTH 8 /* IN2R_VOL - [7:0] */
1636
1637/*
1638 * R804 (0x324) - ADC Digital Volume 3L
1639 */
1640#define WM5100_IN_VU 0x0200 /* IN_VU */
1641#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */
1642#define WM5100_IN_VU_SHIFT 9 /* IN_VU */
1643#define WM5100_IN_VU_WIDTH 1 /* IN_VU */
1644#define WM5100_IN3L_MUTE 0x0100 /* IN3L_MUTE */
1645#define WM5100_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */
1646#define WM5100_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */
1647#define WM5100_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */
1648#define WM5100_IN3L_VOL_MASK 0x00FF /* IN3L_VOL - [7:0] */
1649#define WM5100_IN3L_VOL_SHIFT 0 /* IN3L_VOL - [7:0] */
1650#define WM5100_IN3L_VOL_WIDTH 8 /* IN3L_VOL - [7:0] */
1651
1652/*
1653 * R805 (0x325) - ADC Digital Volume 3R
1654 */
1655#define WM5100_IN_VU 0x0200 /* IN_VU */
1656#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */
1657#define WM5100_IN_VU_SHIFT 9 /* IN_VU */
1658#define WM5100_IN_VU_WIDTH 1 /* IN_VU */
1659#define WM5100_IN3R_MUTE 0x0100 /* IN3R_MUTE */
1660#define WM5100_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */
1661#define WM5100_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */
1662#define WM5100_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */
1663#define WM5100_IN3R_VOL_MASK 0x00FF /* IN3R_VOL - [7:0] */
1664#define WM5100_IN3R_VOL_SHIFT 0 /* IN3R_VOL - [7:0] */
1665#define WM5100_IN3R_VOL_WIDTH 8 /* IN3R_VOL - [7:0] */
1666
1667/*
1668 * R806 (0x326) - ADC Digital Volume 4L
1669 */
1670#define WM5100_IN_VU 0x0200 /* IN_VU */
1671#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */
1672#define WM5100_IN_VU_SHIFT 9 /* IN_VU */
1673#define WM5100_IN_VU_WIDTH 1 /* IN_VU */
1674#define WM5100_IN4L_MUTE 0x0100 /* IN4L_MUTE */
1675#define WM5100_IN4L_MUTE_MASK 0x0100 /* IN4L_MUTE */
1676#define WM5100_IN4L_MUTE_SHIFT 8 /* IN4L_MUTE */
1677#define WM5100_IN4L_MUTE_WIDTH 1 /* IN4L_MUTE */
1678#define WM5100_IN4L_VOL_MASK 0x00FF /* IN4L_VOL - [7:0] */
1679#define WM5100_IN4L_VOL_SHIFT 0 /* IN4L_VOL - [7:0] */
1680#define WM5100_IN4L_VOL_WIDTH 8 /* IN4L_VOL - [7:0] */
1681
1682/*
1683 * R807 (0x327) - ADC Digital Volume 4R
1684 */
1685#define WM5100_IN_VU 0x0200 /* IN_VU */
1686#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */
1687#define WM5100_IN_VU_SHIFT 9 /* IN_VU */
1688#define WM5100_IN_VU_WIDTH 1 /* IN_VU */
1689#define WM5100_IN4R_MUTE 0x0100 /* IN4R_MUTE */
1690#define WM5100_IN4R_MUTE_MASK 0x0100 /* IN4R_MUTE */
1691#define WM5100_IN4R_MUTE_SHIFT 8 /* IN4R_MUTE */
1692#define WM5100_IN4R_MUTE_WIDTH 1 /* IN4R_MUTE */
1693#define WM5100_IN4R_VOL_MASK 0x00FF /* IN4R_VOL - [7:0] */
1694#define WM5100_IN4R_VOL_SHIFT 0 /* IN4R_VOL - [7:0] */
1695#define WM5100_IN4R_VOL_WIDTH 8 /* IN4R_VOL - [7:0] */
1696
1697/*
1698 * R1025 (0x401) - Output Enables 2
1699 */
1700#define WM5100_OUT6L_ENA 0x0800 /* OUT6L_ENA */
1701#define WM5100_OUT6L_ENA_MASK 0x0800 /* OUT6L_ENA */
1702#define WM5100_OUT6L_ENA_SHIFT 11 /* OUT6L_ENA */
1703#define WM5100_OUT6L_ENA_WIDTH 1 /* OUT6L_ENA */
1704#define WM5100_OUT6R_ENA 0x0400 /* OUT6R_ENA */
1705#define WM5100_OUT6R_ENA_MASK 0x0400 /* OUT6R_ENA */
1706#define WM5100_OUT6R_ENA_SHIFT 10 /* OUT6R_ENA */
1707#define WM5100_OUT6R_ENA_WIDTH 1 /* OUT6R_ENA */
1708#define WM5100_OUT5L_ENA 0x0200 /* OUT5L_ENA */
1709#define WM5100_OUT5L_ENA_MASK 0x0200 /* OUT5L_ENA */
1710#define WM5100_OUT5L_ENA_SHIFT 9 /* OUT5L_ENA */
1711#define WM5100_OUT5L_ENA_WIDTH 1 /* OUT5L_ENA */
1712#define WM5100_OUT5R_ENA 0x0100 /* OUT5R_ENA */
1713#define WM5100_OUT5R_ENA_MASK 0x0100 /* OUT5R_ENA */
1714#define WM5100_OUT5R_ENA_SHIFT 8 /* OUT5R_ENA */
1715#define WM5100_OUT5R_ENA_WIDTH 1 /* OUT5R_ENA */
1716#define WM5100_OUT4L_ENA 0x0080 /* OUT4L_ENA */
1717#define WM5100_OUT4L_ENA_MASK 0x0080 /* OUT4L_ENA */
1718#define WM5100_OUT4L_ENA_SHIFT 7 /* OUT4L_ENA */
1719#define WM5100_OUT4L_ENA_WIDTH 1 /* OUT4L_ENA */
1720#define WM5100_OUT4R_ENA 0x0040 /* OUT4R_ENA */
1721#define WM5100_OUT4R_ENA_MASK 0x0040 /* OUT4R_ENA */
1722#define WM5100_OUT4R_ENA_SHIFT 6 /* OUT4R_ENA */
1723#define WM5100_OUT4R_ENA_WIDTH 1 /* OUT4R_ENA */
1724
1725/*
1726 * R1026 (0x402) - Output Status 1
1727 */
1728#define WM5100_OUT3L_ENA_STS 0x0020 /* OUT3L_ENA_STS */
1729#define WM5100_OUT3L_ENA_STS_MASK 0x0020 /* OUT3L_ENA_STS */
1730#define WM5100_OUT3L_ENA_STS_SHIFT 5 /* OUT3L_ENA_STS */
1731#define WM5100_OUT3L_ENA_STS_WIDTH 1 /* OUT3L_ENA_STS */
1732#define WM5100_OUT3R_ENA_STS 0x0010 /* OUT3R_ENA_STS */
1733#define WM5100_OUT3R_ENA_STS_MASK 0x0010 /* OUT3R_ENA_STS */
1734#define WM5100_OUT3R_ENA_STS_SHIFT 4 /* OUT3R_ENA_STS */
1735#define WM5100_OUT3R_ENA_STS_WIDTH 1 /* OUT3R_ENA_STS */
1736#define WM5100_OUT2L_ENA_STS 0x0008 /* OUT2L_ENA_STS */
1737#define WM5100_OUT2L_ENA_STS_MASK 0x0008 /* OUT2L_ENA_STS */
1738#define WM5100_OUT2L_ENA_STS_SHIFT 3 /* OUT2L_ENA_STS */
1739#define WM5100_OUT2L_ENA_STS_WIDTH 1 /* OUT2L_ENA_STS */
1740#define WM5100_OUT2R_ENA_STS 0x0004 /* OUT2R_ENA_STS */
1741#define WM5100_OUT2R_ENA_STS_MASK 0x0004 /* OUT2R_ENA_STS */
1742#define WM5100_OUT2R_ENA_STS_SHIFT 2 /* OUT2R_ENA_STS */
1743#define WM5100_OUT2R_ENA_STS_WIDTH 1 /* OUT2R_ENA_STS */
1744#define WM5100_OUT1L_ENA_STS 0x0002 /* OUT1L_ENA_STS */
1745#define WM5100_OUT1L_ENA_STS_MASK 0x0002 /* OUT1L_ENA_STS */
1746#define WM5100_OUT1L_ENA_STS_SHIFT 1 /* OUT1L_ENA_STS */
1747#define WM5100_OUT1L_ENA_STS_WIDTH 1 /* OUT1L_ENA_STS */
1748#define WM5100_OUT1R_ENA_STS 0x0001 /* OUT1R_ENA_STS */
1749#define WM5100_OUT1R_ENA_STS_MASK 0x0001 /* OUT1R_ENA_STS */
1750#define WM5100_OUT1R_ENA_STS_SHIFT 0 /* OUT1R_ENA_STS */
1751#define WM5100_OUT1R_ENA_STS_WIDTH 1 /* OUT1R_ENA_STS */
1752
1753/*
1754 * R1027 (0x403) - Output Status 2
1755 */
1756#define WM5100_OUT6L_ENA_STS 0x0800 /* OUT6L_ENA_STS */
1757#define WM5100_OUT6L_ENA_STS_MASK 0x0800 /* OUT6L_ENA_STS */
1758#define WM5100_OUT6L_ENA_STS_SHIFT 11 /* OUT6L_ENA_STS */
1759#define WM5100_OUT6L_ENA_STS_WIDTH 1 /* OUT6L_ENA_STS */
1760#define WM5100_OUT6R_ENA_STS 0x0400 /* OUT6R_ENA_STS */
1761#define WM5100_OUT6R_ENA_STS_MASK 0x0400 /* OUT6R_ENA_STS */
1762#define WM5100_OUT6R_ENA_STS_SHIFT 10 /* OUT6R_ENA_STS */
1763#define WM5100_OUT6R_ENA_STS_WIDTH 1 /* OUT6R_ENA_STS */
1764#define WM5100_OUT5L_ENA_STS 0x0200 /* OUT5L_ENA_STS */
1765#define WM5100_OUT5L_ENA_STS_MASK 0x0200 /* OUT5L_ENA_STS */
1766#define WM5100_OUT5L_ENA_STS_SHIFT 9 /* OUT5L_ENA_STS */
1767#define WM5100_OUT5L_ENA_STS_WIDTH 1 /* OUT5L_ENA_STS */
1768#define WM5100_OUT5R_ENA_STS 0x0100 /* OUT5R_ENA_STS */
1769#define WM5100_OUT5R_ENA_STS_MASK 0x0100 /* OUT5R_ENA_STS */
1770#define WM5100_OUT5R_ENA_STS_SHIFT 8 /* OUT5R_ENA_STS */
1771#define WM5100_OUT5R_ENA_STS_WIDTH 1 /* OUT5R_ENA_STS */
1772#define WM5100_OUT4L_ENA_STS 0x0080 /* OUT4L_ENA_STS */
1773#define WM5100_OUT4L_ENA_STS_MASK 0x0080 /* OUT4L_ENA_STS */
1774#define WM5100_OUT4L_ENA_STS_SHIFT 7 /* OUT4L_ENA_STS */
1775#define WM5100_OUT4L_ENA_STS_WIDTH 1 /* OUT4L_ENA_STS */
1776#define WM5100_OUT4R_ENA_STS 0x0040 /* OUT4R_ENA_STS */
1777#define WM5100_OUT4R_ENA_STS_MASK 0x0040 /* OUT4R_ENA_STS */
1778#define WM5100_OUT4R_ENA_STS_SHIFT 6 /* OUT4R_ENA_STS */
1779#define WM5100_OUT4R_ENA_STS_WIDTH 1 /* OUT4R_ENA_STS */
1780
1781/*
1782 * R1032 (0x408) - Channel Enables 1
1783 */
1784#define WM5100_HP3L_ENA 0x0020 /* HP3L_ENA */
1785#define WM5100_HP3L_ENA_MASK 0x0020 /* HP3L_ENA */
1786#define WM5100_HP3L_ENA_SHIFT 5 /* HP3L_ENA */
1787#define WM5100_HP3L_ENA_WIDTH 1 /* HP3L_ENA */
1788#define WM5100_HP3R_ENA 0x0010 /* HP3R_ENA */
1789#define WM5100_HP3R_ENA_MASK 0x0010 /* HP3R_ENA */
1790#define WM5100_HP3R_ENA_SHIFT 4 /* HP3R_ENA */
1791#define WM5100_HP3R_ENA_WIDTH 1 /* HP3R_ENA */
1792#define WM5100_HP2L_ENA 0x0008 /* HP2L_ENA */
1793#define WM5100_HP2L_ENA_MASK 0x0008 /* HP2L_ENA */
1794#define WM5100_HP2L_ENA_SHIFT 3 /* HP2L_ENA */
1795#define WM5100_HP2L_ENA_WIDTH 1 /* HP2L_ENA */
1796#define WM5100_HP2R_ENA 0x0004 /* HP2R_ENA */
1797#define WM5100_HP2R_ENA_MASK 0x0004 /* HP2R_ENA */
1798#define WM5100_HP2R_ENA_SHIFT 2 /* HP2R_ENA */
1799#define WM5100_HP2R_ENA_WIDTH 1 /* HP2R_ENA */
1800#define WM5100_HP1L_ENA 0x0002 /* HP1L_ENA */
1801#define WM5100_HP1L_ENA_MASK 0x0002 /* HP1L_ENA */
1802#define WM5100_HP1L_ENA_SHIFT 1 /* HP1L_ENA */
1803#define WM5100_HP1L_ENA_WIDTH 1 /* HP1L_ENA */
1804#define WM5100_HP1R_ENA 0x0001 /* HP1R_ENA */
1805#define WM5100_HP1R_ENA_MASK 0x0001 /* HP1R_ENA */
1806#define WM5100_HP1R_ENA_SHIFT 0 /* HP1R_ENA */
1807#define WM5100_HP1R_ENA_WIDTH 1 /* HP1R_ENA */
1808
1809/*
1810 * R1040 (0x410) - Out Volume 1L
1811 */
1812#define WM5100_OUT_RATE_MASK 0xC000 /* OUT_RATE - [15:14] */
1813#define WM5100_OUT_RATE_SHIFT 14 /* OUT_RATE - [15:14] */
1814#define WM5100_OUT_RATE_WIDTH 2 /* OUT_RATE - [15:14] */
1815#define WM5100_OUT1_OSR 0x2000 /* OUT1_OSR */
1816#define WM5100_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */
1817#define WM5100_OUT1_OSR_SHIFT 13 /* OUT1_OSR */
1818#define WM5100_OUT1_OSR_WIDTH 1 /* OUT1_OSR */
1819#define WM5100_OUT1_MONO 0x1000 /* OUT1_MONO */
1820#define WM5100_OUT1_MONO_MASK 0x1000 /* OUT1_MONO */
1821#define WM5100_OUT1_MONO_SHIFT 12 /* OUT1_MONO */
1822#define WM5100_OUT1_MONO_WIDTH 1 /* OUT1_MONO */
1823#define WM5100_OUT1L_ANC_SRC 0x0800 /* OUT1L_ANC_SRC */
1824#define WM5100_OUT1L_ANC_SRC_MASK 0x0800 /* OUT1L_ANC_SRC */
1825#define WM5100_OUT1L_ANC_SRC_SHIFT 11 /* OUT1L_ANC_SRC */
1826#define WM5100_OUT1L_ANC_SRC_WIDTH 1 /* OUT1L_ANC_SRC */
1827#define WM5100_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */
1828#define WM5100_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */
1829#define WM5100_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */
1830
1831/*
1832 * R1041 (0x411) - Out Volume 1R
1833 */
1834#define WM5100_OUT1R_ANC_SRC 0x0800 /* OUT1R_ANC_SRC */
1835#define WM5100_OUT1R_ANC_SRC_MASK 0x0800 /* OUT1R_ANC_SRC */
1836#define WM5100_OUT1R_ANC_SRC_SHIFT 11 /* OUT1R_ANC_SRC */
1837#define WM5100_OUT1R_ANC_SRC_WIDTH 1 /* OUT1R_ANC_SRC */
1838#define WM5100_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */
1839#define WM5100_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */
1840#define WM5100_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */
1841
1842/*
1843 * R1042 (0x412) - DAC Volume Limit 1L
1844 */
1845#define WM5100_OUT1L_VOL_LIM_MASK 0x00FF /* OUT1L_VOL_LIM - [7:0] */
1846#define WM5100_OUT1L_VOL_LIM_SHIFT 0 /* OUT1L_VOL_LIM - [7:0] */
1847#define WM5100_OUT1L_VOL_LIM_WIDTH 8 /* OUT1L_VOL_LIM - [7:0] */
1848
1849/*
1850 * R1043 (0x413) - DAC Volume Limit 1R
1851 */
1852#define WM5100_OUT1R_VOL_LIM_MASK 0x00FF /* OUT1R_VOL_LIM - [7:0] */
1853#define WM5100_OUT1R_VOL_LIM_SHIFT 0 /* OUT1R_VOL_LIM - [7:0] */
1854#define WM5100_OUT1R_VOL_LIM_WIDTH 8 /* OUT1R_VOL_LIM - [7:0] */
1855
1856/*
1857 * R1044 (0x414) - Out Volume 2L
1858 */
1859#define WM5100_OUT2_OSR 0x2000 /* OUT2_OSR */
1860#define WM5100_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */
1861#define WM5100_OUT2_OSR_SHIFT 13 /* OUT2_OSR */
1862#define WM5100_OUT2_OSR_WIDTH 1 /* OUT2_OSR */
1863#define WM5100_OUT2_MONO 0x1000 /* OUT2_MONO */
1864#define WM5100_OUT2_MONO_MASK 0x1000 /* OUT2_MONO */
1865#define WM5100_OUT2_MONO_SHIFT 12 /* OUT2_MONO */
1866#define WM5100_OUT2_MONO_WIDTH 1 /* OUT2_MONO */
1867#define WM5100_OUT2L_ANC_SRC 0x0800 /* OUT2L_ANC_SRC */
1868#define WM5100_OUT2L_ANC_SRC_MASK 0x0800 /* OUT2L_ANC_SRC */
1869#define WM5100_OUT2L_ANC_SRC_SHIFT 11 /* OUT2L_ANC_SRC */
1870#define WM5100_OUT2L_ANC_SRC_WIDTH 1 /* OUT2L_ANC_SRC */
1871#define WM5100_OUT2L_PGA_VOL_MASK 0x00FE /* OUT2L_PGA_VOL - [7:1] */
1872#define WM5100_OUT2L_PGA_VOL_SHIFT 1 /* OUT2L_PGA_VOL - [7:1] */
1873#define WM5100_OUT2L_PGA_VOL_WIDTH 7 /* OUT2L_PGA_VOL - [7:1] */
1874
1875/*
1876 * R1045 (0x415) - Out Volume 2R
1877 */
1878#define WM5100_OUT2R_ANC_SRC 0x0800 /* OUT2R_ANC_SRC */
1879#define WM5100_OUT2R_ANC_SRC_MASK 0x0800 /* OUT2R_ANC_SRC */
1880#define WM5100_OUT2R_ANC_SRC_SHIFT 11 /* OUT2R_ANC_SRC */
1881#define WM5100_OUT2R_ANC_SRC_WIDTH 1 /* OUT2R_ANC_SRC */
1882#define WM5100_OUT2R_PGA_VOL_MASK 0x00FE /* OUT2R_PGA_VOL - [7:1] */
1883#define WM5100_OUT2R_PGA_VOL_SHIFT 1 /* OUT2R_PGA_VOL - [7:1] */
1884#define WM5100_OUT2R_PGA_VOL_WIDTH 7 /* OUT2R_PGA_VOL - [7:1] */
1885
1886/*
1887 * R1046 (0x416) - DAC Volume Limit 2L
1888 */
1889#define WM5100_OUT2L_VOL_LIM_MASK 0x00FF /* OUT2L_VOL_LIM - [7:0] */
1890#define WM5100_OUT2L_VOL_LIM_SHIFT 0 /* OUT2L_VOL_LIM - [7:0] */
1891#define WM5100_OUT2L_VOL_LIM_WIDTH 8 /* OUT2L_VOL_LIM - [7:0] */
1892
1893/*
1894 * R1047 (0x417) - DAC Volume Limit 2R
1895 */
1896#define WM5100_OUT2R_VOL_LIM_MASK 0x00FF /* OUT2R_VOL_LIM - [7:0] */
1897#define WM5100_OUT2R_VOL_LIM_SHIFT 0 /* OUT2R_VOL_LIM - [7:0] */
1898#define WM5100_OUT2R_VOL_LIM_WIDTH 8 /* OUT2R_VOL_LIM - [7:0] */
1899
1900/*
1901 * R1048 (0x418) - Out Volume 3L
1902 */
1903#define WM5100_OUT3_OSR 0x2000 /* OUT3_OSR */
1904#define WM5100_OUT3_OSR_MASK 0x2000 /* OUT3_OSR */
1905#define WM5100_OUT3_OSR_SHIFT 13 /* OUT3_OSR */
1906#define WM5100_OUT3_OSR_WIDTH 1 /* OUT3_OSR */
1907#define WM5100_OUT3_MONO 0x1000 /* OUT3_MONO */
1908#define WM5100_OUT3_MONO_MASK 0x1000 /* OUT3_MONO */
1909#define WM5100_OUT3_MONO_SHIFT 12 /* OUT3_MONO */
1910#define WM5100_OUT3_MONO_WIDTH 1 /* OUT3_MONO */
1911#define WM5100_OUT3L_ANC_SRC 0x0800 /* OUT3L_ANC_SRC */
1912#define WM5100_OUT3L_ANC_SRC_MASK 0x0800 /* OUT3L_ANC_SRC */
1913#define WM5100_OUT3L_ANC_SRC_SHIFT 11 /* OUT3L_ANC_SRC */
1914#define WM5100_OUT3L_ANC_SRC_WIDTH 1 /* OUT3L_ANC_SRC */
1915#define WM5100_OUT3L_PGA_VOL_MASK 0x00FE /* OUT3L_PGA_VOL - [7:1] */
1916#define WM5100_OUT3L_PGA_VOL_SHIFT 1 /* OUT3L_PGA_VOL - [7:1] */
1917#define WM5100_OUT3L_PGA_VOL_WIDTH 7 /* OUT3L_PGA_VOL - [7:1] */
1918
1919/*
1920 * R1049 (0x419) - Out Volume 3R
1921 */
1922#define WM5100_OUT3R_ANC_SRC 0x0800 /* OUT3R_ANC_SRC */
1923#define WM5100_OUT3R_ANC_SRC_MASK 0x0800 /* OUT3R_ANC_SRC */
1924#define WM5100_OUT3R_ANC_SRC_SHIFT 11 /* OUT3R_ANC_SRC */
1925#define WM5100_OUT3R_ANC_SRC_WIDTH 1 /* OUT3R_ANC_SRC */
1926#define WM5100_OUT3R_PGA_VOL_MASK 0x00FE /* OUT3R_PGA_VOL - [7:1] */
1927#define WM5100_OUT3R_PGA_VOL_SHIFT 1 /* OUT3R_PGA_VOL - [7:1] */
1928#define WM5100_OUT3R_PGA_VOL_WIDTH 7 /* OUT3R_PGA_VOL - [7:1] */
1929
1930/*
1931 * R1050 (0x41A) - DAC Volume Limit 3L
1932 */
1933#define WM5100_OUT3L_VOL_LIM_MASK 0x00FF /* OUT3L_VOL_LIM - [7:0] */
1934#define WM5100_OUT3L_VOL_LIM_SHIFT 0 /* OUT3L_VOL_LIM - [7:0] */
1935#define WM5100_OUT3L_VOL_LIM_WIDTH 8 /* OUT3L_VOL_LIM - [7:0] */
1936
1937/*
1938 * R1051 (0x41B) - DAC Volume Limit 3R
1939 */
1940#define WM5100_OUT3R_VOL_LIM_MASK 0x00FF /* OUT3R_VOL_LIM - [7:0] */
1941#define WM5100_OUT3R_VOL_LIM_SHIFT 0 /* OUT3R_VOL_LIM - [7:0] */
1942#define WM5100_OUT3R_VOL_LIM_WIDTH 8 /* OUT3R_VOL_LIM - [7:0] */
1943
1944/*
1945 * R1052 (0x41C) - Out Volume 4L
1946 */
1947#define WM5100_OUT4_OSR 0x2000 /* OUT4_OSR */
1948#define WM5100_OUT4_OSR_MASK 0x2000 /* OUT4_OSR */
1949#define WM5100_OUT4_OSR_SHIFT 13 /* OUT4_OSR */
1950#define WM5100_OUT4_OSR_WIDTH 1 /* OUT4_OSR */
1951#define WM5100_OUT4L_ANC_SRC 0x0800 /* OUT4L_ANC_SRC */
1952#define WM5100_OUT4L_ANC_SRC_MASK 0x0800 /* OUT4L_ANC_SRC */
1953#define WM5100_OUT4L_ANC_SRC_SHIFT 11 /* OUT4L_ANC_SRC */
1954#define WM5100_OUT4L_ANC_SRC_WIDTH 1 /* OUT4L_ANC_SRC */
1955#define WM5100_OUT4L_VOL_LIM_MASK 0x00FF /* OUT4L_VOL_LIM - [7:0] */
1956#define WM5100_OUT4L_VOL_LIM_SHIFT 0 /* OUT4L_VOL_LIM - [7:0] */
1957#define WM5100_OUT4L_VOL_LIM_WIDTH 8 /* OUT4L_VOL_LIM - [7:0] */
1958
1959/*
1960 * R1053 (0x41D) - Out Volume 4R
1961 */
1962#define WM5100_OUT4R_ANC_SRC 0x0800 /* OUT4R_ANC_SRC */
1963#define WM5100_OUT4R_ANC_SRC_MASK 0x0800 /* OUT4R_ANC_SRC */
1964#define WM5100_OUT4R_ANC_SRC_SHIFT 11 /* OUT4R_ANC_SRC */
1965#define WM5100_OUT4R_ANC_SRC_WIDTH 1 /* OUT4R_ANC_SRC */
1966#define WM5100_OUT4R_VOL_LIM_MASK 0x00FF /* OUT4R_VOL_LIM - [7:0] */
1967#define WM5100_OUT4R_VOL_LIM_SHIFT 0 /* OUT4R_VOL_LIM - [7:0] */
1968#define WM5100_OUT4R_VOL_LIM_WIDTH 8 /* OUT4R_VOL_LIM - [7:0] */
1969
1970/*
1971 * R1054 (0x41E) - DAC Volume Limit 5L
1972 */
1973#define WM5100_OUT5_OSR 0x2000 /* OUT5_OSR */
1974#define WM5100_OUT5_OSR_MASK 0x2000 /* OUT5_OSR */
1975#define WM5100_OUT5_OSR_SHIFT 13 /* OUT5_OSR */
1976#define WM5100_OUT5_OSR_WIDTH 1 /* OUT5_OSR */
1977#define WM5100_OUT5L_ANC_SRC 0x0800 /* OUT5L_ANC_SRC */
1978#define WM5100_OUT5L_ANC_SRC_MASK 0x0800 /* OUT5L_ANC_SRC */
1979#define WM5100_OUT5L_ANC_SRC_SHIFT 11 /* OUT5L_ANC_SRC */
1980#define WM5100_OUT5L_ANC_SRC_WIDTH 1 /* OUT5L_ANC_SRC */
1981#define WM5100_OUT5L_VOL_LIM_MASK 0x00FF /* OUT5L_VOL_LIM - [7:0] */
1982#define WM5100_OUT5L_VOL_LIM_SHIFT 0 /* OUT5L_VOL_LIM - [7:0] */
1983#define WM5100_OUT5L_VOL_LIM_WIDTH 8 /* OUT5L_VOL_LIM - [7:0] */
1984
1985/*
1986 * R1055 (0x41F) - DAC Volume Limit 5R
1987 */
1988#define WM5100_OUT5R_ANC_SRC 0x0800 /* OUT5R_ANC_SRC */
1989#define WM5100_OUT5R_ANC_SRC_MASK 0x0800 /* OUT5R_ANC_SRC */
1990#define WM5100_OUT5R_ANC_SRC_SHIFT 11 /* OUT5R_ANC_SRC */
1991#define WM5100_OUT5R_ANC_SRC_WIDTH 1 /* OUT5R_ANC_SRC */
1992#define WM5100_OUT5R_VOL_LIM_MASK 0x00FF /* OUT5R_VOL_LIM - [7:0] */
1993#define WM5100_OUT5R_VOL_LIM_SHIFT 0 /* OUT5R_VOL_LIM - [7:0] */
1994#define WM5100_OUT5R_VOL_LIM_WIDTH 8 /* OUT5R_VOL_LIM - [7:0] */
1995
1996/*
1997 * R1056 (0x420) - DAC Volume Limit 6L
1998 */
1999#define WM5100_OUT6_OSR 0x2000 /* OUT6_OSR */
2000#define WM5100_OUT6_OSR_MASK 0x2000 /* OUT6_OSR */
2001#define WM5100_OUT6_OSR_SHIFT 13 /* OUT6_OSR */
2002#define WM5100_OUT6_OSR_WIDTH 1 /* OUT6_OSR */
2003#define WM5100_OUT6L_ANC_SRC 0x0800 /* OUT6L_ANC_SRC */
2004#define WM5100_OUT6L_ANC_SRC_MASK 0x0800 /* OUT6L_ANC_SRC */
2005#define WM5100_OUT6L_ANC_SRC_SHIFT 11 /* OUT6L_ANC_SRC */
2006#define WM5100_OUT6L_ANC_SRC_WIDTH 1 /* OUT6L_ANC_SRC */
2007#define WM5100_OUT6L_VOL_LIM_MASK 0x00FF /* OUT6L_VOL_LIM - [7:0] */
2008#define WM5100_OUT6L_VOL_LIM_SHIFT 0 /* OUT6L_VOL_LIM - [7:0] */
2009#define WM5100_OUT6L_VOL_LIM_WIDTH 8 /* OUT6L_VOL_LIM - [7:0] */
2010
2011/*
2012 * R1057 (0x421) - DAC Volume Limit 6R
2013 */
2014#define WM5100_OUT6R_ANC_SRC 0x0800 /* OUT6R_ANC_SRC */
2015#define WM5100_OUT6R_ANC_SRC_MASK 0x0800 /* OUT6R_ANC_SRC */
2016#define WM5100_OUT6R_ANC_SRC_SHIFT 11 /* OUT6R_ANC_SRC */
2017#define WM5100_OUT6R_ANC_SRC_WIDTH 1 /* OUT6R_ANC_SRC */
2018#define WM5100_OUT6R_VOL_LIM_MASK 0x00FF /* OUT6R_VOL_LIM - [7:0] */
2019#define WM5100_OUT6R_VOL_LIM_SHIFT 0 /* OUT6R_VOL_LIM - [7:0] */
2020#define WM5100_OUT6R_VOL_LIM_WIDTH 8 /* OUT6R_VOL_LIM - [7:0] */
2021
2022/*
2023 * R1088 (0x440) - DAC AEC Control 1
2024 */
2025#define WM5100_AEC_LOOPBACK_SRC_MASK 0x003C /* AEC_LOOPBACK_SRC - [5:2] */
2026#define WM5100_AEC_LOOPBACK_SRC_SHIFT 2 /* AEC_LOOPBACK_SRC - [5:2] */
2027#define WM5100_AEC_LOOPBACK_SRC_WIDTH 4 /* AEC_LOOPBACK_SRC - [5:2] */
2028#define WM5100_AEC_ENA_STS 0x0002 /* AEC_ENA_STS */
2029#define WM5100_AEC_ENA_STS_MASK 0x0002 /* AEC_ENA_STS */
2030#define WM5100_AEC_ENA_STS_SHIFT 1 /* AEC_ENA_STS */
2031#define WM5100_AEC_ENA_STS_WIDTH 1 /* AEC_ENA_STS */
2032#define WM5100_AEC_LOOPBACK_ENA 0x0001 /* AEC_LOOPBACK_ENA */
2033#define WM5100_AEC_LOOPBACK_ENA_MASK 0x0001 /* AEC_LOOPBACK_ENA */
2034#define WM5100_AEC_LOOPBACK_ENA_SHIFT 0 /* AEC_LOOPBACK_ENA */
2035#define WM5100_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */
2036
2037/*
2038 * R1089 (0x441) - Output Volume Ramp
2039 */
2040#define WM5100_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */
2041#define WM5100_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */
2042#define WM5100_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */
2043#define WM5100_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */
2044#define WM5100_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */
2045#define WM5100_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */
2046
2047/*
2048 * R1152 (0x480) - DAC Digital Volume 1L
2049 */
2050#define WM5100_OUT_VU 0x0200 /* OUT_VU */
2051#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
2052#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
2053#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
2054#define WM5100_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */
2055#define WM5100_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */
2056#define WM5100_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */
2057#define WM5100_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */
2058#define WM5100_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */
2059#define WM5100_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */
2060#define WM5100_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */
2061
2062/*
2063 * R1153 (0x481) - DAC Digital Volume 1R
2064 */
2065#define WM5100_OUT_VU 0x0200 /* OUT_VU */
2066#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
2067#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
2068#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
2069#define WM5100_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */
2070#define WM5100_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */
2071#define WM5100_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */
2072#define WM5100_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */
2073#define WM5100_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */
2074#define WM5100_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */
2075#define WM5100_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */
2076
2077/*
2078 * R1154 (0x482) - DAC Digital Volume 2L
2079 */
2080#define WM5100_OUT_VU 0x0200 /* OUT_VU */
2081#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
2082#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
2083#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
2084#define WM5100_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */
2085#define WM5100_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */
2086#define WM5100_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */
2087#define WM5100_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */
2088#define WM5100_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */
2089#define WM5100_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */
2090#define WM5100_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */
2091
2092/*
2093 * R1155 (0x483) - DAC Digital Volume 2R
2094 */
2095#define WM5100_OUT_VU 0x0200 /* OUT_VU */
2096#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
2097#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
2098#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
2099#define WM5100_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */
2100#define WM5100_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */
2101#define WM5100_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */
2102#define WM5100_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */
2103#define WM5100_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */
2104#define WM5100_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */
2105#define WM5100_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */
2106
2107/*
2108 * R1156 (0x484) - DAC Digital Volume 3L
2109 */
2110#define WM5100_OUT_VU 0x0200 /* OUT_VU */
2111#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
2112#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
2113#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
2114#define WM5100_OUT3L_MUTE 0x0100 /* OUT3L_MUTE */
2115#define WM5100_OUT3L_MUTE_MASK 0x0100 /* OUT3L_MUTE */
2116#define WM5100_OUT3L_MUTE_SHIFT 8 /* OUT3L_MUTE */
2117#define WM5100_OUT3L_MUTE_WIDTH 1 /* OUT3L_MUTE */
2118#define WM5100_OUT3L_VOL_MASK 0x00FF /* OUT3L_VOL - [7:0] */
2119#define WM5100_OUT3L_VOL_SHIFT 0 /* OUT3L_VOL - [7:0] */
2120#define WM5100_OUT3L_VOL_WIDTH 8 /* OUT3L_VOL - [7:0] */
2121
2122/*
2123 * R1157 (0x485) - DAC Digital Volume 3R
2124 */
2125#define WM5100_OUT_VU 0x0200 /* OUT_VU */
2126#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
2127#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
2128#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
2129#define WM5100_OUT3R_MUTE 0x0100 /* OUT3R_MUTE */
2130#define WM5100_OUT3R_MUTE_MASK 0x0100 /* OUT3R_MUTE */
2131#define WM5100_OUT3R_MUTE_SHIFT 8 /* OUT3R_MUTE */
2132#define WM5100_OUT3R_MUTE_WIDTH 1 /* OUT3R_MUTE */
2133#define WM5100_OUT3R_VOL_MASK 0x00FF /* OUT3R_VOL - [7:0] */
2134#define WM5100_OUT3R_VOL_SHIFT 0 /* OUT3R_VOL - [7:0] */
2135#define WM5100_OUT3R_VOL_WIDTH 8 /* OUT3R_VOL - [7:0] */
2136
2137/*
2138 * R1158 (0x486) - DAC Digital Volume 4L
2139 */
2140#define WM5100_OUT_VU 0x0200 /* OUT_VU */
2141#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
2142#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
2143#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
2144#define WM5100_OUT4L_MUTE 0x0100 /* OUT4L_MUTE */
2145#define WM5100_OUT4L_MUTE_MASK 0x0100 /* OUT4L_MUTE */
2146#define WM5100_OUT4L_MUTE_SHIFT 8 /* OUT4L_MUTE */
2147#define WM5100_OUT4L_MUTE_WIDTH 1 /* OUT4L_MUTE */
2148#define WM5100_OUT4L_VOL_MASK 0x00FF /* OUT4L_VOL - [7:0] */
2149#define WM5100_OUT4L_VOL_SHIFT 0 /* OUT4L_VOL - [7:0] */
2150#define WM5100_OUT4L_VOL_WIDTH 8 /* OUT4L_VOL - [7:0] */
2151
2152/*
2153 * R1159 (0x487) - DAC Digital Volume 4R
2154 */
2155#define WM5100_OUT_VU 0x0200 /* OUT_VU */
2156#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
2157#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
2158#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
2159#define WM5100_OUT4R_MUTE 0x0100 /* OUT4R_MUTE */
2160#define WM5100_OUT4R_MUTE_MASK 0x0100 /* OUT4R_MUTE */
2161#define WM5100_OUT4R_MUTE_SHIFT 8 /* OUT4R_MUTE */
2162#define WM5100_OUT4R_MUTE_WIDTH 1 /* OUT4R_MUTE */
2163#define WM5100_OUT4R_VOL_MASK 0x00FF /* OUT4R_VOL - [7:0] */
2164#define WM5100_OUT4R_VOL_SHIFT 0 /* OUT4R_VOL - [7:0] */
2165#define WM5100_OUT4R_VOL_WIDTH 8 /* OUT4R_VOL - [7:0] */
2166
2167/*
2168 * R1160 (0x488) - DAC Digital Volume 5L
2169 */
2170#define WM5100_OUT_VU 0x0200 /* OUT_VU */
2171#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
2172#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
2173#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
2174#define WM5100_OUT5L_MUTE 0x0100 /* OUT5L_MUTE */
2175#define WM5100_OUT5L_MUTE_MASK 0x0100 /* OUT5L_MUTE */
2176#define WM5100_OUT5L_MUTE_SHIFT 8 /* OUT5L_MUTE */
2177#define WM5100_OUT5L_MUTE_WIDTH 1 /* OUT5L_MUTE */
2178#define WM5100_OUT5L_VOL_MASK 0x00FF /* OUT5L_VOL - [7:0] */
2179#define WM5100_OUT5L_VOL_SHIFT 0 /* OUT5L_VOL - [7:0] */
2180#define WM5100_OUT5L_VOL_WIDTH 8 /* OUT5L_VOL - [7:0] */
2181
2182/*
2183 * R1161 (0x489) - DAC Digital Volume 5R
2184 */
2185#define WM5100_OUT_VU 0x0200 /* OUT_VU */
2186#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
2187#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
2188#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
2189#define WM5100_OUT5R_MUTE 0x0100 /* OUT5R_MUTE */
2190#define WM5100_OUT5R_MUTE_MASK 0x0100 /* OUT5R_MUTE */
2191#define WM5100_OUT5R_MUTE_SHIFT 8 /* OUT5R_MUTE */
2192#define WM5100_OUT5R_MUTE_WIDTH 1 /* OUT5R_MUTE */
2193#define WM5100_OUT5R_VOL_MASK 0x00FF /* OUT5R_VOL - [7:0] */
2194#define WM5100_OUT5R_VOL_SHIFT 0 /* OUT5R_VOL - [7:0] */
2195#define WM5100_OUT5R_VOL_WIDTH 8 /* OUT5R_VOL - [7:0] */
2196
2197/*
2198 * R1162 (0x48A) - DAC Digital Volume 6L
2199 */
2200#define WM5100_OUT_VU 0x0200 /* OUT_VU */
2201#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
2202#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
2203#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
2204#define WM5100_OUT6L_MUTE 0x0100 /* OUT6L_MUTE */
2205#define WM5100_OUT6L_MUTE_MASK 0x0100 /* OUT6L_MUTE */
2206#define WM5100_OUT6L_MUTE_SHIFT 8 /* OUT6L_MUTE */
2207#define WM5100_OUT6L_MUTE_WIDTH 1 /* OUT6L_MUTE */
2208#define WM5100_OUT6L_VOL_MASK 0x00FF /* OUT6L_VOL - [7:0] */
2209#define WM5100_OUT6L_VOL_SHIFT 0 /* OUT6L_VOL - [7:0] */
2210#define WM5100_OUT6L_VOL_WIDTH 8 /* OUT6L_VOL - [7:0] */
2211
2212/*
2213 * R1163 (0x48B) - DAC Digital Volume 6R
2214 */
2215#define WM5100_OUT_VU 0x0200 /* OUT_VU */
2216#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
2217#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
2218#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
2219#define WM5100_OUT6R_MUTE 0x0100 /* OUT6R_MUTE */
2220#define WM5100_OUT6R_MUTE_MASK 0x0100 /* OUT6R_MUTE */
2221#define WM5100_OUT6R_MUTE_SHIFT 8 /* OUT6R_MUTE */
2222#define WM5100_OUT6R_MUTE_WIDTH 1 /* OUT6R_MUTE */
2223#define WM5100_OUT6R_VOL_MASK 0x00FF /* OUT6R_VOL - [7:0] */
2224#define WM5100_OUT6R_VOL_SHIFT 0 /* OUT6R_VOL - [7:0] */
2225#define WM5100_OUT6R_VOL_WIDTH 8 /* OUT6R_VOL - [7:0] */
2226
2227/*
2228 * R1216 (0x4C0) - PDM SPK1 CTRL 1
2229 */
2230#define WM5100_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */
2231#define WM5100_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */
2232#define WM5100_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */
2233#define WM5100_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */
2234#define WM5100_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */
2235#define WM5100_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */
2236#define WM5100_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */
2237#define WM5100_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */
2238#define WM5100_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */
2239#define WM5100_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */
2240#define WM5100_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */
2241#define WM5100_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */
2242#define WM5100_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */
2243#define WM5100_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */
2244#define WM5100_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */
2245
2246/*
2247 * R1217 (0x4C1) - PDM SPK1 CTRL 2
2248 */
2249#define WM5100_SPK1_FMT 0x0001 /* SPK1_FMT */
2250#define WM5100_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */
2251#define WM5100_SPK1_FMT_SHIFT 0 /* SPK1_FMT */
2252#define WM5100_SPK1_FMT_WIDTH 1 /* SPK1_FMT */
2253
2254/*
2255 * R1218 (0x4C2) - PDM SPK2 CTRL 1
2256 */
2257#define WM5100_SPK2R_MUTE 0x2000 /* SPK2R_MUTE */
2258#define WM5100_SPK2R_MUTE_MASK 0x2000 /* SPK2R_MUTE */
2259#define WM5100_SPK2R_MUTE_SHIFT 13 /* SPK2R_MUTE */
2260#define WM5100_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */
2261#define WM5100_SPK2L_MUTE 0x1000 /* SPK2L_MUTE */
2262#define WM5100_SPK2L_MUTE_MASK 0x1000 /* SPK2L_MUTE */
2263#define WM5100_SPK2L_MUTE_SHIFT 12 /* SPK2L_MUTE */
2264#define WM5100_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */
2265#define WM5100_SPK2_MUTE_ENDIAN 0x0100 /* SPK2_MUTE_ENDIAN */
2266#define WM5100_SPK2_MUTE_ENDIAN_MASK 0x0100 /* SPK2_MUTE_ENDIAN */
2267#define WM5100_SPK2_MUTE_ENDIAN_SHIFT 8 /* SPK2_MUTE_ENDIAN */
2268#define WM5100_SPK2_MUTE_ENDIAN_WIDTH 1 /* SPK2_MUTE_ENDIAN */
2269#define WM5100_SPK2_MUTE_SEQ1_MASK 0x00FF /* SPK2_MUTE_SEQ1 - [7:0] */
2270#define WM5100_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */
2271#define WM5100_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */
2272
2273/*
2274 * R1219 (0x4C3) - PDM SPK2 CTRL 2
2275 */
2276#define WM5100_SPK2_FMT 0x0001 /* SPK2_FMT */
2277#define WM5100_SPK2_FMT_MASK 0x0001 /* SPK2_FMT */
2278#define WM5100_SPK2_FMT_SHIFT 0 /* SPK2_FMT */
2279#define WM5100_SPK2_FMT_WIDTH 1 /* SPK2_FMT */
2280
2281/*
2282 * R1280 (0x500) - Audio IF 1_1
2283 */
2284#define WM5100_AIF1_BCLK_INV 0x0080 /* AIF1_BCLK_INV */
2285#define WM5100_AIF1_BCLK_INV_MASK 0x0080 /* AIF1_BCLK_INV */
2286#define WM5100_AIF1_BCLK_INV_SHIFT 7 /* AIF1_BCLK_INV */
2287#define WM5100_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */
2288#define WM5100_AIF1_BCLK_FRC 0x0040 /* AIF1_BCLK_FRC */
2289#define WM5100_AIF1_BCLK_FRC_MASK 0x0040 /* AIF1_BCLK_FRC */
2290#define WM5100_AIF1_BCLK_FRC_SHIFT 6 /* AIF1_BCLK_FRC */
2291#define WM5100_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */
2292#define WM5100_AIF1_BCLK_MSTR 0x0020 /* AIF1_BCLK_MSTR */
2293#define WM5100_AIF1_BCLK_MSTR_MASK 0x0020 /* AIF1_BCLK_MSTR */
2294#define WM5100_AIF1_BCLK_MSTR_SHIFT 5 /* AIF1_BCLK_MSTR */
2295#define WM5100_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */
2296#define WM5100_AIF1_BCLK_FREQ_MASK 0x001F /* AIF1_BCLK_FREQ - [4:0] */
2297#define WM5100_AIF1_BCLK_FREQ_SHIFT 0 /* AIF1_BCLK_FREQ - [4:0] */
2298#define WM5100_AIF1_BCLK_FREQ_WIDTH 5 /* AIF1_BCLK_FREQ - [4:0] */
2299
2300/*
2301 * R1281 (0x501) - Audio IF 1_2
2302 */
2303#define WM5100_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */
2304#define WM5100_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */
2305#define WM5100_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */
2306#define WM5100_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */
2307#define WM5100_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */
2308#define WM5100_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */
2309#define WM5100_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */
2310#define WM5100_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */
2311#define WM5100_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */
2312#define WM5100_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */
2313#define WM5100_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */
2314#define WM5100_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */
2315#define WM5100_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */
2316#define WM5100_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */
2317#define WM5100_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */
2318#define WM5100_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */
2319#define WM5100_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */
2320#define WM5100_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */
2321#define WM5100_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */
2322#define WM5100_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */
2323
2324/*
2325 * R1282 (0x502) - Audio IF 1_3
2326 */
2327#define WM5100_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */
2328#define WM5100_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */
2329#define WM5100_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */
2330#define WM5100_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */
2331#define WM5100_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */
2332#define WM5100_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */
2333#define WM5100_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */
2334#define WM5100_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */
2335#define WM5100_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */
2336#define WM5100_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */
2337#define WM5100_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */
2338#define WM5100_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */
2339
2340/*
2341 * R1283 (0x503) - Audio IF 1_4
2342 */
2343#define WM5100_AIF1_TRI 0x0040 /* AIF1_TRI */
2344#define WM5100_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */
2345#define WM5100_AIF1_TRI_SHIFT 6 /* AIF1_TRI */
2346#define WM5100_AIF1_TRI_WIDTH 1 /* AIF1_TRI */
2347#define WM5100_AIF1_RATE_MASK 0x0003 /* AIF1_RATE - [1:0] */
2348#define WM5100_AIF1_RATE_SHIFT 0 /* AIF1_RATE - [1:0] */
2349#define WM5100_AIF1_RATE_WIDTH 2 /* AIF1_RATE - [1:0] */
2350
2351/*
2352 * R1284 (0x504) - Audio IF 1_5
2353 */
2354#define WM5100_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */
2355#define WM5100_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */
2356#define WM5100_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */
2357
2358/*
2359 * R1285 (0x505) - Audio IF 1_6
2360 */
2361#define WM5100_AIF1TX_BCPF_MASK 0x1FFF /* AIF1TX_BCPF - [12:0] */
2362#define WM5100_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [12:0] */
2363#define WM5100_AIF1TX_BCPF_WIDTH 13 /* AIF1TX_BCPF - [12:0] */
2364
2365/*
2366 * R1286 (0x506) - Audio IF 1_7
2367 */
2368#define WM5100_AIF1RX_BCPF_MASK 0x1FFF /* AIF1RX_BCPF - [12:0] */
2369#define WM5100_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [12:0] */
2370#define WM5100_AIF1RX_BCPF_WIDTH 13 /* AIF1RX_BCPF - [12:0] */
2371
2372/*
2373 * R1287 (0x507) - Audio IF 1_8
2374 */
2375#define WM5100_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */
2376#define WM5100_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */
2377#define WM5100_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */
2378#define WM5100_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */
2379#define WM5100_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */
2380#define WM5100_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */
2381
2382/*
2383 * R1288 (0x508) - Audio IF 1_9
2384 */
2385#define WM5100_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */
2386#define WM5100_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */
2387#define WM5100_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */
2388#define WM5100_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */
2389#define WM5100_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */
2390#define WM5100_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */
2391
2392/*
2393 * R1289 (0x509) - Audio IF 1_10
2394 */
2395#define WM5100_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */
2396#define WM5100_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */
2397#define WM5100_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */
2398
2399/*
2400 * R1290 (0x50A) - Audio IF 1_11
2401 */
2402#define WM5100_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */
2403#define WM5100_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */
2404#define WM5100_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */
2405
2406/*
2407 * R1291 (0x50B) - Audio IF 1_12
2408 */
2409#define WM5100_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */
2410#define WM5100_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */
2411#define WM5100_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */
2412
2413/*
2414 * R1292 (0x50C) - Audio IF 1_13
2415 */
2416#define WM5100_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */
2417#define WM5100_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */
2418#define WM5100_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */
2419
2420/*
2421 * R1293 (0x50D) - Audio IF 1_14
2422 */
2423#define WM5100_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */
2424#define WM5100_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */
2425#define WM5100_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */
2426
2427/*
2428 * R1294 (0x50E) - Audio IF 1_15
2429 */
2430#define WM5100_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */
2431#define WM5100_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */
2432#define WM5100_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */
2433
2434/*
2435 * R1295 (0x50F) - Audio IF 1_16
2436 */
2437#define WM5100_AIF1TX7_SLOT_MASK 0x003F /* AIF1TX7_SLOT - [5:0] */
2438#define WM5100_AIF1TX7_SLOT_SHIFT 0 /* AIF1TX7_SLOT - [5:0] */
2439#define WM5100_AIF1TX7_SLOT_WIDTH 6 /* AIF1TX7_SLOT - [5:0] */
2440
2441/*
2442 * R1296 (0x510) - Audio IF 1_17
2443 */
2444#define WM5100_AIF1TX8_SLOT_MASK 0x003F /* AIF1TX8_SLOT - [5:0] */
2445#define WM5100_AIF1TX8_SLOT_SHIFT 0 /* AIF1TX8_SLOT - [5:0] */
2446#define WM5100_AIF1TX8_SLOT_WIDTH 6 /* AIF1TX8_SLOT - [5:0] */
2447
2448/*
2449 * R1297 (0x511) - Audio IF 1_18
2450 */
2451#define WM5100_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */
2452#define WM5100_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */
2453#define WM5100_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */
2454
2455/*
2456 * R1298 (0x512) - Audio IF 1_19
2457 */
2458#define WM5100_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */
2459#define WM5100_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */
2460#define WM5100_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */
2461
2462/*
2463 * R1299 (0x513) - Audio IF 1_20
2464 */
2465#define WM5100_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */
2466#define WM5100_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */
2467#define WM5100_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */
2468
2469/*
2470 * R1300 (0x514) - Audio IF 1_21
2471 */
2472#define WM5100_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */
2473#define WM5100_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */
2474#define WM5100_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */
2475
2476/*
2477 * R1301 (0x515) - Audio IF 1_22
2478 */
2479#define WM5100_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */
2480#define WM5100_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */
2481#define WM5100_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */
2482
2483/*
2484 * R1302 (0x516) - Audio IF 1_23
2485 */
2486#define WM5100_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */
2487#define WM5100_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */
2488#define WM5100_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */
2489
2490/*
2491 * R1303 (0x517) - Audio IF 1_24
2492 */
2493#define WM5100_AIF1RX7_SLOT_MASK 0x003F /* AIF1RX7_SLOT - [5:0] */
2494#define WM5100_AIF1RX7_SLOT_SHIFT 0 /* AIF1RX7_SLOT - [5:0] */
2495#define WM5100_AIF1RX7_SLOT_WIDTH 6 /* AIF1RX7_SLOT - [5:0] */
2496
2497/*
2498 * R1304 (0x518) - Audio IF 1_25
2499 */
2500#define WM5100_AIF1RX8_SLOT_MASK 0x003F /* AIF1RX8_SLOT - [5:0] */
2501#define WM5100_AIF1RX8_SLOT_SHIFT 0 /* AIF1RX8_SLOT - [5:0] */
2502#define WM5100_AIF1RX8_SLOT_WIDTH 6 /* AIF1RX8_SLOT - [5:0] */
2503
2504/*
2505 * R1305 (0x519) - Audio IF 1_26
2506 */
2507#define WM5100_AIF1TX8_ENA 0x0080 /* AIF1TX8_ENA */
2508#define WM5100_AIF1TX8_ENA_MASK 0x0080 /* AIF1TX8_ENA */
2509#define WM5100_AIF1TX8_ENA_SHIFT 7 /* AIF1TX8_ENA */
2510#define WM5100_AIF1TX8_ENA_WIDTH 1 /* AIF1TX8_ENA */
2511#define WM5100_AIF1TX7_ENA 0x0040 /* AIF1TX7_ENA */
2512#define WM5100_AIF1TX7_ENA_MASK 0x0040 /* AIF1TX7_ENA */
2513#define WM5100_AIF1TX7_ENA_SHIFT 6 /* AIF1TX7_ENA */
2514#define WM5100_AIF1TX7_ENA_WIDTH 1 /* AIF1TX7_ENA */
2515#define WM5100_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */
2516#define WM5100_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */
2517#define WM5100_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */
2518#define WM5100_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */
2519#define WM5100_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */
2520#define WM5100_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */
2521#define WM5100_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */
2522#define WM5100_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */
2523#define WM5100_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */
2524#define WM5100_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */
2525#define WM5100_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */
2526#define WM5100_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */
2527#define WM5100_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */
2528#define WM5100_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */
2529#define WM5100_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */
2530#define WM5100_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */
2531#define WM5100_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */
2532#define WM5100_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */
2533#define WM5100_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */
2534#define WM5100_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */
2535#define WM5100_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */
2536#define WM5100_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */
2537#define WM5100_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */
2538#define WM5100_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */
2539
2540/*
2541 * R1306 (0x51A) - Audio IF 1_27
2542 */
2543#define WM5100_AIF1RX8_ENA 0x0080 /* AIF1RX8_ENA */
2544#define WM5100_AIF1RX8_ENA_MASK 0x0080 /* AIF1RX8_ENA */
2545#define WM5100_AIF1RX8_ENA_SHIFT 7 /* AIF1RX8_ENA */
2546#define WM5100_AIF1RX8_ENA_WIDTH 1 /* AIF1RX8_ENA */
2547#define WM5100_AIF1RX7_ENA 0x0040 /* AIF1RX7_ENA */
2548#define WM5100_AIF1RX7_ENA_MASK 0x0040 /* AIF1RX7_ENA */
2549#define WM5100_AIF1RX7_ENA_SHIFT 6 /* AIF1RX7_ENA */
2550#define WM5100_AIF1RX7_ENA_WIDTH 1 /* AIF1RX7_ENA */
2551#define WM5100_AIF1RX6_ENA 0x0020 /* AIF1RX6_ENA */
2552#define WM5100_AIF1RX6_ENA_MASK 0x0020 /* AIF1RX6_ENA */
2553#define WM5100_AIF1RX6_ENA_SHIFT 5 /* AIF1RX6_ENA */
2554#define WM5100_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */
2555#define WM5100_AIF1RX5_ENA 0x0010 /* AIF1RX5_ENA */
2556#define WM5100_AIF1RX5_ENA_MASK 0x0010 /* AIF1RX5_ENA */
2557#define WM5100_AIF1RX5_ENA_SHIFT 4 /* AIF1RX5_ENA */
2558#define WM5100_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */
2559#define WM5100_AIF1RX4_ENA 0x0008 /* AIF1RX4_ENA */
2560#define WM5100_AIF1RX4_ENA_MASK 0x0008 /* AIF1RX4_ENA */
2561#define WM5100_AIF1RX4_ENA_SHIFT 3 /* AIF1RX4_ENA */
2562#define WM5100_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */
2563#define WM5100_AIF1RX3_ENA 0x0004 /* AIF1RX3_ENA */
2564#define WM5100_AIF1RX3_ENA_MASK 0x0004 /* AIF1RX3_ENA */
2565#define WM5100_AIF1RX3_ENA_SHIFT 2 /* AIF1RX3_ENA */
2566#define WM5100_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */
2567#define WM5100_AIF1RX2_ENA 0x0002 /* AIF1RX2_ENA */
2568#define WM5100_AIF1RX2_ENA_MASK 0x0002 /* AIF1RX2_ENA */
2569#define WM5100_AIF1RX2_ENA_SHIFT 1 /* AIF1RX2_ENA */
2570#define WM5100_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */
2571#define WM5100_AIF1RX1_ENA 0x0001 /* AIF1RX1_ENA */
2572#define WM5100_AIF1RX1_ENA_MASK 0x0001 /* AIF1RX1_ENA */
2573#define WM5100_AIF1RX1_ENA_SHIFT 0 /* AIF1RX1_ENA */
2574#define WM5100_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */
2575
2576/*
2577 * R1344 (0x540) - Audio IF 2_1
2578 */
2579#define WM5100_AIF2_BCLK_INV 0x0080 /* AIF2_BCLK_INV */
2580#define WM5100_AIF2_BCLK_INV_MASK 0x0080 /* AIF2_BCLK_INV */
2581#define WM5100_AIF2_BCLK_INV_SHIFT 7 /* AIF2_BCLK_INV */
2582#define WM5100_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */
2583#define WM5100_AIF2_BCLK_FRC 0x0040 /* AIF2_BCLK_FRC */
2584#define WM5100_AIF2_BCLK_FRC_MASK 0x0040 /* AIF2_BCLK_FRC */
2585#define WM5100_AIF2_BCLK_FRC_SHIFT 6 /* AIF2_BCLK_FRC */
2586#define WM5100_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */
2587#define WM5100_AIF2_BCLK_MSTR 0x0020 /* AIF2_BCLK_MSTR */
2588#define WM5100_AIF2_BCLK_MSTR_MASK 0x0020 /* AIF2_BCLK_MSTR */
2589#define WM5100_AIF2_BCLK_MSTR_SHIFT 5 /* AIF2_BCLK_MSTR */
2590#define WM5100_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */
2591#define WM5100_AIF2_BCLK_FREQ_MASK 0x001F /* AIF2_BCLK_FREQ - [4:0] */
2592#define WM5100_AIF2_BCLK_FREQ_SHIFT 0 /* AIF2_BCLK_FREQ - [4:0] */
2593#define WM5100_AIF2_BCLK_FREQ_WIDTH 5 /* AIF2_BCLK_FREQ - [4:0] */
2594
2595/*
2596 * R1345 (0x541) - Audio IF 2_2
2597 */
2598#define WM5100_AIF2TX_DAT_TRI 0x0020 /* AIF2TX_DAT_TRI */
2599#define WM5100_AIF2TX_DAT_TRI_MASK 0x0020 /* AIF2TX_DAT_TRI */
2600#define WM5100_AIF2TX_DAT_TRI_SHIFT 5 /* AIF2TX_DAT_TRI */
2601#define WM5100_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */
2602#define WM5100_AIF2TX_LRCLK_SRC 0x0008 /* AIF2TX_LRCLK_SRC */
2603#define WM5100_AIF2TX_LRCLK_SRC_MASK 0x0008 /* AIF2TX_LRCLK_SRC */
2604#define WM5100_AIF2TX_LRCLK_SRC_SHIFT 3 /* AIF2TX_LRCLK_SRC */
2605#define WM5100_AIF2TX_LRCLK_SRC_WIDTH 1 /* AIF2TX_LRCLK_SRC */
2606#define WM5100_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */
2607#define WM5100_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */
2608#define WM5100_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */
2609#define WM5100_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */
2610#define WM5100_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */
2611#define WM5100_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */
2612#define WM5100_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */
2613#define WM5100_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */
2614#define WM5100_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */
2615#define WM5100_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */
2616#define WM5100_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */
2617#define WM5100_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */
2618
2619/*
2620 * R1346 (0x542) - Audio IF 2_3
2621 */
2622#define WM5100_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */
2623#define WM5100_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */
2624#define WM5100_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */
2625#define WM5100_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */
2626#define WM5100_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */
2627#define WM5100_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */
2628#define WM5100_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */
2629#define WM5100_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */
2630#define WM5100_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */
2631#define WM5100_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */
2632#define WM5100_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */
2633#define WM5100_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */
2634
2635/*
2636 * R1347 (0x543) - Audio IF 2_4
2637 */
2638#define WM5100_AIF2_TRI 0x0040 /* AIF2_TRI */
2639#define WM5100_AIF2_TRI_MASK 0x0040 /* AIF2_TRI */
2640#define WM5100_AIF2_TRI_SHIFT 6 /* AIF2_TRI */
2641#define WM5100_AIF2_TRI_WIDTH 1 /* AIF2_TRI */
2642#define WM5100_AIF2_RATE_MASK 0x0003 /* AIF2_RATE - [1:0] */
2643#define WM5100_AIF2_RATE_SHIFT 0 /* AIF2_RATE - [1:0] */
2644#define WM5100_AIF2_RATE_WIDTH 2 /* AIF2_RATE - [1:0] */
2645
2646/*
2647 * R1348 (0x544) - Audio IF 2_5
2648 */
2649#define WM5100_AIF2_FMT_MASK 0x0007 /* AIF2_FMT - [2:0] */
2650#define WM5100_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [2:0] */
2651#define WM5100_AIF2_FMT_WIDTH 3 /* AIF2_FMT - [2:0] */
2652
2653/*
2654 * R1349 (0x545) - Audio IF 2_6
2655 */
2656#define WM5100_AIF2TX_BCPF_MASK 0x1FFF /* AIF2TX_BCPF - [12:0] */
2657#define WM5100_AIF2TX_BCPF_SHIFT 0 /* AIF2TX_BCPF - [12:0] */
2658#define WM5100_AIF2TX_BCPF_WIDTH 13 /* AIF2TX_BCPF - [12:0] */
2659
2660/*
2661 * R1350 (0x546) - Audio IF 2_7
2662 */
2663#define WM5100_AIF2RX_BCPF_MASK 0x1FFF /* AIF2RX_BCPF - [12:0] */
2664#define WM5100_AIF2RX_BCPF_SHIFT 0 /* AIF2RX_BCPF - [12:0] */
2665#define WM5100_AIF2RX_BCPF_WIDTH 13 /* AIF2RX_BCPF - [12:0] */
2666
2667/*
2668 * R1351 (0x547) - Audio IF 2_8
2669 */
2670#define WM5100_AIF2TX_WL_MASK 0x3F00 /* AIF2TX_WL - [13:8] */
2671#define WM5100_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [13:8] */
2672#define WM5100_AIF2TX_WL_WIDTH 6 /* AIF2TX_WL - [13:8] */
2673#define WM5100_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */
2674#define WM5100_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */
2675#define WM5100_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */
2676
2677/*
2678 * R1352 (0x548) - Audio IF 2_9
2679 */
2680#define WM5100_AIF2RX_WL_MASK 0x3F00 /* AIF2RX_WL - [13:8] */
2681#define WM5100_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [13:8] */
2682#define WM5100_AIF2RX_WL_WIDTH 6 /* AIF2RX_WL - [13:8] */
2683#define WM5100_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */
2684#define WM5100_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */
2685#define WM5100_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */
2686
2687/*
2688 * R1353 (0x549) - Audio IF 2_10
2689 */
2690#define WM5100_AIF2TX1_SLOT_MASK 0x003F /* AIF2TX1_SLOT - [5:0] */
2691#define WM5100_AIF2TX1_SLOT_SHIFT 0 /* AIF2TX1_SLOT - [5:0] */
2692#define WM5100_AIF2TX1_SLOT_WIDTH 6 /* AIF2TX1_SLOT - [5:0] */
2693
2694/*
2695 * R1354 (0x54A) - Audio IF 2_11
2696 */
2697#define WM5100_AIF2TX2_SLOT_MASK 0x003F /* AIF2TX2_SLOT - [5:0] */
2698#define WM5100_AIF2TX2_SLOT_SHIFT 0 /* AIF2TX2_SLOT - [5:0] */
2699#define WM5100_AIF2TX2_SLOT_WIDTH 6 /* AIF2TX2_SLOT - [5:0] */
2700
2701/*
2702 * R1361 (0x551) - Audio IF 2_18
2703 */
2704#define WM5100_AIF2RX1_SLOT_MASK 0x003F /* AIF2RX1_SLOT - [5:0] */
2705#define WM5100_AIF2RX1_SLOT_SHIFT 0 /* AIF2RX1_SLOT - [5:0] */
2706#define WM5100_AIF2RX1_SLOT_WIDTH 6 /* AIF2RX1_SLOT - [5:0] */
2707
2708/*
2709 * R1362 (0x552) - Audio IF 2_19
2710 */
2711#define WM5100_AIF2RX2_SLOT_MASK 0x003F /* AIF2RX2_SLOT - [5:0] */
2712#define WM5100_AIF2RX2_SLOT_SHIFT 0 /* AIF2RX2_SLOT - [5:0] */
2713#define WM5100_AIF2RX2_SLOT_WIDTH 6 /* AIF2RX2_SLOT - [5:0] */
2714
2715/*
2716 * R1369 (0x559) - Audio IF 2_26
2717 */
2718#define WM5100_AIF2TX2_ENA 0x0002 /* AIF2TX2_ENA */
2719#define WM5100_AIF2TX2_ENA_MASK 0x0002 /* AIF2TX2_ENA */
2720#define WM5100_AIF2TX2_ENA_SHIFT 1 /* AIF2TX2_ENA */
2721#define WM5100_AIF2TX2_ENA_WIDTH 1 /* AIF2TX2_ENA */
2722#define WM5100_AIF2TX1_ENA 0x0001 /* AIF2TX1_ENA */
2723#define WM5100_AIF2TX1_ENA_MASK 0x0001 /* AIF2TX1_ENA */
2724#define WM5100_AIF2TX1_ENA_SHIFT 0 /* AIF2TX1_ENA */
2725#define WM5100_AIF2TX1_ENA_WIDTH 1 /* AIF2TX1_ENA */
2726
2727/*
2728 * R1370 (0x55A) - Audio IF 2_27
2729 */
2730#define WM5100_AIF2RX2_ENA 0x0002 /* AIF2RX2_ENA */
2731#define WM5100_AIF2RX2_ENA_MASK 0x0002 /* AIF2RX2_ENA */
2732#define WM5100_AIF2RX2_ENA_SHIFT 1 /* AIF2RX2_ENA */
2733#define WM5100_AIF2RX2_ENA_WIDTH 1 /* AIF2RX2_ENA */
2734#define WM5100_AIF2RX1_ENA 0x0001 /* AIF2RX1_ENA */
2735#define WM5100_AIF2RX1_ENA_MASK 0x0001 /* AIF2RX1_ENA */
2736#define WM5100_AIF2RX1_ENA_SHIFT 0 /* AIF2RX1_ENA */
2737#define WM5100_AIF2RX1_ENA_WIDTH 1 /* AIF2RX1_ENA */
2738
2739/*
2740 * R1408 (0x580) - Audio IF 3_1
2741 */
2742#define WM5100_AIF3_BCLK_INV 0x0080 /* AIF3_BCLK_INV */
2743#define WM5100_AIF3_BCLK_INV_MASK 0x0080 /* AIF3_BCLK_INV */
2744#define WM5100_AIF3_BCLK_INV_SHIFT 7 /* AIF3_BCLK_INV */
2745#define WM5100_AIF3_BCLK_INV_WIDTH 1 /* AIF3_BCLK_INV */
2746#define WM5100_AIF3_BCLK_FRC 0x0040 /* AIF3_BCLK_FRC */
2747#define WM5100_AIF3_BCLK_FRC_MASK 0x0040 /* AIF3_BCLK_FRC */
2748#define WM5100_AIF3_BCLK_FRC_SHIFT 6 /* AIF3_BCLK_FRC */
2749#define WM5100_AIF3_BCLK_FRC_WIDTH 1 /* AIF3_BCLK_FRC */
2750#define WM5100_AIF3_BCLK_MSTR 0x0020 /* AIF3_BCLK_MSTR */
2751#define WM5100_AIF3_BCLK_MSTR_MASK 0x0020 /* AIF3_BCLK_MSTR */
2752#define WM5100_AIF3_BCLK_MSTR_SHIFT 5 /* AIF3_BCLK_MSTR */
2753#define WM5100_AIF3_BCLK_MSTR_WIDTH 1 /* AIF3_BCLK_MSTR */
2754#define WM5100_AIF3_BCLK_FREQ_MASK 0x001F /* AIF3_BCLK_FREQ - [4:0] */
2755#define WM5100_AIF3_BCLK_FREQ_SHIFT 0 /* AIF3_BCLK_FREQ - [4:0] */
2756#define WM5100_AIF3_BCLK_FREQ_WIDTH 5 /* AIF3_BCLK_FREQ - [4:0] */
2757
2758/*
2759 * R1409 (0x581) - Audio IF 3_2
2760 */
2761#define WM5100_AIF3TX_DAT_TRI 0x0020 /* AIF3TX_DAT_TRI */
2762#define WM5100_AIF3TX_DAT_TRI_MASK 0x0020 /* AIF3TX_DAT_TRI */
2763#define WM5100_AIF3TX_DAT_TRI_SHIFT 5 /* AIF3TX_DAT_TRI */
2764#define WM5100_AIF3TX_DAT_TRI_WIDTH 1 /* AIF3TX_DAT_TRI */
2765#define WM5100_AIF3TX_LRCLK_SRC 0x0008 /* AIF3TX_LRCLK_SRC */
2766#define WM5100_AIF3TX_LRCLK_SRC_MASK 0x0008 /* AIF3TX_LRCLK_SRC */
2767#define WM5100_AIF3TX_LRCLK_SRC_SHIFT 3 /* AIF3TX_LRCLK_SRC */
2768#define WM5100_AIF3TX_LRCLK_SRC_WIDTH 1 /* AIF3TX_LRCLK_SRC */
2769#define WM5100_AIF3TX_LRCLK_INV 0x0004 /* AIF3TX_LRCLK_INV */
2770#define WM5100_AIF3TX_LRCLK_INV_MASK 0x0004 /* AIF3TX_LRCLK_INV */
2771#define WM5100_AIF3TX_LRCLK_INV_SHIFT 2 /* AIF3TX_LRCLK_INV */
2772#define WM5100_AIF3TX_LRCLK_INV_WIDTH 1 /* AIF3TX_LRCLK_INV */
2773#define WM5100_AIF3TX_LRCLK_FRC 0x0002 /* AIF3TX_LRCLK_FRC */
2774#define WM5100_AIF3TX_LRCLK_FRC_MASK 0x0002 /* AIF3TX_LRCLK_FRC */
2775#define WM5100_AIF3TX_LRCLK_FRC_SHIFT 1 /* AIF3TX_LRCLK_FRC */
2776#define WM5100_AIF3TX_LRCLK_FRC_WIDTH 1 /* AIF3TX_LRCLK_FRC */
2777#define WM5100_AIF3TX_LRCLK_MSTR 0x0001 /* AIF3TX_LRCLK_MSTR */
2778#define WM5100_AIF3TX_LRCLK_MSTR_MASK 0x0001 /* AIF3TX_LRCLK_MSTR */
2779#define WM5100_AIF3TX_LRCLK_MSTR_SHIFT 0 /* AIF3TX_LRCLK_MSTR */
2780#define WM5100_AIF3TX_LRCLK_MSTR_WIDTH 1 /* AIF3TX_LRCLK_MSTR */
2781
2782/*
2783 * R1410 (0x582) - Audio IF 3_3
2784 */
2785#define WM5100_AIF3RX_LRCLK_INV 0x0004 /* AIF3RX_LRCLK_INV */
2786#define WM5100_AIF3RX_LRCLK_INV_MASK 0x0004 /* AIF3RX_LRCLK_INV */
2787#define WM5100_AIF3RX_LRCLK_INV_SHIFT 2 /* AIF3RX_LRCLK_INV */
2788#define WM5100_AIF3RX_LRCLK_INV_WIDTH 1 /* AIF3RX_LRCLK_INV */
2789#define WM5100_AIF3RX_LRCLK_FRC 0x0002 /* AIF3RX_LRCLK_FRC */
2790#define WM5100_AIF3RX_LRCLK_FRC_MASK 0x0002 /* AIF3RX_LRCLK_FRC */
2791#define WM5100_AIF3RX_LRCLK_FRC_SHIFT 1 /* AIF3RX_LRCLK_FRC */
2792#define WM5100_AIF3RX_LRCLK_FRC_WIDTH 1 /* AIF3RX_LRCLK_FRC */
2793#define WM5100_AIF3RX_LRCLK_MSTR 0x0001 /* AIF3RX_LRCLK_MSTR */
2794#define WM5100_AIF3RX_LRCLK_MSTR_MASK 0x0001 /* AIF3RX_LRCLK_MSTR */
2795#define WM5100_AIF3RX_LRCLK_MSTR_SHIFT 0 /* AIF3RX_LRCLK_MSTR */
2796#define WM5100_AIF3RX_LRCLK_MSTR_WIDTH 1 /* AIF3RX_LRCLK_MSTR */
2797
2798/*
2799 * R1411 (0x583) - Audio IF 3_4
2800 */
2801#define WM5100_AIF3_TRI 0x0040 /* AIF3_TRI */
2802#define WM5100_AIF3_TRI_MASK 0x0040 /* AIF3_TRI */
2803#define WM5100_AIF3_TRI_SHIFT 6 /* AIF3_TRI */
2804#define WM5100_AIF3_TRI_WIDTH 1 /* AIF3_TRI */
2805#define WM5100_AIF3_RATE_MASK 0x0003 /* AIF3_RATE - [1:0] */
2806#define WM5100_AIF3_RATE_SHIFT 0 /* AIF3_RATE - [1:0] */
2807#define WM5100_AIF3_RATE_WIDTH 2 /* AIF3_RATE - [1:0] */
2808
2809/*
2810 * R1412 (0x584) - Audio IF 3_5
2811 */
2812#define WM5100_AIF3_FMT_MASK 0x0007 /* AIF3_FMT - [2:0] */
2813#define WM5100_AIF3_FMT_SHIFT 0 /* AIF3_FMT - [2:0] */
2814#define WM5100_AIF3_FMT_WIDTH 3 /* AIF3_FMT - [2:0] */
2815
2816/*
2817 * R1413 (0x585) - Audio IF 3_6
2818 */
2819#define WM5100_AIF3TX_BCPF_MASK 0x1FFF /* AIF3TX_BCPF - [12:0] */
2820#define WM5100_AIF3TX_BCPF_SHIFT 0 /* AIF3TX_BCPF - [12:0] */
2821#define WM5100_AIF3TX_BCPF_WIDTH 13 /* AIF3TX_BCPF - [12:0] */
2822
2823/*
2824 * R1414 (0x586) - Audio IF 3_7
2825 */
2826#define WM5100_AIF3RX_BCPF_MASK 0x1FFF /* AIF3RX_BCPF - [12:0] */
2827#define WM5100_AIF3RX_BCPF_SHIFT 0 /* AIF3RX_BCPF - [12:0] */
2828#define WM5100_AIF3RX_BCPF_WIDTH 13 /* AIF3RX_BCPF - [12:0] */
2829
2830/*
2831 * R1415 (0x587) - Audio IF 3_8
2832 */
2833#define WM5100_AIF3TX_WL_MASK 0x3F00 /* AIF3TX_WL - [13:8] */
2834#define WM5100_AIF3TX_WL_SHIFT 8 /* AIF3TX_WL - [13:8] */
2835#define WM5100_AIF3TX_WL_WIDTH 6 /* AIF3TX_WL - [13:8] */
2836#define WM5100_AIF3TX_SLOT_LEN_MASK 0x00FF /* AIF3TX_SLOT_LEN - [7:0] */
2837#define WM5100_AIF3TX_SLOT_LEN_SHIFT 0 /* AIF3TX_SLOT_LEN - [7:0] */
2838#define WM5100_AIF3TX_SLOT_LEN_WIDTH 8 /* AIF3TX_SLOT_LEN - [7:0] */
2839
2840/*
2841 * R1416 (0x588) - Audio IF 3_9
2842 */
2843#define WM5100_AIF3RX_WL_MASK 0x3F00 /* AIF3RX_WL - [13:8] */
2844#define WM5100_AIF3RX_WL_SHIFT 8 /* AIF3RX_WL - [13:8] */
2845#define WM5100_AIF3RX_WL_WIDTH 6 /* AIF3RX_WL - [13:8] */
2846#define WM5100_AIF3RX_SLOT_LEN_MASK 0x00FF /* AIF3RX_SLOT_LEN - [7:0] */
2847#define WM5100_AIF3RX_SLOT_LEN_SHIFT 0 /* AIF3RX_SLOT_LEN - [7:0] */
2848#define WM5100_AIF3RX_SLOT_LEN_WIDTH 8 /* AIF3RX_SLOT_LEN - [7:0] */
2849
2850/*
2851 * R1417 (0x589) - Audio IF 3_10
2852 */
2853#define WM5100_AIF3TX1_SLOT_MASK 0x003F /* AIF3TX1_SLOT - [5:0] */
2854#define WM5100_AIF3TX1_SLOT_SHIFT 0 /* AIF3TX1_SLOT - [5:0] */
2855#define WM5100_AIF3TX1_SLOT_WIDTH 6 /* AIF3TX1_SLOT - [5:0] */
2856
2857/*
2858 * R1418 (0x58A) - Audio IF 3_11
2859 */
2860#define WM5100_AIF3TX2_SLOT_MASK 0x003F /* AIF3TX2_SLOT - [5:0] */
2861#define WM5100_AIF3TX2_SLOT_SHIFT 0 /* AIF3TX2_SLOT - [5:0] */
2862#define WM5100_AIF3TX2_SLOT_WIDTH 6 /* AIF3TX2_SLOT - [5:0] */
2863
2864/*
2865 * R1425 (0x591) - Audio IF 3_18
2866 */
2867#define WM5100_AIF3RX1_SLOT_MASK 0x003F /* AIF3RX1_SLOT - [5:0] */
2868#define WM5100_AIF3RX1_SLOT_SHIFT 0 /* AIF3RX1_SLOT - [5:0] */
2869#define WM5100_AIF3RX1_SLOT_WIDTH 6 /* AIF3RX1_SLOT - [5:0] */
2870
2871/*
2872 * R1426 (0x592) - Audio IF 3_19
2873 */
2874#define WM5100_AIF3RX2_SLOT_MASK 0x003F /* AIF3RX2_SLOT - [5:0] */
2875#define WM5100_AIF3RX2_SLOT_SHIFT 0 /* AIF3RX2_SLOT - [5:0] */
2876#define WM5100_AIF3RX2_SLOT_WIDTH 6 /* AIF3RX2_SLOT - [5:0] */
2877
2878/*
2879 * R1433 (0x599) - Audio IF 3_26
2880 */
2881#define WM5100_AIF3TX2_ENA 0x0002 /* AIF3TX2_ENA */
2882#define WM5100_AIF3TX2_ENA_MASK 0x0002 /* AIF3TX2_ENA */
2883#define WM5100_AIF3TX2_ENA_SHIFT 1 /* AIF3TX2_ENA */
2884#define WM5100_AIF3TX2_ENA_WIDTH 1 /* AIF3TX2_ENA */
2885#define WM5100_AIF3TX1_ENA 0x0001 /* AIF3TX1_ENA */
2886#define WM5100_AIF3TX1_ENA_MASK 0x0001 /* AIF3TX1_ENA */
2887#define WM5100_AIF3TX1_ENA_SHIFT 0 /* AIF3TX1_ENA */
2888#define WM5100_AIF3TX1_ENA_WIDTH 1 /* AIF3TX1_ENA */
2889
2890/*
2891 * R1434 (0x59A) - Audio IF 3_27
2892 */
2893#define WM5100_AIF3RX2_ENA 0x0002 /* AIF3RX2_ENA */
2894#define WM5100_AIF3RX2_ENA_MASK 0x0002 /* AIF3RX2_ENA */
2895#define WM5100_AIF3RX2_ENA_SHIFT 1 /* AIF3RX2_ENA */
2896#define WM5100_AIF3RX2_ENA_WIDTH 1 /* AIF3RX2_ENA */
2897#define WM5100_AIF3RX1_ENA 0x0001 /* AIF3RX1_ENA */
2898#define WM5100_AIF3RX1_ENA_MASK 0x0001 /* AIF3RX1_ENA */
2899#define WM5100_AIF3RX1_ENA_SHIFT 0 /* AIF3RX1_ENA */
2900#define WM5100_AIF3RX1_ENA_WIDTH 1 /* AIF3RX1_ENA */
2901
2902#define WM5100_MIXER_VOL_MASK 0x00FE /* MIXER_VOL - [7:1] */
2903#define WM5100_MIXER_VOL_SHIFT 1 /* MIXER_VOL - [7:1] */
2904#define WM5100_MIXER_VOL_WIDTH 7 /* MIXER_VOL - [7:1] */
2905
2906/*
2907 * R3072 (0xC00) - GPIO CTRL 1
2908 */
2909#define WM5100_GP1_DIR 0x8000 /* GP1_DIR */
2910#define WM5100_GP1_DIR_MASK 0x8000 /* GP1_DIR */
2911#define WM5100_GP1_DIR_SHIFT 15 /* GP1_DIR */
2912#define WM5100_GP1_DIR_WIDTH 1 /* GP1_DIR */
2913#define WM5100_GP1_PU 0x4000 /* GP1_PU */
2914#define WM5100_GP1_PU_MASK 0x4000 /* GP1_PU */
2915#define WM5100_GP1_PU_SHIFT 14 /* GP1_PU */
2916#define WM5100_GP1_PU_WIDTH 1 /* GP1_PU */
2917#define WM5100_GP1_PD 0x2000 /* GP1_PD */
2918#define WM5100_GP1_PD_MASK 0x2000 /* GP1_PD */
2919#define WM5100_GP1_PD_SHIFT 13 /* GP1_PD */
2920#define WM5100_GP1_PD_WIDTH 1 /* GP1_PD */
2921#define WM5100_GP1_POL 0x0400 /* GP1_POL */
2922#define WM5100_GP1_POL_MASK 0x0400 /* GP1_POL */
2923#define WM5100_GP1_POL_SHIFT 10 /* GP1_POL */
2924#define WM5100_GP1_POL_WIDTH 1 /* GP1_POL */
2925#define WM5100_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */
2926#define WM5100_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */
2927#define WM5100_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */
2928#define WM5100_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */
2929#define WM5100_GP1_DB 0x0100 /* GP1_DB */
2930#define WM5100_GP1_DB_MASK 0x0100 /* GP1_DB */
2931#define WM5100_GP1_DB_SHIFT 8 /* GP1_DB */
2932#define WM5100_GP1_DB_WIDTH 1 /* GP1_DB */
2933#define WM5100_GP1_LVL 0x0040 /* GP1_LVL */
2934#define WM5100_GP1_LVL_MASK 0x0040 /* GP1_LVL */
2935#define WM5100_GP1_LVL_SHIFT 6 /* GP1_LVL */
2936#define WM5100_GP1_LVL_WIDTH 1 /* GP1_LVL */
2937#define WM5100_GP1_FN_MASK 0x003F /* GP1_FN - [5:0] */
2938#define WM5100_GP1_FN_SHIFT 0 /* GP1_FN - [5:0] */
2939#define WM5100_GP1_FN_WIDTH 6 /* GP1_FN - [5:0] */
2940
2941/*
2942 * R3073 (0xC01) - GPIO CTRL 2
2943 */
2944#define WM5100_GP2_DIR 0x8000 /* GP2_DIR */
2945#define WM5100_GP2_DIR_MASK 0x8000 /* GP2_DIR */
2946#define WM5100_GP2_DIR_SHIFT 15 /* GP2_DIR */
2947#define WM5100_GP2_DIR_WIDTH 1 /* GP2_DIR */
2948#define WM5100_GP2_PU 0x4000 /* GP2_PU */
2949#define WM5100_GP2_PU_MASK 0x4000 /* GP2_PU */
2950#define WM5100_GP2_PU_SHIFT 14 /* GP2_PU */
2951#define WM5100_GP2_PU_WIDTH 1 /* GP2_PU */
2952#define WM5100_GP2_PD 0x2000 /* GP2_PD */
2953#define WM5100_GP2_PD_MASK 0x2000 /* GP2_PD */
2954#define WM5100_GP2_PD_SHIFT 13 /* GP2_PD */
2955#define WM5100_GP2_PD_WIDTH 1 /* GP2_PD */
2956#define WM5100_GP2_POL 0x0400 /* GP2_POL */
2957#define WM5100_GP2_POL_MASK 0x0400 /* GP2_POL */
2958#define WM5100_GP2_POL_SHIFT 10 /* GP2_POL */
2959#define WM5100_GP2_POL_WIDTH 1 /* GP2_POL */
2960#define WM5100_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */
2961#define WM5100_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */
2962#define WM5100_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */
2963#define WM5100_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */
2964#define WM5100_GP2_DB 0x0100 /* GP2_DB */
2965#define WM5100_GP2_DB_MASK 0x0100 /* GP2_DB */
2966#define WM5100_GP2_DB_SHIFT 8 /* GP2_DB */
2967#define WM5100_GP2_DB_WIDTH 1 /* GP2_DB */
2968#define WM5100_GP2_LVL 0x0040 /* GP2_LVL */
2969#define WM5100_GP2_LVL_MASK 0x0040 /* GP2_LVL */
2970#define WM5100_GP2_LVL_SHIFT 6 /* GP2_LVL */
2971#define WM5100_GP2_LVL_WIDTH 1 /* GP2_LVL */
2972#define WM5100_GP2_FN_MASK 0x003F /* GP2_FN - [5:0] */
2973#define WM5100_GP2_FN_SHIFT 0 /* GP2_FN - [5:0] */
2974#define WM5100_GP2_FN_WIDTH 6 /* GP2_FN - [5:0] */
2975
2976/*
2977 * R3074 (0xC02) - GPIO CTRL 3
2978 */
2979#define WM5100_GP3_DIR 0x8000 /* GP3_DIR */
2980#define WM5100_GP3_DIR_MASK 0x8000 /* GP3_DIR */
2981#define WM5100_GP3_DIR_SHIFT 15 /* GP3_DIR */
2982#define WM5100_GP3_DIR_WIDTH 1 /* GP3_DIR */
2983#define WM5100_GP3_PU 0x4000 /* GP3_PU */
2984#define WM5100_GP3_PU_MASK 0x4000 /* GP3_PU */
2985#define WM5100_GP3_PU_SHIFT 14 /* GP3_PU */
2986#define WM5100_GP3_PU_WIDTH 1 /* GP3_PU */
2987#define WM5100_GP3_PD 0x2000 /* GP3_PD */
2988#define WM5100_GP3_PD_MASK 0x2000 /* GP3_PD */
2989#define WM5100_GP3_PD_SHIFT 13 /* GP3_PD */
2990#define WM5100_GP3_PD_WIDTH 1 /* GP3_PD */
2991#define WM5100_GP3_POL 0x0400 /* GP3_POL */
2992#define WM5100_GP3_POL_MASK 0x0400 /* GP3_POL */
2993#define WM5100_GP3_POL_SHIFT 10 /* GP3_POL */
2994#define WM5100_GP3_POL_WIDTH 1 /* GP3_POL */
2995#define WM5100_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */
2996#define WM5100_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */
2997#define WM5100_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */
2998#define WM5100_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */
2999#define WM5100_GP3_DB 0x0100 /* GP3_DB */
3000#define WM5100_GP3_DB_MASK 0x0100 /* GP3_DB */
3001#define WM5100_GP3_DB_SHIFT 8 /* GP3_DB */
3002#define WM5100_GP3_DB_WIDTH 1 /* GP3_DB */
3003#define WM5100_GP3_LVL 0x0040 /* GP3_LVL */
3004#define WM5100_GP3_LVL_MASK 0x0040 /* GP3_LVL */
3005#define WM5100_GP3_LVL_SHIFT 6 /* GP3_LVL */
3006#define WM5100_GP3_LVL_WIDTH 1 /* GP3_LVL */
3007#define WM5100_GP3_FN_MASK 0x003F /* GP3_FN - [5:0] */
3008#define WM5100_GP3_FN_SHIFT 0 /* GP3_FN - [5:0] */
3009#define WM5100_GP3_FN_WIDTH 6 /* GP3_FN - [5:0] */
3010
3011/*
3012 * R3075 (0xC03) - GPIO CTRL 4
3013 */
3014#define WM5100_GP4_DIR 0x8000 /* GP4_DIR */
3015#define WM5100_GP4_DIR_MASK 0x8000 /* GP4_DIR */
3016#define WM5100_GP4_DIR_SHIFT 15 /* GP4_DIR */
3017#define WM5100_GP4_DIR_WIDTH 1 /* GP4_DIR */
3018#define WM5100_GP4_PU 0x4000 /* GP4_PU */
3019#define WM5100_GP4_PU_MASK 0x4000 /* GP4_PU */
3020#define WM5100_GP4_PU_SHIFT 14 /* GP4_PU */
3021#define WM5100_GP4_PU_WIDTH 1 /* GP4_PU */
3022#define WM5100_GP4_PD 0x2000 /* GP4_PD */
3023#define WM5100_GP4_PD_MASK 0x2000 /* GP4_PD */
3024#define WM5100_GP4_PD_SHIFT 13 /* GP4_PD */
3025#define WM5100_GP4_PD_WIDTH 1 /* GP4_PD */
3026#define WM5100_GP4_POL 0x0400 /* GP4_POL */
3027#define WM5100_GP4_POL_MASK 0x0400 /* GP4_POL */
3028#define WM5100_GP4_POL_SHIFT 10 /* GP4_POL */
3029#define WM5100_GP4_POL_WIDTH 1 /* GP4_POL */
3030#define WM5100_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */
3031#define WM5100_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */
3032#define WM5100_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */
3033#define WM5100_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */
3034#define WM5100_GP4_DB 0x0100 /* GP4_DB */
3035#define WM5100_GP4_DB_MASK 0x0100 /* GP4_DB */
3036#define WM5100_GP4_DB_SHIFT 8 /* GP4_DB */
3037#define WM5100_GP4_DB_WIDTH 1 /* GP4_DB */
3038#define WM5100_GP4_LVL 0x0040 /* GP4_LVL */
3039#define WM5100_GP4_LVL_MASK 0x0040 /* GP4_LVL */
3040#define WM5100_GP4_LVL_SHIFT 6 /* GP4_LVL */
3041#define WM5100_GP4_LVL_WIDTH 1 /* GP4_LVL */
3042#define WM5100_GP4_FN_MASK 0x003F /* GP4_FN - [5:0] */
3043#define WM5100_GP4_FN_SHIFT 0 /* GP4_FN - [5:0] */
3044#define WM5100_GP4_FN_WIDTH 6 /* GP4_FN - [5:0] */
3045
3046/*
3047 * R3076 (0xC04) - GPIO CTRL 5
3048 */
3049#define WM5100_GP5_DIR 0x8000 /* GP5_DIR */
3050#define WM5100_GP5_DIR_MASK 0x8000 /* GP5_DIR */
3051#define WM5100_GP5_DIR_SHIFT 15 /* GP5_DIR */
3052#define WM5100_GP5_DIR_WIDTH 1 /* GP5_DIR */
3053#define WM5100_GP5_PU 0x4000 /* GP5_PU */
3054#define WM5100_GP5_PU_MASK 0x4000 /* GP5_PU */
3055#define WM5100_GP5_PU_SHIFT 14 /* GP5_PU */
3056#define WM5100_GP5_PU_WIDTH 1 /* GP5_PU */
3057#define WM5100_GP5_PD 0x2000 /* GP5_PD */
3058#define WM5100_GP5_PD_MASK 0x2000 /* GP5_PD */
3059#define WM5100_GP5_PD_SHIFT 13 /* GP5_PD */
3060#define WM5100_GP5_PD_WIDTH 1 /* GP5_PD */
3061#define WM5100_GP5_POL 0x0400 /* GP5_POL */
3062#define WM5100_GP5_POL_MASK 0x0400 /* GP5_POL */
3063#define WM5100_GP5_POL_SHIFT 10 /* GP5_POL */
3064#define WM5100_GP5_POL_WIDTH 1 /* GP5_POL */
3065#define WM5100_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */
3066#define WM5100_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */
3067#define WM5100_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */
3068#define WM5100_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */
3069#define WM5100_GP5_DB 0x0100 /* GP5_DB */
3070#define WM5100_GP5_DB_MASK 0x0100 /* GP5_DB */
3071#define WM5100_GP5_DB_SHIFT 8 /* GP5_DB */
3072#define WM5100_GP5_DB_WIDTH 1 /* GP5_DB */
3073#define WM5100_GP5_LVL 0x0040 /* GP5_LVL */
3074#define WM5100_GP5_LVL_MASK 0x0040 /* GP5_LVL */
3075#define WM5100_GP5_LVL_SHIFT 6 /* GP5_LVL */
3076#define WM5100_GP5_LVL_WIDTH 1 /* GP5_LVL */
3077#define WM5100_GP5_FN_MASK 0x003F /* GP5_FN - [5:0] */
3078#define WM5100_GP5_FN_SHIFT 0 /* GP5_FN - [5:0] */
3079#define WM5100_GP5_FN_WIDTH 6 /* GP5_FN - [5:0] */
3080
3081/*
3082 * R3077 (0xC05) - GPIO CTRL 6
3083 */
3084#define WM5100_GP6_DIR 0x8000 /* GP6_DIR */
3085#define WM5100_GP6_DIR_MASK 0x8000 /* GP6_DIR */
3086#define WM5100_GP6_DIR_SHIFT 15 /* GP6_DIR */
3087#define WM5100_GP6_DIR_WIDTH 1 /* GP6_DIR */
3088#define WM5100_GP6_PU 0x4000 /* GP6_PU */
3089#define WM5100_GP6_PU_MASK 0x4000 /* GP6_PU */
3090#define WM5100_GP6_PU_SHIFT 14 /* GP6_PU */
3091#define WM5100_GP6_PU_WIDTH 1 /* GP6_PU */
3092#define WM5100_GP6_PD 0x2000 /* GP6_PD */
3093#define WM5100_GP6_PD_MASK 0x2000 /* GP6_PD */
3094#define WM5100_GP6_PD_SHIFT 13 /* GP6_PD */
3095#define WM5100_GP6_PD_WIDTH 1 /* GP6_PD */
3096#define WM5100_GP6_POL 0x0400 /* GP6_POL */
3097#define WM5100_GP6_POL_MASK 0x0400 /* GP6_POL */
3098#define WM5100_GP6_POL_SHIFT 10 /* GP6_POL */
3099#define WM5100_GP6_POL_WIDTH 1 /* GP6_POL */
3100#define WM5100_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */
3101#define WM5100_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */
3102#define WM5100_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */
3103#define WM5100_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */
3104#define WM5100_GP6_DB 0x0100 /* GP6_DB */
3105#define WM5100_GP6_DB_MASK 0x0100 /* GP6_DB */
3106#define WM5100_GP6_DB_SHIFT 8 /* GP6_DB */
3107#define WM5100_GP6_DB_WIDTH 1 /* GP6_DB */
3108#define WM5100_GP6_LVL 0x0040 /* GP6_LVL */
3109#define WM5100_GP6_LVL_MASK 0x0040 /* GP6_LVL */
3110#define WM5100_GP6_LVL_SHIFT 6 /* GP6_LVL */
3111#define WM5100_GP6_LVL_WIDTH 1 /* GP6_LVL */
3112#define WM5100_GP6_FN_MASK 0x003F /* GP6_FN - [5:0] */
3113#define WM5100_GP6_FN_SHIFT 0 /* GP6_FN - [5:0] */
3114#define WM5100_GP6_FN_WIDTH 6 /* GP6_FN - [5:0] */
3115
3116/*
3117 * R3107 (0xC23) - Misc Pad Ctrl 1
3118 */
3119#define WM5100_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */
3120#define WM5100_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */
3121#define WM5100_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */
3122#define WM5100_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */
3123#define WM5100_MCLK2_PD 0x2000 /* MCLK2_PD */
3124#define WM5100_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */
3125#define WM5100_MCLK2_PD_SHIFT 13 /* MCLK2_PD */
3126#define WM5100_MCLK2_PD_WIDTH 1 /* MCLK2_PD */
3127#define WM5100_MCLK1_PD 0x1000 /* MCLK1_PD */
3128#define WM5100_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */
3129#define WM5100_MCLK1_PD_SHIFT 12 /* MCLK1_PD */
3130#define WM5100_MCLK1_PD_WIDTH 1 /* MCLK1_PD */
3131#define WM5100_RESET_PU 0x0002 /* RESET_PU */
3132#define WM5100_RESET_PU_MASK 0x0002 /* RESET_PU */
3133#define WM5100_RESET_PU_SHIFT 1 /* RESET_PU */
3134#define WM5100_RESET_PU_WIDTH 1 /* RESET_PU */
3135#define WM5100_ADDR_PD 0x0001 /* ADDR_PD */
3136#define WM5100_ADDR_PD_MASK 0x0001 /* ADDR_PD */
3137#define WM5100_ADDR_PD_SHIFT 0 /* ADDR_PD */
3138#define WM5100_ADDR_PD_WIDTH 1 /* ADDR_PD */
3139
3140/*
3141 * R3108 (0xC24) - Misc Pad Ctrl 2
3142 */
3143#define WM5100_DMICDAT4_PD 0x0008 /* DMICDAT4_PD */
3144#define WM5100_DMICDAT4_PD_MASK 0x0008 /* DMICDAT4_PD */
3145#define WM5100_DMICDAT4_PD_SHIFT 3 /* DMICDAT4_PD */
3146#define WM5100_DMICDAT4_PD_WIDTH 1 /* DMICDAT4_PD */
3147#define WM5100_DMICDAT3_PD 0x0004 /* DMICDAT3_PD */
3148#define WM5100_DMICDAT3_PD_MASK 0x0004 /* DMICDAT3_PD */
3149#define WM5100_DMICDAT3_PD_SHIFT 2 /* DMICDAT3_PD */
3150#define WM5100_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */
3151#define WM5100_DMICDAT2_PD 0x0002 /* DMICDAT2_PD */
3152#define WM5100_DMICDAT2_PD_MASK 0x0002 /* DMICDAT2_PD */
3153#define WM5100_DMICDAT2_PD_SHIFT 1 /* DMICDAT2_PD */
3154#define WM5100_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */
3155#define WM5100_DMICDAT1_PD 0x0001 /* DMICDAT1_PD */
3156#define WM5100_DMICDAT1_PD_MASK 0x0001 /* DMICDAT1_PD */
3157#define WM5100_DMICDAT1_PD_SHIFT 0 /* DMICDAT1_PD */
3158#define WM5100_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */
3159
3160/*
3161 * R3109 (0xC25) - Misc Pad Ctrl 3
3162 */
3163#define WM5100_AIF1RXLRCLK_PU 0x0020 /* AIF1RXLRCLK_PU */
3164#define WM5100_AIF1RXLRCLK_PU_MASK 0x0020 /* AIF1RXLRCLK_PU */
3165#define WM5100_AIF1RXLRCLK_PU_SHIFT 5 /* AIF1RXLRCLK_PU */
3166#define WM5100_AIF1RXLRCLK_PU_WIDTH 1 /* AIF1RXLRCLK_PU */
3167#define WM5100_AIF1RXLRCLK_PD 0x0010 /* AIF1RXLRCLK_PD */
3168#define WM5100_AIF1RXLRCLK_PD_MASK 0x0010 /* AIF1RXLRCLK_PD */
3169#define WM5100_AIF1RXLRCLK_PD_SHIFT 4 /* AIF1RXLRCLK_PD */
3170#define WM5100_AIF1RXLRCLK_PD_WIDTH 1 /* AIF1RXLRCLK_PD */
3171#define WM5100_AIF1BCLK_PU 0x0008 /* AIF1BCLK_PU */
3172#define WM5100_AIF1BCLK_PU_MASK 0x0008 /* AIF1BCLK_PU */
3173#define WM5100_AIF1BCLK_PU_SHIFT 3 /* AIF1BCLK_PU */
3174#define WM5100_AIF1BCLK_PU_WIDTH 1 /* AIF1BCLK_PU */
3175#define WM5100_AIF1BCLK_PD 0x0004 /* AIF1BCLK_PD */
3176#define WM5100_AIF1BCLK_PD_MASK 0x0004 /* AIF1BCLK_PD */
3177#define WM5100_AIF1BCLK_PD_SHIFT 2 /* AIF1BCLK_PD */
3178#define WM5100_AIF1BCLK_PD_WIDTH 1 /* AIF1BCLK_PD */
3179#define WM5100_AIF1RXDAT_PU 0x0002 /* AIF1RXDAT_PU */
3180#define WM5100_AIF1RXDAT_PU_MASK 0x0002 /* AIF1RXDAT_PU */
3181#define WM5100_AIF1RXDAT_PU_SHIFT 1 /* AIF1RXDAT_PU */
3182#define WM5100_AIF1RXDAT_PU_WIDTH 1 /* AIF1RXDAT_PU */
3183#define WM5100_AIF1RXDAT_PD 0x0001 /* AIF1RXDAT_PD */
3184#define WM5100_AIF1RXDAT_PD_MASK 0x0001 /* AIF1RXDAT_PD */
3185#define WM5100_AIF1RXDAT_PD_SHIFT 0 /* AIF1RXDAT_PD */
3186#define WM5100_AIF1RXDAT_PD_WIDTH 1 /* AIF1RXDAT_PD */
3187
3188/*
3189 * R3110 (0xC26) - Misc Pad Ctrl 4
3190 */
3191#define WM5100_AIF2RXLRCLK_PU 0x0020 /* AIF2RXLRCLK_PU */
3192#define WM5100_AIF2RXLRCLK_PU_MASK 0x0020 /* AIF2RXLRCLK_PU */
3193#define WM5100_AIF2RXLRCLK_PU_SHIFT 5 /* AIF2RXLRCLK_PU */
3194#define WM5100_AIF2RXLRCLK_PU_WIDTH 1 /* AIF2RXLRCLK_PU */
3195#define WM5100_AIF2RXLRCLK_PD 0x0010 /* AIF2RXLRCLK_PD */
3196#define WM5100_AIF2RXLRCLK_PD_MASK 0x0010 /* AIF2RXLRCLK_PD */
3197#define WM5100_AIF2RXLRCLK_PD_SHIFT 4 /* AIF2RXLRCLK_PD */
3198#define WM5100_AIF2RXLRCLK_PD_WIDTH 1 /* AIF2RXLRCLK_PD */
3199#define WM5100_AIF2BCLK_PU 0x0008 /* AIF2BCLK_PU */
3200#define WM5100_AIF2BCLK_PU_MASK 0x0008 /* AIF2BCLK_PU */
3201#define WM5100_AIF2BCLK_PU_SHIFT 3 /* AIF2BCLK_PU */
3202#define WM5100_AIF2BCLK_PU_WIDTH 1 /* AIF2BCLK_PU */
3203#define WM5100_AIF2BCLK_PD 0x0004 /* AIF2BCLK_PD */
3204#define WM5100_AIF2BCLK_PD_MASK 0x0004 /* AIF2BCLK_PD */
3205#define WM5100_AIF2BCLK_PD_SHIFT 2 /* AIF2BCLK_PD */
3206#define WM5100_AIF2BCLK_PD_WIDTH 1 /* AIF2BCLK_PD */
3207#define WM5100_AIF2RXDAT_PU 0x0002 /* AIF2RXDAT_PU */
3208#define WM5100_AIF2RXDAT_PU_MASK 0x0002 /* AIF2RXDAT_PU */
3209#define WM5100_AIF2RXDAT_PU_SHIFT 1 /* AIF2RXDAT_PU */
3210#define WM5100_AIF2RXDAT_PU_WIDTH 1 /* AIF2RXDAT_PU */
3211#define WM5100_AIF2RXDAT_PD 0x0001 /* AIF2RXDAT_PD */
3212#define WM5100_AIF2RXDAT_PD_MASK 0x0001 /* AIF2RXDAT_PD */
3213#define WM5100_AIF2RXDAT_PD_SHIFT 0 /* AIF2RXDAT_PD */
3214#define WM5100_AIF2RXDAT_PD_WIDTH 1 /* AIF2RXDAT_PD */
3215
3216/*
3217 * R3111 (0xC27) - Misc Pad Ctrl 5
3218 */
3219#define WM5100_AIF3RXLRCLK_PU 0x0020 /* AIF3RXLRCLK_PU */
3220#define WM5100_AIF3RXLRCLK_PU_MASK 0x0020 /* AIF3RXLRCLK_PU */
3221#define WM5100_AIF3RXLRCLK_PU_SHIFT 5 /* AIF3RXLRCLK_PU */
3222#define WM5100_AIF3RXLRCLK_PU_WIDTH 1 /* AIF3RXLRCLK_PU */
3223#define WM5100_AIF3RXLRCLK_PD 0x0010 /* AIF3RXLRCLK_PD */
3224#define WM5100_AIF3RXLRCLK_PD_MASK 0x0010 /* AIF3RXLRCLK_PD */
3225#define WM5100_AIF3RXLRCLK_PD_SHIFT 4 /* AIF3RXLRCLK_PD */
3226#define WM5100_AIF3RXLRCLK_PD_WIDTH 1 /* AIF3RXLRCLK_PD */
3227#define WM5100_AIF3BCLK_PU 0x0008 /* AIF3BCLK_PU */
3228#define WM5100_AIF3BCLK_PU_MASK 0x0008 /* AIF3BCLK_PU */
3229#define WM5100_AIF3BCLK_PU_SHIFT 3 /* AIF3BCLK_PU */
3230#define WM5100_AIF3BCLK_PU_WIDTH 1 /* AIF3BCLK_PU */
3231#define WM5100_AIF3BCLK_PD 0x0004 /* AIF3BCLK_PD */
3232#define WM5100_AIF3BCLK_PD_MASK 0x0004 /* AIF3BCLK_PD */
3233#define WM5100_AIF3BCLK_PD_SHIFT 2 /* AIF3BCLK_PD */
3234#define WM5100_AIF3BCLK_PD_WIDTH 1 /* AIF3BCLK_PD */
3235#define WM5100_AIF3RXDAT_PU 0x0002 /* AIF3RXDAT_PU */
3236#define WM5100_AIF3RXDAT_PU_MASK 0x0002 /* AIF3RXDAT_PU */
3237#define WM5100_AIF3RXDAT_PU_SHIFT 1 /* AIF3RXDAT_PU */
3238#define WM5100_AIF3RXDAT_PU_WIDTH 1 /* AIF3RXDAT_PU */
3239#define WM5100_AIF3RXDAT_PD 0x0001 /* AIF3RXDAT_PD */
3240#define WM5100_AIF3RXDAT_PD_MASK 0x0001 /* AIF3RXDAT_PD */
3241#define WM5100_AIF3RXDAT_PD_SHIFT 0 /* AIF3RXDAT_PD */
3242#define WM5100_AIF3RXDAT_PD_WIDTH 1 /* AIF3RXDAT_PD */
3243
3244/*
3245 * R3112 (0xC28) - Misc GPIO 1
3246 */
3247#define WM5100_OPCLK_SEL_MASK 0x0003 /* OPCLK_SEL - [1:0] */
3248#define WM5100_OPCLK_SEL_SHIFT 0 /* OPCLK_SEL - [1:0] */
3249#define WM5100_OPCLK_SEL_WIDTH 2 /* OPCLK_SEL - [1:0] */
3250
3251/*
3252 * R3328 (0xD00) - Interrupt Status 1
3253 */
3254#define WM5100_GP6_EINT 0x0020 /* GP6_EINT */
3255#define WM5100_GP6_EINT_MASK 0x0020 /* GP6_EINT */
3256#define WM5100_GP6_EINT_SHIFT 5 /* GP6_EINT */
3257#define WM5100_GP6_EINT_WIDTH 1 /* GP6_EINT */
3258#define WM5100_GP5_EINT 0x0010 /* GP5_EINT */
3259#define WM5100_GP5_EINT_MASK 0x0010 /* GP5_EINT */
3260#define WM5100_GP5_EINT_SHIFT 4 /* GP5_EINT */
3261#define WM5100_GP5_EINT_WIDTH 1 /* GP5_EINT */
3262#define WM5100_GP4_EINT 0x0008 /* GP4_EINT */
3263#define WM5100_GP4_EINT_MASK 0x0008 /* GP4_EINT */
3264#define WM5100_GP4_EINT_SHIFT 3 /* GP4_EINT */
3265#define WM5100_GP4_EINT_WIDTH 1 /* GP4_EINT */
3266#define WM5100_GP3_EINT 0x0004 /* GP3_EINT */
3267#define WM5100_GP3_EINT_MASK 0x0004 /* GP3_EINT */
3268#define WM5100_GP3_EINT_SHIFT 2 /* GP3_EINT */
3269#define WM5100_GP3_EINT_WIDTH 1 /* GP3_EINT */
3270#define WM5100_GP2_EINT 0x0002 /* GP2_EINT */
3271#define WM5100_GP2_EINT_MASK 0x0002 /* GP2_EINT */
3272#define WM5100_GP2_EINT_SHIFT 1 /* GP2_EINT */
3273#define WM5100_GP2_EINT_WIDTH 1 /* GP2_EINT */
3274#define WM5100_GP1_EINT 0x0001 /* GP1_EINT */
3275#define WM5100_GP1_EINT_MASK 0x0001 /* GP1_EINT */
3276#define WM5100_GP1_EINT_SHIFT 0 /* GP1_EINT */
3277#define WM5100_GP1_EINT_WIDTH 1 /* GP1_EINT */
3278
3279/*
3280 * R3329 (0xD01) - Interrupt Status 2
3281 */
3282#define WM5100_DSP_IRQ6_EINT 0x0020 /* DSP_IRQ6_EINT */
3283#define WM5100_DSP_IRQ6_EINT_MASK 0x0020 /* DSP_IRQ6_EINT */
3284#define WM5100_DSP_IRQ6_EINT_SHIFT 5 /* DSP_IRQ6_EINT */
3285#define WM5100_DSP_IRQ6_EINT_WIDTH 1 /* DSP_IRQ6_EINT */
3286#define WM5100_DSP_IRQ5_EINT 0x0010 /* DSP_IRQ5_EINT */
3287#define WM5100_DSP_IRQ5_EINT_MASK 0x0010 /* DSP_IRQ5_EINT */
3288#define WM5100_DSP_IRQ5_EINT_SHIFT 4 /* DSP_IRQ5_EINT */
3289#define WM5100_DSP_IRQ5_EINT_WIDTH 1 /* DSP_IRQ5_EINT */
3290#define WM5100_DSP_IRQ4_EINT 0x0008 /* DSP_IRQ4_EINT */
3291#define WM5100_DSP_IRQ4_EINT_MASK 0x0008 /* DSP_IRQ4_EINT */
3292#define WM5100_DSP_IRQ4_EINT_SHIFT 3 /* DSP_IRQ4_EINT */
3293#define WM5100_DSP_IRQ4_EINT_WIDTH 1 /* DSP_IRQ4_EINT */
3294#define WM5100_DSP_IRQ3_EINT 0x0004 /* DSP_IRQ3_EINT */
3295#define WM5100_DSP_IRQ3_EINT_MASK 0x0004 /* DSP_IRQ3_EINT */
3296#define WM5100_DSP_IRQ3_EINT_SHIFT 2 /* DSP_IRQ3_EINT */
3297#define WM5100_DSP_IRQ3_EINT_WIDTH 1 /* DSP_IRQ3_EINT */
3298#define WM5100_DSP_IRQ2_EINT 0x0002 /* DSP_IRQ2_EINT */
3299#define WM5100_DSP_IRQ2_EINT_MASK 0x0002 /* DSP_IRQ2_EINT */
3300#define WM5100_DSP_IRQ2_EINT_SHIFT 1 /* DSP_IRQ2_EINT */
3301#define WM5100_DSP_IRQ2_EINT_WIDTH 1 /* DSP_IRQ2_EINT */
3302#define WM5100_DSP_IRQ1_EINT 0x0001 /* DSP_IRQ1_EINT */
3303#define WM5100_DSP_IRQ1_EINT_MASK 0x0001 /* DSP_IRQ1_EINT */
3304#define WM5100_DSP_IRQ1_EINT_SHIFT 0 /* DSP_IRQ1_EINT */
3305#define WM5100_DSP_IRQ1_EINT_WIDTH 1 /* DSP_IRQ1_EINT */
3306
3307/*
3308 * R3330 (0xD02) - Interrupt Status 3
3309 */
3310#define WM5100_SPK_SHUTDOWN_WARN_EINT 0x8000 /* SPK_SHUTDOWN_WARN_EINT */
3311#define WM5100_SPK_SHUTDOWN_WARN_EINT_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT */
3312#define WM5100_SPK_SHUTDOWN_WARN_EINT_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT */
3313#define WM5100_SPK_SHUTDOWN_WARN_EINT_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT */
3314#define WM5100_SPK_SHUTDOWN_EINT 0x4000 /* SPK_SHUTDOWN_EINT */
3315#define WM5100_SPK_SHUTDOWN_EINT_MASK 0x4000 /* SPK_SHUTDOWN_EINT */
3316#define WM5100_SPK_SHUTDOWN_EINT_SHIFT 14 /* SPK_SHUTDOWN_EINT */
3317#define WM5100_SPK_SHUTDOWN_EINT_WIDTH 1 /* SPK_SHUTDOWN_EINT */
3318#define WM5100_HPDET_EINT 0x2000 /* HPDET_EINT */
3319#define WM5100_HPDET_EINT_MASK 0x2000 /* HPDET_EINT */
3320#define WM5100_HPDET_EINT_SHIFT 13 /* HPDET_EINT */
3321#define WM5100_HPDET_EINT_WIDTH 1 /* HPDET_EINT */
3322#define WM5100_ACCDET_EINT 0x1000 /* ACCDET_EINT */
3323#define WM5100_ACCDET_EINT_MASK 0x1000 /* ACCDET_EINT */
3324#define WM5100_ACCDET_EINT_SHIFT 12 /* ACCDET_EINT */
3325#define WM5100_ACCDET_EINT_WIDTH 1 /* ACCDET_EINT */
3326#define WM5100_DRC_SIG_DET_EINT 0x0200 /* DRC_SIG_DET_EINT */
3327#define WM5100_DRC_SIG_DET_EINT_MASK 0x0200 /* DRC_SIG_DET_EINT */
3328#define WM5100_DRC_SIG_DET_EINT_SHIFT 9 /* DRC_SIG_DET_EINT */
3329#define WM5100_DRC_SIG_DET_EINT_WIDTH 1 /* DRC_SIG_DET_EINT */
3330#define WM5100_ASRC2_LOCK_EINT 0x0100 /* ASRC2_LOCK_EINT */
3331#define WM5100_ASRC2_LOCK_EINT_MASK 0x0100 /* ASRC2_LOCK_EINT */
3332#define WM5100_ASRC2_LOCK_EINT_SHIFT 8 /* ASRC2_LOCK_EINT */
3333#define WM5100_ASRC2_LOCK_EINT_WIDTH 1 /* ASRC2_LOCK_EINT */
3334#define WM5100_ASRC1_LOCK_EINT 0x0080 /* ASRC1_LOCK_EINT */
3335#define WM5100_ASRC1_LOCK_EINT_MASK 0x0080 /* ASRC1_LOCK_EINT */
3336#define WM5100_ASRC1_LOCK_EINT_SHIFT 7 /* ASRC1_LOCK_EINT */
3337#define WM5100_ASRC1_LOCK_EINT_WIDTH 1 /* ASRC1_LOCK_EINT */
3338#define WM5100_FLL2_LOCK_EINT 0x0008 /* FLL2_LOCK_EINT */
3339#define WM5100_FLL2_LOCK_EINT_MASK 0x0008 /* FLL2_LOCK_EINT */
3340#define WM5100_FLL2_LOCK_EINT_SHIFT 3 /* FLL2_LOCK_EINT */
3341#define WM5100_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */
3342#define WM5100_FLL1_LOCK_EINT 0x0004 /* FLL1_LOCK_EINT */
3343#define WM5100_FLL1_LOCK_EINT_MASK 0x0004 /* FLL1_LOCK_EINT */
3344#define WM5100_FLL1_LOCK_EINT_SHIFT 2 /* FLL1_LOCK_EINT */
3345#define WM5100_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */
3346#define WM5100_CLKGEN_ERR_EINT 0x0002 /* CLKGEN_ERR_EINT */
3347#define WM5100_CLKGEN_ERR_EINT_MASK 0x0002 /* CLKGEN_ERR_EINT */
3348#define WM5100_CLKGEN_ERR_EINT_SHIFT 1 /* CLKGEN_ERR_EINT */
3349#define WM5100_CLKGEN_ERR_EINT_WIDTH 1 /* CLKGEN_ERR_EINT */
3350#define WM5100_CLKGEN_ERR_ASYNC_EINT 0x0001 /* CLKGEN_ERR_ASYNC_EINT */
3351#define WM5100_CLKGEN_ERR_ASYNC_EINT_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT */
3352#define WM5100_CLKGEN_ERR_ASYNC_EINT_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT */
3353#define WM5100_CLKGEN_ERR_ASYNC_EINT_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT */
3354
3355/*
3356 * R3331 (0xD03) - Interrupt Status 4
3357 */
3358#define WM5100_AIF3_ERR_EINT 0x2000 /* AIF3_ERR_EINT */
3359#define WM5100_AIF3_ERR_EINT_MASK 0x2000 /* AIF3_ERR_EINT */
3360#define WM5100_AIF3_ERR_EINT_SHIFT 13 /* AIF3_ERR_EINT */
3361#define WM5100_AIF3_ERR_EINT_WIDTH 1 /* AIF3_ERR_EINT */
3362#define WM5100_AIF2_ERR_EINT 0x1000 /* AIF2_ERR_EINT */
3363#define WM5100_AIF2_ERR_EINT_MASK 0x1000 /* AIF2_ERR_EINT */
3364#define WM5100_AIF2_ERR_EINT_SHIFT 12 /* AIF2_ERR_EINT */
3365#define WM5100_AIF2_ERR_EINT_WIDTH 1 /* AIF2_ERR_EINT */
3366#define WM5100_AIF1_ERR_EINT 0x0800 /* AIF1_ERR_EINT */
3367#define WM5100_AIF1_ERR_EINT_MASK 0x0800 /* AIF1_ERR_EINT */
3368#define WM5100_AIF1_ERR_EINT_SHIFT 11 /* AIF1_ERR_EINT */
3369#define WM5100_AIF1_ERR_EINT_WIDTH 1 /* AIF1_ERR_EINT */
3370#define WM5100_CTRLIF_ERR_EINT 0x0400 /* CTRLIF_ERR_EINT */
3371#define WM5100_CTRLIF_ERR_EINT_MASK 0x0400 /* CTRLIF_ERR_EINT */
3372#define WM5100_CTRLIF_ERR_EINT_SHIFT 10 /* CTRLIF_ERR_EINT */
3373#define WM5100_CTRLIF_ERR_EINT_WIDTH 1 /* CTRLIF_ERR_EINT */
3374#define WM5100_ISRC2_UNDERCLOCKED_EINT 0x0200 /* ISRC2_UNDERCLOCKED_EINT */
3375#define WM5100_ISRC2_UNDERCLOCKED_EINT_MASK 0x0200 /* ISRC2_UNDERCLOCKED_EINT */
3376#define WM5100_ISRC2_UNDERCLOCKED_EINT_SHIFT 9 /* ISRC2_UNDERCLOCKED_EINT */
3377#define WM5100_ISRC2_UNDERCLOCKED_EINT_WIDTH 1 /* ISRC2_UNDERCLOCKED_EINT */
3378#define WM5100_ISRC1_UNDERCLOCKED_EINT 0x0100 /* ISRC1_UNDERCLOCKED_EINT */
3379#define WM5100_ISRC1_UNDERCLOCKED_EINT_MASK 0x0100 /* ISRC1_UNDERCLOCKED_EINT */
3380#define WM5100_ISRC1_UNDERCLOCKED_EINT_SHIFT 8 /* ISRC1_UNDERCLOCKED_EINT */
3381#define WM5100_ISRC1_UNDERCLOCKED_EINT_WIDTH 1 /* ISRC1_UNDERCLOCKED_EINT */
3382#define WM5100_FX_UNDERCLOCKED_EINT 0x0080 /* FX_UNDERCLOCKED_EINT */
3383#define WM5100_FX_UNDERCLOCKED_EINT_MASK 0x0080 /* FX_UNDERCLOCKED_EINT */
3384#define WM5100_FX_UNDERCLOCKED_EINT_SHIFT 7 /* FX_UNDERCLOCKED_EINT */
3385#define WM5100_FX_UNDERCLOCKED_EINT_WIDTH 1 /* FX_UNDERCLOCKED_EINT */
3386#define WM5100_AIF3_UNDERCLOCKED_EINT 0x0040 /* AIF3_UNDERCLOCKED_EINT */
3387#define WM5100_AIF3_UNDERCLOCKED_EINT_MASK 0x0040 /* AIF3_UNDERCLOCKED_EINT */
3388#define WM5100_AIF3_UNDERCLOCKED_EINT_SHIFT 6 /* AIF3_UNDERCLOCKED_EINT */
3389#define WM5100_AIF3_UNDERCLOCKED_EINT_WIDTH 1 /* AIF3_UNDERCLOCKED_EINT */
3390#define WM5100_AIF2_UNDERCLOCKED_EINT 0x0020 /* AIF2_UNDERCLOCKED_EINT */
3391#define WM5100_AIF2_UNDERCLOCKED_EINT_MASK 0x0020 /* AIF2_UNDERCLOCKED_EINT */
3392#define WM5100_AIF2_UNDERCLOCKED_EINT_SHIFT 5 /* AIF2_UNDERCLOCKED_EINT */
3393#define WM5100_AIF2_UNDERCLOCKED_EINT_WIDTH 1 /* AIF2_UNDERCLOCKED_EINT */
3394#define WM5100_AIF1_UNDERCLOCKED_EINT 0x0010 /* AIF1_UNDERCLOCKED_EINT */
3395#define WM5100_AIF1_UNDERCLOCKED_EINT_MASK 0x0010 /* AIF1_UNDERCLOCKED_EINT */
3396#define WM5100_AIF1_UNDERCLOCKED_EINT_SHIFT 4 /* AIF1_UNDERCLOCKED_EINT */
3397#define WM5100_AIF1_UNDERCLOCKED_EINT_WIDTH 1 /* AIF1_UNDERCLOCKED_EINT */
3398#define WM5100_ASRC_UNDERCLOCKED_EINT 0x0008 /* ASRC_UNDERCLOCKED_EINT */
3399#define WM5100_ASRC_UNDERCLOCKED_EINT_MASK 0x0008 /* ASRC_UNDERCLOCKED_EINT */
3400#define WM5100_ASRC_UNDERCLOCKED_EINT_SHIFT 3 /* ASRC_UNDERCLOCKED_EINT */
3401#define WM5100_ASRC_UNDERCLOCKED_EINT_WIDTH 1 /* ASRC_UNDERCLOCKED_EINT */
3402#define WM5100_DAC_UNDERCLOCKED_EINT 0x0004 /* DAC_UNDERCLOCKED_EINT */
3403#define WM5100_DAC_UNDERCLOCKED_EINT_MASK 0x0004 /* DAC_UNDERCLOCKED_EINT */
3404#define WM5100_DAC_UNDERCLOCKED_EINT_SHIFT 2 /* DAC_UNDERCLOCKED_EINT */
3405#define WM5100_DAC_UNDERCLOCKED_EINT_WIDTH 1 /* DAC_UNDERCLOCKED_EINT */
3406#define WM5100_ADC_UNDERCLOCKED_EINT 0x0002 /* ADC_UNDERCLOCKED_EINT */
3407#define WM5100_ADC_UNDERCLOCKED_EINT_MASK 0x0002 /* ADC_UNDERCLOCKED_EINT */
3408#define WM5100_ADC_UNDERCLOCKED_EINT_SHIFT 1 /* ADC_UNDERCLOCKED_EINT */
3409#define WM5100_ADC_UNDERCLOCKED_EINT_WIDTH 1 /* ADC_UNDERCLOCKED_EINT */
3410#define WM5100_MIXER_UNDERCLOCKED_EINT 0x0001 /* MIXER_UNDERCLOCKED_EINT */
3411#define WM5100_MIXER_UNDERCLOCKED_EINT_MASK 0x0001 /* MIXER_UNDERCLOCKED_EINT */
3412#define WM5100_MIXER_UNDERCLOCKED_EINT_SHIFT 0 /* MIXER_UNDERCLOCKED_EINT */
3413#define WM5100_MIXER_UNDERCLOCKED_EINT_WIDTH 1 /* MIXER_UNDERCLOCKED_EINT */
3414
3415/*
3416 * R3332 (0xD04) - Interrupt Raw Status 2
3417 */
3418#define WM5100_DSP_IRQ6_STS 0x0020 /* DSP_IRQ6_STS */
3419#define WM5100_DSP_IRQ6_STS_MASK 0x0020 /* DSP_IRQ6_STS */
3420#define WM5100_DSP_IRQ6_STS_SHIFT 5 /* DSP_IRQ6_STS */
3421#define WM5100_DSP_IRQ6_STS_WIDTH 1 /* DSP_IRQ6_STS */
3422#define WM5100_DSP_IRQ5_STS 0x0010 /* DSP_IRQ5_STS */
3423#define WM5100_DSP_IRQ5_STS_MASK 0x0010 /* DSP_IRQ5_STS */
3424#define WM5100_DSP_IRQ5_STS_SHIFT 4 /* DSP_IRQ5_STS */
3425#define WM5100_DSP_IRQ5_STS_WIDTH 1 /* DSP_IRQ5_STS */
3426#define WM5100_DSP_IRQ4_STS 0x0008 /* DSP_IRQ4_STS */
3427#define WM5100_DSP_IRQ4_STS_MASK 0x0008 /* DSP_IRQ4_STS */
3428#define WM5100_DSP_IRQ4_STS_SHIFT 3 /* DSP_IRQ4_STS */
3429#define WM5100_DSP_IRQ4_STS_WIDTH 1 /* DSP_IRQ4_STS */
3430#define WM5100_DSP_IRQ3_STS 0x0004 /* DSP_IRQ3_STS */
3431#define WM5100_DSP_IRQ3_STS_MASK 0x0004 /* DSP_IRQ3_STS */
3432#define WM5100_DSP_IRQ3_STS_SHIFT 2 /* DSP_IRQ3_STS */
3433#define WM5100_DSP_IRQ3_STS_WIDTH 1 /* DSP_IRQ3_STS */
3434#define WM5100_DSP_IRQ2_STS 0x0002 /* DSP_IRQ2_STS */
3435#define WM5100_DSP_IRQ2_STS_MASK 0x0002 /* DSP_IRQ2_STS */
3436#define WM5100_DSP_IRQ2_STS_SHIFT 1 /* DSP_IRQ2_STS */
3437#define WM5100_DSP_IRQ2_STS_WIDTH 1 /* DSP_IRQ2_STS */
3438#define WM5100_DSP_IRQ1_STS 0x0001 /* DSP_IRQ1_STS */
3439#define WM5100_DSP_IRQ1_STS_MASK 0x0001 /* DSP_IRQ1_STS */
3440#define WM5100_DSP_IRQ1_STS_SHIFT 0 /* DSP_IRQ1_STS */
3441#define WM5100_DSP_IRQ1_STS_WIDTH 1 /* DSP_IRQ1_STS */
3442
3443/*
3444 * R3333 (0xD05) - Interrupt Raw Status 3
3445 */
3446#define WM5100_SPK_SHUTDOWN_WARN_STS 0x8000 /* SPK_SHUTDOWN_WARN_STS */
3447#define WM5100_SPK_SHUTDOWN_WARN_STS_MASK 0x8000 /* SPK_SHUTDOWN_WARN_STS */
3448#define WM5100_SPK_SHUTDOWN_WARN_STS_SHIFT 15 /* SPK_SHUTDOWN_WARN_STS */
3449#define WM5100_SPK_SHUTDOWN_WARN_STS_WIDTH 1 /* SPK_SHUTDOWN_WARN_STS */
3450#define WM5100_SPK_SHUTDOWN_STS 0x4000 /* SPK_SHUTDOWN_STS */
3451#define WM5100_SPK_SHUTDOWN_STS_MASK 0x4000 /* SPK_SHUTDOWN_STS */
3452#define WM5100_SPK_SHUTDOWN_STS_SHIFT 14 /* SPK_SHUTDOWN_STS */
3453#define WM5100_SPK_SHUTDOWN_STS_WIDTH 1 /* SPK_SHUTDOWN_STS */
3454#define WM5100_HPDET_STS 0x2000 /* HPDET_STS */
3455#define WM5100_HPDET_STS_MASK 0x2000 /* HPDET_STS */
3456#define WM5100_HPDET_STS_SHIFT 13 /* HPDET_STS */
3457#define WM5100_HPDET_STS_WIDTH 1 /* HPDET_STS */
3458#define WM5100_DRC_SID_DET_STS 0x0200 /* DRC_SID_DET_STS */
3459#define WM5100_DRC_SID_DET_STS_MASK 0x0200 /* DRC_SID_DET_STS */
3460#define WM5100_DRC_SID_DET_STS_SHIFT 9 /* DRC_SID_DET_STS */
3461#define WM5100_DRC_SID_DET_STS_WIDTH 1 /* DRC_SID_DET_STS */
3462#define WM5100_ASRC2_LOCK_STS 0x0100 /* ASRC2_LOCK_STS */
3463#define WM5100_ASRC2_LOCK_STS_MASK 0x0100 /* ASRC2_LOCK_STS */
3464#define WM5100_ASRC2_LOCK_STS_SHIFT 8 /* ASRC2_LOCK_STS */
3465#define WM5100_ASRC2_LOCK_STS_WIDTH 1 /* ASRC2_LOCK_STS */
3466#define WM5100_ASRC1_LOCK_STS 0x0080 /* ASRC1_LOCK_STS */
3467#define WM5100_ASRC1_LOCK_STS_MASK 0x0080 /* ASRC1_LOCK_STS */
3468#define WM5100_ASRC1_LOCK_STS_SHIFT 7 /* ASRC1_LOCK_STS */
3469#define WM5100_ASRC1_LOCK_STS_WIDTH 1 /* ASRC1_LOCK_STS */
3470#define WM5100_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */
3471#define WM5100_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */
3472#define WM5100_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */
3473#define WM5100_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */
3474#define WM5100_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */
3475#define WM5100_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */
3476#define WM5100_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */
3477#define WM5100_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */
3478#define WM5100_CLKGEN_ERR_STS 0x0002 /* CLKGEN_ERR_STS */
3479#define WM5100_CLKGEN_ERR_STS_MASK 0x0002 /* CLKGEN_ERR_STS */
3480#define WM5100_CLKGEN_ERR_STS_SHIFT 1 /* CLKGEN_ERR_STS */
3481#define WM5100_CLKGEN_ERR_STS_WIDTH 1 /* CLKGEN_ERR_STS */
3482#define WM5100_CLKGEN_ERR_ASYNC_STS 0x0001 /* CLKGEN_ERR_ASYNC_STS */
3483#define WM5100_CLKGEN_ERR_ASYNC_STS_MASK 0x0001 /* CLKGEN_ERR_ASYNC_STS */
3484#define WM5100_CLKGEN_ERR_ASYNC_STS_SHIFT 0 /* CLKGEN_ERR_ASYNC_STS */
3485#define WM5100_CLKGEN_ERR_ASYNC_STS_WIDTH 1 /* CLKGEN_ERR_ASYNC_STS */
3486
3487/*
3488 * R3334 (0xD06) - Interrupt Raw Status 4
3489 */
3490#define WM5100_AIF3_ERR_STS 0x2000 /* AIF3_ERR_STS */
3491#define WM5100_AIF3_ERR_STS_MASK 0x2000 /* AIF3_ERR_STS */
3492#define WM5100_AIF3_ERR_STS_SHIFT 13 /* AIF3_ERR_STS */
3493#define WM5100_AIF3_ERR_STS_WIDTH 1 /* AIF3_ERR_STS */
3494#define WM5100_AIF2_ERR_STS 0x1000 /* AIF2_ERR_STS */
3495#define WM5100_AIF2_ERR_STS_MASK 0x1000 /* AIF2_ERR_STS */
3496#define WM5100_AIF2_ERR_STS_SHIFT 12 /* AIF2_ERR_STS */
3497#define WM5100_AIF2_ERR_STS_WIDTH 1 /* AIF2_ERR_STS */
3498#define WM5100_AIF1_ERR_STS 0x0800 /* AIF1_ERR_STS */
3499#define WM5100_AIF1_ERR_STS_MASK 0x0800 /* AIF1_ERR_STS */
3500#define WM5100_AIF1_ERR_STS_SHIFT 11 /* AIF1_ERR_STS */
3501#define WM5100_AIF1_ERR_STS_WIDTH 1 /* AIF1_ERR_STS */
3502#define WM5100_CTRLIF_ERR_STS 0x0400 /* CTRLIF_ERR_STS */
3503#define WM5100_CTRLIF_ERR_STS_MASK 0x0400 /* CTRLIF_ERR_STS */
3504#define WM5100_CTRLIF_ERR_STS_SHIFT 10 /* CTRLIF_ERR_STS */
3505#define WM5100_CTRLIF_ERR_STS_WIDTH 1 /* CTRLIF_ERR_STS */
3506#define WM5100_ISRC2_UNDERCLOCKED_STS 0x0200 /* ISRC2_UNDERCLOCKED_STS */
3507#define WM5100_ISRC2_UNDERCLOCKED_STS_MASK 0x0200 /* ISRC2_UNDERCLOCKED_STS */
3508#define WM5100_ISRC2_UNDERCLOCKED_STS_SHIFT 9 /* ISRC2_UNDERCLOCKED_STS */
3509#define WM5100_ISRC2_UNDERCLOCKED_STS_WIDTH 1 /* ISRC2_UNDERCLOCKED_STS */
3510#define WM5100_ISRC1_UNDERCLOCKED_STS 0x0100 /* ISRC1_UNDERCLOCKED_STS */
3511#define WM5100_ISRC1_UNDERCLOCKED_STS_MASK 0x0100 /* ISRC1_UNDERCLOCKED_STS */
3512#define WM5100_ISRC1_UNDERCLOCKED_STS_SHIFT 8 /* ISRC1_UNDERCLOCKED_STS */
3513#define WM5100_ISRC1_UNDERCLOCKED_STS_WIDTH 1 /* ISRC1_UNDERCLOCKED_STS */
3514#define WM5100_FX_UNDERCLOCKED_STS 0x0080 /* FX_UNDERCLOCKED_STS */
3515#define WM5100_FX_UNDERCLOCKED_STS_MASK 0x0080 /* FX_UNDERCLOCKED_STS */
3516#define WM5100_FX_UNDERCLOCKED_STS_SHIFT 7 /* FX_UNDERCLOCKED_STS */
3517#define WM5100_FX_UNDERCLOCKED_STS_WIDTH 1 /* FX_UNDERCLOCKED_STS */
3518#define WM5100_AIF3_UNDERCLOCKED_STS 0x0040 /* AIF3_UNDERCLOCKED_STS */
3519#define WM5100_AIF3_UNDERCLOCKED_STS_MASK 0x0040 /* AIF3_UNDERCLOCKED_STS */
3520#define WM5100_AIF3_UNDERCLOCKED_STS_SHIFT 6 /* AIF3_UNDERCLOCKED_STS */
3521#define WM5100_AIF3_UNDERCLOCKED_STS_WIDTH 1 /* AIF3_UNDERCLOCKED_STS */
3522#define WM5100_AIF2_UNDERCLOCKED_STS 0x0020 /* AIF2_UNDERCLOCKED_STS */
3523#define WM5100_AIF2_UNDERCLOCKED_STS_MASK 0x0020 /* AIF2_UNDERCLOCKED_STS */
3524#define WM5100_AIF2_UNDERCLOCKED_STS_SHIFT 5 /* AIF2_UNDERCLOCKED_STS */
3525#define WM5100_AIF2_UNDERCLOCKED_STS_WIDTH 1 /* AIF2_UNDERCLOCKED_STS */
3526#define WM5100_AIF1_UNDERCLOCKED_STS 0x0010 /* AIF1_UNDERCLOCKED_STS */
3527#define WM5100_AIF1_UNDERCLOCKED_STS_MASK 0x0010 /* AIF1_UNDERCLOCKED_STS */
3528#define WM5100_AIF1_UNDERCLOCKED_STS_SHIFT 4 /* AIF1_UNDERCLOCKED_STS */
3529#define WM5100_AIF1_UNDERCLOCKED_STS_WIDTH 1 /* AIF1_UNDERCLOCKED_STS */
3530#define WM5100_ASRC_UNDERCLOCKED_STS 0x0008 /* ASRC_UNDERCLOCKED_STS */
3531#define WM5100_ASRC_UNDERCLOCKED_STS_MASK 0x0008 /* ASRC_UNDERCLOCKED_STS */
3532#define WM5100_ASRC_UNDERCLOCKED_STS_SHIFT 3 /* ASRC_UNDERCLOCKED_STS */
3533#define WM5100_ASRC_UNDERCLOCKED_STS_WIDTH 1 /* ASRC_UNDERCLOCKED_STS */
3534#define WM5100_DAC_UNDERCLOCKED_STS 0x0004 /* DAC_UNDERCLOCKED_STS */
3535#define WM5100_DAC_UNDERCLOCKED_STS_MASK 0x0004 /* DAC_UNDERCLOCKED_STS */
3536#define WM5100_DAC_UNDERCLOCKED_STS_SHIFT 2 /* DAC_UNDERCLOCKED_STS */
3537#define WM5100_DAC_UNDERCLOCKED_STS_WIDTH 1 /* DAC_UNDERCLOCKED_STS */
3538#define WM5100_ADC_UNDERCLOCKED_STS 0x0002 /* ADC_UNDERCLOCKED_STS */
3539#define WM5100_ADC_UNDERCLOCKED_STS_MASK 0x0002 /* ADC_UNDERCLOCKED_STS */
3540#define WM5100_ADC_UNDERCLOCKED_STS_SHIFT 1 /* ADC_UNDERCLOCKED_STS */
3541#define WM5100_ADC_UNDERCLOCKED_STS_WIDTH 1 /* ADC_UNDERCLOCKED_STS */
3542#define WM5100_MIXER_UNDERCLOCKED_STS 0x0001 /* MIXER_UNDERCLOCKED_STS */
3543#define WM5100_MIXER_UNDERCLOCKED_STS_MASK 0x0001 /* MIXER_UNDERCLOCKED_STS */
3544#define WM5100_MIXER_UNDERCLOCKED_STS_SHIFT 0 /* MIXER_UNDERCLOCKED_STS */
3545#define WM5100_MIXER_UNDERCLOCKED_STS_WIDTH 1 /* MIXER_UNDERCLOCKED_STS */
3546
3547/*
3548 * R3335 (0xD07) - Interrupt Status 1 Mask
3549 */
3550#define WM5100_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */
3551#define WM5100_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */
3552#define WM5100_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */
3553#define WM5100_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */
3554#define WM5100_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
3555#define WM5100_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
3556#define WM5100_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */
3557#define WM5100_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
3558#define WM5100_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
3559#define WM5100_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
3560#define WM5100_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
3561#define WM5100_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
3562#define WM5100_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
3563#define WM5100_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
3564#define WM5100_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
3565#define WM5100_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
3566#define WM5100_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
3567#define WM5100_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
3568#define WM5100_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
3569#define WM5100_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
3570#define WM5100_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
3571#define WM5100_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
3572#define WM5100_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
3573#define WM5100_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
3574
3575/*
3576 * R3336 (0xD08) - Interrupt Status 2 Mask
3577 */
3578#define WM5100_IM_DSP_IRQ6_EINT 0x0020 /* IM_DSP_IRQ6_EINT */
3579#define WM5100_IM_DSP_IRQ6_EINT_MASK 0x0020 /* IM_DSP_IRQ6_EINT */
3580#define WM5100_IM_DSP_IRQ6_EINT_SHIFT 5 /* IM_DSP_IRQ6_EINT */
3581#define WM5100_IM_DSP_IRQ6_EINT_WIDTH 1 /* IM_DSP_IRQ6_EINT */
3582#define WM5100_IM_DSP_IRQ5_EINT 0x0010 /* IM_DSP_IRQ5_EINT */
3583#define WM5100_IM_DSP_IRQ5_EINT_MASK 0x0010 /* IM_DSP_IRQ5_EINT */
3584#define WM5100_IM_DSP_IRQ5_EINT_SHIFT 4 /* IM_DSP_IRQ5_EINT */
3585#define WM5100_IM_DSP_IRQ5_EINT_WIDTH 1 /* IM_DSP_IRQ5_EINT */
3586#define WM5100_IM_DSP_IRQ4_EINT 0x0008 /* IM_DSP_IRQ4_EINT */
3587#define WM5100_IM_DSP_IRQ4_EINT_MASK 0x0008 /* IM_DSP_IRQ4_EINT */
3588#define WM5100_IM_DSP_IRQ4_EINT_SHIFT 3 /* IM_DSP_IRQ4_EINT */
3589#define WM5100_IM_DSP_IRQ4_EINT_WIDTH 1 /* IM_DSP_IRQ4_EINT */
3590#define WM5100_IM_DSP_IRQ3_EINT 0x0004 /* IM_DSP_IRQ3_EINT */
3591#define WM5100_IM_DSP_IRQ3_EINT_MASK 0x0004 /* IM_DSP_IRQ3_EINT */
3592#define WM5100_IM_DSP_IRQ3_EINT_SHIFT 2 /* IM_DSP_IRQ3_EINT */
3593#define WM5100_IM_DSP_IRQ3_EINT_WIDTH 1 /* IM_DSP_IRQ3_EINT */
3594#define WM5100_IM_DSP_IRQ2_EINT 0x0002 /* IM_DSP_IRQ2_EINT */
3595#define WM5100_IM_DSP_IRQ2_EINT_MASK 0x0002 /* IM_DSP_IRQ2_EINT */
3596#define WM5100_IM_DSP_IRQ2_EINT_SHIFT 1 /* IM_DSP_IRQ2_EINT */
3597#define WM5100_IM_DSP_IRQ2_EINT_WIDTH 1 /* IM_DSP_IRQ2_EINT */
3598#define WM5100_IM_DSP_IRQ1_EINT 0x0001 /* IM_DSP_IRQ1_EINT */
3599#define WM5100_IM_DSP_IRQ1_EINT_MASK 0x0001 /* IM_DSP_IRQ1_EINT */
3600#define WM5100_IM_DSP_IRQ1_EINT_SHIFT 0 /* IM_DSP_IRQ1_EINT */
3601#define WM5100_IM_DSP_IRQ1_EINT_WIDTH 1 /* IM_DSP_IRQ1_EINT */
3602
3603/*
3604 * R3337 (0xD09) - Interrupt Status 3 Mask
3605 */
3606#define WM5100_IM_SPK_SHUTDOWN_WARN_EINT 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT */
3607#define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT */
3608#define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT */
3609#define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT */
3610#define WM5100_IM_SPK_SHUTDOWN_EINT 0x4000 /* IM_SPK_SHUTDOWN_EINT */
3611#define WM5100_IM_SPK_SHUTDOWN_EINT_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT */
3612#define WM5100_IM_SPK_SHUTDOWN_EINT_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT */
3613#define WM5100_IM_SPK_SHUTDOWN_EINT_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT */
3614#define WM5100_IM_HPDET_EINT 0x2000 /* IM_HPDET_EINT */
3615#define WM5100_IM_HPDET_EINT_MASK 0x2000 /* IM_HPDET_EINT */
3616#define WM5100_IM_HPDET_EINT_SHIFT 13 /* IM_HPDET_EINT */
3617#define WM5100_IM_HPDET_EINT_WIDTH 1 /* IM_HPDET_EINT */
3618#define WM5100_IM_ACCDET_EINT 0x1000 /* IM_ACCDET_EINT */
3619#define WM5100_IM_ACCDET_EINT_MASK 0x1000 /* IM_ACCDET_EINT */
3620#define WM5100_IM_ACCDET_EINT_SHIFT 12 /* IM_ACCDET_EINT */
3621#define WM5100_IM_ACCDET_EINT_WIDTH 1 /* IM_ACCDET_EINT */
3622#define WM5100_IM_DRC_SIG_DET_EINT 0x0200 /* IM_DRC_SIG_DET_EINT */
3623#define WM5100_IM_DRC_SIG_DET_EINT_MASK 0x0200 /* IM_DRC_SIG_DET_EINT */
3624#define WM5100_IM_DRC_SIG_DET_EINT_SHIFT 9 /* IM_DRC_SIG_DET_EINT */
3625#define WM5100_IM_DRC_SIG_DET_EINT_WIDTH 1 /* IM_DRC_SIG_DET_EINT */
3626#define WM5100_IM_ASRC2_LOCK_EINT 0x0100 /* IM_ASRC2_LOCK_EINT */
3627#define WM5100_IM_ASRC2_LOCK_EINT_MASK 0x0100 /* IM_ASRC2_LOCK_EINT */
3628#define WM5100_IM_ASRC2_LOCK_EINT_SHIFT 8 /* IM_ASRC2_LOCK_EINT */
3629#define WM5100_IM_ASRC2_LOCK_EINT_WIDTH 1 /* IM_ASRC2_LOCK_EINT */
3630#define WM5100_IM_ASRC1_LOCK_EINT 0x0080 /* IM_ASRC1_LOCK_EINT */
3631#define WM5100_IM_ASRC1_LOCK_EINT_MASK 0x0080 /* IM_ASRC1_LOCK_EINT */
3632#define WM5100_IM_ASRC1_LOCK_EINT_SHIFT 7 /* IM_ASRC1_LOCK_EINT */
3633#define WM5100_IM_ASRC1_LOCK_EINT_WIDTH 1 /* IM_ASRC1_LOCK_EINT */
3634#define WM5100_IM_FLL2_LOCK_EINT 0x0008 /* IM_FLL2_LOCK_EINT */
3635#define WM5100_IM_FLL2_LOCK_EINT_MASK 0x0008 /* IM_FLL2_LOCK_EINT */
3636#define WM5100_IM_FLL2_LOCK_EINT_SHIFT 3 /* IM_FLL2_LOCK_EINT */
3637#define WM5100_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */
3638#define WM5100_IM_FLL1_LOCK_EINT 0x0004 /* IM_FLL1_LOCK_EINT */
3639#define WM5100_IM_FLL1_LOCK_EINT_MASK 0x0004 /* IM_FLL1_LOCK_EINT */
3640#define WM5100_IM_FLL1_LOCK_EINT_SHIFT 2 /* IM_FLL1_LOCK_EINT */
3641#define WM5100_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */
3642#define WM5100_IM_CLKGEN_ERR_EINT 0x0002 /* IM_CLKGEN_ERR_EINT */
3643#define WM5100_IM_CLKGEN_ERR_EINT_MASK 0x0002 /* IM_CLKGEN_ERR_EINT */
3644#define WM5100_IM_CLKGEN_ERR_EINT_SHIFT 1 /* IM_CLKGEN_ERR_EINT */
3645#define WM5100_IM_CLKGEN_ERR_EINT_WIDTH 1 /* IM_CLKGEN_ERR_EINT */
3646#define WM5100_IM_CLKGEN_ERR_ASYNC_EINT 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT */
3647#define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT */
3648#define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT */
3649#define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT */
3650
3651/*
3652 * R3338 (0xD0A) - Interrupt Status 4 Mask
3653 */
3654#define WM5100_IM_AIF3_ERR_EINT 0x2000 /* IM_AIF3_ERR_EINT */
3655#define WM5100_IM_AIF3_ERR_EINT_MASK 0x2000 /* IM_AIF3_ERR_EINT */
3656#define WM5100_IM_AIF3_ERR_EINT_SHIFT 13 /* IM_AIF3_ERR_EINT */
3657#define WM5100_IM_AIF3_ERR_EINT_WIDTH 1 /* IM_AIF3_ERR_EINT */
3658#define WM5100_IM_AIF2_ERR_EINT 0x1000 /* IM_AIF2_ERR_EINT */
3659#define WM5100_IM_AIF2_ERR_EINT_MASK 0x1000 /* IM_AIF2_ERR_EINT */
3660#define WM5100_IM_AIF2_ERR_EINT_SHIFT 12 /* IM_AIF2_ERR_EINT */
3661#define WM5100_IM_AIF2_ERR_EINT_WIDTH 1 /* IM_AIF2_ERR_EINT */
3662#define WM5100_IM_AIF1_ERR_EINT 0x0800 /* IM_AIF1_ERR_EINT */
3663#define WM5100_IM_AIF1_ERR_EINT_MASK 0x0800 /* IM_AIF1_ERR_EINT */
3664#define WM5100_IM_AIF1_ERR_EINT_SHIFT 11 /* IM_AIF1_ERR_EINT */
3665#define WM5100_IM_AIF1_ERR_EINT_WIDTH 1 /* IM_AIF1_ERR_EINT */
3666#define WM5100_IM_CTRLIF_ERR_EINT 0x0400 /* IM_CTRLIF_ERR_EINT */
3667#define WM5100_IM_CTRLIF_ERR_EINT_MASK 0x0400 /* IM_CTRLIF_ERR_EINT */
3668#define WM5100_IM_CTRLIF_ERR_EINT_SHIFT 10 /* IM_CTRLIF_ERR_EINT */
3669#define WM5100_IM_CTRLIF_ERR_EINT_WIDTH 1 /* IM_CTRLIF_ERR_EINT */
3670#define WM5100_IM_ISRC2_UNDERCLOCKED_EINT 0x0200 /* IM_ISRC2_UNDERCLOCKED_EINT */
3671#define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_MASK 0x0200 /* IM_ISRC2_UNDERCLOCKED_EINT */
3672#define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_SHIFT 9 /* IM_ISRC2_UNDERCLOCKED_EINT */
3673#define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ISRC2_UNDERCLOCKED_EINT */
3674#define WM5100_IM_ISRC1_UNDERCLOCKED_EINT 0x0100 /* IM_ISRC1_UNDERCLOCKED_EINT */
3675#define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_MASK 0x0100 /* IM_ISRC1_UNDERCLOCKED_EINT */
3676#define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_SHIFT 8 /* IM_ISRC1_UNDERCLOCKED_EINT */
3677#define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ISRC1_UNDERCLOCKED_EINT */
3678#define WM5100_IM_FX_UNDERCLOCKED_EINT 0x0080 /* IM_FX_UNDERCLOCKED_EINT */
3679#define WM5100_IM_FX_UNDERCLOCKED_EINT_MASK 0x0080 /* IM_FX_UNDERCLOCKED_EINT */
3680#define WM5100_IM_FX_UNDERCLOCKED_EINT_SHIFT 7 /* IM_FX_UNDERCLOCKED_EINT */
3681#define WM5100_IM_FX_UNDERCLOCKED_EINT_WIDTH 1 /* IM_FX_UNDERCLOCKED_EINT */
3682#define WM5100_IM_AIF3_UNDERCLOCKED_EINT 0x0040 /* IM_AIF3_UNDERCLOCKED_EINT */
3683#define WM5100_IM_AIF3_UNDERCLOCKED_EINT_MASK 0x0040 /* IM_AIF3_UNDERCLOCKED_EINT */
3684#define WM5100_IM_AIF3_UNDERCLOCKED_EINT_SHIFT 6 /* IM_AIF3_UNDERCLOCKED_EINT */
3685#define WM5100_IM_AIF3_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF3_UNDERCLOCKED_EINT */
3686#define WM5100_IM_AIF2_UNDERCLOCKED_EINT 0x0020 /* IM_AIF2_UNDERCLOCKED_EINT */
3687#define WM5100_IM_AIF2_UNDERCLOCKED_EINT_MASK 0x0020 /* IM_AIF2_UNDERCLOCKED_EINT */
3688#define WM5100_IM_AIF2_UNDERCLOCKED_EINT_SHIFT 5 /* IM_AIF2_UNDERCLOCKED_EINT */
3689#define WM5100_IM_AIF2_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF2_UNDERCLOCKED_EINT */
3690#define WM5100_IM_AIF1_UNDERCLOCKED_EINT 0x0010 /* IM_AIF1_UNDERCLOCKED_EINT */
3691#define WM5100_IM_AIF1_UNDERCLOCKED_EINT_MASK 0x0010 /* IM_AIF1_UNDERCLOCKED_EINT */
3692#define WM5100_IM_AIF1_UNDERCLOCKED_EINT_SHIFT 4 /* IM_AIF1_UNDERCLOCKED_EINT */
3693#define WM5100_IM_AIF1_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF1_UNDERCLOCKED_EINT */
3694#define WM5100_IM_ASRC_UNDERCLOCKED_EINT 0x0008 /* IM_ASRC_UNDERCLOCKED_EINT */
3695#define WM5100_IM_ASRC_UNDERCLOCKED_EINT_MASK 0x0008 /* IM_ASRC_UNDERCLOCKED_EINT */
3696#define WM5100_IM_ASRC_UNDERCLOCKED_EINT_SHIFT 3 /* IM_ASRC_UNDERCLOCKED_EINT */
3697#define WM5100_IM_ASRC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ASRC_UNDERCLOCKED_EINT */
3698#define WM5100_IM_DAC_UNDERCLOCKED_EINT 0x0004 /* IM_DAC_UNDERCLOCKED_EINT */
3699#define WM5100_IM_DAC_UNDERCLOCKED_EINT_MASK 0x0004 /* IM_DAC_UNDERCLOCKED_EINT */
3700#define WM5100_IM_DAC_UNDERCLOCKED_EINT_SHIFT 2 /* IM_DAC_UNDERCLOCKED_EINT */
3701#define WM5100_IM_DAC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_DAC_UNDERCLOCKED_EINT */
3702#define WM5100_IM_ADC_UNDERCLOCKED_EINT 0x0002 /* IM_ADC_UNDERCLOCKED_EINT */
3703#define WM5100_IM_ADC_UNDERCLOCKED_EINT_MASK 0x0002 /* IM_ADC_UNDERCLOCKED_EINT */
3704#define WM5100_IM_ADC_UNDERCLOCKED_EINT_SHIFT 1 /* IM_ADC_UNDERCLOCKED_EINT */
3705#define WM5100_IM_ADC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ADC_UNDERCLOCKED_EINT */
3706#define WM5100_IM_MIXER_UNDERCLOCKED_EINT 0x0001 /* IM_MIXER_UNDERCLOCKED_EINT */
3707#define WM5100_IM_MIXER_UNDERCLOCKED_EINT_MASK 0x0001 /* IM_MIXER_UNDERCLOCKED_EINT */
3708#define WM5100_IM_MIXER_UNDERCLOCKED_EINT_SHIFT 0 /* IM_MIXER_UNDERCLOCKED_EINT */
3709#define WM5100_IM_MIXER_UNDERCLOCKED_EINT_WIDTH 1 /* IM_MIXER_UNDERCLOCKED_EINT */
3710
3711/*
3712 * R3359 (0xD1F) - Interrupt Control
3713 */
3714#define WM5100_IM_IRQ 0x0001 /* IM_IRQ */
3715#define WM5100_IM_IRQ_MASK 0x0001 /* IM_IRQ */
3716#define WM5100_IM_IRQ_SHIFT 0 /* IM_IRQ */
3717#define WM5100_IM_IRQ_WIDTH 1 /* IM_IRQ */
3718
3719/*
3720 * R3360 (0xD20) - IRQ Debounce 1
3721 */
3722#define WM5100_SPK_SHUTDOWN_WARN_DB 0x0200 /* SPK_SHUTDOWN_WARN_DB */
3723#define WM5100_SPK_SHUTDOWN_WARN_DB_MASK 0x0200 /* SPK_SHUTDOWN_WARN_DB */
3724#define WM5100_SPK_SHUTDOWN_WARN_DB_SHIFT 9 /* SPK_SHUTDOWN_WARN_DB */
3725#define WM5100_SPK_SHUTDOWN_WARN_DB_WIDTH 1 /* SPK_SHUTDOWN_WARN_DB */
3726#define WM5100_SPK_SHUTDOWN_DB 0x0100 /* SPK_SHUTDOWN_DB */
3727#define WM5100_SPK_SHUTDOWN_DB_MASK 0x0100 /* SPK_SHUTDOWN_DB */
3728#define WM5100_SPK_SHUTDOWN_DB_SHIFT 8 /* SPK_SHUTDOWN_DB */
3729#define WM5100_SPK_SHUTDOWN_DB_WIDTH 1 /* SPK_SHUTDOWN_DB */
3730#define WM5100_FLL1_LOCK_IRQ_DB 0x0008 /* FLL1_LOCK_IRQ_DB */
3731#define WM5100_FLL1_LOCK_IRQ_DB_MASK 0x0008 /* FLL1_LOCK_IRQ_DB */
3732#define WM5100_FLL1_LOCK_IRQ_DB_SHIFT 3 /* FLL1_LOCK_IRQ_DB */
3733#define WM5100_FLL1_LOCK_IRQ_DB_WIDTH 1 /* FLL1_LOCK_IRQ_DB */
3734#define WM5100_FLL2_LOCK_IRQ_DB 0x0004 /* FLL2_LOCK_IRQ_DB */
3735#define WM5100_FLL2_LOCK_IRQ_DB_MASK 0x0004 /* FLL2_LOCK_IRQ_DB */
3736#define WM5100_FLL2_LOCK_IRQ_DB_SHIFT 2 /* FLL2_LOCK_IRQ_DB */
3737#define WM5100_FLL2_LOCK_IRQ_DB_WIDTH 1 /* FLL2_LOCK_IRQ_DB */
3738#define WM5100_CLKGEN_ERR_IRQ_DB 0x0002 /* CLKGEN_ERR_IRQ_DB */
3739#define WM5100_CLKGEN_ERR_IRQ_DB_MASK 0x0002 /* CLKGEN_ERR_IRQ_DB */
3740#define WM5100_CLKGEN_ERR_IRQ_DB_SHIFT 1 /* CLKGEN_ERR_IRQ_DB */
3741#define WM5100_CLKGEN_ERR_IRQ_DB_WIDTH 1 /* CLKGEN_ERR_IRQ_DB */
3742#define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB 0x0001 /* CLKGEN_ERR_ASYNC_IRQ_DB */
3743#define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_MASK 0x0001 /* CLKGEN_ERR_ASYNC_IRQ_DB */
3744#define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_SHIFT 0 /* CLKGEN_ERR_ASYNC_IRQ_DB */
3745#define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_WIDTH 1 /* CLKGEN_ERR_ASYNC_IRQ_DB */
3746
3747/*
3748 * R3361 (0xD21) - IRQ Debounce 2
3749 */
3750#define WM5100_AIF_ERR_DB 0x0001 /* AIF_ERR_DB */
3751#define WM5100_AIF_ERR_DB_MASK 0x0001 /* AIF_ERR_DB */
3752#define WM5100_AIF_ERR_DB_SHIFT 0 /* AIF_ERR_DB */
3753#define WM5100_AIF_ERR_DB_WIDTH 1 /* AIF_ERR_DB */
3754
3755/*
3756 * R3584 (0xE00) - FX_Ctrl
3757 */
3758#define WM5100_FX_STS_MASK 0xFFC0 /* FX_STS - [15:6] */
3759#define WM5100_FX_STS_SHIFT 6 /* FX_STS - [15:6] */
3760#define WM5100_FX_STS_WIDTH 10 /* FX_STS - [15:6] */
3761#define WM5100_FX_RATE_MASK 0x0003 /* FX_RATE - [1:0] */
3762#define WM5100_FX_RATE_SHIFT 0 /* FX_RATE - [1:0] */
3763#define WM5100_FX_RATE_WIDTH 2 /* FX_RATE - [1:0] */
3764
3765/*
3766 * R3600 (0xE10) - EQ1_1
3767 */
3768#define WM5100_EQ1_B1_GAIN_MASK 0xF800 /* EQ1_B1_GAIN - [15:11] */
3769#define WM5100_EQ1_B1_GAIN_SHIFT 11 /* EQ1_B1_GAIN - [15:11] */
3770#define WM5100_EQ1_B1_GAIN_WIDTH 5 /* EQ1_B1_GAIN - [15:11] */
3771#define WM5100_EQ1_B2_GAIN_MASK 0x07C0 /* EQ1_B2_GAIN - [10:6] */
3772#define WM5100_EQ1_B2_GAIN_SHIFT 6 /* EQ1_B2_GAIN - [10:6] */
3773#define WM5100_EQ1_B2_GAIN_WIDTH 5 /* EQ1_B2_GAIN - [10:6] */
3774#define WM5100_EQ1_B3_GAIN_MASK 0x003E /* EQ1_B3_GAIN - [5:1] */
3775#define WM5100_EQ1_B3_GAIN_SHIFT 1 /* EQ1_B3_GAIN - [5:1] */
3776#define WM5100_EQ1_B3_GAIN_WIDTH 5 /* EQ1_B3_GAIN - [5:1] */
3777#define WM5100_EQ1_ENA 0x0001 /* EQ1_ENA */
3778#define WM5100_EQ1_ENA_MASK 0x0001 /* EQ1_ENA */
3779#define WM5100_EQ1_ENA_SHIFT 0 /* EQ1_ENA */
3780#define WM5100_EQ1_ENA_WIDTH 1 /* EQ1_ENA */
3781
3782/*
3783 * R3601 (0xE11) - EQ1_2
3784 */
3785#define WM5100_EQ1_B4_GAIN_MASK 0xF800 /* EQ1_B4_GAIN - [15:11] */
3786#define WM5100_EQ1_B4_GAIN_SHIFT 11 /* EQ1_B4_GAIN - [15:11] */
3787#define WM5100_EQ1_B4_GAIN_WIDTH 5 /* EQ1_B4_GAIN - [15:11] */
3788#define WM5100_EQ1_B5_GAIN_MASK 0x07C0 /* EQ1_B5_GAIN - [10:6] */
3789#define WM5100_EQ1_B5_GAIN_SHIFT 6 /* EQ1_B5_GAIN - [10:6] */
3790#define WM5100_EQ1_B5_GAIN_WIDTH 5 /* EQ1_B5_GAIN - [10:6] */
3791
3792/*
3793 * R3602 (0xE12) - EQ1_3
3794 */
3795#define WM5100_EQ1_B1_A_MASK 0xFFFF /* EQ1_B1_A - [15:0] */
3796#define WM5100_EQ1_B1_A_SHIFT 0 /* EQ1_B1_A - [15:0] */
3797#define WM5100_EQ1_B1_A_WIDTH 16 /* EQ1_B1_A - [15:0] */
3798
3799/*
3800 * R3603 (0xE13) - EQ1_4
3801 */
3802#define WM5100_EQ1_B1_B_MASK 0xFFFF /* EQ1_B1_B - [15:0] */
3803#define WM5100_EQ1_B1_B_SHIFT 0 /* EQ1_B1_B - [15:0] */
3804#define WM5100_EQ1_B1_B_WIDTH 16 /* EQ1_B1_B - [15:0] */
3805
3806/*
3807 * R3604 (0xE14) - EQ1_5
3808 */
3809#define WM5100_EQ1_B1_PG_MASK 0xFFFF /* EQ1_B1_PG - [15:0] */
3810#define WM5100_EQ1_B1_PG_SHIFT 0 /* EQ1_B1_PG - [15:0] */
3811#define WM5100_EQ1_B1_PG_WIDTH 16 /* EQ1_B1_PG - [15:0] */
3812
3813/*
3814 * R3605 (0xE15) - EQ1_6
3815 */
3816#define WM5100_EQ1_B2_A_MASK 0xFFFF /* EQ1_B2_A - [15:0] */
3817#define WM5100_EQ1_B2_A_SHIFT 0 /* EQ1_B2_A - [15:0] */
3818#define WM5100_EQ1_B2_A_WIDTH 16 /* EQ1_B2_A - [15:0] */
3819
3820/*
3821 * R3606 (0xE16) - EQ1_7
3822 */
3823#define WM5100_EQ1_B2_B_MASK 0xFFFF /* EQ1_B2_B - [15:0] */
3824#define WM5100_EQ1_B2_B_SHIFT 0 /* EQ1_B2_B - [15:0] */
3825#define WM5100_EQ1_B2_B_WIDTH 16 /* EQ1_B2_B - [15:0] */
3826
3827/*
3828 * R3607 (0xE17) - EQ1_8
3829 */
3830#define WM5100_EQ1_B2_C_MASK 0xFFFF /* EQ1_B2_C - [15:0] */
3831#define WM5100_EQ1_B2_C_SHIFT 0 /* EQ1_B2_C - [15:0] */
3832#define WM5100_EQ1_B2_C_WIDTH 16 /* EQ1_B2_C - [15:0] */
3833
3834/*
3835 * R3608 (0xE18) - EQ1_9
3836 */
3837#define WM5100_EQ1_B2_PG_MASK 0xFFFF /* EQ1_B2_PG - [15:0] */
3838#define WM5100_EQ1_B2_PG_SHIFT 0 /* EQ1_B2_PG - [15:0] */
3839#define WM5100_EQ1_B2_PG_WIDTH 16 /* EQ1_B2_PG - [15:0] */
3840
3841/*
3842 * R3609 (0xE19) - EQ1_10
3843 */
3844#define WM5100_EQ1_B3_A_MASK 0xFFFF /* EQ1_B3_A - [15:0] */
3845#define WM5100_EQ1_B3_A_SHIFT 0 /* EQ1_B3_A - [15:0] */
3846#define WM5100_EQ1_B3_A_WIDTH 16 /* EQ1_B3_A - [15:0] */
3847
3848/*
3849 * R3610 (0xE1A) - EQ1_11
3850 */
3851#define WM5100_EQ1_B3_B_MASK 0xFFFF /* EQ1_B3_B - [15:0] */
3852#define WM5100_EQ1_B3_B_SHIFT 0 /* EQ1_B3_B - [15:0] */
3853#define WM5100_EQ1_B3_B_WIDTH 16 /* EQ1_B3_B - [15:0] */
3854
3855/*
3856 * R3611 (0xE1B) - EQ1_12
3857 */
3858#define WM5100_EQ1_B3_C_MASK 0xFFFF /* EQ1_B3_C - [15:0] */
3859#define WM5100_EQ1_B3_C_SHIFT 0 /* EQ1_B3_C - [15:0] */
3860#define WM5100_EQ1_B3_C_WIDTH 16 /* EQ1_B3_C - [15:0] */
3861
3862/*
3863 * R3612 (0xE1C) - EQ1_13
3864 */
3865#define WM5100_EQ1_B3_PG_MASK 0xFFFF /* EQ1_B3_PG - [15:0] */
3866#define WM5100_EQ1_B3_PG_SHIFT 0 /* EQ1_B3_PG - [15:0] */
3867#define WM5100_EQ1_B3_PG_WIDTH 16 /* EQ1_B3_PG - [15:0] */
3868
3869/*
3870 * R3613 (0xE1D) - EQ1_14
3871 */
3872#define WM5100_EQ1_B4_A_MASK 0xFFFF /* EQ1_B4_A - [15:0] */
3873#define WM5100_EQ1_B4_A_SHIFT 0 /* EQ1_B4_A - [15:0] */
3874#define WM5100_EQ1_B4_A_WIDTH 16 /* EQ1_B4_A - [15:0] */
3875
3876/*
3877 * R3614 (0xE1E) - EQ1_15
3878 */
3879#define WM5100_EQ1_B4_B_MASK 0xFFFF /* EQ1_B4_B - [15:0] */
3880#define WM5100_EQ1_B4_B_SHIFT 0 /* EQ1_B4_B - [15:0] */
3881#define WM5100_EQ1_B4_B_WIDTH 16 /* EQ1_B4_B - [15:0] */
3882
3883/*
3884 * R3615 (0xE1F) - EQ1_16
3885 */
3886#define WM5100_EQ1_B4_C_MASK 0xFFFF /* EQ1_B4_C - [15:0] */
3887#define WM5100_EQ1_B4_C_SHIFT 0 /* EQ1_B4_C - [15:0] */
3888#define WM5100_EQ1_B4_C_WIDTH 16 /* EQ1_B4_C - [15:0] */
3889
3890/*
3891 * R3616 (0xE20) - EQ1_17
3892 */
3893#define WM5100_EQ1_B4_PG_MASK 0xFFFF /* EQ1_B4_PG - [15:0] */
3894#define WM5100_EQ1_B4_PG_SHIFT 0 /* EQ1_B4_PG - [15:0] */
3895#define WM5100_EQ1_B4_PG_WIDTH 16 /* EQ1_B4_PG - [15:0] */
3896
3897/*
3898 * R3617 (0xE21) - EQ1_18
3899 */
3900#define WM5100_EQ1_B5_A_MASK 0xFFFF /* EQ1_B5_A - [15:0] */
3901#define WM5100_EQ1_B5_A_SHIFT 0 /* EQ1_B5_A - [15:0] */
3902#define WM5100_EQ1_B5_A_WIDTH 16 /* EQ1_B5_A - [15:0] */
3903
3904/*
3905 * R3618 (0xE22) - EQ1_19
3906 */
3907#define WM5100_EQ1_B5_B_MASK 0xFFFF /* EQ1_B5_B - [15:0] */
3908#define WM5100_EQ1_B5_B_SHIFT 0 /* EQ1_B5_B - [15:0] */
3909#define WM5100_EQ1_B5_B_WIDTH 16 /* EQ1_B5_B - [15:0] */
3910
3911/*
3912 * R3619 (0xE23) - EQ1_20
3913 */
3914#define WM5100_EQ1_B5_PG_MASK 0xFFFF /* EQ1_B5_PG - [15:0] */
3915#define WM5100_EQ1_B5_PG_SHIFT 0 /* EQ1_B5_PG - [15:0] */
3916#define WM5100_EQ1_B5_PG_WIDTH 16 /* EQ1_B5_PG - [15:0] */
3917
3918/*
3919 * R3622 (0xE26) - EQ2_1
3920 */
3921#define WM5100_EQ2_B1_GAIN_MASK 0xF800 /* EQ2_B1_GAIN - [15:11] */
3922#define WM5100_EQ2_B1_GAIN_SHIFT 11 /* EQ2_B1_GAIN - [15:11] */
3923#define WM5100_EQ2_B1_GAIN_WIDTH 5 /* EQ2_B1_GAIN - [15:11] */
3924#define WM5100_EQ2_B2_GAIN_MASK 0x07C0 /* EQ2_B2_GAIN - [10:6] */
3925#define WM5100_EQ2_B2_GAIN_SHIFT 6 /* EQ2_B2_GAIN - [10:6] */
3926#define WM5100_EQ2_B2_GAIN_WIDTH 5 /* EQ2_B2_GAIN - [10:6] */
3927#define WM5100_EQ2_B3_GAIN_MASK 0x003E /* EQ2_B3_GAIN - [5:1] */
3928#define WM5100_EQ2_B3_GAIN_SHIFT 1 /* EQ2_B3_GAIN - [5:1] */
3929#define WM5100_EQ2_B3_GAIN_WIDTH 5 /* EQ2_B3_GAIN - [5:1] */
3930#define WM5100_EQ2_ENA 0x0001 /* EQ2_ENA */
3931#define WM5100_EQ2_ENA_MASK 0x0001 /* EQ2_ENA */
3932#define WM5100_EQ2_ENA_SHIFT 0 /* EQ2_ENA */
3933#define WM5100_EQ2_ENA_WIDTH 1 /* EQ2_ENA */
3934
3935/*
3936 * R3623 (0xE27) - EQ2_2
3937 */
3938#define WM5100_EQ2_B4_GAIN_MASK 0xF800 /* EQ2_B4_GAIN - [15:11] */
3939#define WM5100_EQ2_B4_GAIN_SHIFT 11 /* EQ2_B4_GAIN - [15:11] */
3940#define WM5100_EQ2_B4_GAIN_WIDTH 5 /* EQ2_B4_GAIN - [15:11] */
3941#define WM5100_EQ2_B5_GAIN_MASK 0x07C0 /* EQ2_B5_GAIN - [10:6] */
3942#define WM5100_EQ2_B5_GAIN_SHIFT 6 /* EQ2_B5_GAIN - [10:6] */
3943#define WM5100_EQ2_B5_GAIN_WIDTH 5 /* EQ2_B5_GAIN - [10:6] */
3944
3945/*
3946 * R3624 (0xE28) - EQ2_3
3947 */
3948#define WM5100_EQ2_B1_A_MASK 0xFFFF /* EQ2_B1_A - [15:0] */
3949#define WM5100_EQ2_B1_A_SHIFT 0 /* EQ2_B1_A - [15:0] */
3950#define WM5100_EQ2_B1_A_WIDTH 16 /* EQ2_B1_A - [15:0] */
3951
3952/*
3953 * R3625 (0xE29) - EQ2_4
3954 */
3955#define WM5100_EQ2_B1_B_MASK 0xFFFF /* EQ2_B1_B - [15:0] */
3956#define WM5100_EQ2_B1_B_SHIFT 0 /* EQ2_B1_B - [15:0] */
3957#define WM5100_EQ2_B1_B_WIDTH 16 /* EQ2_B1_B - [15:0] */
3958
3959/*
3960 * R3626 (0xE2A) - EQ2_5
3961 */
3962#define WM5100_EQ2_B1_PG_MASK 0xFFFF /* EQ2_B1_PG - [15:0] */
3963#define WM5100_EQ2_B1_PG_SHIFT 0 /* EQ2_B1_PG - [15:0] */
3964#define WM5100_EQ2_B1_PG_WIDTH 16 /* EQ2_B1_PG - [15:0] */
3965
3966/*
3967 * R3627 (0xE2B) - EQ2_6
3968 */
3969#define WM5100_EQ2_B2_A_MASK 0xFFFF /* EQ2_B2_A - [15:0] */
3970#define WM5100_EQ2_B2_A_SHIFT 0 /* EQ2_B2_A - [15:0] */
3971#define WM5100_EQ2_B2_A_WIDTH 16 /* EQ2_B2_A - [15:0] */
3972
3973/*
3974 * R3628 (0xE2C) - EQ2_7
3975 */
3976#define WM5100_EQ2_B2_B_MASK 0xFFFF /* EQ2_B2_B - [15:0] */
3977#define WM5100_EQ2_B2_B_SHIFT 0 /* EQ2_B2_B - [15:0] */
3978#define WM5100_EQ2_B2_B_WIDTH 16 /* EQ2_B2_B - [15:0] */
3979
3980/*
3981 * R3629 (0xE2D) - EQ2_8
3982 */
3983#define WM5100_EQ2_B2_C_MASK 0xFFFF /* EQ2_B2_C - [15:0] */
3984#define WM5100_EQ2_B2_C_SHIFT 0 /* EQ2_B2_C - [15:0] */
3985#define WM5100_EQ2_B2_C_WIDTH 16 /* EQ2_B2_C - [15:0] */
3986
3987/*
3988 * R3630 (0xE2E) - EQ2_9
3989 */
3990#define WM5100_EQ2_B2_PG_MASK 0xFFFF /* EQ2_B2_PG - [15:0] */
3991#define WM5100_EQ2_B2_PG_SHIFT 0 /* EQ2_B2_PG - [15:0] */
3992#define WM5100_EQ2_B2_PG_WIDTH 16 /* EQ2_B2_PG - [15:0] */
3993
3994/*
3995 * R3631 (0xE2F) - EQ2_10
3996 */
3997#define WM5100_EQ2_B3_A_MASK 0xFFFF /* EQ2_B3_A - [15:0] */
3998#define WM5100_EQ2_B3_A_SHIFT 0 /* EQ2_B3_A - [15:0] */
3999#define WM5100_EQ2_B3_A_WIDTH 16 /* EQ2_B3_A - [15:0] */
4000
4001/*
4002 * R3632 (0xE30) - EQ2_11
4003 */
4004#define WM5100_EQ2_B3_B_MASK 0xFFFF /* EQ2_B3_B - [15:0] */
4005#define WM5100_EQ2_B3_B_SHIFT 0 /* EQ2_B3_B - [15:0] */
4006#define WM5100_EQ2_B3_B_WIDTH 16 /* EQ2_B3_B - [15:0] */
4007
4008/*
4009 * R3633 (0xE31) - EQ2_12
4010 */
4011#define WM5100_EQ2_B3_C_MASK 0xFFFF /* EQ2_B3_C - [15:0] */
4012#define WM5100_EQ2_B3_C_SHIFT 0 /* EQ2_B3_C - [15:0] */
4013#define WM5100_EQ2_B3_C_WIDTH 16 /* EQ2_B3_C - [15:0] */
4014
4015/*
4016 * R3634 (0xE32) - EQ2_13
4017 */
4018#define WM5100_EQ2_B3_PG_MASK 0xFFFF /* EQ2_B3_PG - [15:0] */
4019#define WM5100_EQ2_B3_PG_SHIFT 0 /* EQ2_B3_PG - [15:0] */
4020#define WM5100_EQ2_B3_PG_WIDTH 16 /* EQ2_B3_PG - [15:0] */
4021
4022/*
4023 * R3635 (0xE33) - EQ2_14
4024 */
4025#define WM5100_EQ2_B4_A_MASK 0xFFFF /* EQ2_B4_A - [15:0] */
4026#define WM5100_EQ2_B4_A_SHIFT 0 /* EQ2_B4_A - [15:0] */
4027#define WM5100_EQ2_B4_A_WIDTH 16 /* EQ2_B4_A - [15:0] */
4028
4029/*
4030 * R3636 (0xE34) - EQ2_15
4031 */
4032#define WM5100_EQ2_B4_B_MASK 0xFFFF /* EQ2_B4_B - [15:0] */
4033#define WM5100_EQ2_B4_B_SHIFT 0 /* EQ2_B4_B - [15:0] */
4034#define WM5100_EQ2_B4_B_WIDTH 16 /* EQ2_B4_B - [15:0] */
4035
4036/*
4037 * R3637 (0xE35) - EQ2_16
4038 */
4039#define WM5100_EQ2_B4_C_MASK 0xFFFF /* EQ2_B4_C - [15:0] */
4040#define WM5100_EQ2_B4_C_SHIFT 0 /* EQ2_B4_C - [15:0] */
4041#define WM5100_EQ2_B4_C_WIDTH 16 /* EQ2_B4_C - [15:0] */
4042
4043/*
4044 * R3638 (0xE36) - EQ2_17
4045 */
4046#define WM5100_EQ2_B4_PG_MASK 0xFFFF /* EQ2_B4_PG - [15:0] */
4047#define WM5100_EQ2_B4_PG_SHIFT 0 /* EQ2_B4_PG - [15:0] */
4048#define WM5100_EQ2_B4_PG_WIDTH 16 /* EQ2_B4_PG - [15:0] */
4049
4050/*
4051 * R3639 (0xE37) - EQ2_18
4052 */
4053#define WM5100_EQ2_B5_A_MASK 0xFFFF /* EQ2_B5_A - [15:0] */
4054#define WM5100_EQ2_B5_A_SHIFT 0 /* EQ2_B5_A - [15:0] */
4055#define WM5100_EQ2_B5_A_WIDTH 16 /* EQ2_B5_A - [15:0] */
4056
4057/*
4058 * R3640 (0xE38) - EQ2_19
4059 */
4060#define WM5100_EQ2_B5_B_MASK 0xFFFF /* EQ2_B5_B - [15:0] */
4061#define WM5100_EQ2_B5_B_SHIFT 0 /* EQ2_B5_B - [15:0] */
4062#define WM5100_EQ2_B5_B_WIDTH 16 /* EQ2_B5_B - [15:0] */
4063
4064/*
4065 * R3641 (0xE39) - EQ2_20
4066 */
4067#define WM5100_EQ2_B5_PG_MASK 0xFFFF /* EQ2_B5_PG - [15:0] */
4068#define WM5100_EQ2_B5_PG_SHIFT 0 /* EQ2_B5_PG - [15:0] */
4069#define WM5100_EQ2_B5_PG_WIDTH 16 /* EQ2_B5_PG - [15:0] */
4070
4071/*
4072 * R3644 (0xE3C) - EQ3_1
4073 */
4074#define WM5100_EQ3_B1_GAIN_MASK 0xF800 /* EQ3_B1_GAIN - [15:11] */
4075#define WM5100_EQ3_B1_GAIN_SHIFT 11 /* EQ3_B1_GAIN - [15:11] */
4076#define WM5100_EQ3_B1_GAIN_WIDTH 5 /* EQ3_B1_GAIN - [15:11] */
4077#define WM5100_EQ3_B2_GAIN_MASK 0x07C0 /* EQ3_B2_GAIN - [10:6] */
4078#define WM5100_EQ3_B2_GAIN_SHIFT 6 /* EQ3_B2_GAIN - [10:6] */
4079#define WM5100_EQ3_B2_GAIN_WIDTH 5 /* EQ3_B2_GAIN - [10:6] */
4080#define WM5100_EQ3_B3_GAIN_MASK 0x003E /* EQ3_B3_GAIN - [5:1] */
4081#define WM5100_EQ3_B3_GAIN_SHIFT 1 /* EQ3_B3_GAIN - [5:1] */
4082#define WM5100_EQ3_B3_GAIN_WIDTH 5 /* EQ3_B3_GAIN - [5:1] */
4083#define WM5100_EQ3_ENA 0x0001 /* EQ3_ENA */
4084#define WM5100_EQ3_ENA_MASK 0x0001 /* EQ3_ENA */
4085#define WM5100_EQ3_ENA_SHIFT 0 /* EQ3_ENA */
4086#define WM5100_EQ3_ENA_WIDTH 1 /* EQ3_ENA */
4087
4088/*
4089 * R3645 (0xE3D) - EQ3_2
4090 */
4091#define WM5100_EQ3_B4_GAIN_MASK 0xF800 /* EQ3_B4_GAIN - [15:11] */
4092#define WM5100_EQ3_B4_GAIN_SHIFT 11 /* EQ3_B4_GAIN - [15:11] */
4093#define WM5100_EQ3_B4_GAIN_WIDTH 5 /* EQ3_B4_GAIN - [15:11] */
4094#define WM5100_EQ3_B5_GAIN_MASK 0x07C0 /* EQ3_B5_GAIN - [10:6] */
4095#define WM5100_EQ3_B5_GAIN_SHIFT 6 /* EQ3_B5_GAIN - [10:6] */
4096#define WM5100_EQ3_B5_GAIN_WIDTH 5 /* EQ3_B5_GAIN - [10:6] */
4097
4098/*
4099 * R3646 (0xE3E) - EQ3_3
4100 */
4101#define WM5100_EQ3_B1_A_MASK 0xFFFF /* EQ3_B1_A - [15:0] */
4102#define WM5100_EQ3_B1_A_SHIFT 0 /* EQ3_B1_A - [15:0] */
4103#define WM5100_EQ3_B1_A_WIDTH 16 /* EQ3_B1_A - [15:0] */
4104
4105/*
4106 * R3647 (0xE3F) - EQ3_4
4107 */
4108#define WM5100_EQ3_B1_B_MASK 0xFFFF /* EQ3_B1_B - [15:0] */
4109#define WM5100_EQ3_B1_B_SHIFT 0 /* EQ3_B1_B - [15:0] */
4110#define WM5100_EQ3_B1_B_WIDTH 16 /* EQ3_B1_B - [15:0] */
4111
4112/*
4113 * R3648 (0xE40) - EQ3_5
4114 */
4115#define WM5100_EQ3_B1_PG_MASK 0xFFFF /* EQ3_B1_PG - [15:0] */
4116#define WM5100_EQ3_B1_PG_SHIFT 0 /* EQ3_B1_PG - [15:0] */
4117#define WM5100_EQ3_B1_PG_WIDTH 16 /* EQ3_B1_PG - [15:0] */
4118
4119/*
4120 * R3649 (0xE41) - EQ3_6
4121 */
4122#define WM5100_EQ3_B2_A_MASK 0xFFFF /* EQ3_B2_A - [15:0] */
4123#define WM5100_EQ3_B2_A_SHIFT 0 /* EQ3_B2_A - [15:0] */
4124#define WM5100_EQ3_B2_A_WIDTH 16 /* EQ3_B2_A - [15:0] */
4125
4126/*
4127 * R3650 (0xE42) - EQ3_7
4128 */
4129#define WM5100_EQ3_B2_B_MASK 0xFFFF /* EQ3_B2_B - [15:0] */
4130#define WM5100_EQ3_B2_B_SHIFT 0 /* EQ3_B2_B - [15:0] */
4131#define WM5100_EQ3_B2_B_WIDTH 16 /* EQ3_B2_B - [15:0] */
4132
4133/*
4134 * R3651 (0xE43) - EQ3_8
4135 */
4136#define WM5100_EQ3_B2_C_MASK 0xFFFF /* EQ3_B2_C - [15:0] */
4137#define WM5100_EQ3_B2_C_SHIFT 0 /* EQ3_B2_C - [15:0] */
4138#define WM5100_EQ3_B2_C_WIDTH 16 /* EQ3_B2_C - [15:0] */
4139
4140/*
4141 * R3652 (0xE44) - EQ3_9
4142 */
4143#define WM5100_EQ3_B2_PG_MASK 0xFFFF /* EQ3_B2_PG - [15:0] */
4144#define WM5100_EQ3_B2_PG_SHIFT 0 /* EQ3_B2_PG - [15:0] */
4145#define WM5100_EQ3_B2_PG_WIDTH 16 /* EQ3_B2_PG - [15:0] */
4146
4147/*
4148 * R3653 (0xE45) - EQ3_10
4149 */
4150#define WM5100_EQ3_B3_A_MASK 0xFFFF /* EQ3_B3_A - [15:0] */
4151#define WM5100_EQ3_B3_A_SHIFT 0 /* EQ3_B3_A - [15:0] */
4152#define WM5100_EQ3_B3_A_WIDTH 16 /* EQ3_B3_A - [15:0] */
4153
4154/*
4155 * R3654 (0xE46) - EQ3_11
4156 */
4157#define WM5100_EQ3_B3_B_MASK 0xFFFF /* EQ3_B3_B - [15:0] */
4158#define WM5100_EQ3_B3_B_SHIFT 0 /* EQ3_B3_B - [15:0] */
4159#define WM5100_EQ3_B3_B_WIDTH 16 /* EQ3_B3_B - [15:0] */
4160
4161/*
4162 * R3655 (0xE47) - EQ3_12
4163 */
4164#define WM5100_EQ3_B3_C_MASK 0xFFFF /* EQ3_B3_C - [15:0] */
4165#define WM5100_EQ3_B3_C_SHIFT 0 /* EQ3_B3_C - [15:0] */
4166#define WM5100_EQ3_B3_C_WIDTH 16 /* EQ3_B3_C - [15:0] */
4167
4168/*
4169 * R3656 (0xE48) - EQ3_13
4170 */
4171#define WM5100_EQ3_B3_PG_MASK 0xFFFF /* EQ3_B3_PG - [15:0] */
4172#define WM5100_EQ3_B3_PG_SHIFT 0 /* EQ3_B3_PG - [15:0] */
4173#define WM5100_EQ3_B3_PG_WIDTH 16 /* EQ3_B3_PG - [15:0] */
4174
4175/*
4176 * R3657 (0xE49) - EQ3_14
4177 */
4178#define WM5100_EQ3_B4_A_MASK 0xFFFF /* EQ3_B4_A - [15:0] */
4179#define WM5100_EQ3_B4_A_SHIFT 0 /* EQ3_B4_A - [15:0] */
4180#define WM5100_EQ3_B4_A_WIDTH 16 /* EQ3_B4_A - [15:0] */
4181
4182/*
4183 * R3658 (0xE4A) - EQ3_15
4184 */
4185#define WM5100_EQ3_B4_B_MASK 0xFFFF /* EQ3_B4_B - [15:0] */
4186#define WM5100_EQ3_B4_B_SHIFT 0 /* EQ3_B4_B - [15:0] */
4187#define WM5100_EQ3_B4_B_WIDTH 16 /* EQ3_B4_B - [15:0] */
4188
4189/*
4190 * R3659 (0xE4B) - EQ3_16
4191 */
4192#define WM5100_EQ3_B4_C_MASK 0xFFFF /* EQ3_B4_C - [15:0] */
4193#define WM5100_EQ3_B4_C_SHIFT 0 /* EQ3_B4_C - [15:0] */
4194#define WM5100_EQ3_B4_C_WIDTH 16 /* EQ3_B4_C - [15:0] */
4195
4196/*
4197 * R3660 (0xE4C) - EQ3_17
4198 */
4199#define WM5100_EQ3_B4_PG_MASK 0xFFFF /* EQ3_B4_PG - [15:0] */
4200#define WM5100_EQ3_B4_PG_SHIFT 0 /* EQ3_B4_PG - [15:0] */
4201#define WM5100_EQ3_B4_PG_WIDTH 16 /* EQ3_B4_PG - [15:0] */
4202
4203/*
4204 * R3661 (0xE4D) - EQ3_18
4205 */
4206#define WM5100_EQ3_B5_A_MASK 0xFFFF /* EQ3_B5_A - [15:0] */
4207#define WM5100_EQ3_B5_A_SHIFT 0 /* EQ3_B5_A - [15:0] */
4208#define WM5100_EQ3_B5_A_WIDTH 16 /* EQ3_B5_A - [15:0] */
4209
4210/*
4211 * R3662 (0xE4E) - EQ3_19
4212 */
4213#define WM5100_EQ3_B5_B_MASK 0xFFFF /* EQ3_B5_B - [15:0] */
4214#define WM5100_EQ3_B5_B_SHIFT 0 /* EQ3_B5_B - [15:0] */
4215#define WM5100_EQ3_B5_B_WIDTH 16 /* EQ3_B5_B - [15:0] */
4216
4217/*
4218 * R3663 (0xE4F) - EQ3_20
4219 */
4220#define WM5100_EQ3_B5_PG_MASK 0xFFFF /* EQ3_B5_PG - [15:0] */
4221#define WM5100_EQ3_B5_PG_SHIFT 0 /* EQ3_B5_PG - [15:0] */
4222#define WM5100_EQ3_B5_PG_WIDTH 16 /* EQ3_B5_PG - [15:0] */
4223
4224/*
4225 * R3666 (0xE52) - EQ4_1
4226 */
4227#define WM5100_EQ4_B1_GAIN_MASK 0xF800 /* EQ4_B1_GAIN - [15:11] */
4228#define WM5100_EQ4_B1_GAIN_SHIFT 11 /* EQ4_B1_GAIN - [15:11] */
4229#define WM5100_EQ4_B1_GAIN_WIDTH 5 /* EQ4_B1_GAIN - [15:11] */
4230#define WM5100_EQ4_B2_GAIN_MASK 0x07C0 /* EQ4_B2_GAIN - [10:6] */
4231#define WM5100_EQ4_B2_GAIN_SHIFT 6 /* EQ4_B2_GAIN - [10:6] */
4232#define WM5100_EQ4_B2_GAIN_WIDTH 5 /* EQ4_B2_GAIN - [10:6] */
4233#define WM5100_EQ4_B3_GAIN_MASK 0x003E /* EQ4_B3_GAIN - [5:1] */
4234#define WM5100_EQ4_B3_GAIN_SHIFT 1 /* EQ4_B3_GAIN - [5:1] */
4235#define WM5100_EQ4_B3_GAIN_WIDTH 5 /* EQ4_B3_GAIN - [5:1] */
4236#define WM5100_EQ4_ENA 0x0001 /* EQ4_ENA */
4237#define WM5100_EQ4_ENA_MASK 0x0001 /* EQ4_ENA */
4238#define WM5100_EQ4_ENA_SHIFT 0 /* EQ4_ENA */
4239#define WM5100_EQ4_ENA_WIDTH 1 /* EQ4_ENA */
4240
4241/*
4242 * R3667 (0xE53) - EQ4_2
4243 */
4244#define WM5100_EQ4_B4_GAIN_MASK 0xF800 /* EQ4_B4_GAIN - [15:11] */
4245#define WM5100_EQ4_B4_GAIN_SHIFT 11 /* EQ4_B4_GAIN - [15:11] */
4246#define WM5100_EQ4_B4_GAIN_WIDTH 5 /* EQ4_B4_GAIN - [15:11] */
4247#define WM5100_EQ4_B5_GAIN_MASK 0x07C0 /* EQ4_B5_GAIN - [10:6] */
4248#define WM5100_EQ4_B5_GAIN_SHIFT 6 /* EQ4_B5_GAIN - [10:6] */
4249#define WM5100_EQ4_B5_GAIN_WIDTH 5 /* EQ4_B5_GAIN - [10:6] */
4250
4251/*
4252 * R3668 (0xE54) - EQ4_3
4253 */
4254#define WM5100_EQ4_B1_A_MASK 0xFFFF /* EQ4_B1_A - [15:0] */
4255#define WM5100_EQ4_B1_A_SHIFT 0 /* EQ4_B1_A - [15:0] */
4256#define WM5100_EQ4_B1_A_WIDTH 16 /* EQ4_B1_A - [15:0] */
4257
4258/*
4259 * R3669 (0xE55) - EQ4_4
4260 */
4261#define WM5100_EQ4_B1_B_MASK 0xFFFF /* EQ4_B1_B - [15:0] */
4262#define WM5100_EQ4_B1_B_SHIFT 0 /* EQ4_B1_B - [15:0] */
4263#define WM5100_EQ4_B1_B_WIDTH 16 /* EQ4_B1_B - [15:0] */
4264
4265/*
4266 * R3670 (0xE56) - EQ4_5
4267 */
4268#define WM5100_EQ4_B1_PG_MASK 0xFFFF /* EQ4_B1_PG - [15:0] */
4269#define WM5100_EQ4_B1_PG_SHIFT 0 /* EQ4_B1_PG - [15:0] */
4270#define WM5100_EQ4_B1_PG_WIDTH 16 /* EQ4_B1_PG - [15:0] */
4271
4272/*
4273 * R3671 (0xE57) - EQ4_6
4274 */
4275#define WM5100_EQ4_B2_A_MASK 0xFFFF /* EQ4_B2_A - [15:0] */
4276#define WM5100_EQ4_B2_A_SHIFT 0 /* EQ4_B2_A - [15:0] */
4277#define WM5100_EQ4_B2_A_WIDTH 16 /* EQ4_B2_A - [15:0] */
4278
4279/*
4280 * R3672 (0xE58) - EQ4_7
4281 */
4282#define WM5100_EQ4_B2_B_MASK 0xFFFF /* EQ4_B2_B - [15:0] */
4283#define WM5100_EQ4_B2_B_SHIFT 0 /* EQ4_B2_B - [15:0] */
4284#define WM5100_EQ4_B2_B_WIDTH 16 /* EQ4_B2_B - [15:0] */
4285
4286/*
4287 * R3673 (0xE59) - EQ4_8
4288 */
4289#define WM5100_EQ4_B2_C_MASK 0xFFFF /* EQ4_B2_C - [15:0] */
4290#define WM5100_EQ4_B2_C_SHIFT 0 /* EQ4_B2_C - [15:0] */
4291#define WM5100_EQ4_B2_C_WIDTH 16 /* EQ4_B2_C - [15:0] */
4292
4293/*
4294 * R3674 (0xE5A) - EQ4_9
4295 */
4296#define WM5100_EQ4_B2_PG_MASK 0xFFFF /* EQ4_B2_PG - [15:0] */
4297#define WM5100_EQ4_B2_PG_SHIFT 0 /* EQ4_B2_PG - [15:0] */
4298#define WM5100_EQ4_B2_PG_WIDTH 16 /* EQ4_B2_PG - [15:0] */
4299
4300/*
4301 * R3675 (0xE5B) - EQ4_10
4302 */
4303#define WM5100_EQ4_B3_A_MASK 0xFFFF /* EQ4_B3_A - [15:0] */
4304#define WM5100_EQ4_B3_A_SHIFT 0 /* EQ4_B3_A - [15:0] */
4305#define WM5100_EQ4_B3_A_WIDTH 16 /* EQ4_B3_A - [15:0] */
4306
4307/*
4308 * R3676 (0xE5C) - EQ4_11
4309 */
4310#define WM5100_EQ4_B3_B_MASK 0xFFFF /* EQ4_B3_B - [15:0] */
4311#define WM5100_EQ4_B3_B_SHIFT 0 /* EQ4_B3_B - [15:0] */
4312#define WM5100_EQ4_B3_B_WIDTH 16 /* EQ4_B3_B - [15:0] */
4313
4314/*
4315 * R3677 (0xE5D) - EQ4_12
4316 */
4317#define WM5100_EQ4_B3_C_MASK 0xFFFF /* EQ4_B3_C - [15:0] */
4318#define WM5100_EQ4_B3_C_SHIFT 0 /* EQ4_B3_C - [15:0] */
4319#define WM5100_EQ4_B3_C_WIDTH 16 /* EQ4_B3_C - [15:0] */
4320
4321/*
4322 * R3678 (0xE5E) - EQ4_13
4323 */
4324#define WM5100_EQ4_B3_PG_MASK 0xFFFF /* EQ4_B3_PG - [15:0] */
4325#define WM5100_EQ4_B3_PG_SHIFT 0 /* EQ4_B3_PG - [15:0] */
4326#define WM5100_EQ4_B3_PG_WIDTH 16 /* EQ4_B3_PG - [15:0] */
4327
4328/*
4329 * R3679 (0xE5F) - EQ4_14
4330 */
4331#define WM5100_EQ4_B4_A_MASK 0xFFFF /* EQ4_B4_A - [15:0] */
4332#define WM5100_EQ4_B4_A_SHIFT 0 /* EQ4_B4_A - [15:0] */
4333#define WM5100_EQ4_B4_A_WIDTH 16 /* EQ4_B4_A - [15:0] */
4334
4335/*
4336 * R3680 (0xE60) - EQ4_15
4337 */
4338#define WM5100_EQ4_B4_B_MASK 0xFFFF /* EQ4_B4_B - [15:0] */
4339#define WM5100_EQ4_B4_B_SHIFT 0 /* EQ4_B4_B - [15:0] */
4340#define WM5100_EQ4_B4_B_WIDTH 16 /* EQ4_B4_B - [15:0] */
4341
4342/*
4343 * R3681 (0xE61) - EQ4_16
4344 */
4345#define WM5100_EQ4_B4_C_MASK 0xFFFF /* EQ4_B4_C - [15:0] */
4346#define WM5100_EQ4_B4_C_SHIFT 0 /* EQ4_B4_C - [15:0] */
4347#define WM5100_EQ4_B4_C_WIDTH 16 /* EQ4_B4_C - [15:0] */
4348
4349/*
4350 * R3682 (0xE62) - EQ4_17
4351 */
4352#define WM5100_EQ4_B4_PG_MASK 0xFFFF /* EQ4_B4_PG - [15:0] */
4353#define WM5100_EQ4_B4_PG_SHIFT 0 /* EQ4_B4_PG - [15:0] */
4354#define WM5100_EQ4_B4_PG_WIDTH 16 /* EQ4_B4_PG - [15:0] */
4355
4356/*
4357 * R3683 (0xE63) - EQ4_18
4358 */
4359#define WM5100_EQ4_B5_A_MASK 0xFFFF /* EQ4_B5_A - [15:0] */
4360#define WM5100_EQ4_B5_A_SHIFT 0 /* EQ4_B5_A - [15:0] */
4361#define WM5100_EQ4_B5_A_WIDTH 16 /* EQ4_B5_A - [15:0] */
4362
4363/*
4364 * R3684 (0xE64) - EQ4_19
4365 */
4366#define WM5100_EQ4_B5_B_MASK 0xFFFF /* EQ4_B5_B - [15:0] */
4367#define WM5100_EQ4_B5_B_SHIFT 0 /* EQ4_B5_B - [15:0] */
4368#define WM5100_EQ4_B5_B_WIDTH 16 /* EQ4_B5_B - [15:0] */
4369
4370/*
4371 * R3685 (0xE65) - EQ4_20
4372 */
4373#define WM5100_EQ4_B5_PG_MASK 0xFFFF /* EQ4_B5_PG - [15:0] */
4374#define WM5100_EQ4_B5_PG_SHIFT 0 /* EQ4_B5_PG - [15:0] */
4375#define WM5100_EQ4_B5_PG_WIDTH 16 /* EQ4_B5_PG - [15:0] */
4376
4377/*
4378 * R3712 (0xE80) - DRC1 ctrl1
4379 */
4380#define WM5100_DRC_SIG_DET_RMS_MASK 0xF800 /* DRC_SIG_DET_RMS - [15:11] */
4381#define WM5100_DRC_SIG_DET_RMS_SHIFT 11 /* DRC_SIG_DET_RMS - [15:11] */
4382#define WM5100_DRC_SIG_DET_RMS_WIDTH 5 /* DRC_SIG_DET_RMS - [15:11] */
4383#define WM5100_DRC_SIG_DET_PK_MASK 0x0600 /* DRC_SIG_DET_PK - [10:9] */
4384#define WM5100_DRC_SIG_DET_PK_SHIFT 9 /* DRC_SIG_DET_PK - [10:9] */
4385#define WM5100_DRC_SIG_DET_PK_WIDTH 2 /* DRC_SIG_DET_PK - [10:9] */
4386#define WM5100_DRC_NG_ENA 0x0100 /* DRC_NG_ENA */
4387#define WM5100_DRC_NG_ENA_MASK 0x0100 /* DRC_NG_ENA */
4388#define WM5100_DRC_NG_ENA_SHIFT 8 /* DRC_NG_ENA */
4389#define WM5100_DRC_NG_ENA_WIDTH 1 /* DRC_NG_ENA */
4390#define WM5100_DRC_SIG_DET_MODE 0x0080 /* DRC_SIG_DET_MODE */
4391#define WM5100_DRC_SIG_DET_MODE_MASK 0x0080 /* DRC_SIG_DET_MODE */
4392#define WM5100_DRC_SIG_DET_MODE_SHIFT 7 /* DRC_SIG_DET_MODE */
4393#define WM5100_DRC_SIG_DET_MODE_WIDTH 1 /* DRC_SIG_DET_MODE */
4394#define WM5100_DRC_SIG_DET 0x0040 /* DRC_SIG_DET */
4395#define WM5100_DRC_SIG_DET_MASK 0x0040 /* DRC_SIG_DET */
4396#define WM5100_DRC_SIG_DET_SHIFT 6 /* DRC_SIG_DET */
4397#define WM5100_DRC_SIG_DET_WIDTH 1 /* DRC_SIG_DET */
4398#define WM5100_DRC_KNEE2_OP_ENA 0x0020 /* DRC_KNEE2_OP_ENA */
4399#define WM5100_DRC_KNEE2_OP_ENA_MASK 0x0020 /* DRC_KNEE2_OP_ENA */
4400#define WM5100_DRC_KNEE2_OP_ENA_SHIFT 5 /* DRC_KNEE2_OP_ENA */
4401#define WM5100_DRC_KNEE2_OP_ENA_WIDTH 1 /* DRC_KNEE2_OP_ENA */
4402#define WM5100_DRC_QR 0x0010 /* DRC_QR */
4403#define WM5100_DRC_QR_MASK 0x0010 /* DRC_QR */
4404#define WM5100_DRC_QR_SHIFT 4 /* DRC_QR */
4405#define WM5100_DRC_QR_WIDTH 1 /* DRC_QR */
4406#define WM5100_DRC_ANTICLIP 0x0008 /* DRC_ANTICLIP */
4407#define WM5100_DRC_ANTICLIP_MASK 0x0008 /* DRC_ANTICLIP */
4408#define WM5100_DRC_ANTICLIP_SHIFT 3 /* DRC_ANTICLIP */
4409#define WM5100_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */
4410#define WM5100_DRCL_ENA 0x0002 /* DRCL_ENA */
4411#define WM5100_DRCL_ENA_MASK 0x0002 /* DRCL_ENA */
4412#define WM5100_DRCL_ENA_SHIFT 1 /* DRCL_ENA */
4413#define WM5100_DRCL_ENA_WIDTH 1 /* DRCL_ENA */
4414#define WM5100_DRCR_ENA 0x0001 /* DRCR_ENA */
4415#define WM5100_DRCR_ENA_MASK 0x0001 /* DRCR_ENA */
4416#define WM5100_DRCR_ENA_SHIFT 0 /* DRCR_ENA */
4417#define WM5100_DRCR_ENA_WIDTH 1 /* DRCR_ENA */
4418
4419/*
4420 * R3713 (0xE81) - DRC1 ctrl2
4421 */
4422#define WM5100_DRC_ATK_MASK 0x1E00 /* DRC_ATK - [12:9] */
4423#define WM5100_DRC_ATK_SHIFT 9 /* DRC_ATK - [12:9] */
4424#define WM5100_DRC_ATK_WIDTH 4 /* DRC_ATK - [12:9] */
4425#define WM5100_DRC_DCY_MASK 0x01E0 /* DRC_DCY - [8:5] */
4426#define WM5100_DRC_DCY_SHIFT 5 /* DRC_DCY - [8:5] */
4427#define WM5100_DRC_DCY_WIDTH 4 /* DRC_DCY - [8:5] */
4428#define WM5100_DRC_MINGAIN_MASK 0x001C /* DRC_MINGAIN - [4:2] */
4429#define WM5100_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [4:2] */
4430#define WM5100_DRC_MINGAIN_WIDTH 3 /* DRC_MINGAIN - [4:2] */
4431#define WM5100_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */
4432#define WM5100_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */
4433#define WM5100_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */
4434
4435/*
4436 * R3714 (0xE82) - DRC1 ctrl3
4437 */
4438#define WM5100_DRC_NG_MINGAIN_MASK 0xF000 /* DRC_NG_MINGAIN - [15:12] */
4439#define WM5100_DRC_NG_MINGAIN_SHIFT 12 /* DRC_NG_MINGAIN - [15:12] */
4440#define WM5100_DRC_NG_MINGAIN_WIDTH 4 /* DRC_NG_MINGAIN - [15:12] */
4441#define WM5100_DRC_NG_EXP_MASK 0x0C00 /* DRC_NG_EXP - [11:10] */
4442#define WM5100_DRC_NG_EXP_SHIFT 10 /* DRC_NG_EXP - [11:10] */
4443#define WM5100_DRC_NG_EXP_WIDTH 2 /* DRC_NG_EXP - [11:10] */
4444#define WM5100_DRC_QR_THR_MASK 0x0300 /* DRC_QR_THR - [9:8] */
4445#define WM5100_DRC_QR_THR_SHIFT 8 /* DRC_QR_THR - [9:8] */
4446#define WM5100_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [9:8] */
4447#define WM5100_DRC_QR_DCY_MASK 0x00C0 /* DRC_QR_DCY - [7:6] */
4448#define WM5100_DRC_QR_DCY_SHIFT 6 /* DRC_QR_DCY - [7:6] */
4449#define WM5100_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [7:6] */
4450#define WM5100_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */
4451#define WM5100_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */
4452#define WM5100_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */
4453#define WM5100_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */
4454#define WM5100_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */
4455#define WM5100_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */
4456
4457/*
4458 * R3715 (0xE83) - DRC1 ctrl4
4459 */
4460#define WM5100_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */
4461#define WM5100_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */
4462#define WM5100_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */
4463#define WM5100_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */
4464#define WM5100_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */
4465#define WM5100_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */
4466
4467/*
4468 * R3716 (0xE84) - DRC1 ctrl5
4469 */
4470#define WM5100_DRC_KNEE2_IP_MASK 0x03E0 /* DRC_KNEE2_IP - [9:5] */
4471#define WM5100_DRC_KNEE2_IP_SHIFT 5 /* DRC_KNEE2_IP - [9:5] */
4472#define WM5100_DRC_KNEE2_IP_WIDTH 5 /* DRC_KNEE2_IP - [9:5] */
4473#define WM5100_DRC_KNEE2_OP_MASK 0x001F /* DRC_KNEE2_OP - [4:0] */
4474#define WM5100_DRC_KNEE2_OP_SHIFT 0 /* DRC_KNEE2_OP - [4:0] */
4475#define WM5100_DRC_KNEE2_OP_WIDTH 5 /* DRC_KNEE2_OP - [4:0] */
4476
4477/*
4478 * R3776 (0xEC0) - HPLPF1_1
4479 */
4480#define WM5100_LHPF1_MODE 0x0002 /* LHPF1_MODE */
4481#define WM5100_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */
4482#define WM5100_LHPF1_MODE_SHIFT 1 /* LHPF1_MODE */
4483#define WM5100_LHPF1_MODE_WIDTH 1 /* LHPF1_MODE */
4484#define WM5100_LHPF1_ENA 0x0001 /* LHPF1_ENA */
4485#define WM5100_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */
4486#define WM5100_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */
4487#define WM5100_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */
4488
4489/*
4490 * R3777 (0xEC1) - HPLPF1_2
4491 */
4492#define WM5100_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */
4493#define WM5100_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */
4494#define WM5100_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */
4495
4496/*
4497 * R3780 (0xEC4) - HPLPF2_1
4498 */
4499#define WM5100_LHPF2_MODE 0x0002 /* LHPF2_MODE */
4500#define WM5100_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */
4501#define WM5100_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */
4502#define WM5100_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */
4503#define WM5100_LHPF2_ENA 0x0001 /* LHPF2_ENA */
4504#define WM5100_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */
4505#define WM5100_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */
4506#define WM5100_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */
4507
4508/*
4509 * R3781 (0xEC5) - HPLPF2_2
4510 */
4511#define WM5100_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */
4512#define WM5100_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */
4513#define WM5100_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */
4514
4515/*
4516 * R3784 (0xEC8) - HPLPF3_1
4517 */
4518#define WM5100_LHPF3_MODE 0x0002 /* LHPF3_MODE */
4519#define WM5100_LHPF3_MODE_MASK 0x0002 /* LHPF3_MODE */
4520#define WM5100_LHPF3_MODE_SHIFT 1 /* LHPF3_MODE */
4521#define WM5100_LHPF3_MODE_WIDTH 1 /* LHPF3_MODE */
4522#define WM5100_LHPF3_ENA 0x0001 /* LHPF3_ENA */
4523#define WM5100_LHPF3_ENA_MASK 0x0001 /* LHPF3_ENA */
4524#define WM5100_LHPF3_ENA_SHIFT 0 /* LHPF3_ENA */
4525#define WM5100_LHPF3_ENA_WIDTH 1 /* LHPF3_ENA */
4526
4527/*
4528 * R3785 (0xEC9) - HPLPF3_2
4529 */
4530#define WM5100_LHPF3_COEFF_MASK 0xFFFF /* LHPF3_COEFF - [15:0] */
4531#define WM5100_LHPF3_COEFF_SHIFT 0 /* LHPF3_COEFF - [15:0] */
4532#define WM5100_LHPF3_COEFF_WIDTH 16 /* LHPF3_COEFF - [15:0] */
4533
4534/*
4535 * R3788 (0xECC) - HPLPF4_1
4536 */
4537#define WM5100_LHPF4_MODE 0x0002 /* LHPF4_MODE */
4538#define WM5100_LHPF4_MODE_MASK 0x0002 /* LHPF4_MODE */
4539#define WM5100_LHPF4_MODE_SHIFT 1 /* LHPF4_MODE */
4540#define WM5100_LHPF4_MODE_WIDTH 1 /* LHPF4_MODE */
4541#define WM5100_LHPF4_ENA 0x0001 /* LHPF4_ENA */
4542#define WM5100_LHPF4_ENA_MASK 0x0001 /* LHPF4_ENA */
4543#define WM5100_LHPF4_ENA_SHIFT 0 /* LHPF4_ENA */
4544#define WM5100_LHPF4_ENA_WIDTH 1 /* LHPF4_ENA */
4545
4546/*
4547 * R3789 (0xECD) - HPLPF4_2
4548 */
4549#define WM5100_LHPF4_COEFF_MASK 0xFFFF /* LHPF4_COEFF - [15:0] */
4550#define WM5100_LHPF4_COEFF_SHIFT 0 /* LHPF4_COEFF - [15:0] */
4551#define WM5100_LHPF4_COEFF_WIDTH 16 /* LHPF4_COEFF - [15:0] */
4552
4553/*
4554 * R16384 (0x4000) - DSP1 DM 0
4555 */
4556#define WM5100_DSP1_DM_START_1_MASK 0x00FF /* DSP1_DM_START - [7:0] */
4557#define WM5100_DSP1_DM_START_1_SHIFT 0 /* DSP1_DM_START - [7:0] */
4558#define WM5100_DSP1_DM_START_1_WIDTH 8 /* DSP1_DM_START - [7:0] */
4559
4560/*
4561 * R16385 (0x4001) - DSP1 DM 1
4562 */
4563#define WM5100_DSP1_DM_START_MASK 0xFFFF /* DSP1_DM_START - [15:0] */
4564#define WM5100_DSP1_DM_START_SHIFT 0 /* DSP1_DM_START - [15:0] */
4565#define WM5100_DSP1_DM_START_WIDTH 16 /* DSP1_DM_START - [15:0] */
4566
4567/*
4568 * R16386 (0x4002) - DSP1 DM 2
4569 */
4570#define WM5100_DSP1_DM_1_1_MASK 0x00FF /* DSP1_DM_1 - [7:0] */
4571#define WM5100_DSP1_DM_1_1_SHIFT 0 /* DSP1_DM_1 - [7:0] */
4572#define WM5100_DSP1_DM_1_1_WIDTH 8 /* DSP1_DM_1 - [7:0] */
4573
4574/*
4575 * R16387 (0x4003) - DSP1 DM 3
4576 */
4577#define WM5100_DSP1_DM_1_MASK 0xFFFF /* DSP1_DM_1 - [15:0] */
4578#define WM5100_DSP1_DM_1_SHIFT 0 /* DSP1_DM_1 - [15:0] */
4579#define WM5100_DSP1_DM_1_WIDTH 16 /* DSP1_DM_1 - [15:0] */
4580
4581/*
4582 * R16892 (0x41FC) - DSP1 DM 508
4583 */
4584#define WM5100_DSP1_DM_254_1_MASK 0x00FF /* DSP1_DM_254 - [7:0] */
4585#define WM5100_DSP1_DM_254_1_SHIFT 0 /* DSP1_DM_254 - [7:0] */
4586#define WM5100_DSP1_DM_254_1_WIDTH 8 /* DSP1_DM_254 - [7:0] */
4587
4588/*
4589 * R16893 (0x41FD) - DSP1 DM 509
4590 */
4591#define WM5100_DSP1_DM_254_MASK 0xFFFF /* DSP1_DM_254 - [15:0] */
4592#define WM5100_DSP1_DM_254_SHIFT 0 /* DSP1_DM_254 - [15:0] */
4593#define WM5100_DSP1_DM_254_WIDTH 16 /* DSP1_DM_254 - [15:0] */
4594
4595/*
4596 * R16894 (0x41FE) - DSP1 DM 510
4597 */
4598#define WM5100_DSP1_DM_END_1_MASK 0x00FF /* DSP1_DM_END - [7:0] */
4599#define WM5100_DSP1_DM_END_1_SHIFT 0 /* DSP1_DM_END - [7:0] */
4600#define WM5100_DSP1_DM_END_1_WIDTH 8 /* DSP1_DM_END - [7:0] */
4601
4602/*
4603 * R16895 (0x41FF) - DSP1 DM 511
4604 */
4605#define WM5100_DSP1_DM_END_MASK 0xFFFF /* DSP1_DM_END - [15:0] */
4606#define WM5100_DSP1_DM_END_SHIFT 0 /* DSP1_DM_END - [15:0] */
4607#define WM5100_DSP1_DM_END_WIDTH 16 /* DSP1_DM_END - [15:0] */
4608
4609/*
4610 * R18432 (0x4800) - DSP1 PM 0
4611 */
4612#define WM5100_DSP1_PM_START_2_MASK 0x00FF /* DSP1_PM_START - [7:0] */
4613#define WM5100_DSP1_PM_START_2_SHIFT 0 /* DSP1_PM_START - [7:0] */
4614#define WM5100_DSP1_PM_START_2_WIDTH 8 /* DSP1_PM_START - [7:0] */
4615
4616/*
4617 * R18433 (0x4801) - DSP1 PM 1
4618 */
4619#define WM5100_DSP1_PM_START_1_MASK 0xFFFF /* DSP1_PM_START - [15:0] */
4620#define WM5100_DSP1_PM_START_1_SHIFT 0 /* DSP1_PM_START - [15:0] */
4621#define WM5100_DSP1_PM_START_1_WIDTH 16 /* DSP1_PM_START - [15:0] */
4622
4623/*
4624 * R18434 (0x4802) - DSP1 PM 2
4625 */
4626#define WM5100_DSP1_PM_START_MASK 0xFFFF /* DSP1_PM_START - [15:0] */
4627#define WM5100_DSP1_PM_START_SHIFT 0 /* DSP1_PM_START - [15:0] */
4628#define WM5100_DSP1_PM_START_WIDTH 16 /* DSP1_PM_START - [15:0] */
4629
4630/*
4631 * R18435 (0x4803) - DSP1 PM 3
4632 */
4633#define WM5100_DSP1_PM_1_2_MASK 0x00FF /* DSP1_PM_1 - [7:0] */
4634#define WM5100_DSP1_PM_1_2_SHIFT 0 /* DSP1_PM_1 - [7:0] */
4635#define WM5100_DSP1_PM_1_2_WIDTH 8 /* DSP1_PM_1 - [7:0] */
4636
4637/*
4638 * R18436 (0x4804) - DSP1 PM 4
4639 */
4640#define WM5100_DSP1_PM_1_1_MASK 0xFFFF /* DSP1_PM_1 - [15:0] */
4641#define WM5100_DSP1_PM_1_1_SHIFT 0 /* DSP1_PM_1 - [15:0] */
4642#define WM5100_DSP1_PM_1_1_WIDTH 16 /* DSP1_PM_1 - [15:0] */
4643
4644/*
4645 * R18437 (0x4805) - DSP1 PM 5
4646 */
4647#define WM5100_DSP1_PM_1_MASK 0xFFFF /* DSP1_PM_1 - [15:0] */
4648#define WM5100_DSP1_PM_1_SHIFT 0 /* DSP1_PM_1 - [15:0] */
4649#define WM5100_DSP1_PM_1_WIDTH 16 /* DSP1_PM_1 - [15:0] */
4650
4651/*
4652 * R19962 (0x4DFA) - DSP1 PM 1530
4653 */
4654#define WM5100_DSP1_PM_510_2_MASK 0x00FF /* DSP1_PM_510 - [7:0] */
4655#define WM5100_DSP1_PM_510_2_SHIFT 0 /* DSP1_PM_510 - [7:0] */
4656#define WM5100_DSP1_PM_510_2_WIDTH 8 /* DSP1_PM_510 - [7:0] */
4657
4658/*
4659 * R19963 (0x4DFB) - DSP1 PM 1531
4660 */
4661#define WM5100_DSP1_PM_510_1_MASK 0xFFFF /* DSP1_PM_510 - [15:0] */
4662#define WM5100_DSP1_PM_510_1_SHIFT 0 /* DSP1_PM_510 - [15:0] */
4663#define WM5100_DSP1_PM_510_1_WIDTH 16 /* DSP1_PM_510 - [15:0] */
4664
4665/*
4666 * R19964 (0x4DFC) - DSP1 PM 1532
4667 */
4668#define WM5100_DSP1_PM_510_MASK 0xFFFF /* DSP1_PM_510 - [15:0] */
4669#define WM5100_DSP1_PM_510_SHIFT 0 /* DSP1_PM_510 - [15:0] */
4670#define WM5100_DSP1_PM_510_WIDTH 16 /* DSP1_PM_510 - [15:0] */
4671
4672/*
4673 * R19965 (0x4DFD) - DSP1 PM 1533
4674 */
4675#define WM5100_DSP1_PM_END_2_MASK 0x00FF /* DSP1_PM_END - [7:0] */
4676#define WM5100_DSP1_PM_END_2_SHIFT 0 /* DSP1_PM_END - [7:0] */
4677#define WM5100_DSP1_PM_END_2_WIDTH 8 /* DSP1_PM_END - [7:0] */
4678
4679/*
4680 * R19966 (0x4DFE) - DSP1 PM 1534
4681 */
4682#define WM5100_DSP1_PM_END_1_MASK 0xFFFF /* DSP1_PM_END - [15:0] */
4683#define WM5100_DSP1_PM_END_1_SHIFT 0 /* DSP1_PM_END - [15:0] */
4684#define WM5100_DSP1_PM_END_1_WIDTH 16 /* DSP1_PM_END - [15:0] */
4685
4686/*
4687 * R19967 (0x4DFF) - DSP1 PM 1535
4688 */
4689#define WM5100_DSP1_PM_END_MASK 0xFFFF /* DSP1_PM_END - [15:0] */
4690#define WM5100_DSP1_PM_END_SHIFT 0 /* DSP1_PM_END - [15:0] */
4691#define WM5100_DSP1_PM_END_WIDTH 16 /* DSP1_PM_END - [15:0] */
4692
4693/*
4694 * R20480 (0x5000) - DSP1 ZM 0
4695 */
4696#define WM5100_DSP1_ZM_START_1_MASK 0x00FF /* DSP1_ZM_START - [7:0] */
4697#define WM5100_DSP1_ZM_START_1_SHIFT 0 /* DSP1_ZM_START - [7:0] */
4698#define WM5100_DSP1_ZM_START_1_WIDTH 8 /* DSP1_ZM_START - [7:0] */
4699
4700/*
4701 * R20481 (0x5001) - DSP1 ZM 1
4702 */
4703#define WM5100_DSP1_ZM_START_MASK 0xFFFF /* DSP1_ZM_START - [15:0] */
4704#define WM5100_DSP1_ZM_START_SHIFT 0 /* DSP1_ZM_START - [15:0] */
4705#define WM5100_DSP1_ZM_START_WIDTH 16 /* DSP1_ZM_START - [15:0] */
4706
4707/*
4708 * R20482 (0x5002) - DSP1 ZM 2
4709 */
4710#define WM5100_DSP1_ZM_1_1_MASK 0x00FF /* DSP1_ZM_1 - [7:0] */
4711#define WM5100_DSP1_ZM_1_1_SHIFT 0 /* DSP1_ZM_1 - [7:0] */
4712#define WM5100_DSP1_ZM_1_1_WIDTH 8 /* DSP1_ZM_1 - [7:0] */
4713
4714/*
4715 * R20483 (0x5003) - DSP1 ZM 3
4716 */
4717#define WM5100_DSP1_ZM_1_MASK 0xFFFF /* DSP1_ZM_1 - [15:0] */
4718#define WM5100_DSP1_ZM_1_SHIFT 0 /* DSP1_ZM_1 - [15:0] */
4719#define WM5100_DSP1_ZM_1_WIDTH 16 /* DSP1_ZM_1 - [15:0] */
4720
4721/*
4722 * R22524 (0x57FC) - DSP1 ZM 2044
4723 */
4724#define WM5100_DSP1_ZM_1022_1_MASK 0x00FF /* DSP1_ZM_1022 - [7:0] */
4725#define WM5100_DSP1_ZM_1022_1_SHIFT 0 /* DSP1_ZM_1022 - [7:0] */
4726#define WM5100_DSP1_ZM_1022_1_WIDTH 8 /* DSP1_ZM_1022 - [7:0] */
4727
4728/*
4729 * R22525 (0x57FD) - DSP1 ZM 2045
4730 */
4731#define WM5100_DSP1_ZM_1022_MASK 0xFFFF /* DSP1_ZM_1022 - [15:0] */
4732#define WM5100_DSP1_ZM_1022_SHIFT 0 /* DSP1_ZM_1022 - [15:0] */
4733#define WM5100_DSP1_ZM_1022_WIDTH 16 /* DSP1_ZM_1022 - [15:0] */
4734
4735/*
4736 * R22526 (0x57FE) - DSP1 ZM 2046
4737 */
4738#define WM5100_DSP1_ZM_END_1_MASK 0x00FF /* DSP1_ZM_END - [7:0] */
4739#define WM5100_DSP1_ZM_END_1_SHIFT 0 /* DSP1_ZM_END - [7:0] */
4740#define WM5100_DSP1_ZM_END_1_WIDTH 8 /* DSP1_ZM_END - [7:0] */
4741
4742/*
4743 * R22527 (0x57FF) - DSP1 ZM 2047
4744 */
4745#define WM5100_DSP1_ZM_END_MASK 0xFFFF /* DSP1_ZM_END - [15:0] */
4746#define WM5100_DSP1_ZM_END_SHIFT 0 /* DSP1_ZM_END - [15:0] */
4747#define WM5100_DSP1_ZM_END_WIDTH 16 /* DSP1_ZM_END - [15:0] */
4748
4749/*
4750 * R24576 (0x6000) - DSP2 DM 0
4751 */
4752#define WM5100_DSP2_DM_START_1_MASK 0x00FF /* DSP2_DM_START - [7:0] */
4753#define WM5100_DSP2_DM_START_1_SHIFT 0 /* DSP2_DM_START - [7:0] */
4754#define WM5100_DSP2_DM_START_1_WIDTH 8 /* DSP2_DM_START - [7:0] */
4755
4756/*
4757 * R24577 (0x6001) - DSP2 DM 1
4758 */
4759#define WM5100_DSP2_DM_START_MASK 0xFFFF /* DSP2_DM_START - [15:0] */
4760#define WM5100_DSP2_DM_START_SHIFT 0 /* DSP2_DM_START - [15:0] */
4761#define WM5100_DSP2_DM_START_WIDTH 16 /* DSP2_DM_START - [15:0] */
4762
4763/*
4764 * R24578 (0x6002) - DSP2 DM 2
4765 */
4766#define WM5100_DSP2_DM_1_1_MASK 0x00FF /* DSP2_DM_1 - [7:0] */
4767#define WM5100_DSP2_DM_1_1_SHIFT 0 /* DSP2_DM_1 - [7:0] */
4768#define WM5100_DSP2_DM_1_1_WIDTH 8 /* DSP2_DM_1 - [7:0] */
4769
4770/*
4771 * R24579 (0x6003) - DSP2 DM 3
4772 */
4773#define WM5100_DSP2_DM_1_MASK 0xFFFF /* DSP2_DM_1 - [15:0] */
4774#define WM5100_DSP2_DM_1_SHIFT 0 /* DSP2_DM_1 - [15:0] */
4775#define WM5100_DSP2_DM_1_WIDTH 16 /* DSP2_DM_1 - [15:0] */
4776
4777/*
4778 * R25084 (0x61FC) - DSP2 DM 508
4779 */
4780#define WM5100_DSP2_DM_254_1_MASK 0x00FF /* DSP2_DM_254 - [7:0] */
4781#define WM5100_DSP2_DM_254_1_SHIFT 0 /* DSP2_DM_254 - [7:0] */
4782#define WM5100_DSP2_DM_254_1_WIDTH 8 /* DSP2_DM_254 - [7:0] */
4783
4784/*
4785 * R25085 (0x61FD) - DSP2 DM 509
4786 */
4787#define WM5100_DSP2_DM_254_MASK 0xFFFF /* DSP2_DM_254 - [15:0] */
4788#define WM5100_DSP2_DM_254_SHIFT 0 /* DSP2_DM_254 - [15:0] */
4789#define WM5100_DSP2_DM_254_WIDTH 16 /* DSP2_DM_254 - [15:0] */
4790
4791/*
4792 * R25086 (0x61FE) - DSP2 DM 510
4793 */
4794#define WM5100_DSP2_DM_END_1_MASK 0x00FF /* DSP2_DM_END - [7:0] */
4795#define WM5100_DSP2_DM_END_1_SHIFT 0 /* DSP2_DM_END - [7:0] */
4796#define WM5100_DSP2_DM_END_1_WIDTH 8 /* DSP2_DM_END - [7:0] */
4797
4798/*
4799 * R25087 (0x61FF) - DSP2 DM 511
4800 */
4801#define WM5100_DSP2_DM_END_MASK 0xFFFF /* DSP2_DM_END - [15:0] */
4802#define WM5100_DSP2_DM_END_SHIFT 0 /* DSP2_DM_END - [15:0] */
4803#define WM5100_DSP2_DM_END_WIDTH 16 /* DSP2_DM_END - [15:0] */
4804
4805/*
4806 * R26624 (0x6800) - DSP2 PM 0
4807 */
4808#define WM5100_DSP2_PM_START_2_MASK 0x00FF /* DSP2_PM_START - [7:0] */
4809#define WM5100_DSP2_PM_START_2_SHIFT 0 /* DSP2_PM_START - [7:0] */
4810#define WM5100_DSP2_PM_START_2_WIDTH 8 /* DSP2_PM_START - [7:0] */
4811
4812/*
4813 * R26625 (0x6801) - DSP2 PM 1
4814 */
4815#define WM5100_DSP2_PM_START_1_MASK 0xFFFF /* DSP2_PM_START - [15:0] */
4816#define WM5100_DSP2_PM_START_1_SHIFT 0 /* DSP2_PM_START - [15:0] */
4817#define WM5100_DSP2_PM_START_1_WIDTH 16 /* DSP2_PM_START - [15:0] */
4818
4819/*
4820 * R26626 (0x6802) - DSP2 PM 2
4821 */
4822#define WM5100_DSP2_PM_START_MASK 0xFFFF /* DSP2_PM_START - [15:0] */
4823#define WM5100_DSP2_PM_START_SHIFT 0 /* DSP2_PM_START - [15:0] */
4824#define WM5100_DSP2_PM_START_WIDTH 16 /* DSP2_PM_START - [15:0] */
4825
4826/*
4827 * R26627 (0x6803) - DSP2 PM 3
4828 */
4829#define WM5100_DSP2_PM_1_2_MASK 0x00FF /* DSP2_PM_1 - [7:0] */
4830#define WM5100_DSP2_PM_1_2_SHIFT 0 /* DSP2_PM_1 - [7:0] */
4831#define WM5100_DSP2_PM_1_2_WIDTH 8 /* DSP2_PM_1 - [7:0] */
4832
4833/*
4834 * R26628 (0x6804) - DSP2 PM 4
4835 */
4836#define WM5100_DSP2_PM_1_1_MASK 0xFFFF /* DSP2_PM_1 - [15:0] */
4837#define WM5100_DSP2_PM_1_1_SHIFT 0 /* DSP2_PM_1 - [15:0] */
4838#define WM5100_DSP2_PM_1_1_WIDTH 16 /* DSP2_PM_1 - [15:0] */
4839
4840/*
4841 * R26629 (0x6805) - DSP2 PM 5
4842 */
4843#define WM5100_DSP2_PM_1_MASK 0xFFFF /* DSP2_PM_1 - [15:0] */
4844#define WM5100_DSP2_PM_1_SHIFT 0 /* DSP2_PM_1 - [15:0] */
4845#define WM5100_DSP2_PM_1_WIDTH 16 /* DSP2_PM_1 - [15:0] */
4846
4847/*
4848 * R28154 (0x6DFA) - DSP2 PM 1530
4849 */
4850#define WM5100_DSP2_PM_510_2_MASK 0x00FF /* DSP2_PM_510 - [7:0] */
4851#define WM5100_DSP2_PM_510_2_SHIFT 0 /* DSP2_PM_510 - [7:0] */
4852#define WM5100_DSP2_PM_510_2_WIDTH 8 /* DSP2_PM_510 - [7:0] */
4853
4854/*
4855 * R28155 (0x6DFB) - DSP2 PM 1531
4856 */
4857#define WM5100_DSP2_PM_510_1_MASK 0xFFFF /* DSP2_PM_510 - [15:0] */
4858#define WM5100_DSP2_PM_510_1_SHIFT 0 /* DSP2_PM_510 - [15:0] */
4859#define WM5100_DSP2_PM_510_1_WIDTH 16 /* DSP2_PM_510 - [15:0] */
4860
4861/*
4862 * R28156 (0x6DFC) - DSP2 PM 1532
4863 */
4864#define WM5100_DSP2_PM_510_MASK 0xFFFF /* DSP2_PM_510 - [15:0] */
4865#define WM5100_DSP2_PM_510_SHIFT 0 /* DSP2_PM_510 - [15:0] */
4866#define WM5100_DSP2_PM_510_WIDTH 16 /* DSP2_PM_510 - [15:0] */
4867
4868/*
4869 * R28157 (0x6DFD) - DSP2 PM 1533
4870 */
4871#define WM5100_DSP2_PM_END_2_MASK 0x00FF /* DSP2_PM_END - [7:0] */
4872#define WM5100_DSP2_PM_END_2_SHIFT 0 /* DSP2_PM_END - [7:0] */
4873#define WM5100_DSP2_PM_END_2_WIDTH 8 /* DSP2_PM_END - [7:0] */
4874
4875/*
4876 * R28158 (0x6DFE) - DSP2 PM 1534
4877 */
4878#define WM5100_DSP2_PM_END_1_MASK 0xFFFF /* DSP2_PM_END - [15:0] */
4879#define WM5100_DSP2_PM_END_1_SHIFT 0 /* DSP2_PM_END - [15:0] */
4880#define WM5100_DSP2_PM_END_1_WIDTH 16 /* DSP2_PM_END - [15:0] */
4881
4882/*
4883 * R28159 (0x6DFF) - DSP2 PM 1535
4884 */
4885#define WM5100_DSP2_PM_END_MASK 0xFFFF /* DSP2_PM_END - [15:0] */
4886#define WM5100_DSP2_PM_END_SHIFT 0 /* DSP2_PM_END - [15:0] */
4887#define WM5100_DSP2_PM_END_WIDTH 16 /* DSP2_PM_END - [15:0] */
4888
4889/*
4890 * R28672 (0x7000) - DSP2 ZM 0
4891 */
4892#define WM5100_DSP2_ZM_START_1_MASK 0x00FF /* DSP2_ZM_START - [7:0] */
4893#define WM5100_DSP2_ZM_START_1_SHIFT 0 /* DSP2_ZM_START - [7:0] */
4894#define WM5100_DSP2_ZM_START_1_WIDTH 8 /* DSP2_ZM_START - [7:0] */
4895
4896/*
4897 * R28673 (0x7001) - DSP2 ZM 1
4898 */
4899#define WM5100_DSP2_ZM_START_MASK 0xFFFF /* DSP2_ZM_START - [15:0] */
4900#define WM5100_DSP2_ZM_START_SHIFT 0 /* DSP2_ZM_START - [15:0] */
4901#define WM5100_DSP2_ZM_START_WIDTH 16 /* DSP2_ZM_START - [15:0] */
4902
4903/*
4904 * R28674 (0x7002) - DSP2 ZM 2
4905 */
4906#define WM5100_DSP2_ZM_1_1_MASK 0x00FF /* DSP2_ZM_1 - [7:0] */
4907#define WM5100_DSP2_ZM_1_1_SHIFT 0 /* DSP2_ZM_1 - [7:0] */
4908#define WM5100_DSP2_ZM_1_1_WIDTH 8 /* DSP2_ZM_1 - [7:0] */
4909
4910/*
4911 * R28675 (0x7003) - DSP2 ZM 3
4912 */
4913#define WM5100_DSP2_ZM_1_MASK 0xFFFF /* DSP2_ZM_1 - [15:0] */
4914#define WM5100_DSP2_ZM_1_SHIFT 0 /* DSP2_ZM_1 - [15:0] */
4915#define WM5100_DSP2_ZM_1_WIDTH 16 /* DSP2_ZM_1 - [15:0] */
4916
4917/*
4918 * R30716 (0x77FC) - DSP2 ZM 2044
4919 */
4920#define WM5100_DSP2_ZM_1022_1_MASK 0x00FF /* DSP2_ZM_1022 - [7:0] */
4921#define WM5100_DSP2_ZM_1022_1_SHIFT 0 /* DSP2_ZM_1022 - [7:0] */
4922#define WM5100_DSP2_ZM_1022_1_WIDTH 8 /* DSP2_ZM_1022 - [7:0] */
4923
4924/*
4925 * R30717 (0x77FD) - DSP2 ZM 2045
4926 */
4927#define WM5100_DSP2_ZM_1022_MASK 0xFFFF /* DSP2_ZM_1022 - [15:0] */
4928#define WM5100_DSP2_ZM_1022_SHIFT 0 /* DSP2_ZM_1022 - [15:0] */
4929#define WM5100_DSP2_ZM_1022_WIDTH 16 /* DSP2_ZM_1022 - [15:0] */
4930
4931/*
4932 * R30718 (0x77FE) - DSP2 ZM 2046
4933 */
4934#define WM5100_DSP2_ZM_END_1_MASK 0x00FF /* DSP2_ZM_END - [7:0] */
4935#define WM5100_DSP2_ZM_END_1_SHIFT 0 /* DSP2_ZM_END - [7:0] */
4936#define WM5100_DSP2_ZM_END_1_WIDTH 8 /* DSP2_ZM_END - [7:0] */
4937
4938/*
4939 * R30719 (0x77FF) - DSP2 ZM 2047
4940 */
4941#define WM5100_DSP2_ZM_END_MASK 0xFFFF /* DSP2_ZM_END - [15:0] */
4942#define WM5100_DSP2_ZM_END_SHIFT 0 /* DSP2_ZM_END - [15:0] */
4943#define WM5100_DSP2_ZM_END_WIDTH 16 /* DSP2_ZM_END - [15:0] */
4944
4945/*
4946 * R32768 (0x8000) - DSP3 DM 0
4947 */
4948#define WM5100_DSP3_DM_START_1_MASK 0x00FF /* DSP3_DM_START - [7:0] */
4949#define WM5100_DSP3_DM_START_1_SHIFT 0 /* DSP3_DM_START - [7:0] */
4950#define WM5100_DSP3_DM_START_1_WIDTH 8 /* DSP3_DM_START - [7:0] */
4951
4952/*
4953 * R32769 (0x8001) - DSP3 DM 1
4954 */
4955#define WM5100_DSP3_DM_START_MASK 0xFFFF /* DSP3_DM_START - [15:0] */
4956#define WM5100_DSP3_DM_START_SHIFT 0 /* DSP3_DM_START - [15:0] */
4957#define WM5100_DSP3_DM_START_WIDTH 16 /* DSP3_DM_START - [15:0] */
4958
4959/*
4960 * R32770 (0x8002) - DSP3 DM 2
4961 */
4962#define WM5100_DSP3_DM_1_1_MASK 0x00FF /* DSP3_DM_1 - [7:0] */
4963#define WM5100_DSP3_DM_1_1_SHIFT 0 /* DSP3_DM_1 - [7:0] */
4964#define WM5100_DSP3_DM_1_1_WIDTH 8 /* DSP3_DM_1 - [7:0] */
4965
4966/*
4967 * R32771 (0x8003) - DSP3 DM 3
4968 */
4969#define WM5100_DSP3_DM_1_MASK 0xFFFF /* DSP3_DM_1 - [15:0] */
4970#define WM5100_DSP3_DM_1_SHIFT 0 /* DSP3_DM_1 - [15:0] */
4971#define WM5100_DSP3_DM_1_WIDTH 16 /* DSP3_DM_1 - [15:0] */
4972
4973/*
4974 * R33276 (0x81FC) - DSP3 DM 508
4975 */
4976#define WM5100_DSP3_DM_254_1_MASK 0x00FF /* DSP3_DM_254 - [7:0] */
4977#define WM5100_DSP3_DM_254_1_SHIFT 0 /* DSP3_DM_254 - [7:0] */
4978#define WM5100_DSP3_DM_254_1_WIDTH 8 /* DSP3_DM_254 - [7:0] */
4979
4980/*
4981 * R33277 (0x81FD) - DSP3 DM 509
4982 */
4983#define WM5100_DSP3_DM_254_MASK 0xFFFF /* DSP3_DM_254 - [15:0] */
4984#define WM5100_DSP3_DM_254_SHIFT 0 /* DSP3_DM_254 - [15:0] */
4985#define WM5100_DSP3_DM_254_WIDTH 16 /* DSP3_DM_254 - [15:0] */
4986
4987/*
4988 * R33278 (0x81FE) - DSP3 DM 510
4989 */
4990#define WM5100_DSP3_DM_END_1_MASK 0x00FF /* DSP3_DM_END - [7:0] */
4991#define WM5100_DSP3_DM_END_1_SHIFT 0 /* DSP3_DM_END - [7:0] */
4992#define WM5100_DSP3_DM_END_1_WIDTH 8 /* DSP3_DM_END - [7:0] */
4993
4994/*
4995 * R33279 (0x81FF) - DSP3 DM 511
4996 */
4997#define WM5100_DSP3_DM_END_MASK 0xFFFF /* DSP3_DM_END - [15:0] */
4998#define WM5100_DSP3_DM_END_SHIFT 0 /* DSP3_DM_END - [15:0] */
4999#define WM5100_DSP3_DM_END_WIDTH 16 /* DSP3_DM_END - [15:0] */
5000
5001/*
5002 * R34816 (0x8800) - DSP3 PM 0
5003 */
5004#define WM5100_DSP3_PM_START_2_MASK 0x00FF /* DSP3_PM_START - [7:0] */
5005#define WM5100_DSP3_PM_START_2_SHIFT 0 /* DSP3_PM_START - [7:0] */
5006#define WM5100_DSP3_PM_START_2_WIDTH 8 /* DSP3_PM_START - [7:0] */
5007
5008/*
5009 * R34817 (0x8801) - DSP3 PM 1
5010 */
5011#define WM5100_DSP3_PM_START_1_MASK 0xFFFF /* DSP3_PM_START - [15:0] */
5012#define WM5100_DSP3_PM_START_1_SHIFT 0 /* DSP3_PM_START - [15:0] */
5013#define WM5100_DSP3_PM_START_1_WIDTH 16 /* DSP3_PM_START - [15:0] */
5014
5015/*
5016 * R34818 (0x8802) - DSP3 PM 2
5017 */
5018#define WM5100_DSP3_PM_START_MASK 0xFFFF /* DSP3_PM_START - [15:0] */
5019#define WM5100_DSP3_PM_START_SHIFT 0 /* DSP3_PM_START - [15:0] */
5020#define WM5100_DSP3_PM_START_WIDTH 16 /* DSP3_PM_START - [15:0] */
5021
5022/*
5023 * R34819 (0x8803) - DSP3 PM 3
5024 */
5025#define WM5100_DSP3_PM_1_2_MASK 0x00FF /* DSP3_PM_1 - [7:0] */
5026#define WM5100_DSP3_PM_1_2_SHIFT 0 /* DSP3_PM_1 - [7:0] */
5027#define WM5100_DSP3_PM_1_2_WIDTH 8 /* DSP3_PM_1 - [7:0] */
5028
5029/*
5030 * R34820 (0x8804) - DSP3 PM 4
5031 */
5032#define WM5100_DSP3_PM_1_1_MASK 0xFFFF /* DSP3_PM_1 - [15:0] */
5033#define WM5100_DSP3_PM_1_1_SHIFT 0 /* DSP3_PM_1 - [15:0] */
5034#define WM5100_DSP3_PM_1_1_WIDTH 16 /* DSP3_PM_1 - [15:0] */
5035
5036/*
5037 * R34821 (0x8805) - DSP3 PM 5
5038 */
5039#define WM5100_DSP3_PM_1_MASK 0xFFFF /* DSP3_PM_1 - [15:0] */
5040#define WM5100_DSP3_PM_1_SHIFT 0 /* DSP3_PM_1 - [15:0] */
5041#define WM5100_DSP3_PM_1_WIDTH 16 /* DSP3_PM_1 - [15:0] */
5042
5043/*
5044 * R36346 (0x8DFA) - DSP3 PM 1530
5045 */
5046#define WM5100_DSP3_PM_510_2_MASK 0x00FF /* DSP3_PM_510 - [7:0] */
5047#define WM5100_DSP3_PM_510_2_SHIFT 0 /* DSP3_PM_510 - [7:0] */
5048#define WM5100_DSP3_PM_510_2_WIDTH 8 /* DSP3_PM_510 - [7:0] */
5049
5050/*
5051 * R36347 (0x8DFB) - DSP3 PM 1531
5052 */
5053#define WM5100_DSP3_PM_510_1_MASK 0xFFFF /* DSP3_PM_510 - [15:0] */
5054#define WM5100_DSP3_PM_510_1_SHIFT 0 /* DSP3_PM_510 - [15:0] */
5055#define WM5100_DSP3_PM_510_1_WIDTH 16 /* DSP3_PM_510 - [15:0] */
5056
5057/*
5058 * R36348 (0x8DFC) - DSP3 PM 1532
5059 */
5060#define WM5100_DSP3_PM_510_MASK 0xFFFF /* DSP3_PM_510 - [15:0] */
5061#define WM5100_DSP3_PM_510_SHIFT 0 /* DSP3_PM_510 - [15:0] */
5062#define WM5100_DSP3_PM_510_WIDTH 16 /* DSP3_PM_510 - [15:0] */
5063
5064/*
5065 * R36349 (0x8DFD) - DSP3 PM 1533
5066 */
5067#define WM5100_DSP3_PM_END_2_MASK 0x00FF /* DSP3_PM_END - [7:0] */
5068#define WM5100_DSP3_PM_END_2_SHIFT 0 /* DSP3_PM_END - [7:0] */
5069#define WM5100_DSP3_PM_END_2_WIDTH 8 /* DSP3_PM_END - [7:0] */
5070
5071/*
5072 * R36350 (0x8DFE) - DSP3 PM 1534
5073 */
5074#define WM5100_DSP3_PM_END_1_MASK 0xFFFF /* DSP3_PM_END - [15:0] */
5075#define WM5100_DSP3_PM_END_1_SHIFT 0 /* DSP3_PM_END - [15:0] */
5076#define WM5100_DSP3_PM_END_1_WIDTH 16 /* DSP3_PM_END - [15:0] */
5077
5078/*
5079 * R36351 (0x8DFF) - DSP3 PM 1535
5080 */
5081#define WM5100_DSP3_PM_END_MASK 0xFFFF /* DSP3_PM_END - [15:0] */
5082#define WM5100_DSP3_PM_END_SHIFT 0 /* DSP3_PM_END - [15:0] */
5083#define WM5100_DSP3_PM_END_WIDTH 16 /* DSP3_PM_END - [15:0] */
5084
5085/*
5086 * R36864 (0x9000) - DSP3 ZM 0
5087 */
5088#define WM5100_DSP3_ZM_START_1_MASK 0x00FF /* DSP3_ZM_START - [7:0] */
5089#define WM5100_DSP3_ZM_START_1_SHIFT 0 /* DSP3_ZM_START - [7:0] */
5090#define WM5100_DSP3_ZM_START_1_WIDTH 8 /* DSP3_ZM_START - [7:0] */
5091
5092/*
5093 * R36865 (0x9001) - DSP3 ZM 1
5094 */
5095#define WM5100_DSP3_ZM_START_MASK 0xFFFF /* DSP3_ZM_START - [15:0] */
5096#define WM5100_DSP3_ZM_START_SHIFT 0 /* DSP3_ZM_START - [15:0] */
5097#define WM5100_DSP3_ZM_START_WIDTH 16 /* DSP3_ZM_START - [15:0] */
5098
5099/*
5100 * R36866 (0x9002) - DSP3 ZM 2
5101 */
5102#define WM5100_DSP3_ZM_1_1_MASK 0x00FF /* DSP3_ZM_1 - [7:0] */
5103#define WM5100_DSP3_ZM_1_1_SHIFT 0 /* DSP3_ZM_1 - [7:0] */
5104#define WM5100_DSP3_ZM_1_1_WIDTH 8 /* DSP3_ZM_1 - [7:0] */
5105
5106/*
5107 * R36867 (0x9003) - DSP3 ZM 3
5108 */
5109#define WM5100_DSP3_ZM_1_MASK 0xFFFF /* DSP3_ZM_1 - [15:0] */
5110#define WM5100_DSP3_ZM_1_SHIFT 0 /* DSP3_ZM_1 - [15:0] */
5111#define WM5100_DSP3_ZM_1_WIDTH 16 /* DSP3_ZM_1 - [15:0] */
5112
5113/*
5114 * R38908 (0x97FC) - DSP3 ZM 2044
5115 */
5116#define WM5100_DSP3_ZM_1022_1_MASK 0x00FF /* DSP3_ZM_1022 - [7:0] */
5117#define WM5100_DSP3_ZM_1022_1_SHIFT 0 /* DSP3_ZM_1022 - [7:0] */
5118#define WM5100_DSP3_ZM_1022_1_WIDTH 8 /* DSP3_ZM_1022 - [7:0] */
5119
5120/*
5121 * R38909 (0x97FD) - DSP3 ZM 2045
5122 */
5123#define WM5100_DSP3_ZM_1022_MASK 0xFFFF /* DSP3_ZM_1022 - [15:0] */
5124#define WM5100_DSP3_ZM_1022_SHIFT 0 /* DSP3_ZM_1022 - [15:0] */
5125#define WM5100_DSP3_ZM_1022_WIDTH 16 /* DSP3_ZM_1022 - [15:0] */
5126
5127/*
5128 * R38910 (0x97FE) - DSP3 ZM 2046
5129 */
5130#define WM5100_DSP3_ZM_END_1_MASK 0x00FF /* DSP3_ZM_END - [7:0] */
5131#define WM5100_DSP3_ZM_END_1_SHIFT 0 /* DSP3_ZM_END - [7:0] */
5132#define WM5100_DSP3_ZM_END_1_WIDTH 8 /* DSP3_ZM_END - [7:0] */
5133
5134/*
5135 * R38911 (0x97FF) - DSP3 ZM 2047
5136 */
5137#define WM5100_DSP3_ZM_END_MASK 0xFFFF /* DSP3_ZM_END - [15:0] */
5138#define WM5100_DSP3_ZM_END_SHIFT 0 /* DSP3_ZM_END - [15:0] */
5139#define WM5100_DSP3_ZM_END_WIDTH 16 /* DSP3_ZM_END - [15:0] */
5140
5141int wm5100_readable_register(struct snd_soc_codec *codec, unsigned int reg);
5142int wm5100_volatile_register(struct snd_soc_codec *codec, unsigned int reg);
5143
5144extern u16 wm5100_reg_defaults[WM5100_MAX_REGISTER + 1];
5145
5146#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 15:09:58 -0500