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-rw-r--r--arch/arm/mach-omap1/clock.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 436eed22801b..fcbea61cb8ca 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -398,7 +398,7 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
398 * Reprogramming the DPLL is tricky, it must be done from SRAM. 398 * Reprogramming the DPLL is tricky, it must be done from SRAM.
399 * (on 730, bit 13 must always be 1) 399 * (on 730, bit 13 must always be 1)
400 */ 400 */
401 if (cpu_is_omap730()) 401 if (cpu_is_omap7xx())
402 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000); 402 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
403 else 403 else
404 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); 404 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
@@ -783,7 +783,7 @@ int __init omap1_clk_init(void)
783 cpu_mask |= CK_16XX; 783 cpu_mask |= CK_16XX;
784 if (cpu_is_omap1510()) 784 if (cpu_is_omap1510())
785 cpu_mask |= CK_1510; 785 cpu_mask |= CK_1510;
786 if (cpu_is_omap730()) 786 if (cpu_is_omap7xx())
787 cpu_mask |= CK_730; 787 cpu_mask |= CK_730;
788 if (cpu_is_omap310()) 788 if (cpu_is_omap310())
789 cpu_mask |= CK_310; 789 cpu_mask |= CK_310;
@@ -800,7 +800,7 @@ int __init omap1_clk_init(void)
800 crystal_type = info->system_clock_type; 800 crystal_type = info->system_clock_type;
801 } 801 }
802 802
803#if defined(CONFIG_ARCH_OMAP730) 803#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
804 ck_ref.rate = 13000000; 804 ck_ref.rate = 13000000;
805#elif defined(CONFIG_ARCH_OMAP16XX) 805#elif defined(CONFIG_ARCH_OMAP16XX)
806 if (crystal_type == 2) 806 if (crystal_type == 2)
@@ -847,7 +847,7 @@ int __init omap1_clk_init(void)
847 printk(KERN_ERR "System frequencies not set. Check your config.\n"); 847 printk(KERN_ERR "System frequencies not set. Check your config.\n");
848 /* Guess sane values (60MHz) */ 848 /* Guess sane values (60MHz) */
849 omap_writew(0x2290, DPLL_CTL); 849 omap_writew(0x2290, DPLL_CTL);
850 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); 850 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
851 ck_dpll1.rate = 60000000; 851 ck_dpll1.rate = 60000000;
852 } 852 }
853#endif 853#endif
@@ -873,7 +873,7 @@ int __init omap1_clk_init(void)
873 873
874 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ 874 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
875 /* (on 730, bit 13 must not be cleared) */ 875 /* (on 730, bit 13 must not be cleared) */
876 if (cpu_is_omap730()) 876 if (cpu_is_omap7xx())
877 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); 877 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
878 else 878 else
879 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); 879 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);