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-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts483
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts234
2 files changed, 717 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
new file mode 100644
index 000000000000..c114c4ee9931
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
@@ -0,0 +1,483 @@
1/*
2 * MPC8572 DS Core0 Device Tree Source in CAMP mode.
3 *
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
7 * eth1, crypto, pci0, pci1.
8 *
9 * Copyright 2007, 2008 Freescale Semiconductor Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17/dts-v1/;
18/ {
19 model = "fsl,MPC8572DS";
20 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 aliases {
25 ethernet0 = &enet0;
26 ethernet1 = &enet1;
27 serial0 = &serial0;
28 pci0 = &pci0;
29 pci1 = &pci1;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8572@0 {
37 device_type = "cpu";
38 reg = <0x0>;
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>;
44 bus-frequency = <0>;
45 clock-frequency = <0>;
46 next-level-cache = <&L2>;
47 };
48
49 };
50
51 memory {
52 device_type = "memory";
53 reg = <0x0 0x0>; // Filled by U-Boot
54 };
55
56 soc8572@ffe00000 {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 device_type = "soc";
60 compatible = "simple-bus";
61 ranges = <0x0 0xffe00000 0x100000>;
62 reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
63 bus-frequency = <0>; // Filled out by uboot.
64
65 memory-controller@2000 {
66 compatible = "fsl,mpc8572-memory-controller";
67 reg = <0x2000 0x1000>;
68 interrupt-parent = <&mpic>;
69 interrupts = <18 2>;
70 };
71
72 memory-controller@6000 {
73 compatible = "fsl,mpc8572-memory-controller";
74 reg = <0x6000 0x1000>;
75 interrupt-parent = <&mpic>;
76 interrupts = <18 2>;
77 };
78
79 L2: l2-cache-controller@20000 {
80 compatible = "fsl,mpc8572-l2-cache-controller";
81 reg = <0x20000 0x1000>;
82 cache-line-size = <32>; // 32 bytes
83 cache-size = <0x80000>; // L2, 512K
84 interrupt-parent = <&mpic>;
85 interrupts = <16 2>;
86 };
87
88 i2c@3000 {
89 #address-cells = <1>;
90 #size-cells = <0>;
91 cell-index = <0>;
92 compatible = "fsl-i2c";
93 reg = <0x3000 0x100>;
94 interrupts = <43 2>;
95 interrupt-parent = <&mpic>;
96 dfsrr;
97 };
98
99 i2c@3100 {
100 #address-cells = <1>;
101 #size-cells = <0>;
102 cell-index = <1>;
103 compatible = "fsl-i2c";
104 reg = <0x3100 0x100>;
105 interrupts = <43 2>;
106 interrupt-parent = <&mpic>;
107 dfsrr;
108 };
109
110 dma@21300 {
111 #address-cells = <1>;
112 #size-cells = <1>;
113 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
114 reg = <0x21300 0x4>;
115 ranges = <0x0 0x21100 0x200>;
116 cell-index = <0>;
117 dma-channel@0 {
118 compatible = "fsl,mpc8572-dma-channel",
119 "fsl,eloplus-dma-channel";
120 reg = <0x0 0x80>;
121 cell-index = <0>;
122 interrupt-parent = <&mpic>;
123 interrupts = <20 2>;
124 };
125 dma-channel@80 {
126 compatible = "fsl,mpc8572-dma-channel",
127 "fsl,eloplus-dma-channel";
128 reg = <0x80 0x80>;
129 cell-index = <1>;
130 interrupt-parent = <&mpic>;
131 interrupts = <21 2>;
132 };
133 dma-channel@100 {
134 compatible = "fsl,mpc8572-dma-channel",
135 "fsl,eloplus-dma-channel";
136 reg = <0x100 0x80>;
137 cell-index = <2>;
138 interrupt-parent = <&mpic>;
139 interrupts = <22 2>;
140 };
141 dma-channel@180 {
142 compatible = "fsl,mpc8572-dma-channel",
143 "fsl,eloplus-dma-channel";
144 reg = <0x180 0x80>;
145 cell-index = <3>;
146 interrupt-parent = <&mpic>;
147 interrupts = <23 2>;
148 };
149 };
150
151 mdio@24520 {
152 #address-cells = <1>;
153 #size-cells = <0>;
154 compatible = "fsl,gianfar-mdio";
155 reg = <0x24520 0x20>;
156
157 phy0: ethernet-phy@0 {
158 interrupt-parent = <&mpic>;
159 interrupts = <10 1>;
160 reg = <0x0>;
161 };
162 phy1: ethernet-phy@1 {
163 interrupt-parent = <&mpic>;
164 interrupts = <10 1>;
165 reg = <0x1>;
166 };
167 };
168
169 enet0: ethernet@24000 {
170 cell-index = <0>;
171 device_type = "network";
172 model = "eTSEC";
173 compatible = "gianfar";
174 reg = <0x24000 0x1000>;
175 local-mac-address = [ 00 00 00 00 00 00 ];
176 interrupts = <29 2 30 2 34 2>;
177 interrupt-parent = <&mpic>;
178 phy-handle = <&phy0>;
179 phy-connection-type = "rgmii-id";
180 };
181
182 enet1: ethernet@25000 {
183 cell-index = <1>;
184 device_type = "network";
185 model = "eTSEC";
186 compatible = "gianfar";
187 reg = <0x25000 0x1000>;
188 local-mac-address = [ 00 00 00 00 00 00 ];
189 interrupts = <35 2 36 2 40 2>;
190 interrupt-parent = <&mpic>;
191 phy-handle = <&phy1>;
192 phy-connection-type = "rgmii-id";
193 };
194
195 serial0: serial@4500 {
196 cell-index = <0>;
197 device_type = "serial";
198 compatible = "ns16550";
199 reg = <0x4500 0x100>;
200 clock-frequency = <0>;
201 };
202
203 global-utilities@e0000 { //global utilities block
204 compatible = "fsl,mpc8572-guts";
205 reg = <0xe0000 0x1000>;
206 fsl,has-rstcr;
207 };
208
209 crypto@30000 {
210 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
211 "fsl,sec2.1", "fsl,sec2.0";
212 reg = <0x30000 0x10000>;
213 interrupts = <45 2 58 2>;
214 interrupt-parent = <&mpic>;
215 fsl,num-channels = <4>;
216 fsl,channel-fifo-len = <24>;
217 fsl,exec-units-mask = <0x9fe>;
218 fsl,descriptor-types-mask = <0x3ab0ebf>;
219 };
220
221 mpic: pic@40000 {
222 interrupt-controller;
223 #address-cells = <0>;
224 #interrupt-cells = <2>;
225 reg = <0x40000 0x40000>;
226 compatible = "chrp,open-pic";
227 device_type = "open-pic";
228 protected-sources = <
229 31 32 33 37 38 39 /* enet2 enet3 */
230 76 77 78 79 27 42 /* dma2 pci2 serial*/
231 0xe0 0xe1 0xe2 0xe3 /* msi */
232 0xe4 0xe5 0xe6 0xe7
233 >;
234 };
235 };
236
237 pci0: pcie@ffe08000 {
238 cell-index = <0>;
239 compatible = "fsl,mpc8548-pcie";
240 device_type = "pci";
241 #interrupt-cells = <1>;
242 #size-cells = <2>;
243 #address-cells = <3>;
244 reg = <0xffe08000 0x1000>;
245 bus-range = <0 255>;
246 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
247 0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
248 clock-frequency = <33333333>;
249 interrupt-parent = <&mpic>;
250 interrupts = <24 2>;
251 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
252 interrupt-map = <
253 /* IDSEL 0x11 func 0 - PCI slot 1 */
254 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
255 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
256 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
257 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
258
259 /* IDSEL 0x11 func 1 - PCI slot 1 */
260 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
261 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
262 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
263 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
264
265 /* IDSEL 0x11 func 2 - PCI slot 1 */
266 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
267 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
268 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
269 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
270
271 /* IDSEL 0x11 func 3 - PCI slot 1 */
272 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
273 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
274 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
275 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
276
277 /* IDSEL 0x11 func 4 - PCI slot 1 */
278 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
279 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
280 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
281 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
282
283 /* IDSEL 0x11 func 5 - PCI slot 1 */
284 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
285 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
286 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
287 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
288
289 /* IDSEL 0x11 func 6 - PCI slot 1 */
290 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
291 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
292 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
293 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
294
295 /* IDSEL 0x11 func 7 - PCI slot 1 */
296 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
297 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
298 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
299 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
300
301 /* IDSEL 0x12 func 0 - PCI slot 2 */
302 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
303 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
304 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
305 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
306
307 /* IDSEL 0x12 func 1 - PCI slot 2 */
308 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
309 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
310 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
311 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
312
313 /* IDSEL 0x12 func 2 - PCI slot 2 */
314 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
315 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
316 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
317 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
318
319 /* IDSEL 0x12 func 3 - PCI slot 2 */
320 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
321 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
322 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
323 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
324
325 /* IDSEL 0x12 func 4 - PCI slot 2 */
326 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
327 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
328 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
329 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
330
331 /* IDSEL 0x12 func 5 - PCI slot 2 */
332 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
333 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
334 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
335 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
336
337 /* IDSEL 0x12 func 6 - PCI slot 2 */
338 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
339 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
340 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
341 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
342
343 /* IDSEL 0x12 func 7 - PCI slot 2 */
344 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
345 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
346 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
347 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
348
349 // IDSEL 0x1c USB
350 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
351 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
352 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
353 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
354
355 // IDSEL 0x1d Audio
356 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
357
358 // IDSEL 0x1e Legacy
359 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
360 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
361
362 // IDSEL 0x1f IDE/SATA
363 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
364 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
365
366 >;
367
368 pcie@0 {
369 reg = <0x0 0x0 0x0 0x0 0x0>;
370 #size-cells = <2>;
371 #address-cells = <3>;
372 device_type = "pci";
373 ranges = <0x2000000 0x0 0x80000000
374 0x2000000 0x0 0x80000000
375 0x0 0x20000000
376
377 0x1000000 0x0 0x0
378 0x1000000 0x0 0x0
379 0x0 0x100000>;
380 uli1575@0 {
381 reg = <0x0 0x0 0x0 0x0 0x0>;
382 #size-cells = <2>;
383 #address-cells = <3>;
384 ranges = <0x2000000 0x0 0x80000000
385 0x2000000 0x0 0x80000000
386 0x0 0x20000000
387
388 0x1000000 0x0 0x0
389 0x1000000 0x0 0x0
390 0x0 0x100000>;
391 isa@1e {
392 device_type = "isa";
393 #interrupt-cells = <2>;
394 #size-cells = <1>;
395 #address-cells = <2>;
396 reg = <0xf000 0x0 0x0 0x0 0x0>;
397 ranges = <0x1 0x0 0x1000000 0x0 0x0
398 0x1000>;
399 interrupt-parent = <&i8259>;
400
401 i8259: interrupt-controller@20 {
402 reg = <0x1 0x20 0x2
403 0x1 0xa0 0x2
404 0x1 0x4d0 0x2>;
405 interrupt-controller;
406 device_type = "interrupt-controller";
407 #address-cells = <0>;
408 #interrupt-cells = <2>;
409 compatible = "chrp,iic";
410 interrupts = <9 2>;
411 interrupt-parent = <&mpic>;
412 };
413
414 i8042@60 {
415 #size-cells = <0>;
416 #address-cells = <1>;
417 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
418 interrupts = <1 3 12 3>;
419 interrupt-parent =
420 <&i8259>;
421
422 keyboard@0 {
423 reg = <0x0>;
424 compatible = "pnpPNP,303";
425 };
426
427 mouse@1 {
428 reg = <0x1>;
429 compatible = "pnpPNP,f03";
430 };
431 };
432
433 rtc@70 {
434 compatible = "pnpPNP,b00";
435 reg = <0x1 0x70 0x2>;
436 };
437
438 gpio@400 {
439 reg = <0x1 0x400 0x80>;
440 };
441 };
442 };
443 };
444
445 };
446
447 pci1: pcie@ffe09000 {
448 cell-index = <1>;
449 compatible = "fsl,mpc8548-pcie";
450 device_type = "pci";
451 #interrupt-cells = <1>;
452 #size-cells = <2>;
453 #address-cells = <3>;
454 reg = <0xffe09000 0x1000>;
455 bus-range = <0 255>;
456 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
457 0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
458 clock-frequency = <33333333>;
459 interrupt-parent = <&mpic>;
460 interrupts = <26 2>;
461 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
462 interrupt-map = <
463 /* IDSEL 0x0 */
464 0000 0x0 0x0 0x1 &mpic 0x4 0x1
465 0000 0x0 0x0 0x2 &mpic 0x5 0x1
466 0000 0x0 0x0 0x3 &mpic 0x6 0x1
467 0000 0x0 0x0 0x4 &mpic 0x7 0x1
468 >;
469 pcie@0 {
470 reg = <0x0 0x0 0x0 0x0 0x0>;
471 #size-cells = <2>;
472 #address-cells = <3>;
473 device_type = "pci";
474 ranges = <0x2000000 0x0 0xa0000000
475 0x2000000 0x0 0xa0000000
476 0x0 0x20000000
477
478 0x1000000 0x0 0x0
479 0x1000000 0x0 0x0
480 0x0 0x100000>;
481 };
482 };
483};
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
new file mode 100644
index 000000000000..04ecda18d206
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
@@ -0,0 +1,234 @@
1/*
2 * MPC8572 DS Core1 Device Tree Source in CAMP mode.
3 *
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts allows core1 to have l2, dma2, eth2, eth3, pci2, msi.
7 *
8 * Please note to add "-b 1" for core1's dts compiling.
9 *
10 * Copyright 2007, 2008 Freescale Semiconductor Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18/dts-v1/;
19/ {
20 model = "fsl,MPC8572DS";
21 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 aliases {
26 ethernet2 = &enet2;
27 ethernet3 = &enet3;
28 serial0 = &serial0;
29 pci2 = &pci2;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8572@1 {
37 device_type = "cpu";
38 reg = <0x1>;
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>;
44 bus-frequency = <0>;
45 clock-frequency = <0>;
46 next-level-cache = <&L2>;
47 };
48 };
49
50 memory {
51 device_type = "memory";
52 reg = <0x0 0x0>; // Filled by U-Boot
53 };
54
55 soc8572@ffe00000 {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 device_type = "soc";
59 compatible = "simple-bus";
60 ranges = <0x0 0xffe00000 0x100000>;
61 reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
62 bus-frequency = <0>; // Filled out by uboot.
63
64 L2: l2-cache-controller@20000 {
65 compatible = "fsl,mpc8572-l2-cache-controller";
66 reg = <0x20000 0x1000>;
67 cache-line-size = <32>; // 32 bytes
68 cache-size = <0x80000>; // L2, 512K
69 interrupt-parent = <&mpic>;
70 };
71
72 dma@c300 {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
76 reg = <0xc300 0x4>;
77 ranges = <0x0 0xc100 0x200>;
78 cell-index = <0>;
79 dma-channel@0 {
80 compatible = "fsl,mpc8572-dma-channel",
81 "fsl,eloplus-dma-channel";
82 reg = <0x0 0x80>;
83 cell-index = <0>;
84 interrupt-parent = <&mpic>;
85 interrupts = <76 2>;
86 };
87 dma-channel@80 {
88 compatible = "fsl,mpc8572-dma-channel",
89 "fsl,eloplus-dma-channel";
90 reg = <0x80 0x80>;
91 cell-index = <1>;
92 interrupt-parent = <&mpic>;
93 interrupts = <77 2>;
94 };
95 dma-channel@100 {
96 compatible = "fsl,mpc8572-dma-channel",
97 "fsl,eloplus-dma-channel";
98 reg = <0x100 0x80>;
99 cell-index = <2>;
100 interrupt-parent = <&mpic>;
101 interrupts = <78 2>;
102 };
103 dma-channel@180 {
104 compatible = "fsl,mpc8572-dma-channel",
105 "fsl,eloplus-dma-channel";
106 reg = <0x180 0x80>;
107 cell-index = <3>;
108 interrupt-parent = <&mpic>;
109 interrupts = <79 2>;
110 };
111 };
112
113 mdio@24520 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 compatible = "fsl,gianfar-mdio";
117 reg = <0x24520 0x20>;
118
119 phy2: ethernet-phy@2 {
120 interrupt-parent = <&mpic>;
121 reg = <0x2>;
122 };
123 phy3: ethernet-phy@3 {
124 interrupt-parent = <&mpic>;
125 reg = <0x3>;
126 };
127 };
128
129 enet2: ethernet@26000 {
130 cell-index = <2>;
131 device_type = "network";
132 model = "eTSEC";
133 compatible = "gianfar";
134 reg = <0x26000 0x1000>;
135 local-mac-address = [ 00 00 00 00 00 00 ];
136 interrupts = <31 2 32 2 33 2>;
137 interrupt-parent = <&mpic>;
138 phy-handle = <&phy2>;
139 phy-connection-type = "rgmii-id";
140 };
141
142 enet3: ethernet@27000 {
143 cell-index = <3>;
144 device_type = "network";
145 model = "eTSEC";
146 compatible = "gianfar";
147 reg = <0x27000 0x1000>;
148 local-mac-address = [ 00 00 00 00 00 00 ];
149 interrupts = <37 2 38 2 39 2>;
150 interrupt-parent = <&mpic>;
151 phy-handle = <&phy3>;
152 phy-connection-type = "rgmii-id";
153 };
154
155 msi@41600 {
156 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
157 reg = <0x41600 0x80>;
158 msi-available-ranges = <0 0x100>;
159 interrupts = <
160 0xe0 0
161 0xe1 0
162 0xe2 0
163 0xe3 0
164 0xe4 0
165 0xe5 0
166 0xe6 0
167 0xe7 0>;
168 interrupt-parent = <&mpic>;
169 };
170
171 serial0: serial@4600 {
172 cell-index = <1>;
173 device_type = "serial";
174 compatible = "ns16550";
175 reg = <0x4600 0x100>;
176 clock-frequency = <0>;
177 };
178
179 mpic: pic@40000 {
180 interrupt-controller;
181 #address-cells = <0>;
182 #interrupt-cells = <2>;
183 reg = <0x40000 0x40000>;
184 compatible = "chrp,open-pic";
185 device_type = "open-pic";
186 protected-sources = <
187 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
188 29 30 34 35 36 40 /* enet0 enet1 */
189 24 26 20 21 22 23 /* pcie0 pcie1 dma1 */
190 43 /* i2c */
191 0x1 0x2 0x3 0x4 /* pci slot */
192 0x9 0xa 0xb 0xc /* usb */
193 0x6 0x7 0xe 0x5 /* Audio elgacy SATA */
194 >;
195 };
196 };
197
198 pci2: pcie@ffe0a000 {
199 cell-index = <2>;
200 compatible = "fsl,mpc8548-pcie";
201 device_type = "pci";
202 #interrupt-cells = <1>;
203 #size-cells = <2>;
204 #address-cells = <3>;
205 reg = <0xffe0a000 0x1000>;
206 bus-range = <0 255>;
207 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
208 0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
209 clock-frequency = <33333333>;
210 interrupt-parent = <&mpic>;
211 interrupts = <27 2>;
212 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
213 interrupt-map = <
214 /* IDSEL 0x0 */
215 0000 0x0 0x0 0x1 &mpic 0x0 0x1
216 0000 0x0 0x0 0x2 &mpic 0x1 0x1
217 0000 0x0 0x0 0x3 &mpic 0x2 0x1
218 0000 0x0 0x0 0x4 &mpic 0x3 0x1
219 >;
220 pcie@0 {
221 reg = <0x0 0x0 0x0 0x0 0x0>;
222 #size-cells = <2>;
223 #address-cells = <3>;
224 device_type = "pci";
225 ranges = <0x2000000 0x0 0xc0000000
226 0x2000000 0x0 0xc0000000
227 0x0 0x20000000
228
229 0x1000000 0x0 0x0
230 0x1000000 0x0 0x0
231 0x0 0x100000>;
232 };
233 };
234};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 07:59:15 -0500