127 files changed, 6093 insertions, 1176 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 92622eb5cc0d..3f8718fc4050 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -647,7 +647,7 @@ config ARCH_SA1100
           Support for StrongARM 11x0 based boards.
 
 config ARCH_S3C2410
-        bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443"
+        bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
         select GENERIC_GPIO
         select ARCH_HAS_CPUFREQ
         select HAVE_CLK
@@ -656,6 +656,10 @@ config ARCH_S3C2410
           BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
           the Samsung SMDK2410 development board (and derivatives).
 
+          Note, the S3C2416 and the S3C2450 are so close that they even share
+          the same SoC ID code. This means that there is no seperate machine
+          directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
+
 config ARCH_S3C64XX
         bool "Samsung S3C64XX"
         select PLAT_SAMSUNG
@@ -892,6 +896,7 @@ if ARCH_S3C2410
 source "arch/arm/mach-s3c2400/Kconfig"
 source "arch/arm/mach-s3c2410/Kconfig"
 source "arch/arm/mach-s3c2412/Kconfig"
+source "arch/arm/mach-s3c2416/Kconfig"
 source "arch/arm/mach-s3c2440/Kconfig"
 source "arch/arm/mach-s3c2443/Kconfig"
 endif
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ed820e737a8a..9505a70bfc0a 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -110,6 +110,8 @@ CHECKFLAGS	+= -D__arm__
 head-y          := arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o
 textofs-y       := 0x00008000
 textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000
+# We don't want the htc bootloader to corrupt kernel during resume
+textofs-$(CONFIG_PM_H1940)      := 0x00108000
 # SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory
 ifeq ($(CONFIG_ARCH_SA1100),y)
 textofs-$(CONFIG_SA1111) := 0x00208000
@@ -160,7 +162,7 @@ machine-$(CONFIG_ARCH_PNX4008)		:= pnx4008
 machine-$(CONFIG_ARCH_PXA)              := pxa
 machine-$(CONFIG_ARCH_REALVIEW)         := realview
 machine-$(CONFIG_ARCH_RPC)              := rpc
-machine-$(CONFIG_ARCH_S3C2410)          := s3c2410 s3c2400 s3c2412 s3c2440 s3c2443
+machine-$(CONFIG_ARCH_S3C2410)          := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443
 machine-$(CONFIG_ARCH_S3C24A0)          := s3c24a0
 machine-$(CONFIG_ARCH_S3C64XX)          := s3c64xx
 machine-$(CONFIG_ARCH_S5P6440)          := s5p6440
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 554731868b07..a4c0b3fcdbba 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -6,6 +6,7 @@ config CPU_S3C2410
         bool
         depends on ARCH_S3C2410
         select CPU_ARM920T
+        select S3C_GPIO_PULL_UP
         select S3C2410_CLOCK
         select S3C2410_GPIO
         select CPU_LLSERIAL_S3C2410
@@ -95,12 +96,19 @@ config PM_H1940
 config MACH_N30
         bool "Acer N30 family"
         select CPU_S3C2410
+        select MACH_N35
         select S3C_DEV_USB_HOST
         select S3C_DEV_NAND
         help
           Say Y here if you want suppt for the Acer N30, Acer N35,
           Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs.
 
+config MACH_N35
+        bool
+        help
+          Internal node in order to enable support for Acer N35 if Acer N30 is
+          selected.
+
 config ARCH_BAST
         bool "Simtec Electronics BAST (EB2410ITX)"
         select CPU_S3C2410
@@ -110,6 +118,7 @@ config ARCH_BAST
         select MACH_BAST_IDE
         select S3C24XX_DCLK
         select ISA
+        select S3C_DEV_HWMON
         select S3C_DEV_USB_HOST
         select S3C_DEV_NAND
         help
diff --git a/arch/arm/mach-s3c2410/Makefile.boot b/arch/arm/mach-s3c2410/Makefile.boot
index 7dab2a0325b5..58c1dd7f8e1d 100644
--- a/arch/arm/mach-s3c2410/Makefile.boot
+++ b/arch/arm/mach-s3c2410/Makefile.boot
@@ -1,3 +1,7 @@
-   zreladdr-y   := 0x30008000
-params_phys-y   := 0x30000100
-
+ifeq ($(CONFIG_PM_H1940),y)
+        zreladdr-y              := 0x30108000
+        params_phys-y   := 0x30100100
+else
+        zreladdr-y              := 0x30008000
+        params_phys-y   := 0x30000100
+endif
diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c
index a3f3c7b1ca38..8cdeb14af592 100644
--- a/arch/arm/mach-s3c2410/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c
@@ -33,14 +33,15 @@ static void h1940bt_enable(int on)
                 h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER);
                 /* Reset the chip */
                 mdelay(10);
-                s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
+
+                gpio_set_value(S3C2410_GPH(1), 1);
                 mdelay(10);
-                s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
+                gpio_set_value(S3C2410_GPH(1), 0);
         }
         else {
-                s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
+                gpio_set_value(S3C2410_GPH(1), 1);
                 mdelay(10);
-                s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
+                gpio_set_value(S3C2410_GPH(1), 0);
                 mdelay(10);
                 h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0);
         }
@@ -61,15 +62,21 @@ static int __devinit h1940bt_probe(struct platform_device *pdev)
         struct rfkill *rfk;
         int ret = 0;
 
+        ret = gpio_request(S3C2410_GPH(1), dev_name(&pdev->dev));
+        if (ret) {
+                dev_err(&pdev->dev, "could not get GPH1\n");\
+                return ret;
+        }
+
         /* Configures BT serial port GPIOs */
-        s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
-        s3c2410_gpio_pullup(S3C2410_GPH(0), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_pullup(S3C2410_GPH(1), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0);
-        s3c2410_gpio_pullup(S3C2410_GPH(2), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
-        s3c2410_gpio_pullup(S3C2410_GPH(3), 1);
+        s3c_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
+        s3c_gpio_cfgpull(S3C2410_GPH(0), S3C_GPIO_PULL_NONE);
+        s3c_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpull(S3C2410_GPH(1), S3C_GPIO_PULL_NONE);
+        s3c_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0);
+        s3c_gpio_cfgpull(S3C2410_GPH(2), S3C_GPIO_PULL_NONE);
+        s3c_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
+        s3c_gpio_cfgpull(S3C2410_GPH(3), S3C_GPIO_PULL_NONE);
 
 
         rfk = rfkill_alloc(DRV_NAME, &pdev->dev, RFKILL_TYPE_BLUETOOTH,
@@ -100,6 +107,7 @@ static int h1940bt_remove(struct platform_device *pdev)
         struct rfkill *rfk = platform_get_drvdata(pdev);
 
         platform_set_drvdata(pdev, NULL);
+        gpio_free(S3C2410_GPH(1));
 
         if (rfk) {
                 rfkill_unregister(rfk);
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
index 08ac5f96c012..cf68136cc668 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -54,7 +54,7 @@ enum dma_ch {
 #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
 
 /* we have 4 dma channels */
-#ifndef CONFIG_CPU_S3C2443
+#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
 #define S3C_DMA_CHANNELS                (4)
 #else
 #define S3C_DMA_CHANNELS                (6)
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
index 035a493952db..f453c4f2cb8e 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
@@ -10,14 +10,28 @@
  * published by the Free Software Foundation.
 */
 
+#ifndef __MACH_GPIO_FNS_H
+#define __MACH_GPIO_FNS_H __FILE__
+
 /* These functions are in the to-be-removed category and it is strongly
  * encouraged not to use these in new code. They will be marked deprecated
  * very soon.
  *
  * Most of the functionality can be either replaced by the gpiocfg calls
  * for the s3c platform or by the generic GPIOlib API.
+ *
+ * As of 2.6.35-rc, these will be removed, with the few drivers using them
+ * either replaced or given a wrapper until the calls can be removed.
 */
 
+#include <plat/gpio-cfg.h>
+
+static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg)
+{
+        /* 1:1 mapping between cfgpin and setcfg calls at the moment */
+        s3c_gpio_cfgpin(pin, cfg);
+}
+
 /* external functions for GPIO support
  *
  * These allow various different clients to access the same GPIO
@@ -25,17 +39,6 @@
  * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
 */
 
-/* s3c2410_gpio_cfgpin
- *
- * set the configuration of the given pin to the value passed.
- *
- * eg:
- *    s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);
- *    s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
-*/
-
-extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
-
 extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
 
 /* s3c2410_gpio_getirq
@@ -73,6 +76,14 @@ extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
 
 /* s3c2410_gpio_pullup
  *
+ * This call should be replaced with s3c_gpio_setpull().
+ *
+ * As a note, there is currently no distinction between pull-up and pull-down
+ * in the s3c24xx series devices with only an on/off configuration.
+ */
+
+/* s3c2410_gpio_pullup
+ *
  * configure the pull-up control on the given pin
  *
  * to = 1 => disable the pull-up
@@ -86,18 +97,8 @@ extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
 
 extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
 
-/* s3c2410_gpio_getpull
- *
- * Read the state of the pull-up on a given pin
- *
- * return:
- *      < 0 => error code
- *        0 => enabled
- *        1 => disabled
-*/
-
-extern int s3c2410_gpio_getpull(unsigned int pin);
-
 extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
 
 extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
+
+#endif /* __MACH_GPIO_FNS_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
index 2edbb9c88ab3..4f7bf3272e87 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
@@ -16,15 +16,28 @@
 
 #define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
 
-#define S3C2410_GPIO_BANKA   (32*0)
-#define S3C2410_GPIO_BANKB   (32*1)
-#define S3C2410_GPIO_BANKC   (32*2)
-#define S3C2410_GPIO_BANKD   (32*3)
-#define S3C2410_GPIO_BANKE   (32*4)
-#define S3C2410_GPIO_BANKF   (32*5)
 #define S3C2410_GPIO_BANKG   (32*6)
 #define S3C2410_GPIO_BANKH   (32*7)
 
+/* GPIO sizes for various SoCs:
+ *
+ *             2442
+ *   2410 2412 2440 2443 2416
+ *   ---- ---- ---- ---- ----
+ * A 23   22   25   16   25
+ * B 11   11   11   11   9
+ * C 16   15   16   16   16
+ * D 16   16   16   16   16
+ * E 16   16   16   16   16
+ * F 8    8    8    8    8
+ * G 16   16   16   16   8
+ * H 11   11   9    15   15
+ * J --   --   13   16   --
+ * K --   --   --   --   16
+ * L --   --   --   15   7
+ * M --   --   --   2    2
+ */
+
 /* GPIO bank sizes */
 #define S3C2410_GPIO_A_NR       (32)
 #define S3C2410_GPIO_B_NR       (32)
@@ -34,6 +47,10 @@
 #define S3C2410_GPIO_F_NR       (32)
 #define S3C2410_GPIO_G_NR       (32)
 #define S3C2410_GPIO_H_NR       (32)
+#define S3C2410_GPIO_J_NR       (32)    /* technically 16. */
+#define S3C2410_GPIO_K_NR       (32)    /* technically 16. */
+#define S3C2410_GPIO_L_NR       (32)    /* technically 15. */
+#define S3C2410_GPIO_M_NR       (32)    /* technically 2. */
 
 #if CONFIG_S3C_GPIO_SPACE != 0
 #error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment
@@ -53,6 +70,10 @@ enum s3c_gpio_number {
         S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
         S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
         S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
+        S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H),
+        S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J),
+        S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K),
+        S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L),
 };
 
 #endif /* __ASSEMBLY__ */
@@ -67,6 +88,10 @@ enum s3c_gpio_number {
 #define S3C2410_GPF(_nr)        (S3C2410_GPIO_F_START + (_nr))
 #define S3C2410_GPG(_nr)        (S3C2410_GPIO_G_START + (_nr))
 #define S3C2410_GPH(_nr)        (S3C2410_GPIO_H_START + (_nr))
+#define S3C2410_GPJ(_nr)        (S3C2410_GPIO_J_START + (_nr))
+#define S3C2410_GPK(_nr)        (S3C2410_GPIO_K_START + (_nr))
+#define S3C2410_GPL(_nr)        (S3C2410_GPIO_L_START + (_nr))
+#define S3C2410_GPM(_nr)        (S3C2410_GPIO_M_START + (_nr))
 
 /* compatibility until drivers can be modified */
 
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-track.h b/arch/arm/mach-s3c2410/include/mach/gpio-track.h
index acb259103808..d67819dde42a 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-track.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-track.h
@@ -23,11 +23,11 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
 {
         struct s3c_gpio_chip *chip;
 
-        if (pin > S3C2410_GPG(10))
+        if (pin > S3C_GPIO_END)
                 return NULL;
 
         chip = &s3c24xx_gpios[pin/32];
-        return (S3C2410_GPIO_OFFSET(pin) < chip->chip.ngpio) ? chip : NULL;
+        return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL;
 }
 
 #endif /* __ASM_ARCH_GPIO_CORE_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h
index 15f0b3e7ce69..b649bf2ccd5c 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio.h
@@ -20,10 +20,18 @@
  * devices that need GPIO.
  */
 
+#ifdef CONFIG_CPU_S3C244X
+#define ARCH_NR_GPIOS   (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
+#else
 #define ARCH_NR_GPIOS   (256 + CONFIG_S3C24XX_GPIO_EXTRA)
+#endif
 
 #include <asm-generic/gpio.h>
 #include <mach/gpio-nrs.h>
 #include <mach/gpio-fns.h>
 
+#ifdef CONFIG_CPU_S3C24XX
+#define S3C_GPIO_END    (S3C2410_GPIO_BANKJ + 32)
+#else
 #define S3C_GPIO_END    (S3C2410_GPIO_BANKH + 32)
+#endif
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h
index 6c12c6312ad8..11bb0f08fe6a 100644
--- a/arch/arm/mach-s3c2410/include/mach/irqs.h
+++ b/arch/arm/mach-s3c2410/include/mach/irqs.h
@@ -115,6 +115,26 @@
 #define IRQ_S3C2412_SDI         S3C2410_IRQSUB(13)
 #define IRQ_S3C2412_CF          S3C2410_IRQSUB(14)
 
+
+#define IRQ_S3C2416_EINT8t15    S3C2410_IRQ(5)
+#define IRQ_S3C2416_DMA         S3C2410_IRQ(17)
+#define IRQ_S3C2416_UART3       S3C2410_IRQ(18)
+#define IRQ_S3C2416_SDI1        S3C2410_IRQ(20)
+#define IRQ_S3C2416_SDI0        S3C2410_IRQ(21)
+
+#define IRQ_S3C2416_LCD2        S3C2410_IRQSUB(15)
+#define IRQ_S3C2416_LCD3        S3C2410_IRQSUB(16)
+#define IRQ_S3C2416_LCD4        S3C2410_IRQSUB(17)
+#define IRQ_S3C2416_DMA0        S3C2410_IRQSUB(18)
+#define IRQ_S3C2416_DMA1        S3C2410_IRQSUB(19)
+#define IRQ_S3C2416_DMA2        S3C2410_IRQSUB(20)
+#define IRQ_S3C2416_DMA3        S3C2410_IRQSUB(21)
+#define IRQ_S3C2416_DMA4        S3C2410_IRQSUB(22)
+#define IRQ_S3C2416_DMA5        S3C2410_IRQSUB(23)
+#define IRQ_S32416_WDT          S3C2410_IRQSUB(27)
+#define IRQ_S32416_AC97         S3C2410_IRQSUB(28)
+
+
 /* extra irqs for s3c2440 */
 
 #define IRQ_S3C2440_CAM_C       S3C2410_IRQSUB(11)      /* S3C2443 too */
@@ -130,7 +150,10 @@
 #define IRQ_S3C2443_HSMMC       S3C2410_IRQ(20)         /* IRQ_SDI */
 #define IRQ_S3C2443_NAND        S3C2410_IRQ(24)         /* reserved */
 
+#define IRQ_S3C2416_HSMMC0      S3C2410_IRQ(21)         /* S3C2416/S3C2450 */
+
 #define IRQ_HSMMC0              IRQ_S3C2443_HSMMC
+#define IRQ_HSMMC1              IRQ_S3C2416_HSMMC0
 
 #define IRQ_S3C2443_LCD1        S3C2410_IRQSUB(14)
 #define IRQ_S3C2443_LCD2        S3C2410_IRQSUB(15)
@@ -152,7 +175,7 @@
 #define IRQ_S3C2443_WDT         S3C2410_IRQSUB(27)
 #define IRQ_S3C2443_AC97        S3C2410_IRQSUB(28)
 
-#ifdef CONFIG_CPU_S3C2443
+#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
 #define NR_IRQS (IRQ_S3C2443_AC97+1)
 #else
 #define NR_IRQS (IRQ_S3C2440_AC97+1)
@@ -164,6 +187,9 @@
 #define IRQ_S3CUART_TX3         IRQ_S3C2443_TX3
 #define IRQ_S3CUART_ERR3        IRQ_S3C2443_ERR3
 
+#define IRQ_LCD_VSYNC           IRQ_S3C2443_LCD3
+#define IRQ_LCD_SYSTEM          IRQ_S3C2443_LCD2
+
 #ifdef CONFIG_CPU_S3C2440
 #define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97
 #else
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index b049e61460b6..091c98a639d9 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -63,9 +63,11 @@
 #define S3C2440_PA_AC97    (0x5B000000)
 #define S3C2440_SZ_AC97    SZ_1M
 
-/* S3C2443 High-speed SD/MMC */
+/* S3C2443/S3C2416 High-speed SD/MMC */
 #define S3C2443_PA_HSMMC   (0x4A800000)
-#define S3C2443_SZ_HSMMC   (256)
+#define S3C2416_PA_HSMMC0  (0x4AC00000)
+
+#define S3C2443_PA_FB   (0x4C800000)
 
 /* S3C2412 memory and IO controls */
 #define S3C2412_PA_SSMC (0x4F000000)
@@ -106,10 +108,12 @@
 #define S3C24XX_PA_SDI      S3C2410_PA_SDI
 #define S3C24XX_PA_NAND     S3C2410_PA_NAND
 
+#define S3C_PA_FB           S3C2443_PA_FB
 #define S3C_PA_IIC          S3C2410_PA_IIC
 #define S3C_PA_UART         S3C24XX_PA_UART
 #define S3C_PA_USBHOST  S3C2410_PA_USBHOST
 #define S3C_PA_HSMMC0       S3C2443_PA_HSMMC
+#define S3C_PA_HSMMC1       S3C2416_PA_HSMMC0
 #define S3C_PA_NAND         S3C24XX_PA_NAND
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
index 9a0d169be137..3415b60082d7 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
@@ -161,4 +161,6 @@
 
 #endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
 
+#define S3C2416_CLKDIV2         S3C2410_CLKREG(0x28)
+
 #endif /* __ASM_ARM_REGS_CLOCK */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
index 3c3853cd3cf7..98fd4a05587c 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
@@ -19,6 +19,42 @@
 #define S3C2412_DSC1       S3C2410_GPIOREG(0xe0)
 #endif
 
+#if defined(CONFIG_CPU_S3C2416)
+#define S3C2416_DSC0       S3C2410_GPIOREG(0xc0)
+#define S3C2416_DSC1       S3C2410_GPIOREG(0xc4)
+#define S3C2416_DSC2       S3C2410_GPIOREG(0xc8)
+#define S3C2416_DSC3       S3C2410_GPIOREG(0x110)
+
+#define S3C2416_SELECT_DSC0     (0 << 30)
+#define S3C2416_SELECT_DSC1     (1 << 30)
+#define S3C2416_SELECT_DSC2     (2 << 30)
+#define S3C2416_SELECT_DSC3     (3 << 30)
+
+#define S3C2416_DSC_GETSHIFT(x) (x & 30)
+
+#define S3C2416_DSC0_CF         (S3C2416_SELECT_DSC0 | 28)
+#define S3C2416_DSC0_CF_5mA     (0 << 28)
+#define S3C2416_DSC0_CF_10mA    (1 << 28)
+#define S3C2416_DSC0_CF_15mA    (2 << 28)
+#define S3C2416_DSC0_CF_21mA    (3 << 28)
+#define S3C2416_DSC0_CF_MASK    (3 << 28)
+
+#define S3C2416_DSC0_nRBE       (S3C2416_SELECT_DSC0 | 26)
+#define S3C2416_DSC0_nRBE_5mA   (0 << 26)
+#define S3C2416_DSC0_nRBE_10mA  (1 << 26)
+#define S3C2416_DSC0_nRBE_15mA  (2 << 26)
+#define S3C2416_DSC0_nRBE_21mA  (3 << 26)
+#define S3C2416_DSC0_nRBE_MASK  (3 << 26)
+
+#define S3C2416_DSC0_nROE       (S3C2416_SELECT_DSC0 | 24)
+#define S3C2416_DSC0_nROE_5mA   (0 << 24)
+#define S3C2416_DSC0_nROE_10mA  (1 << 24)
+#define S3C2416_DSC0_nROE_15mA  (2 << 24)
+#define S3C2416_DSC0_nROE_21mA  (3 << 24)
+#define S3C2416_DSC0_nROE_MASK  (3 << 24)
+
+#endif
+
 #if defined(CONFIG_CPU_S3C244X)
 
 #define S3C2440_DSC0       S3C2410_GPIOREG(0xc4)
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index fd672f330bf2..a0a89d429296 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -17,29 +17,11 @@
 #include <mach/gpio-nrs.h>
 
 #ifdef CONFIG_CPU_S3C2400
-#define S3C24XX_GPIO_BASE(x)  S3C2400_GPIO_BASE(x)
-#define S3C24XX_MISCCR        S3C2400_MISCCR
+#define S3C24XX_MISCCR          S3C2400_MISCCR
 #else
-#define S3C24XX_GPIO_BASE(x)  S3C2410_GPIO_BASE(x)
-#define S3C24XX_MISCCR        S3C24XX_GPIOREG2(0x80)
+#define S3C24XX_MISCCR          S3C24XX_GPIOREG2(0x80)
 #endif /* CONFIG_CPU_S3C2400 */
 
-
-/* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */
-
-#define S3C2400_BANKNUM(pin)     (((pin) & ~31) / 32)
-#define S3C2400_BASEA2B(pin)     ((((pin) & ~31) >> 2))
-#define S3C2400_BASEC2H(pin)     ((S3C2400_BANKNUM(pin) * 10) + \
-                                 (2 * (S3C2400_BANKNUM(pin)-2)))
-
-#define S3C2400_GPIO_BASE(pin)   (pin < S3C2410_GPIO_BANKC ? \
-                                 S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \
-                                 S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO)
-
-
-#define S3C2410_GPIO_BASE(pin)   ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO)
-#define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)
-
 /* general configuration options */
 
 #define S3C2410_GPIO_LEAVE   (0xFFFFFFFF)
@@ -610,35 +592,73 @@
 #define S3C2410_GPHUP      S3C2410_GPIOREG(0x78)
 
 #define S3C2410_GPH0_nCTS0  (0x02 << 0)
+#define S3C2416_GPH0_TXD0  (0x02 << 0)
 
 #define S3C2410_GPH1_nRTS0  (0x02 << 2)
+#define S3C2416_GPH1_RXD0  (0x02 << 2)
 
 #define S3C2410_GPH2_TXD0   (0x02 << 4)
+#define S3C2416_GPH2_TXD1   (0x02 << 4)
 
 #define S3C2410_GPH3_RXD0   (0x02 << 6)
+#define S3C2416_GPH3_RXD1   (0x02 << 6)
 
 #define S3C2410_GPH4_TXD1   (0x02 << 8)
+#define S3C2416_GPH4_TXD2   (0x02 << 8)
 
 #define S3C2410_GPH5_RXD1   (0x02 << 10)
+#define S3C2416_GPH5_RXD2   (0x02 << 10)
 
 #define S3C2410_GPH6_TXD2   (0x02 << 12)
+#define S3C2416_GPH6_TXD3   (0x02 << 12)
 #define S3C2410_GPH6_nRTS1  (0x03 << 12)
+#define S3C2416_GPH6_nRTS2  (0x03 << 12)
 
 #define S3C2410_GPH7_RXD2   (0x02 << 14)
+#define S3C2416_GPH7_RXD3   (0x02 << 14)
 #define S3C2410_GPH7_nCTS1  (0x03 << 14)
+#define S3C2416_GPH7_nCTS2  (0x03 << 14)
 
 #define S3C2410_GPH8_UCLK   (0x02 << 16)
+#define S3C2416_GPH8_nCTS0  (0x02 << 16)
 
 #define S3C2410_GPH9_CLKOUT0  (0x02 << 18)
 #define S3C2442_GPH9_nSPICS0  (0x03 << 18)
+#define S3C2416_GPH9_nRTS0    (0x02 << 18)
 
 #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
+#define S3C2416_GPH10_nCTS1   (0x02 << 20)
+
+#define S3C2416_GPH11_nRTS1   (0x02 << 22)
+
+#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24)
+
+#define S3C2416_GPH13_CLKOUT0 (0x02 << 26)
+
+#define S3C2416_GPH14_CLKOUT1 (0x02 << 28)
 
 /* The S3C2412 and S3C2413 move the GPJ register set to after
  * GPH, which means all registers after 0x80 are now offset by 0x10
  * for the 2412/2413 from the 2410/2440/2442
 */
 
+/* S3C2443 and above */
+#define S3C2440_GPJCON     S3C2410_GPIOREG(0xD0)
+#define S3C2440_GPJDAT     S3C2410_GPIOREG(0xD4)
+#define S3C2440_GPJUP      S3C2410_GPIOREG(0xD8)
+
+#define S3C2443_GPKCON     S3C2410_GPIOREG(0xE0)
+#define S3C2443_GPKDAT     S3C2410_GPIOREG(0xE4)
+#define S3C2443_GPKUP      S3C2410_GPIOREG(0xE8)
+
+#define S3C2443_GPLCON     S3C2410_GPIOREG(0xF0)
+#define S3C2443_GPLDAT     S3C2410_GPIOREG(0xF4)
+#define S3C2443_GPLUP      S3C2410_GPIOREG(0xF8)
+
+#define S3C2443_GPMCON     S3C2410_GPIOREG(0x100)
+#define S3C2443_GPMDAT     S3C2410_GPIOREG(0x104)
+#define S3C2443_GPMUP      S3C2410_GPIOREG(0x108)
+
 /* miscellaneous control */
 #define S3C2400_MISCCR     S3C2410_GPIOREG(0x54)
 #define S3C2410_MISCCR     S3C2410_GPIOREG(0x80)
@@ -686,6 +706,7 @@
 #define S3C2412_MISCCR_CLK1_CLKsrc  (0<<8)
 
 #define S3C2410_MISCCR_USBSUSPND0   (1<<12)
+#define S3C2416_MISCCR_SEL_SUSPND   (1<<12)
 #define S3C2410_MISCCR_USBSUSPND1   (1<<13)
 
 #define S3C2410_MISCCR_nRSTCON      (1<<16)
@@ -695,6 +716,9 @@
 #define S3C2410_MISCCR_nEN_SCLKE    (1<<19)     /* not 2412 */
 #define S3C2410_MISCCR_SDSLEEP      (7<<17)
 
+#define S3C2416_MISCCR_FLT_I2C      (1<<24)
+#define S3C2416_MISCCR_HSSPI_EN2    (1<<31)
+
 /* external interrupt control... */
 /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
  * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
@@ -762,8 +786,11 @@
 #define S3C2410_GSTATUS1_IDMASK    (0xffff0000)
 #define S3C2410_GSTATUS1_2410      (0x32410000)
 #define S3C2410_GSTATUS1_2412      (0x32412001)
+#define S3C2410_GSTATUS1_2416      (0x32416003)
 #define S3C2410_GSTATUS1_2440      (0x32440000)
 #define S3C2410_GSTATUS1_2442      (0x32440aaa)
+/* some 2416 CPUs report this value also */
+#define S3C2410_GSTATUS1_2450      (0x32450003)
 
 #define S3C2410_GSTATUS2_WTRESET   (1<<2)
 #define S3C2410_GSTATUS2_OFFRESET  (1<<1)
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
index 1202ca5e99f6..19575e061114 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
@@ -22,85 +22,49 @@
  * pull up works like all other ports.
 */
 
-#define S3C2440_GPIO_BANKJ  (416)
-
-#define S3C2440_GPJCON      S3C2410_GPIOREG(0xd0)
-#define S3C2440_GPJDAT      S3C2410_GPIOREG(0xd4)
-#define S3C2440_GPJUP       S3C2410_GPIOREG(0xd8)
-
 #define S3C2413_GPJCON          S3C2410_GPIOREG(0x80)
 #define S3C2413_GPJDAT          S3C2410_GPIOREG(0x84)
 #define S3C2413_GPJUP           S3C2410_GPIOREG(0x88)
 #define S3C2413_GPJSLPCON       S3C2410_GPIOREG(0x8C)
 
-#define S3C2440_GPJ0            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0)
-#define S3C2440_GPJ0_INP        (0x00 << 0)
 #define S3C2440_GPJ0_OUTP       (0x01 << 0)
 #define S3C2440_GPJ0_CAMDATA0   (0x02 << 0)
 
-#define S3C2440_GPJ1            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 1)
-#define S3C2440_GPJ1_INP        (0x00 << 2)
 #define S3C2440_GPJ1_OUTP       (0x01 << 2)
 #define S3C2440_GPJ1_CAMDATA1   (0x02 << 2)
 
-#define S3C2440_GPJ2            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 2)
-#define S3C2440_GPJ2_INP        (0x00 << 4)
 #define S3C2440_GPJ2_OUTP       (0x01 << 4)
 #define S3C2440_GPJ2_CAMDATA2   (0x02 << 4)
 
-#define S3C2440_GPJ3            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 3)
-#define S3C2440_GPJ3_INP        (0x00 << 6)
 #define S3C2440_GPJ3_OUTP       (0x01 << 6)
 #define S3C2440_GPJ3_CAMDATA3   (0x02 << 6)
 
-#define S3C2440_GPJ4            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 4)
-#define S3C2440_GPJ4_INP        (0x00 << 8)
 #define S3C2440_GPJ4_OUTP       (0x01 << 8)
 #define S3C2440_GPJ4_CAMDATA4   (0x02 << 8)
 
-#define S3C2440_GPJ5            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 5)
-#define S3C2440_GPJ5_INP        (0x00 << 10)
 #define S3C2440_GPJ5_OUTP       (0x01 << 10)
 #define S3C2440_GPJ5_CAMDATA5   (0x02 << 10)
 
-#define S3C2440_GPJ6            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 6)
-#define S3C2440_GPJ6_INP        (0x00 << 12)
 #define S3C2440_GPJ6_OUTP       (0x01 << 12)
 #define S3C2440_GPJ6_CAMDATA6   (0x02 << 12)
 
-#define S3C2440_GPJ7            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 7)
-#define S3C2440_GPJ7_INP        (0x00 << 14)
 #define S3C2440_GPJ7_OUTP       (0x01 << 14)
 #define S3C2440_GPJ7_CAMDATA7   (0x02 << 14)
 
-#define S3C2440_GPJ8            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 8)
-#define S3C2440_GPJ8_INP        (0x00 << 16)
 #define S3C2440_GPJ8_OUTP       (0x01 << 16)
 #define S3C2440_GPJ8_CAMPCLK    (0x02 << 16)
 
-#define S3C2440_GPJ9            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 9)
-#define S3C2440_GPJ9_INP        (0x00 << 18)
 #define S3C2440_GPJ9_OUTP       (0x01 << 18)
 #define S3C2440_GPJ9_CAMVSYNC   (0x02 << 18)
 
-#define S3C2440_GPJ10           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 10)
-#define S3C2440_GPJ10_INP       (0x00 << 20)
 #define S3C2440_GPJ10_OUTP      (0x01 << 20)
 #define S3C2440_GPJ10_CAMHREF   (0x02 << 20)
 
-#define S3C2440_GPJ11           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 11)
-#define S3C2440_GPJ11_INP       (0x00 << 22)
 #define S3C2440_GPJ11_OUTP      (0x01 << 22)
 #define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22)
 
-#define S3C2440_GPJ12           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 12)
-#define S3C2440_GPJ12_INP       (0x00 << 24)
 #define S3C2440_GPJ12_OUTP      (0x01 << 24)
 #define S3C2440_GPJ12_CAMRESET  (0x02 << 24)
 
-#define S3C2443_GPJ13           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 13)
-#define S3C2443_GPJ14           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 14)
-#define S3C2443_GPJ15           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 15)
-
 #endif  /* __ASM_ARCH_REGS_GPIOJ_H */
 
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-irq.h b/arch/arm/mach-s3c2410/include/mach/regs-irq.h
index de86ee8812bd..0f07ba30b1fb 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-irq.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-irq.h
@@ -27,6 +27,16 @@
 #define S3C2410_SUBSRCPND      S3C2410_IRQREG(0x018)
 #define S3C2410_INTSUBMSK      S3C2410_IRQREG(0x01C)
 
+#define S3C2416_PRIORITY_MODE1          S3C2410_IRQREG(0x030)
+#define S3C2416_PRIORITY_UPDATE1        S3C2410_IRQREG(0x034)
+#define S3C2416_SRCPND2                 S3C2410_IRQREG(0x040)
+#define S3C2416_INTMOD2                 S3C2410_IRQREG(0x044)
+#define S3C2416_INTMSK2                 S3C2410_IRQREG(0x048)
+#define S3C2416_INTPND2                 S3C2410_IRQREG(0x050)
+#define S3C2416_INTOFFSET2              S3C2410_IRQREG(0x054)
+#define S3C2416_PRIORITY_MODE2          S3C2410_IRQREG(0x070)
+#define S3C2416_PRIORITY_UPDATE2        S3C2410_IRQREG(0x074)
+
 /* mask: 0=enable, 1=disable
  * 1 bit EINT, 4=EINT4, 23=EINT23
  * EINT0,1,2,3 are not handled here.
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
new file mode 100644
index 000000000000..2f31b74974af
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
@@ -0,0 +1,30 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
+ *
+ * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
+ *      as part of OpenInkpot project
+ * Copyright (c) 2009 Promwad Innovation Company
+ *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2416 memory register definitions
+*/
+
+#ifndef __ASM_ARM_REGS_S3C2416_MEM
+#define __ASM_ARM_REGS_S3C2416_MEM
+
+#ifndef S3C2416_MEMREG
+#define S3C2416_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
+#endif
+
+#define S3C2416_BANKCFG                 S3C2416_MEMREG(0x00)
+#define S3C2416_BANKCON1                S3C2416_MEMREG(0x04)
+#define S3C2416_BANKCON2                S3C2416_MEMREG(0x08)
+#define S3C2416_BANKCON3                S3C2416_MEMREG(0x0C)
+
+#define S3C2416_REFRESH                 S3C2416_MEMREG(0x10)
+#define S3C2416_TIMEOUT                 S3C2416_MEMREG(0x14)
+
+#endif /*  __ASM_ARM_REGS_S3C2416_MEM */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
new file mode 100644
index 000000000000..e443167efb87
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
@@ -0,0 +1,24 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
+ *
+ * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
+ *      as part of OpenInkpot project
+ * Copyright (c) 2009 Promwad Innovation Company
+ *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2416 specific register definitions
+*/
+
+#ifndef __ASM_ARCH_REGS_S3C2416_H
+#define __ASM_ARCH_REGS_S3C2416_H "s3c2416"
+
+#define S3C2416_SWRST           (S3C24XX_VA_CLKPWR + 0x44)
+#define S3C2416_SWRST_RESET     (0x533C2416)
+
+/* see regs-power.h for the other registers in the power block. */
+
+#endif  /* __ASM_ARCH_REGS_S3C2416_H */
+
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
index d87ebe0cb625..08ab9dfb6ae6 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
@@ -83,8 +83,7 @@
 #define S3C2443_HCLKCON_DMA4            (1<<4)
 #define S3C2443_HCLKCON_DMA5            (1<<5)
 #define S3C2443_HCLKCON_CAMIF           (1<<8)
-#define S3C2443_HCLKCON_DISP            (1<<9)
-#define S3C2443_HCLKCON_LCDC            (1<<10)
+#define S3C2443_HCLKCON_LCDC            (1<<9)
 #define S3C2443_HCLKCON_USBH            (1<<11)
 #define S3C2443_HCLKCON_USBD            (1<<12)
 #define S3C2443_HCLKCON_HSMMC           (1<<16)
diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c2410/include/mach/uncompress.h
index 72f756c5e504..8b283f847daa 100644
--- a/arch/arm/mach-s3c2410/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c2410/include/mach/uncompress.h
@@ -40,7 +40,9 @@ static void arch_detect_cpu(void)
         cpuid &= S3C2410_GSTATUS1_IDMASK;
 
         if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
-            cpuid == S3C2410_GSTATUS1_2442) {
+            cpuid == S3C2410_GSTATUS1_2442 ||
+            cpuid == S3C2410_GSTATUS1_2416 ||
+            cpuid == S3C2410_GSTATUS1_2450) {
                 fifo_mask = S3C2440_UFSTAT_TXMASK;
                 fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
         } else {
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 7047317ed7f4..34fc05a4244b 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -56,6 +56,7 @@
 #include <plat/iic.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/gpio-cfg.h>
 
 #ifdef CONFIG_MTD_PARTITIONS
 
@@ -225,8 +226,8 @@ static void amlm5900_init_pm(void)
         } else {
                 enable_irq_wake(IRQ_EINT9);
                 /* configure the suspend/resume status pin */
-                s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
-                s3c2410_gpio_pullup(S3C2410_GPF(2), 0);
+                s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
+                s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_UP);
         }
 }
 static void __init amlm5900_init(void)
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 02b1b6220cba..c1f90f6fab42 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -61,6 +61,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/cpu-freq.h>
+#include <plat/gpio-cfg.h>
 #include <plat/audio-simtec.h>
 
 #include "usb-simtec.h"
@@ -216,15 +217,13 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
 static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
 {
         /* ensure that an nRESET is not generated on resume. */
-        s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
-
+        gpio_direction_output(S3C2410_GPA(21), 1);
         return 0;
 }
 
 static int bast_pm_resume(struct sys_device *sd)
 {
-        s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
+        s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
         return 0;
 }
 
@@ -634,7 +633,7 @@ static void __init bast_map_io(void)
 
         s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
 
-        s3c_device_hwmon.dev.platform_data = &bast_hwmon_info;
+        s3c_hwmon_set_platdata(&bast_hwmon_info);
 
         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
         s3c24xx_init_clocks(0);
@@ -658,6 +657,8 @@ static void __init bast_init(void)
         nor_simtec_init();
         simtec_audio_add(NULL, true, &bast_audio);
 
+        WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
+        
         s3c_cpufreq_setboard(&bast_cpufreq);
 }
 
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index fbedd0760941..d2a2fad7db97 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -50,6 +50,7 @@
 #include <plat/udc.h>
 #include <plat/iic.h>
 
+#include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
@@ -162,8 +163,8 @@ static struct s3c2410fb_display h1940_lcd __initdata = {
         .xres =         240,
         .yres =         320,
         .bpp =          16,
-        .left_margin =  20,
-        .right_margin = 8,
+        .left_margin =  8,
+        .right_margin = 20,
         .hsync_len =    4,
         .upper_margin = 8,
         .lower_margin = 7,
@@ -207,16 +208,16 @@ static int h1940_backlight_init(struct device *dev)
 {
         gpio_request(S3C2410_GPB(0), "Backlight");
 
-        s3c2410_gpio_setpin(S3C2410_GPB(0), 0);
-        s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
+        gpio_direction_output(S3C2410_GPB(0), 0);
+        s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE);
+        s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
 
         return 0;
 }
 
 static void h1940_backlight_exit(struct device *dev)
 {
-        s3c2410_gpio_cfgpin(S3C2410_GPB(0), 1/*S3C2410_GPB0_OUTP*/);
+        gpio_direction_output(S3C2410_GPB(0), 1);
 }
 
 static struct platform_pwm_backlight_data backlight_data = {
@@ -245,18 +246,18 @@ static void h1940_lcd_power_set(struct plat_lcd_data *pd,
 
         if (!power) {
                 /* set to 3ec */
-                s3c2410_gpio_setpin(S3C2410_GPC(0), 0);
+                gpio_direction_output(S3C2410_GPC(0), 0);
                 /* wait for 3ac */
                 do {
-                        value = s3c2410_gpio_getpin(S3C2410_GPC(6));
+                        value = gpio_get_value(S3C2410_GPC(6));
                 } while (value);
                 /* set to 38c */
-                s3c2410_gpio_setpin(S3C2410_GPC(5), 0);
+                gpio_direction_output(S3C2410_GPC(5), 0);
         } else {
                 /* Set to 3ac */
-                s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
+                gpio_direction_output(S3C2410_GPC(5), 1);
                 /* Set to 3ad */
-                s3c2410_gpio_setpin(S3C2410_GPC(0), 1);
+                gpio_direction_output(S3C2410_GPC(0), 1);
         }
 }
 
@@ -271,7 +272,6 @@ static struct platform_device h1940_lcd_powerdev = {
 };
 
 static struct platform_device *h1940_devices[] __initdata = {
-        &s3c_device_ts,
         &s3c_device_ohci,
         &s3c_device_lcd,
         &s3c_device_wdt,
@@ -285,6 +285,8 @@ static struct platform_device *h1940_devices[] __initdata = {
         &s3c_device_timer[0],
         &h1940_backlight,
         &h1940_lcd_powerdev,
+        &s3c_device_adc,
+        &s3c_device_ts,
 };
 
 static void __init h1940_map_io(void)
@@ -332,12 +334,13 @@ static void __init h1940_init(void)
         gpio_request(S3C2410_GPC(5), "LCD power");
         gpio_request(S3C2410_GPC(6), "LCD power");
 
+        gpio_direction_input(S3C2410_GPC(6));
 
         platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
 }
 
 MACHINE_START(H1940, "IPAQ-H1940")
-        /* Maintainer: Ben Dooks <ben@fluff.org> */
+        /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .phys_io        = S3C2410_PA_UART,
         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 684710f88142..41f299d983eb 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -26,6 +26,7 @@
 #include <linux/serial_core.h>
 #include <linux/timer.h>
 #include <linux/io.h>
+#include <linux/mmc/host.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -46,6 +47,7 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
+#include <plat/mci.h>
 #include <plat/s3c2410.h>
 #include <plat/udc.h>
 
@@ -86,10 +88,10 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
 {
         switch (cmd) {
         case S3C2410_UDC_P_ENABLE :
-                s3c2410_gpio_setpin(S3C2410_GPB(3), 1);
+                gpio_set_value(S3C2410_GPB(3), 1);
                 break;
         case S3C2410_UDC_P_DISABLE :
-                s3c2410_gpio_setpin(S3C2410_GPB(3), 0);
+                gpio_set_value(S3C2410_GPB(3), 0);
                 break;
         case S3C2410_UDC_P_RESET :
                 break;
@@ -172,8 +174,10 @@ static struct gpio_keys_button n35_buttons[] = {
         {
                 .gpio           = S3C2410_GPF(0),
                 .code           = KEY_POWER,
+                .type           = EV_PWR,
                 .desc           = "Power",
                 .active_low     = 0,
+                .wakeup         = 1,
         },
         {
                 .gpio           = S3C2410_GPG(9),
@@ -264,6 +268,14 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = {
         .def_trigger    = "",
 };
 
+/* This is the blue LED on the device. Originaly used to indicate GPS activity
+ * by flashing. */
+static struct s3c24xx_led_platdata n35_blue_led_pdata = {
+        .name           = "blue_led",
+        .gpio           = S3C2410_GPD(8),
+        .def_trigger    = "",
+};
+
 /* This LED is driven by the battery microcontroller, and is blinking
  * red, blinking green or solid green when the battery is low,
  * charging or full respectively.  By driving GPD9 low, it's possible
@@ -275,6 +287,13 @@ static struct s3c24xx_led_platdata n30_warning_led_pdata = {
         .def_trigger    = "",
 };
 
+static struct s3c24xx_led_platdata n35_warning_led_pdata = {
+        .name           = "warning_led",
+        .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
+        .gpio           = S3C2410_GPD(9),
+        .def_trigger    = "",
+};
+
 static struct platform_device n30_blue_led = {
         .name           = "s3c24xx_led",
         .id             = 1,
@@ -283,6 +302,14 @@ static struct platform_device n30_blue_led = {
         },
 };
 
+static struct platform_device n35_blue_led = {
+        .name           = "s3c24xx_led",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &n35_blue_led_pdata,
+        },
+};
+
 static struct platform_device n30_warning_led = {
         .name           = "s3c24xx_led",
         .id             = 2,
@@ -291,6 +318,14 @@ static struct platform_device n30_warning_led = {
         },
 };
 
+static struct platform_device n35_warning_led = {
+        .name           = "s3c24xx_led",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &n35_warning_led_pdata,
+        },
+};
+
 static struct s3c2410fb_display n30_display __initdata = {
         .type           = S3C2410_LCDCON1_TFT,
         .width          = 240,
@@ -317,13 +352,36 @@ static struct s3c2410fb_mach_info n30_fb_info __initdata = {
         .lpcsel         = 0x06,
 };
 
+static void n30_sdi_set_power(unsigned char power_mode, unsigned short vdd)
+{
+        switch (power_mode) {
+        case MMC_POWER_ON:
+        case MMC_POWER_UP:
+                gpio_set_value(S3C2410_GPG(4), 1);
+                break;
+        case MMC_POWER_OFF:
+        default:
+                gpio_set_value(S3C2410_GPG(4), 0);
+                break;
+        }
+}
+
+static struct s3c24xx_mci_pdata n30_mci_cfg __initdata = {
+        .gpio_detect    = S3C2410_GPF(1),
+        .gpio_wprotect  = S3C2410_GPG(10),
+        .ocr_avail      = MMC_VDD_32_33,
+        .set_power      = n30_sdi_set_power,
+};
+
 static struct platform_device *n30_devices[] __initdata = {
         &s3c_device_lcd,
         &s3c_device_wdt,
         &s3c_device_i2c0,
         &s3c_device_iis,
         &s3c_device_ohci,
+        &s3c_device_rtc,
         &s3c_device_usbgadget,
+        &s3c_device_sdi,
         &n30_button_device,
         &n30_blue_led,
         &n30_warning_led,
@@ -334,8 +392,12 @@ static struct platform_device *n35_devices[] __initdata = {
         &s3c_device_wdt,
         &s3c_device_i2c0,
         &s3c_device_iis,
+        &s3c_device_rtc,
         &s3c_device_usbgadget,
+        &s3c_device_sdi,
         &n35_button_device,
+        &n35_blue_led,
+        &n35_warning_led,
 };
 
 static struct s3c2410_platform_i2c __initdata n30_i2ccfg = {
@@ -490,17 +552,15 @@ static void __init n30_map_io(void)
         s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
 }
 
-static void __init n30_init_irq(void)
-{
-        s3c24xx_init_irq();
-}
-
 /* GPB3 is the line that controls the pull-up for the USB D+ line */
 
 static void __init n30_init(void)
 {
+        WARN_ON(gpio_request(S3C2410_GPG(4), "mmc power"));
+
         s3c24xx_fb_set_platdata(&n30_fb_info);
         s3c24xx_udc_set_platdata(&n30_udc_cfg);
+        s3c24xx_mci_set_platdata(&n30_mci_cfg);
         s3c_i2c0_set_platdata(&n30_i2ccfg);
 
         /* Turn off suspend on both USB ports, and switch the
@@ -532,10 +592,13 @@ static void __init n30_init(void)
                 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
                                       S3C2410_MISCCR_USBSUSPND0 |
                                       S3C2410_MISCCR_USBSUSPND1,
-                                      S3C2410_MISCCR_USBSUSPND1);
+                                      S3C2410_MISCCR_USBSUSPND0);
 
                 platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices));
         }
+
+        WARN_ON(gpio_request(S3C2410_GPB(3), "udc pup"));
+        gpio_direction_output(S3C2410_GPB(3), 0);
 }
 
 MACHINE_START(N30, "Acer-N30")
@@ -547,7 +610,7 @@ MACHINE_START(N30, "Acer-N30")
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .timer          = &s3c24xx_timer,
         .init_machine   = n30_init,
-        .init_irq       = n30_init_irq,
+        .init_irq       = s3c24xx_init_irq,
         .map_io         = n30_map_io,
 MACHINE_END
 
@@ -559,6 +622,6 @@ MACHINE_START(N35, "Acer-N35")
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .timer          = &s3c24xx_timer,
         .init_machine   = n30_init,
-        .init_irq       = n30_init_irq,
+        .init_irq       = s3c24xx_init_irq,
         .map_io         = n30_map_io,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 92a4ec375d82..d0e87b6e2e0f 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -58,6 +58,7 @@
 #include <plat/iic.h>
 
 #include <plat/common-smdk.h>
+#include <plat/gpio-cfg.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
@@ -219,10 +220,10 @@ static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
 {
         switch (cs) {
         case BITBANG_CS_ACTIVE:
-                s3c2410_gpio_setpin(S3C2410_GPB(5), 0);
+                gpio_set_value(S3C2410_GPB(5), 0);
                 break;
         case BITBANG_CS_INACTIVE:
-                s3c2410_gpio_setpin(S3C2410_GPB(5), 1);
+                gpio_set_value(S3C2410_GPB(5), 1);
                 break;
         }
 }
@@ -347,13 +348,14 @@ static void __init qt2410_machine_init(void)
         }
         s3c24xx_fb_set_platdata(&qt2410_fb_info);
 
-        s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
         s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
 
         s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
         s3c_i2c0_set_platdata(NULL);
 
-        s3c2410_gpio_cfgpin(S3C2410_GPB(5), S3C2410_GPIO_OUTPUT);
+        WARN_ON(gpio_request(S3C2410_GPB(5), "spi cs"));
+        gpio_direction_output(S3C2410_GPB(5), 1);
 
         platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
         s3c_pm_init();
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 9051f0d31123..d540d79dd264 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -357,8 +357,7 @@ static struct clk *vr1000_clocks[] __initdata = {
 
 static void vr1000_power_off(void)
 {
-        s3c2410_gpio_cfgpin(S3C2410_GPB(9), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_setpin(S3C2410_GPB(9), 1);
+        gpio_direction_output(S3C2410_GPB(9), 1);
 }
 
 static void __init vr1000_map_io(void)
@@ -395,6 +394,8 @@ static void __init vr1000_init(void)
 
         nor_simtec_init();
         simtec_audio_add(NULL, true, NULL);
+
+        WARN_ON(gpio_request(S3C2410_GPB(9), "power off"));
 }
 
 MACHINE_START(VR1000, "Thorcom-VR1000")
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index 966119c8efee..725636fc4dc3 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -60,10 +60,10 @@ static void s3c2410_pm_prepare(void)
                 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
         }
 
-        /* the RX3715 uses similar code and the same H1940 and the
+        /* RX3715 and RX1950 use similar to H1940 code and the
          * same offsets for resume and checksum pointers */
 
-        if (machine_is_rx3715()) {
+        if (machine_is_rx3715() || machine_is_rx1950()) {
                 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
                 unsigned long ptr;
                 unsigned long calc = 0;
@@ -79,6 +79,17 @@ static void s3c2410_pm_prepare(void)
         if ( machine_is_aml_m5900() )
                 s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
 
+        if (machine_is_rx1950()) {
+                /* According to S3C2442 user's manual, page 7-17,
+                 * when the system is operating in NAND boot mode,
+                 * the hardware pin configuration - EINT[23:21] –
+                 * must be set as input for starting up after
+                 * wakeup from sleep mode
+                 */
+                s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT);
+                s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT);
+                s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT);
+        }
 }
 
 static int s3c2410_pm_resume(struct sys_device *dev)
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index 91ba42f688ac..adc90a3c5890 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -16,6 +16,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/clk.h>
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
@@ -40,6 +41,10 @@
 #include <plat/clock.h>
 #include <plat/pll.h>
 
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+
 /* Initial IO mappings */
 
 static struct map_desc s3c2410_iodesc[] __initdata = {
@@ -65,6 +70,9 @@ void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 
 void __init s3c2410_map_io(void)
 {
+        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
+        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
+
         iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
 }
 
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index 9a8c0657ae50..cef6a65637bd 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -16,7 +16,8 @@ config CPU_S3C2412
 config CPU_S3C2412_ONLY
         bool
         depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \
-                   !CPU_S3C2440 && !CPU_S3C2442 && !CPU_S3C2443 && CPU_S3C2412
+                   !CPU_2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
+                   !CPU_S3C2443 && CPU_S3C2412
         default y if CPU_S3C2412
 
 config S3C2412_DMA
diff --git a/arch/arm/mach-s3c2412/gpio.c b/arch/arm/mach-s3c2412/gpio.c
index f7afece7fc38..3404a876b33e 100644
--- a/arch/arm/mach-s3c2412/gpio.c
+++ b/arch/arm/mach-s3c2412/gpio.c
@@ -16,41 +16,43 @@
 #include <linux/types.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
+#include <linux/gpio.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include <mach/regs-gpio.h>
-
 #include <mach/hardware.h>
 
+#include <plat/gpio-core.h>
+
 int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state)
 {
-        void __iomem *base = S3C24XX_GPIO_BASE(pin);
-        unsigned long offs = S3C2410_GPIO_OFFSET(pin);
+        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+        unsigned long offs = pin - chip->chip.base;
         unsigned long flags;
         unsigned long slpcon;
 
         offs *= 2;
 
-        if (pin < S3C2410_GPIO_BANKB)
+        if (pin < S3C2410_GPB(0))
                 return -EINVAL;
 
-        if (pin >= S3C2410_GPIO_BANKF &&
-            pin <= S3C2410_GPIO_BANKG)
+        if (pin >= S3C2410_GPF(0) &&
+            pin <= S3C2410_GPG(16))
                 return -EINVAL;
 
-        if (pin > (S3C2410_GPIO_BANKH + 32))
+        if (pin > S3C2410_GPH(16))
                 return -EINVAL;
 
         local_irq_save(flags);
 
-        slpcon = __raw_readl(base + 0x0C);
+        slpcon = __raw_readl(chip->base + 0x0C);
 
         slpcon &= ~(3 << offs);
         slpcon |= state << offs;
 
-        __raw_writel(slpcon, base + 0x0C);
+        __raw_writel(slpcon, chip->base + 0x0C);
 
         local_irq_restore(flags);
 
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 14f4798291aa..478f4b4606c2 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -48,6 +48,7 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
 
+#include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
@@ -357,8 +358,7 @@ static void jive_lcm_reset(unsigned int set)
 {
         printk(KERN_DEBUG "%s(%d)\n", __func__, set);
 
-        s3c2410_gpio_setpin(S3C2410_GPG(13), set);
-        s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT);
+        gpio_set_value(S3C2410_GPG(13), set);
 }
 
 #undef LCD_UPPER_MARGIN
@@ -391,7 +391,7 @@ static struct ili9320_platdata jive_lcm_config = {
 
 static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
 {
-        s3c2410_gpio_setpin(S3C2410_GPB(7), cs ? 0 : 1);
+        gpio_set_value(S3C2410_GPB(7), cs ? 0 : 1);
 }
 
 static struct s3c2410_spigpio_info jive_lcd_spi = {
@@ -413,7 +413,7 @@ static struct platform_device jive_device_lcdspi = {
 
 static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
 {
-        s3c2410_gpio_setpin(S3C2410_GPH(10), cs ? 0 : 1);
+        gpio_set_value(S3C2410_GPH(10), cs ? 0 : 1);
 }
 
 static struct s3c2410_spigpio_info jive_wm8750_spi = {
@@ -531,7 +531,7 @@ static void jive_power_off(void)
         printk(KERN_INFO "powering system down...\n");
 
         s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
 }
 
 static void __init jive_machine_init(void)
@@ -636,22 +636,22 @@ static void __init jive_machine_init(void)
 
         /* initialise the spi */
 
-        s3c2410_gpio_setpin(S3C2410_GPG(13), 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT);
+        gpio_request(S3C2410_GPG(13), "lcm reset");
+        gpio_direction_output(S3C2410_GPG(13), 0);
 
-        s3c2410_gpio_setpin(S3C2410_GPB(7), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPB(7), S3C2410_GPIO_OUTPUT);
+        gpio_request(S3C2410_GPB(7), "jive spi");
+        gpio_direction_output(S3C2410_GPB(7), 1);
 
         s3c2410_gpio_setpin(S3C2410_GPB(6), 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
 
         s3c2410_gpio_setpin(S3C2410_GPG(8), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
 
         /* initialise the WM8750 spi */
 
-        s3c2410_gpio_setpin(S3C2410_GPH(10), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPH(10), S3C2410_GPIO_OUTPUT);
+        gpio_request(S3C2410_GPH(10), "jive wm8750 spi");
+        gpio_direction_output(S3C2410_GPH(10), 1);
 
         /* Turn off suspend on both USB ports, and switch the
          * selectable USB port to USB device mode. */
@@ -674,7 +674,7 @@ static void __init jive_machine_init(void)
 }
 
 MACHINE_START(JIVE, "JIVE")
-        /* Maintainer: Ben Dooks <ben@fluff.org> */
+        /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .phys_io        = S3C2410_PA_UART,
         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index 0392065af1af..ba93a356a839 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -85,10 +85,10 @@ static void smdk2413_udc_pullup(enum s3c2410_udc_cmd_e cmd)
         switch (cmd)
         {
                 case S3C2410_UDC_P_ENABLE :
-                        s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
+                        gpio_set_value(S3C2410_GPF(2), 1);
                         break;
                 case S3C2410_UDC_P_DISABLE :
-                        s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
+                        gpio_set_value(S3C2410_GPF(2), 0);
                         break;
                 case S3C2410_UDC_P_RESET :
                         break;
@@ -134,8 +134,8 @@ static void __init smdk2413_machine_init(void)
 {       /* Turn off suspend on both USB ports, and switch the
          * selectable USB port to USB device mode. */
 
-        s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
+        WARN_ON(gpio_request(S3C2410_GPF(2), "udc pull"));
+        gpio_direction_output(S3C2410_GPF(2), 0);
 
         s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
                               S3C2410_MISCCR_USBSUSPND0 |
@@ -150,7 +150,7 @@ static void __init smdk2413_machine_init(void)
 }
 
 MACHINE_START(S3C2413, "S3C2413")
-        /* Maintainer: Ben Dooks <ben@fluff.org> */
+        /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .phys_io        = S3C2410_PA_UART,
         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
@@ -163,7 +163,7 @@ MACHINE_START(S3C2413, "S3C2413")
 MACHINE_END
 
 MACHINE_START(SMDK2412, "SMDK2412")
-        /* Maintainer: Ben Dooks <ben@fluff.org> */
+        /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .phys_io        = S3C2410_PA_UART,
         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
@@ -176,7 +176,7 @@ MACHINE_START(SMDK2412, "SMDK2412")
 MACHINE_END
 
 MACHINE_START(SMDK2413, "SMDK2413")
-        /* Maintainer: Ben Dooks <ben@fluff.org> */
+        /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .phys_io        = S3C2410_PA_UART,
         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
new file mode 100644
index 000000000000..657e4fe17f39
--- /dev/null
+++ b/arch/arm/mach-s3c2416/Kconfig
@@ -0,0 +1,39 @@
+# arch/arm/mach-s3c2416/Kconfig
+#
+# Copyright 2009 Yauhen Kharuzhy <jekhor@gmail.com>
+#
+# Licensed under GPLv2
+
+# note, this also supports the S3C2450 which is so similar it has the same
+# ID code as the S3C2416.
+
+config CPU_S3C2416
+        bool
+        depends on ARCH_S3C2410
+        select CPU_ARM926T
+        select S3C2416_DMA if S3C2410_DMA
+        select CPU_LLSERIAL_S3C2440
+        select S3C_GPIO_PULL_UPDOWN
+        select SAMSUNG_CLKSRC
+        select S3C2443_CLOCK
+        help
+          Support for the S3C2416 SoC from the S3C24XX line
+
+config S3C2416_DMA
+        bool
+        depends on CPU_S3C2416
+        help
+          Internal config node for S3C2416 DMA support
+
+menu "S3C2416 Machines"
+
+config MACH_SMDK2416
+        bool "SMDK2416"
+        select CPU_S3C2416
+        select S3C_DEV_FB
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        help
+          Say Y here if you are using an SMDK2416
+
+endmenu
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
new file mode 100644
index 000000000000..6c12c7bf40ad
--- /dev/null
+++ b/arch/arm/mach-s3c2416/Makefile
@@ -0,0 +1,19 @@
+# arch/arm/mach-s3c2416/Makefile
+#
+# Copyright 2009 Yauhen Kharuzhy <jekhor@gmail.com>
+#
+# Licensed under GPLv2
+
+obj-y                           :=
+obj-m                           :=
+obj-n                           :=
+obj-                            :=
+
+obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o clock.o
+obj-$(CONFIG_CPU_S3C2416)       += irq.o
+
+#obj-$(CONFIG_S3C2416_DMA)      += dma.o
+
+# Machine support
+
+obj-$(CONFIG_MACH_SMDK2416)     += mach-smdk2416.o
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
new file mode 100644
index 000000000000..7ccf5a2a2bfc
--- /dev/null
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -0,0 +1,135 @@
+/* linux/arch/arm/mach-s3c2416/clock.c
+ *
+ * Copyright (c) 2010 Simtec Electronics
+ * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
+ *
+ * S3C2416 Clock control support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/clk.h>
+
+#include <plat/s3c2416.h>
+#include <plat/s3c2443.h>
+#include <plat/clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/cpu.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/pll6553x.h>
+#include <plat/pll.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/regs-clock.h>
+#include <mach/regs-s3c2443-clock.h>
+
+static unsigned int armdiv[8] = {
+        [0] = 1,
+        [1] = 2,
+        [2] = 3,
+        [3] = 4,
+        [5] = 6,
+        [7] = 8,
+};
+
+/* ID to hardware numbering, 0 is HSMMC1, 1 is HSMMC0 */
+static struct clksrc_clk hsmmc_div[] = {
+        [0] = {
+                .clk = {
+                        .name   = "hsmmc-div",
+                        .id     = 1,
+                        .parent = &clk_esysclk.clk,
+                },
+                .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
+        },
+        [1] = {
+                .clk = {
+                        .name   = "hsmmc-div",
+                        .id     = 0,
+                        .parent = &clk_esysclk.clk,
+                },
+                .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
+        },
+};
+
+static struct clksrc_clk hsmmc_mux[] = {
+        [0] = {
+                .clk    = {
+                        .id     = 1,
+                        .name   = "hsmmc-if",
+                        .ctrlbit = (1 << 6),
+                        .enable = s3c2443_clkcon_enable_s,
+                },
+                .sources = &(struct clksrc_sources) {
+                        .nr_sources = 2,
+                        .sources = (struct clk *[]) {
+                                [0] = &hsmmc_div[0].clk,
+                                [1] = NULL, /* to fix */
+                        },
+                },
+                .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
+        },
+        [1] = {
+                .clk    = {
+                        .id     = 0,
+                        .name   = "hsmmc-if",
+                        .ctrlbit = (1 << 12),
+                        .enable = s3c2443_clkcon_enable_s,
+                },
+                .sources = &(struct clksrc_sources) {
+                        .nr_sources = 2,
+                        .sources = (struct clk *[]) {
+                                [0] = &hsmmc_div[1].clk,
+                                [1] = NULL, /* to fix */
+                        },
+                },
+                .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
+        },
+};
+
+
+static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
+{
+        clkcon0 &= 7 << S3C2443_CLKDIV0_ARMDIV_SHIFT;
+
+        return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
+}
+
+void __init_or_cpufreq s3c2416_setup_clocks(void)
+{
+        s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div);
+}
+
+
+static struct clksrc_clk *clksrcs[] __initdata = {
+        &hsmmc_div[0],
+        &hsmmc_div[1],
+        &hsmmc_mux[0],
+        &hsmmc_mux[1],
+};
+
+void __init s3c2416_init_clocks(int xtal)
+{
+        u32 epllcon = __raw_readl(S3C2443_EPLLCON);
+        u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
+        int ptr;
+
+        /* s3c2416 EPLL compatible with s3c64xx */
+        clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
+
+        clk_epll.parent = &clk_epllref.clk;
+
+        s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div);
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
+                s3c_register_clksrc(clksrcs[ptr], 1);
+
+        s3c_pwmclk_init();
+
+}
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c
new file mode 100644
index 000000000000..89f521d59d06
--- /dev/null
+++ b/arch/arm/mach-s3c2416/irq.c
@@ -0,0 +1,254 @@
+/* linux/arch/arm/mach-s3c2416/irq.c
+ *
+ * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
+ *      as part of OpenInkpot project
+ * Copyright (c) 2009 Promwad Innovation Company
+ *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+#include <asm/mach/irq.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/irq.h>
+
+#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
+
+static inline void s3c2416_irq_demux(unsigned int irq, unsigned int len)
+{
+        unsigned int subsrc, submsk;
+        unsigned int end;
+
+        /* read the current pending interrupts, and the mask
+         * for what it is available */
+
+        subsrc = __raw_readl(S3C2410_SUBSRCPND);
+        submsk = __raw_readl(S3C2410_INTSUBMSK);
+
+        subsrc  &= ~submsk;
+        subsrc >>= (irq - S3C2410_IRQSUB(0));
+        subsrc  &= (1 << len)-1;
+
+        end = len + irq;
+
+        for (; irq < end && subsrc; irq++) {
+                if (subsrc & 1)
+                        generic_handle_irq(irq);
+
+                subsrc >>= 1;
+        }
+}
+
+/* WDT/AC97 sub interrupts */
+
+static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
+{
+        s3c2416_irq_demux(IRQ_S3C2443_WDT, 4);
+}
+
+#define INTMSK_WDTAC97  (1UL << (IRQ_WDT - IRQ_EINT0))
+#define SUBMSK_WDTAC97  INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
+
+static void s3c2416_irq_wdtac97_mask(unsigned int irqno)
+{
+        s3c_irqsub_mask(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
+}
+
+static void s3c2416_irq_wdtac97_unmask(unsigned int irqno)
+{
+        s3c_irqsub_unmask(irqno, INTMSK_WDTAC97);
+}
+
+static void s3c2416_irq_wdtac97_ack(unsigned int irqno)
+{
+        s3c_irqsub_maskack(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
+}
+
+static struct irq_chip s3c2416_irq_wdtac97 = {
+        .mask       = s3c2416_irq_wdtac97_mask,
+        .unmask     = s3c2416_irq_wdtac97_unmask,
+        .ack        = s3c2416_irq_wdtac97_ack,
+};
+
+
+/* LCD sub interrupts */
+
+static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
+{
+        s3c2416_irq_demux(IRQ_S3C2443_LCD1, 4);
+}
+
+#define INTMSK_LCD      (1UL << (IRQ_LCD - IRQ_EINT0))
+#define SUBMSK_LCD      INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
+
+static void s3c2416_irq_lcd_mask(unsigned int irqno)
+{
+        s3c_irqsub_mask(irqno, INTMSK_LCD, SUBMSK_LCD);
+}
+
+static void s3c2416_irq_lcd_unmask(unsigned int irqno)
+{
+        s3c_irqsub_unmask(irqno, INTMSK_LCD);
+}
+
+static void s3c2416_irq_lcd_ack(unsigned int irqno)
+{
+        s3c_irqsub_maskack(irqno, INTMSK_LCD, SUBMSK_LCD);
+}
+
+static struct irq_chip s3c2416_irq_lcd = {
+        .mask       = s3c2416_irq_lcd_mask,
+        .unmask     = s3c2416_irq_lcd_unmask,
+        .ack        = s3c2416_irq_lcd_ack,
+};
+
+
+/* DMA sub interrupts */
+
+static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
+{
+        s3c2416_irq_demux(IRQ_S3C2443_DMA0, 6);
+}
+
+#define INTMSK_DMA      (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
+#define SUBMSK_DMA      INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
+
+
+static void s3c2416_irq_dma_mask(unsigned int irqno)
+{
+        s3c_irqsub_mask(irqno, INTMSK_DMA, SUBMSK_DMA);
+}
+
+static void s3c2416_irq_dma_unmask(unsigned int irqno)
+{
+        s3c_irqsub_unmask(irqno, INTMSK_DMA);
+}
+
+static void s3c2416_irq_dma_ack(unsigned int irqno)
+{
+        s3c_irqsub_maskack(irqno, INTMSK_DMA, SUBMSK_DMA);
+}
+
+static struct irq_chip s3c2416_irq_dma = {
+        .mask       = s3c2416_irq_dma_mask,
+        .unmask     = s3c2416_irq_dma_unmask,
+        .ack        = s3c2416_irq_dma_ack,
+};
+
+
+/* UART3 sub interrupts */
+
+static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
+{
+        s3c2416_irq_demux(IRQ_S3C2443_UART3, 3);
+}
+
+#define INTMSK_UART3    (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
+#define SUBMSK_UART3    (0xf << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
+
+
+static void s3c2416_irq_uart3_mask(unsigned int irqno)
+{
+        s3c_irqsub_mask(irqno, INTMSK_UART3, SUBMSK_UART3);
+}
+
+static void s3c2416_irq_uart3_unmask(unsigned int irqno)
+{
+        s3c_irqsub_unmask(irqno, INTMSK_UART3);
+}
+
+static void s3c2416_irq_uart3_ack(unsigned int irqno)
+{
+        s3c_irqsub_maskack(irqno, INTMSK_UART3, SUBMSK_UART3);
+}
+
+static struct irq_chip s3c2416_irq_uart3 = {
+        .mask       = s3c2416_irq_uart3_mask,
+        .unmask     = s3c2416_irq_uart3_unmask,
+        .ack        = s3c2416_irq_uart3_ack,
+};
+
+
+/* IRQ initialisation code */
+
+static int __init s3c2416_add_sub(unsigned int base,
+                                   void (*demux)(unsigned int,
+                                                 struct irq_desc *),
+                                   struct irq_chip *chip,
+                                   unsigned int start, unsigned int end)
+{
+        unsigned int irqno;
+
+        set_irq_chip(base, &s3c_irq_level_chip);
+        set_irq_handler(base, handle_level_irq);
+        set_irq_chained_handler(base, demux);
+
+        for (irqno = start; irqno <= end; irqno++) {
+                set_irq_chip(irqno, chip);
+                set_irq_handler(irqno, handle_level_irq);
+                set_irq_flags(irqno, IRQF_VALID);
+        }
+
+        return 0;
+}
+
+static int __init s3c2416_irq_add(struct sys_device *sysdev)
+{
+        printk(KERN_INFO "S3C2416: IRQ Support\n");
+
+        s3c2416_add_sub(IRQ_LCD, s3c2416_irq_demux_lcd, &s3c2416_irq_lcd,
+                        IRQ_S3C2443_LCD2, IRQ_S3C2443_LCD4);
+
+        s3c2416_add_sub(IRQ_S3C2443_DMA, s3c2416_irq_demux_dma,
+                        &s3c2416_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
+
+        s3c2416_add_sub(IRQ_S3C2443_UART3, s3c2416_irq_demux_uart3,
+                        &s3c2416_irq_uart3,
+                        IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
+
+        s3c2416_add_sub(IRQ_WDT, s3c2416_irq_demux_wdtac97,
+                        &s3c2416_irq_wdtac97,
+                        IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
+
+        return 0;
+}
+
+static struct sysdev_driver s3c2416_irq_driver = {
+        .add            = s3c2416_irq_add,
+};
+
+static int __init s3c2416_irq_init(void)
+{
+        return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_irq_driver);
+}
+
+arch_initcall(s3c2416_irq_init);
+
diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
new file mode 100644
index 000000000000..5fc3f67ef265
--- /dev/null
+++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
@@ -0,0 +1,206 @@
+/* linux/arch/arm/mach-s3c2416/mach-hanlin_v3c.c
+ *
+ * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
+ *      as part of OpenInkpot project
+ * Copyright (c) 2009 Promwad Innovation Company
+ *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/mtd/partitions.h>
+#include <linux/gpio.h>
+#include <linux/fb.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-lcd.h>
+
+#include <mach/idle.h>
+#include <mach/leds-gpio.h>
+#include <plat/iic.h>
+
+#include <plat/s3c2416.h>
+#include <plat/gpio-cfg.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/nand.h>
+
+#include <plat/regs-fb-v4.h>
+#include <plat/fb.h>
+
+#include <plat/common-smdk.h>
+
+static struct map_desc smdk2416_iodesc[] __initdata = {
+        /* ISA IO Space map (memory space selected by A24) */
+
+        {
+                .virtual        = (u32)S3C24XX_VA_ISA_WORD,
+                .pfn            = __phys_to_pfn(S3C2410_CS2),
+                .length         = 0x10000,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
+                .pfn            = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
+                .length         = SZ_4M,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (u32)S3C24XX_VA_ISA_BYTE,
+                .pfn            = __phys_to_pfn(S3C2410_CS2),
+                .length         = 0x10000,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (u32)S3C24XX_VA_ISA_BYTE + 0x10000,
+                .pfn            = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
+                .length         = SZ_4M,
+                .type           = MT_DEVICE,
+        }
+};
+
+#define UCON (S3C2410_UCON_DEFAULT      | \
+                S3C2440_UCON_PCLK       | \
+                S3C2443_UCON_RXERR_IRQEN)
+
+#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
+
+#define UFCON (S3C2410_UFCON_RXTRIG8    | \
+                S3C2410_UFCON_FIFOMODE  | \
+                S3C2440_UFCON_TXTRIG16)
+
+static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        /* IR port */
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON | 0x50,
+                .ufcon       = UFCON,
+        }
+};
+
+struct s3c_fb_pd_win smdk2416_fb_win[] = {
+        [0] = {
+                /* think this is the same as the smdk6410 */
+                .win_mode       = {
+                        .pixclock       = 41094,
+                        .left_margin    = 8,
+                        .right_margin   = 13,
+                        .upper_margin   = 7,
+                        .lower_margin   = 5,
+                        .hsync_len      = 3,
+                        .vsync_len      = 1,
+                        .xres           = 800,
+                        .yres           = 480,
+                },
+                .default_bpp    = 16,
+                .max_bpp        = 32,
+        },
+};
+
+static void s3c2416_fb_gpio_setup_24bpp(void)
+{
+        unsigned int gpio;
+
+        for (gpio = S3C2410_GPC(1); gpio <= S3C2410_GPC(4); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+
+        for (gpio = S3C2410_GPC(8); gpio <= S3C2410_GPC(15); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+
+        for (gpio = S3C2410_GPD(0); gpio <= S3C2410_GPD(15); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+}
+
+static struct s3c_fb_platdata smdk2416_fb_platdata = {
+        .win[0]         = &smdk2416_fb_win[0],
+        .setup_gpio     = s3c2416_fb_gpio_setup_24bpp,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+};
+
+static struct platform_device *smdk2416_devices[] __initdata = {
+        &s3c_device_fb,
+        &s3c_device_wdt,
+        &s3c_device_ohci,
+        &s3c_device_i2c0,
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc1,
+};
+
+static void __init smdk2416_map_io(void)
+{
+        s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
+}
+
+static void __init smdk2416_machine_init(void)
+{
+        s3c_i2c0_set_platdata(NULL);
+        s3c_fb_set_platdata(&smdk2416_fb_platdata);
+
+        gpio_request(S3C2410_GPB(4), "USBHost Power");
+        gpio_direction_output(S3C2410_GPB(4), 1);
+
+        gpio_request(S3C2410_GPB(3), "Display Power");
+        gpio_direction_output(S3C2410_GPB(3), 1);
+
+        gpio_request(S3C2410_GPB(1), "Display Reset");
+        gpio_direction_output(S3C2410_GPB(1), 1);
+
+        platform_add_devices(smdk2416_devices, ARRAY_SIZE(smdk2416_devices));
+        smdk_machine_init();
+}
+
+MACHINE_START(SMDK2416, "SMDK2416")
+        /* Maintainer: Yauhen Kharuzhy <jekhor@gmail.com> */
+        .phys_io        = S3C2410_PA_UART,
+        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+
+        .init_irq       = s3c24xx_init_irq,
+        .map_io         = smdk2416_map_io,
+        .init_machine   = smdk2416_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
new file mode 100644
index 000000000000..35dabccd0ac2
--- /dev/null
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -0,0 +1,130 @@
+/* linux/arch/arm/mach-s3c2416/s3c2416.c
+ *
+ * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
+ *      as part of OpenInkpot project
+ * Copyright (c) 2009 Promwad Innovation Company
+ *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
+ *
+ * Samsung S3C2416 Mobile CPU support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/sysdev.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <asm/proc-fns.h>
+#include <asm/irq.h>
+
+#include <mach/reset.h>
+#include <mach/idle.h>
+#include <mach/regs-s3c2443-clock.h>
+
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+#include <plat/s3c2416.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+#include <plat/iic-core.h>
+
+static struct map_desc s3c2416_iodesc[] __initdata = {
+        IODESC_ENT(WATCHDOG),
+        IODESC_ENT(CLKPWR),
+        IODESC_ENT(TIMER),
+};
+
+struct sysdev_class s3c2416_sysclass = {
+        .name = "s3c2416-core",
+};
+
+static struct sys_device s3c2416_sysdev = {
+        .cls            = &s3c2416_sysclass,
+};
+
+static void s3c2416_hard_reset(void)
+{
+        __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
+}
+
+int __init s3c2416_init(void)
+{
+        printk(KERN_INFO "S3C2416: Initializing architecture\n");
+
+        s3c24xx_reset_hook = s3c2416_hard_reset;
+        /* s3c24xx_idle = s3c2416_idle; */
+
+        /* change WDT IRQ number */
+        s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
+        s3c_device_wdt.resource[1].end   = IRQ_S3C2443_WDT;
+
+        /* the i2c devices are directly compatible with s3c2440 */
+        s3c_i2c0_setname("s3c2440-i2c");
+        s3c_i2c1_setname("s3c2440-i2c");
+
+        s3c_device_fb.name = "s3c2443-fb";
+
+        return sysdev_register(&s3c2416_sysdev);
+}
+
+void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
+
+        s3c_device_nand.name = "s3c2416-nand";
+}
+
+/* s3c2416_map_io
+ *
+ * register the standard cpu IO areas, and any passed in from the
+ * machine specific initialisation.
+ */
+
+void __init s3c2416_map_io(void)
+{
+        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown;
+        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown;
+
+        iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
+}
+
+/* need to register class before we actually register the device, and
+ * we also need to ensure that it has been initialised before any of the
+ * drivers even try to use it (even if not on an s3c2416 based system)
+ * as a driver which may support both 2443 and 2440 may try and use it.
+*/
+
+static int __init s3c2416_core_init(void)
+{
+        return sysdev_class_register(&s3c2416_sysclass);
+}
+
+core_initcall(s3c2416_core_init);
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index 7f465265cf04..cd8e7de388f0 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -6,6 +6,7 @@ config CPU_S3C2440
         bool
         depends on ARCH_S3C2410
         select CPU_ARM920T
+        select S3C_GPIO_PULL_UP
         select S3C2410_CLOCK
         select S3C2410_PM if PM
         select S3C2410_GPIO
@@ -187,4 +188,17 @@ config MACH_MINI2440
           Say Y here to select support for the MINI2440. Is a 10cm x 10cm board
           available via various sources. It can come with a 3.5" or 7" touch LCD.
 
+config MACH_RX1950
+        bool "HP iPAQ rx1950"
+        select CPU_S3C2442
+        select S3C24XX_DCLK
+        select PM_H1940 if PM
+        select I2C
+        select S3C2410_PWM
+        select S3C_DEV_NAND
+        select S3C2410_IOTIMING if S3C2440_CPUFREQ
+        select S3C2440_XTAL_16934400
+        help
+           Say Y here if you're using HP iPAQ rx1950
+
 endmenu
diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile
index c85ba32d8956..d5440fa34b04 100644
--- a/arch/arm/mach-s3c2440/Makefile
+++ b/arch/arm/mach-s3c2440/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
 obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
 obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o
 obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o
+obj-$(CONFIG_MACH_RX1950) += mach-rx1950.o
 
 # extra machine support
 
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index 571b17683d96..a76bcda210ad 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -53,6 +53,7 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
 
+#include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
@@ -102,10 +103,10 @@ static void mini2440_udc_pullup(enum s3c2410_udc_cmd_e cmd)
 
         switch (cmd) {
                 case S3C2410_UDC_P_ENABLE :
-                        s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
+                        gpio_set_value(S3C2410_GPC(5), 1);
                         break;
                 case S3C2410_UDC_P_DISABLE :
-                        s3c2410_gpio_setpin(S3C2410_GPC(5), 0);
+                        gpio_set_value(S3C2410_GPC(5), 0);
                         break;
                 case S3C2410_UDC_P_RESET :
                         break;
@@ -632,25 +633,25 @@ static void __init mini2440_init(void)
         mini2440_parse_features(&features, mini2440_features_str);
 
         /* turn LCD on */
-        s3c2410_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND);
+        s3c_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND);
 
         /* Turn the backlight early on */
-        s3c2410_gpio_setpin(S3C2410_GPG(4), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPG(4), S3C2410_GPIO_OUTPUT);
+        WARN_ON(gpio_request(S3C2410_GPG(4), "backlight"));
+        gpio_direction_output(S3C2410_GPG(4), 1);
 
         /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */
-        s3c2410_gpio_pullup(S3C2410_GPB(1), 0);
+        s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP);
         s3c2410_gpio_setpin(S3C2410_GPB(1), 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT);
+        s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT);
 
         /* Make sure the D+ pullup pin is output */
-        s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
+        WARN_ON(gpio_request(S3C2410_GPC(5), "udc pup"));
+        gpio_direction_output(S3C2410_GPC(5), 0);
 
         /* mark the key as input, without pullups (there is one on the board) */
         for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) {
-                s3c2410_gpio_pullup(mini2440_buttons[i].gpio, 0);
-                s3c2410_gpio_cfgpin(mini2440_buttons[i].gpio,
-                                        S3C2410_GPIO_INPUT);
+                s3c_gpio_setpull(mini2440_buttons[i].gpio, S3C_GPIO_PULL_UP);
+                s3c_gpio_cfgpin(mini2440_buttons[i].gpio, S3C2410_GPIO_INPUT);
         }
         if (features.lcd_index != -1) {
                 int li;
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 342041593f22..3ff62de45fde 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -40,6 +40,7 @@
 #include <plat/regs-serial.h>
 #include <plat/iic.h>
 
+#include <plat/gpio-cfg.h>
 #include <plat/s3c2410.h>
 #include <plat/s3c244x.h>
 #include <plat/clock.h>
@@ -122,15 +123,15 @@ static void __init nexcoder_sensorboard_init(void)
 {
         // Initialize SCCB bus
         s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL
-        s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT);
         s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA
-        s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT);
 
         // Power up the sensor board
         s3c2410_gpio_setpin(S3C2410_GPF(1), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
+        s3c_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
         s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
+        s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
 }
 
 static void __init nexcoder_map_io(void)
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index f35371db33f5..319458da71a0 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -49,6 +49,7 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
 
+#include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
@@ -298,7 +299,7 @@ static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
 
         /* ensure that an nRESET is not generated on resume. */
         s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
 
         return 0;
 }
@@ -310,7 +311,7 @@ static int osiris_pm_resume(struct sys_device *sd)
 
         __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
 
-        s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
+        s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
 
         return 0;
 }
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
new file mode 100644
index 000000000000..8603b577a24b
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -0,0 +1,582 @@
+/* linux/arch/arm/mach-s3c2440/mach-rx1950.c
+ *
+ * Copyright (c) 2006-2009 Victor Chukhantsev, Denis Grigoriev,
+ * Copyright (c) 2007-2010 Vasily Khoruzhick
+ *
+ * based on smdk2440 written by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/delay.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+#include <linux/sysdev.h>
+#include <linux/pwm_backlight.h>
+#include <linux/pwm.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <linux/mmc/host.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+
+#include <mach/regs-gpio.h>
+#include <mach/regs-gpioj.h>
+#include <mach/h1940.h>
+#include <mach/fb.h>
+
+#include <plat/clock.h>
+#include <plat/regs-serial.h>
+#include <plat/regs-iic.h>
+#include <plat/mci.h>
+#include <plat/udc.h>
+#include <plat/nand.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/irq.h>
+#include <plat/ts.h>
+
+#define LCD_PWM_PERIOD 192960
+#define LCD_PWM_DUTY 127353
+
+static struct map_desc rx1950_iodesc[] __initdata = {
+};
+
+static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = {
+        [0] = {
+               .name = "fclk",
+               .divisor = 0x0a,
+               .min_baud = 0,
+               .max_baud = 0,
+        },
+};
+
+static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
+        [0] = {
+               .hwport = 0,
+               .flags = 0,
+               .ucon = 0x3c5,
+               .ulcon = 0x03,
+               .ufcon = 0x51,
+               .clocks = rx1950_serial_clocks,
+               .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
+        },
+        [1] = {
+               .hwport = 1,
+               .flags = 0,
+               .ucon = 0x3c5,
+               .ulcon = 0x03,
+               .ufcon = 0x51,
+               .clocks = rx1950_serial_clocks,
+               .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
+        },
+        /* IR port */
+        [2] = {
+               .hwport = 2,
+               .flags = 0,
+               .ucon = 0x3c5,
+               .ulcon = 0x43,
+               .ufcon = 0xf1,
+               .clocks = rx1950_serial_clocks,
+               .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
+        },
+};
+
+static struct s3c2410fb_display rx1950_display = {
+        .type = S3C2410_LCDCON1_TFT,
+        .width = 240,
+        .height = 320,
+        .xres = 240,
+        .yres = 320,
+        .bpp = 16,
+
+        .pixclock = 260000,
+        .left_margin = 10,
+        .right_margin = 20,
+        .hsync_len = 10,
+        .upper_margin = 2,
+        .lower_margin = 2,
+        .vsync_len = 2,
+
+        .lcdcon5 = S3C2410_LCDCON5_FRM565 |
+                           S3C2410_LCDCON5_INVVCLK |
+                           S3C2410_LCDCON5_INVVLINE |
+                           S3C2410_LCDCON5_INVVFRAME |
+                           S3C2410_LCDCON5_HWSWP |
+                           (0x02 << 13) |
+                           (0x02 << 15),
+
+};
+
+static struct s3c2410fb_mach_info rx1950_lcd_cfg = {
+        .displays = &rx1950_display,
+        .num_displays = 1,
+        .default_display = 0,
+
+        .lpcsel = 0x02,
+        .gpccon = 0xaa9556a9,
+        .gpccon_mask = 0xffc003fc,
+        .gpcup = 0x0000ffff,
+        .gpcup_mask = 0xffffffff,
+
+        .gpdcon = 0xaa90aaa1,
+        .gpdcon_mask = 0xffc0fff0,
+        .gpdup = 0x0000fcfd,
+        .gpdup_mask = 0xffffffff,
+
+};
+
+static struct pwm_device *lcd_pwm;
+
+void rx1950_lcd_power(int enable)
+{
+        int i;
+        static int enabled;
+        if (enabled == enable)
+                return;
+        if (!enable) {
+
+                /* GPC11-GPC15->OUTPUT */
+                for (i = 11; i < 16; i++)
+                        gpio_direction_output(S3C2410_GPC(i), 1);
+
+                /* Wait a bit here... */
+                mdelay(100);
+
+                /* GPD2-GPD7->OUTPUT */
+                /* GPD11-GPD15->OUTPUT */
+                /* GPD2-GPD7->1, GPD11-GPD15->1 */
+                for (i = 2; i < 8; i++)
+                        gpio_direction_output(S3C2410_GPD(i), 1);
+                for (i = 11; i < 16; i++)
+                        gpio_direction_output(S3C2410_GPD(i), 1);
+
+                /* Wait a bit here...*/
+                mdelay(100);
+
+                /* GPB0->OUTPUT, GPB0->0 */
+                gpio_direction_output(S3C2410_GPB(0), 0);
+
+                /* GPC1-GPC4->OUTPUT, GPC1-4->0 */
+                for (i = 1; i < 5; i++)
+                        gpio_direction_output(S3C2410_GPC(i), 0);
+
+                /* GPC15-GPC11->0 */
+                for (i = 11; i < 16; i++)
+                        gpio_direction_output(S3C2410_GPC(i), 0);
+
+                /* GPD15-GPD11->0, GPD2->GPD7->0 */
+                for (i = 11; i < 16; i++)
+                        gpio_direction_output(S3C2410_GPD(i), 0);
+
+                for (i = 2; i < 8; i++)
+                        gpio_direction_output(S3C2410_GPD(i), 0);
+
+                /* GPC6->0, GPC7->0, GPC5->0 */
+                gpio_direction_output(S3C2410_GPC(6), 0);
+                gpio_direction_output(S3C2410_GPC(7), 0);
+                gpio_direction_output(S3C2410_GPC(5), 0);
+
+                /* GPB1->OUTPUT, GPB1->0 */
+                gpio_direction_output(S3C2410_GPB(1), 0);
+                pwm_config(lcd_pwm, 0, LCD_PWM_PERIOD);
+                pwm_disable(lcd_pwm);
+
+                /* GPC0->0, GPC10->0 */
+                gpio_direction_output(S3C2410_GPC(0), 0);
+                gpio_direction_output(S3C2410_GPC(10), 0);
+        } else {
+                pwm_config(lcd_pwm, LCD_PWM_DUTY, LCD_PWM_PERIOD);
+                pwm_enable(lcd_pwm);
+
+                gpio_direction_output(S3C2410_GPC(0), 1);
+                gpio_direction_output(S3C2410_GPC(5), 1);
+
+                s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPB1_TOUT1);
+                gpio_direction_output(S3C2410_GPC(7), 1);
+
+                for (i = 1; i < 5; i++)
+                        s3c_gpio_cfgpin(S3C2410_GPC(i), S3C_GPIO_SFN(2));
+
+                for (i = 11; i < 16; i++)
+                        s3c_gpio_cfgpin(S3C2410_GPC(i), S3C_GPIO_SFN(2));
+
+                for (i = 2; i < 8; i++)
+                        s3c_gpio_cfgpin(S3C2410_GPD(i), S3C_GPIO_SFN(2));
+
+                for (i = 11; i < 16; i++)
+                        s3c_gpio_cfgpin(S3C2410_GPD(i), S3C_GPIO_SFN(2));
+
+                gpio_direction_output(S3C2410_GPC(10), 1);
+                gpio_direction_output(S3C2410_GPC(6), 1);
+        }
+        enabled = enable;
+}
+
+static void rx1950_bl_power(int enable)
+{
+        static int enabled;
+        if (enabled == enable)
+                return;
+        if (!enable) {
+                        gpio_direction_output(S3C2410_GPB(0), 0);
+        } else {
+                        /* LED driver need a "push" to power on */
+                        gpio_direction_output(S3C2410_GPB(0), 1);
+                        /* Warm up backlight for one period of PWM.
+                         * Without this trick its almost impossible to
+                         * enable backlight with low brightness value
+                         */
+                        ndelay(48000);
+                        s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
+        }
+        enabled = enable;
+}
+
+static int rx1950_backlight_init(struct device *dev)
+{
+        WARN_ON(gpio_request(S3C2410_GPB(0), "Backlight"));
+        lcd_pwm = pwm_request(1, "RX1950 LCD");
+        if (IS_ERR(lcd_pwm)) {
+                dev_err(dev, "Unable to request PWM for LCD power!\n");
+                return PTR_ERR(lcd_pwm);
+        }
+
+        rx1950_lcd_power(1);
+        rx1950_bl_power(1);
+
+        return 0;
+}
+
+static void rx1950_backlight_exit(struct device *dev)
+{
+        rx1950_bl_power(0);
+        rx1950_lcd_power(0);
+
+        pwm_free(lcd_pwm);
+        gpio_free(S3C2410_GPB(0));
+}
+
+
+static int rx1950_backlight_notify(struct device *dev, int brightness)
+{
+        if (!brightness) {
+                rx1950_bl_power(0);
+                rx1950_lcd_power(0);
+        } else {
+                rx1950_lcd_power(1);
+                rx1950_bl_power(1);
+        }
+        return brightness;
+}
+
+static struct platform_pwm_backlight_data rx1950_backlight_data = {
+        .pwm_id = 0,
+        .max_brightness = 24,
+        .dft_brightness = 4,
+        .pwm_period_ns = 48000,
+        .init = rx1950_backlight_init,
+        .notify = rx1950_backlight_notify,
+        .exit = rx1950_backlight_exit,
+};
+
+static struct platform_device rx1950_backlight = {
+        .name = "pwm-backlight",
+        .dev = {
+                .parent = &s3c_device_timer[0].dev,
+                .platform_data = &rx1950_backlight_data,
+        },
+};
+
+static void rx1950_set_mmc_power(unsigned char power_mode, unsigned short vdd)
+{
+        switch (power_mode) {
+        case MMC_POWER_OFF:
+                gpio_direction_output(S3C2410_GPJ(1), 0);
+                break;
+        case MMC_POWER_UP:
+        case MMC_POWER_ON:
+                gpio_direction_output(S3C2410_GPJ(1), 1);
+                break;
+        default:
+                break;
+        }
+}
+
+static struct s3c24xx_mci_pdata rx1950_mmc_cfg __initdata = {
+        .gpio_detect = S3C2410_GPF(5),
+        .gpio_wprotect = S3C2410_GPH(8),
+        .set_power = rx1950_set_mmc_power,
+        .ocr_avail = MMC_VDD_32_33,
+};
+
+static struct mtd_partition rx1950_nand_part[] = {
+        [0] = {
+                        .name = "Boot0",
+                        .offset = 0,
+                        .size = 0x4000,
+                        .mask_flags = MTD_WRITEABLE,
+        },
+        [1] = {
+                        .name = "Boot1",
+                        .offset = MTDPART_OFS_APPEND,
+                        .size = 0x40000,
+                        .mask_flags = MTD_WRITEABLE,
+        },
+        [2] = {
+                        .name = "Kernel",
+                        .offset = MTDPART_OFS_APPEND,
+                        .size = 0x300000,
+                        .mask_flags = 0,
+        },
+        [3] = {
+                        .name = "Filesystem",
+                        .offset = MTDPART_OFS_APPEND,
+                        .size = MTDPART_SIZ_FULL,
+                        .mask_flags = 0,
+        },
+};
+
+static struct s3c2410_nand_set rx1950_nand_sets[] = {
+        [0] = {
+                        .name = "Internal",
+                        .nr_chips = 1,
+                        .nr_partitions = ARRAY_SIZE(rx1950_nand_part),
+                        .partitions = rx1950_nand_part,
+        },
+};
+
+static struct s3c2410_platform_nand rx1950_nand_info = {
+        .tacls = 25,
+        .twrph0 = 50,
+        .twrph1 = 15,
+        .nr_sets = ARRAY_SIZE(rx1950_nand_sets),
+        .sets = rx1950_nand_sets,
+};
+
+static void rx1950_udc_pullup(enum s3c2410_udc_cmd_e cmd)
+{
+        switch (cmd) {
+        case S3C2410_UDC_P_ENABLE:
+                gpio_direction_output(S3C2410_GPJ(5), 1);
+                break;
+        case S3C2410_UDC_P_DISABLE:
+                gpio_direction_output(S3C2410_GPJ(5), 0);
+                break;
+        case S3C2410_UDC_P_RESET:
+                break;
+        default:
+                break;
+        }
+}
+
+static struct s3c2410_udc_mach_info rx1950_udc_cfg __initdata = {
+        .udc_command = rx1950_udc_pullup,
+        .vbus_pin = S3C2410_GPG(5),
+        .vbus_pin_inverted = 1,
+};
+
+static struct s3c2410_ts_mach_info rx1950_ts_cfg __initdata = {
+        .delay = 10000,
+        .presc = 49,
+        .oversampling_shift = 3,
+};
+
+static struct gpio_keys_button rx1950_gpio_keys_table[] = {
+        {
+                .code           = KEY_POWER,
+                .gpio           = S3C2410_GPF(0),
+                .active_low     = 1,
+                .desc           = "Power button",
+                .wakeup         = 1,
+        },
+        {
+                .code           = KEY_F5,
+                .gpio           = S3C2410_GPF(7),
+                .active_low     = 1,
+                .desc           = "Record button",
+        },
+        {
+                .code           = KEY_F1,
+                .gpio           = S3C2410_GPG(0),
+                .active_low     = 1,
+                .desc           = "Calendar button",
+        },
+        {
+                .code           = KEY_F2,
+                .gpio           = S3C2410_GPG(2),
+                .active_low     = 1,
+                .desc           = "Contacts button",
+        },
+        {
+                .code           = KEY_F3,
+                .gpio           = S3C2410_GPG(3),
+                .active_low     = 1,
+                .desc           = "Mail button",
+        },
+        {
+                .code           = KEY_F4,
+                .gpio           = S3C2410_GPG(7),
+                .active_low     = 1,
+                .desc           = "WLAN button",
+        },
+        {
+                .code           = KEY_LEFT,
+                .gpio           = S3C2410_GPG(10),
+                .active_low     = 1,
+                .desc           = "Left button",
+        },
+        {
+                .code           = KEY_RIGHT,
+                .gpio           = S3C2410_GPG(11),
+                .active_low     = 1,
+                .desc           = "Right button",
+        },
+        {
+                .code           = KEY_UP,
+                .gpio           = S3C2410_GPG(4),
+                .active_low     = 1,
+                .desc           = "Up button",
+        },
+        {
+                .code           = KEY_DOWN,
+                .gpio           = S3C2410_GPG(6),
+                .active_low     = 1,
+                .desc           = "Down button",
+        },
+        {
+                .code           = KEY_ENTER,
+                .gpio           = S3C2410_GPG(9),
+                .active_low     = 1,
+                .desc           = "Ok button"
+        },
+};
+
+static struct gpio_keys_platform_data rx1950_gpio_keys_data = {
+        .buttons = rx1950_gpio_keys_table,
+        .nbuttons = ARRAY_SIZE(rx1950_gpio_keys_table),
+};
+
+static struct platform_device rx1950_device_gpiokeys = {
+        .name = "gpio-keys",
+        .dev.platform_data = &rx1950_gpio_keys_data,
+};
+
+static struct s3c2410_platform_i2c rx1950_i2c_data = {
+        .flags = 0,
+        .slave_addr = 0x42,
+        .frequency = 400 * 1000,
+        .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
+};
+
+static struct platform_device *rx1950_devices[] __initdata = {
+        &s3c_device_lcd,
+        &s3c_device_wdt,
+        &s3c_device_i2c0,
+        &s3c_device_iis,
+        &s3c_device_usbgadget,
+        &s3c_device_rtc,
+        &s3c_device_nand,
+        &s3c_device_sdi,
+        &s3c_device_adc,
+        &s3c_device_ts,
+        &s3c_device_timer[0],
+        &s3c_device_timer[1],
+        &rx1950_backlight,
+        &rx1950_device_gpiokeys,
+};
+
+static struct clk *rx1950_clocks[] __initdata = {
+        &s3c24xx_clkout0,
+        &s3c24xx_clkout1,
+};
+
+static void __init rx1950_map_io(void)
+{
+        s3c24xx_clkout0.parent  = &clk_h;
+        s3c24xx_clkout1.parent  = &clk_f;
+
+        s3c24xx_register_clocks(rx1950_clocks, ARRAY_SIZE(rx1950_clocks));
+
+        s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc));
+        s3c24xx_init_clocks(16934000);
+        s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs));
+
+        /* setup PM */
+
+#ifdef CONFIG_PM_H1940
+        memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 8);
+#endif
+
+        s3c_pm_init();
+}
+
+static void __init rx1950_init_machine(void)
+{
+        int i;
+
+        s3c24xx_fb_set_platdata(&rx1950_lcd_cfg);
+        s3c24xx_udc_set_platdata(&rx1950_udc_cfg);
+        s3c24xx_ts_set_platdata(&rx1950_ts_cfg);
+        s3c24xx_mci_set_platdata(&rx1950_mmc_cfg);
+        s3c_i2c0_set_platdata(&rx1950_i2c_data);
+        s3c_nand_set_platdata(&rx1950_nand_info);
+
+        /* Turn off suspend on both USB ports, and switch the
+         * selectable USB port to USB device mode. */
+        s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
+                                                S3C2410_MISCCR_USBSUSPND0 |
+                                                S3C2410_MISCCR_USBSUSPND1, 0x0);
+
+        WARN_ON(gpio_request(S3C2410_GPJ(5), "UDC pullup"));
+        gpio_direction_output(S3C2410_GPJ(5), 0);
+
+        /* mmc power is disabled by default */
+        WARN_ON(gpio_request(S3C2410_GPJ(1), "MMC power"));
+        gpio_direction_output(S3C2410_GPJ(1), 0);
+
+        for (i = 0; i < 8; i++)
+                WARN_ON(gpio_request(S3C2410_GPC(i), "LCD power"));
+
+        for (i = 10; i < 16; i++)
+                WARN_ON(gpio_request(S3C2410_GPC(i), "LCD power"));
+
+        for (i = 2; i < 8; i++)
+                WARN_ON(gpio_request(S3C2410_GPD(i), "LCD power"));
+
+        for (i = 11; i < 16; i++)
+                WARN_ON(gpio_request(S3C2410_GPD(i), "LCD power"));
+
+        WARN_ON(gpio_request(S3C2410_GPB(1), "LCD power"));
+
+        platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices));
+}
+
+MACHINE_START(RX1950, "HP iPAQ RX1950")
+    /* Maintainers: Vasily Khoruzhick */
+    .phys_io = S3C2410_PA_UART,
+        .io_pg_offst = (((u32) S3C24XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params = S3C2410_SDRAM_PA + 0x100,
+        .map_io = rx1950_map_io,
+        .init_irq = s3c24xx_init_irq,
+        .init_machine = rx1950_init_machine,
+        .timer = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index 1e836e506f8b..d2946de3f365 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -209,7 +209,7 @@ static void __init rx3715_init_machine(void)
 }
 
 MACHINE_START(RX3715, "IPAQ-RX3715")
-        /* Maintainer: Ben Dooks <ben@fluff.org> */
+        /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .phys_io        = S3C2410_PA_UART,
         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index 3ac3d636d615..df83276d85ae 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -174,7 +174,7 @@ static void __init smdk2440_machine_init(void)
 }
 
 MACHINE_START(S3C2440, "SMDK2440")
-        /* Maintainer: Ben Dooks <ben@fluff.org> */
+        /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .phys_io        = S3C2410_PA_UART,
         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c
index 2b68f7ea45ae..d50f3ae6173d 100644
--- a/arch/arm/mach-s3c2440/s3c2440.c
+++ b/arch/arm/mach-s3c2440/s3c2440.c
@@ -19,6 +19,7 @@
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
 #include <linux/sysdev.h>
+#include <linux/gpio.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 
@@ -33,6 +34,10 @@
 #include <plat/cpu.h>
 #include <plat/s3c244x.h>
 
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+
 static struct sys_device s3c2440_sysdev = {
         .cls            = &s3c2440_sysclass,
 };
@@ -41,6 +46,9 @@ int __init s3c2440_init(void)
 {
         printk("S3C2440: Initialising architecture\n");
 
+        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
+        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
+
         /* change irq for watchdog */
 
         s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT;
diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig
index 698140af247c..4fef723126fa 100644
--- a/arch/arm/mach-s3c2443/Kconfig
+++ b/arch/arm/mach-s3c2443/Kconfig
@@ -8,6 +8,7 @@ config CPU_S3C2443
         select S3C2443_DMA if S3C2410_DMA
         select CPU_LLSERIAL_S3C2440
         select SAMSUNG_CLKSRC
+        select S3C2443_CLOCK
         help
           Support for the S3C2443 SoC from the S3C24XX line
 
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index 62cd4eaee01b..83b1aa63d778 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -21,6 +21,7 @@
 */
 
 #include <linux/init.h>
+
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/list.h>
@@ -54,111 +55,13 @@
  * set the correct muxing at initialisation
 */
 
-static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
-{
-        u32 ctrlbit = clk->ctrlbit;
-        u32 con = __raw_readl(reg);
-
-        if (enable)
-                con |= ctrlbit;
-        else
-                con &= ~ctrlbit;
-
-        __raw_writel(con, reg);
-        return 0;
-}
-
-static int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
-{
-        return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
-}
-
-static int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
-{
-        return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
-}
-
-static int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
-{
-        return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
-}
-
 /* clock selections */
 
-/* mpllref is a direct descendant of clk_xtal by default, but it is not
- * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
- * such directly equating the two source clocks is impossible.
- */
-static struct clk clk_mpllref = {
-        .name           = "mpllref",
-        .parent         = &clk_xtal,
-        .id             = -1,
-};
-
 static struct clk clk_i2s_ext = {
         .name           = "i2s-ext",
         .id             = -1,
 };
 
-static struct clk *clk_epllref_sources[] = {
-        [0] = &clk_mpllref,
-        [1] = &clk_mpllref,
-        [2] = &clk_xtal,
-        [3] = &clk_ext,
-};
-
-static struct clksrc_clk clk_epllref = {
-        .clk    = {
-                .name           = "epllref",
-                .id             = -1,
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = clk_epllref_sources,
-                .nr_sources = ARRAY_SIZE(clk_epllref_sources),
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
-};
-
-static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long div = __raw_readl(S3C2443_CLKDIV0);
-
-        div  &= S3C2443_CLKDIV0_EXTDIV_MASK;
-        div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1);       /* x2 */
-
-        return parent_rate / (div + 1);
-}
-
-static struct clk clk_mdivclk = {
-        .name           = "mdivclk",
-        .parent         = &clk_mpllref,
-        .id             = -1,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2443_getrate_mdivclk,
-        },
-};
-
-static struct clk *clk_msysclk_sources[] = {
-        [0] = &clk_mpllref,
-        [1] = &clk_mpll,
-        [2] = &clk_mdivclk,
-        [3] = &clk_mpllref,
-};
-
-static struct clksrc_clk clk_msysclk = {
-        .clk    = {
-                .name           = "msysclk",
-                .parent         = &clk_xtal,
-                .id             = -1,
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = clk_msysclk_sources,
-                .nr_sources = ARRAY_SIZE(clk_msysclk_sources),
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
-};
-
 /* armdiv
  *
  * this clock is sourced from msysclk and can have a number of
@@ -266,44 +169,6 @@ static struct clksrc_clk clk_arm = {
         .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
 };
 
-/* esysclk
- *
- * this is sourced from either the EPLL or the EPLLref clock
-*/
-
-static struct clk *clk_sysclk_sources[] = {
-        [0] = &clk_epllref.clk,
-        [1] = &clk_epll,
-};
-
-static struct clksrc_clk clk_esysclk = {
-        .clk    = {
-                .name           = "esysclk",
-                .parent         = &clk_epll,
-                .id             = -1,
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = clk_sysclk_sources,
-                .nr_sources = ARRAY_SIZE(clk_sysclk_sources),
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
-};
-
-/* uartclk
- *
- * UART baud-rate clock sourced from esysclk via a divisor
-*/
-
-static struct clksrc_clk clk_uart = {
-        .clk    = {
-                .name           = "uartclk",
-                .id             = -1,
-                .parent         = &clk_esysclk.clk,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
-};
-
-
 /* hsspi
  *
  * high-speed spi clock, sourced from esysclk
@@ -320,21 +185,6 @@ static struct clksrc_clk clk_hsspi = {
         .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
 };
 
-/* usbhost
- *
- * usb host bus-clock, usually 48MHz to provide USB bus clock timing
-*/
-
-static struct clksrc_clk clk_usb_bus_host = {
-        .clk    = {
-                .name           = "usb-bus-host-parent",
-                .id             = -1,
-                .parent         = &clk_esysclk.clk,
-                .ctrlbit        = S3C2443_SCLKCON_USBHOST,
-                .enable         = s3c2443_clkcon_enable_s,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
-};
 
 /* clk_hsmcc_div
  *
@@ -433,89 +283,16 @@ static struct clksrc_clk clk_i2s = {
         .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
 };
 
-/* cam-if
- *
- * camera interface bus-clock, divided down from esysclk
-*/
-
-static struct clksrc_clk clk_cam = {
-        .clk    = {
-                .name           = "camif-upll", /* same as 2440 name */
-                .id             = -1,
-                .parent         = &clk_esysclk.clk,
-                .ctrlbit        = S3C2443_SCLKCON_CAMCLK,
-                .enable         = s3c2443_clkcon_enable_s,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
-};
-
-/* display-if
- *
- * display interface clock, divided from esysclk
-*/
-
-static struct clksrc_clk clk_display = {
-        .clk    = {
-                .name           = "display-if",
-                .id             = -1,
-                .parent         = &clk_esysclk.clk,
-                .ctrlbit        = S3C2443_SCLKCON_DISPCLK,
-                .enable         = s3c2443_clkcon_enable_s,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
-};
-
-/* prediv
- *
- * this divides the msysclk down to pass to h/p/etc.
- */
-
-static unsigned long s3c2443_prediv_getrate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
-
-        clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
-        clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
-
-        return rate / (clkdiv0 + 1);
-}
-
-static struct clk clk_prediv = {
-        .name           = "prediv",
-        .id             = -1,
-        .parent         = &clk_msysclk.clk,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2443_prediv_getrate,
-        },
-};
-
 /* standard clock definitions */
 
-static struct clk init_clocks_disable[] = {
+static struct clk init_clocks_off[] = {
         {
-                .name           = "nand",
-                .id             = -1,
-                .parent         = &clk_h,
-        }, {
                 .name           = "sdi",
                 .id             = -1,
                 .parent         = &clk_p,
                 .enable         = s3c2443_clkcon_enable_p,
                 .ctrlbit        = S3C2443_PCLKCON_SDI,
         }, {
-                .name           = "adc",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_ADC,
-        }, {
-                .name           = "i2c",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_IIC,
-        }, {
                 .name           = "iis",
                 .id             = -1,
                 .parent         = &clk_p,
@@ -537,179 +314,12 @@ static struct clk init_clocks_disable[] = {
 };
 
 static struct clk init_clocks[] = {
-        {
-                .name           = "dma",
-                .id             = 0,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA0,
-        }, {
-                .name           = "dma",
-                .id             = 1,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA1,
-        }, {
-                .name           = "dma",
-                .id             = 2,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA2,
-        }, {
-                .name           = "dma",
-                .id             = 3,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA3,
-        }, {
-                .name           = "dma",
-                .id             = 4,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA4,
-        }, {
-                .name           = "dma",
-                .id             = 5,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA5,
-        }, {
-                .name           = "lcd",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_LCDC,
-        }, {
-                .name           = "gpio",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_GPIO,
-        }, {
-                .name           = "usb-host",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_USBH,
-        }, {
-                .name           = "usb-device",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_USBD,
-        }, {
-                .name           = "hsmmc",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_HSMMC,
-        }, {
-                .name           = "cfc",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_CFC,
-        }, {
-                .name           = "ssmc",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_SSMC,
-        }, {
-                .name           = "timers",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_PWMT,
-        }, {
-                .name           = "uart",
-                .id             = 0,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_UART0,
-        }, {
-                .name           = "uart",
-                .id             = 1,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_UART1,
-        }, {
-                .name           = "uart",
-                .id             = 2,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_UART2,
-        }, {
-                .name           = "uart",
-                .id             = 3,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_UART3,
-        }, {
-                .name           = "rtc",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_RTC,
-        }, {
-                .name           = "watchdog",
-                .id             = -1,
-                .parent         = &clk_p,
-                .ctrlbit        = S3C2443_PCLKCON_WDT,
-        }, {
-                .name           = "usb-bus-host",
-                .id             = -1,
-                .parent         = &clk_usb_bus_host.clk,
-        }, {
-                .name           = "ac97",
-                .id             = -1,
-                .parent         = &clk_p,
-                .ctrlbit        = S3C2443_PCLKCON_AC97,
-        }
-};
-
-/* clocks to add where we need to check their parentage */
-
-static struct clksrc_clk __initdata *init_list[] = {
-        &clk_epllref, /* should be first */
-        &clk_esysclk,
-        &clk_msysclk,
-        &clk_arm,
-        &clk_i2s_eplldiv,
-        &clk_i2s,
-        &clk_cam,
-        &clk_uart,
-        &clk_display,
-        &clk_hsmmc_div,
-        &clk_usb_bus_host,
 };
 
-static void __init s3c2443_clk_initparents(void)
-{
-        int ptr;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(init_list); ptr++)
-                s3c_set_clksrc(init_list[ptr], true);
-}
-
-static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
-{
-        clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
-
-        return clkcon0 + 1;
-}
-
 /* clocks to add straight away */
 
 static struct clksrc_clk *clksrcs[] __initdata = {
-        &clk_usb_bus_host,
-        &clk_epllref,
-        &clk_esysclk,
-        &clk_msysclk,
         &clk_arm,
-        &clk_uart,
-        &clk_display,
-        &clk_cam,
         &clk_i2s_eplldiv,
         &clk_i2s,
         &clk_hsspi,
@@ -717,92 +327,32 @@ static struct clksrc_clk *clksrcs[] __initdata = {
 };
 
 static struct clk *clks[] __initdata = {
-        &clk_ext,
-        &clk_epll,
-        &clk_usb_bus,
-        &clk_mpllref,
         &clk_hsmmc,
         &clk_armdiv,
-        &clk_prediv,
 };
 
 void __init_or_cpufreq s3c2443_setup_clocks(void)
 {
-        unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
-        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
-        struct clk *xtal_clk;
-        unsigned long xtal;
-        unsigned long pll;
-        unsigned long fclk;
-        unsigned long hclk;
-        unsigned long pclk;
-
-        xtal_clk = clk_get(NULL, "xtal");
-        xtal = clk_get_rate(xtal_clk);
-        clk_put(xtal_clk);
-
-        pll = s3c2443_get_mpll(mpllcon, xtal);
-        clk_msysclk.clk.rate = pll;
-
-        fclk = pll / s3c2443_fclk_div(clkdiv0);
-        hclk = s3c2443_prediv_getrate(&clk_prediv);
-        hclk /= s3c2443_get_hdiv(clkdiv0);
-        pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
-
-        s3c24xx_setup_clocks(fclk, hclk, pclk);
-
-        printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
-               (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
-               print_mhz(pll), print_mhz(fclk),
-               print_mhz(hclk), print_mhz(pclk));
-
-        s3c24xx_setup_clocks(fclk, hclk, pclk);
+        s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div);
 }
 
 void __init s3c2443_init_clocks(int xtal)
 {
-        struct clk *clkp;
         unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
-        int ret;
         int ptr;
 
-        /* s3c2443 parents h and p clocks from prediv */
-        clk_h.parent = &clk_prediv;
-        clk_p.parent = &clk_prediv;
+        clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
+        clk_epll.parent = &clk_epllref.clk;
+
+        s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div);
 
-        s3c24xx_register_baseclocks(xtal);
         s3c2443_setup_clocks();
-        s3c2443_clk_initparents();
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
-                clkp = clks[ptr];
 
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-        }
+        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 
         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
                 s3c_register_clksrc(clksrcs[ptr], 1);
 
-        clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
-        clk_epll.parent = &clk_epllref.clk;
-        clk_usb_bus.parent = &clk_usb_bus_host.clk;
-
-        /* ensure usb bus clock is within correct rate of 48MHz */
-
-        if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
-                printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
-                clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
-        }
-
-        printk("S3C2443: epll %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
-               (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
-               print_mhz(clk_get_rate(&clk_epll)),
-               print_mhz(clk_get_rate(&clk_usb_bus)));
-
         /* register clocks from clock array */
 
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
@@ -819,17 +369,8 @@ void __init s3c2443_init_clocks(int xtal)
 
         /* install (and disable) the clocks we do not need immediately */
 
-        clkp = init_clocks_disable;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
-
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-
-                (clkp->enable)(clkp, 0);
-        }
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
         s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index e2e362bda9b7..4c863d3a52f4 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -131,7 +131,7 @@ static void __init smdk2443_machine_init(void)
 }
 
 MACHINE_START(SMDK2443, "SMDK2443")
-        /* Maintainer: Ben Dooks <ben@fluff.org> */
+        /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .phys_io        = S3C2410_PA_UART,
         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 2ac2e7d73e53..7a4138beb665 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -88,6 +88,12 @@ struct clk clk_48m = {
         .enable         = clk_48m_ctrl,
 };
 
+struct clk clk_xusbxti = {
+        .name           = "xusbxti",
+        .id             = -1,
+        .rate           = 48000000,
+};
+
 static int inline s3c64xx_gate(void __iomem *reg,
                                 struct clk *clk,
                                 int enable)
@@ -518,6 +524,11 @@ static struct clk clk_iis_cd1 = {
         .id             = -1,
 };
 
+static struct clk clk_iisv4_cd = {
+        .name           = "iis_cdclk_v4",
+        .id             = -1,
+};
+
 static struct clk clk_pcm_cd = {
         .name           = "pcm_cdclk",
         .id             = -1,
@@ -549,6 +560,19 @@ static struct clksrc_sources clkset_audio1 = {
         .nr_sources     = ARRAY_SIZE(clkset_audio1_list),
 };
 
+static struct clk *clkset_audio2_list[] = {
+        [0] = &clk_mout_epll.clk,
+        [1] = &clk_dout_mpll,
+        [2] = &clk_fin_epll,
+        [3] = &clk_iisv4_cd,
+        [4] = &clk_pcm_cd,
+};
+
+static struct clksrc_sources clkset_audio2 = {
+        .sources        = clkset_audio2_list,
+        .nr_sources     = ARRAY_SIZE(clkset_audio2_list),
+};
+
 static struct clk *clkset_camif_list[] = {
         &clk_h2,
 };
@@ -652,6 +676,16 @@ static struct clksrc_clk clksrcs[] = {
                 .sources        = &clkset_audio1,
         }, {
                 .clk    = {
+                        .name           = "audio-bus",
+                        .id             = -1,  /* There's only one IISv4 port */
+                        .ctrlbit        = S3C6410_CLKCON_SCLK_AUDIO2,
+                        .enable         = s3c64xx_sclk_ctrl,
+                },
+                .reg_src        = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3  },
+                .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4  },
+                .sources        = &clkset_audio2,
+        }, {
+                .clk    = {
                         .name           = "irda-bus",
                         .id             = 0,
                         .ctrlbit        = S3C_CLKCON_SCLK_IRDA,
@@ -749,6 +783,7 @@ static struct clk *clks1[] __initdata = {
         &clk_ext_xtal_mux,
         &clk_iis_cd0,
         &clk_iis_cd1,
+        &clk_iisv4_cd,
         &clk_pcm_cd,
         &clk_mout_epll.clk,
         &clk_mout_mpll.clk,
@@ -762,6 +797,7 @@ static struct clk *clks[] __initdata = {
         &clk_27m,
         &clk_48m,
         &clk_h2,
+        &clk_xusbxti,
 };
 
 /**
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 33ccf7bf766a..5567e037b0d1 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -414,7 +414,7 @@ err_buff:
 EXPORT_SYMBOL(s3c2410_dma_enqueue);
 
 
-int s3c2410_dma_devconfig(int channel,
+int s3c2410_dma_devconfig(unsigned int channel,
                           enum s3c2410_dmasrc source,
                           unsigned long devaddr)
 {
diff --git a/arch/arm/mach-s3c64xx/gpiolib.c b/arch/arm/mach-s3c64xx/gpiolib.c
index 66e6794481d2..60c929a3cab6 100644
--- a/arch/arm/mach-s3c64xx/gpiolib.c
+++ b/arch/arm/mach-s3c64xx/gpiolib.c
@@ -51,6 +51,7 @@
 
 static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
         .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .get_config     = s3c_gpio_getcfg_s3c64xx_4bit,
         .set_pull       = s3c_gpio_setpull_updown,
         .get_pull       = s3c_gpio_getpull_updown,
 };
@@ -58,12 +59,14 @@ static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
 static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
         .cfg_eint       = 7,
         .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .get_config     = s3c_gpio_getcfg_s3c64xx_4bit,
         .set_pull       = s3c_gpio_setpull_updown,
         .get_pull       = s3c_gpio_getpull_updown,
 };
 
 static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
         .cfg_eint       = 3,
+        .get_config     = s3c_gpio_getcfg_s3c64xx_4bit,
         .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
         .set_pull       = s3c_gpio_setpull_updown,
         .get_pull       = s3c_gpio_getpull_updown,
@@ -171,6 +174,7 @@ static struct s3c_gpio_chip gpio_4bit2[] = {
 
 static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
         .set_config     = s3c_gpio_setcfg_s3c24xx,
+        .get_config     = s3c_gpio_getcfg_s3c24xx,
         .set_pull       = s3c_gpio_setpull_updown,
         .get_pull       = s3c_gpio_getpull_updown,
 };
@@ -178,6 +182,7 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
 static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
         .cfg_eint       = 2,
         .set_config     = s3c_gpio_setcfg_s3c24xx,
+        .get_config     = s3c_gpio_getcfg_s3c24xx,
         .set_pull       = s3c_gpio_setpull_updown,
         .get_pull       = s3c_gpio_getpull_updown,
 };
@@ -185,6 +190,7 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
 static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
         .cfg_eint       = 3,
         .set_config     = s3c_gpio_setcfg_s3c24xx,
+        .get_config     = s3c_gpio_getcfg_s3c24xx,
         .set_pull       = s3c_gpio_setpull_updown,
         .get_pull       = s3c_gpio_getpull_updown,
 };
diff --git a/arch/arm/mach-s3c64xx/include/mach/pll.h b/arch/arm/mach-s3c64xx/include/mach/pll.h
index 90bbd72fdc4e..5ef0bb698ee0 100644
--- a/arch/arm/mach-s3c64xx/include/mach/pll.h
+++ b/arch/arm/mach-s3c64xx/include/mach/pll.h
@@ -20,6 +20,7 @@
 #define S3C6400_PLL_SDIV_SHIFT  (0)
 
 #include <asm/div64.h>
+#include <plat/pll6553x.h>
 
 static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
                                             u32 pllcon)
@@ -37,38 +38,8 @@ static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
         return (unsigned long)fvco;
 }
 
-#define S3C6400_EPLL_MDIV_MASK  ((1 << (23-16)) - 1)
-#define S3C6400_EPLL_PDIV_MASK  ((1 << (13-8)) - 1)
-#define S3C6400_EPLL_SDIV_MASK  ((1 << (2-0)) - 1)
-#define S3C6400_EPLL_MDIV_SHIFT (16)
-#define S3C6400_EPLL_PDIV_SHIFT (8)
-#define S3C6400_EPLL_SDIV_SHIFT (0)
-#define S3C6400_EPLL_KDIV_MASK  (0xffff)
-
 static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
 {
-        unsigned long result;
-        u32 epll0 = __raw_readl(S3C_EPLL_CON0);
-        u32 epll1 = __raw_readl(S3C_EPLL_CON1);
-        u32 mdiv, pdiv, sdiv, kdiv;
-        u64 tmp;
-
-        mdiv = (epll0 >> S3C6400_EPLL_MDIV_SHIFT) & S3C6400_EPLL_MDIV_MASK;
-        pdiv = (epll0 >> S3C6400_EPLL_PDIV_SHIFT) & S3C6400_EPLL_PDIV_MASK;
-        sdiv = (epll0 >> S3C6400_EPLL_SDIV_SHIFT) & S3C6400_EPLL_SDIV_MASK;
-        kdiv = epll1 & S3C6400_EPLL_KDIV_MASK;
-
-        /* We need to multiple baseclk by mdiv (the integer part) and kdiv
-         * which is in 2^16ths, so shift mdiv up (does not overflow) and
-         * add kdiv before multiplying. The use of tmp is to avoid any
-         * overflows before shifting bac down into result when multipling
-         * by the mdiv and kdiv pair.
-         */
-
-        tmp = baseclk;
-        tmp *= (mdiv << 16) + kdiv;
-        do_div(tmp, (pdiv << sdiv));
-        result = tmp >> 16;
-
-        return result;
+        return s3c_get_pll6553x(baseclk, __raw_readl(S3C_EPLL_CON0),
+                                __raw_readl(S3C_EPLL_CON1));
 }
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
index 3ef62741e5d1..0114eb0c1fe7 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
@@ -33,6 +33,7 @@
 #define S3C_PCLK_GATE           S3C_CLKREG(0x34)
 #define S3C_SCLK_GATE           S3C_CLKREG(0x38)
 #define S3C_MEM0_GATE           S3C_CLKREG(0x3C)
+#define S3C6410_CLK_SRC2        S3C_CLKREG(0x10C)
 
 /* CLKDIV0 */
 #define S3C6400_CLKDIV0_PCLK_MASK       (0xf << 12)
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index f7b18983950c..59916676d8d2 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -84,7 +84,7 @@ static void __init smdk6400_machine_init(void)
 }
 
 MACHINE_START(SMDK6400, "SMDK6400")
-        /* Maintainer: Ben Dooks <ben@fluff.org> */
+        /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .phys_io        = S3C_PA_UART & 0xfff00000,
         .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C64XX_PA_SDRAM + 0x100,
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 2d5afd221d77..9d51455feb31 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -656,7 +656,7 @@ static void __init smdk6410_machine_init(void)
 }
 
 MACHINE_START(SMDK6410, "SMDK6410")
-        /* Maintainer: Ben Dooks <ben@fluff.org> */
+        /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .phys_io        = S3C_PA_UART & 0xfff00000,
         .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C64XX_PA_SDRAM + 0x100,
diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig
index 4c29ff8b07de..77aeffd17330 100644
--- a/arch/arm/mach-s5p6440/Kconfig
+++ b/arch/arm/mach-s5p6440/Kconfig
@@ -9,6 +9,7 @@ if ARCH_S5P6440
 
 config CPU_S5P6440
         bool
+        select S3C_PL330_DMA
         help
           Enable S5P6440 CPU support
 
diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile
index a2e99a249767..5fd17d3da0cb 100644
--- a/arch/arm/mach-s5p6440/Makefile
+++ b/arch/arm/mach-s5p6440/Makefile
@@ -12,7 +12,7 @@ obj-				:=
 
 # Core support for S5P6440 system
 
-obj-$(CONFIG_CPU_S5P6440)       += cpu.o init.o clock.o gpio.o
+obj-$(CONFIG_CPU_S5P6440)       += cpu.o init.o clock.o gpio.o dma.o
 
 # machine support
 
diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c
index b2672e16e7aa..ca6e48dce777 100644
--- a/arch/arm/mach-s5p6440/clock.c
+++ b/arch/arm/mach-s5p6440/clock.c
@@ -134,24 +134,6 @@ static struct clksrc_clk clk_mout_mpll = {
         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 },
 };
 
-static struct clk clk_h_low = {
-        .name           = "hclk_low",
-        .id             = -1,
-        .rate           = 0,
-        .parent         = NULL,
-        .ctrlbit        = 0,
-        .ops            = &clk_ops_def_setrate,
-};
-
-static struct clk clk_p_low = {
-        .name           = "pclk_low",
-        .id             = -1,
-        .rate           = 0,
-        .parent         = NULL,
-        .ctrlbit        = 0,
-        .ops            = &clk_ops_def_setrate,
-};
-
 enum perf_level {
         L0 = 532*1000,
         L1 = 266*1000,
@@ -247,23 +229,70 @@ static struct clk_ops s5p6440_clkarm_ops = {
         .round_rate     = s5p6440_armclk_round_rate,
 };
 
-static unsigned long s5p6440_clk_doutmpll_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
+static struct clksrc_clk clk_armclk = {
+        .clk    = {
+                .name   = "armclk",
+                .id     = 1,
+                .parent = &clk_mout_apll.clk,
+                .ops    = &s5p6440_clkarm_ops,
+        },
+        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 },
+};
 
-        if (__raw_readl(S5P_CLK_DIV0) & S5P_CLKDIV0_MPLL_MASK)
-                rate /= 2;
+static struct clksrc_clk clk_dout_mpll = {
+        .clk    = {
+                .name   = "dout_mpll",
+                .id     = -1,
+                .parent = &clk_mout_mpll.clk,
+        },
+        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
+};
 
-        return rate;
-}
+static struct clksrc_clk clk_hclk = {
+        .clk    = {
+                .name   = "clk_hclk",
+                .id     = -1,
+                .parent = &clk_armclk.clk,
+        },
+        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
+};
 
-static struct clk clk_dout_mpll = {
-        .name           = "dout_mpll",
-        .id             = -1,
-        .parent         = &clk_mout_mpll.clk,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s5p6440_clk_doutmpll_get_rate,
+static struct clksrc_clk clk_pclk = {
+        .clk    = {
+                .name   = "clk_pclk",
+                .id     = -1,
+                .parent = &clk_hclk.clk,
         },
+        .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
+};
+
+static struct clk *clkset_hclklow_list[] = {
+        &clk_mout_apll.clk,
+        &clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_hclklow = {
+        .sources        = clkset_hclklow_list,
+        .nr_sources     = ARRAY_SIZE(clkset_hclklow_list),
+};
+
+static struct clksrc_clk clk_hclk_low = {
+        .clk = {
+                .name   = "hclk_low",
+                .id     = -1,
+        },
+        .sources        = &clkset_hclklow,
+        .reg_src        = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 },
+        .reg_div        = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk_low = {
+        .clk    = {
+                .name   = "pclk_low",
+                .id     = -1,
+                .parent = &clk_hclk_low.clk,
+        },
+        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
 };
 
 int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
@@ -307,6 +336,11 @@ static int s5p6440_sclk_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable);
 }
 
+static int s5p6440_sclk1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLK_GATE_SCLK1, clk, enable);
+}
+
 static int s5p6440_mem_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable);
@@ -321,37 +355,37 @@ static struct clk init_clocks_disable[] = {
         {
                 .name           = "nand",
                 .id             = -1,
-                .parent         = &clk_h,
+                .parent         = &clk_hclk.clk,
                 .enable         = s5p6440_mem_ctrl,
                 .ctrlbit        = S5P_CLKCON_MEM0_HCLK_NFCON,
         }, {
                 .name           = "adc",
                 .id             = -1,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_TSADC,
         }, {
                 .name           = "i2c",
                 .id             = -1,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_IIC0,
         }, {
                 .name           = "i2s_v40",
                 .id             = 0,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_IIS2,
         }, {
                 .name           = "spi",
                 .id             = 0,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_SPI0,
         }, {
                 .name           = "spi",
                 .id             = 1,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_SPI1,
         }, {
@@ -387,58 +421,124 @@ static struct clk init_clocks_disable[] = {
         }, {
                 .name           = "otg",
                 .id             = -1,
-                .parent         = &clk_h_low,
+                .parent         = &clk_hclk_low.clk,
                 .enable         = s5p6440_hclk0_ctrl,
                 .ctrlbit        = S5P_CLKCON_HCLK0_USB
         }, {
                 .name           = "post",
                 .id             = -1,
-                .parent         = &clk_h_low,
+                .parent         = &clk_hclk_low.clk,
                 .enable         = s5p6440_hclk0_ctrl,
                 .ctrlbit        = S5P_CLKCON_HCLK0_POST0
         }, {
                 .name           = "lcd",
                 .id             = -1,
-                .parent         = &clk_h_low,
+                .parent         = &clk_hclk_low.clk,
                 .enable         = s5p6440_hclk1_ctrl,
                 .ctrlbit        = S5P_CLKCON_HCLK1_DISPCON,
         }, {
                 .name           = "hsmmc",
                 .id             = 0,
-                .parent         = &clk_h_low,
+                .parent         = &clk_hclk_low.clk,
                 .enable         = s5p6440_hclk0_ctrl,
                 .ctrlbit        = S5P_CLKCON_HCLK0_HSMMC0,
         }, {
                 .name           = "hsmmc",
                 .id             = 1,
-                .parent         = &clk_h_low,
+                .parent         = &clk_hclk_low.clk,
                 .enable         = s5p6440_hclk0_ctrl,
                 .ctrlbit        = S5P_CLKCON_HCLK0_HSMMC1,
         }, {
                 .name           = "hsmmc",
                 .id             = 2,
-                .parent         = &clk_h_low,
+                .parent         = &clk_hclk_low.clk,
                 .enable         = s5p6440_hclk0_ctrl,
                 .ctrlbit        = S5P_CLKCON_HCLK0_HSMMC2,
         }, {
                 .name           = "rtc",
                 .id             = -1,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_RTC,
         }, {
                 .name           = "watchdog",
                 .id             = -1,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_WDT,
         }, {
                 .name           = "timers",
                 .id             = -1,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_PWM,
-        }
+        }, {
+                .name           = "hclk_fimgvg",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p6440_hclk1_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "tsi",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p6440_hclk1_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "pclk_fimgvg",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p6440_pclk_ctrl,
+                .ctrlbit        = (1 << 31),
+        }, {
+                .name           = "dmc0",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p6440_pclk_ctrl,
+                .ctrlbit        = (1 << 30),
+        }, {
+                .name           = "etm",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p6440_pclk_ctrl,
+                .ctrlbit        = (1 << 29),
+        }, {
+                .name           = "dsim",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p6440_pclk_ctrl,
+                .ctrlbit        = (1 << 28),
+        }, {
+                .name           = "gps",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p6440_pclk_ctrl,
+                .ctrlbit        = (1 << 25),
+        }, {
+                .name           = "pcm",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p6440_pclk_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "irom",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p6440_hclk0_ctrl,
+                .ctrlbit        = (1 << 25),
+        }, {
+                .name           = "dma",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p6440_hclk0_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "2d",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p6440_hclk0_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
 };
 
 /*
@@ -448,34 +548,46 @@ static struct clk init_clocks[] = {
         {
                 .name           = "gpio",
                 .id             = -1,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_GPIO,
         }, {
                 .name           = "uart",
                 .id             = 0,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_UART0,
         }, {
                 .name           = "uart",
                 .id             = 1,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_UART1,
         }, {
                 .name           = "uart",
                 .id             = 2,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_UART2,
         }, {
                 .name           = "uart",
                 .id             = 3,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_UART3,
-        }
+        }, {
+                .name           = "mem",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p6440_hclk0_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "intc",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p6440_hclk0_ctrl,
+                .ctrlbit        = (1 << 1),
+        },
 };
 
 static struct clk clk_iis_cd_v40 = {
@@ -488,20 +600,20 @@ static struct clk clk_pcm_cd = {
         .id             = -1,
 };
 
-static struct clk *clkset_spi_mmc_list[] = {
+static struct clk *clkset_group1_list[] = {
         &clk_mout_epll.clk,
-        &clk_dout_mpll,
+        &clk_dout_mpll.clk,
         &clk_fin_epll,
 };
 
-static struct clksrc_sources clkset_spi_mmc = {
-        .sources        = clkset_spi_mmc_list,
-        .nr_sources     = ARRAY_SIZE(clkset_spi_mmc_list),
+static struct clksrc_sources clkset_group1 = {
+        .sources        = clkset_group1_list,
+        .nr_sources     = ARRAY_SIZE(clkset_group1_list),
 };
 
 static struct clk *clkset_uart_list[] = {
         &clk_mout_epll.clk,
-        &clk_dout_mpll
+        &clk_dout_mpll.clk,
 };
 
 static struct clksrc_sources clkset_uart = {
@@ -509,6 +621,19 @@ static struct clksrc_sources clkset_uart = {
         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 };
 
+static struct clk *clkset_audio_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll.clk,
+        &clk_fin_epll,
+        &clk_iis_cd_v40,
+        &clk_pcm_cd,
+};
+
+static struct clksrc_sources clkset_audio = {
+        .sources        = clkset_audio_list,
+        .nr_sources     = ARRAY_SIZE(clkset_audio_list),
+};
+
 static struct clksrc_clk clksrcs[] = {
         {
                 .clk    = {
@@ -517,7 +642,7 @@ static struct clksrc_clk clksrcs[] = {
                         .ctrlbit        = S5P_CLKCON_SCLK0_MMC0,
                         .enable         = s5p6440_sclk_ctrl,
                 },
-                .sources = &clkset_spi_mmc,
+                .sources = &clkset_group1,
                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
         }, {
@@ -527,7 +652,7 @@ static struct clksrc_clk clksrcs[] = {
                         .ctrlbit        = S5P_CLKCON_SCLK0_MMC1,
                         .enable         = s5p6440_sclk_ctrl,
                 },
-                .sources = &clkset_spi_mmc,
+                .sources = &clkset_group1,
                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
         }, {
@@ -537,7 +662,7 @@ static struct clksrc_clk clksrcs[] = {
                         .ctrlbit        = S5P_CLKCON_SCLK0_MMC2,
                         .enable         = s5p6440_sclk_ctrl,
                 },
-                .sources = &clkset_spi_mmc,
+                .sources = &clkset_group1,
                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
         }, {
@@ -557,7 +682,7 @@ static struct clksrc_clk clksrcs[] = {
                         .ctrlbit        = S5P_CLKCON_SCLK0_SPI0,
                         .enable         = s5p6440_sclk_ctrl,
                 },
-                .sources = &clkset_spi_mmc,
+                .sources = &clkset_group1,
                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
         }, {
@@ -567,17 +692,63 @@ static struct clksrc_clk clksrcs[] = {
                         .ctrlbit        = S5P_CLKCON_SCLK0_SPI1,
                         .enable         = s5p6440_sclk_ctrl,
                 },
-                .sources = &clkset_spi_mmc,
+                .sources = &clkset_group1,
                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
-        }
+        }, {
+                .clk    = {
+                        .name           = "sclk_post",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 10),
+                        .enable         = s5p6440_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 26, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_dispcon",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 1),
+                        .enable         = s5p6440_sclk1_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimgvg",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 2),
+                        .enable         = s5p6440_sclk1_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_audio2",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 11),
+                        .enable         = s5p6440_sclk_ctrl,
+                },
+                .sources = &clkset_audio,
+                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 3 },
+                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 24, .size = 4 },
+        },
 };
 
 /* Clock initialisation code */
-static struct clksrc_clk *init_parents[] = {
+static struct clksrc_clk *sysclks[] = {
         &clk_mout_apll,
         &clk_mout_epll,
         &clk_mout_mpll,
+        &clk_dout_mpll,
+        &clk_armclk,
+        &clk_hclk,
+        &clk_pclk,
+        &clk_hclk_low,
+        &clk_pclk_low,
 };
 
 void __init_or_cpufreq s5p6440_setup_clocks(void)
@@ -593,21 +764,13 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
         unsigned long apll;
         unsigned long mpll;
         unsigned int ptr;
-        u32 clkdiv0;
-        u32 clkdiv3;
 
         /* Set S5P6440 functions for clk_fout_epll */
         clk_fout_epll.enable = s5p6440_epll_enable;
         clk_fout_epll.ops = &s5p6440_epll_ops;
 
-        /* Set S5P6440 functions for arm clock */
-        clk_arm.parent = &clk_mout_apll.clk;
-        clk_arm.ops = &s5p6440_clkarm_ops;
         clk_48m.enable = s5p6440_clk48m_ctrl;
 
-        clkdiv0 = __raw_readl(S5P_CLK_DIV0);
-        clkdiv3 = __raw_readl(S5P_CLK_DIV3);
-
         xtal_clk = clk_get(NULL, "ext_xtal");
         BUG_ON(IS_ERR(xtal_clk));
 
@@ -619,41 +782,28 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);
 
+        clk_fout_mpll.rate = mpll;
+        clk_fout_epll.rate = epll;
+        clk_fout_apll.rate = apll;
+
         printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
                         " E=%ld.%ldMHz\n",
                         print_mhz(apll), print_mhz(mpll), print_mhz(epll));
 
-        fclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_ARM);
-        hclk = fclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK);
-        pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK);
-
-        if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) {
-                /* Asynchronous mode */
-                hclk_low = mpll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW);
-        } else {
-                /* Synchronous mode */
-                hclk_low = apll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW);
-        }
-
-        pclk_low = hclk_low / GET_DIV(clkdiv3, S5P_CLKDIV3_PCLK_LOW);
+        fclk = clk_get_rate(&clk_armclk.clk);
+        hclk = clk_get_rate(&clk_hclk.clk);
+        pclk = clk_get_rate(&clk_pclk.clk);
+        hclk_low = clk_get_rate(&clk_hclk_low.clk);
+        pclk_low = clk_get_rate(&clk_pclk_low.clk);
 
         printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
                         " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
                         print_mhz(hclk), print_mhz(hclk_low),
                         print_mhz(pclk), print_mhz(pclk_low));
 
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-        clk_fout_apll.rate = apll;
-
         clk_f.rate = fclk;
         clk_h.rate = hclk;
         clk_p.rate = pclk;
-        clk_h_low.rate = hclk_low;
-        clk_p_low.rate = pclk_low;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
-                s3c_set_clksrc(init_parents[ptr], true);
 
         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
                 s3c_set_clksrc(&clksrcs[ptr], true);
@@ -661,13 +811,8 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
 
 static struct clk *clks[] __initdata = {
         &clk_ext,
-        &clk_mout_epll.clk,
-        &clk_mout_mpll.clk,
-        &clk_dout_mpll,
         &clk_iis_cd_v40,
         &clk_pcm_cd,
-        &clk_p_low,
-        &clk_h_low,
 };
 
 void __init s5p6440_register_clocks(void)
@@ -680,6 +825,9 @@ void __init s5p6440_register_clocks(void)
         if (ret > 0)
                 printk(KERN_ERR "Failed to register %u clocks\n", ret);
 
+        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+                s3c_register_clksrc(sysclks[ptr], 1);
+
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c
index 1794131aeacb..ca3b3206e6f8 100644
--- a/arch/arm/mach-s5p6440/cpu.c
+++ b/arch/arm/mach-s5p6440/cpu.c
@@ -88,7 +88,7 @@ void __init s5p6440_init_irq(void)
         s5p_init_irq(vic, ARRAY_SIZE(vic));
 }
 
-static struct sysdev_class s5p6440_sysclass = {
+struct sysdev_class s5p6440_sysclass = {
         .name   = "s5p6440-core",
 };
 
diff --git a/arch/arm/mach-s5p6440/dma.c b/arch/arm/mach-s5p6440/dma.c
new file mode 100644
index 000000000000..07606ad57519
--- /dev/null
+++ b/arch/arm/mach-s5p6440/dma.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <plat/devs.h>
+#include <plat/irqs.h>
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+
+#include <plat/s3c-pl330-pdata.h>
+
+static u64 dma_dmamask = DMA_BIT_MASK(32);
+
+static struct resource s5p6440_pdma_resource[] = {
+        [0] = {
+                .start  = S5P6440_PA_PDMA,
+                .end    = S5P6440_PA_PDMA + SZ_4K,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_DMA0,
+                .end    = IRQ_DMA0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c_pl330_platdata s5p6440_pdma_pdata = {
+        .peri = {
+                [0] = DMACH_UART0_RX,
+                [1] = DMACH_UART0_TX,
+                [2] = DMACH_UART1_RX,
+                [3] = DMACH_UART1_TX,
+                [4] = DMACH_UART2_RX,
+                [5] = DMACH_UART2_TX,
+                [6] = DMACH_UART3_RX,
+                [7] = DMACH_UART3_TX,
+                [8] = DMACH_MAX,
+                [9] = DMACH_MAX,
+                [10] = DMACH_PCM0_TX,
+                [11] = DMACH_PCM0_RX,
+                [12] = DMACH_I2S0_TX,
+                [13] = DMACH_I2S0_RX,
+                [14] = DMACH_SPI0_TX,
+                [15] = DMACH_SPI0_RX,
+                [16] = DMACH_MAX,
+                [17] = DMACH_MAX,
+                [18] = DMACH_MAX,
+                [19] = DMACH_MAX,
+                [20] = DMACH_SPI1_TX,
+                [21] = DMACH_SPI1_RX,
+                [22] = DMACH_MAX,
+                [23] = DMACH_MAX,
+                [24] = DMACH_MAX,
+                [25] = DMACH_MAX,
+                [26] = DMACH_MAX,
+                [27] = DMACH_MAX,
+                [28] = DMACH_MAX,
+                [29] = DMACH_PWM,
+                [30] = DMACH_MAX,
+                [31] = DMACH_MAX,
+        },
+};
+
+static struct platform_device s5p6440_device_pdma = {
+        .name           = "s3c-pl330",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(s5p6440_pdma_resource),
+        .resource       = s5p6440_pdma_resource,
+        .dev            = {
+                .dma_mask = &dma_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &s5p6440_pdma_pdata,
+        },
+};
+
+static struct platform_device *s5p6440_dmacs[] __initdata = {
+        &s5p6440_device_pdma,
+};
+
+static int __init s5p6440_dma_init(void)
+{
+        platform_add_devices(s5p6440_dmacs, ARRAY_SIZE(s5p6440_dmacs));
+
+        return 0;
+}
+arch_initcall(s5p6440_dma_init);
diff --git a/arch/arm/mach-s5p6440/gpio.c b/arch/arm/mach-s5p6440/gpio.c
index b0ea741177ad..262dc75d5bea 100644
--- a/arch/arm/mach-s5p6440/gpio.c
+++ b/arch/arm/mach-s5p6440/gpio.c
@@ -161,12 +161,15 @@ static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
         }, {
                 .cfg_eint       = 0,
                 .set_config     = s3c_gpio_setcfg_s3c24xx,
+                .get_config     = s3c_gpio_getcfg_s3c24xx,
         }, {
                 .cfg_eint       = 2,
                 .set_config     = s3c_gpio_setcfg_s3c24xx,
+                .get_config     = s3c_gpio_getcfg_s3c24xx,
         }, {
                 .cfg_eint       = 3,
                 .set_config     = s3c_gpio_setcfg_s3c24xx,
+                .get_config     = s3c_gpio_getcfg_s3c24xx,
         },
 };
 
@@ -279,6 +282,8 @@ void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
         for (; nr_chips > 0; nr_chips--, chipcfg++) {
                 if (!chipcfg->set_config)
                         chipcfg->set_config     = s3c_gpio_setcfg_s3c64xx_4bit;
+                if (!chipcfg->get_config)
+                        chipcfg->get_config     = s3c_gpio_getcfg_s3c64xx_4bit;
                 if (!chipcfg->set_pull)
                         chipcfg->set_pull       = s3c_gpio_setpull_updown;
                 if (!chipcfg->get_pull)
diff --git a/arch/arm/mach-s5p6440/include/mach/dma.h b/arch/arm/mach-s5p6440/include/mach/dma.h
new file mode 100644
index 000000000000..81209eb1409b
--- /dev/null
+++ b/arch/arm/mach-s5p6440/include/mach/dma.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __MACH_DMA_H
+#define __MACH_DMA_H
+
+/* This platform uses the common S3C DMA API driver for PL330 */
+#include <plat/s3c-dma-pl330.h>
+
+#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h
index ccbfdaea6eb6..72aedadd412c 100644
--- a/arch/arm/mach-s5p6440/include/mach/map.h
+++ b/arch/arm/mach-s5p6440/include/mach/map.h
@@ -29,6 +29,8 @@
 #define S5P6440_PA_VIC0         (0xE4000000)
 #define S5P_PA_VIC0             S5P6440_PA_VIC0
 
+#define S5P6440_PA_PDMA         0xE9000000
+
 #define S5P6440_PA_VIC1         (0xE4100000)
 #define S5P_PA_VIC1             S5P6440_PA_VIC1
 
diff --git a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h b/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
index c4bb7c555477..6a2a02fdf12a 100644
--- a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
+++ b/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
@@ -1,11 +1,14 @@
 /* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
  *
+ * Copyright (c) 2009 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Copyright 2008 Openmoko, Inc.
  * Copyright 2008 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *      http://armlinux.simtec.co.uk/
  *
- * Copyright 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
  *
  * S5P6440 - pwm clock and timer support
  *
@@ -14,16 +17,19 @@
  * published by the Free Software Foundation.
 */
 
+#ifndef __ASM_ARCH_PWMCLK_H
+#define __ASM_ARCH_PWMCLK_H __FILE__
+
 /**
  * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @cfg: The timer TCFG1 register bits shifted down to 0.
+ * @tcfg: The timer TCFG1 register bits shifted down to 0.
  *
  * Return true if the given configuration from TCFG1 is a TCLK instead
  * any of the TDIV clocks.
  */
 static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
 {
-        return tcfg == S3C2410_TCFG1_MUX_TCLK;
+        return 0;
 }
 
 /**
@@ -35,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
  */
 static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
 {
-        return 1 << (1 + tcfg1);
+        return 1 << tcfg1;
 }
 
 /**
@@ -45,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
  */
 static inline unsigned int pwm_tdiv_has_div1(void)
 {
-        return 0;
+        return 1;
 }
 
 /**
@@ -56,7 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void)
  */
 static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
 {
-        return ilog2(div) - 1;
+        return ilog2(div);
 }
 
-#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK
+#define S3C_TCFG1_MUX_TCLK 0
+
+#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-s5p6442/Kconfig b/arch/arm/mach-s5p6442/Kconfig
index 4f3f6de6a013..0fd41b447915 100644
--- a/arch/arm/mach-s5p6442/Kconfig
+++ b/arch/arm/mach-s5p6442/Kconfig
@@ -12,6 +12,7 @@ if ARCH_S5P6442
 config CPU_S5P6442
         bool
         select PLAT_S5P
+        select S3C_PL330_DMA
         help
           Enable S5P6442 CPU support
 
diff --git a/arch/arm/mach-s5p6442/Makefile b/arch/arm/mach-s5p6442/Makefile
index a43d5da5c583..bf30550349cf 100644
--- a/arch/arm/mach-s5p6442/Makefile
+++ b/arch/arm/mach-s5p6442/Makefile
@@ -12,7 +12,7 @@ obj-				:=
 
 # Core support for S5P6442 system
 
-obj-$(CONFIG_CPU_S5P6442)       += cpu.o init.o clock.o
+obj-$(CONFIG_CPU_S5P6442)       += cpu.o init.o clock.o dma.o
 
 # machine support
 
diff --git a/arch/arm/mach-s5p6442/cpu.c b/arch/arm/mach-s5p6442/cpu.c
index bc2524df89b3..a48fb553fd01 100644
--- a/arch/arm/mach-s5p6442/cpu.c
+++ b/arch/arm/mach-s5p6442/cpu.c
@@ -95,7 +95,7 @@ void __init s5p6442_init_irq(void)
         s5p_init_irq(vic, ARRAY_SIZE(vic));
 }
 
-static struct sysdev_class s5p6442_sysclass = {
+struct sysdev_class s5p6442_sysclass = {
         .name   = "s5p6442-core",
 };
 
diff --git a/arch/arm/mach-s5p6442/dma.c b/arch/arm/mach-s5p6442/dma.c
new file mode 100644
index 000000000000..ad4f8704b93d
--- /dev/null
+++ b/arch/arm/mach-s5p6442/dma.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <plat/devs.h>
+#include <plat/irqs.h>
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+
+#include <plat/s3c-pl330-pdata.h>
+
+static u64 dma_dmamask = DMA_BIT_MASK(32);
+
+static struct resource s5p6442_pdma_resource[] = {
+        [0] = {
+                .start  = S5P6442_PA_PDMA,
+                .end    = S5P6442_PA_PDMA + SZ_4K,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_PDMA,
+                .end    = IRQ_PDMA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c_pl330_platdata s5p6442_pdma_pdata = {
+        .peri = {
+                [0] = DMACH_UART0_RX,
+                [1] = DMACH_UART0_TX,
+                [2] = DMACH_UART1_RX,
+                [3] = DMACH_UART1_TX,
+                [4] = DMACH_UART2_RX,
+                [5] = DMACH_UART2_TX,
+                [6] = DMACH_MAX,
+                [7] = DMACH_MAX,
+                [8] = DMACH_MAX,
+                [9] = DMACH_I2S0_RX,
+                [10] = DMACH_I2S0_TX,
+                [11] = DMACH_I2S0S_TX,
+                [12] = DMACH_I2S1_RX,
+                [13] = DMACH_I2S1_TX,
+                [14] = DMACH_MAX,
+                [15] = DMACH_MAX,
+                [16] = DMACH_SPI0_RX,
+                [17] = DMACH_SPI0_TX,
+                [18] = DMACH_MAX,
+                [19] = DMACH_MAX,
+                [20] = DMACH_PCM0_RX,
+                [21] = DMACH_PCM0_TX,
+                [22] = DMACH_PCM1_RX,
+                [23] = DMACH_PCM1_TX,
+                [24] = DMACH_MAX,
+                [25] = DMACH_MAX,
+                [26] = DMACH_MAX,
+                [27] = DMACH_MSM_REQ0,
+                [28] = DMACH_MSM_REQ1,
+                [29] = DMACH_MSM_REQ2,
+                [30] = DMACH_MSM_REQ3,
+                [31] = DMACH_MAX,
+        },
+};
+
+static struct platform_device s5p6442_device_pdma = {
+        .name           = "s3c-pl330",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(s5p6442_pdma_resource),
+        .resource       = s5p6442_pdma_resource,
+        .dev            = {
+                .dma_mask = &dma_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &s5p6442_pdma_pdata,
+        },
+};
+
+static struct platform_device *s5p6442_dmacs[] __initdata = {
+        &s5p6442_device_pdma,
+};
+
+static int __init s5p6442_dma_init(void)
+{
+        platform_add_devices(s5p6442_dmacs, ARRAY_SIZE(s5p6442_dmacs));
+
+        return 0;
+}
+arch_initcall(s5p6442_dma_init);
diff --git a/arch/arm/mach-s5p6442/include/mach/dma.h b/arch/arm/mach-s5p6442/include/mach/dma.h
new file mode 100644
index 000000000000..81209eb1409b
--- /dev/null
+++ b/arch/arm/mach-s5p6442/include/mach/dma.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __MACH_DMA_H
+#define __MACH_DMA_H
+
+/* This platform uses the common S3C DMA API driver for PL330 */
+#include <plat/s3c-dma-pl330.h>
+
+#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h
index 767c596143c4..7568dc0d6be0 100644
--- a/arch/arm/mach-s5p6442/include/mach/map.h
+++ b/arch/arm/mach-s5p6442/include/mach/map.h
@@ -34,6 +34,9 @@
 #define S5P6442_PA_VIC2         (0xE4200000)
 #define S5P_PA_VIC2             S5P6442_PA_VIC2
 
+#define S5P6442_PA_MDMA         0xE8000000
+#define S5P6442_PA_PDMA         0xE9000000
+
 #define S5P6442_PA_TIMER        (0xEA000000)
 #define S5P_PA_TIMER            S5P6442_PA_TIMER
 
diff --git a/arch/arm/mach-s5p6442/include/mach/pwm-clock.h b/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
index 15e8525da0f1..2724b37def31 100644
--- a/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
+++ b/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
@@ -1,13 +1,14 @@
 /* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
  *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Copyright 2008 Openmoko, Inc.
  * Copyright 2008 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *      http://armlinux.simtec.co.uk/
  *
- * Copyright 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Based on arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
+ * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
  *
  * S5P6442 - pwm clock and timer support
  *
@@ -21,14 +22,14 @@
 
 /**
  * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @cfg: The timer TCFG1 register bits shifted down to 0.
+ * @tcfg: The timer TCFG1 register bits shifted down to 0.
  *
  * Return true if the given configuration from TCFG1 is a TCLK instead
  * any of the TDIV clocks.
  */
 static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
 {
-        return tcfg == S3C2410_TCFG1_MUX_TCLK;
+        return tcfg == S3C64XX_TCFG1_MUX_TCLK;
 }
 
 /**
@@ -40,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
  */
 static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
 {
-        return 1 << (1 + tcfg1);
+        return 1 << tcfg1;
 }
 
 /**
@@ -50,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
  */
 static inline unsigned int pwm_tdiv_has_div1(void)
 {
-        return 0;
+        return 1;
 }
 
 /**
@@ -61,9 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void)
  */
 static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
 {
-        return ilog2(div) - 1;
+        return ilog2(div);
 }
 
-#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK
+#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
 
 #endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index af33a1a89b72..7601c28e240b 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -12,6 +12,7 @@ if ARCH_S5PV210
 config CPU_S5PV210
         bool
         select PLAT_S5P
+        select S3C_PL330_DMA
         help
           Enable S5PV210 CPU support
 
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index e435afe7cffe..1d60b358589b 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -12,7 +12,7 @@ obj-				:=
 
 # Core support for S5PV210 system
 
-obj-$(CONFIG_CPU_S5PV210)       += cpu.o init.o clock.o
+obj-$(CONFIG_CPU_S5PV210)       += cpu.o init.o clock.o dma.o gpiolib.o
 
 # machine support
 
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index ccccae262351..154bca4abc09 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -31,6 +31,128 @@
 #include <plat/clock-clksrc.h>
 #include <plat/s5pv210.h>
 
+static struct clksrc_clk clk_mout_apll = {
+        .clk    = {
+                .name           = "mout_apll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_apll,
+        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk clk_mout_epll = {
+        .clk    = {
+                .name           = "mout_epll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_epll,
+        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk clk_mout_mpll = {
+        .clk = {
+                .name           = "mout_mpll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_mpll,
+        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
+};
+
+static struct clk *clkset_armclk_list[] = {
+        [0] = &clk_mout_apll.clk,
+        [1] = &clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_armclk = {
+        .sources        = clkset_armclk_list,
+        .nr_sources     = ARRAY_SIZE(clkset_armclk_list),
+};
+
+static struct clksrc_clk clk_armclk = {
+        .clk    = {
+                .name           = "armclk",
+                .id             = -1,
+        },
+        .sources        = &clkset_armclk,
+        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
+        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk clk_hclk_msys = {
+        .clk    = {
+                .name           = "hclk_msys",
+                .id             = -1,
+                .parent         = &clk_armclk.clk,
+        },
+        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk clk_pclk_msys = {
+        .clk    = {
+                .name           = "pclk_msys",
+                .id             = -1,
+                .parent         = &clk_hclk_msys.clk,
+        },
+        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk clk_sclk_a2m = {
+        .clk    = {
+                .name           = "sclk_a2m",
+                .id             = -1,
+                .parent         = &clk_mout_apll.clk,
+        },
+        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
+};
+
+static struct clk *clkset_hclk_sys_list[] = {
+        [0] = &clk_mout_mpll.clk,
+        [1] = &clk_sclk_a2m.clk,
+};
+
+static struct clksrc_sources clkset_hclk_sys = {
+        .sources        = clkset_hclk_sys_list,
+        .nr_sources     = ARRAY_SIZE(clkset_hclk_sys_list),
+};
+
+static struct clksrc_clk clk_hclk_dsys = {
+        .clk    = {
+                .name   = "hclk_dsys",
+                .id     = -1,
+        },
+        .sources        = &clkset_hclk_sys,
+        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
+        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk_dsys = {
+        .clk    = {
+                .name   = "pclk_dsys",
+                .id     = -1,
+                .parent = &clk_hclk_dsys.clk,
+        },
+        .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
+};
+
+static struct clksrc_clk clk_hclk_psys = {
+        .clk    = {
+                .name   = "hclk_psys",
+                .id     = -1,
+        },
+        .sources        = &clkset_hclk_sys,
+        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
+        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk_psys = {
+        .clk    = {
+                .name   = "pclk_psys",
+                .id     = -1,
+                .parent = &clk_hclk_psys.clk,
+        },
+        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
+};
+
 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
@@ -51,176 +173,226 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
 }
 
-static struct clk clk_h200 = {
-        .name           = "hclk200",
+static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable);
+}
+
+static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
+}
+
+static struct clk clk_sclk_hdmi27m = {
+        .name           = "sclk_hdmi27m",
         .id             = -1,
+        .rate           = 27000000,
 };
 
-static struct clk clk_h100 = {
-        .name           = "hclk100",
+static struct clk clk_sclk_hdmiphy = {
+        .name           = "sclk_hdmiphy",
         .id             = -1,
 };
 
-static struct clk clk_h166 = {
-        .name           = "hclk166",
+static struct clk clk_sclk_usbphy0 = {
+        .name           = "sclk_usbphy0",
         .id             = -1,
 };
 
-static struct clk clk_h133 = {
-        .name           = "hclk133",
+static struct clk clk_sclk_usbphy1 = {
+        .name           = "sclk_usbphy1",
         .id             = -1,
 };
 
-static struct clk clk_p100 = {
-        .name           = "pclk100",
+static struct clk clk_pcmcdclk0 = {
+        .name           = "pcmcdclk",
         .id             = -1,
 };
 
-static struct clk clk_p83 = {
-        .name           = "pclk83",
+static struct clk clk_pcmcdclk1 = {
+        .name           = "pcmcdclk",
         .id             = -1,
 };
 
-static struct clk clk_p66 = {
-        .name           = "pclk66",
+static struct clk clk_pcmcdclk2 = {
+        .name           = "pcmcdclk",
         .id             = -1,
 };
 
-static struct clk *sys_clks[] = {
-        &clk_h200,
-        &clk_h100,
-        &clk_h166,
-        &clk_h133,
-        &clk_p100,
-        &clk_p83,
-        &clk_p66
+static struct clk *clkset_vpllsrc_list[] = {
+        [0] = &clk_fin_vpll,
+        [1] = &clk_sclk_hdmi27m,
+};
+
+static struct clksrc_sources clkset_vpllsrc = {
+        .sources        = clkset_vpllsrc_list,
+        .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
+};
+
+static struct clksrc_clk clk_vpllsrc = {
+        .clk    = {
+                .name           = "vpll_src",
+                .id             = -1,
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 7),
+        },
+        .sources        = &clkset_vpllsrc,
+        .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
+};
+
+static struct clk *clkset_sclk_vpll_list[] = {
+        [0] = &clk_vpllsrc.clk,
+        [1] = &clk_fout_vpll,
+};
+
+static struct clksrc_sources clkset_sclk_vpll = {
+        .sources        = clkset_sclk_vpll_list,
+        .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
+};
+
+static struct clksrc_clk clk_sclk_vpll = {
+        .clk    = {
+                .name           = "sclk_vpll",
+                .id             = -1,
+        },
+        .sources        = &clkset_sclk_vpll,
+        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
+};
+
+static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / 2;
+}
+
+static struct clk_ops clk_hclk_imem_ops = {
+        .get_rate       = s5pv210_clk_imem_get_rate,
 };
 
 static struct clk init_clocks_disable[] = {
         {
                 .name           = "rot",
                 .id             = -1,
-                .parent         = &clk_h166,
+                .parent         = &clk_hclk_dsys.clk,
                 .enable         = s5pv210_clk_ip0_ctrl,
                 .ctrlbit        = (1<<29),
         }, {
                 .name           = "otg",
                 .id             = -1,
-                .parent         = &clk_h133,
+                .parent         = &clk_hclk_psys.clk,
                 .enable         = s5pv210_clk_ip1_ctrl,
                 .ctrlbit        = (1<<16),
         }, {
                 .name           = "usb-host",
                 .id             = -1,
-                .parent         = &clk_h133,
+                .parent         = &clk_hclk_psys.clk,
                 .enable         = s5pv210_clk_ip1_ctrl,
                 .ctrlbit        = (1<<17),
         }, {
                 .name           = "lcd",
                 .id             = -1,
-                .parent         = &clk_h166,
+                .parent         = &clk_hclk_dsys.clk,
                 .enable         = s5pv210_clk_ip1_ctrl,
                 .ctrlbit        = (1<<0),
         }, {
                 .name           = "cfcon",
                 .id             = 0,
-                .parent         = &clk_h133,
+                .parent         = &clk_hclk_psys.clk,
                 .enable         = s5pv210_clk_ip1_ctrl,
                 .ctrlbit        = (1<<25),
         }, {
                 .name           = "hsmmc",
                 .id             = 0,
-                .parent         = &clk_h133,
+                .parent         = &clk_hclk_psys.clk,
                 .enable         = s5pv210_clk_ip2_ctrl,
                 .ctrlbit        = (1<<16),
         }, {
                 .name           = "hsmmc",
                 .id             = 1,
-                .parent         = &clk_h133,
+                .parent         = &clk_hclk_psys.clk,
                 .enable         = s5pv210_clk_ip2_ctrl,
                 .ctrlbit        = (1<<17),
         }, {
                 .name           = "hsmmc",
                 .id             = 2,
-                .parent         = &clk_h133,
+                .parent         = &clk_hclk_psys.clk,
                 .enable         = s5pv210_clk_ip2_ctrl,
                 .ctrlbit        = (1<<18),
         }, {
                 .name           = "hsmmc",
                 .id             = 3,
-                .parent         = &clk_h133,
+                .parent         = &clk_hclk_psys.clk,
                 .enable         = s5pv210_clk_ip2_ctrl,
                 .ctrlbit        = (1<<19),
         }, {
                 .name           = "systimer",
                 .id             = -1,
-                .parent         = &clk_p66,
+                .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<16),
         }, {
                 .name           = "watchdog",
                 .id             = -1,
-                .parent         = &clk_p66,
+                .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<22),
         }, {
                 .name           = "rtc",
                 .id             = -1,
-                .parent         = &clk_p66,
+                .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<15),
         }, {
                 .name           = "i2c",
                 .id             = 0,
-                .parent         = &clk_p66,
+                .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<7),
         }, {
                 .name           = "i2c",
                 .id             = 1,
-                .parent         = &clk_p66,
+                .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<8),
         }, {
                 .name           = "i2c",
                 .id             = 2,
-                .parent         = &clk_p66,
+                .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<9),
         }, {
                 .name           = "spi",
                 .id             = 0,
-                .parent         = &clk_p66,
+                .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<12),
         }, {
                 .name           = "spi",
                 .id             = 1,
-                .parent         = &clk_p66,
+                .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<13),
         }, {
                 .name           = "spi",
                 .id             = 2,
-                .parent         = &clk_p66,
+                .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<14),
         }, {
                 .name           = "timers",
                 .id             = -1,
-                .parent         = &clk_p66,
+                .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<23),
         }, {
                 .name           = "adc",
                 .id             = -1,
-                .parent         = &clk_p66,
+                .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<24),
         }, {
                 .name           = "keypad",
                 .id             = -1,
-                .parent         = &clk_p66,
+                .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<21),
         }, {
@@ -246,106 +418,537 @@ static struct clk init_clocks_disable[] = {
 
 static struct clk init_clocks[] = {
         {
+                .name           = "hclk_imem",
+                .id             = -1,
+                .parent         = &clk_hclk_msys.clk,
+                .ctrlbit        = (1 << 5),
+                .enable         = s5pv210_clk_ip0_ctrl,
+                .ops            = &clk_hclk_imem_ops,
+        }, {
                 .name           = "uart",
                 .id             = 0,
-                .parent         = &clk_p66,
+                .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<7),
         }, {
                 .name           = "uart",
                 .id             = 1,
-                .parent         = &clk_p66,
+                .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<8),
         }, {
                 .name           = "uart",
                 .id             = 2,
-                .parent         = &clk_p66,
+                .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<9),
         }, {
                 .name           = "uart",
                 .id             = 3,
-                .parent         = &clk_p66,
+                .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<10),
         },
 };
 
-static struct clksrc_clk clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
+static struct clk *clkset_uart_list[] = {
+        [6] = &clk_mout_mpll.clk,
+        [7] = &clk_mout_epll.clk,
+};
+
+static struct clksrc_sources clkset_uart = {
+        .sources        = clkset_uart_list,
+        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
+};
+
+static struct clk *clkset_group1_list[] = {
+        [0] = &clk_sclk_a2m.clk,
+        [1] = &clk_mout_mpll.clk,
+        [2] = &clk_mout_epll.clk,
+        [3] = &clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources clkset_group1 = {
+        .sources        = clkset_group1_list,
+        .nr_sources     = ARRAY_SIZE(clkset_group1_list),
+};
+
+static struct clk *clkset_sclk_onenand_list[] = {
+        [0] = &clk_hclk_psys.clk,
+        [1] = &clk_hclk_dsys.clk,
+};
+
+static struct clksrc_sources clkset_sclk_onenand = {
+        .sources        = clkset_sclk_onenand_list,
+        .nr_sources     = ARRAY_SIZE(clkset_sclk_onenand_list),
+};
+
+static struct clk *clkset_sclk_dac_list[] = {
+        [0] = &clk_sclk_vpll.clk,
+        [1] = &clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources clkset_sclk_dac = {
+        .sources        = clkset_sclk_dac_list,
+        .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
+};
+
+static struct clksrc_clk clk_sclk_dac = {
+        .clk            = {
+                .name           = "sclk_dac",
                 .id             = -1,
+                .ctrlbit        = (1 << 10),
+                .enable         = s5pv210_clk_ip1_ctrl,
         },
-        .sources        = &clk_src_apll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
+        .sources        = &clkset_sclk_dac,
+        .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
 };
 
-static struct clksrc_clk clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
+static struct clksrc_clk clk_sclk_pixel = {
+        .clk            = {
+                .name           = "sclk_pixel",
                 .id             = -1,
+                .parent         = &clk_sclk_vpll.clk,
         },
-        .sources        = &clk_src_epll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
+        .reg_div        = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
 };
 
-static struct clksrc_clk clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
+static struct clk *clkset_sclk_hdmi_list[] = {
+        [0] = &clk_sclk_pixel.clk,
+        [1] = &clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources clkset_sclk_hdmi = {
+        .sources        = clkset_sclk_hdmi_list,
+        .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk clk_sclk_hdmi = {
+        .clk            = {
+                .name           = "sclk_hdmi",
                 .id             = -1,
+                .enable         = s5pv210_clk_ip1_ctrl,
+                .ctrlbit        = (1 << 11),
         },
-        .sources        = &clk_src_mpll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
+        .sources        = &clkset_sclk_hdmi,
+        .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
 };
 
-static struct clk *clkset_uart_list[] = {
+static struct clk *clkset_sclk_mixer_list[] = {
+        [0] = &clk_sclk_dac.clk,
+        [1] = &clk_sclk_hdmi.clk,
+};
+
+static struct clksrc_sources clkset_sclk_mixer = {
+        .sources        = clkset_sclk_mixer_list,
+        .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
+};
+
+static struct clk *clkset_sclk_audio0_list[] = {
+        [0] = &clk_ext_xtal_mux,
+        [1] = &clk_pcmcdclk0,
+        [2] = &clk_sclk_hdmi27m,
+        [3] = &clk_sclk_usbphy0,
+        [4] = &clk_sclk_usbphy1,
+        [5] = &clk_sclk_hdmiphy,
         [6] = &clk_mout_mpll.clk,
         [7] = &clk_mout_epll.clk,
+        [8] = &clk_sclk_vpll.clk,
 };
 
-static struct clksrc_sources clkset_uart = {
-        .sources        = clkset_uart_list,
-        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
+static struct clksrc_sources clkset_sclk_audio0 = {
+        .sources        = clkset_sclk_audio0_list,
+        .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
+};
+
+static struct clksrc_clk clk_sclk_audio0 = {
+        .clk            = {
+                .name           = "sclk_audio",
+                .id             = 0,
+                .enable         = s5pv210_clk_ip3_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .sources = &clkset_sclk_audio0,
+        .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
+};
+
+static struct clk *clkset_sclk_audio1_list[] = {
+        [0] = &clk_ext_xtal_mux,
+        [1] = &clk_pcmcdclk1,
+        [2] = &clk_sclk_hdmi27m,
+        [3] = &clk_sclk_usbphy0,
+        [4] = &clk_sclk_usbphy1,
+        [5] = &clk_sclk_hdmiphy,
+        [6] = &clk_mout_mpll.clk,
+        [7] = &clk_mout_epll.clk,
+        [8] = &clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources clkset_sclk_audio1 = {
+        .sources        = clkset_sclk_audio1_list,
+        .nr_sources     = ARRAY_SIZE(clkset_sclk_audio1_list),
+};
+
+static struct clksrc_clk clk_sclk_audio1 = {
+        .clk            = {
+                .name           = "sclk_audio",
+                .id             = 1,
+                .enable         = s5pv210_clk_ip3_ctrl,
+                .ctrlbit        = (1 << 5),
+        },
+        .sources = &clkset_sclk_audio1,
+        .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
+};
+
+static struct clk *clkset_sclk_audio2_list[] = {
+        [0] = &clk_ext_xtal_mux,
+        [1] = &clk_pcmcdclk0,
+        [2] = &clk_sclk_hdmi27m,
+        [3] = &clk_sclk_usbphy0,
+        [4] = &clk_sclk_usbphy1,
+        [5] = &clk_sclk_hdmiphy,
+        [6] = &clk_mout_mpll.clk,
+        [7] = &clk_mout_epll.clk,
+        [8] = &clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources clkset_sclk_audio2 = {
+        .sources        = clkset_sclk_audio2_list,
+        .nr_sources     = ARRAY_SIZE(clkset_sclk_audio2_list),
+};
+
+static struct clksrc_clk clk_sclk_audio2 = {
+        .clk            = {
+                .name           = "sclk_audio",
+                .id             = 2,
+                .enable         = s5pv210_clk_ip3_ctrl,
+                .ctrlbit        = (1 << 6),
+        },
+        .sources = &clkset_sclk_audio2,
+        .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
+};
+
+static struct clk *clkset_sclk_spdif_list[] = {
+        [0] = &clk_sclk_audio0.clk,
+        [1] = &clk_sclk_audio1.clk,
+        [2] = &clk_sclk_audio2.clk,
+};
+
+static struct clksrc_sources clkset_sclk_spdif = {
+        .sources        = clkset_sclk_spdif_list,
+        .nr_sources     = ARRAY_SIZE(clkset_sclk_spdif_list),
+};
+
+static struct clk *clkset_group2_list[] = {
+        [0] = &clk_ext_xtal_mux,
+        [1] = &clk_xusbxti,
+        [2] = &clk_sclk_hdmi27m,
+        [3] = &clk_sclk_usbphy0,
+        [4] = &clk_sclk_usbphy1,
+        [5] = &clk_sclk_hdmiphy,
+        [6] = &clk_mout_mpll.clk,
+        [7] = &clk_mout_epll.clk,
+        [8] = &clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources clkset_group2 = {
+        .sources        = clkset_group2_list,
+        .nr_sources     = ARRAY_SIZE(clkset_group2_list),
 };
 
 static struct clksrc_clk clksrcs[] = {
         {
                 .clk    = {
-                        .name           = "uclk1",
+                        .name           = "sclk_dmc",
                         .id             = -1,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_onenand",
+                        .id             = -1,
+                },
+                .sources = &clkset_sclk_onenand,
+                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
+                .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
+        }, {
+                .clk    = {
+                        .name           = "uclk1",
+                        .id             = 0,
                         .ctrlbit        = (1<<17),
                         .enable         = s5pv210_clk_ip3_ctrl,
                 },
                 .sources = &clkset_uart,
                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
-        }
+        }, {
+                .clk            = {
+                        .name           = "uclk1",
+                        .id             = 1,
+                        .enable         = s5pv210_clk_ip3_ctrl,
+                        .ctrlbit        = (1 << 18),
+                },
+                .sources = &clkset_uart,
+                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "uclk1",
+                        .id             = 2,
+                        .enable         = s5pv210_clk_ip3_ctrl,
+                        .ctrlbit        = (1 << 19),
+                },
+                .sources = &clkset_uart,
+                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "uclk1",
+                        .id             = 3,
+                        .enable         = s5pv210_clk_ip3_ctrl,
+                        .ctrlbit        = (1 << 20),
+                },
+                .sources = &clkset_uart,
+                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_mixer",
+                        .id             = -1,
+                        .enable         = s5pv210_clk_ip1_ctrl,
+                        .ctrlbit        = (1 << 9),
+                },
+                .sources = &clkset_sclk_mixer,
+                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_spdif",
+                        .id             = -1,
+                        .enable         = s5pv210_clk_mask0_ctrl,
+                        .ctrlbit        = (1 << 27),
+                },
+                .sources = &clkset_sclk_spdif,
+                .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .id             = 0,
+                        .enable         = s5pv210_clk_ip0_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .id             = 1,
+                        .enable         = s5pv210_clk_ip0_ctrl,
+                        .ctrlbit        = (1 << 25),
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .id             = 2,
+                        .enable         = s5pv210_clk_ip0_ctrl,
+                        .ctrlbit        = (1 << 26),
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_cam",
+                        .id             = 0,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_cam",
+                        .id             = 1,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_fimd",
+                        .id             = -1,
+                        .enable         = s5pv210_clk_ip1_ctrl,
+                        .ctrlbit        = (1 << 0),
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_mmc",
+                        .id             = 0,
+                        .enable         = s5pv210_clk_ip2_ctrl,
+                        .ctrlbit        = (1 << 16),
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_mmc",
+                        .id             = 1,
+                        .enable         = s5pv210_clk_ip2_ctrl,
+                        .ctrlbit        = (1 << 17),
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_mmc",
+                        .id             = 2,
+                        .enable         = s5pv210_clk_ip2_ctrl,
+                        .ctrlbit        = (1 << 18),
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_mmc",
+                        .id             = 3,
+                        .enable         = s5pv210_clk_ip2_ctrl,
+                        .ctrlbit        = (1 << 19),
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_mfc",
+                        .id             = -1,
+                        .enable         = s5pv210_clk_ip0_ctrl,
+                        .ctrlbit        = (1 << 16),
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_g2d",
+                        .id             = -1,
+                        .enable         = s5pv210_clk_ip0_ctrl,
+                        .ctrlbit        = (1 << 12),
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_g3d",
+                        .id             = -1,
+                        .enable         = s5pv210_clk_ip0_ctrl,
+                        .ctrlbit        = (1 << 8),
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_csis",
+                        .id             = -1,
+                        .enable         = s5pv210_clk_ip0_ctrl,
+                        .ctrlbit        = (1 << 31),
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_spi",
+                        .id             = 0,
+                        .enable         = s5pv210_clk_ip3_ctrl,
+                        .ctrlbit        = (1 << 12),
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_spi",
+                        .id             = 1,
+                        .enable         = s5pv210_clk_ip3_ctrl,
+                        .ctrlbit        = (1 << 13),
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_pwi",
+                        .id             = -1,
+                        .enable         = &s5pv210_clk_ip4_ctrl,
+                        .ctrlbit        = (1 << 2),
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_pwm",
+                        .id             = -1,
+                        .enable         = s5pv210_clk_ip3_ctrl,
+                        .ctrlbit        = (1 << 23),
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
+                .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
+        },
 };
 
 /* Clock initialisation code */
-static struct clksrc_clk *init_parents[] = {
+static struct clksrc_clk *sysclks[] = {
         &clk_mout_apll,
         &clk_mout_epll,
         &clk_mout_mpll,
+        &clk_armclk,
+        &clk_hclk_msys,
+        &clk_sclk_a2m,
+        &clk_hclk_dsys,
+        &clk_hclk_psys,
+        &clk_pclk_msys,
+        &clk_pclk_dsys,
+        &clk_pclk_psys,
+        &clk_vpllsrc,
+        &clk_sclk_vpll,
+        &clk_sclk_dac,
+        &clk_sclk_pixel,
+        &clk_sclk_hdmi,
 };
 
-#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
-
 void __init_or_cpufreq s5pv210_setup_clocks(void)
 {
         struct clk *xtal_clk;
         unsigned long xtal;
+        unsigned long vpllsrc;
         unsigned long armclk;
-        unsigned long hclk200;
-        unsigned long hclk166;
-        unsigned long hclk133;
-        unsigned long pclk100;
-        unsigned long pclk83;
-        unsigned long pclk66;
+        unsigned long hclk_msys;
+        unsigned long hclk_dsys;
+        unsigned long hclk_psys;
+        unsigned long pclk_msys;
+        unsigned long pclk_dsys;
+        unsigned long pclk_psys;
         unsigned long apll;
         unsigned long mpll;
         unsigned long epll;
+        unsigned long vpll;
         unsigned int ptr;
         u32 clkdiv0, clkdiv1;
 
@@ -368,59 +971,46 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
         epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
-
-        printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
-                        apll, mpll, epll);
-
-        armclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_APLL);
-        if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX200_MASK)
-                hclk200 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200);
-        else
-                hclk200 = armclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200);
-
-        if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX166_MASK) {
-                hclk166 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M);
-                hclk166 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166);
-        } else
-                hclk166 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166);
-
-        if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX133_MASK) {
-                hclk133 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M);
-                hclk133 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
-        } else
-                hclk133 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
-
-        pclk100 = hclk200 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK100);
-        pclk83 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83);
-        pclk66 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);
-
-        printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld, \
-                        HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
-               armclk, hclk200, hclk166, hclk133, pclk100, pclk83, pclk66);
+        vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
+        vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
 
         clk_fout_apll.rate = apll;
         clk_fout_mpll.rate = mpll;
         clk_fout_epll.rate = epll;
+        clk_fout_vpll.rate = vpll;
 
-        clk_f.rate = armclk;
-        clk_h.rate = hclk133;
-        clk_p.rate = pclk66;
-        clk_p66.rate = pclk66;
-        clk_p83.rate = pclk83;
-        clk_h133.rate = hclk133;
-        clk_h166.rate = hclk166;
-        clk_h200.rate = hclk200;
+        printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
+                        apll, mpll, epll, vpll);
+
+        armclk = clk_get_rate(&clk_armclk.clk);
+        hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
+        hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
+        hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
+        pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
+        pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
+        pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
+
+        printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
+                         "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
+                        armclk, hclk_msys, hclk_dsys, hclk_psys,
+                        pclk_msys, pclk_dsys, pclk_psys);
 
-        for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
-                s3c_set_clksrc(init_parents[ptr], true);
+        clk_f.rate = armclk;
+        clk_h.rate = hclk_psys;
+        clk_p.rate = pclk_psys;
 
         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
                 s3c_set_clksrc(&clksrcs[ptr], true);
 }
 
 static struct clk *clks[] __initdata = {
-        &clk_mout_epll.clk,
-        &clk_mout_mpll.clk,
+        &clk_sclk_hdmi27m,
+        &clk_sclk_hdmiphy,
+        &clk_sclk_usbphy0,
+        &clk_sclk_usbphy1,
+        &clk_pcmcdclk0,
+        &clk_pcmcdclk1,
+        &clk_pcmcdclk2,
 };
 
 void __init s5pv210_register_clocks(void)
@@ -433,13 +1023,12 @@ void __init s5pv210_register_clocks(void)
         if (ret > 0)
                 printk(KERN_ERR "Failed to register %u clocks\n", ret);
 
+        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+                s3c_register_clksrc(sysclks[ptr], 1);
+
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
-        ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks));
-        if (ret > 0)
-                printk(KERN_ERR "Failed to register system clocks\n");
-
         clkp = init_clocks_disable;
         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
                 ret = s3c24xx_register_clock(clkp);
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 0e0f8fde2aa6..2b776eb5d150 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -100,7 +100,7 @@ void __init s5pv210_init_irq(void)
         s5p_init_irq(vic, ARRAY_SIZE(vic));
 }
 
-static struct sysdev_class s5pv210_sysclass = {
+struct sysdev_class s5pv210_sysclass = {
         .name   = "s5pv210-core",
 };
 
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c
new file mode 100644
index 000000000000..778ad5fe231a
--- /dev/null
+++ b/arch/arm/mach-s5pv210/dma.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <plat/devs.h>
+#include <plat/irqs.h>
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+
+#include <plat/s3c-pl330-pdata.h>
+
+static u64 dma_dmamask = DMA_BIT_MASK(32);
+
+static struct resource s5pv210_pdma0_resource[] = {
+        [0] = {
+                .start  = S5PV210_PA_PDMA0,
+                .end    = S5PV210_PA_PDMA0 + SZ_4K,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_PDMA0,
+                .end    = IRQ_PDMA0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c_pl330_platdata s5pv210_pdma0_pdata = {
+        .peri = {
+                [0] = DMACH_UART0_RX,
+                [1] = DMACH_UART0_TX,
+                [2] = DMACH_UART1_RX,
+                [3] = DMACH_UART1_TX,
+                [4] = DMACH_UART2_RX,
+                [5] = DMACH_UART2_TX,
+                [6] = DMACH_UART3_RX,
+                [7] = DMACH_UART3_TX,
+                [8] = DMACH_MAX,
+                [9] = DMACH_I2S0_RX,
+                [10] = DMACH_I2S0_TX,
+                [11] = DMACH_I2S0S_TX,
+                [12] = DMACH_I2S1_RX,
+                [13] = DMACH_I2S1_TX,
+                [14] = DMACH_MAX,
+                [15] = DMACH_MAX,
+                [16] = DMACH_SPI0_RX,
+                [17] = DMACH_SPI0_TX,
+                [18] = DMACH_SPI1_RX,
+                [19] = DMACH_SPI1_TX,
+                [20] = DMACH_MAX,
+                [21] = DMACH_MAX,
+                [22] = DMACH_AC97_MICIN,
+                [23] = DMACH_AC97_PCMIN,
+                [24] = DMACH_AC97_PCMOUT,
+                [25] = DMACH_MAX,
+                [26] = DMACH_PWM,
+                [27] = DMACH_SPDIF,
+                [28] = DMACH_MAX,
+                [29] = DMACH_MAX,
+                [30] = DMACH_MAX,
+                [31] = DMACH_MAX,
+        },
+};
+
+static struct platform_device s5pv210_device_pdma0 = {
+        .name           = "s3c-pl330",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(s5pv210_pdma0_resource),
+        .resource       = s5pv210_pdma0_resource,
+        .dev            = {
+                .dma_mask = &dma_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &s5pv210_pdma0_pdata,
+        },
+};
+
+static struct resource s5pv210_pdma1_resource[] = {
+        [0] = {
+                .start  = S5PV210_PA_PDMA1,
+                .end    = S5PV210_PA_PDMA1 + SZ_4K,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_PDMA1,
+                .end    = IRQ_PDMA1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c_pl330_platdata s5pv210_pdma1_pdata = {
+        .peri = {
+                [0] = DMACH_UART0_RX,
+                [1] = DMACH_UART0_TX,
+                [2] = DMACH_UART1_RX,
+                [3] = DMACH_UART1_TX,
+                [4] = DMACH_UART2_RX,
+                [5] = DMACH_UART2_TX,
+                [6] = DMACH_UART3_RX,
+                [7] = DMACH_UART3_TX,
+                [8] = DMACH_MAX,
+                [9] = DMACH_I2S0_RX,
+                [10] = DMACH_I2S0_TX,
+                [11] = DMACH_I2S0S_TX,
+                [12] = DMACH_I2S1_RX,
+                [13] = DMACH_I2S1_TX,
+                [14] = DMACH_I2S2_RX,
+                [15] = DMACH_I2S2_TX,
+                [16] = DMACH_SPI0_RX,
+                [17] = DMACH_SPI0_TX,
+                [18] = DMACH_SPI1_RX,
+                [19] = DMACH_SPI1_TX,
+                [20] = DMACH_MAX,
+                [21] = DMACH_MAX,
+                [22] = DMACH_PCM0_RX,
+                [23] = DMACH_PCM0_TX,
+                [24] = DMACH_PCM1_RX,
+                [25] = DMACH_PCM1_TX,
+                [26] = DMACH_MSM_REQ0,
+                [27] = DMACH_MSM_REQ1,
+                [28] = DMACH_MSM_REQ2,
+                [29] = DMACH_MSM_REQ3,
+                [30] = DMACH_PCM2_RX,
+                [31] = DMACH_PCM2_TX,
+        },
+};
+
+static struct platform_device s5pv210_device_pdma1 = {
+        .name           = "s3c-pl330",
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(s5pv210_pdma1_resource),
+        .resource       = s5pv210_pdma1_resource,
+        .dev            = {
+                .dma_mask = &dma_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &s5pv210_pdma1_pdata,
+        },
+};
+
+static struct platform_device *s5pv210_dmacs[] __initdata = {
+        &s5pv210_device_pdma0,
+        &s5pv210_device_pdma1,
+};
+
+static int __init s5pv210_dma_init(void)
+{
+        platform_add_devices(s5pv210_dmacs, ARRAY_SIZE(s5pv210_dmacs));
+
+        return 0;
+}
+arch_initcall(s5pv210_dma_init);
diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c
new file mode 100644
index 000000000000..9ea8972e023d
--- /dev/null
+++ b/arch/arm/mach-s5pv210/gpiolib.c
@@ -0,0 +1,261 @@
+/* linux/arch/arm/mach-s5pv210/gpiolib.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5PV210 - GPIOlib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+#include <mach/map.h>
+
+static struct s3c_gpio_cfg gpio_cfg = {
+        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .set_pull       = s3c_gpio_setpull_updown,
+        .get_pull       = s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_cfg gpio_cfg_noint = {
+        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .set_pull       = s3c_gpio_setpull_updown,
+        .get_pull       = s3c_gpio_getpull_updown,
+};
+
+/* GPIO bank's base address given the index of the bank in the
+ * list of all gpio banks.
+ */
+#define S5PV210_BANK_BASE(bank_nr)      (S5P_VA_GPIO + ((bank_nr) * 0x20))
+
+/*
+ * Following are the gpio banks in v210.
+ *
+ * The 'config' member when left to NULL, is initialized to the default
+ * structure gpio_cfg in the init function below.
+ *
+ * The 'base' member is also initialized in the init function below.
+ * Note: The initialization of 'base' member of s3c_gpio_chip structure
+ * uses the above macro and depends on the banks being listed in order here.
+ */
+static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
+        {
+                .chip   = {
+                        .base   = S5PV210_GPA0(0),
+                        .ngpio  = S5PV210_GPIO_A0_NR,
+                        .label  = "GPA0",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPA1(0),
+                        .ngpio  = S5PV210_GPIO_A1_NR,
+                        .label  = "GPA1",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPB(0),
+                        .ngpio  = S5PV210_GPIO_B_NR,
+                        .label  = "GPB",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPC0(0),
+                        .ngpio  = S5PV210_GPIO_C0_NR,
+                        .label  = "GPC0",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPC1(0),
+                        .ngpio  = S5PV210_GPIO_C1_NR,
+                        .label  = "GPC1",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPD0(0),
+                        .ngpio  = S5PV210_GPIO_D0_NR,
+                        .label  = "GPD0",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPD1(0),
+                        .ngpio  = S5PV210_GPIO_D1_NR,
+                        .label  = "GPD1",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPE0(0),
+                        .ngpio  = S5PV210_GPIO_E0_NR,
+                        .label  = "GPE0",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPE1(0),
+                        .ngpio  = S5PV210_GPIO_E1_NR,
+                        .label  = "GPE1",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPF0(0),
+                        .ngpio  = S5PV210_GPIO_F0_NR,
+                        .label  = "GPF0",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPF1(0),
+                        .ngpio  = S5PV210_GPIO_F1_NR,
+                        .label  = "GPF1",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPF2(0),
+                        .ngpio  = S5PV210_GPIO_F2_NR,
+                        .label  = "GPF2",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPF3(0),
+                        .ngpio  = S5PV210_GPIO_F3_NR,
+                        .label  = "GPF3",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPG0(0),
+                        .ngpio  = S5PV210_GPIO_G0_NR,
+                        .label  = "GPG0",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPG1(0),
+                        .ngpio  = S5PV210_GPIO_G1_NR,
+                        .label  = "GPG1",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPG2(0),
+                        .ngpio  = S5PV210_GPIO_G2_NR,
+                        .label  = "GPG2",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPG3(0),
+                        .ngpio  = S5PV210_GPIO_G3_NR,
+                        .label  = "GPG3",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPI(0),
+                        .ngpio  = S5PV210_GPIO_I_NR,
+                        .label  = "GPI",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPJ0(0),
+                        .ngpio  = S5PV210_GPIO_J0_NR,
+                        .label  = "GPJ0",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPJ1(0),
+                        .ngpio  = S5PV210_GPIO_J1_NR,
+                        .label  = "GPJ1",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPJ2(0),
+                        .ngpio  = S5PV210_GPIO_J2_NR,
+                        .label  = "GPJ2",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPJ3(0),
+                        .ngpio  = S5PV210_GPIO_J3_NR,
+                        .label  = "GPJ3",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV210_GPJ4(0),
+                        .ngpio  = S5PV210_GPIO_J4_NR,
+                        .label  = "GPJ4",
+                },
+        }, {
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PV210_MP01(0),
+                        .ngpio  = S5PV210_GPIO_MP01_NR,
+                        .label  = "MP01",
+                },
+        }, {
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PV210_MP02(0),
+                        .ngpio  = S5PV210_GPIO_MP02_NR,
+                        .label  = "MP02",
+                },
+        }, {
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PV210_MP03(0),
+                        .ngpio  = S5PV210_GPIO_MP03_NR,
+                        .label  = "MP03",
+                },
+        }, {
+                .base   = (S5P_VA_GPIO + 0xC00),
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PV210_GPH0(0),
+                        .ngpio  = S5PV210_GPIO_H0_NR,
+                        .label  = "GPH0",
+                },
+        }, {
+                .base   = (S5P_VA_GPIO + 0xC20),
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PV210_GPH1(0),
+                        .ngpio  = S5PV210_GPIO_H1_NR,
+                        .label  = "GPH1",
+                },
+        }, {
+                .base   = (S5P_VA_GPIO + 0xC40),
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PV210_GPH2(0),
+                        .ngpio  = S5PV210_GPIO_H2_NR,
+                        .label  = "GPH2",
+                },
+        }, {
+                .base   = (S5P_VA_GPIO + 0xC60),
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PV210_GPH3(0),
+                        .ngpio  = S5PV210_GPIO_H3_NR,
+                        .label  = "GPH3",
+                },
+        },
+};
+
+static __init int s5pv210_gpiolib_init(void)
+{
+        struct s3c_gpio_chip *chip = s5pv210_gpio_4bit;
+        int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit);
+        int i = 0;
+
+        for (i = 0; i < nr_chips; i++, chip++) {
+                if (chip->config == NULL)
+                        chip->config = &gpio_cfg;
+                if (chip->base == NULL)
+                        chip->base = S5PV210_BANK_BASE(i);
+        }
+
+        samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips);
+
+        return 0;
+}
+core_initcall(s5pv210_gpiolib_init);
diff --git a/arch/arm/mach-s5pv210/include/mach/dma.h b/arch/arm/mach-s5pv210/include/mach/dma.h
new file mode 100644
index 000000000000..81209eb1409b
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/dma.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __MACH_DMA_H
+#define __MACH_DMA_H
+
+/* This platform uses the common S3C DMA API driver for PL330 */
+#include <plat/s3c-dma-pl330.h>
+
+#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h
index 533b020e21e9..d6461ba2b71d 100644
--- a/arch/arm/mach-s5pv210/include/mach/gpio.h
+++ b/arch/arm/mach-s5pv210/include/mach/gpio.h
@@ -18,6 +18,8 @@
 #define gpio_cansleep   __gpio_cansleep
 #define gpio_to_irq     __gpio_to_irq
 
+/* Practically, GPIO banks upto MP03 are the configurable gpio banks */
+
 /* GPIO bank sizes */
 #define S5PV210_GPIO_A0_NR      (8)
 #define S5PV210_GPIO_A1_NR      (4)
@@ -47,6 +49,10 @@
 #define S5PV210_GPIO_J3_NR      (8)
 #define S5PV210_GPIO_J4_NR      (5)
 
+#define S5PV210_GPIO_MP01_NR    (8)
+#define S5PV210_GPIO_MP02_NR    (4)
+#define S5PV210_GPIO_MP03_NR    (8)
+
 /* GPIO bank numbers */
 
 /* CONFIG_S3C_GPIO_SPACE allows the user to select extra
@@ -85,6 +91,9 @@ enum s5p_gpio_number {
         S5PV210_GPIO_J2_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_J1),
         S5PV210_GPIO_J3_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_J2),
         S5PV210_GPIO_J4_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_J3),
+        S5PV210_GPIO_MP01_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J4),
+        S5PV210_GPIO_MP02_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01),
+        S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02),
 };
 
 /* S5PV210 GPIO number definitions */
@@ -115,13 +124,16 @@ enum s5p_gpio_number {
 #define S5PV210_GPJ2(_nr)       (S5PV210_GPIO_J2_START + (_nr))
 #define S5PV210_GPJ3(_nr)       (S5PV210_GPIO_J3_START + (_nr))
 #define S5PV210_GPJ4(_nr)       (S5PV210_GPIO_J4_START + (_nr))
+#define S5PV210_MP01(_nr)       (S5PV210_GPIO_MP01_START + (_nr))
+#define S5PV210_MP02(_nr)       (S5PV210_GPIO_MP02_START + (_nr))
+#define S5PV210_MP03(_nr)       (S5PV210_GPIO_MP03_START + (_nr))
 
 /* the end of the S5PV210 specific gpios */
-#define S5PV210_GPIO_END        (S5PV210_GPJ4(S5PV210_GPIO_J4_NR) + 1)
+#define S5PV210_GPIO_END        (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + 1)
 #define S3C_GPIO_END            S5PV210_GPIO_END
 
-/* define the number of gpios we need to the one after the GPJ4() range */
-#define ARCH_NR_GPIOS           (S5PV210_GPJ4(S5PV210_GPIO_J4_NR) +     \
+/* define the number of gpios we need to the one after the MP03() range */
+#define ARCH_NR_GPIOS           (S5PV210_MP03(S5PV210_GPIO_MP03_NR) +   \
                                  CONFIG_SAMSUNG_GPIO_EXTRA + 1)
 
 #include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index bcd2e82c2e2b..5adcb9f26e44 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -43,6 +43,10 @@
 
 #define S5PV210_PA_SROMC        (0xE8000000)
 
+#define S5PV210_PA_MDMA         0xFA200000
+#define S5PV210_PA_PDMA0        0xE0900000
+#define S5PV210_PA_PDMA1        0xE0A00000
+
 #define S5PV210_PA_VIC0         (0xF2000000)
 #define S5P_PA_VIC0             S5PV210_PA_VIC0
 
diff --git a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h b/arch/arm/mach-s5pv210/include/mach/pwm-clock.h
index 69027fea987a..f8a9f1b330e0 100644
--- a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/pwm-clock.h
@@ -1,13 +1,14 @@
 /* linux/arch/arm/mach-s5pv210/include/mach/pwm-clock.h
  *
+ * Copyright (c) 2009 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Copyright 2008 Openmoko, Inc.
  * Copyright 2008 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *      http://armlinux.simtec.co.uk/
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Based on arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
+ * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
  *
  * S5PV210 - pwm clock and timer support
  *
@@ -21,14 +22,14 @@
 
 /**
  * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @cfg: The timer TCFG1 register bits shifted down to 0.
+ * @tcfg: The timer TCFG1 register bits shifted down to 0.
  *
  * Return true if the given configuration from TCFG1 is a TCLK instead
  * any of the TDIV clocks.
  */
 static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
 {
-        return tcfg == S3C2410_TCFG1_MUX_TCLK;
+        return tcfg == S3C64XX_TCFG1_MUX_TCLK;
 }
 
 /**
@@ -40,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
  */
 static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
 {
-        return 1 << (1 + tcfg1);
+        return 1 << tcfg1;
 }
 
 /**
@@ -50,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
  */
 static inline unsigned int pwm_tdiv_has_div1(void)
 {
-        return 0;
+        return 1;
 }
 
 /**
@@ -61,9 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void)
  */
 static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
 {
-        return ilog2(div) - 1;
+        return ilog2(div);
 }
 
-#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK
+#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
 
 #endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 241c24a1c18f..45a1bc275f0a 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -869,9 +869,10 @@ void __init reserve_node_zero(pg_data_t *pgdat)
         if (machine_is_p720t())
                 res_size = 0x00014000;
 
-        /* H1940 and RX3715 need to reserve this for suspend */
+        /* H1940, RX3715 and RX1950 need to reserve this for suspend */
 
-        if (machine_is_h1940() || machine_is_rx3715()) {
+        if (machine_is_h1940() || machine_is_rx3715()
+                || machine_is_rx1950()) {
                 reserve_bootmem_node(pgdat, 0x30003000, 0x1000,
                                 BOOTMEM_DEFAULT);
                 reserve_bootmem_node(pgdat, 0x30081000, 0x1000,
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 6e93ef8f3d43..3ce8f010b3c6 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -9,6 +9,7 @@ config PLAT_S3C24XX
         select NO_IOPORT
         select ARCH_REQUIRE_GPIOLIB
         select S3C_DEVICE_NAND
+        select S3C_GPIO_CFG_S3C24XX
         help
           Base platform code for any Samsung S3C24XX device
 
@@ -44,6 +45,12 @@ config S3C2410_CLOCK
           Clock code for the S3C2410, and similar processors which
           is currently includes the S3C2410, S3C2440, S3C2442.
 
+config S3C2443_CLOCK
+        bool
+        help
+          Clock code for the S3C2443 and similar processors, which includes
+          the S3C2416 and S3C2450.
+
 config S3C24XX_DCLK
         bool
         help
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index c2237c41141f..44aea8868f89 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_PM)		+= pm.o
 obj-$(CONFIG_PM)                += irq-pm.o
 obj-$(CONFIG_PM)                += sleep.o
 obj-$(CONFIG_S3C2410_CLOCK)     += s3c2410-clock.o
+obj-$(CONFIG_S3C2443_CLOCK)     += s3c2443-clock.o
 obj-$(CONFIG_S3C2410_DMA)       += dma.o
 obj-$(CONFIG_S3C2410_IOTIMING)  += s3c2410-iotiming.o
 obj-$(CONFIG_S3C2412_IOTIMING)  += s3c2412-iotiming.o
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index 9e0e20ad2e46..7b44d0c592b5 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -42,6 +42,7 @@
 #include <plat/nand.h>
 
 #include <plat/common-smdk.h>
+#include <plat/gpio-cfg.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
 
@@ -185,10 +186,10 @@ void __init smdk_machine_init(void)
 {
         /* Configure the LEDs (even if we have no LED support)*/
 
-        s3c2410_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT);
 
         s3c2410_gpio_setpin(S3C2410_GPF(4), 1);
         s3c2410_gpio_setpin(S3C2410_GPF(5), 1);
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 9ca64df35bf6..76d0858c3cbb 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -49,6 +49,7 @@
 #include <plat/s3c2400.h>
 #include <plat/s3c2410.h>
 #include <plat/s3c2412.h>
+#include <plat/s3c2416.h>
 #include <plat/s3c244x.h>
 #include <plat/s3c2443.h>
 
@@ -57,6 +58,7 @@
 static const char name_s3c2400[]  = "S3C2400";
 static const char name_s3c2410[]  = "S3C2410";
 static const char name_s3c2412[]  = "S3C2412";
+static const char name_s3c2416[]  = "S3C2416/S3C2450";
 static const char name_s3c2440[]  = "S3C2440";
 static const char name_s3c2442[]  = "S3C2442";
 static const char name_s3c2442b[]  = "S3C2442B";
@@ -137,6 +139,15 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .init           = s3c2412_init,
                 .name           = name_s3c2412,
         },
+        {                       /* a strange version of the s3c2416 */
+                .idcode         = 0x32450003,
+                .idmask         = 0xffffffff,
+                .map_io         = s3c2416_map_io,
+                .init_clocks    = s3c2416_init_clocks,
+                .init_uarts     = s3c2416_init_uarts,
+                .init           = s3c2416_init,
+                .name           = name_s3c2416,
+        },
         {
                 .idcode         = 0x32443001,
                 .idmask         = 0xffffffff,
@@ -170,6 +181,16 @@ static struct map_desc s3c_iodesc[] __initdata = {
 
 static unsigned long s3c24xx_read_idcode_v5(void)
 {
+#if defined(CONFIG_CPU_S3C2416)
+        /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
+
+        u32 gs = __raw_readl(S3C24XX_GSTATUS1);
+
+        /* test for s3c2416 or similar device */
+        if ((gs >> 16) == 0x3245)
+                return gs;
+#endif
+
 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
         return __raw_readl(S3C2412_GSTATUS1);
 #else
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 9265f09bfa58..cd5b41d0b5a4 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -21,6 +21,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/string.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -149,10 +150,14 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
 {
         struct s3c2410fb_mach_info *npd;
 
-        npd = kmalloc(sizeof(*npd), GFP_KERNEL);
+        npd = kmemdup(pd, sizeof(*npd), GFP_KERNEL);
         if (npd) {
-                memcpy(npd, pd, sizeof(*npd));
                 s3c_device_lcd.dev.platform_data = npd;
+                npd->displays = kmemdup(pd->displays,
+                        sizeof(struct s3c2410fb_display) * npd->num_displays,
+                        GFP_KERNEL);
+                if (!npd->displays)
+                        printk(KERN_ERR "no memory for LCD display data\n");
         } else {
                 printk(KERN_ERR "no memory for LCD platform data\n");
         }
@@ -338,14 +343,6 @@ struct platform_device s3c_device_adc = {
         .resource         = s3c_adc_resource,
 };
 
-/* HWMON */
-
-struct platform_device s3c_device_hwmon = {
-        .name           = "s3c-hwmon",
-        .id             = -1,
-        .dev.parent     = &s3c_device_adc.dev,
-};
-
 /* SDI */
 
 static struct resource s3c_sdi_resource[] = {
@@ -371,7 +368,7 @@ struct platform_device s3c_device_sdi = {
 
 EXPORT_SYMBOL(s3c_device_sdi);
 
-void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
+void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
 {
         struct s3c24xx_mci_pdata *npd;
 
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 93827b3d4e84..6ad274e7593d 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -1104,7 +1104,7 @@ EXPORT_SYMBOL(s3c2410_dma_config);
  * devaddr:   physical address of the source
 */
 
-int s3c2410_dma_devconfig(int channel,
+int s3c2410_dma_devconfig(unsigned int channel,
                           enum s3c2410_dmasrc source,
                           unsigned long devaddr)
 {
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
index 5467470badfd..2f3d7c089dfa 100644
--- a/arch/arm/plat-s3c24xx/gpio.c
+++ b/arch/arm/plat-s3c24xx/gpio.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/gpio.c
  *
- * Copyright (c) 2004-2005 Simtec Electronics
+ * Copyright (c) 2004-2010 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *
  * S3C24XX GPIO support
@@ -20,12 +20,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 
-
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
+#include <linux/gpio.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -34,133 +34,46 @@
 
 #include <mach/regs-gpio.h>
 
-void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
-{
-        void __iomem *base = S3C24XX_GPIO_BASE(pin);
-        unsigned long mask;
-        unsigned long con;
-        unsigned long flags;
+#include <plat/gpio-core.h>
 
-        if (pin < S3C2410_GPIO_BANKB) {
-                mask = 1 << S3C2410_GPIO_OFFSET(pin);
-        } else {
-                mask = 3 << S3C2410_GPIO_OFFSET(pin)*2;
-        }
-
-        switch (function) {
-        case S3C2410_GPIO_LEAVE:
-                mask = 0;
-                function = 0;
-                break;
-
-        case S3C2410_GPIO_INPUT:
-        case S3C2410_GPIO_OUTPUT:
-        case S3C2410_GPIO_SFN2:
-        case S3C2410_GPIO_SFN3:
-                if (pin < S3C2410_GPIO_BANKB) {
-                        function -= 1;
-                        function &= 1;
-                        function <<= S3C2410_GPIO_OFFSET(pin);
-                } else {
-                        function &= 3;
-                        function <<= S3C2410_GPIO_OFFSET(pin)*2;
-                }
-        }
-
-        /* modify the specified register wwith IRQs off */
-
-        local_irq_save(flags);
-
-        con  = __raw_readl(base + 0x00);
-        con &= ~mask;
-        con |= function;
-
-        __raw_writel(con, base + 0x00);
-
-        local_irq_restore(flags);
-}
-
-EXPORT_SYMBOL(s3c2410_gpio_cfgpin);
-
-unsigned int s3c2410_gpio_getcfg(unsigned int pin)
-{
-        void __iomem *base = S3C24XX_GPIO_BASE(pin);
-        unsigned long val = __raw_readl(base);
-
-        if (pin < S3C2410_GPIO_BANKB) {
-                val >>= S3C2410_GPIO_OFFSET(pin);
-                val &= 1;
-                val += 1;
-        } else {
-                val >>= S3C2410_GPIO_OFFSET(pin)*2;
-                val &= 3;
-        }
-
-        return val | S3C2410_GPIO_INPUT;
-}
-
-EXPORT_SYMBOL(s3c2410_gpio_getcfg);
+/* gpiolib wrappers until these are totally eliminated */
 
 void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
 {
-        void __iomem *base = S3C24XX_GPIO_BASE(pin);
-        unsigned long offs = S3C2410_GPIO_OFFSET(pin);
-        unsigned long flags;
-        unsigned long up;
+        int ret;
 
-        if (pin < S3C2410_GPIO_BANKB)
-                return;
+        WARN_ON(to);    /* should be none of these left */
 
-        local_irq_save(flags);
-
-        up = __raw_readl(base + 0x08);
-        up &= ~(1L << offs);
-        up |= to << offs;
-        __raw_writel(up, base + 0x08);
+        if (!to) {
+                /* if pull is enabled, try first with up, and if that
+                 * fails, try using down */
 
-        local_irq_restore(flags);
+                ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP);
+                if (ret)
+                        s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN);
+        } else {
+                s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE);
+        }
 }
-
 EXPORT_SYMBOL(s3c2410_gpio_pullup);
 
-int s3c2410_gpio_getpull(unsigned int pin)
-{
-        void __iomem *base = S3C24XX_GPIO_BASE(pin);
-        unsigned long offs = S3C2410_GPIO_OFFSET(pin);
-
-        if (pin < S3C2410_GPIO_BANKB)
-                return -EINVAL;
-
-        return (__raw_readl(base + 0x08) & (1L << offs)) ? 1 : 0;
-}
-
-EXPORT_SYMBOL(s3c2410_gpio_getpull);
-
 void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
 {
-        void __iomem *base = S3C24XX_GPIO_BASE(pin);
-        unsigned long offs = S3C2410_GPIO_OFFSET(pin);
-        unsigned long flags;
-        unsigned long dat;
+        /* do this via gpiolib until all users removed */
 
-        local_irq_save(flags);
-
-        dat = __raw_readl(base + 0x04);
-        dat &= ~(1 << offs);
-        dat |= to << offs;
-        __raw_writel(dat, base + 0x04);
-
-        local_irq_restore(flags);
+        gpio_request(pin, "temporary");
+        gpio_set_value(pin, to);
+        gpio_free(pin);
 }
 
 EXPORT_SYMBOL(s3c2410_gpio_setpin);
 
 unsigned int s3c2410_gpio_getpin(unsigned int pin)
 {
-        void __iomem *base = S3C24XX_GPIO_BASE(pin);
-        unsigned long offs = S3C2410_GPIO_OFFSET(pin);
+        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+        unsigned long offs = pin - chip->chip.base;
 
-        return __raw_readl(base + 0x04) & (1<< offs);
+        return __raw_readl(chip->base + 0x04) & (1<< offs);
 }
 
 EXPORT_SYMBOL(s3c2410_gpio_getpin);
@@ -181,22 +94,3 @@ unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
 }
 
 EXPORT_SYMBOL(s3c2410_modify_misccr);
-
-int s3c2410_gpio_getirq(unsigned int pin)
-{
-        if (pin < S3C2410_GPF(0) || pin > S3C2410_GPG(15))
-                return -EINVAL; /* not valid interrupts */
-
-        if (pin < S3C2410_GPG(0) && pin > S3C2410_GPF(7))
-                return -EINVAL; /* not valid pin */
-
-        if (pin < S3C2410_GPF(4))
-                return (pin - S3C2410_GPF(0)) + IRQ_EINT0;
-
-        if (pin < S3C2410_GPG(0))
-                return (pin - S3C2410_GPF(4)) + IRQ_EINT4;
-
-        return (pin - S3C2410_GPG(0)) + IRQ_EINT8;
-}
-
-EXPORT_SYMBOL(s3c2410_gpio_getirq);
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 4f0f11a6a677..4c0896f2572d 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/gpiolib.c
  *
- * Copyright (c) 2008 Simtec Electronics
+ * Copyright (c) 2008-2010 Simtec Electronics
  *      http://armlinux.simtec.co.uk/
  *      Ben Dooks <ben@simtec.co.uk>
  *
@@ -21,6 +21,8 @@
 #include <linux/gpio.h>
 
 #include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <plat/pm.h>
@@ -77,10 +79,21 @@ static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
         return IRQ_EINT8 + offset;
 }
 
+static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
+        .set_config     = s3c_gpio_setcfg_s3c24xx_a,
+        .get_config     = s3c_gpio_getcfg_s3c24xx_a,
+};
+
+struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
+        .set_config     = s3c_gpio_setcfg_s3c24xx,
+        .get_config     = s3c_gpio_getcfg_s3c24xx,
+};
+
 struct s3c_gpio_chip s3c24xx_gpios[] = {
         [0] = {
                 .base   = S3C2410_GPACON,
                 .pm     = __gpio_pm(&s3c_gpio_pm_1bit),
+                .config = &s3c24xx_gpiocfg_banka,
                 .chip   = {
                         .base                   = S3C2410_GPA(0),
                         .owner                  = THIS_MODULE,
@@ -161,15 +174,58 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
                         .ngpio                  = 11,
                 },
         },
+                /* GPIOS for the S3C2443 and later devices. */
+        {
+                .base   = S3C2440_GPJCON,
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
+                .chip   = {
+                        .base                   = S3C2410_GPJ(0),
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOJ",
+                        .ngpio                  = 16,
+                },
+        }, {
+                .base   = S3C2443_GPKCON,
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
+                .chip   = {
+                        .base                   = S3C2410_GPK(0),
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOK",
+                        .ngpio                  = 16,
+                },
+        }, {
+                .base   = S3C2443_GPLCON,
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
+                .chip   = {
+                        .base                   = S3C2410_GPL(0),
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOL",
+                        .ngpio                  = 15,
+                },
+        }, {
+                .base   = S3C2443_GPMCON,
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
+                .chip   = {
+                        .base                   = S3C2410_GPM(0),
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOM",
+                        .ngpio                  = 2,
+                },
+        },
 };
 
+
 static __init int s3c24xx_gpiolib_init(void)
 {
         struct s3c_gpio_chip *chip = s3c24xx_gpios;
         int gpn;
 
-        for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++)
+        for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) {
+                if (!chip->config)
+                        chip->config = &s3c24xx_gpiocfg_default;
+
                 s3c_gpiolib_add(chip);
+        }
 
         return 0;
 }
diff --git a/arch/arm/plat-s3c24xx/include/plat/pll.h b/arch/arm/plat-s3c24xx/include/plat/pll.h
index 7ea8bffa7a9c..005729a1077a 100644
--- a/arch/arm/plat-s3c24xx/include/plat/pll.h
+++ b/arch/arm/plat-s3c24xx/include/plat/pll.h
@@ -35,3 +35,28 @@ s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
 
         return (unsigned int)fvco;
 }
+
+#define S3C2416_PLL_M_SHIFT     (14)
+#define S3C2416_PLL_P_SHIFT     (5)
+#define S3C2416_PLL_S_MASK      (7)
+#define S3C2416_PLL_M_MASK      ((1 << 10) - 1)
+#define S3C2416_PLL_P_MASK      (63)
+
+static inline unsigned int
+s3c2416_get_pll(unsigned int pllval, unsigned int baseclk)
+{
+        unsigned int m, p, s;
+        uint64_t fvco;
+
+        m = pllval >> S3C2416_PLL_M_SHIFT;
+        p = pllval >> S3C2416_PLL_P_SHIFT;
+
+        s = pllval & S3C2416_PLL_S_MASK;
+        m &= S3C2416_PLL_M_MASK;
+        p &= S3C2416_PLL_P_MASK;
+
+        fvco = (uint64_t)baseclk * m;
+        do_div(fvco, (p << s));
+
+        return (unsigned int)fvco;
+}
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2416.h b/arch/arm/plat-s3c24xx/include/plat/s3c2416.h
new file mode 100644
index 000000000000..dc3c0907d221
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2416.h
@@ -0,0 +1,31 @@
+/* linux/include/asm-arm/plat-s3c24xx/s3c2443.h
+ *
+ * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>
+ *
+ * Header file for s3c2416 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifdef CONFIG_CPU_S3C2416
+
+struct s3c2410_uartcfg;
+
+extern  int s3c2416_init(void);
+
+extern void s3c2416_map_io(void);
+
+extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+
+extern void s3c2416_init_clocks(int xtal);
+
+extern  int s3c2416_baseclk_add(void);
+
+#else
+#define s3c2416_init_clocks NULL
+#define s3c2416_init_uarts NULL
+#define s3c2416_map_io NULL
+#define s3c2416_init NULL
+#endif
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
index 815b107ed890..a19715feb798 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
@@ -30,3 +30,22 @@ extern  int s3c2443_baseclk_add(void);
 #define s3c2443_map_io NULL
 #define s3c2443_init NULL
 #endif
+
+/* common code used by s3c2443 and others.
+ * note, not to be used outside of arch/arm/mach-s3c* */
+
+struct clk;     /* some files don't need clk.h otherwise */
+
+typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
+typedef unsigned int (*fdiv_fn)(unsigned long clkcon0);
+
+extern void s3c2443_common_setup_clocks(pll_fn get_mpll, fdiv_fn fdiv);
+extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, fdiv_fn fdiv);
+
+extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
+extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
+extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
+
+extern struct clksrc_clk clk_epllref;
+extern struct clksrc_clk clk_esysclk;
+extern struct clksrc_clk clk_msysclk;
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 3620dd299095..60627e63a254 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -43,6 +43,7 @@
 
 #include <asm/mach/time.h>
 
+#include <plat/gpio-cfg.h>
 #include <plat/pm.h>
 
 #define PFX "s3c24xx-pm: "
@@ -90,22 +91,22 @@ static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
 {
         unsigned long irqstate;
         unsigned long pinstate;
-        int irq = s3c2410_gpio_getirq(pin);
+        int irq = gpio_to_irq(pin);
 
         if (irqoffs < 4)
                 irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
         else
                 irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
 
-        pinstate = s3c2410_gpio_getcfg(pin);
+        pinstate = s3c_gpio_getcfg(pin);
 
         if (!irqstate) {
                 if (pinstate == S3C2410_GPIO_IRQ)
-                        S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
+                        S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin);
         } else {
                 if (pinstate == S3C2410_GPIO_IRQ) {
                         S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
-                        s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
+                        s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
                 }
         }
 }
diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/plat-s3c24xx/s3c2410-clock.c
index b61bdb793734..9ecc5d913679 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c
@@ -87,7 +87,7 @@ static int s3c2410_upll_enable(struct clk *clk, int enable)
 
 /* standard clock definitions */
 
-static struct clk init_clocks_disable[] = {
+static struct clk init_clocks_off[] = {
         {
                 .name           = "nand",
                 .id             = -1,
@@ -249,17 +249,8 @@ int __init s3c2410_baseclk_add(void)
 
         /* install (and disable) the clocks we do not need immediately */
 
-        clkp = init_clocks_disable;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
-
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-
-                s3c2410_clkcon_enable(clkp, 0);
-        }
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
         /* show the clock-slow value */
 
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
new file mode 100644
index 000000000000..461f070eb62d
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -0,0 +1,472 @@
+/* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c
+ *
+ * Copyright (c) 2007, 2010 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2443 Clock control suport - common code
+ */
+
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/regs-s3c2443-clock.h>
+
+#include <plat/s3c2443.h>
+#include <plat/clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/cpu.h>
+
+#include <plat/cpu-freq.h>
+
+
+static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
+{
+        u32 ctrlbit = clk->ctrlbit;
+        u32 con = __raw_readl(reg);
+
+        if (enable)
+                con |= ctrlbit;
+        else
+                con &= ~ctrlbit;
+
+        __raw_writel(con, reg);
+        return 0;
+}
+
+int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
+{
+        return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
+}
+
+int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
+{
+        return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
+}
+
+int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
+{
+        return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
+}
+
+/* mpllref is a direct descendant of clk_xtal by default, but it is not
+ * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
+ * such directly equating the two source clocks is impossible.
+ */
+struct clk clk_mpllref = {
+        .name           = "mpllref",
+        .parent         = &clk_xtal,
+        .id             = -1,
+};
+
+static struct clk *clk_epllref_sources[] = {
+        [0] = &clk_mpllref,
+        [1] = &clk_mpllref,
+        [2] = &clk_xtal,
+        [3] = &clk_ext,
+};
+
+struct clksrc_clk clk_epllref = {
+        .clk    = {
+                .name           = "epllref",
+                .id             = -1,
+        },
+        .sources = &(struct clksrc_sources) {
+                .sources = clk_epllref_sources,
+                .nr_sources = ARRAY_SIZE(clk_epllref_sources),
+        },
+        .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
+};
+
+/* esysclk
+ *
+ * this is sourced from either the EPLL or the EPLLref clock
+*/
+
+static struct clk *clk_sysclk_sources[] = {
+        [0] = &clk_epllref.clk,
+        [1] = &clk_epll,
+};
+
+struct clksrc_clk clk_esysclk = {
+        .clk    = {
+                .name           = "esysclk",
+                .parent         = &clk_epll,
+                .id             = -1,
+        },
+        .sources = &(struct clksrc_sources) {
+                .sources = clk_sysclk_sources,
+                .nr_sources = ARRAY_SIZE(clk_sysclk_sources),
+        },
+        .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
+};
+
+static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long div = __raw_readl(S3C2443_CLKDIV0);
+
+        div  &= S3C2443_CLKDIV0_EXTDIV_MASK;
+        div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1);       /* x2 */
+
+        return parent_rate / (div + 1);
+}
+
+static struct clk clk_mdivclk = {
+        .name           = "mdivclk",
+        .parent         = &clk_mpllref,
+        .id             = -1,
+        .ops            = &(struct clk_ops) {
+                .get_rate       = s3c2443_getrate_mdivclk,
+        },
+};
+
+static struct clk *clk_msysclk_sources[] = {
+        [0] = &clk_mpllref,
+        [1] = &clk_mpll,
+        [2] = &clk_mdivclk,
+        [3] = &clk_mpllref,
+};
+
+struct clksrc_clk clk_msysclk = {
+        .clk    = {
+                .name           = "msysclk",
+                .parent         = &clk_xtal,
+                .id             = -1,
+        },
+        .sources = &(struct clksrc_sources) {
+                .sources = clk_msysclk_sources,
+                .nr_sources = ARRAY_SIZE(clk_msysclk_sources),
+        },
+        .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
+};
+
+/* prediv
+ *
+ * this divides the msysclk down to pass to h/p/etc.
+ */
+
+static unsigned long s3c2443_prediv_getrate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
+
+        clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
+        clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
+
+        return rate / (clkdiv0 + 1);
+}
+
+static struct clk clk_prediv = {
+        .name           = "prediv",
+        .id             = -1,
+        .parent         = &clk_msysclk.clk,
+        .ops            = &(struct clk_ops) {
+                .get_rate       = s3c2443_prediv_getrate,
+        },
+};
+
+/* usbhost
+ *
+ * usb host bus-clock, usually 48MHz to provide USB bus clock timing
+*/
+
+static struct clksrc_clk clk_usb_bus_host = {
+        .clk    = {
+                .name           = "usb-bus-host-parent",
+                .id             = -1,
+                .parent         = &clk_esysclk.clk,
+                .ctrlbit        = S3C2443_SCLKCON_USBHOST,
+                .enable         = s3c2443_clkcon_enable_s,
+        },
+        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
+};
+
+/* common clksrc clocks */
+
+static struct clksrc_clk clksrc_clks[] = {
+        {
+                /* ART baud-rate clock sourced from esysclk via a divisor */
+                .clk    = {
+                        .name           = "uartclk",
+                        .id             = -1,
+                        .parent         = &clk_esysclk.clk,
+                },
+                .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
+        }, {
+                /* camera interface bus-clock, divided down from esysclk */
+                .clk    = {
+                        .name           = "camif-upll", /* same as 2440 name */
+                        .id             = -1,
+                        .parent         = &clk_esysclk.clk,
+                        .ctrlbit        = S3C2443_SCLKCON_CAMCLK,
+                        .enable         = s3c2443_clkcon_enable_s,
+                },
+                .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
+        }, {
+                .clk    = {
+                        .name           = "display-if",
+                        .id             = -1,
+                        .parent         = &clk_esysclk.clk,
+                        .ctrlbit        = S3C2443_SCLKCON_DISPCLK,
+                        .enable         = s3c2443_clkcon_enable_s,
+                },
+                .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
+        },
+};
+
+
+static struct clk init_clocks_off[] = {
+        {
+                .name           = "adc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_ADC,
+        }, {
+                .name           = "i2c",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_IIC,
+        }
+};
+
+static struct clk init_clocks[] = {
+        {
+                .name           = "dma",
+                .id             = 0,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_DMA0,
+        }, {
+                .name           = "dma",
+                .id             = 1,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_DMA1,
+        }, {
+                .name           = "dma",
+                .id             = 2,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_DMA2,
+        }, {
+                .name           = "dma",
+                .id             = 3,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_DMA3,
+        }, {
+                .name           = "dma",
+                .id             = 4,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_DMA4,
+        }, {
+                .name           = "dma",
+                .id             = 5,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_DMA5,
+        }, {
+                .name           = "hsmmc",
+                .id             = 0,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_HSMMC,
+        }, {
+                .name           = "gpio",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_GPIO,
+        }, {
+                .name           = "usb-host",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_USBH,
+        }, {
+                .name           = "usb-device",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_USBD,
+        }, {
+                .name           = "lcd",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_LCDC,
+
+        }, {
+                .name           = "timers",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_PWMT,
+        }, {
+                .name           = "cfc",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_CFC,
+        }, {
+                .name           = "ssmc",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_SSMC,
+        }, {
+                .name           = "uart",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_UART0,
+        }, {
+                .name           = "uart",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_UART1,
+        }, {
+                .name           = "uart",
+                .id             = 2,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_UART2,
+        }, {
+                .name           = "uart",
+                .id             = 3,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_UART3,
+        }, {
+                .name           = "rtc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_RTC,
+        }, {
+                .name           = "watchdog",
+                .id             = -1,
+                .parent         = &clk_p,
+                .ctrlbit        = S3C2443_PCLKCON_WDT,
+        }, {
+                .name           = "ac97",
+                .id             = -1,
+                .parent         = &clk_p,
+                .ctrlbit        = S3C2443_PCLKCON_AC97,
+        }, {
+                .name           = "nand",
+                .id             = -1,
+                .parent         = &clk_h,
+        }, {
+                .name           = "usb-bus-host",
+                .id             = -1,
+                .parent         = &clk_usb_bus_host.clk,
+        }
+};
+
+static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
+{
+        clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
+
+        return clkcon0 + 1;
+}
+
+/* EPLLCON compatible enough to get on/off information */
+
+void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll,
+                                                   fdiv_fn get_fdiv)
+{
+        unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
+        unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
+        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
+        struct clk *xtal_clk;
+        unsigned long xtal;
+        unsigned long pll;
+        unsigned long fclk;
+        unsigned long hclk;
+        unsigned long pclk;
+        int ptr;
+
+        xtal_clk = clk_get(NULL, "xtal");
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+
+        pll = get_mpll(mpllcon, xtal);
+        clk_msysclk.clk.rate = pll;
+
+        fclk = pll / get_fdiv(clkdiv0);
+        hclk = s3c2443_prediv_getrate(&clk_prediv);
+        hclk /= s3c2443_get_hdiv(clkdiv0);
+        pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
+
+        s3c24xx_setup_clocks(fclk, hclk, pclk);
+
+        printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
+               (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
+               print_mhz(pll), print_mhz(fclk),
+               print_mhz(hclk), print_mhz(pclk));
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
+                s3c_set_clksrc(&clksrc_clks[ptr], true);
+
+        /* ensure usb bus clock is within correct rate of 48MHz */
+
+        if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
+                printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
+                clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
+        }
+
+        printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
+               (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
+               print_mhz(clk_get_rate(&clk_epll)),
+               print_mhz(clk_get_rate(&clk_usb_bus)));
+}
+
+static struct clk *clks[] __initdata = {
+        &clk_prediv,
+        &clk_mpllref,
+        &clk_mdivclk,
+        &clk_ext,
+        &clk_epll,
+        &clk_usb_bus,
+};
+
+static struct clksrc_clk *clksrcs[] __initdata = {
+        &clk_usb_bus_host,
+        &clk_epllref,
+        &clk_esysclk,
+        &clk_msysclk,
+};
+
+void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
+                                       fdiv_fn get_fdiv)
+{
+        int ptr;
+
+        /* s3c2443 parents h and p clocks from prediv */
+        clk_h.parent = &clk_prediv;
+        clk_p.parent = &clk_prediv;
+
+        clk_usb_bus.parent = &clk_usb_bus_host.clk;
+        clk_epll.parent = &clk_epllref.clk;
+
+        s3c24xx_register_baseclocks(xtal);
+        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
+                s3c_register_clksrc(clksrcs[ptr], 1);
+
+        s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
+        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+
+        /* See s3c2443/etc notes on disabling clocks at init time */
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+
+        s3c2443_common_setup_clocks(get_mpll, get_fdiv);
+}
diff --git a/arch/arm/plat-s3c24xx/setup-i2c.c b/arch/arm/plat-s3c24xx/setup-i2c.c
index 71a6accf114e..9e90a7cbd1d6 100644
--- a/arch/arm/plat-s3c24xx/setup-i2c.c
+++ b/arch/arm/plat-s3c24xx/setup-i2c.c
@@ -15,12 +15,13 @@
 
 struct platform_device;
 
+#include <plat/gpio-cfg.h>
 #include <plat/iic.h>
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
-        s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA);
-        s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL);
+        s3c_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA);
+        s3c_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL);
 }
diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
index da7a61728c18..9793544a6ace 100644
--- a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
+++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
@@ -21,16 +21,16 @@ void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
                                           int enable)
 {
         if (enable) {
-                s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0);
-                s3c2410_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0);
-                s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0);
+                s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0);
+                s3c_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0);
+                s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0);
                 s3c2410_gpio_pullup(S3C2410_GPE(11), 0);
                 s3c2410_gpio_pullup(S3C2410_GPE(13), 0);
         } else {
-                s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT);
-                s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT);
-                s3c2410_gpio_pullup(S3C2410_GPE(11), 1);
-                s3c2410_gpio_pullup(S3C2410_GPE(12), 1);
-                s3c2410_gpio_pullup(S3C2410_GPE(13), 1);
+                s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT);
+                s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT);
+                s3c_gpio_cfgpull(S3C2410_GPE(11), S3C_GPIO_PULL_NONE);
+                s3c_gpio_cfgpull(S3C2410_GPE(12), S3C_GPIO_PULL_NONE);
+                s3c_gpio_cfgpull(S3C2410_GPE(13), S3C_GPIO_PULL_NONE);
         }
 }
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
index 89fcf5308cf6..db9e9e477ec1 100644
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
+++ b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
@@ -23,16 +23,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
 
         printk(KERN_INFO "%s(%d)\n", __func__, enable);
         if (enable) {
-                s3c2410_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1);
-                s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1);
-                s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1);
+                s3c_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1);
+                s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1);
+                s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1);
                 s3c2410_gpio_pullup(S3C2410_GPD(10), 0);
                 s3c2410_gpio_pullup(S3C2410_GPD(9), 0);
         } else {
-                s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT);
-                s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT);
-                s3c2410_gpio_pullup(S3C2410_GPD(10), 1);
-                s3c2410_gpio_pullup(S3C2410_GPD(9), 1);
-                s3c2410_gpio_pullup(S3C2410_GPD(8), 1);
+                s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT);
+                s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT);
+                s3c_gpio_cfgpull(S3C2410_GPD(10), S3C_GPIO_PULL_NONE);
+                s3c_gpio_cfgpull(S3C2410_GPD(9), S3C_GPIO_PULL_NONE);
+                s3c_gpio_cfgpull(S3C2410_GPD(8), S3C_GPIO_PULL_NONE);
         }
 }
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
index 86b9edc67413..8ea663a438bb 100644
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
+++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
@@ -21,16 +21,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
                                        int enable)
 {
         if (enable) {
-                s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1);
-                s3c2410_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1);
-                s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1);
+                s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1);
+                s3c_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1);
+                s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1);
                 s3c2410_gpio_pullup(S3C2410_GPG(5), 0);
                 s3c2410_gpio_pullup(S3C2410_GPG(6), 0);
         } else {
-                s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT);
-                s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT);
-                s3c2410_gpio_pullup(S3C2410_GPG(5), 1);
-                s3c2410_gpio_pullup(S3C2410_GPG(6), 1);
-                s3c2410_gpio_pullup(S3C2410_GPG(7), 1);
+                s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT);
+                s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT);
+                s3c_gpio_cfgpull(S3C2410_GPG(5), S3C_GPIO_PULL_NONE);
+                s3c_gpio_cfgpull(S3C2410_GPG(6), S3C_GPIO_PULL_NONE);
+                s3c_gpio_cfgpull(S3C2410_GPG(7), S3C_GPIO_PULL_NONE);
         }
 }
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index aa96e335073b..a8bfabf4b6bc 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -33,6 +33,11 @@ struct clk clk_ext_xtal_mux = {
         .id             = -1,
 };
 
+struct clk clk_xusbxti = {
+        .name           = "xusbxti",
+        .id             = -1,
+};
+
 static struct clk s5p_clk_27m = {
         .name           = "clk_27m",
         .id             = -1,
@@ -69,6 +74,13 @@ struct clk clk_fout_epll = {
         .ctrlbit        = (1 << 31),
 };
 
+/* VPLL clock output */
+struct clk clk_fout_vpll = {
+        .name           = "fout_vpll",
+        .id             = -1,
+        .ctrlbit        = (1 << 31),
+};
+
 /* ARM clock */
 struct clk clk_arm = {
         .name           = "armclk",
@@ -133,6 +145,7 @@ static struct clk *s5p_clks[] __initdata = {
         &clk_fout_apll,
         &clk_fout_mpll,
         &clk_fout_epll,
+        &clk_fout_vpll,
         &clk_arm,
         &clk_vpll,
 };
diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h
index 42e757f2e40c..9ff3d718be39 100644
--- a/arch/arm/plat-s5p/include/plat/irqs.h
+++ b/arch/arm/plat-s5p/include/plat/irqs.h
@@ -79,7 +79,7 @@
 #define S5P_IRQ_VIC2(x)         (S5P_VIC2_BASE + (x))
 #define S5P_IRQ_VIC3(x)         (S5P_VIC3_BASE + (x))
 
-#define S5P_TIMER_IRQ(x)        S5P_IRQ(11 + (x))
+#define S5P_TIMER_IRQ(x)        (11 + (x))
 
 #define IRQ_TIMER0              S5P_TIMER_IRQ(0)
 #define IRQ_TIMER1              S5P_TIMER_IRQ(1)
diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h
index 56fb8b414d41..aa0447a18903 100644
--- a/arch/arm/plat-s5p/include/plat/s5p-clock.h
+++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h
@@ -23,10 +23,12 @@
 #define clk_fin_vpll clk_ext_xtal_mux
 
 extern struct clk clk_ext_xtal_mux;
+extern struct clk clk_xusbxti;
 extern struct clk clk_48m;
 extern struct clk clk_fout_apll;
 extern struct clk clk_fout_mpll;
 extern struct clk clk_fout_epll;
+extern struct clk clk_fout_vpll;
 extern struct clk clk_arm;
 extern struct clk clk_vpll;
 
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index d552c65fa1b0..5349d2181bd2 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -160,6 +160,11 @@ config S3C_DEV_HSMMC2
         help
           Compile in platform device definitions for HSMMC channel 2
 
+config S3C_DEV_HWMON
+        bool
+        help
+            Compile in platform device definitions for HWMON
+
 config S3C_DEV_I2C1
         bool
         help
@@ -198,6 +203,12 @@ config S3C_DMA
         help
           Internal configuration for S3C DMA core
 
+config S3C_PL330_DMA
+        bool
+        select PL330
+        help
+          S3C DMA API Driver for PL330 DMAC.
+
 comment "Power management"
 
 config SAMSUNG_PM_DEBUG
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 22c89d08f6e5..ca6036745edc 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_S3C_ADC)	+= adc.o
 obj-$(CONFIG_S3C_DEV_HSMMC)     += dev-hsmmc.o
 obj-$(CONFIG_S3C_DEV_HSMMC1)    += dev-hsmmc1.o
 obj-$(CONFIG_S3C_DEV_HSMMC2)    += dev-hsmmc2.o
+obj-$(CONFIG_S3C_DEV_HWMON)     += dev-hwmon.o
 obj-y                           += dev-i2c0.o
 obj-$(CONFIG_S3C_DEV_I2C1)      += dev-i2c1.o
 obj-$(CONFIG_S3C_DEV_FB)        += dev-fb.o
@@ -45,6 +46,8 @@ obj-$(CONFIG_S3C_DEV_NAND)	+= dev-nand.o
 
 obj-$(CONFIG_S3C_DMA)           += dma.o
 
+obj-$(CONFIG_S3C_PL330_DMA)     += s3c-pl330.o
+
 # PM support
 
 obj-$(CONFIG_PM)                += pm.o
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 1b25c9d8c403..8bf79f3efdfb 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -376,6 +376,21 @@ void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
         }
 }
 
+/**
+ * s3c_disable_clocks() - disable an array of clocks
+ * @clkp: Pointer to the first clock in the array.
+ * @nr_clks: Number of clocks to register.
+ *
+ * for internal use only at initialisation time. disable the clocks in the
+ * @clkp array.
+ */
+
+void __init s3c_disable_clocks(struct clk *clkp, int nr_clks)
+{
+        for (; nr_clks > 0; nr_clks--, clkp++)
+                (clkp->enable)(clkp, 0);
+}
+
 /* initalise all the clocks */
 
 int __init s3c24xx_register_baseclocks(unsigned long xtal)
diff --git a/arch/arm/plat-samsung/dev-fb.c b/arch/arm/plat-samsung/dev-fb.c
index 002a15f313f3..bf60204c6297 100644
--- a/arch/arm/plat-samsung/dev-fb.c
+++ b/arch/arm/plat-samsung/dev-fb.c
@@ -19,7 +19,6 @@
 
 #include <mach/irqs.h>
 #include <mach/map.h>
-#include <mach/regs-fb.h>
 
 #include <plat/fb.h>
 #include <plat/devs.h>
diff --git a/arch/arm/plat-samsung/dev-hwmon.c b/arch/arm/plat-samsung/dev-hwmon.c
new file mode 100644
index 000000000000..b3ffb9587250
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-hwmon.c
@@ -0,0 +1,42 @@
+/* linux/arch/arm/plat-samsung/dev-hwmon.c
+ *
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Adapted for HWMON by Maurus Cuelenaere
+ *
+ * Samsung series device definition for HWMON
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <plat/devs.h>
+#include <plat/hwmon.h>
+
+struct platform_device s3c_device_hwmon = {
+        .name           = "s3c-hwmon",
+        .id             = -1,
+        .dev.parent     = &s3c_device_adc.dev,
+};
+
+void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
+{
+        struct s3c_hwmon_pdata *npd;
+
+        if (!pd) {
+                printk(KERN_ERR "%s: no platform data\n", __func__);
+                return;
+        }
+
+        npd = kmemdup(pd, sizeof(struct s3c_hwmon_pdata), GFP_KERNEL);
+        if (!npd)
+                printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+
+        s3c_device_hwmon.dev.platform_data = npd;
+}
diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c
index 44a84e896546..a76eef533392 100644
--- a/arch/arm/plat-samsung/gpio-config.c
+++ b/arch/arm/plat-samsung/gpio-config.c
@@ -1,7 +1,7 @@
 /* linux/arch/arm/plat-s3c/gpio-config.c
  *
  * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
+ * Copyright 2008-2010 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *      http://armlinux.simtec.co.uk/
  *
@@ -33,14 +33,34 @@ int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
 
         offset = pin - chip->chip.base;
 
-        local_irq_save(flags);
+        s3c_gpio_lock(chip, flags);
         ret = s3c_gpio_do_setcfg(chip, offset, config);
-        local_irq_restore(flags);
+        s3c_gpio_unlock(chip, flags);
 
         return ret;
 }
 EXPORT_SYMBOL(s3c_gpio_cfgpin);
 
+unsigned s3c_gpio_getcfg(unsigned int pin)
+{
+        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+        unsigned long flags;
+        unsigned ret = 0;
+        int offset;
+
+        if (chip) {
+                offset = pin - chip->chip.base;
+
+                s3c_gpio_lock(chip, flags);
+                ret = s3c_gpio_do_getcfg(chip, offset);
+                s3c_gpio_unlock(chip, flags);
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL(s3c_gpio_getcfg);
+
+
 int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
 {
         struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
@@ -52,17 +72,17 @@ int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
 
         offset = pin - chip->chip.base;
 
-        local_irq_save(flags);
+        s3c_gpio_lock(chip, flags);
         ret = s3c_gpio_do_setpull(chip, offset, pull);
-        local_irq_restore(flags);
+        s3c_gpio_unlock(chip, flags);
 
         return ret;
 }
 EXPORT_SYMBOL(s3c_gpio_setpull);
 
 #ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
-int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip,
-                                  unsigned int off, unsigned int cfg)
+int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
+                              unsigned int off, unsigned int cfg)
 {
         void __iomem *reg = chip->base;
         unsigned int shift = off;
@@ -87,6 +107,19 @@ int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip,
         return 0;
 }
 
+unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
+                                   unsigned int off)
+{
+        u32 con;
+
+        con = __raw_readl(chip->base);
+        con >>= off;
+        con &= 1;
+        con++;
+
+        return S3C_GPIO_SFN(con);
+}
+
 int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
                             unsigned int off, unsigned int cfg)
 {
@@ -109,6 +142,19 @@ int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
 
         return 0;
 }
+
+unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,
+                                     unsigned int off)
+{
+        u32 con;
+
+        con = __raw_readl(chip->base);
+        con >>= off * 2;
+        con &= 3;
+
+        /* this conversion works for IN and OUT as well as special mode */
+        return S3C_GPIO_SPECIAL(con);
+}
 #endif
 
 #ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
@@ -134,6 +180,25 @@ int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
 
         return 0;
 }
+
+unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
+                                      unsigned int off)
+{
+        void __iomem *reg = chip->base;
+        unsigned int shift = (off & 7) * 4;
+        u32 con;
+
+        if (off < 8 && chip->chip.ngpio > 8)
+                reg -= 4;
+
+        con = __raw_readl(reg);
+        con >>= shift;
+        con &= 0xf;
+
+        /* this conversion works for IN and OUT as well as special mode */
+        return S3C_GPIO_SPECIAL(con);
+}
+
 #endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
 
 #ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
@@ -164,3 +229,35 @@ s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
         return (__force s3c_gpio_pull_t)pup;
 }
 #endif
+
+#ifdef CONFIG_S3C_GPIO_PULL_UP
+int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
+                         unsigned int off, s3c_gpio_pull_t pull)
+{
+        void __iomem *reg = chip->base + 0x08;
+        u32 pup = __raw_readl(reg);
+
+        pup = __raw_readl(reg);
+
+        if (pup == S3C_GPIO_PULL_UP)
+                pup &= ~(1 << off);
+        else if (pup == S3C_GPIO_PULL_NONE)
+                pup |= (1 << off);
+        else
+                return -EINVAL;
+
+        __raw_writel(pup, reg);
+        return 0;
+}
+
+s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
+                                     unsigned int off)
+{
+        void __iomem *reg = chip->base + 0x08;
+        u32 pup = __raw_readl(reg);
+
+        pup &= (1 << off);
+        return pup ? S3C_GPIO_PULL_NONE : S3C_GPIO_PULL_UP;
+}
+#endif /* CONFIG_S3C_GPIO_PULL_UP */
+
diff --git a/arch/arm/plat-samsung/gpio.c b/arch/arm/plat-samsung/gpio.c
index 28d2ab8a08db..b83a83351cea 100644
--- a/arch/arm/plat-samsung/gpio.c
+++ b/arch/arm/plat-samsung/gpio.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/spinlock.h>
 
 #include <plat/gpio-core.h>
 
@@ -52,14 +53,14 @@ static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset)
         unsigned long flags;
         unsigned long con;
 
-        local_irq_save(flags);
+        s3c_gpio_lock(ourchip, flags);
 
         con = __raw_readl(base + 0x00);
         con &= ~(3 << (offset * 2));
 
         __raw_writel(con, base + 0x00);
 
-        local_irq_restore(flags);
+        s3c_gpio_unlock(ourchip, flags);
         return 0;
 }
 
@@ -72,7 +73,7 @@ static int s3c_gpiolib_output(struct gpio_chip *chip,
         unsigned long dat;
         unsigned long con;
 
-        local_irq_save(flags);
+        s3c_gpio_lock(ourchip, flags);
 
         dat = __raw_readl(base + 0x04);
         dat &= ~(1 << offset);
@@ -87,7 +88,7 @@ static int s3c_gpiolib_output(struct gpio_chip *chip,
         __raw_writel(con, base + 0x00);
         __raw_writel(dat, base + 0x04);
 
-        local_irq_restore(flags);
+        s3c_gpio_unlock(ourchip, flags);
         return 0;
 }
 
@@ -99,7 +100,7 @@ static void s3c_gpiolib_set(struct gpio_chip *chip,
         unsigned long flags;
         unsigned long dat;
 
-        local_irq_save(flags);
+        s3c_gpio_lock(ourchip, flags);
 
         dat = __raw_readl(base + 0x04);
         dat &= ~(1 << offset);
@@ -107,7 +108,7 @@ static void s3c_gpiolib_set(struct gpio_chip *chip,
                 dat |= 1 << offset;
         __raw_writel(dat, base + 0x04);
 
-        local_irq_restore(flags);
+        s3c_gpio_unlock(ourchip, flags);
 }
 
 static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset)
@@ -131,6 +132,8 @@ __init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
         BUG_ON(!gc->label);
         BUG_ON(!gc->ngpio);
 
+        spin_lock_init(&chip->lock);
+
         if (!gc->direction_input)
                 gc->direction_input = s3c_gpiolib_input;
         if (!gc->direction_output)
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 60b62692ac7a..0fbcd0effd8e 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -74,6 +74,7 @@ extern struct clk clk_ext;
 extern struct clk clk_h2;
 extern struct clk clk_27m;
 extern struct clk clk_48m;
+extern struct clk clk_xusbxti;
 
 extern int clk_default_setrate(struct clk *clk, unsigned long rate);
 extern struct clk_ops clk_ops_def_setrate;
@@ -91,6 +92,7 @@ extern int s3c24xx_register_clock(struct clk *clk);
 extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
 
 extern void s3c_register_clocks(struct clk *clk, int nr_clks);
+extern void s3c_disable_clocks(struct clk *clkp, int nr_clks);
 
 extern int s3c24xx_register_baseclocks(unsigned long xtal);
 
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index d316b4a579f4..6412933d6fbb 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -73,11 +73,15 @@ extern struct sys_timer s3c24xx_timer;
 extern struct sysdev_class s3c2410_sysclass;
 extern struct sysdev_class s3c2410a_sysclass;
 extern struct sysdev_class s3c2412_sysclass;
+extern struct sysdev_class s3c2416_sysclass;
 extern struct sysdev_class s3c2440_sysclass;
 extern struct sysdev_class s3c2442_sysclass;
 extern struct sysdev_class s3c2443_sysclass;
 extern struct sysdev_class s3c6410_sysclass;
 extern struct sysdev_class s3c64xx_sysclass;
+extern struct sysdev_class s5p6440_sysclass;
+extern struct sysdev_class s5p6442_sysclass;
+extern struct sysdev_class s5pv210_sysclass;
 
 extern void (*s5pc1xx_idle)(void);
 
diff --git a/arch/arm/plat-samsung/include/plat/dma.h b/arch/arm/plat-samsung/include/plat/dma.h
index 7584d751ed51..2e8f8c6560d7 100644
--- a/arch/arm/plat-samsung/include/plat/dma.h
+++ b/arch/arm/plat-samsung/include/plat/dma.h
@@ -110,8 +110,8 @@ extern int s3c2410_dma_config(unsigned int channel, int xferunit);
  * configure the device we're talking to
 */
 
-extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
-                                 unsigned long devaddr);
+extern int s3c2410_dma_devconfig(unsigned int channel,
+                enum s3c2410_dmasrc source, unsigned long devaddr);
 
 /* s3c2410_dma_getposition
  *
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index ffc01a76b7ce..1f85649d8c18 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -15,6 +15,13 @@
 #ifndef __PLAT_S3C_FB_H
 #define __PLAT_S3C_FB_H __FILE__
 
+/* S3C_FB_MAX_WIN
+ * Set to the maximum number of windows that any of the supported hardware
+ * can use. Since the platform data uses this for an array size, having it
+ * set to the maximum of any version of the hardware can do is safe.
+ */
+#define S3C_FB_MAX_WIN  (5)
+
 /**
  * struct s3c_fb_pd_win - per window setup data
  * @win_mode: The display parameters to initialise (not for window 0)
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
index dda19da037ad..3e21c75feefa 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
@@ -30,6 +30,12 @@ static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip,
         return (chip->config->set_config)(chip, off, config);
 }
 
+static inline unsigned s3c_gpio_do_getcfg(struct s3c_gpio_chip *chip,
+                                          unsigned int off)
+{
+        return (chip->config->get_config)(chip, off);
+}
+
 static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip,
                                       unsigned int off, s3c_gpio_pull_t pull)
 {
@@ -53,6 +59,18 @@ extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
                                    unsigned int off, unsigned int cfg);
 
 /**
+ * s3c_gpio_getcfg_s3c24xx - S3C24XX style GPIO configuration read.
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ *
+ * The reverse of s3c_gpio_setcfg_s3c24xx(). Will return a value whicg
+ * could be directly passed back to s3c_gpio_setcfg_s3c24xx(), from the
+ * S3C_GPIO_SPECIAL() macro.
+ */
+unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,
+                                     unsigned int off);
+
+/**
  * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A)
  * @chip: The gpio chip that is being configured.
  * @off: The offset for the GPIO being configured.
@@ -65,6 +83,21 @@ extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
 extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
                                      unsigned int off, unsigned int cfg);
 
+
+/**
+ * s3c_gpio_getcfg_s3c24xx_a - S3C24XX style GPIO configuration read (Bank A)
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ *
+ * The reverse of s3c_gpio_setcfg_s3c24xx_a() turning an GPIO into a usable
+ * GPIO configuration value.
+ *
+ * @sa s3c_gpio_getcfg_s3c24xx
+ * @sa s3c_gpio_getcfg_s3c64xx_4bit
+ */
+extern unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
+                                          unsigned int off);
+
 /**
  * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config.
  * @chip: The gpio chip that is being configured.
@@ -85,6 +118,20 @@ extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
                                         unsigned int off, unsigned int cfg);
 
 
+/**
+ * s3c_gpio_getcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config read.
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ *
+ * The reverse of s3c_gpio_setcfg_s3c64xx_4bit(), turning a gpio configuration
+ * register setting into a value the software can use, such as could be passed
+ * to s3c_gpio_setcfg_s3c64xx_4bit().
+ *
+ * @sa s3c_gpio_getcfg_s3c24xx
+ */
+extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
+                                             unsigned int off);
+
 /* Pull-{up,down} resistor controls.
  *
  * S3C2410,S3C2440,S3C24A0 = Pull-UP,
@@ -146,6 +193,17 @@ extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
                                                unsigned int off);
 
 /**
+ * s3c_gpio_getpull_1up() - Get configuration for choice of up or none
+ * @chip: The gpio chip that the GPIO pin belongs to
+ * @off: The offset to the pin to get the configuration of.
+ *
+ * This helper function reads the state of the pull-up resistor for the
+ * given GPIO in the same case as s3c_gpio_setpull_1up.
+*/
+extern s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
+                                            unsigned int off);
+
+/**
  * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443.
  * @chip: The gpio chip that is being configured.
  * @off: The offset for the GPIO being configured.
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index 29cd6a86cade..8d01e853df39 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -77,6 +77,17 @@ struct s3c_gpio_cfg {
  */
 extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to);
 
+/**
+ * s3c_gpio_getcfg - Read the current function for a GPIO pin
+ * @pin: The pin to read the configuration value for.
+ *
+ * Read the configuration state of the given @pin, returning a value that
+ * could be passed back to s3c_gpio_cfgpin().
+ *
+ * @sa s3c_gpio_cfgpin
+ */
+extern unsigned s3c_gpio_getcfg(unsigned int pin);
+
 /* Define values for the pull-{up,down} available for each gpio pin.
  *
  * These values control the state of the weak pull-{up,down} resistors
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index 49ff406a7066..f3a68d1a07b9 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -44,16 +44,26 @@ struct s3c_gpio_cfg;
  * @chip: The chip structure to be exported via gpiolib.
  * @base: The base pointer to the gpio configuration registers.
  * @config: special function and pull-resistor control information.
+ * @lock: Lock for exclusive access to this gpio bank.
  * @pm_save: Save information for suspend/resume support.
  *
  * This wrapper provides the necessary information for the Samsung
  * specific gpios being registered with gpiolib.
+ *
+ * The lock protects each gpio bank from multiple access of the shared
+ * configuration registers, or from reading of data whilst another thread
+ * is writing to the register set.
+ *
+ * Each chip has its own lock to avoid any  contention between different
+ * CPU cores trying to get one lock for different GPIO banks, where each
+ * bank of GPIO has its own register space and configuration registers.
  */
 struct s3c_gpio_chip {
         struct gpio_chip        chip;
         struct s3c_gpio_cfg     *config;
         struct s3c_gpio_pm      *pm;
         void __iomem            *base;
+        spinlock_t               lock;
 #ifdef CONFIG_PM
         u32                     pm_save[4];
 #endif
@@ -108,6 +118,9 @@ extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
 extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip);
 extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
 
+/* exported for core SoC support to change */
+extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
+
 #ifdef CONFIG_S3C_GPIO_TRACK
 extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
 
@@ -135,3 +148,7 @@ extern struct s3c_gpio_pm s3c_gpio_pm_4bit;
 #define __gpio_pm(x) NULL
 
 #endif /* CONFIG_PM */
+
+/* locking wrappers to deal with multiple access to the same gpio bank */
+#define s3c_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl)
+#define s3c_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl)
diff --git a/arch/arm/plat-samsung/include/plat/hwmon.h b/arch/arm/plat-samsung/include/plat/hwmon.h
index 1ba88ea0aa31..c167e4429bc7 100644
--- a/arch/arm/plat-samsung/include/plat/hwmon.h
+++ b/arch/arm/plat-samsung/include/plat/hwmon.h
@@ -37,5 +37,15 @@ struct s3c_hwmon_pdata {
         struct s3c_hwmon_chcfg  *in[8];
 };
 
+/**
+ * s3c_hwmon_set_platdata - Set platform data for S3C HWMON device
+ * @pd: Platform data to register to device.
+ *
+ * Register the given platform data for use with the S3C HWMON device.
+ * The call will copy the platform data, so the board definitions can
+ * make the structure itself __initdata.
+ */
+extern void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd);
+
 #endif /* __ASM_ARCH_ADC_HWMON_H */
 
diff --git a/arch/arm/plat-samsung/include/plat/pll6553x.h b/arch/arm/plat-samsung/include/plat/pll6553x.h
new file mode 100644
index 000000000000..b8b7e1d884f8
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pll6553x.h
@@ -0,0 +1,51 @@
+/* arch/arm/plat-samsung/include/plat/pll6553x.h
+ *      partially from arch/arm/mach-s3c64xx/include/mach/pll.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Samsung PLL6553x PLL code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* S3C6400 and compatible (S3C2416, etc.) EPLL code */
+
+#define PLL6553X_MDIV_MASK      ((1 << (23-16)) - 1)
+#define PLL6553X_PDIV_MASK      ((1 << (13-8)) - 1)
+#define PLL6553X_SDIV_MASK      ((1 << (2-0)) - 1)
+#define PLL6553X_MDIV_SHIFT     (16)
+#define PLL6553X_PDIV_SHIFT     (8)
+#define PLL6553X_SDIV_SHIFT     (0)
+#define PLL6553X_KDIV_MASK      (0xffff)
+
+static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
+                                             u32 pll0, u32 pll1)
+{
+        unsigned long result;
+        u32 mdiv, pdiv, sdiv, kdiv;
+        u64 tmp;
+
+        mdiv = (pll0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
+        pdiv = (pll0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
+        sdiv = (pll0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
+        kdiv = pll1 & PLL6553X_KDIV_MASK;
+
+        /* We need to multiple baseclk by mdiv (the integer part) and kdiv
+         * which is in 2^16ths, so shift mdiv up (does not overflow) and
+         * add kdiv before multiplying. The use of tmp is to avoid any
+         * overflows before shifting bac down into result when multipling
+         * by the mdiv and kdiv pair.
+         */
+
+        tmp = baseclk;
+        tmp *= (mdiv << 16) + kdiv;
+        do_div(tmp, (pdiv << sdiv));
+        result = tmp >> 16;
+
+        return result;
+}
diff --git a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
new file mode 100644
index 000000000000..5fe6721b57f7
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __S3C_DMA_PL330_H_
+#define __S3C_DMA_PL330_H_
+
+#define S3C2410_DMAF_AUTOSTART          (1 << 0)
+#define S3C2410_DMAF_CIRCULAR           (1 << 1)
+
+/*
+ * PL330 can assign any channel to communicate with
+ * any of the peripherals attched to the DMAC.
+ * For the sake of consistency across client drivers,
+ * We keep the channel names unchanged and only add
+ * missing peripherals are added.
+ * Order is not important since S3C PL330 API driver
+ * use these just as IDs.
+ */
+enum dma_ch {
+        DMACH_UART0_RX,
+        DMACH_UART0_TX,
+        DMACH_UART1_RX,
+        DMACH_UART1_TX,
+        DMACH_UART2_RX,
+        DMACH_UART2_TX,
+        DMACH_UART3_RX,
+        DMACH_UART3_TX,
+        DMACH_IRDA,
+        DMACH_I2S0_RX,
+        DMACH_I2S0_TX,
+        DMACH_I2S0S_TX,
+        DMACH_I2S1_RX,
+        DMACH_I2S1_TX,
+        DMACH_I2S2_RX,
+        DMACH_I2S2_TX,
+        DMACH_SPI0_RX,
+        DMACH_SPI0_TX,
+        DMACH_SPI1_RX,
+        DMACH_SPI1_TX,
+        DMACH_SPI2_RX,
+        DMACH_SPI2_TX,
+        DMACH_AC97_MICIN,
+        DMACH_AC97_PCMIN,
+        DMACH_AC97_PCMOUT,
+        DMACH_EXTERNAL,
+        DMACH_PWM,
+        DMACH_SPDIF,
+        DMACH_HSI_RX,
+        DMACH_HSI_TX,
+        DMACH_PCM0_TX,
+        DMACH_PCM0_RX,
+        DMACH_PCM1_TX,
+        DMACH_PCM1_RX,
+        DMACH_PCM2_TX,
+        DMACH_PCM2_RX,
+        DMACH_MSM_REQ3,
+        DMACH_MSM_REQ2,
+        DMACH_MSM_REQ1,
+        DMACH_MSM_REQ0,
+        /* END Marker, also used to denote a reserved channel */
+        DMACH_MAX,
+};
+
+static inline bool s3c_dma_has_circular(void)
+{
+        return true;
+}
+
+#include <plat/dma.h>
+
+#endif  /* __S3C_DMA_PL330_H_ */
diff --git a/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h b/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h
new file mode 100644
index 000000000000..bf5e2a9d408d
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h
@@ -0,0 +1,32 @@
+/* linux/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __S3C_PL330_PDATA_H
+#define __S3C_PL330_PDATA_H
+
+#include <plat/s3c-dma-pl330.h>
+
+/*
+ * Every PL330 DMAC has max 32 peripheral interfaces,
+ * of which some may be not be really used in your
+ * DMAC's configuration.
+ * Populate this array of 32 peri i/fs with relevant
+ * channel IDs for used peri i/f and DMACH_MAX for
+ * those unused.
+ *
+ * The platforms just need to provide this info
+ * to the S3C DMA API driver for PL330.
+ */
+struct s3c_pl330_platdata {
+        enum dma_ch peri[32];
+};
+
+#endif /* __S3C_PL330_PDATA_H */
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index 69a4c7f02e25..d50ab9d2af53 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -329,7 +329,7 @@ void s3c_pm_save_gpios(void)
         struct s3c_gpio_chip *ourchip;
         unsigned int gpio_nr;
 
-        for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
+        for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) {
                 ourchip = s3c_gpiolib_getchip(gpio_nr);
                 if (!ourchip)
                         continue;
@@ -367,7 +367,7 @@ void s3c_pm_restore_gpios(void)
         struct s3c_gpio_chip *ourchip;
         unsigned int gpio_nr;
 
-        for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
+        for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) {
                 ourchip = s3c_gpiolib_getchip(gpio_nr);
                 if (!ourchip)
                         continue;
diff --git a/arch/arm/plat-samsung/s3c-pl330.c b/arch/arm/plat-samsung/s3c-pl330.c
new file mode 100644
index 000000000000..a91305a60aed
--- /dev/null
+++ b/arch/arm/plat-samsung/s3c-pl330.c
@@ -0,0 +1,1224 @@
+/* linux/arch/arm/plat-samsung/s3c-pl330.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+
+#include <asm/hardware/pl330.h>
+
+#include <plat/s3c-pl330-pdata.h>
+
+/**
+ * struct s3c_pl330_dmac - Logical representation of a PL330 DMAC.
+ * @busy_chan: Number of channels currently busy.
+ * @peri: List of IDs of peripherals this DMAC can work with.
+ * @node: To attach to the global list of DMACs.
+ * @pi: PL330 configuration info for the DMAC.
+ * @kmcache: Pool to quickly allocate xfers for all channels in the dmac.
+ */
+struct s3c_pl330_dmac {
+        unsigned                busy_chan;
+        enum dma_ch             *peri;
+        struct list_head        node;
+        struct pl330_info       *pi;
+        struct kmem_cache       *kmcache;
+};
+
+/**
+ * struct s3c_pl330_xfer - A request submitted by S3C DMA clients.
+ * @token: Xfer ID provided by the client.
+ * @node: To attach to the list of xfers on a channel.
+ * @px: Xfer for PL330 core.
+ * @chan: Owner channel of this xfer.
+ */
+struct s3c_pl330_xfer {
+        void                    *token;
+        struct list_head        node;
+        struct pl330_xfer       px;
+        struct s3c_pl330_chan   *chan;
+};
+
+/**
+ * struct s3c_pl330_chan - Logical channel to communicate with
+ *      a Physical peripheral.
+ * @pl330_chan_id: Token of a hardware channel thread of PL330 DMAC.
+ *      NULL if the channel is available to be acquired.
+ * @id: ID of the peripheral that this channel can communicate with.
+ * @options: Options specified by the client.
+ * @sdaddr: Address provided via s3c2410_dma_devconfig.
+ * @node: To attach to the global list of channels.
+ * @lrq: Pointer to the last submitted pl330_req to PL330 core.
+ * @xfer_list: To manage list of xfers enqueued.
+ * @req: Two requests to communicate with the PL330 engine.
+ * @callback_fn: Callback function to the client.
+ * @rqcfg: Channel configuration for the xfers.
+ * @xfer_head: Pointer to the xfer to be next excecuted.
+ * @dmac: Pointer to the DMAC that manages this channel, NULL if the
+ *      channel is available to be acquired.
+ * @client: Client of this channel. NULL if the
+ *      channel is available to be acquired.
+ */
+struct s3c_pl330_chan {
+        void                            *pl330_chan_id;
+        enum dma_ch                     id;
+        unsigned int                    options;
+        unsigned long                   sdaddr;
+        struct list_head                node;
+        struct pl330_req                *lrq;
+        struct list_head                xfer_list;
+        struct pl330_req                req[2];
+        s3c2410_dma_cbfn_t              callback_fn;
+        struct pl330_reqcfg             rqcfg;
+        struct s3c_pl330_xfer           *xfer_head;
+        struct s3c_pl330_dmac           *dmac;
+        struct s3c2410_dma_client       *client;
+};
+
+/* All DMACs in the platform */
+static LIST_HEAD(dmac_list);
+
+/* All channels to peripherals in the platform */
+static LIST_HEAD(chan_list);
+
+/*
+ * Since we add resources(DMACs and Channels) to the global pool,
+ * we need to guard access to the resources using a global lock
+ */
+static DEFINE_SPINLOCK(res_lock);
+
+/* Returns the channel with ID 'id' in the chan_list */
+static struct s3c_pl330_chan *id_to_chan(const enum dma_ch id)
+{
+        struct s3c_pl330_chan *ch;
+
+        list_for_each_entry(ch, &chan_list, node)
+                if (ch->id == id)
+                        return ch;
+
+        return NULL;
+}
+
+/* Allocate a new channel with ID 'id' and add to chan_list */
+static void chan_add(const enum dma_ch id)
+{
+        struct s3c_pl330_chan *ch = id_to_chan(id);
+
+        /* Return if the channel already exists */
+        if (ch)
+                return;
+
+        ch = kmalloc(sizeof(*ch), GFP_KERNEL);
+        /* Return silently to work with other channels */
+        if (!ch)
+                return;
+
+        ch->id = id;
+        ch->dmac = NULL;
+
+        list_add_tail(&ch->node, &chan_list);
+}
+
+/* If the channel is not yet acquired by any client */
+static bool chan_free(struct s3c_pl330_chan *ch)
+{
+        if (!ch)
+                return false;
+
+        /* Channel points to some DMAC only when it's acquired */
+        return ch->dmac ? false : true;
+}
+
+/*
+ * Returns 0 is peripheral i/f is invalid or not present on the dmac.
+ * Index + 1, otherwise.
+ */
+static unsigned iface_of_dmac(struct s3c_pl330_dmac *dmac, enum dma_ch ch_id)
+{
+        enum dma_ch *id = dmac->peri;
+        int i;
+
+        /* Discount invalid markers */
+        if (ch_id == DMACH_MAX)
+                return 0;
+
+        for (i = 0; i < PL330_MAX_PERI; i++)
+                if (id[i] == ch_id)
+                        return i + 1;
+
+        return 0;
+}
+
+/* If all channel threads of the DMAC are busy */
+static inline bool dmac_busy(struct s3c_pl330_dmac *dmac)
+{
+        struct pl330_info *pi = dmac->pi;
+
+        return (dmac->busy_chan < pi->pcfg.num_chan) ? false : true;
+}
+
+/*
+ * Returns the number of free channels that
+ * can be handled by this dmac only.
+ */
+static unsigned ch_onlyby_dmac(struct s3c_pl330_dmac *dmac)
+{
+        enum dma_ch *id = dmac->peri;
+        struct s3c_pl330_dmac *d;
+        struct s3c_pl330_chan *ch;
+        unsigned found, count = 0;
+        enum dma_ch p;
+        int i;
+
+        for (i = 0; i < PL330_MAX_PERI; i++) {
+                p = id[i];
+                ch = id_to_chan(p);
+
+                if (p == DMACH_MAX || !chan_free(ch))
+                        continue;
+
+                found = 0;
+                list_for_each_entry(d, &dmac_list, node) {
+                        if (d != dmac && iface_of_dmac(d, ch->id)) {
+                                found = 1;
+                                break;
+                        }
+                }
+                if (!found)
+                        count++;
+        }
+
+        return count;
+}
+
+/*
+ * Measure of suitability of 'dmac' handling 'ch'
+ *
+ * 0 indicates 'dmac' can not handle 'ch' either
+ * because it is not supported by the hardware or
+ * because all dmac channels are currently busy.
+ *
+ * >0 vlaue indicates 'dmac' has the capability.
+ * The bigger the value the more suitable the dmac.
+ */
+#define MAX_SUIT        UINT_MAX
+#define MIN_SUIT        0
+
+static unsigned suitablility(struct s3c_pl330_dmac *dmac,
+                struct s3c_pl330_chan *ch)
+{
+        struct pl330_info *pi = dmac->pi;
+        enum dma_ch *id = dmac->peri;
+        struct s3c_pl330_dmac *d;
+        unsigned s;
+        int i;
+
+        s = MIN_SUIT;
+        /* If all the DMAC channel threads are busy */
+        if (dmac_busy(dmac))
+                return s;
+
+        for (i = 0; i < PL330_MAX_PERI; i++)
+                if (id[i] == ch->id)
+                        break;
+
+        /* If the 'dmac' can't talk to 'ch' */
+        if (i == PL330_MAX_PERI)
+                return s;
+
+        s = MAX_SUIT;
+        list_for_each_entry(d, &dmac_list, node) {
+                /*
+                 * If some other dmac can talk to this
+                 * peri and has some channel free.
+                 */
+                if (d != dmac && iface_of_dmac(d, ch->id) && !dmac_busy(d)) {
+                        s = 0;
+                        break;
+                }
+        }
+        if (s)
+                return s;
+
+        s = 100;
+
+        /* Good if free chans are more, bad otherwise */
+        s += (pi->pcfg.num_chan - dmac->busy_chan) - ch_onlyby_dmac(dmac);
+
+        return s;
+}
+
+/* More than one DMAC may have capability to transfer data with the
+ * peripheral. This function assigns most suitable DMAC to manage the
+ * channel and hence communicate with the peripheral.
+ */
+static struct s3c_pl330_dmac *map_chan_to_dmac(struct s3c_pl330_chan *ch)
+{
+        struct s3c_pl330_dmac *d, *dmac = NULL;
+        unsigned sn, sl = MIN_SUIT;
+
+        list_for_each_entry(d, &dmac_list, node) {
+                sn = suitablility(d, ch);
+
+                if (sn == MAX_SUIT)
+                        return d;
+
+                if (sn > sl)
+                        dmac = d;
+        }
+
+        return dmac;
+}
+
+/* Acquire the channel for peripheral 'id' */
+static struct s3c_pl330_chan *chan_acquire(const enum dma_ch id)
+{
+        struct s3c_pl330_chan *ch = id_to_chan(id);
+        struct s3c_pl330_dmac *dmac;
+
+        /* If the channel doesn't exist or is already acquired */
+        if (!ch || !chan_free(ch)) {
+                ch = NULL;
+                goto acq_exit;
+        }
+
+        dmac = map_chan_to_dmac(ch);
+        /* If couldn't map */
+        if (!dmac) {
+                ch = NULL;
+                goto acq_exit;
+        }
+
+        dmac->busy_chan++;
+        ch->dmac = dmac;
+
+acq_exit:
+        return ch;
+}
+
+/* Delete xfer from the queue */
+static inline void del_from_queue(struct s3c_pl330_xfer *xfer)
+{
+        struct s3c_pl330_xfer *t;
+        struct s3c_pl330_chan *ch;
+        int found;
+
+        if (!xfer)
+                return;
+
+        ch = xfer->chan;
+
+        /* Make sure xfer is in the queue */
+        found = 0;
+        list_for_each_entry(t, &ch->xfer_list, node)
+                if (t == xfer) {
+                        found = 1;
+                        break;
+                }
+
+        if (!found)
+                return;
+
+        /* If xfer is last entry in the queue */
+        if (xfer->node.next == &ch->xfer_list)
+                t = list_entry(ch->xfer_list.next,
+                                struct s3c_pl330_xfer, node);
+        else
+                t = list_entry(xfer->node.next,
+                                struct s3c_pl330_xfer, node);
+
+        /* If there was only one node left */
+        if (t == xfer)
+                ch->xfer_head = NULL;
+        else if (ch->xfer_head == xfer)
+                ch->xfer_head = t;
+
+        list_del(&xfer->node);
+}
+
+/* Provides pointer to the next xfer in the queue.
+ * If CIRCULAR option is set, the list is left intact,
+ * otherwise the xfer is removed from the list.
+ * Forced delete 'pluck' can be set to override the CIRCULAR option.
+ */
+static struct s3c_pl330_xfer *get_from_queue(struct s3c_pl330_chan *ch,
+                int pluck)
+{
+        struct s3c_pl330_xfer *xfer = ch->xfer_head;
+
+        if (!xfer)
+                return NULL;
+
+        /* If xfer is last entry in the queue */
+        if (xfer->node.next == &ch->xfer_list)
+                ch->xfer_head = list_entry(ch->xfer_list.next,
+                                        struct s3c_pl330_xfer, node);
+        else
+                ch->xfer_head = list_entry(xfer->node.next,
+                                        struct s3c_pl330_xfer, node);
+
+        if (pluck || !(ch->options & S3C2410_DMAF_CIRCULAR))
+                del_from_queue(xfer);
+
+        return xfer;
+}
+
+static inline void add_to_queue(struct s3c_pl330_chan *ch,
+                struct s3c_pl330_xfer *xfer, int front)
+{
+        struct pl330_xfer *xt;
+
+        /* If queue empty */
+        if (ch->xfer_head == NULL)
+                ch->xfer_head = xfer;
+
+        xt = &ch->xfer_head->px;
+        /* If the head already submitted (CIRCULAR head) */
+        if (ch->options & S3C2410_DMAF_CIRCULAR &&
+                (xt == ch->req[0].x || xt == ch->req[1].x))
+                ch->xfer_head = xfer;
+
+        /* If this is a resubmission, it should go at the head */
+        if (front) {
+                ch->xfer_head = xfer;
+                list_add(&xfer->node, &ch->xfer_list);
+        } else {
+                list_add_tail(&xfer->node, &ch->xfer_list);
+        }
+}
+
+static inline void _finish_off(struct s3c_pl330_xfer *xfer,
+                enum s3c2410_dma_buffresult res, int ffree)
+{
+        struct s3c_pl330_chan *ch;
+
+        if (!xfer)
+                return;
+
+        ch = xfer->chan;
+
+        /* Do callback */
+        if (ch->callback_fn)
+                ch->callback_fn(NULL, xfer->token, xfer->px.bytes, res);
+
+        /* Force Free or if buffer is not needed anymore */
+        if (ffree || !(ch->options & S3C2410_DMAF_CIRCULAR))
+                kmem_cache_free(ch->dmac->kmcache, xfer);
+}
+
+static inline int s3c_pl330_submit(struct s3c_pl330_chan *ch,
+                struct pl330_req *r)
+{
+        struct s3c_pl330_xfer *xfer;
+        int ret = 0;
+
+        /* If already submitted */
+        if (r->x)
+                return 0;
+
+        xfer = get_from_queue(ch, 0);
+        if (xfer) {
+                r->x = &xfer->px;
+
+                /* Use max bandwidth for M<->M xfers */
+                if (r->rqtype == MEMTOMEM) {
+                        struct pl330_info *pi = xfer->chan->dmac->pi;
+                        int burst = 1 << ch->rqcfg.brst_size;
+                        u32 bytes = r->x->bytes;
+                        int bl;
+
+                        bl = pi->pcfg.data_bus_width / 8;
+                        bl *= pi->pcfg.data_buf_dep;
+                        bl /= burst;
+
+                        /* src/dst_burst_len can't be more than 16 */
+                        if (bl > 16)
+                                bl = 16;
+
+                        while (bl > 1) {
+                                if (!(bytes % (bl * burst)))
+                                        break;
+                                bl--;
+                        }
+
+                        ch->rqcfg.brst_len = bl;
+                } else {
+                        ch->rqcfg.brst_len = 1;
+                }
+
+                ret = pl330_submit_req(ch->pl330_chan_id, r);
+
+                /* If submission was successful */
+                if (!ret) {
+                        ch->lrq = r; /* latest submitted req */
+                        return 0;
+                }
+
+                r->x = NULL;
+
+                /* If both of the PL330 ping-pong buffers filled */
+                if (ret == -EAGAIN) {
+                        dev_err(ch->dmac->pi->dev, "%s:%d!\n",
+                                __func__, __LINE__);
+                        /* Queue back again */
+                        add_to_queue(ch, xfer, 1);
+                        ret = 0;
+                } else {
+                        dev_err(ch->dmac->pi->dev, "%s:%d!\n",
+                                __func__, __LINE__);
+                        _finish_off(xfer, S3C2410_RES_ERR, 0);
+                }
+        }
+
+        return ret;
+}
+
+static void s3c_pl330_rq(struct s3c_pl330_chan *ch,
+        struct pl330_req *r, enum pl330_op_err err)
+{
+        unsigned long flags;
+        struct s3c_pl330_xfer *xfer;
+        struct pl330_xfer *xl = r->x;
+        enum s3c2410_dma_buffresult res;
+
+        spin_lock_irqsave(&res_lock, flags);
+
+        r->x = NULL;
+
+        s3c_pl330_submit(ch, r);
+
+        spin_unlock_irqrestore(&res_lock, flags);
+
+        /* Map result to S3C DMA API */
+        if (err == PL330_ERR_NONE)
+                res = S3C2410_RES_OK;
+        else if (err == PL330_ERR_ABORT)
+                res = S3C2410_RES_ABORT;
+        else
+                res = S3C2410_RES_ERR;
+
+        /* If last request had some xfer */
+        if (xl) {
+                xfer = container_of(xl, struct s3c_pl330_xfer, px);
+                _finish_off(xfer, res, 0);
+        } else {
+                dev_info(ch->dmac->pi->dev, "%s:%d No Xfer?!\n",
+                        __func__, __LINE__);
+        }
+}
+
+static void s3c_pl330_rq0(void *token, enum pl330_op_err err)
+{
+        struct pl330_req *r = token;
+        struct s3c_pl330_chan *ch = container_of(r,
+                                        struct s3c_pl330_chan, req[0]);
+        s3c_pl330_rq(ch, r, err);
+}
+
+static void s3c_pl330_rq1(void *token, enum pl330_op_err err)
+{
+        struct pl330_req *r = token;
+        struct s3c_pl330_chan *ch = container_of(r,
+                                        struct s3c_pl330_chan, req[1]);
+        s3c_pl330_rq(ch, r, err);
+}
+
+/* Release an acquired channel */
+static void chan_release(struct s3c_pl330_chan *ch)
+{
+        struct s3c_pl330_dmac *dmac;
+
+        if (chan_free(ch))
+                return;
+
+        dmac = ch->dmac;
+        ch->dmac = NULL;
+        dmac->busy_chan--;
+}
+
+int s3c2410_dma_ctrl(enum dma_ch id, enum s3c2410_chan_op op)
+{
+        struct s3c_pl330_xfer *xfer;
+        enum pl330_chan_op pl330op;
+        struct s3c_pl330_chan *ch;
+        unsigned long flags;
+        int idx, ret;
+
+        spin_lock_irqsave(&res_lock, flags);
+
+        ch = id_to_chan(id);
+
+        if (!ch || chan_free(ch)) {
+                ret = -EINVAL;
+                goto ctrl_exit;
+        }
+
+        switch (op) {
+        case S3C2410_DMAOP_START:
+                /* Make sure both reqs are enqueued */
+                idx = (ch->lrq == &ch->req[0]) ? 1 : 0;
+                s3c_pl330_submit(ch, &ch->req[idx]);
+                s3c_pl330_submit(ch, &ch->req[1 - idx]);
+                pl330op = PL330_OP_START;
+                break;
+
+        case S3C2410_DMAOP_STOP:
+                pl330op = PL330_OP_ABORT;
+                break;
+
+        case S3C2410_DMAOP_FLUSH:
+                pl330op = PL330_OP_FLUSH;
+                break;
+
+        case S3C2410_DMAOP_PAUSE:
+        case S3C2410_DMAOP_RESUME:
+        case S3C2410_DMAOP_TIMEOUT:
+        case S3C2410_DMAOP_STARTED:
+                spin_unlock_irqrestore(&res_lock, flags);
+                return 0;
+
+        default:
+                spin_unlock_irqrestore(&res_lock, flags);
+                return -EINVAL;
+        }
+
+        ret = pl330_chan_ctrl(ch->pl330_chan_id, pl330op);
+
+        if (pl330op == PL330_OP_START) {
+                spin_unlock_irqrestore(&res_lock, flags);
+                return ret;
+        }
+
+        idx = (ch->lrq == &ch->req[0]) ? 1 : 0;
+
+        /* Abort the current xfer */
+        if (ch->req[idx].x) {
+                xfer = container_of(ch->req[idx].x,
+                                struct s3c_pl330_xfer, px);
+
+                /* Drop xfer during FLUSH */
+                if (pl330op == PL330_OP_FLUSH)
+                        del_from_queue(xfer);
+
+                ch->req[idx].x = NULL;
+
+                spin_unlock_irqrestore(&res_lock, flags);
+                _finish_off(xfer, S3C2410_RES_ABORT,
+                                pl330op == PL330_OP_FLUSH ? 1 : 0);
+                spin_lock_irqsave(&res_lock, flags);
+        }
+
+        /* Flush the whole queue */
+        if (pl330op == PL330_OP_FLUSH) {
+
+                if (ch->req[1 - idx].x) {
+                        xfer = container_of(ch->req[1 - idx].x,
+                                        struct s3c_pl330_xfer, px);
+
+                        del_from_queue(xfer);
+
+                        ch->req[1 - idx].x = NULL;
+
+                        spin_unlock_irqrestore(&res_lock, flags);
+                        _finish_off(xfer, S3C2410_RES_ABORT, 1);
+                        spin_lock_irqsave(&res_lock, flags);
+                }
+
+                /* Finish off the remaining in the queue */
+                xfer = ch->xfer_head;
+                while (xfer) {
+
+                        del_from_queue(xfer);
+
+                        spin_unlock_irqrestore(&res_lock, flags);
+                        _finish_off(xfer, S3C2410_RES_ABORT, 1);
+                        spin_lock_irqsave(&res_lock, flags);
+
+                        xfer = ch->xfer_head;
+                }
+        }
+
+ctrl_exit:
+        spin_unlock_irqrestore(&res_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(s3c2410_dma_ctrl);
+
+int s3c2410_dma_enqueue(enum dma_ch id, void *token,
+                        dma_addr_t addr, int size)
+{
+        struct s3c_pl330_chan *ch;
+        struct s3c_pl330_xfer *xfer;
+        unsigned long flags;
+        int idx, ret = 0;
+
+        spin_lock_irqsave(&res_lock, flags);
+
+        ch = id_to_chan(id);
+
+        /* Error if invalid or free channel */
+        if (!ch || chan_free(ch)) {
+                ret = -EINVAL;
+                goto enq_exit;
+        }
+
+        /* Error if size is unaligned */
+        if (ch->rqcfg.brst_size && size % (1 << ch->rqcfg.brst_size)) {
+                ret = -EINVAL;
+                goto enq_exit;
+        }
+
+        xfer = kmem_cache_alloc(ch->dmac->kmcache, GFP_ATOMIC);
+        if (!xfer) {
+                ret = -ENOMEM;
+                goto enq_exit;
+        }
+
+        xfer->token = token;
+        xfer->chan = ch;
+        xfer->px.bytes = size;
+        xfer->px.next = NULL; /* Single request */
+
+        /* For S3C DMA API, direction is always fixed for all xfers */
+        if (ch->req[0].rqtype == MEMTODEV) {
+                xfer->px.src_addr = addr;
+                xfer->px.dst_addr = ch->sdaddr;
+        } else {
+                xfer->px.src_addr = ch->sdaddr;
+                xfer->px.dst_addr = addr;
+        }
+
+        add_to_queue(ch, xfer, 0);
+
+        /* Try submitting on either request */
+        idx = (ch->lrq == &ch->req[0]) ? 1 : 0;
+
+        if (!ch->req[idx].x)
+                s3c_pl330_submit(ch, &ch->req[idx]);
+        else
+                s3c_pl330_submit(ch, &ch->req[1 - idx]);
+
+        spin_unlock_irqrestore(&res_lock, flags);
+
+        if (ch->options & S3C2410_DMAF_AUTOSTART)
+                s3c2410_dma_ctrl(id, S3C2410_DMAOP_START);
+
+        return 0;
+
+enq_exit:
+        spin_unlock_irqrestore(&res_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(s3c2410_dma_enqueue);
+
+int s3c2410_dma_request(enum dma_ch id,
+                        struct s3c2410_dma_client *client,
+                        void *dev)
+{
+        struct s3c_pl330_dmac *dmac;
+        struct s3c_pl330_chan *ch;
+        unsigned long flags;
+        int ret = 0;
+
+        spin_lock_irqsave(&res_lock, flags);
+
+        ch = chan_acquire(id);
+        if (!ch) {
+                ret = -EBUSY;
+                goto req_exit;
+        }
+
+        dmac = ch->dmac;
+
+        ch->pl330_chan_id = pl330_request_channel(dmac->pi);
+        if (!ch->pl330_chan_id) {
+                chan_release(ch);
+                ret = -EBUSY;
+                goto req_exit;
+        }
+
+        ch->client = client;
+        ch->options = 0; /* Clear any option */
+        ch->callback_fn = NULL; /* Clear any callback */
+        ch->lrq = NULL;
+
+        ch->rqcfg.brst_size = 2; /* Default word size */
+        ch->rqcfg.swap = SWAP_NO;
+        ch->rqcfg.scctl = SCCTRL0; /* Noncacheable and nonbufferable */
+        ch->rqcfg.dcctl = DCCTRL0; /* Noncacheable and nonbufferable */
+        ch->rqcfg.privileged = 0;
+        ch->rqcfg.insnaccess = 0;
+
+        /* Set invalid direction */
+        ch->req[0].rqtype = DEVTODEV;
+        ch->req[1].rqtype = ch->req[0].rqtype;
+
+        ch->req[0].cfg = &ch->rqcfg;
+        ch->req[1].cfg = ch->req[0].cfg;
+
+        ch->req[0].peri = iface_of_dmac(dmac, id) - 1; /* Original index */
+        ch->req[1].peri = ch->req[0].peri;
+
+        ch->req[0].token = &ch->req[0];
+        ch->req[0].xfer_cb = s3c_pl330_rq0;
+        ch->req[1].token = &ch->req[1];
+        ch->req[1].xfer_cb = s3c_pl330_rq1;
+
+        ch->req[0].x = NULL;
+        ch->req[1].x = NULL;
+
+        /* Reset xfer list */
+        INIT_LIST_HEAD(&ch->xfer_list);
+        ch->xfer_head = NULL;
+
+req_exit:
+        spin_unlock_irqrestore(&res_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(s3c2410_dma_request);
+
+int s3c2410_dma_free(enum dma_ch id, struct s3c2410_dma_client *client)
+{
+        struct s3c_pl330_chan *ch;
+        struct s3c_pl330_xfer *xfer;
+        unsigned long flags;
+        int ret = 0;
+        unsigned idx;
+
+        spin_lock_irqsave(&res_lock, flags);
+
+        ch = id_to_chan(id);
+
+        if (!ch || chan_free(ch))
+                goto free_exit;
+
+        /* Refuse if someone else wanted to free the channel */
+        if (ch->client != client) {
+                ret = -EBUSY;
+                goto free_exit;
+        }
+
+        /* Stop any active xfer, Flushe the queue and do callbacks */
+        pl330_chan_ctrl(ch->pl330_chan_id, PL330_OP_FLUSH);
+
+        /* Abort the submitted requests */
+        idx = (ch->lrq == &ch->req[0]) ? 1 : 0;
+
+        if (ch->req[idx].x) {
+                xfer = container_of(ch->req[idx].x,
+                                struct s3c_pl330_xfer, px);
+
+                ch->req[idx].x = NULL;
+                del_from_queue(xfer);
+
+                spin_unlock_irqrestore(&res_lock, flags);
+                _finish_off(xfer, S3C2410_RES_ABORT, 1);
+                spin_lock_irqsave(&res_lock, flags);
+        }
+
+        if (ch->req[1 - idx].x) {
+                xfer = container_of(ch->req[1 - idx].x,
+                                struct s3c_pl330_xfer, px);
+
+                ch->req[1 - idx].x = NULL;
+                del_from_queue(xfer);
+
+                spin_unlock_irqrestore(&res_lock, flags);
+                _finish_off(xfer, S3C2410_RES_ABORT, 1);
+                spin_lock_irqsave(&res_lock, flags);
+        }
+
+        /* Pluck and Abort the queued requests in order */
+        do {
+                xfer = get_from_queue(ch, 1);
+
+                spin_unlock_irqrestore(&res_lock, flags);
+                _finish_off(xfer, S3C2410_RES_ABORT, 1);
+                spin_lock_irqsave(&res_lock, flags);
+        } while (xfer);
+
+        ch->client = NULL;
+
+        pl330_release_channel(ch->pl330_chan_id);
+
+        ch->pl330_chan_id = NULL;
+
+        chan_release(ch);
+
+free_exit:
+        spin_unlock_irqrestore(&res_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(s3c2410_dma_free);
+
+int s3c2410_dma_config(enum dma_ch id, int xferunit)
+{
+        struct s3c_pl330_chan *ch;
+        struct pl330_info *pi;
+        unsigned long flags;
+        int i, dbwidth, ret = 0;
+
+        spin_lock_irqsave(&res_lock, flags);
+
+        ch = id_to_chan(id);
+
+        if (!ch || chan_free(ch)) {
+                ret = -EINVAL;
+                goto cfg_exit;
+        }
+
+        pi = ch->dmac->pi;
+        dbwidth = pi->pcfg.data_bus_width / 8;
+
+        /* Max size of xfer can be pcfg.data_bus_width */
+        if (xferunit > dbwidth) {
+                ret = -EINVAL;
+                goto cfg_exit;
+        }
+
+        i = 0;
+        while (xferunit != (1 << i))
+                i++;
+
+        /* If valid value */
+        if (xferunit == (1 << i))
+                ch->rqcfg.brst_size = i;
+        else
+                ret = -EINVAL;
+
+cfg_exit:
+        spin_unlock_irqrestore(&res_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(s3c2410_dma_config);
+
+/* Options that are supported by this driver */
+#define S3C_PL330_FLAGS (S3C2410_DMAF_CIRCULAR | S3C2410_DMAF_AUTOSTART)
+
+int s3c2410_dma_setflags(enum dma_ch id, unsigned int options)
+{
+        struct s3c_pl330_chan *ch;
+        unsigned long flags;
+        int ret = 0;
+
+        spin_lock_irqsave(&res_lock, flags);
+
+        ch = id_to_chan(id);
+
+        if (!ch || chan_free(ch) || options & ~(S3C_PL330_FLAGS))
+                ret = -EINVAL;
+        else
+                ch->options = options;
+
+        spin_unlock_irqrestore(&res_lock, flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_setflags);
+
+int s3c2410_dma_set_buffdone_fn(enum dma_ch id, s3c2410_dma_cbfn_t rtn)
+{
+        struct s3c_pl330_chan *ch;
+        unsigned long flags;
+        int ret = 0;
+
+        spin_lock_irqsave(&res_lock, flags);
+
+        ch = id_to_chan(id);
+
+        if (!ch || chan_free(ch))
+                ret = -EINVAL;
+        else
+                ch->callback_fn = rtn;
+
+        spin_unlock_irqrestore(&res_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
+
+int s3c2410_dma_devconfig(enum dma_ch id, enum s3c2410_dmasrc source,
+                          unsigned long address)
+{
+        struct s3c_pl330_chan *ch;
+        unsigned long flags;
+        int ret = 0;
+
+        spin_lock_irqsave(&res_lock, flags);
+
+        ch = id_to_chan(id);
+
+        if (!ch || chan_free(ch)) {
+                ret = -EINVAL;
+                goto devcfg_exit;
+        }
+
+        switch (source) {
+        case S3C2410_DMASRC_HW: /* P->M */
+                ch->req[0].rqtype = DEVTOMEM;
+                ch->req[1].rqtype = DEVTOMEM;
+                ch->rqcfg.src_inc = 0;
+                ch->rqcfg.dst_inc = 1;
+                break;
+        case S3C2410_DMASRC_MEM: /* M->P */
+                ch->req[0].rqtype = MEMTODEV;
+                ch->req[1].rqtype = MEMTODEV;
+                ch->rqcfg.src_inc = 1;
+                ch->rqcfg.dst_inc = 0;
+                break;
+        default:
+                ret = -EINVAL;
+                goto devcfg_exit;
+        }
+
+        ch->sdaddr = address;
+
+devcfg_exit:
+        spin_unlock_irqrestore(&res_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(s3c2410_dma_devconfig);
+
+int s3c2410_dma_getposition(enum dma_ch id, dma_addr_t *src, dma_addr_t *dst)
+{
+        struct s3c_pl330_chan *ch = id_to_chan(id);
+        struct pl330_chanstatus status;
+        int ret;
+
+        if (!ch || chan_free(ch))
+                return -EINVAL;
+
+        ret = pl330_chan_status(ch->pl330_chan_id, &status);
+        if (ret < 0)
+                return ret;
+
+        *src = status.src_addr;
+        *dst = status.dst_addr;
+
+        return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_getposition);
+
+static irqreturn_t pl330_irq_handler(int irq, void *data)
+{
+        if (pl330_update(data))
+                return IRQ_HANDLED;
+        else
+                return IRQ_NONE;
+}
+
+static int pl330_probe(struct platform_device *pdev)
+{
+        struct s3c_pl330_dmac *s3c_pl330_dmac;
+        struct s3c_pl330_platdata *pl330pd;
+        struct pl330_info *pl330_info;
+        struct resource *res;
+        int i, ret, irq;
+
+        pl330pd = pdev->dev.platform_data;
+
+        /* Can't do without the list of _32_ peripherals */
+        if (!pl330pd || !pl330pd->peri) {
+                dev_err(&pdev->dev, "platform data missing!\n");
+                return -ENODEV;
+        }
+
+        pl330_info = kzalloc(sizeof(*pl330_info), GFP_KERNEL);
+        if (!pl330_info)
+                return -ENOMEM;
+
+        pl330_info->pl330_data = NULL;
+        pl330_info->dev = &pdev->dev;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                ret = -ENODEV;
+                goto probe_err1;
+        }
+
+        request_mem_region(res->start, resource_size(res), pdev->name);
+
+        pl330_info->base = ioremap(res->start, resource_size(res));
+        if (!pl330_info->base) {
+                ret = -ENXIO;
+                goto probe_err2;
+        }
+
+        irq = platform_get_irq(pdev, 0);
+        if (irq < 0) {
+                ret = irq;
+                goto probe_err3;
+        }
+
+        ret = request_irq(irq, pl330_irq_handler, 0,
+                        dev_name(&pdev->dev), pl330_info);
+        if (ret)
+                goto probe_err4;
+
+        ret = pl330_add(pl330_info);
+        if (ret)
+                goto probe_err5;
+
+        /* Allocate a new DMAC */
+        s3c_pl330_dmac = kmalloc(sizeof(*s3c_pl330_dmac), GFP_KERNEL);
+        if (!s3c_pl330_dmac) {
+                ret = -ENOMEM;
+                goto probe_err6;
+        }
+
+        /* Hook the info */
+        s3c_pl330_dmac->pi = pl330_info;
+
+        /* No busy channels */
+        s3c_pl330_dmac->busy_chan = 0;
+
+        s3c_pl330_dmac->kmcache = kmem_cache_create(dev_name(&pdev->dev),
+                                sizeof(struct s3c_pl330_xfer), 0, 0, NULL);
+
+        if (!s3c_pl330_dmac->kmcache) {
+                ret = -ENOMEM;
+                goto probe_err7;
+        }
+
+        /* Get the list of peripherals */
+        s3c_pl330_dmac->peri = pl330pd->peri;
+
+        /* Attach to the list of DMACs */
+        list_add_tail(&s3c_pl330_dmac->node, &dmac_list);
+
+        /* Create a channel for each peripheral in the DMAC
+         * that is, if it doesn't already exist
+         */
+        for (i = 0; i < PL330_MAX_PERI; i++)
+                if (s3c_pl330_dmac->peri[i] != DMACH_MAX)
+                        chan_add(s3c_pl330_dmac->peri[i]);
+
+        printk(KERN_INFO
+                "Loaded driver for PL330 DMAC-%d %s\n", pdev->id, pdev->name);
+        printk(KERN_INFO
+                "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
+                pl330_info->pcfg.data_buf_dep,
+                pl330_info->pcfg.data_bus_width / 8, pl330_info->pcfg.num_chan,
+                pl330_info->pcfg.num_peri, pl330_info->pcfg.num_events);
+
+        return 0;
+
+probe_err7:
+        kfree(s3c_pl330_dmac);
+probe_err6:
+        pl330_del(pl330_info);
+probe_err5:
+        free_irq(irq, pl330_info);
+probe_err4:
+probe_err3:
+        iounmap(pl330_info->base);
+probe_err2:
+        release_mem_region(res->start, resource_size(res));
+probe_err1:
+        kfree(pl330_info);
+
+        return ret;
+}
+
+static int pl330_remove(struct platform_device *pdev)
+{
+        struct s3c_pl330_dmac *dmac, *d;
+        struct s3c_pl330_chan *ch;
+        unsigned long flags;
+        int del, found;
+
+        if (!pdev->dev.platform_data)
+                return -EINVAL;
+
+        spin_lock_irqsave(&res_lock, flags);
+
+        found = 0;
+        list_for_each_entry(d, &dmac_list, node)
+                if (d->pi->dev == &pdev->dev) {
+                        found = 1;
+                        break;
+                }
+
+        if (!found) {
+                spin_unlock_irqrestore(&res_lock, flags);
+                return 0;
+        }
+
+        dmac = d;
+
+        /* Remove all Channels that are managed only by this DMAC */
+        list_for_each_entry(ch, &chan_list, node) {
+
+                /* Only channels that are handled by this DMAC */
+                if (iface_of_dmac(dmac, ch->id))
+                        del = 1;
+                else
+                        continue;
+
+                /* Don't remove if some other DMAC has it too */
+                list_for_each_entry(d, &dmac_list, node)
+                        if (d != dmac && iface_of_dmac(d, ch->id)) {
+                                del = 0;
+                                break;
+                        }
+
+                if (del) {
+                        spin_unlock_irqrestore(&res_lock, flags);
+                        s3c2410_dma_free(ch->id, ch->client);
+                        spin_lock_irqsave(&res_lock, flags);
+                        list_del(&ch->node);
+                        kfree(ch);
+                }
+        }
+
+        /* Remove the DMAC */
+        list_del(&dmac->node);
+        kfree(dmac);
+
+        spin_unlock_irqrestore(&res_lock, flags);
+
+        return 0;
+}
+
+static struct platform_driver pl330_driver = {
+        .driver         = {
+                .owner  = THIS_MODULE,
+                .name   = "s3c-pl330",
+        },
+        .probe          = pl330_probe,
+        .remove         = pl330_remove,
+};
+
+static int __init pl330_init(void)
+{
+        return platform_driver_register(&pl330_driver);
+}
+module_init(pl330_init);
+
+static void __exit pl330_exit(void)
+{
+        platform_driver_unregister(&pl330_driver);
+        return;
+}
+module_exit(pl330_exit);
+
+MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
+MODULE_DESCRIPTION("Driver for PL330 DMA Controller");
+MODULE_LICENSE("GPL");
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index f55c49475a8c..5f3f03df92e3 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -518,12 +518,13 @@ config SERIAL_S3C2412
           Serial port support for the Samsung S3C2412 and S3C2413 SoC
 
 config SERIAL_S3C2440
-        tristate "Samsung S3C2440/S3C2442 Serial port support"
-        depends on SERIAL_SAMSUNG && (CPU_S3C2440 || CPU_S3C2442)
+        tristate "Samsung S3C2440/S3C2442/S3C2416 Serial port support"
+        depends on SERIAL_SAMSUNG && (CPU_S3C2440 || CPU_S3C2442 || CPU_S3C2416)
         default y if CPU_S3C2440
         default y if CPU_S3C2442
+        select SERIAL_SAMSUNG_UARTS_4 if CPU_S3C2416
         help
-          Serial port support for the Samsung S3C2440 and S3C2442 SoC
+          Serial port support for the Samsung S3C2440, S3C2416 and S3C2442 SoC
 
 config SERIAL_S3C24A0
         tristate "Samsung S3C24A0 Serial port support"