diff options
-rw-r--r-- | sound/soc/samsung/i2s-regs.h | 123 | ||||
-rw-r--r-- | sound/soc/samsung/i2s.c | 104 |
2 files changed, 124 insertions, 103 deletions
diff --git a/sound/soc/samsung/i2s-regs.h b/sound/soc/samsung/i2s-regs.h new file mode 100644 index 000000000000..1fa0cd10153c --- /dev/null +++ b/sound/soc/samsung/i2s-regs.h | |||
@@ -0,0 +1,123 @@ | |||
1 | /* | ||
2 | * linux/sound/soc/samsung/i2s-regs.h | ||
3 | * | ||
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
5 | * http://www.samsung.com | ||
6 | * | ||
7 | * Samsung I2S driver's register header | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify it | ||
10 | * under the terms of the GNU General Public License as published by the | ||
11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
12 | * option) any later version. | ||
13 | */ | ||
14 | |||
15 | #ifndef __SND_SOC_SAMSUNG_I2S_REGS_H | ||
16 | #define __SND_SOC_SAMSUNG_I2S_REGS_H | ||
17 | |||
18 | #define I2SCON 0x0 | ||
19 | #define I2SMOD 0x4 | ||
20 | #define I2SFIC 0x8 | ||
21 | #define I2SPSR 0xc | ||
22 | #define I2STXD 0x10 | ||
23 | #define I2SRXD 0x14 | ||
24 | #define I2SFICS 0x18 | ||
25 | #define I2STXDS 0x1c | ||
26 | |||
27 | #define CON_RSTCLR (1 << 31) | ||
28 | #define CON_FRXOFSTATUS (1 << 26) | ||
29 | #define CON_FRXORINTEN (1 << 25) | ||
30 | #define CON_FTXSURSTAT (1 << 24) | ||
31 | #define CON_FTXSURINTEN (1 << 23) | ||
32 | #define CON_TXSDMA_PAUSE (1 << 20) | ||
33 | #define CON_TXSDMA_ACTIVE (1 << 18) | ||
34 | |||
35 | #define CON_FTXURSTATUS (1 << 17) | ||
36 | #define CON_FTXURINTEN (1 << 16) | ||
37 | #define CON_TXFIFO2_EMPTY (1 << 15) | ||
38 | #define CON_TXFIFO1_EMPTY (1 << 14) | ||
39 | #define CON_TXFIFO2_FULL (1 << 13) | ||
40 | #define CON_TXFIFO1_FULL (1 << 12) | ||
41 | |||
42 | #define CON_LRINDEX (1 << 11) | ||
43 | #define CON_TXFIFO_EMPTY (1 << 10) | ||
44 | #define CON_RXFIFO_EMPTY (1 << 9) | ||
45 | #define CON_TXFIFO_FULL (1 << 8) | ||
46 | #define CON_RXFIFO_FULL (1 << 7) | ||
47 | #define CON_TXDMA_PAUSE (1 << 6) | ||
48 | #define CON_RXDMA_PAUSE (1 << 5) | ||
49 | #define CON_TXCH_PAUSE (1 << 4) | ||
50 | #define CON_RXCH_PAUSE (1 << 3) | ||
51 | #define CON_TXDMA_ACTIVE (1 << 2) | ||
52 | #define CON_RXDMA_ACTIVE (1 << 1) | ||
53 | #define CON_ACTIVE (1 << 0) | ||
54 | |||
55 | #define MOD_OPCLK_CDCLK_OUT (0 << 30) | ||
56 | #define MOD_OPCLK_CDCLK_IN (1 << 30) | ||
57 | #define MOD_OPCLK_BCLK_OUT (2 << 30) | ||
58 | #define MOD_OPCLK_PCLK (3 << 30) | ||
59 | #define MOD_OPCLK_MASK (3 << 30) | ||
60 | #define MOD_TXS_IDMA (1 << 28) /* Sec_TXFIFO use I-DMA */ | ||
61 | |||
62 | #define MOD_BLCS_SHIFT 26 | ||
63 | #define MOD_BLCS_16BIT (0 << MOD_BLCS_SHIFT) | ||
64 | #define MOD_BLCS_8BIT (1 << MOD_BLCS_SHIFT) | ||
65 | #define MOD_BLCS_24BIT (2 << MOD_BLCS_SHIFT) | ||
66 | #define MOD_BLCS_MASK (3 << MOD_BLCS_SHIFT) | ||
67 | #define MOD_BLCP_SHIFT 24 | ||
68 | #define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT) | ||
69 | #define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT) | ||
70 | #define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT) | ||
71 | #define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT) | ||
72 | |||
73 | #define MOD_C2DD_HHALF (1 << 21) /* Discard Higher-half */ | ||
74 | #define MOD_C2DD_LHALF (1 << 20) /* Discard Lower-half */ | ||
75 | #define MOD_C1DD_HHALF (1 << 19) | ||
76 | #define MOD_C1DD_LHALF (1 << 18) | ||
77 | #define MOD_DC2_EN (1 << 17) | ||
78 | #define MOD_DC1_EN (1 << 16) | ||
79 | #define MOD_BLC_16BIT (0 << 13) | ||
80 | #define MOD_BLC_8BIT (1 << 13) | ||
81 | #define MOD_BLC_24BIT (2 << 13) | ||
82 | #define MOD_BLC_MASK (3 << 13) | ||
83 | |||
84 | #define MOD_IMS_SYSMUX (1 << 10) | ||
85 | #define MOD_SLAVE (1 << 11) | ||
86 | #define MOD_TXONLY (0 << 8) | ||
87 | #define MOD_RXONLY (1 << 8) | ||
88 | #define MOD_TXRX (2 << 8) | ||
89 | #define MOD_MASK (3 << 8) | ||
90 | #define MOD_LR_LLOW (0 << 7) | ||
91 | #define MOD_LR_RLOW (1 << 7) | ||
92 | #define MOD_SDF_IIS (0 << 5) | ||
93 | #define MOD_SDF_MSB (1 << 5) | ||
94 | #define MOD_SDF_LSB (2 << 5) | ||
95 | #define MOD_SDF_MASK (3 << 5) | ||
96 | #define MOD_RCLK_256FS (0 << 3) | ||
97 | #define MOD_RCLK_512FS (1 << 3) | ||
98 | #define MOD_RCLK_384FS (2 << 3) | ||
99 | #define MOD_RCLK_768FS (3 << 3) | ||
100 | #define MOD_RCLK_MASK (3 << 3) | ||
101 | #define MOD_BCLK_32FS (0 << 1) | ||
102 | #define MOD_BCLK_48FS (1 << 1) | ||
103 | #define MOD_BCLK_16FS (2 << 1) | ||
104 | #define MOD_BCLK_24FS (3 << 1) | ||
105 | #define MOD_BCLK_MASK (3 << 1) | ||
106 | #define MOD_8BIT (1 << 0) | ||
107 | |||
108 | #define MOD_CDCLKCON (1 << 12) | ||
109 | |||
110 | #define PSR_PSREN (1 << 15) | ||
111 | |||
112 | #define FIC_TX2COUNT(x) (((x) >> 24) & 0xf) | ||
113 | #define FIC_TX1COUNT(x) (((x) >> 16) & 0xf) | ||
114 | |||
115 | #define FIC_TXFLUSH (1 << 15) | ||
116 | #define FIC_RXFLUSH (1 << 7) | ||
117 | #define FIC_TXCOUNT(x) (((x) >> 8) & 0xf) | ||
118 | #define FIC_RXCOUNT(x) (((x) >> 0) & 0xf) | ||
119 | #define FICS_TXCOUNT(x) (((x) >> 8) & 0x7f) | ||
120 | |||
121 | #endif /* __SND_SOC_SAMSUNG_I2S_REGS_H */ | ||
122 | |||
123 | |||
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c index 992a732b5211..1568eea31f41 100644 --- a/sound/soc/samsung/i2s.c +++ b/sound/soc/samsung/i2s.c | |||
@@ -22,109 +22,7 @@ | |||
22 | 22 | ||
23 | #include "dma.h" | 23 | #include "dma.h" |
24 | #include "i2s.h" | 24 | #include "i2s.h" |
25 | 25 | #include "i2s-regs.h" | |
26 | #define I2SCON 0x0 | ||
27 | #define I2SMOD 0x4 | ||
28 | #define I2SFIC 0x8 | ||
29 | #define I2SPSR 0xc | ||
30 | #define I2STXD 0x10 | ||
31 | #define I2SRXD 0x14 | ||
32 | #define I2SFICS 0x18 | ||
33 | #define I2STXDS 0x1c | ||
34 | |||
35 | #define CON_RSTCLR (1 << 31) | ||
36 | #define CON_FRXOFSTATUS (1 << 26) | ||
37 | #define CON_FRXORINTEN (1 << 25) | ||
38 | #define CON_FTXSURSTAT (1 << 24) | ||
39 | #define CON_FTXSURINTEN (1 << 23) | ||
40 | #define CON_TXSDMA_PAUSE (1 << 20) | ||
41 | #define CON_TXSDMA_ACTIVE (1 << 18) | ||
42 | |||
43 | #define CON_FTXURSTATUS (1 << 17) | ||
44 | #define CON_FTXURINTEN (1 << 16) | ||
45 | #define CON_TXFIFO2_EMPTY (1 << 15) | ||
46 | #define CON_TXFIFO1_EMPTY (1 << 14) | ||
47 | #define CON_TXFIFO2_FULL (1 << 13) | ||
48 | #define CON_TXFIFO1_FULL (1 << 12) | ||
49 | |||
50 | #define CON_LRINDEX (1 << 11) | ||
51 | #define CON_TXFIFO_EMPTY (1 << 10) | ||
52 | #define CON_RXFIFO_EMPTY (1 << 9) | ||
53 | #define CON_TXFIFO_FULL (1 << 8) | ||
54 | #define CON_RXFIFO_FULL (1 << 7) | ||
55 | #define CON_TXDMA_PAUSE (1 << 6) | ||
56 | #define CON_RXDMA_PAUSE (1 << 5) | ||
57 | #define CON_TXCH_PAUSE (1 << 4) | ||
58 | #define CON_RXCH_PAUSE (1 << 3) | ||
59 | #define CON_TXDMA_ACTIVE (1 << 2) | ||
60 | #define CON_RXDMA_ACTIVE (1 << 1) | ||
61 | #define CON_ACTIVE (1 << 0) | ||
62 | |||
63 | #define MOD_OPCLK_CDCLK_OUT (0 << 30) | ||
64 | #define MOD_OPCLK_CDCLK_IN (1 << 30) | ||
65 | #define MOD_OPCLK_BCLK_OUT (2 << 30) | ||
66 | #define MOD_OPCLK_PCLK (3 << 30) | ||
67 | #define MOD_OPCLK_MASK (3 << 30) | ||
68 | #define MOD_TXS_IDMA (1 << 28) /* Sec_TXFIFO use I-DMA */ | ||
69 | |||
70 | #define MOD_BLCS_SHIFT 26 | ||
71 | #define MOD_BLCS_16BIT (0 << MOD_BLCS_SHIFT) | ||
72 | #define MOD_BLCS_8BIT (1 << MOD_BLCS_SHIFT) | ||
73 | #define MOD_BLCS_24BIT (2 << MOD_BLCS_SHIFT) | ||
74 | #define MOD_BLCS_MASK (3 << MOD_BLCS_SHIFT) | ||
75 | #define MOD_BLCP_SHIFT 24 | ||
76 | #define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT) | ||
77 | #define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT) | ||
78 | #define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT) | ||
79 | #define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT) | ||
80 | |||
81 | #define MOD_C2DD_HHALF (1 << 21) /* Discard Higher-half */ | ||
82 | #define MOD_C2DD_LHALF (1 << 20) /* Discard Lower-half */ | ||
83 | #define MOD_C1DD_HHALF (1 << 19) | ||
84 | #define MOD_C1DD_LHALF (1 << 18) | ||
85 | #define MOD_DC2_EN (1 << 17) | ||
86 | #define MOD_DC1_EN (1 << 16) | ||
87 | #define MOD_BLC_16BIT (0 << 13) | ||
88 | #define MOD_BLC_8BIT (1 << 13) | ||
89 | #define MOD_BLC_24BIT (2 << 13) | ||
90 | #define MOD_BLC_MASK (3 << 13) | ||
91 | |||
92 | #define MOD_IMS_SYSMUX (1 << 10) | ||
93 | #define MOD_SLAVE (1 << 11) | ||
94 | #define MOD_TXONLY (0 << 8) | ||
95 | #define MOD_RXONLY (1 << 8) | ||
96 | #define MOD_TXRX (2 << 8) | ||
97 | #define MOD_MASK (3 << 8) | ||
98 | #define MOD_LR_LLOW (0 << 7) | ||
99 | #define MOD_LR_RLOW (1 << 7) | ||
100 | #define MOD_SDF_IIS (0 << 5) | ||
101 | #define MOD_SDF_MSB (1 << 5) | ||
102 | #define MOD_SDF_LSB (2 << 5) | ||
103 | #define MOD_SDF_MASK (3 << 5) | ||
104 | #define MOD_RCLK_256FS (0 << 3) | ||
105 | #define MOD_RCLK_512FS (1 << 3) | ||
106 | #define MOD_RCLK_384FS (2 << 3) | ||
107 | #define MOD_RCLK_768FS (3 << 3) | ||
108 | #define MOD_RCLK_MASK (3 << 3) | ||
109 | #define MOD_BCLK_32FS (0 << 1) | ||
110 | #define MOD_BCLK_48FS (1 << 1) | ||
111 | #define MOD_BCLK_16FS (2 << 1) | ||
112 | #define MOD_BCLK_24FS (3 << 1) | ||
113 | #define MOD_BCLK_MASK (3 << 1) | ||
114 | #define MOD_8BIT (1 << 0) | ||
115 | |||
116 | #define MOD_CDCLKCON (1 << 12) | ||
117 | |||
118 | #define PSR_PSREN (1 << 15) | ||
119 | |||
120 | #define FIC_TX2COUNT(x) (((x) >> 24) & 0xf) | ||
121 | #define FIC_TX1COUNT(x) (((x) >> 16) & 0xf) | ||
122 | |||
123 | #define FIC_TXFLUSH (1 << 15) | ||
124 | #define FIC_RXFLUSH (1 << 7) | ||
125 | #define FIC_TXCOUNT(x) (((x) >> 8) & 0xf) | ||
126 | #define FIC_RXCOUNT(x) (((x) >> 0) & 0xf) | ||
127 | #define FICS_TXCOUNT(x) (((x) >> 8) & 0x7f) | ||
128 | 26 | ||
129 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | 27 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) |
130 | 28 | ||