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-rw-r--r--arch/mips/Kconfig25
-rw-r--r--arch/mips/Makefile11
-rw-r--r--arch/mips/configs/atlas_defconfig1
-rw-r--r--arch/mips/configs/bigsur_defconfig1
-rw-r--r--arch/mips/configs/capcella_defconfig1
-rw-r--r--arch/mips/configs/cobalt_defconfig1
-rw-r--r--arch/mips/configs/db1000_defconfig1
-rw-r--r--arch/mips/configs/db1100_defconfig1
-rw-r--r--arch/mips/configs/db1200_defconfig1
-rw-r--r--arch/mips/configs/db1500_defconfig1
-rw-r--r--arch/mips/configs/db1550_defconfig1
-rw-r--r--arch/mips/configs/ddb5477_defconfig988
-rw-r--r--arch/mips/configs/decstation_defconfig1
-rw-r--r--arch/mips/configs/e55_defconfig1
-rw-r--r--arch/mips/configs/emma2rh_defconfig1
-rw-r--r--arch/mips/configs/excite_defconfig1
-rw-r--r--arch/mips/configs/fulong_defconfig1
-rw-r--r--arch/mips/configs/ip22_defconfig1
-rw-r--r--arch/mips/configs/ip27_defconfig1
-rw-r--r--arch/mips/configs/ip32_defconfig1
-rw-r--r--arch/mips/configs/jazz_defconfig1
-rw-r--r--arch/mips/configs/jmr3927_defconfig1
-rw-r--r--arch/mips/configs/malta_defconfig1
-rw-r--r--arch/mips/configs/mipssim_defconfig1
-rw-r--r--arch/mips/configs/mpc30x_defconfig1
-rw-r--r--arch/mips/configs/msp71xx_defconfig1
-rw-r--r--arch/mips/configs/pb1100_defconfig1
-rw-r--r--arch/mips/configs/pb1500_defconfig1
-rw-r--r--arch/mips/configs/pb1550_defconfig1
-rw-r--r--arch/mips/configs/pnx8550-jbs_defconfig1
-rw-r--r--arch/mips/configs/pnx8550-stb810_defconfig1
-rw-r--r--arch/mips/configs/qemu_defconfig1
-rw-r--r--arch/mips/configs/rbhma4200_defconfig1
-rw-r--r--arch/mips/configs/rbhma4500_defconfig1
-rw-r--r--arch/mips/configs/rm200_defconfig1
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig1
-rw-r--r--arch/mips/configs/sead_defconfig1
-rw-r--r--arch/mips/configs/tb0219_defconfig1
-rw-r--r--arch/mips/configs/tb0226_defconfig1
-rw-r--r--arch/mips/configs/tb0287_defconfig1
-rw-r--r--arch/mips/configs/workpad_defconfig1
-rw-r--r--arch/mips/configs/wrppmc_defconfig1
-rw-r--r--arch/mips/configs/yosemite_defconfig1
-rw-r--r--arch/mips/ddb5xxx/Kconfig4
-rw-r--r--arch/mips/ddb5xxx/common/Makefile7
-rw-r--r--arch/mips/ddb5xxx/common/nile4.c130
-rw-r--r--arch/mips/ddb5xxx/common/prom.c132
-rw-r--r--arch/mips/ddb5xxx/common/rtc_ds1386.c170
-rw-r--r--arch/mips/ddb5xxx/ddb5477/Makefile11
-rw-r--r--arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c49
-rw-r--r--arch/mips/ddb5xxx/ddb5477/debug.c160
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq.c209
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq_5477.c154
-rw-r--r--arch/mips/ddb5xxx/ddb5477/kgdb_io.c136
-rw-r--r--arch/mips/ddb5xxx/ddb5477/lcd44780.c96
-rw-r--r--arch/mips/ddb5xxx/ddb5477/lcd44780.h15
-rw-r--r--arch/mips/ddb5xxx/ddb5477/setup.c399
-rw-r--r--arch/mips/defconfig1
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/fixup-ddb5477.c78
-rw-r--r--arch/mips/pci/ops-ddb5477.c278
-rw-r--r--arch/mips/pci/pci-ddb5477.c207
-rw-r--r--include/asm-mips/bootinfo.h10
-rw-r--r--include/asm-mips/ddb5xxx/ddb5477.h342
-rw-r--r--include/asm-mips/ddb5xxx/ddb5xxx.h263
65 files changed, 0 insertions, 3916 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1d9a65e4c5cc..3b404b7dfa39 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -227,26 +227,6 @@ config MIPS_SIM
227 This option enables support for MIPS Technologies MIPSsim software 227 This option enables support for MIPS Technologies MIPSsim software
228 emulator. 228 emulator.
229 229
230config DDB5477
231 bool "NEC DDB Vrc-5477"
232 select DDB5XXX_COMMON
233 select DMA_NONCOHERENT
234 select HW_HAS_PCI
235 select I8259
236 select IRQ_CPU
237 select SYS_HAS_CPU_R5432
238 select SYS_SUPPORTS_32BIT_KERNEL
239 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
240 select SYS_SUPPORTS_KGDB
241 select SYS_SUPPORTS_KGDB
242 select SYS_SUPPORTS_LITTLE_ENDIAN
243 help
244 This enables support for the R5432-based NEC DDB Vrc-5477,
245 or Rockhopper/SolutionGear boards with R5432/R5500 CPUs.
246
247 Features : kernel debugging, serial terminal, NFS root fs, on-board
248 ether port USB, AC97, PCI, etc.
249
250config MARKEINS 230config MARKEINS
251 bool "NEC EMMA2RH Mark-eins" 231 bool "NEC EMMA2RH Mark-eins"
252 select DMA_NONCOHERENT 232 select DMA_NONCOHERENT
@@ -617,7 +597,6 @@ config WR_PPMC
617endchoice 597endchoice
618 598
619source "arch/mips/au1000/Kconfig" 599source "arch/mips/au1000/Kconfig"
620source "arch/mips/ddb5xxx/Kconfig"
621source "arch/mips/jazz/Kconfig" 600source "arch/mips/jazz/Kconfig"
622source "arch/mips/pmc-sierra/Kconfig" 601source "arch/mips/pmc-sierra/Kconfig"
623source "arch/mips/sgi-ip27/Kconfig" 602source "arch/mips/sgi-ip27/Kconfig"
@@ -789,10 +768,6 @@ config IRQ_MSP_SLP
789config IRQ_MSP_CIC 768config IRQ_MSP_CIC
790 bool 769 bool
791 770
792config DDB5XXX_COMMON
793 bool
794 select SYS_SUPPORTS_KGDB
795
796config MIPS_BOARDS_GEN 771config MIPS_BOARDS_GEN
797 bool 772 bool
798 773
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 2bd0a86e2f9c..32c1c8fb6f98 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -367,17 +367,6 @@ cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite
367load-$(CONFIG_BASLER_EXCITE) += 0x80100000 367load-$(CONFIG_BASLER_EXCITE) += 0x80100000
368 368
369# 369#
370# NEC DDB
371#
372core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/
373
374#
375# NEC DDB Vrc-5477
376#
377core-$(CONFIG_DDB5477) += arch/mips/ddb5xxx/ddb5477/
378load-$(CONFIG_DDB5477) += 0xffffffff80100000
379
380#
381# Common VR41xx 370# Common VR41xx
382# 371#
383core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/ 372core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/
diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig
index 28d36961f0ca..62bcc887f2ca 100644
--- a/arch/mips/configs/atlas_defconfig
+++ b/arch/mips/configs/atlas_defconfig
@@ -35,7 +35,6 @@ CONFIG_MIPS_ATLAS=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index 98dd3196b7c3..67a80f4c7d87 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig
index 5ffbd3885c14..4dc3197e2e9f 100644
--- a/arch/mips/configs/capcella_defconfig
+++ b/arch/mips/configs/capcella_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39CONFIG_MACH_VR41XX=y 38CONFIG_MACH_VR41XX=y
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index 410b441c5ca8..6d6a01b9a817 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -20,7 +20,6 @@ CONFIG_MIPS_COBALT=y
20# CONFIG_MIPS_SIM is not set 20# CONFIG_MIPS_SIM is not set
21# CONFIG_PNX8550_JBS is not set 21# CONFIG_PNX8550_JBS is not set
22# CONFIG_PNX8550_STB810 is not set 22# CONFIG_PNX8550_STB810 is not set
23# CONFIG_DDB5477 is not set
24# CONFIG_MACH_VR41XX is not set 23# CONFIG_MACH_VR41XX is not set
25# CONFIG_PMC_YOSEMITE is not set 24# CONFIG_PMC_YOSEMITE is not set
26# CONFIG_QEMU is not set 25# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index 7c515d7e189f..885b633647e9 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -36,7 +36,6 @@ CONFIG_MIPS_DB1000=y
36# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
37# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_DDB5477 is not set
40# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
41# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
42# CONFIG_QEMU is not set 41# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index 9460d6587a65..e3c3a07e8a7c 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -36,7 +36,6 @@ CONFIG_MIPS_DB1100=y
36# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
37# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_DDB5477 is not set
40# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
41# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
42# CONFIG_QEMU is not set 41# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index dc3985fadbd2..9aa7c3ebfa3f 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -36,7 +36,6 @@ CONFIG_MIPS_DB1200=y
36# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
37# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_DDB5477 is not set
40# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
41# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
42# CONFIG_QEMU is not set 41# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index d56931762279..99240668bca1 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -36,7 +36,6 @@ CONFIG_MIPS_DB1500=y
36# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
37# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_DDB5477 is not set
40# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
41# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
42# CONFIG_QEMU is not set 41# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 2348486cc4cd..19992f76c60d 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -36,7 +36,6 @@ CONFIG_MIPS_DB1550=y
36# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
37# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_DDB5477 is not set
40# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
41# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
42# CONFIG_QEMU is not set 41# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig
deleted file mode 100644
index 90123c69c11c..000000000000
--- a/arch/mips/configs/ddb5477_defconfig
+++ /dev/null
@@ -1,988 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.20
4# Tue Feb 20 21:47:28 2007
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11CONFIG_ZONE_DMA=y
12# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set
15# CONFIG_MIPS_PB1100 is not set
16# CONFIG_MIPS_PB1500 is not set
17# CONFIG_MIPS_PB1550 is not set
18# CONFIG_MIPS_PB1200 is not set
19# CONFIG_MIPS_DB1000 is not set
20# CONFIG_MIPS_DB1100 is not set
21# CONFIG_MIPS_DB1500 is not set
22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set
29# CONFIG_MIPS_ATLAS is not set
30# CONFIG_MIPS_MALTA is not set
31# CONFIG_MIPS_SEAD is not set
32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set
35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set
38CONFIG_DDB5477=y
39# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set
42# CONFIG_MARKEINS is not set
43# CONFIG_SGI_IP22 is not set
44# CONFIG_SGI_IP27 is not set
45# CONFIG_SGI_IP32 is not set
46# CONFIG_SIBYTE_BIGSUR is not set
47# CONFIG_SIBYTE_SWARM is not set
48# CONFIG_SIBYTE_SENTOSA is not set
49# CONFIG_SIBYTE_RHONE is not set
50# CONFIG_SIBYTE_CARMEL is not set
51# CONFIG_SIBYTE_PTSWARM is not set
52# CONFIG_SIBYTE_LITTLESUR is not set
53# CONFIG_SIBYTE_CRHINE is not set
54# CONFIG_SIBYTE_CRHONE is not set
55# CONFIG_SNI_RM is not set
56# CONFIG_TOSHIBA_JMR3927 is not set
57# CONFIG_TOSHIBA_RBTX4927 is not set
58# CONFIG_TOSHIBA_RBTX4938 is not set
59CONFIG_DDB5477_BUS_FREQUENCY=0
60CONFIG_RWSEM_GENERIC_SPINLOCK=y
61# CONFIG_ARCH_HAS_ILOG2_U32 is not set
62# CONFIG_ARCH_HAS_ILOG2_U64 is not set
63CONFIG_GENERIC_FIND_NEXT_BIT=y
64CONFIG_GENERIC_HWEIGHT=y
65CONFIG_GENERIC_CALIBRATE_DELAY=y
66CONFIG_GENERIC_TIME=y
67CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
68# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
69CONFIG_DMA_NONCOHERENT=y
70CONFIG_DMA_NEED_PCI_MAP_STATE=y
71CONFIG_I8259=y
72# CONFIG_CPU_BIG_ENDIAN is not set
73CONFIG_CPU_LITTLE_ENDIAN=y
74CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
75CONFIG_IRQ_CPU=y
76CONFIG_DDB5XXX_COMMON=y
77CONFIG_MIPS_L1_CACHE_SHIFT=5
78
79#
80# CPU selection
81#
82# CONFIG_CPU_MIPS32_R1 is not set
83# CONFIG_CPU_MIPS32_R2 is not set
84# CONFIG_CPU_MIPS64_R1 is not set
85# CONFIG_CPU_MIPS64_R2 is not set
86# CONFIG_CPU_R3000 is not set
87# CONFIG_CPU_TX39XX is not set
88# CONFIG_CPU_VR41XX is not set
89# CONFIG_CPU_R4300 is not set
90# CONFIG_CPU_R4X00 is not set
91# CONFIG_CPU_TX49XX is not set
92# CONFIG_CPU_R5000 is not set
93CONFIG_CPU_R5432=y
94# CONFIG_CPU_R6000 is not set
95# CONFIG_CPU_NEVADA is not set
96# CONFIG_CPU_R8000 is not set
97# CONFIG_CPU_R10000 is not set
98# CONFIG_CPU_RM7000 is not set
99# CONFIG_CPU_RM9000 is not set
100# CONFIG_CPU_SB1 is not set
101CONFIG_SYS_HAS_CPU_R5432=y
102CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
103CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
104CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
105CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
106
107#
108# Kernel type
109#
110CONFIG_32BIT=y
111# CONFIG_64BIT is not set
112CONFIG_PAGE_SIZE_4KB=y
113# CONFIG_PAGE_SIZE_8KB is not set
114# CONFIG_PAGE_SIZE_16KB is not set
115# CONFIG_PAGE_SIZE_64KB is not set
116CONFIG_MIPS_MT_DISABLED=y
117# CONFIG_MIPS_MT_SMP is not set
118# CONFIG_MIPS_MT_SMTC is not set
119# CONFIG_MIPS_VPE_LOADER is not set
120CONFIG_CPU_HAS_LLSC=y
121CONFIG_CPU_HAS_SYNC=y
122CONFIG_GENERIC_HARDIRQS=y
123CONFIG_GENERIC_IRQ_PROBE=y
124CONFIG_ARCH_FLATMEM_ENABLE=y
125CONFIG_SELECT_MEMORY_MODEL=y
126CONFIG_FLATMEM_MANUAL=y
127# CONFIG_DISCONTIGMEM_MANUAL is not set
128# CONFIG_SPARSEMEM_MANUAL is not set
129CONFIG_FLATMEM=y
130CONFIG_FLAT_NODE_MEM_MAP=y
131# CONFIG_SPARSEMEM_STATIC is not set
132CONFIG_SPLIT_PTLOCK_CPUS=4
133# CONFIG_RESOURCES_64BIT is not set
134CONFIG_ZONE_DMA_FLAG=1
135# CONFIG_HZ_48 is not set
136# CONFIG_HZ_100 is not set
137# CONFIG_HZ_128 is not set
138# CONFIG_HZ_250 is not set
139# CONFIG_HZ_256 is not set
140CONFIG_HZ_1000=y
141# CONFIG_HZ_1024 is not set
142CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
143CONFIG_HZ=1000
144CONFIG_PREEMPT_NONE=y
145# CONFIG_PREEMPT_VOLUNTARY is not set
146# CONFIG_PREEMPT is not set
147# CONFIG_KEXEC is not set
148CONFIG_LOCKDEP_SUPPORT=y
149CONFIG_STACKTRACE_SUPPORT=y
150CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
151
152#
153# Code maturity level options
154#
155CONFIG_EXPERIMENTAL=y
156CONFIG_BROKEN_ON_SMP=y
157CONFIG_INIT_ENV_ARG_LIMIT=32
158
159#
160# General setup
161#
162CONFIG_LOCALVERSION=""
163CONFIG_LOCALVERSION_AUTO=y
164CONFIG_SWAP=y
165CONFIG_SYSVIPC=y
166# CONFIG_IPC_NS is not set
167CONFIG_SYSVIPC_SYSCTL=y
168# CONFIG_POSIX_MQUEUE is not set
169# CONFIG_BSD_PROCESS_ACCT is not set
170# CONFIG_TASKSTATS is not set
171# CONFIG_UTS_NS is not set
172# CONFIG_AUDIT is not set
173# CONFIG_IKCONFIG is not set
174CONFIG_SYSFS_DEPRECATED=y
175CONFIG_RELAY=y
176# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
177CONFIG_SYSCTL=y
178CONFIG_EMBEDDED=y
179CONFIG_SYSCTL_SYSCALL=y
180CONFIG_KALLSYMS=y
181# CONFIG_KALLSYMS_EXTRA_PASS is not set
182CONFIG_HOTPLUG=y
183CONFIG_PRINTK=y
184CONFIG_BUG=y
185CONFIG_ELF_CORE=y
186CONFIG_BASE_FULL=y
187CONFIG_FUTEX=y
188CONFIG_EPOLL=y
189CONFIG_SHMEM=y
190CONFIG_SLAB=y
191CONFIG_VM_EVENT_COUNTERS=y
192CONFIG_RT_MUTEXES=y
193# CONFIG_TINY_SHMEM is not set
194CONFIG_BASE_SMALL=0
195# CONFIG_SLOB is not set
196
197#
198# Loadable module support
199#
200# CONFIG_MODULES is not set
201
202#
203# Block layer
204#
205CONFIG_BLOCK=y
206# CONFIG_LBD is not set
207# CONFIG_BLK_DEV_IO_TRACE is not set
208# CONFIG_LSF is not set
209
210#
211# IO Schedulers
212#
213CONFIG_IOSCHED_NOOP=y
214CONFIG_IOSCHED_AS=y
215CONFIG_IOSCHED_DEADLINE=y
216CONFIG_IOSCHED_CFQ=y
217CONFIG_DEFAULT_AS=y
218# CONFIG_DEFAULT_DEADLINE is not set
219# CONFIG_DEFAULT_CFQ is not set
220# CONFIG_DEFAULT_NOOP is not set
221CONFIG_DEFAULT_IOSCHED="anticipatory"
222
223#
224# Bus options (PCI, PCMCIA, EISA, ISA, TC)
225#
226CONFIG_HW_HAS_PCI=y
227CONFIG_PCI=y
228CONFIG_MMU=y
229
230#
231# PCCARD (PCMCIA/CardBus) support
232#
233# CONFIG_PCCARD is not set
234
235#
236# PCI Hotplug Support
237#
238# CONFIG_HOTPLUG_PCI is not set
239
240#
241# Executable file formats
242#
243CONFIG_BINFMT_ELF=y
244# CONFIG_BINFMT_MISC is not set
245CONFIG_TRAD_SIGNALS=y
246
247#
248# Power management options
249#
250CONFIG_PM=y
251# CONFIG_PM_LEGACY is not set
252# CONFIG_PM_DEBUG is not set
253# CONFIG_PM_SYSFS_DEPRECATED is not set
254
255#
256# Networking
257#
258CONFIG_NET=y
259
260#
261# Networking options
262#
263# CONFIG_NETDEBUG is not set
264CONFIG_PACKET=y
265# CONFIG_PACKET_MMAP is not set
266CONFIG_UNIX=y
267CONFIG_XFRM=y
268CONFIG_XFRM_USER=y
269# CONFIG_XFRM_SUB_POLICY is not set
270CONFIG_XFRM_MIGRATE=y
271CONFIG_NET_KEY=y
272CONFIG_NET_KEY_MIGRATE=y
273CONFIG_INET=y
274# CONFIG_IP_MULTICAST is not set
275# CONFIG_IP_ADVANCED_ROUTER is not set
276CONFIG_IP_FIB_HASH=y
277CONFIG_IP_PNP=y
278# CONFIG_IP_PNP_DHCP is not set
279CONFIG_IP_PNP_BOOTP=y
280# CONFIG_IP_PNP_RARP is not set
281# CONFIG_NET_IPIP is not set
282# CONFIG_NET_IPGRE is not set
283# CONFIG_ARPD is not set
284# CONFIG_SYN_COOKIES is not set
285# CONFIG_INET_AH is not set
286# CONFIG_INET_ESP is not set
287# CONFIG_INET_IPCOMP is not set
288# CONFIG_INET_XFRM_TUNNEL is not set
289# CONFIG_INET_TUNNEL is not set
290CONFIG_INET_XFRM_MODE_TRANSPORT=y
291CONFIG_INET_XFRM_MODE_TUNNEL=y
292CONFIG_INET_XFRM_MODE_BEET=y
293CONFIG_INET_DIAG=y
294CONFIG_INET_TCP_DIAG=y
295# CONFIG_TCP_CONG_ADVANCED is not set
296CONFIG_TCP_CONG_CUBIC=y
297CONFIG_DEFAULT_TCP_CONG="cubic"
298CONFIG_TCP_MD5SIG=y
299# CONFIG_IPV6 is not set
300# CONFIG_INET6_XFRM_TUNNEL is not set
301# CONFIG_INET6_TUNNEL is not set
302CONFIG_NETWORK_SECMARK=y
303# CONFIG_NETFILTER is not set
304
305#
306# DCCP Configuration (EXPERIMENTAL)
307#
308# CONFIG_IP_DCCP is not set
309
310#
311# SCTP Configuration (EXPERIMENTAL)
312#
313# CONFIG_IP_SCTP is not set
314
315#
316# TIPC Configuration (EXPERIMENTAL)
317#
318# CONFIG_TIPC is not set
319# CONFIG_ATM is not set
320# CONFIG_BRIDGE is not set
321# CONFIG_VLAN_8021Q is not set
322# CONFIG_DECNET is not set
323# CONFIG_LLC2 is not set
324# CONFIG_IPX is not set
325# CONFIG_ATALK is not set
326# CONFIG_X25 is not set
327# CONFIG_LAPB is not set
328# CONFIG_ECONET is not set
329# CONFIG_WAN_ROUTER is not set
330
331#
332# QoS and/or fair queueing
333#
334# CONFIG_NET_SCHED is not set
335
336#
337# Network testing
338#
339# CONFIG_NET_PKTGEN is not set
340# CONFIG_HAMRADIO is not set
341# CONFIG_IRDA is not set
342# CONFIG_BT is not set
343CONFIG_IEEE80211=y
344# CONFIG_IEEE80211_DEBUG is not set
345CONFIG_IEEE80211_CRYPT_WEP=y
346CONFIG_IEEE80211_CRYPT_CCMP=y
347CONFIG_IEEE80211_SOFTMAC=y
348# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
349CONFIG_WIRELESS_EXT=y
350
351#
352# Device Drivers
353#
354
355#
356# Generic Driver Options
357#
358CONFIG_STANDALONE=y
359CONFIG_PREVENT_FIRMWARE_BUILD=y
360CONFIG_FW_LOADER=y
361# CONFIG_SYS_HYPERVISOR is not set
362
363#
364# Connector - unified userspace <-> kernelspace linker
365#
366CONFIG_CONNECTOR=y
367CONFIG_PROC_EVENTS=y
368
369#
370# Memory Technology Devices (MTD)
371#
372# CONFIG_MTD is not set
373
374#
375# Parallel port support
376#
377# CONFIG_PARPORT is not set
378
379#
380# Plug and Play support
381#
382# CONFIG_PNPACPI is not set
383
384#
385# Block devices
386#
387# CONFIG_BLK_CPQ_DA is not set
388# CONFIG_BLK_CPQ_CISS_DA is not set
389# CONFIG_BLK_DEV_DAC960 is not set
390# CONFIG_BLK_DEV_UMEM is not set
391# CONFIG_BLK_DEV_COW_COMMON is not set
392# CONFIG_BLK_DEV_LOOP is not set
393# CONFIG_BLK_DEV_NBD is not set
394# CONFIG_BLK_DEV_SX8 is not set
395# CONFIG_BLK_DEV_RAM is not set
396# CONFIG_BLK_DEV_INITRD is not set
397CONFIG_CDROM_PKTCDVD=y
398CONFIG_CDROM_PKTCDVD_BUFFERS=8
399# CONFIG_CDROM_PKTCDVD_WCACHE is not set
400CONFIG_ATA_OVER_ETH=y
401
402#
403# Misc devices
404#
405CONFIG_SGI_IOC4=y
406# CONFIG_TIFM_CORE is not set
407
408#
409# ATA/ATAPI/MFM/RLL support
410#
411# CONFIG_IDE is not set
412
413#
414# SCSI device support
415#
416CONFIG_RAID_ATTRS=y
417# CONFIG_SCSI is not set
418# CONFIG_SCSI_NETLINK is not set
419
420#
421# Serial ATA (prod) and Parallel ATA (experimental) drivers
422#
423# CONFIG_ATA is not set
424
425#
426# Multi-device support (RAID and LVM)
427#
428# CONFIG_MD is not set
429
430#
431# Fusion MPT device support
432#
433# CONFIG_FUSION is not set
434
435#
436# IEEE 1394 (FireWire) support
437#
438# CONFIG_IEEE1394 is not set
439
440#
441# I2O device support
442#
443# CONFIG_I2O is not set
444
445#
446# Network device support
447#
448CONFIG_NETDEVICES=y
449# CONFIG_DUMMY is not set
450# CONFIG_BONDING is not set
451# CONFIG_EQUALIZER is not set
452# CONFIG_TUN is not set
453
454#
455# ARCnet devices
456#
457# CONFIG_ARCNET is not set
458
459#
460# PHY device support
461#
462CONFIG_PHYLIB=y
463
464#
465# MII PHY device drivers
466#
467CONFIG_MARVELL_PHY=y
468CONFIG_DAVICOM_PHY=y
469CONFIG_QSEMI_PHY=y
470CONFIG_LXT_PHY=y
471CONFIG_CICADA_PHY=y
472CONFIG_VITESSE_PHY=y
473CONFIG_SMSC_PHY=y
474# CONFIG_BROADCOM_PHY is not set
475# CONFIG_FIXED_PHY is not set
476
477#
478# Ethernet (10 or 100Mbit)
479#
480CONFIG_NET_ETHERNET=y
481CONFIG_MII=y
482# CONFIG_HAPPYMEAL is not set
483# CONFIG_SUNGEM is not set
484# CONFIG_CASSINI is not set
485# CONFIG_NET_VENDOR_3COM is not set
486# CONFIG_DM9000 is not set
487
488#
489# Tulip family network device support
490#
491# CONFIG_NET_TULIP is not set
492# CONFIG_HP100 is not set
493CONFIG_NET_PCI=y
494CONFIG_PCNET32=y
495# CONFIG_PCNET32_NAPI is not set
496# CONFIG_AMD8111_ETH is not set
497# CONFIG_ADAPTEC_STARFIRE is not set
498# CONFIG_B44 is not set
499# CONFIG_FORCEDETH is not set
500# CONFIG_DGRS is not set
501# CONFIG_EEPRO100 is not set
502# CONFIG_E100 is not set
503# CONFIG_FEALNX is not set
504# CONFIG_NATSEMI is not set
505# CONFIG_NE2K_PCI is not set
506# CONFIG_8139CP is not set
507# CONFIG_8139TOO is not set
508# CONFIG_SIS900 is not set
509# CONFIG_EPIC100 is not set
510# CONFIG_SUNDANCE is not set
511# CONFIG_TLAN is not set
512# CONFIG_VIA_RHINE is not set
513# CONFIG_SC92031 is not set
514
515#
516# Ethernet (1000 Mbit)
517#
518# CONFIG_ACENIC is not set
519# CONFIG_DL2K is not set
520# CONFIG_E1000 is not set
521# CONFIG_NS83820 is not set
522# CONFIG_HAMACHI is not set
523# CONFIG_YELLOWFIN is not set
524# CONFIG_R8169 is not set
525# CONFIG_SIS190 is not set
526# CONFIG_SKGE is not set
527# CONFIG_SKY2 is not set
528# CONFIG_SK98LIN is not set
529# CONFIG_VIA_VELOCITY is not set
530# CONFIG_TIGON3 is not set
531# CONFIG_BNX2 is not set
532CONFIG_QLA3XXX=y
533# CONFIG_ATL1 is not set
534
535#
536# Ethernet (10000 Mbit)
537#
538# CONFIG_CHELSIO_T1 is not set
539CONFIG_CHELSIO_T3=y
540# CONFIG_IXGB is not set
541# CONFIG_S2IO is not set
542# CONFIG_MYRI10GE is not set
543CONFIG_NETXEN_NIC=y
544
545#
546# Token Ring devices
547#
548# CONFIG_TR is not set
549
550#
551# Wireless LAN (non-hamradio)
552#
553# CONFIG_NET_RADIO is not set
554
555#
556# Wan interfaces
557#
558# CONFIG_WAN is not set
559# CONFIG_FDDI is not set
560# CONFIG_HIPPI is not set
561# CONFIG_PPP is not set
562# CONFIG_SLIP is not set
563# CONFIG_SHAPER is not set
564# CONFIG_NETCONSOLE is not set
565# CONFIG_NETPOLL is not set
566# CONFIG_NET_POLL_CONTROLLER is not set
567
568#
569# ISDN subsystem
570#
571# CONFIG_ISDN is not set
572
573#
574# Telephony Support
575#
576# CONFIG_PHONE is not set
577
578#
579# Input device support
580#
581CONFIG_INPUT=y
582# CONFIG_INPUT_FF_MEMLESS is not set
583
584#
585# Userland interfaces
586#
587CONFIG_INPUT_MOUSEDEV=y
588CONFIG_INPUT_MOUSEDEV_PSAUX=y
589CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
590CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
591# CONFIG_INPUT_JOYDEV is not set
592# CONFIG_INPUT_TSDEV is not set
593# CONFIG_INPUT_EVDEV is not set
594# CONFIG_INPUT_EVBUG is not set
595
596#
597# Input Device Drivers
598#
599# CONFIG_INPUT_KEYBOARD is not set
600# CONFIG_INPUT_MOUSE is not set
601# CONFIG_INPUT_JOYSTICK is not set
602# CONFIG_INPUT_TOUCHSCREEN is not set
603# CONFIG_INPUT_MISC is not set
604
605#
606# Hardware I/O ports
607#
608CONFIG_SERIO=y
609# CONFIG_SERIO_I8042 is not set
610CONFIG_SERIO_SERPORT=y
611# CONFIG_SERIO_PCIPS2 is not set
612# CONFIG_SERIO_LIBPS2 is not set
613CONFIG_SERIO_RAW=y
614# CONFIG_GAMEPORT is not set
615
616#
617# Character devices
618#
619CONFIG_VT=y
620CONFIG_VT_CONSOLE=y
621CONFIG_HW_CONSOLE=y
622CONFIG_VT_HW_CONSOLE_BINDING=y
623# CONFIG_SERIAL_NONSTANDARD is not set
624
625#
626# Serial drivers
627#
628CONFIG_SERIAL_8250=y
629CONFIG_SERIAL_8250_CONSOLE=y
630CONFIG_SERIAL_8250_PCI=y
631CONFIG_SERIAL_8250_NR_UARTS=4
632CONFIG_SERIAL_8250_RUNTIME_UARTS=4
633# CONFIG_SERIAL_8250_EXTENDED is not set
634
635#
636# Non-8250 serial port support
637#
638CONFIG_SERIAL_CORE=y
639CONFIG_SERIAL_CORE_CONSOLE=y
640# CONFIG_SERIAL_JSM is not set
641CONFIG_UNIX98_PTYS=y
642CONFIG_LEGACY_PTYS=y
643CONFIG_LEGACY_PTY_COUNT=256
644
645#
646# IPMI
647#
648# CONFIG_IPMI_HANDLER is not set
649
650#
651# Watchdog Cards
652#
653# CONFIG_WATCHDOG is not set
654# CONFIG_HW_RANDOM is not set
655# CONFIG_RTC is not set
656# CONFIG_GEN_RTC is not set
657# CONFIG_DTLK is not set
658# CONFIG_R3964 is not set
659# CONFIG_APPLICOM is not set
660# CONFIG_DRM is not set
661# CONFIG_RAW_DRIVER is not set
662
663#
664# TPM devices
665#
666# CONFIG_TCG_TPM is not set
667
668#
669# I2C support
670#
671# CONFIG_I2C is not set
672
673#
674# SPI support
675#
676# CONFIG_SPI is not set
677# CONFIG_SPI_MASTER is not set
678
679#
680# Dallas's 1-wire bus
681#
682# CONFIG_W1 is not set
683
684#
685# Hardware Monitoring support
686#
687# CONFIG_HWMON is not set
688# CONFIG_HWMON_VID is not set
689
690#
691# Multimedia devices
692#
693# CONFIG_VIDEO_DEV is not set
694
695#
696# Digital Video Broadcasting Devices
697#
698# CONFIG_DVB is not set
699
700#
701# Graphics support
702#
703# CONFIG_FIRMWARE_EDID is not set
704# CONFIG_FB is not set
705
706#
707# Console display driver support
708#
709# CONFIG_VGA_CONSOLE is not set
710CONFIG_DUMMY_CONSOLE=y
711# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
712
713#
714# Sound
715#
716# CONFIG_SOUND is not set
717
718#
719# HID Devices
720#
721# CONFIG_HID is not set
722
723#
724# USB support
725#
726CONFIG_USB_ARCH_HAS_HCD=y
727CONFIG_USB_ARCH_HAS_OHCI=y
728CONFIG_USB_ARCH_HAS_EHCI=y
729# CONFIG_USB is not set
730
731#
732# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
733#
734
735#
736# USB Gadget Support
737#
738# CONFIG_USB_GADGET is not set
739
740#
741# MMC/SD Card support
742#
743# CONFIG_MMC is not set
744
745#
746# LED devices
747#
748# CONFIG_NEW_LEDS is not set
749
750#
751# LED drivers
752#
753
754#
755# LED Triggers
756#
757
758#
759# InfiniBand support
760#
761# CONFIG_INFINIBAND is not set
762
763#
764# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
765#
766
767#
768# Real Time Clock
769#
770# CONFIG_RTC_CLASS is not set
771
772#
773# DMA Engine support
774#
775# CONFIG_DMA_ENGINE is not set
776
777#
778# DMA Clients
779#
780
781#
782# DMA Devices
783#
784
785#
786# Auxiliary Display support
787#
788
789#
790# Virtualization
791#
792
793#
794# File systems
795#
796CONFIG_EXT2_FS=y
797# CONFIG_EXT2_FS_XATTR is not set
798# CONFIG_EXT2_FS_XIP is not set
799# CONFIG_EXT3_FS is not set
800# CONFIG_EXT4DEV_FS is not set
801# CONFIG_REISERFS_FS is not set
802# CONFIG_JFS_FS is not set
803# CONFIG_FS_POSIX_ACL is not set
804# CONFIG_XFS_FS is not set
805# CONFIG_GFS2_FS is not set
806# CONFIG_OCFS2_FS is not set
807# CONFIG_MINIX_FS is not set
808# CONFIG_ROMFS_FS is not set
809CONFIG_INOTIFY=y
810CONFIG_INOTIFY_USER=y
811# CONFIG_QUOTA is not set
812CONFIG_DNOTIFY=y
813CONFIG_AUTOFS_FS=y
814CONFIG_AUTOFS4_FS=y
815CONFIG_FUSE_FS=y
816
817#
818# CD-ROM/DVD Filesystems
819#
820# CONFIG_ISO9660_FS is not set
821# CONFIG_UDF_FS is not set
822
823#
824# DOS/FAT/NT Filesystems
825#
826# CONFIG_MSDOS_FS is not set
827# CONFIG_VFAT_FS is not set
828# CONFIG_NTFS_FS is not set
829
830#
831# Pseudo filesystems
832#
833CONFIG_PROC_FS=y
834CONFIG_PROC_KCORE=y
835CONFIG_PROC_SYSCTL=y
836CONFIG_SYSFS=y
837# CONFIG_TMPFS is not set
838# CONFIG_HUGETLB_PAGE is not set
839CONFIG_RAMFS=y
840CONFIG_CONFIGFS_FS=y
841
842#
843# Miscellaneous filesystems
844#
845# CONFIG_ADFS_FS is not set
846# CONFIG_AFFS_FS is not set
847# CONFIG_ECRYPT_FS is not set
848# CONFIG_HFS_FS is not set
849# CONFIG_HFSPLUS_FS is not set
850# CONFIG_BEFS_FS is not set
851# CONFIG_BFS_FS is not set
852# CONFIG_EFS_FS is not set
853# CONFIG_CRAMFS is not set
854# CONFIG_VXFS_FS is not set
855# CONFIG_HPFS_FS is not set
856# CONFIG_QNX4FS_FS is not set
857# CONFIG_SYSV_FS is not set
858# CONFIG_UFS_FS is not set
859
860#
861# Network File Systems
862#
863CONFIG_NFS_FS=y
864# CONFIG_NFS_V3 is not set
865# CONFIG_NFS_V4 is not set
866# CONFIG_NFS_DIRECTIO is not set
867CONFIG_NFSD=y
868# CONFIG_NFSD_V3 is not set
869# CONFIG_NFSD_TCP is not set
870CONFIG_ROOT_NFS=y
871CONFIG_LOCKD=y
872CONFIG_EXPORTFS=y
873CONFIG_NFS_COMMON=y
874CONFIG_SUNRPC=y
875# CONFIG_RPCSEC_GSS_KRB5 is not set
876# CONFIG_RPCSEC_GSS_SPKM3 is not set
877# CONFIG_SMB_FS is not set
878# CONFIG_CIFS is not set
879# CONFIG_NCP_FS is not set
880# CONFIG_CODA_FS is not set
881# CONFIG_AFS_FS is not set
882# CONFIG_9P_FS is not set
883
884#
885# Partition Types
886#
887# CONFIG_PARTITION_ADVANCED is not set
888CONFIG_MSDOS_PARTITION=y
889
890#
891# Native Language Support
892#
893# CONFIG_NLS is not set
894
895#
896# Distributed Lock Manager
897#
898CONFIG_DLM=y
899CONFIG_DLM_TCP=y
900# CONFIG_DLM_SCTP is not set
901# CONFIG_DLM_DEBUG is not set
902
903#
904# Profiling support
905#
906# CONFIG_PROFILING is not set
907
908#
909# Kernel hacking
910#
911CONFIG_TRACE_IRQFLAGS_SUPPORT=y
912# CONFIG_PRINTK_TIME is not set
913CONFIG_ENABLE_MUST_CHECK=y
914# CONFIG_MAGIC_SYSRQ is not set
915# CONFIG_UNUSED_SYMBOLS is not set
916# CONFIG_DEBUG_FS is not set
917# CONFIG_HEADERS_CHECK is not set
918# CONFIG_DEBUG_KERNEL is not set
919CONFIG_LOG_BUF_SHIFT=14
920CONFIG_CROSSCOMPILE=y
921CONFIG_CMDLINE="ip=any"
922CONFIG_SYS_SUPPORTS_KGDB=y
923
924#
925# Security options
926#
927CONFIG_KEYS=y
928CONFIG_KEYS_DEBUG_PROC_KEYS=y
929# CONFIG_SECURITY is not set
930
931#
932# Cryptographic options
933#
934CONFIG_CRYPTO=y
935CONFIG_CRYPTO_ALGAPI=y
936CONFIG_CRYPTO_BLKCIPHER=y
937CONFIG_CRYPTO_HASH=y
938CONFIG_CRYPTO_MANAGER=y
939CONFIG_CRYPTO_HMAC=y
940CONFIG_CRYPTO_XCBC=y
941CONFIG_CRYPTO_NULL=y
942CONFIG_CRYPTO_MD4=y
943CONFIG_CRYPTO_MD5=y
944CONFIG_CRYPTO_SHA1=y
945CONFIG_CRYPTO_SHA256=y
946CONFIG_CRYPTO_SHA512=y
947CONFIG_CRYPTO_WP512=y
948CONFIG_CRYPTO_TGR192=y
949CONFIG_CRYPTO_GF128MUL=y
950CONFIG_CRYPTO_ECB=y
951CONFIG_CRYPTO_CBC=y
952CONFIG_CRYPTO_PCBC=y
953CONFIG_CRYPTO_LRW=y
954CONFIG_CRYPTO_DES=y
955CONFIG_CRYPTO_FCRYPT=y
956CONFIG_CRYPTO_BLOWFISH=y
957CONFIG_CRYPTO_TWOFISH=y
958CONFIG_CRYPTO_TWOFISH_COMMON=y
959CONFIG_CRYPTO_SERPENT=y
960CONFIG_CRYPTO_AES=y
961CONFIG_CRYPTO_CAST5=y
962CONFIG_CRYPTO_CAST6=y
963CONFIG_CRYPTO_TEA=y
964CONFIG_CRYPTO_ARC4=y
965CONFIG_CRYPTO_KHAZAD=y
966CONFIG_CRYPTO_ANUBIS=y
967CONFIG_CRYPTO_DEFLATE=y
968CONFIG_CRYPTO_MICHAEL_MIC=y
969CONFIG_CRYPTO_CRC32C=y
970CONFIG_CRYPTO_CAMELLIA=y
971
972#
973# Hardware crypto devices
974#
975
976#
977# Library routines
978#
979CONFIG_BITREVERSE=y
980# CONFIG_CRC_CCITT is not set
981CONFIG_CRC16=y
982CONFIG_CRC32=y
983CONFIG_LIBCRC32C=y
984CONFIG_ZLIB_INFLATE=y
985CONFIG_ZLIB_DEFLATE=y
986CONFIG_PLIST=y
987CONFIG_HAS_IOMEM=y
988CONFIG_HAS_IOPORT=y
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig
index 37d3bc5fdba3..2fb350432669 100644
--- a/arch/mips/configs/decstation_defconfig
+++ b/arch/mips/configs/decstation_defconfig
@@ -35,7 +35,6 @@ CONFIG_MACH_DECSTATION=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig
index 629737830d29..5467d750b6eb 100644
--- a/arch/mips/configs/e55_defconfig
+++ b/arch/mips/configs/e55_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39CONFIG_MACH_VR41XX=y 38CONFIG_MACH_VR41XX=y
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig
index ec54880a2ec9..d73d965f7615 100644
--- a/arch/mips/configs/emma2rh_defconfig
+++ b/arch/mips/configs/emma2rh_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig
index 801f5ac8b849..17a866057fd4 100644
--- a/arch/mips/configs/excite_defconfig
+++ b/arch/mips/configs/excite_defconfig
@@ -36,7 +36,6 @@ CONFIG_BASLER_EXCITE=y
36# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
37# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_DDB5477 is not set
40# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
41# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
42# CONFIG_QEMU is not set 41# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/fulong_defconfig b/arch/mips/configs/fulong_defconfig
index feacaf073777..4ef39a0527cc 100644
--- a/arch/mips/configs/fulong_defconfig
+++ b/arch/mips/configs/fulong_defconfig
@@ -21,7 +21,6 @@ CONFIG_LEMOTE_FULONG=y
21# CONFIG_MIPS_SIM is not set 21# CONFIG_MIPS_SIM is not set
22# CONFIG_PNX8550_JBS is not set 22# CONFIG_PNX8550_JBS is not set
23# CONFIG_PNX8550_STB810 is not set 23# CONFIG_PNX8550_STB810 is not set
24# CONFIG_DDB5477 is not set
25# CONFIG_MACH_VR41XX is not set 24# CONFIG_MACH_VR41XX is not set
26# CONFIG_PMC_YOSEMITE is not set 25# CONFIG_PMC_YOSEMITE is not set
27# CONFIG_QEMU is not set 26# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index 5d2d29a0e062..934d8a008936 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 82131929cdb4..eb35f7518d06 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig
index 849f9c932b3f..47f49b60c5d6 100644
--- a/arch/mips/configs/ip32_defconfig
+++ b/arch/mips/configs/ip32_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig
index 49487493eb1d..fa655e247ecc 100644
--- a/arch/mips/configs/jazz_defconfig
+++ b/arch/mips/configs/jazz_defconfig
@@ -35,7 +35,6 @@ CONFIG_MACH_JAZZ=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index 1e6d3cb6cde2..95a72d2750ef 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index b17eb6f33724..fbfa5685887c 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -35,7 +35,6 @@ CONFIG_MIPS_MALTA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
index 2d94569f0547..86dcb7464353 100644
--- a/arch/mips/configs/mipssim_defconfig
+++ b/arch/mips/configs/mipssim_defconfig
@@ -35,7 +35,6 @@ CONFIG_MIPS_SIM=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig
index 090eb2fa0564..239810b6c88d 100644
--- a/arch/mips/configs/mpc30x_defconfig
+++ b/arch/mips/configs/mpc30x_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39CONFIG_MACH_VR41XX=y 38CONFIG_MACH_VR41XX=y
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig
index 7296f0c8b1ec..69278999c9a2 100644
--- a/arch/mips/configs/msp71xx_defconfig
+++ b/arch/mips/configs/msp71xx_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40CONFIG_PMC_MSP=y 39CONFIG_PMC_MSP=y
41# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index cb4ad4f87e89..d53fa8f8e099 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -36,7 +36,6 @@ CONFIG_MIPS_PB1100=y
36# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
37# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_DDB5477 is not set
40# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
41# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
42# CONFIG_QEMU is not set 41# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index 0d2c945ac81e..dc4aa0c66847 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -36,7 +36,6 @@ CONFIG_MIPS_PB1500=y
36# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
37# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_DDB5477 is not set
40# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
41# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
42# CONFIG_QEMU is not set 41# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 2d7df49d191a..24428e13002b 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -36,7 +36,6 @@ CONFIG_MIPS_PB1550=y
36# CONFIG_MIPS_XXS1500 is not set 36# CONFIG_MIPS_XXS1500 is not set
37# CONFIG_PNX8550_JBS is not set 37# CONFIG_PNX8550_JBS is not set
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_DDB5477 is not set
40# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
41# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
42# CONFIG_QEMU is not set 41# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index 18996ed7be25..f6906b069e04 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36CONFIG_PNX8550_JBS=y 36CONFIG_PNX8550_JBS=y
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig
index 9bbc09e5b86d..b741f81696fb 100644
--- a/arch/mips/configs/pnx8550-stb810_defconfig
+++ b/arch/mips/configs/pnx8550-stb810_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37CONFIG_PNX8550_STB810=y 37CONFIG_PNX8550_STB810=y
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig
index 5df7cc3ba001..b3caf5125c15 100644
--- a/arch/mips/configs/qemu_defconfig
+++ b/arch/mips/configs/qemu_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41CONFIG_QEMU=y 40CONFIG_QEMU=y
diff --git a/arch/mips/configs/rbhma4200_defconfig b/arch/mips/configs/rbhma4200_defconfig
index 3da990353295..9913980add21 100644
--- a/arch/mips/configs/rbhma4200_defconfig
+++ b/arch/mips/configs/rbhma4200_defconfig
@@ -33,7 +33,6 @@ CONFIG_MIPS=y
33# CONFIG_MIPS_XXS1500 is not set 33# CONFIG_MIPS_XXS1500 is not set
34# CONFIG_PNX8550_JBS is not set 34# CONFIG_PNX8550_JBS is not set
35# CONFIG_PNX8550_STB810 is not set 35# CONFIG_PNX8550_STB810 is not set
36# CONFIG_DDB5477 is not set
37# CONFIG_MACH_VR41XX is not set 36# CONFIG_MACH_VR41XX is not set
38# CONFIG_PMC_YOSEMITE is not set 37# CONFIG_PMC_YOSEMITE is not set
39# CONFIG_QEMU is not set 38# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig
index badf679e3f52..40453cd7c70e 100644
--- a/arch/mips/configs/rbhma4500_defconfig
+++ b/arch/mips/configs/rbhma4500_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_SIM is not set 22# CONFIG_MIPS_SIM is not set
23# CONFIG_PNX8550_JBS is not set 23# CONFIG_PNX8550_JBS is not set
24# CONFIG_PNX8550_STB810 is not set 24# CONFIG_PNX8550_STB810 is not set
25# CONFIG_DDB5477 is not set
26# CONFIG_MACH_VR41XX is not set 25# CONFIG_MACH_VR41XX is not set
27# CONFIG_PMC_MSP is not set 26# CONFIG_PMC_MSP is not set
28# CONFIG_PMC_YOSEMITE is not set 27# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index 091f41d13ddd..fc388118b114 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 21cc7eaae5c5..e72fdf36b3fe 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig
index 1f0122877731..2b6282d132a8 100644
--- a/arch/mips/configs/sead_defconfig
+++ b/arch/mips/configs/sead_defconfig
@@ -35,7 +35,6 @@ CONFIG_MIPS_SEAD=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig
index 9b2fe199db90..e9f2cef4c716 100644
--- a/arch/mips/configs/tb0219_defconfig
+++ b/arch/mips/configs/tb0219_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39CONFIG_MACH_VR41XX=y 38CONFIG_MACH_VR41XX=y
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig
index 3e9f41d98ad3..aea67568842a 100644
--- a/arch/mips/configs/tb0226_defconfig
+++ b/arch/mips/configs/tb0226_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39CONFIG_MACH_VR41XX=y 38CONFIG_MACH_VR41XX=y
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig
index 94511f9dc8f3..66383ecff200 100644
--- a/arch/mips/configs/tb0287_defconfig
+++ b/arch/mips/configs/tb0287_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39CONFIG_MACH_VR41XX=y 38CONFIG_MACH_VR41XX=y
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig
index 0fcb6e52c30d..db6fd4f15719 100644
--- a/arch/mips/configs/workpad_defconfig
+++ b/arch/mips/configs/workpad_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39CONFIG_MACH_VR41XX=y 38CONFIG_MACH_VR41XX=y
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig
index f58418c5f1e7..7e410e10fed7 100644
--- a/arch/mips/configs/wrppmc_defconfig
+++ b/arch/mips/configs/wrppmc_defconfig
@@ -35,7 +35,6 @@ CONFIG_WR_PPMC=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index 850d4e8570cb..acaf0e21bb00 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40CONFIG_PMC_YOSEMITE=y 39CONFIG_PMC_YOSEMITE=y
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/ddb5xxx/Kconfig b/arch/mips/ddb5xxx/Kconfig
deleted file mode 100644
index e9b5de49f4c2..000000000000
--- a/arch/mips/ddb5xxx/Kconfig
+++ /dev/null
@@ -1,4 +0,0 @@
1config DDB5477_BUS_FREQUENCY
2 int "bus frequency (in kHZ, 0 for auto-detect)"
3 depends on DDB5477
4 default 0
diff --git a/arch/mips/ddb5xxx/common/Makefile b/arch/mips/ddb5xxx/common/Makefile
deleted file mode 100644
index 2a6a4e91991c..000000000000
--- a/arch/mips/ddb5xxx/common/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# Makefile for the common code of NEC DDB-Vrc5xxx board
3#
4
5obj-y += nile4.o prom.o rtc_ds1386.o
6
7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/ddb5xxx/common/nile4.c b/arch/mips/ddb5xxx/common/nile4.c
deleted file mode 100644
index 7ec7d903ba97..000000000000
--- a/arch/mips/ddb5xxx/common/nile4.c
+++ /dev/null
@@ -1,130 +0,0 @@
1/*
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: jsun@mvista.com or jsun@junsun.net
5 *
6 * arch/mips/ddb5xxx/common/nile4.c
7 * misc low-level routines for vrc-5xxx controllers.
8 *
9 * derived from original code by Geert Uytterhoeven <geert@sonycom.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#include <linux/types.h>
17#include <linux/kernel.h>
18
19#include <asm/ddb5xxx/ddb5xxx.h>
20
21u32
22ddb_calc_pdar(u32 phys, u32 size, int width,
23 int on_memory_bus, int pci_visible)
24{
25 u32 maskbits;
26 u32 widthbits;
27
28 switch (size) {
29#if 0 /* We don't support 4 GB yet */
30 case 0x100000000: /* 4 GB */
31 maskbits = 4;
32 break;
33#endif
34 case 0x80000000: /* 2 GB */
35 maskbits = 5;
36 break;
37 case 0x40000000: /* 1 GB */
38 maskbits = 6;
39 break;
40 case 0x20000000: /* 512 MB */
41 maskbits = 7;
42 break;
43 case 0x10000000: /* 256 MB */
44 maskbits = 8;
45 break;
46 case 0x08000000: /* 128 MB */
47 maskbits = 9;
48 break;
49 case 0x04000000: /* 64 MB */
50 maskbits = 10;
51 break;
52 case 0x02000000: /* 32 MB */
53 maskbits = 11;
54 break;
55 case 0x01000000: /* 16 MB */
56 maskbits = 12;
57 break;
58 case 0x00800000: /* 8 MB */
59 maskbits = 13;
60 break;
61 case 0x00400000: /* 4 MB */
62 maskbits = 14;
63 break;
64 case 0x00200000: /* 2 MB */
65 maskbits = 15;
66 break;
67 case 0: /* OFF */
68 maskbits = 0;
69 break;
70 default:
71 panic("nile4_set_pdar: unsupported size %p", (void *) size);
72 }
73 switch (width) {
74 case 8:
75 widthbits = 0;
76 break;
77 case 16:
78 widthbits = 1;
79 break;
80 case 32:
81 widthbits = 2;
82 break;
83 case 64:
84 widthbits = 3;
85 break;
86 default:
87 panic("nile4_set_pdar: unsupported width %d", width);
88 }
89
90 return maskbits | (on_memory_bus ? 0x10 : 0) |
91 (pci_visible ? 0x20 : 0) | (widthbits << 6) |
92 (phys & 0xffe00000);
93}
94
95void
96ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width,
97 int on_memory_bus, int pci_visible)
98{
99 u32 temp= ddb_calc_pdar(phys, size, width, on_memory_bus, pci_visible);
100 ddb_out32(pdar, temp);
101 ddb_out32(pdar + 4, 0);
102
103 /*
104 * When programming a PDAR, the register should be read immediately
105 * after writing it. This ensures that address decoders are properly
106 * configured.
107 * [jsun] is this really necessary?
108 */
109 ddb_in32(pdar);
110 ddb_in32(pdar + 4);
111}
112
113/*
114 * routines that mess with PCIINITx registers
115 */
116
117void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options)
118{
119 switch (type) {
120 case DDB_PCICMD_IACK: /* PCI Interrupt Acknowledge */
121 case DDB_PCICMD_IO: /* PCI I/O Space */
122 case DDB_PCICMD_MEM: /* PCI Memory Space */
123 case DDB_PCICMD_CFG: /* PCI Configuration Space */
124 break;
125 default:
126 panic("nile4_set_pmr: invalid type %d", type);
127 }
128 ddb_out32(pmr, (type << 1) | (addr & 0xffe00000) | options );
129 ddb_out32(pmr + 4, 0);
130}
diff --git a/arch/mips/ddb5xxx/common/prom.c b/arch/mips/ddb5xxx/common/prom.c
deleted file mode 100644
index 54a857b5e3ba..000000000000
--- a/arch/mips/ddb5xxx/common/prom.c
+++ /dev/null
@@ -1,132 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: jsun@mvista.com or jsun@junsun.net
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10#include <linux/init.h>
11#include <linux/mm.h>
12#include <linux/sched.h>
13#include <linux/bootmem.h>
14
15#include <asm/addrspace.h>
16#include <asm/bootinfo.h>
17#include <asm/ddb5xxx/ddb5xxx.h>
18#include <asm/debug.h>
19
20const char *get_system_type(void)
21{
22 switch (mips_machtype) {
23 case MACH_NEC_DDB5477: return "NEC DDB Vrc-5477";
24 case MACH_NEC_ROCKHOPPER: return "NEC Rockhopper";
25 case MACH_NEC_ROCKHOPPERII: return "NEC RockhopperII";
26 default: return "Unknown NEC board";
27 }
28}
29
30#if defined(CONFIG_DDB5477)
31void ddb5477_runtime_detection(void);
32#endif
33
34/* [jsun@junsun.net] PMON passes arguments in C main() style */
35void __init prom_init(void)
36{
37 int argc = fw_arg0;
38 char **arg = (char**) fw_arg1;
39 int i;
40
41 /* if user passes kernel args, ignore the default one */
42 if (argc > 1)
43 arcs_cmdline[0] = '\0';
44
45 /* arg[0] is "g", the rest is boot parameters */
46 for (i = 1; i < argc; i++) {
47 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
48 >= sizeof(arcs_cmdline))
49 break;
50 strcat(arcs_cmdline, arg[i]);
51 strcat(arcs_cmdline, " ");
52 }
53
54 mips_machgroup = MACH_GROUP_NEC_DDB;
55
56#if defined(CONFIG_DDB5477)
57 ddb5477_runtime_detection();
58 add_memory_region(0, board_ram_size, BOOT_MEM_RAM);
59#endif
60}
61
62void __init prom_free_prom_memory(void)
63{
64}
65
66#if defined(CONFIG_DDB5477)
67
68#define DEFAULT_LCS1_BASE 0x19000000
69#define TESTVAL1 'K'
70#define TESTVAL2 'S'
71
72int board_ram_size;
73void ddb5477_runtime_detection(void)
74{
75 volatile char *test_offset;
76 char saved_test_byte;
77
78 /* Determine if this is a DDB5477 board, or a BSB-VR0300
79 base board. We can tell by checking for the location of
80 the NVRAM. It lives at the beginning of LCS1 on the DDB5477,
81 and the beginning of LCS1 on the BSB-VR0300 is flash memory.
82 The first 2K of the NVRAM are reserved, so don't we'll poke
83 around just after that.
84 */
85
86 /* We can only use the PCI bus to distinquish between
87 the Rockhopper and RockhopperII backplanes and this must
88 wait until ddb5477_board_init() in setup.c after the 5477
89 is initialized. So, until then handle
90 both Rockhopper and RockhopperII backplanes as Rockhopper 1
91 */
92
93 test_offset = (char *)KSEG1ADDR(DEFAULT_LCS1_BASE + 0x800);
94 saved_test_byte = *test_offset;
95
96 *test_offset = TESTVAL1;
97 if (*test_offset != TESTVAL1) {
98 /* We couldn't set our test value, so it must not be NVRAM,
99 so it's a BSB_VR0300 */
100 mips_machtype = MACH_NEC_ROCKHOPPER;
101 } else {
102 /* We may have gotten lucky, and the TESTVAL1 was already
103 stored at the test location, so we must check a second
104 test value */
105 *test_offset = TESTVAL2;
106 if (*test_offset != TESTVAL2) {
107 /* OK, we couldn't set this value either, so it must
108 definately be a BSB_VR0300 */
109 mips_machtype = MACH_NEC_ROCKHOPPER;
110 } else {
111 /* We could change the value twice, so it must be
112 NVRAM, so it's a DDB_VRC5477 */
113 mips_machtype = MACH_NEC_DDB5477;
114 }
115 }
116 /* Restore the original byte */
117 *test_offset = saved_test_byte;
118
119 /* before we know a better way, we will trust PMON for getting
120 * RAM size
121 */
122 board_ram_size = 1 << (36 - (ddb_in32(DDB_SDRAM0) & 0xf));
123
124 db_run(printk("DDB run-time detection : %s, %d MB RAM\n",
125 mips_machtype == MACH_NEC_DDB5477 ?
126 "DDB5477" : "Rockhopper",
127 board_ram_size >> 20));
128
129 /* we can't handle ram size > 128 MB */
130 db_assert(board_ram_size <= (128 << 20));
131}
132#endif
diff --git a/arch/mips/ddb5xxx/common/rtc_ds1386.c b/arch/mips/ddb5xxx/common/rtc_ds1386.c
deleted file mode 100644
index 5dc34daa7150..000000000000
--- a/arch/mips/ddb5xxx/common/rtc_ds1386.c
+++ /dev/null
@@ -1,170 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/ddb5xxx/common/rtc_ds1386.c
6 * low-level RTC hookups for s for Dallas 1396 chip.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14
15/*
16 * This file exports a function, rtc_ds1386_init(), which expects an
17 * uncached base address as the argument. It will set the two function
18 * pointers expected by the MIPS generic timer code.
19 */
20
21#include <linux/types.h>
22#include <linux/time.h>
23#include <linux/bcd.h>
24
25#include <asm/time.h>
26#include <asm/addrspace.h>
27
28#include <asm/mc146818rtc.h>
29#include <asm/debug.h>
30
31#define EPOCH 2000
32
33#define READ_RTC(x) *(volatile unsigned char*)(rtc_base+x)
34#define WRITE_RTC(x, y) *(volatile unsigned char*)(rtc_base+x) = y
35
36static unsigned long rtc_base;
37
38static unsigned long
39rtc_ds1386_get_time(void)
40{
41 u8 byte;
42 u8 temp;
43 unsigned int year, month, day, hour, minute, second;
44 unsigned long flags;
45
46 spin_lock_irqsave(&rtc_lock, flags);
47 /* let us freeze external registers */
48 byte = READ_RTC(0xB);
49 byte &= 0x3f;
50 WRITE_RTC(0xB, byte);
51
52 /* read time data */
53 year = BCD2BIN(READ_RTC(0xA)) + EPOCH;
54 month = BCD2BIN(READ_RTC(0x9) & 0x1f);
55 day = BCD2BIN(READ_RTC(0x8));
56 minute = BCD2BIN(READ_RTC(0x2));
57 second = BCD2BIN(READ_RTC(0x1));
58
59 /* hour is special - deal with it later */
60 temp = READ_RTC(0x4);
61
62 /* enable time transfer */
63 byte |= 0x80;
64 WRITE_RTC(0xB, byte);
65 spin_unlock_irqrestore(&rtc_lock, flags);
66
67 /* calc hour */
68 if (temp & 0x40) {
69 /* 12 hour format */
70 hour = BCD2BIN(temp & 0x1f);
71 if (temp & 0x20) hour += 12; /* PM */
72 } else {
73 /* 24 hour format */
74 hour = BCD2BIN(temp & 0x3f);
75 }
76
77 return mktime(year, month, day, hour, minute, second);
78}
79
80static int
81rtc_ds1386_set_time(unsigned long t)
82{
83 struct rtc_time tm;
84 u8 byte;
85 u8 temp;
86 u8 year, month, day, hour, minute, second;
87 unsigned long flags;
88
89 spin_lock_irqsave(&rtc_lock, flags);
90 /* let us freeze external registers */
91 byte = READ_RTC(0xB);
92 byte &= 0x3f;
93 WRITE_RTC(0xB, byte);
94
95 /* convert */
96 to_tm(t, &tm);
97
98
99 /* check each field one by one */
100 year = BIN2BCD(tm.tm_year - EPOCH);
101 if (year != READ_RTC(0xA)) {
102 WRITE_RTC(0xA, year);
103 }
104
105 temp = READ_RTC(0x9);
106 month = BIN2BCD(tm.tm_mon+1); /* tm_mon starts from 0 to 11 */
107 if (month != (temp & 0x1f)) {
108 WRITE_RTC( 0x9,
109 (month & 0x1f) | (temp & ~0x1f) );
110 }
111
112 day = BIN2BCD(tm.tm_mday);
113 if (day != READ_RTC(0x8)) {
114 WRITE_RTC(0x8, day);
115 }
116
117 temp = READ_RTC(0x4);
118 if (temp & 0x40) {
119 /* 12 hour format */
120 hour = 0x40;
121 if (tm.tm_hour > 12) {
122 hour |= 0x20 | (BIN2BCD(hour-12) & 0x1f);
123 } else {
124 hour |= BIN2BCD(tm.tm_hour);
125 }
126 } else {
127 /* 24 hour format */
128 hour = BIN2BCD(tm.tm_hour) & 0x3f;
129 }
130 if (hour != temp) WRITE_RTC(0x4, hour);
131
132 minute = BIN2BCD(tm.tm_min);
133 if (minute != READ_RTC(0x2)) {
134 WRITE_RTC(0x2, minute);
135 }
136
137 second = BIN2BCD(tm.tm_sec);
138 if (second != READ_RTC(0x1)) {
139 WRITE_RTC(0x1, second);
140 }
141 spin_unlock_irqrestore(&rtc_lock, flags);
142
143 return 0;
144}
145
146void
147rtc_ds1386_init(unsigned long base)
148{
149 unsigned char byte;
150
151 /* remember the base */
152 rtc_base = base;
153 db_assert((rtc_base & 0xe0000000) == KSEG1);
154
155 /* turn on RTC if it is not on */
156 byte = READ_RTC(0x9);
157 if (byte & 0x80) {
158 byte &= 0x7f;
159 WRITE_RTC(0x9, byte);
160 }
161
162 /* enable time transfer */
163 byte = READ_RTC(0xB);
164 byte |= 0x80;
165 WRITE_RTC(0xB, byte);
166
167 /* set the function pointers */
168 rtc_mips_get_time = rtc_ds1386_get_time;
169 rtc_mips_set_time = rtc_ds1386_set_time;
170}
diff --git a/arch/mips/ddb5xxx/ddb5477/Makefile b/arch/mips/ddb5xxx/ddb5477/Makefile
deleted file mode 100644
index 520094405905..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
1#
2# Makefile for NEC DDB-Vrc5477 board
3#
4
5obj-y += ddb5477-platform.o irq.o irq_5477.o setup.o \
6 lcd44780.o
7
8obj-$(CONFIG_RUNTIME_DEBUG) += debug.o
9obj-$(CONFIG_KGDB) += kgdb_io.o
10
11EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c b/arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c
deleted file mode 100644
index c16020ad54c2..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 */
8#include <linux/init.h>
9#include <linux/module.h>
10#include <linux/serial_8250.h>
11
12#include <asm/ddb5xxx/ddb5477.h>
13
14#define DDB_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
15
16#define DDB5477_PORT(base, int) \
17{ \
18 .mapbase = base, \
19 .irq = int, \
20 .uartclk = 1843200, \
21 .iotype = UPIO_MEM, \
22 .flags = DDB_UART_FLAGS, \
23 .regshift = 3, \
24}
25
26static struct plat_serial8250_port uart8250_data[] = {
27 DDB5477_PORT(0xbfa04200, VRC5477_IRQ_UART0),
28 DDB5477_PORT(0xbfa04240, VRC5477_IRQ_UART1),
29 { },
30};
31
32static struct platform_device uart8250_device = {
33 .name = "serial8250",
34 .id = PLAT8250_DEV_PLATFORM,
35 .dev = {
36 .platform_data = uart8250_data,
37 },
38};
39
40static int __init uart8250_init(void)
41{
42 return platform_device_register(&uart8250_device);
43}
44
45module_init(uart8250_init);
46
47MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
48MODULE_LICENSE("GPL");
49MODULE_DESCRIPTION("8250 UART probe driver for the NEC DDB5477");
diff --git a/arch/mips/ddb5xxx/ddb5477/debug.c b/arch/mips/ddb5xxx/ddb5477/debug.c
deleted file mode 100644
index 68919d5f8ffd..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/debug.c
+++ /dev/null
@@ -1,160 +0,0 @@
1/***********************************************************************
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: jsun@mvista.com or jsun@junsun.net
5 *
6 * arch/mips/ddb5xxx/ddb5477/debug.c
7 * vrc5477 specific debug routines.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 ***********************************************************************
15 */
16
17#include <linux/kernel.h>
18
19#include <asm/mipsregs.h>
20#include <asm/ddb5xxx/ddb5xxx.h>
21
22typedef struct {
23 const char *regname;
24 unsigned regaddr;
25} Register;
26
27void jsun_show_regs(char *name, Register *regs)
28{
29 int i;
30
31 printk("\nshow regs: %s\n", name);
32 for(i=0;regs[i].regname!= NULL; i++) {
33 printk("%-16s= %08x\t\t(@%08x)\n",
34 regs[i].regname,
35 *(unsigned *)(regs[i].regaddr),
36 regs[i].regaddr);
37 }
38}
39
40static Register int_regs[] = {
41 {"DDB_INTCTRL0", DDB_BASE + DDB_INTCTRL0},
42 {"DDB_INTCTRL1", DDB_BASE + DDB_INTCTRL1},
43 {"DDB_INTCTRL2", DDB_BASE + DDB_INTCTRL2},
44 {"DDB_INTCTRL3", DDB_BASE + DDB_INTCTRL3},
45 {"DDB_INT0STAT", DDB_BASE + DDB_INT0STAT},
46 {"DDB_INT1STAT", DDB_BASE + DDB_INT1STAT},
47 {"DDB_INT2STAT", DDB_BASE + DDB_INT2STAT},
48 {"DDB_INT3STAT", DDB_BASE + DDB_INT3STAT},
49 {"DDB_INT4STAT", DDB_BASE + DDB_INT4STAT},
50 {"DDB_NMISTAT", DDB_BASE + DDB_NMISTAT},
51 {"DDB_INTPPES0", DDB_BASE + DDB_INTPPES0},
52 {"DDB_INTPPES1", DDB_BASE + DDB_INTPPES1},
53 {NULL, 0x0}
54};
55
56void vrc5477_show_int_regs()
57{
58 jsun_show_regs("interrupt registers", int_regs);
59 printk("CPU CAUSE = %08x\n", read_c0_cause());
60 printk("CPU STATUS = %08x\n", read_c0_status());
61}
62static Register pdar_regs[] = {
63 {"DDB_SDRAM0", DDB_BASE + DDB_SDRAM0},
64 {"DDB_SDRAM1", DDB_BASE + DDB_SDRAM1},
65 {"DDB_LCS0", DDB_BASE + DDB_LCS0},
66 {"DDB_LCS1", DDB_BASE + DDB_LCS1},
67 {"DDB_LCS2", DDB_BASE + DDB_LCS2},
68 {"DDB_INTCS", DDB_BASE + DDB_INTCS},
69 {"DDB_BOOTCS", DDB_BASE + DDB_BOOTCS},
70 {"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
71 {"DDB_PCIW1", DDB_BASE + DDB_PCIW1},
72 {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0},
73 {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1},
74 {NULL, 0x0}
75};
76void vrc5477_show_pdar_regs(void)
77{
78 jsun_show_regs("PDAR regs", pdar_regs);
79}
80
81static Register bar_regs[] = {
82 {"DDB_BARC0", DDB_BASE + DDB_BARC0},
83 {"DDB_BARM010", DDB_BASE + DDB_BARM010},
84 {"DDB_BARM230", DDB_BASE + DDB_BARM230},
85 {"DDB_BAR00", DDB_BASE + DDB_BAR00},
86 {"DDB_BAR10", DDB_BASE + DDB_BAR10},
87 {"DDB_BAR20", DDB_BASE + DDB_BAR20},
88 {"DDB_BAR30", DDB_BASE + DDB_BAR30},
89 {"DDB_BAR40", DDB_BASE + DDB_BAR40},
90 {"DDB_BAR50", DDB_BASE + DDB_BAR50},
91 {"DDB_BARB0", DDB_BASE + DDB_BARB0},
92 {"DDB_BARC1", DDB_BASE + DDB_BARC1},
93 {"DDB_BARM011", DDB_BASE + DDB_BARM011},
94 {"DDB_BARM231", DDB_BASE + DDB_BARM231},
95 {"DDB_BAR01", DDB_BASE + DDB_BAR01},
96 {"DDB_BAR11", DDB_BASE + DDB_BAR11},
97 {"DDB_BAR21", DDB_BASE + DDB_BAR21},
98 {"DDB_BAR31", DDB_BASE + DDB_BAR31},
99 {"DDB_BAR41", DDB_BASE + DDB_BAR41},
100 {"DDB_BAR51", DDB_BASE + DDB_BAR51},
101 {"DDB_BARB1", DDB_BASE + DDB_BARB1},
102 {NULL, 0x0}
103};
104void vrc5477_show_bar_regs(void)
105{
106 jsun_show_regs("BAR regs", bar_regs);
107}
108
109static Register pci_regs[] = {
110 {"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
111 {"DDB_PCIW1", DDB_BASE + DDB_PCIW1},
112 {"DDB_PCIINIT00", DDB_BASE + DDB_PCIINIT00},
113 {"DDB_PCIINIT10", DDB_BASE + DDB_PCIINIT10},
114 {"DDB_PCICTL0_L", DDB_BASE + DDB_PCICTL0_L},
115 {"DDB_PCICTL0_H", DDB_BASE + DDB_PCICTL0_H},
116 {"DDB_PCIARB0_L", DDB_BASE + DDB_PCIARB0_L},
117 {"DDB_PCIARB0_H", DDB_BASE + DDB_PCIARB0_H},
118 {"DDB_PCISWP0", DDB_BASE + DDB_PCISWP0},
119 {"DDB_PCIERR0", DDB_BASE + DDB_PCIERR0},
120 {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0},
121 {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1},
122 {"DDB_PCIINIT01", DDB_BASE + DDB_PCIINIT01},
123 {"DDB_PCIINIT11", DDB_BASE + DDB_PCIINIT11},
124 {"DDB_PCICTL1_L", DDB_BASE + DDB_PCICTL1_L},
125 {"DDB_PCICTL1_H", DDB_BASE + DDB_PCICTL1_H},
126 {"DDB_PCIARB1_L", DDB_BASE + DDB_PCIARB1_L},
127 {"DDB_PCIARB1_H", DDB_BASE + DDB_PCIARB1_H},
128 {"DDB_PCISWP1", DDB_BASE + DDB_PCISWP1},
129 {"DDB_PCIERR1", DDB_BASE + DDB_PCIERR1},
130 {NULL, 0x0}
131};
132void vrc5477_show_pci_regs(void)
133{
134 jsun_show_regs("PCI regs", pci_regs);
135}
136
137static Register lb_regs[] = {
138 {"DDB_LCNFG", DDB_BASE + DDB_LCNFG},
139 {"DDB_LCST0", DDB_BASE + DDB_LCST0},
140 {"DDB_LCST1", DDB_BASE + DDB_LCST1},
141 {"DDB_LCST2", DDB_BASE + DDB_LCST2},
142 {"DDB_ERRADR", DDB_BASE + DDB_ERRADR},
143 {"DDB_ERRCS", DDB_BASE + DDB_ERRCS},
144 {"DDB_BTM", DDB_BASE + DDB_BTM},
145 {"DDB_BCST", DDB_BASE + DDB_BCST},
146 {NULL, 0x0}
147};
148void vrc5477_show_lb_regs(void)
149{
150 jsun_show_regs("Local Bus regs", lb_regs);
151}
152
153void vrc5477_show_all_regs(void)
154{
155 vrc5477_show_pdar_regs();
156 vrc5477_show_pci_regs();
157 vrc5477_show_bar_regs();
158 vrc5477_show_int_regs();
159 vrc5477_show_lb_regs();
160}
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c
deleted file mode 100644
index faa4a506bf82..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/irq.c
+++ /dev/null
@@ -1,209 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/ddb5xxx/ddb5477/irq.c
6 * The irq setup and misc routines for DDB5476.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/types.h>
17#include <linux/ptrace.h>
18
19#include <asm/i8259.h>
20#include <asm/irq_cpu.h>
21#include <asm/system.h>
22#include <asm/mipsregs.h>
23#include <asm/debug.h>
24#include <asm/addrspace.h>
25#include <asm/bootinfo.h>
26
27#include <asm/ddb5xxx/ddb5xxx.h>
28
29
30/*
31 * IRQ mapping
32 *
33 * 0-7: 8 CPU interrupts
34 * 0 - software interrupt 0
35 * 1 - software interrupt 1
36 * 2 - most Vrc5477 interrupts are routed to this pin
37 * 3 - (optional) some other interrupts routed to this pin for debugg
38 * 4 - not used
39 * 5 - not used
40 * 6 - not used
41 * 7 - cpu timer (used by default)
42 *
43 * 8-39: 32 Vrc5477 interrupt sources
44 * (refer to the Vrc5477 manual)
45 */
46
47#define PCI0 DDB_INTPPES0
48#define PCI1 DDB_INTPPES1
49
50#define ACTIVE_LOW 1
51#define ACTIVE_HIGH 0
52
53#define LEVEL_SENSE 2
54#define EDGE_TRIGGER 0
55
56#define INTA 0
57#define INTB 1
58#define INTC 2
59#define INTD 3
60#define INTE 4
61
62static inline void
63set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
64{
65 u32 reg_value;
66 u32 reg_bitmask;
67
68 reg_value = ddb_in32(pci);
69 reg_bitmask = 0x3 << (intn * 2);
70
71 reg_value &= ~reg_bitmask;
72 reg_value |= (active | trigger) << (intn * 2);
73 ddb_out32(pci, reg_value);
74}
75
76extern void vrc5477_irq_init(u32 base);
77static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
78
79void __init arch_init_irq(void)
80{
81 /* by default, we disable all interrupts and route all vrc5477
82 * interrupts to pin 0 (irq 2) */
83 ddb_out32(DDB_INTCTRL0, 0);
84 ddb_out32(DDB_INTCTRL1, 0);
85 ddb_out32(DDB_INTCTRL2, 0);
86 ddb_out32(DDB_INTCTRL3, 0);
87
88 clear_c0_status(0xff00);
89 set_c0_status(0x0400);
90
91 /* setup PCI interrupt attributes */
92 set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
93 set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
94 if (mips_machtype == MACH_NEC_ROCKHOPPERII)
95 set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE);
96 else
97 set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
98 set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE);
99 set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE);
100
101 set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE);
102 set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE);
103 set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE);
104 set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE);
105 set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE);
106
107 /*
108 * for debugging purpose, we enable several error interrupts
109 * and route them to pin 1. (IP3)
110 */
111 /* cpu parity check - 0 */
112 ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0);
113 /* cpu no-target decode - 1 */
114 ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1);
115 /* local bus read time-out - 7 */
116 ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7);
117 /* PCI SERR# - 14 */
118 ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14);
119 /* PCI internal error - 15 */
120 ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15);
121 /* IOPCI SERR# - 30 */
122 ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30);
123 /* IOPCI internal error - 31 */
124 ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31);
125
126 /* init all controllers */
127 init_i8259_irqs();
128 mips_cpu_irq_init();
129 vrc5477_irq_init(VRC5477_IRQ_BASE);
130
131
132 /* setup cascade interrupts */
133 setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade);
134 setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
135}
136
137u8 i8259_interrupt_ack(void)
138{
139 u8 irq;
140 u32 reg;
141
142 /* Set window 0 for interrupt acknowledge */
143 reg = ddb_in32(DDB_PCIINIT10);
144
145 ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
146 irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
147 ddb_out32(DDB_PCIINIT10, reg);
148
149 return irq;
150}
151/*
152 * the first level int-handler will jump here if it is a vrc5477 irq
153 */
154#define NUM_5477_IRQS 32
155static void vrc5477_irq_dispatch(void)
156{
157 u32 intStatus;
158 u32 bitmask;
159 u32 i;
160
161 db_assert(ddb_in32(DDB_INT2STAT) == 0);
162 db_assert(ddb_in32(DDB_INT3STAT) == 0);
163 db_assert(ddb_in32(DDB_INT4STAT) == 0);
164 db_assert(ddb_in32(DDB_NMISTAT) == 0);
165
166 if (ddb_in32(DDB_INT1STAT) != 0) {
167#if defined(CONFIG_RUNTIME_DEBUG)
168 vrc5477_show_int_regs();
169#endif
170 panic("error interrupt has happened.");
171 }
172
173 intStatus = ddb_in32(DDB_INT0STAT);
174
175 if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
176 /* check for i8259 interrupts */
177 if (intStatus & (1 << VRC5477_I8259_CASCADE)) {
178 int i8259_irq = i8259_interrupt_ack();
179 do_IRQ(i8259_irq);
180 return;
181 }
182 }
183
184 for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) {
185 /* do we need to "and" with the int mask? */
186 if (intStatus & bitmask) {
187 do_IRQ(VRC5477_IRQ_BASE + i);
188 return;
189 }
190 }
191}
192
193#define VR5477INTS (STATUSF_IP2|STATUSF_IP3|STATUSF_IP4|STATUSF_IP5|STATUSF_IP6)
194
195asmlinkage void plat_irq_dispatch(void)
196{
197 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
198
199 if (pending & STATUSF_IP7)
200 do_IRQ(CPU_IRQ_BASE + 7);
201 else if (pending & VR5477INTS)
202 vrc5477_irq_dispatch();
203 else if (pending & STATUSF_IP0)
204 do_IRQ(CPU_IRQ_BASE);
205 else if (pending & STATUSF_IP1)
206 do_IRQ(CPU_IRQ_BASE + 1);
207 else
208 spurious_interrupt();
209}
diff --git a/arch/mips/ddb5xxx/ddb5477/irq_5477.c b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
deleted file mode 100644
index 98c3b15eb369..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/irq_5477.c
+++ /dev/null
@@ -1,154 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/ddb5xxx/ddb5477/irq_5477.c
6 * This file defines the irq handler for Vrc5477.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15/*
16 * Vrc5477 defines 32 IRQs.
17 *
18 * This file exports one function:
19 * vrc5477_irq_init(u32 irq_base);
20 */
21
22#include <linux/interrupt.h>
23#include <linux/types.h>
24#include <linux/ptrace.h>
25
26#include <asm/debug.h>
27
28#include <asm/ddb5xxx/ddb5xxx.h>
29
30/* number of total irqs supported by Vrc5477 */
31#define NUM_5477_IRQ 32
32
33static int vrc5477_irq_base = -1;
34
35
36static void
37vrc5477_irq_enable(unsigned int irq)
38{
39 db_assert(vrc5477_irq_base != -1);
40 db_assert(irq >= vrc5477_irq_base);
41 db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
42
43 ll_vrc5477_irq_enable(irq - vrc5477_irq_base);
44}
45
46static void
47vrc5477_irq_disable(unsigned int irq)
48{
49 db_assert(vrc5477_irq_base != -1);
50 db_assert(irq >= vrc5477_irq_base);
51 db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
52
53 ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
54}
55
56static void
57vrc5477_irq_ack(unsigned int irq)
58{
59 db_assert(vrc5477_irq_base != -1);
60 db_assert(irq >= vrc5477_irq_base);
61 db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
62
63 /* clear the interrupt bit */
64 /* some irqs require the driver to clear the sources */
65 ddb_out32(DDB_INTCLR32, 1 << (irq - vrc5477_irq_base));
66
67 /* disable interrupt - some handler will re-enable the irq
68 * and if the interrupt is leveled, we will have infinite loop
69 */
70 ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
71}
72
73static void
74vrc5477_irq_end(unsigned int irq)
75{
76 db_assert(vrc5477_irq_base != -1);
77 db_assert(irq >= vrc5477_irq_base);
78 db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
79
80 if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
81 ll_vrc5477_irq_enable( irq - vrc5477_irq_base);
82}
83
84struct irq_chip vrc5477_irq_controller = {
85 .name = "vrc5477_irq",
86 .ack = vrc5477_irq_ack,
87 .mask = vrc5477_irq_disable,
88 .mask_ack = vrc5477_irq_ack,
89 .unmask = vrc5477_irq_enable,
90 .end = vrc5477_irq_end
91};
92
93void __init vrc5477_irq_init(u32 irq_base)
94{
95 u32 i;
96
97 for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++)
98 set_irq_chip(i, &vrc5477_irq_controller);
99
100 vrc5477_irq_base = irq_base;
101}
102
103void ll_vrc5477_irq_route(int vrc5477_irq, int ip)
104{
105 u32 reg_value;
106 u32 reg_bitmask;
107 u32 reg_index;
108
109 db_assert(vrc5477_irq >= 0);
110 db_assert(vrc5477_irq < NUM_5477_IRQ);
111 db_assert(ip >= 0);
112 db_assert((ip < 5) || (ip == 6));
113
114 reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
115 reg_value = ddb_in32(reg_index);
116 reg_bitmask = 7 << (vrc5477_irq % 8 * 4);
117 reg_value &= ~reg_bitmask;
118 reg_value |= ip << (vrc5477_irq % 8 * 4);
119 ddb_out32(reg_index, reg_value);
120}
121
122void ll_vrc5477_irq_enable(int vrc5477_irq)
123{
124 u32 reg_value;
125 u32 reg_bitmask;
126 u32 reg_index;
127
128 db_assert(vrc5477_irq >= 0);
129 db_assert(vrc5477_irq < NUM_5477_IRQ);
130
131 reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
132 reg_value = ddb_in32(reg_index);
133 reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
134 db_assert((reg_value & reg_bitmask) == 0);
135 ddb_out32(reg_index, reg_value | reg_bitmask);
136}
137
138void ll_vrc5477_irq_disable(int vrc5477_irq)
139{
140 u32 reg_value;
141 u32 reg_bitmask;
142 u32 reg_index;
143
144 db_assert(vrc5477_irq >= 0);
145 db_assert(vrc5477_irq < NUM_5477_IRQ);
146
147 reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
148 reg_value = ddb_in32(reg_index);
149 reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
150
151 /* we assert that the interrupt is enabled (perhaps over-zealous) */
152 db_assert( (reg_value & reg_bitmask) != 0);
153 ddb_out32(reg_index, reg_value & ~reg_bitmask);
154}
diff --git a/arch/mips/ddb5xxx/ddb5477/kgdb_io.c b/arch/mips/ddb5xxx/ddb5477/kgdb_io.c
deleted file mode 100644
index 385bbdb10170..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/kgdb_io.c
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * kgdb io functions for DDB5477. We use the second serial port (upper one).
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14/* ======================= CONFIG ======================== */
15
16/* [jsun] we use the second serial port for kdb */
17#define BASE 0xbfa04240
18#define MAX_BAUD 115200
19
20/* distance in bytes between two serial registers */
21#define REG_OFFSET 8
22
23/*
24 * 0 - kgdb does serial init
25 * 1 - kgdb skip serial init
26 */
27static int remoteDebugInitialized = 0;
28
29/*
30 * the default baud rate *if* kgdb does serial init
31 */
32#define BAUD_DEFAULT UART16550_BAUD_38400
33
34/* ======================= END OF CONFIG ======================== */
35
36typedef unsigned char uint8;
37typedef unsigned int uint32;
38
39#define UART16550_BAUD_2400 2400
40#define UART16550_BAUD_4800 4800
41#define UART16550_BAUD_9600 9600
42#define UART16550_BAUD_19200 19200
43#define UART16550_BAUD_38400 38400
44#define UART16550_BAUD_57600 57600
45#define UART16550_BAUD_115200 115200
46
47#define UART16550_PARITY_NONE 0
48#define UART16550_PARITY_ODD 0x08
49#define UART16550_PARITY_EVEN 0x18
50#define UART16550_PARITY_MARK 0x28
51#define UART16550_PARITY_SPACE 0x38
52
53#define UART16550_DATA_5BIT 0x0
54#define UART16550_DATA_6BIT 0x1
55#define UART16550_DATA_7BIT 0x2
56#define UART16550_DATA_8BIT 0x3
57
58#define UART16550_STOP_1BIT 0x0
59#define UART16550_STOP_2BIT 0x4
60
61/* register offset */
62#define OFS_RCV_BUFFER 0
63#define OFS_TRANS_HOLD 0
64#define OFS_SEND_BUFFER 0
65#define OFS_INTR_ENABLE (1*REG_OFFSET)
66#define OFS_INTR_ID (2*REG_OFFSET)
67#define OFS_DATA_FORMAT (3*REG_OFFSET)
68#define OFS_LINE_CONTROL (3*REG_OFFSET)
69#define OFS_MODEM_CONTROL (4*REG_OFFSET)
70#define OFS_RS232_OUTPUT (4*REG_OFFSET)
71#define OFS_LINE_STATUS (5*REG_OFFSET)
72#define OFS_MODEM_STATUS (6*REG_OFFSET)
73#define OFS_RS232_INPUT (6*REG_OFFSET)
74#define OFS_SCRATCH_PAD (7*REG_OFFSET)
75
76#define OFS_DIVISOR_LSB (0*REG_OFFSET)
77#define OFS_DIVISOR_MSB (1*REG_OFFSET)
78
79
80/* memory-mapped read/write of the port */
81#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
82#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
83
84void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
85{
86 /* disable interrupts */
87 UART16550_WRITE(OFS_INTR_ENABLE, 0);
88
89 /* set up baud rate */
90 {
91 uint32 divisor;
92
93 /* set DIAB bit */
94 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
95
96 /* set divisor */
97 divisor = MAX_BAUD / baud;
98 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
99 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
100
101 /* clear DIAB bit */
102 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
103 }
104
105 /* set data format */
106 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
107}
108
109
110uint8 getDebugChar(void)
111{
112 if (!remoteDebugInitialized) {
113 remoteDebugInitialized = 1;
114 debugInit(BAUD_DEFAULT,
115 UART16550_DATA_8BIT,
116 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
117 }
118
119 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
120 return UART16550_READ(OFS_RCV_BUFFER);
121}
122
123
124int putDebugChar(uint8 byte)
125{
126 if (!remoteDebugInitialized) {
127 remoteDebugInitialized = 1;
128 debugInit(BAUD_DEFAULT,
129 UART16550_DATA_8BIT,
130 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
131 }
132
133 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
134 UART16550_WRITE(OFS_SEND_BUFFER, byte);
135 return 1;
136}
diff --git a/arch/mips/ddb5xxx/ddb5477/lcd44780.c b/arch/mips/ddb5xxx/ddb5477/lcd44780.c
deleted file mode 100644
index 9510b9ae6453..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/lcd44780.c
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * lcd44780.c
3 * Simple "driver" for a memory-mapped 44780-style LCD display.
4 *
5 * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#define LCD44780_COMMAND ((volatile unsigned char *)0xbe020000)
15#define LCD44780_DATA ((volatile unsigned char *)0xbe020001)
16
17#define LCD44780_4BIT_1LINE 0x20
18#define LCD44780_4BIT_2LINE 0x28
19#define LCD44780_8BIT_1LINE 0x30
20#define LCD44780_8BIT_2LINE 0x38
21#define LCD44780_MODE_DEC 0x04
22#define LCD44780_MODE_DEC_SHIFT 0x05
23#define LCD44780_MODE_INC 0x06
24#define LCD44780_MODE_INC_SHIFT 0x07
25#define LCD44780_SCROLL_LEFT 0x18
26#define LCD44780_SCROLL_RIGHT 0x1e
27#define LCD44780_CURSOR_UNDERLINE 0x0e
28#define LCD44780_CURSOR_BLOCK 0x0f
29#define LCD44780_CURSOR_OFF 0x0c
30#define LCD44780_CLEAR 0x01
31#define LCD44780_BLANK 0x08
32#define LCD44780_RESTORE 0x0c // Same as CURSOR_OFF
33#define LCD44780_HOME 0x02
34#define LCD44780_LEFT 0x10
35#define LCD44780_RIGHT 0x14
36
37void lcd44780_wait(void)
38{
39 int i, j;
40 for(i=0; i < 400; i++)
41 for(j=0; j < 10000; j++);
42}
43
44void lcd44780_command(unsigned char c)
45{
46 *LCD44780_COMMAND = c;
47 lcd44780_wait();
48}
49
50void lcd44780_data(unsigned char c)
51{
52 *LCD44780_DATA = c;
53 lcd44780_wait();
54}
55
56void lcd44780_puts(const char* s)
57{
58 int j;
59 int pos = 0;
60
61 lcd44780_command(LCD44780_CLEAR);
62 while(*s) {
63 lcd44780_data(*s);
64 s++;
65 pos++;
66 if (pos == 8) {
67 /* We must write 32 of spaces to get cursor to 2nd line */
68 for (j=0; j<32; j++) {
69 lcd44780_data(' ');
70 }
71 }
72 if (pos == 16) {
73 /* We have filled all 16 character positions, so stop
74 outputing data */
75 break;
76 }
77 }
78#ifdef LCD44780_PUTS_PAUSE
79 {
80 int i;
81
82 for(i = 1; i < 2000; i++)
83 lcd44780_wait();
84 }
85#endif
86}
87
88void lcd44780_init(void)
89{
90 // The display on the RockHopper is physically a single
91 // 16 char line (two 8 char lines concatenated). bdl
92 lcd44780_command(LCD44780_8BIT_2LINE);
93 lcd44780_command(LCD44780_MODE_INC);
94 lcd44780_command(LCD44780_CURSOR_BLOCK);
95 lcd44780_command(LCD44780_CLEAR);
96}
diff --git a/arch/mips/ddb5xxx/ddb5477/lcd44780.h b/arch/mips/ddb5xxx/ddb5477/lcd44780.h
deleted file mode 100644
index cf2f0f71eee5..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/lcd44780.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * lcd44780.h
3 * Simple "driver" for a memory-mapped 44780-style LCD display.
4 *
5 * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14void lcd44780_puts(const char* s);
15void lcd44780_init(void);
diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c
deleted file mode 100644
index f0cc0e8a8afa..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/setup.c
+++ /dev/null
@@ -1,399 +0,0 @@
1/*
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: jsun@mvista.com or jsun@junsun.net
5 *
6 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
7 *
8 * arch/mips/ddb5xxx/ddb5477/setup.c
9 * Setup file for DDB5477.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/sched.h>
20#include <linux/pci.h>
21#include <linux/ide.h>
22#include <linux/irq.h>
23#include <linux/fs.h>
24#include <linux/ioport.h>
25#include <linux/param.h> /* for HZ */
26#include <linux/major.h>
27#include <linux/kdev_t.h>
28#include <linux/root_dev.h>
29#include <linux/pm.h>
30
31#include <asm/cpu.h>
32#include <asm/bootinfo.h>
33#include <asm/addrspace.h>
34#include <asm/time.h>
35#include <asm/bcache.h>
36#include <asm/irq.h>
37#include <asm/reboot.h>
38#include <asm/gdb-stub.h>
39#include <asm/traps.h>
40#include <asm/debug.h>
41
42#include <asm/ddb5xxx/ddb5xxx.h>
43
44#include "lcd44780.h"
45
46
47#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
48
49#define SP_TIMER_BASE DDB_SPT1CTRL_L
50#define SP_TIMER_IRQ VRC5477_IRQ_SPT1
51
52static int bus_frequency = CONFIG_DDB5477_BUS_FREQUENCY*1000;
53
54static void ddb_machine_restart(char *command)
55{
56 static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
57
58 u32 t;
59
60 /* PCI cold reset */
61 ddb_pci_reset_bus();
62
63 /* CPU cold reset */
64 t = ddb_in32(DDB_CPUSTAT);
65 db_assert((t&1));
66 ddb_out32(DDB_CPUSTAT, t);
67
68 /* Call the PROM */
69 back_to_prom();
70}
71
72static void ddb_machine_halt(void)
73{
74 printk("DDB Vrc-5477 halted.\n");
75 while (1);
76}
77
78static void ddb_machine_power_off(void)
79{
80 printk("DDB Vrc-5477 halted. Please turn off the power.\n");
81 while (1);
82}
83
84extern void rtc_ds1386_init(unsigned long base);
85
86static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
87{
88 unsigned int freq;
89 unsigned char c;
90 unsigned int t1, t2;
91 unsigned i;
92
93 ddb_out32(SP_TIMER_BASE, 0xffffffff);
94 ddb_out32(SP_TIMER_BASE+4, 0x1);
95 ddb_out32(SP_TIMER_BASE+8, 0xffffffff);
96
97 /* check if rtc is running */
98 c= *(volatile unsigned char*)rtc_base;
99 for(i=0; (c == *(volatile unsigned char*)rtc_base) && (i<100000000); i++);
100 if (c == *(volatile unsigned char*)rtc_base) {
101 printk("Failed to detect bus frequency. Use default 83.3MHz.\n");
102 return 83333000;
103 }
104
105 c= *(volatile unsigned char*)rtc_base;
106 while (c == *(volatile unsigned char*)rtc_base);
107 /* we are now at the turn of 1/100th second, if no error. */
108 t1 = ddb_in32(SP_TIMER_BASE+8);
109
110 for (i=0; i< 10; i++) {
111 c= *(volatile unsigned char*)rtc_base;
112 while (c == *(volatile unsigned char*)rtc_base);
113 /* we are now at the turn of another 1/100th second */
114 t2 = ddb_in32(SP_TIMER_BASE+8);
115 }
116
117 ddb_out32(SP_TIMER_BASE+4, 0x0); /* disable it again */
118
119 freq = (t1 - t2)*10;
120 printk("DDB bus frequency detection : %u \n", freq);
121 return freq;
122}
123
124static void __init ddb_time_init(void)
125{
126 unsigned long rtc_base;
127 unsigned int i;
128
129 /* we have ds1396 RTC chip */
130 if (mips_machtype == MACH_NEC_ROCKHOPPER
131 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
132 rtc_base = KSEG1ADDR(DDB_LCS2_BASE);
133 } else {
134 rtc_base = KSEG1ADDR(DDB_LCS1_BASE);
135 }
136 rtc_ds1386_init(rtc_base);
137
138 /* do we need to do run-time detection of bus speed? */
139 if (bus_frequency == 0) {
140 bus_frequency = detect_bus_frequency(rtc_base);
141 }
142
143 /* mips_hpt_frequency is 1/2 of the cpu core freq */
144 i = (read_c0_config() >> 28 ) & 7;
145 if ((current_cpu_data.cputype == CPU_R5432) && (i == 3))
146 i = 4;
147 mips_hpt_frequency = bus_frequency*(i+4)/4;
148}
149
150void __init plat_timer_setup(struct irqaction *irq)
151{
152#if defined(USE_CPU_COUNTER_TIMER)
153
154 /* we are using the cpu counter for timer interrupts */
155 setup_irq(CPU_IRQ_BASE + 7, irq);
156
157#else
158
159 /* if we use Special purpose timer 1 */
160 ddb_out32(SP_TIMER_BASE, bus_frequency/HZ);
161 ddb_out32(SP_TIMER_BASE+4, 0x1);
162 setup_irq(SP_TIMER_IRQ, irq);
163
164#endif
165}
166
167static void ddb5477_board_init(void);
168
169extern struct pci_controller ddb5477_ext_controller;
170extern struct pci_controller ddb5477_io_controller;
171
172void __init plat_mem_setup(void)
173{
174 /* initialize board - we don't trust the loader */
175 ddb5477_board_init();
176
177 set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
178
179 board_time_init = ddb_time_init;
180
181 _machine_restart = ddb_machine_restart;
182 _machine_halt = ddb_machine_halt;
183 pm_power_off = ddb_machine_power_off;
184
185 /* setup resource limits */
186 ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1;
187 iomem_resource.end = 0xffffffff;
188
189 /* Reboot on panic */
190 panic_timeout = 180;
191
192 register_pci_controller (&ddb5477_ext_controller);
193 register_pci_controller (&ddb5477_io_controller);
194}
195
196static void __init ddb5477_board_init(void)
197{
198 /* ----------- setup PDARs ------------ */
199
200 /* SDRAM should have been set */
201 db_assert(ddb_in32(DDB_SDRAM0) ==
202 ddb_calc_pdar(DDB_SDRAM_BASE, board_ram_size, 32, 0, 1));
203
204 /* SDRAM1 should be turned off. What is this for anyway ? */
205 db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
206
207 /* Setup local bus. */
208
209 /* Flash U12 PDAR and timing. */
210 ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0);
211 ddb_out32(DDB_LCST0, 0x00090842);
212
213 /* We need to setup LCS1 and LCS2 differently based on the
214 board_version */
215 if (mips_machtype == MACH_NEC_ROCKHOPPER) {
216 /* Flash U13 PDAR and timing. */
217 ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 16, 0, 0);
218 ddb_out32(DDB_LCST1, 0x00090842);
219
220 /* EPLD (NVRAM, switch, LCD, and mezzanie). */
221 ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 8, 0, 0);
222 } else {
223 /* misc */
224 ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0);
225 /* mezzanie (?) */
226 ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0);
227 }
228
229 /* verify VRC5477 base addr */
230 db_assert(ddb_in32(DDB_VRC5477) ==
231 ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
232
233 /* verify BOOT ROM addr */
234 db_assert(ddb_in32(DDB_BOOTCS) ==
235 ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
236
237 /* setup PCI windows - window0 for MEM/config, window1 for IO */
238 ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
239 ddb_set_pdar(DDB_PCIW1, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
240 ddb_set_pdar(DDB_IOPCIW0, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
241 ddb_set_pdar(DDB_IOPCIW1, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
242
243 /* ------------ reset PCI bus and BARs ----------------- */
244 ddb_pci_reset_bus();
245
246 ddb_out32(DDB_BARM010, 0x00000008);
247 ddb_out32(DDB_BARM011, 0x00000008);
248
249 ddb_out32(DDB_BARC0, 0xffffffff);
250 ddb_out32(DDB_BARM230, 0xffffffff);
251 ddb_out32(DDB_BAR00, 0xffffffff);
252 ddb_out32(DDB_BAR10, 0xffffffff);
253 ddb_out32(DDB_BAR20, 0xffffffff);
254 ddb_out32(DDB_BAR30, 0xffffffff);
255 ddb_out32(DDB_BAR40, 0xffffffff);
256 ddb_out32(DDB_BAR50, 0xffffffff);
257 ddb_out32(DDB_BARB0, 0xffffffff);
258
259 ddb_out32(DDB_BARC1, 0xffffffff);
260 ddb_out32(DDB_BARM231, 0xffffffff);
261 ddb_out32(DDB_BAR01, 0xffffffff);
262 ddb_out32(DDB_BAR11, 0xffffffff);
263 ddb_out32(DDB_BAR21, 0xffffffff);
264 ddb_out32(DDB_BAR31, 0xffffffff);
265 ddb_out32(DDB_BAR41, 0xffffffff);
266 ddb_out32(DDB_BAR51, 0xffffffff);
267 ddb_out32(DDB_BARB1, 0xffffffff);
268
269 /*
270 * We use pci master register 0 for memory space / config space
271 * And we use register 1 for IO space.
272 * Note that for memory space, we bump up the pci base address
273 * so that we have 1:1 mapping between PCI memory and cpu physical.
274 * For PCI IO space, it starts from 0 in PCI IO space but with
275 * DDB_xx_IO_BASE in CPU physical address space.
276 */
277 ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE,
278 DDB_PCI_ACCESS_32);
279 ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
280
281 ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE,
282 DDB_PCI_ACCESS_32);
283 ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE,
284 DDB_PCI_ACCESS_32);
285
286
287 /* PCI cross window should be set properly */
288 ddb_set_pdar(DDB_BARP00, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
289 ddb_set_pdar(DDB_BARP10, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
290 ddb_set_pdar(DDB_BARP01, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
291 ddb_set_pdar(DDB_BARP11, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
292
293 if (mips_machtype == MACH_NEC_ROCKHOPPER
294 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
295 /* Disable bus diagnostics. */
296 ddb_out32(DDB_PCICTL0_L, 0);
297 ddb_out32(DDB_PCICTL0_H, 0);
298 ddb_out32(DDB_PCICTL1_L, 0);
299 ddb_out32(DDB_PCICTL1_H, 0);
300 }
301
302 if (mips_machtype == MACH_NEC_ROCKHOPPER) {
303 u16 vid;
304 struct pci_bus bus;
305 struct pci_dev dev_m1533;
306 extern struct pci_ops ddb5477_ext_pci_ops;
307
308 bus.parent = NULL; /* we scan the top level only */
309 bus.ops = &ddb5477_ext_pci_ops;
310 dev_m1533.bus = &bus;
311 dev_m1533.sysdata = NULL;
312 dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
313 pci_read_config_word(&dev_m1533, 0, &vid);
314 if (vid == PCI_VENDOR_ID_AL) {
315 printk("Changing mips_machtype to MACH_NEC_ROCKHOPPERII\n");
316 mips_machtype = MACH_NEC_ROCKHOPPERII;
317 }
318 }
319
320 /* enable USB input buffers */
321 ddb_out32(DDB_PIBMISC, 0x00000007);
322
323 /* For dual-function pins, make them all non-GPIO */
324 ddb_out32(DDB_GIUFUNSEL, 0x0);
325 // ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff); /* NEC recommanded value */
326
327 if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
328
329 /* enable IDE controller on Ali chip (south bridge) */
330 u8 temp8;
331 struct pci_bus bus;
332 struct pci_dev dev_m1533;
333 struct pci_dev dev_m5229;
334 extern struct pci_ops ddb5477_ext_pci_ops;
335
336 /* Setup M1535 registers */
337 bus.parent = NULL; /* we scan the top level only */
338 bus.ops = &ddb5477_ext_pci_ops;
339 dev_m1533.bus = &bus;
340 dev_m1533.sysdata = NULL;
341 dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
342
343 /* setup IDE controller
344 * enable IDE controller (bit 6 - 1)
345 * IDE IDSEL to be addr:A15 (bit 4:5 - 11)
346 * disable IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
347 * enable IDE ATA Primary Bus Signal Pad Control (bit 2 - 1)
348 */
349 pci_write_config_byte(&dev_m1533, 0x58, 0x74);
350
351 /*
352 * positive decode (bit6 -0)
353 * enable IDE controler interrupt (bit 4 -1)
354 * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101)
355 */
356 pci_write_config_byte(&dev_m1533, 0x44, 0x1d);
357
358 /* Setup M5229 registers */
359 dev_m5229.bus = &bus;
360 dev_m5229.sysdata = NULL;
361 dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE
362
363 /*
364 * enable IDE in the M5229 config register 0x50 (bit 0 - 1)
365 * M5229 IDSEL is addr:15; see above setting
366 */
367 pci_read_config_byte(&dev_m5229, 0x50, &temp8);
368 pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1);
369
370 /*
371 * enable bus master (bit 2) and IO decoding (bit 0)
372 */
373 pci_read_config_byte(&dev_m5229, 0x04, &temp8);
374 pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5);
375
376 /*
377 * enable native, copied from arch/ppc/k2boot/head.S
378 * TODO - need volatile, need to be portable
379 */
380 pci_write_config_byte(&dev_m5229, 0x09, 0xef);
381
382 /* Set Primary Channel Command Block Timing */
383 pci_write_config_byte(&dev_m5229, 0x59, 0x31);
384
385 /*
386 * Enable primary channel 40-pin cable
387 * M5229 register 0x4a (bit 0)
388 */
389 pci_read_config_byte(&dev_m5229, 0x4a, &temp8);
390 pci_write_config_byte(&dev_m5229, 0x4a, temp8 | 0x1);
391 }
392
393 if (mips_machtype == MACH_NEC_ROCKHOPPER
394 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
395 printk("lcd44780: initializing\n");
396 lcd44780_init();
397 lcd44780_puts("MontaVista Linux");
398 }
399}
diff --git a/arch/mips/defconfig b/arch/mips/defconfig
index fee0f9f948b3..d3d81fb2765a 100644
--- a/arch/mips/defconfig
+++ b/arch/mips/defconfig
@@ -35,7 +35,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_XXS1500 is not set 35# CONFIG_MIPS_XXS1500 is not set
36# CONFIG_PNX8550_JBS is not set 36# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_DDB5477 is not set
39# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set 40# CONFIG_QEMU is not set
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 8be9f2b9db26..4ee6800e67e6 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -19,7 +19,6 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
19# These are still pretty much in the old state, watch, go blind. 19# These are still pretty much in the old state, watch, go blind.
20# 20#
21obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o 21obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o
22obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
23obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o 22obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
24obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o 23obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
25obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o 24obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
diff --git a/arch/mips/pci/fixup-ddb5477.c b/arch/mips/pci/fixup-ddb5477.c
deleted file mode 100644
index 2f1444e60654..000000000000
--- a/arch/mips/pci/fixup-ddb5477.c
+++ /dev/null
@@ -1,78 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Board specific pci fixups.
5 *
6 * Copyright 2001, 2002, 2003 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/types.h>
31#include <linux/pci.h>
32#include <linux/kernel.h>
33#include <linux/init.h>
34
35static void ddb5477_fixup(struct pci_dev *dev)
36{
37 u8 old;
38
39 printk(KERN_NOTICE "Enabling ALI M1533/35 PS2 keyboard/mouse.\n");
40 pci_read_config_byte(dev, 0x41, &old);
41 pci_write_config_byte(dev, 0x41, old | 0xd0);
42}
43
44DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533,
45 ddb5477_fixup);
46DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1535,
47 ddb5477_fixup);
48
49/*
50 * Fixup baseboard AMD chip so that tx does not underflow.
51 * bcr_18 |= 0x0800
52 * This sets NOUFLO bit which makes tx not start until whole pkt
53 * is fetched to the chip.
54 */
55#define PCNET32_WIO_RDP 0x10
56#define PCNET32_WIO_RAP 0x12
57#define PCNET32_WIO_RESET 0x14
58#define PCNET32_WIO_BDP 0x16
59
60static void ddb5477_amd_lance_fixup(struct pci_dev *dev)
61{
62 unsigned long ioaddr;
63 u16 temp;
64
65 ioaddr = pci_resource_start(dev, 0);
66
67 inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */
68
69 /* bcr_18 |= 0x0800 */
70 outw(18, ioaddr + PCNET32_WIO_RAP);
71 temp = inw(ioaddr + PCNET32_WIO_BDP);
72 temp |= 0x0800;
73 outw(18, ioaddr + PCNET32_WIO_RAP);
74 outw(temp, ioaddr + PCNET32_WIO_BDP);
75}
76
77DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE,
78 ddb5477_amd_lance_fixup);
diff --git a/arch/mips/pci/ops-ddb5477.c b/arch/mips/pci/ops-ddb5477.c
deleted file mode 100644
index 8e57d4c5d90f..000000000000
--- a/arch/mips/pci/ops-ddb5477.c
+++ /dev/null
@@ -1,278 +0,0 @@
1/***********************************************************************
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/ddb5xxx/ddb5477/pci_ops.c
6 * Define the pci_ops for DB5477.
7 *
8 * Much of the code is derived from the original DDB5074 port by
9 * Geert Uytterhoeven <geert@sonycom.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 ***********************************************************************
16 */
17
18/*
19 * DDB5477 has two PCI channels, external PCI and IOPIC (internal)
20 * Therefore we provide two sets of pci_ops.
21 */
22#include <linux/pci.h>
23#include <linux/kernel.h>
24#include <linux/types.h>
25
26#include <asm/addrspace.h>
27#include <asm/debug.h>
28
29#include <asm/ddb5xxx/ddb5xxx.h>
30
31/*
32 * config_swap structure records what set of pdar/pmr are used
33 * to access pci config space. It also provides a place hold the
34 * original values for future restoring.
35 */
36struct pci_config_swap {
37 u32 pdar;
38 u32 pmr;
39 u32 config_base;
40 u32 config_size;
41 u32 pdar_backup;
42 u32 pmr_backup;
43};
44
45/*
46 * On DDB5477, we have two sets of swap registers, for ext PCI and IOPCI.
47 */
48struct pci_config_swap ext_pci_swap = {
49 DDB_PCIW0,
50 DDB_PCIINIT00,
51 DDB_PCI0_CONFIG_BASE,
52 DDB_PCI0_CONFIG_SIZE
53};
54struct pci_config_swap io_pci_swap = {
55 DDB_IOPCIW0,
56 DDB_PCIINIT01,
57 DDB_PCI1_CONFIG_BASE,
58 DDB_PCI1_CONFIG_SIZE
59};
60
61
62/*
63 * access config space
64 */
65static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */
66 u32 slot_num)
67{
68 u32 pci_addr = 0;
69 u32 pciinit_offset = 0;
70 u32 virt_addr;
71 u32 option;
72
73 /* minimum pdar (window) size is 2MB */
74 db_assert(swap->config_size >= (2 << 20));
75
76 db_assert(slot_num < (1 << 5));
77 db_assert(bus < (1 << 8));
78
79 /* backup registers */
80 swap->pdar_backup = ddb_in32(swap->pdar);
81 swap->pmr_backup = ddb_in32(swap->pmr);
82
83 /* set the pdar (pci window) register */
84 ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */
85 0, /* not on local memory bus */
86 0); /* not visible from PCI bus (N/A) */
87
88 /*
89 * calcuate the absolute pci config addr;
90 * according to the spec, we start scanning from adr:11 (0x800)
91 */
92 if (bus == 0) {
93 /* type 0 config */
94 pci_addr = 0x800 << slot_num;
95 } else {
96 /* type 1 config */
97 pci_addr = (bus << 16) | (slot_num << 11);
98 }
99
100 /*
101 * if pci_addr is less than pci config window size, we set
102 * pciinit_offset to 0 and adjust the virt_address.
103 * Otherwise we will try to adjust pciinit_offset.
104 */
105 if (pci_addr < swap->config_size) {
106 virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
107 pciinit_offset = 0;
108 } else {
109 db_assert((pci_addr & (swap->config_size - 1)) == 0);
110 virt_addr = KSEG1ADDR(swap->config_base);
111 pciinit_offset = pci_addr;
112 }
113
114 /* set the pmr register */
115 option = DDB_PCI_ACCESS_32;
116 if (bus != 0)
117 option |= DDB_PCI_CFGTYPE1;
118 ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
119
120 return virt_addr;
121}
122
123static inline void ddb_close_config_base(struct pci_config_swap *swap)
124{
125 ddb_out32(swap->pdar, swap->pdar_backup);
126 ddb_out32(swap->pmr, swap->pmr_backup);
127}
128
129static int read_config_dword(struct pci_config_swap *swap,
130 struct pci_bus *bus, u32 devfn, u32 where,
131 u32 * val)
132{
133 u32 bus_num, slot_num, func_num;
134 u32 base;
135
136 db_assert((where & 3) == 0);
137 db_assert(where < (1 << 8));
138
139 /* check if the bus is top-level */
140 if (bus->parent != NULL) {
141 bus_num = bus->number;
142 db_assert(bus_num != 0);
143 } else {
144 bus_num = 0;
145 }
146
147 slot_num = PCI_SLOT(devfn);
148 func_num = PCI_FUNC(devfn);
149 base = ddb_access_config_base(swap, bus_num, slot_num);
150 *val = *(volatile u32 *) (base + (func_num << 8) + where);
151 ddb_close_config_base(swap);
152 return PCIBIOS_SUCCESSFUL;
153}
154
155static int read_config_word(struct pci_config_swap *swap,
156 struct pci_bus *bus, u32 devfn, u32 where,
157 u16 * val)
158{
159 int status;
160 u32 result;
161
162 db_assert((where & 1) == 0);
163
164 status = read_config_dword(swap, bus, devfn, where & ~3, &result);
165 if (where & 2)
166 result >>= 16;
167 *val = result & 0xffff;
168 return status;
169}
170
171static int read_config_byte(struct pci_config_swap *swap,
172 struct pci_bus *bus, u32 devfn, u32 where,
173 u8 * val)
174{
175 int status;
176 u32 result;
177
178 status = read_config_dword(swap, bus, devfn, where & ~3, &result);
179 if (where & 1)
180 result >>= 8;
181 if (where & 2)
182 result >>= 16;
183 *val = result & 0xff;
184
185 return status;
186}
187
188static int write_config_dword(struct pci_config_swap *swap,
189 struct pci_bus *bus, u32 devfn, u32 where,
190 u32 val)
191{
192 u32 bus_num, slot_num, func_num;
193 u32 base;
194
195 db_assert((where & 3) == 0);
196 db_assert(where < (1 << 8));
197
198 /* check if the bus is top-level */
199 if (bus->parent != NULL) {
200 bus_num = bus->number;
201 db_assert(bus_num != 0);
202 } else {
203 bus_num = 0;
204 }
205
206 slot_num = PCI_SLOT(devfn);
207 func_num = PCI_FUNC(devfn);
208 base = ddb_access_config_base(swap, bus_num, slot_num);
209 *(volatile u32 *) (base + (func_num << 8) + where) = val;
210 ddb_close_config_base(swap);
211 return PCIBIOS_SUCCESSFUL;
212}
213
214static int write_config_word(struct pci_config_swap *swap,
215 struct pci_bus *bus, u32 devfn, u32 where, u16 val)
216{
217 int status, shift = 0;
218 u32 result;
219
220 db_assert((where & 1) == 0);
221
222 status = read_config_dword(swap, bus, devfn, where & ~3, &result);
223 if (status != PCIBIOS_SUCCESSFUL)
224 return status;
225
226 if (where & 2)
227 shift += 16;
228 result &= ~(0xffff << shift);
229 result |= val << shift;
230 return write_config_dword(swap, bus, devfn, where & ~3, result);
231}
232
233static int write_config_byte(struct pci_config_swap *swap,
234 struct pci_bus *bus, u32 devfn, u32 where, u8 val)
235{
236 int status, shift = 0;
237 u32 result;
238
239 status = read_config_dword(swap, bus, devfn, where & ~3, &result);
240 if (status != PCIBIOS_SUCCESSFUL)
241 return status;
242
243 if (where & 2)
244 shift += 16;
245 if (where & 1)
246 shift += 8;
247 result &= ~(0xff << shift);
248 result |= val << shift;
249 return write_config_dword(swap, bus, devfn, where & ~3, result);
250}
251
252#define MAKE_PCI_OPS(prefix, rw, pciswap, star) \
253static int prefix##_##rw##_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 star val) \
254{ \
255 if (size == 1) \
256 return rw##_config_byte(pciswap, bus, devfn, where, (u8 star)val); \
257 else if (size == 2) \
258 return rw##_config_word(pciswap, bus, devfn, where, (u16 star)val); \
259 /* Size must be 4 */ \
260 return rw##_config_dword(pciswap, bus, devfn, where, val); \
261}
262
263MAKE_PCI_OPS(extpci, read, &ext_pci_swap, *)
264MAKE_PCI_OPS(extpci, write, &ext_pci_swap,)
265
266MAKE_PCI_OPS(iopci, read, &io_pci_swap, *)
267MAKE_PCI_OPS(iopci, write, &io_pci_swap,)
268
269struct pci_ops ddb5477_ext_pci_ops = {
270 .read = extpci_read_config,
271 .write = extpci_write_config
272};
273
274
275struct pci_ops ddb5477_io_pci_ops = {
276 .read = iopci_read_config,
277 .write = iopci_write_config
278};
diff --git a/arch/mips/pci/pci-ddb5477.c b/arch/mips/pci/pci-ddb5477.c
deleted file mode 100644
index 7363e1877842..000000000000
--- a/arch/mips/pci/pci-ddb5477.c
+++ /dev/null
@@ -1,207 +0,0 @@
1/*
2 * PCI code for DDB5477.
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
6 *
7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/types.h>
17#include <linux/pci.h>
18
19#include <asm/bootinfo.h>
20#include <asm/debug.h>
21
22#include <asm/ddb5xxx/ddb5xxx.h>
23
24static struct resource extpci_io_resource = {
25 .start = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000,
26 .end = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1,
27 .name = "ext pci IO space",
28 .flags = IORESOURCE_IO
29};
30
31static struct resource extpci_mem_resource = {
32 .start = DDB_PCI0_MEM_BASE + 0x100000,
33 .end = DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1,
34 .name = "ext pci memory space",
35 .flags = IORESOURCE_MEM
36};
37
38static struct resource iopci_io_resource = {
39 .start = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE,
40 .end = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1,
41 .name = "io pci IO space",
42 .flags = IORESOURCE_IO
43};
44
45static struct resource iopci_mem_resource = {
46 .start = DDB_PCI1_MEM_BASE,
47 .end = DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1,
48 .name = "ext pci memory space",
49 .flags = IORESOURCE_MEM
50};
51
52extern struct pci_ops ddb5477_ext_pci_ops;
53extern struct pci_ops ddb5477_io_pci_ops;
54
55struct pci_controller ddb5477_ext_controller = {
56 .pci_ops = &ddb5477_ext_pci_ops,
57 .io_resource = &extpci_io_resource,
58 .mem_resource = &extpci_mem_resource
59};
60
61struct pci_controller ddb5477_io_controller = {
62 .pci_ops = &ddb5477_io_pci_ops,
63 .io_resource = &iopci_io_resource,
64 .mem_resource = &iopci_mem_resource
65};
66
67
68
69/*
70 * we fix up irqs based on the slot number.
71 * The first entry is at AD:11.
72 * Fortunately this works because, although we have two pci buses,
73 * they all have different slot numbers (except for rockhopper slot 20
74 * which is handled below).
75 *
76 */
77
78/*
79 * irq mapping : device -> pci int # -> vrc4377 irq# ,
80 * ddb5477 board manual page 4 and vrc5477 manual page 46
81 */
82
83/*
84 * based on ddb5477 manual page 11
85 */
86#define MAX_SLOT_NUM 21
87static unsigned char irq_map[MAX_SLOT_NUM] = {
88 /* SLOT: 0, AD:11 */ 0xff,
89 /* SLOT: 1, AD:12 */ 0xff,
90 /* SLOT: 2, AD:13 */ 0xff,
91 /* SLOT: 3, AD:14 */ 0xff,
92 /* SLOT: 4, AD:15 */ VRC5477_IRQ_INTA, /* onboard tulip */
93 /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTB, /* slot 1 */
94 /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTC, /* slot 2 */
95 /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 3 */
96 /* SLOT: 8, AD:19 */ VRC5477_IRQ_INTE, /* slot 4 */
97 /* SLOT: 9, AD:20 */ 0xff,
98 /* SLOT: 10, AD:21 */ 0xff,
99 /* SLOT: 11, AD:22 */ 0xff,
100 /* SLOT: 12, AD:23 */ 0xff,
101 /* SLOT: 13, AD:24 */ 0xff,
102 /* SLOT: 14, AD:25 */ 0xff,
103 /* SLOT: 15, AD:26 */ 0xff,
104 /* SLOT: 16, AD:27 */ 0xff,
105 /* SLOT: 17, AD:28 */ 0xff,
106 /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */
107 /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */
108 /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */
109};
110static unsigned char rockhopperII_irq_map[MAX_SLOT_NUM] = {
111 /* SLOT: 0, AD:11 */ 0xff,
112 /* SLOT: 1, AD:12 */ VRC5477_IRQ_INTB, /* onboard AMD PCNET */
113 /* SLOT: 2, AD:13 */ 0xff,
114 /* SLOT: 3, AD:14 */ 0xff,
115 /* SLOT: 4, AD:15 */ 14, /* M5229 ide ISA irq */
116 /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTD, /* slot 3 */
117 /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTA, /* slot 4 */
118 /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 5 */
119 /* SLOT: 8, AD:19 */ 0, /* M5457 modem nop */
120 /* SLOT: 9, AD:20 */ VRC5477_IRQ_INTA, /* slot 2 */
121 /* SLOT: 10, AD:21 */ 0xff,
122 /* SLOT: 11, AD:22 */ 0xff,
123 /* SLOT: 12, AD:23 */ 0xff,
124 /* SLOT: 13, AD:24 */ 0xff,
125 /* SLOT: 14, AD:25 */ 0xff,
126 /* SLOT: 15, AD:26 */ 0xff,
127 /* SLOT: 16, AD:27 */ 0xff,
128 /* SLOT: 17, AD:28 */ 0, /* M7101 PMU nop */
129 /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */
130 /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */
131 /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */
132};
133
134int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
135{
136 int slot_num;
137 unsigned char *slot_irq_map;
138 unsigned char irq;
139
140 /*
141 * We ignore the swizzled slot and pin values. The original
142 * pci_fixup_irq() codes largely base irq number on the dev slot
143 * numbers because except for one case they are unique even
144 * though there are multiple pci buses.
145 */
146
147 if (mips_machtype == MACH_NEC_ROCKHOPPERII)
148 slot_irq_map = rockhopperII_irq_map;
149 else
150 slot_irq_map = irq_map;
151
152 slot_num = PCI_SLOT(dev->devfn);
153 irq = slot_irq_map[slot_num];
154
155 db_assert(slot_num < MAX_SLOT_NUM);
156
157 db_assert(irq != 0xff);
158
159 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
160
161 if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
162 /* hack to distinquish overlapping slot 20s, one
163 * on bus 0 (ALI USB on the M1535 on the backplane),
164 * and one on bus 2 (NEC USB controller on the CPU board)
165 * Make the M1535 USB - ISA IRQ number 9.
166 */
167 if (slot_num == 20 && dev->bus->number == 0) {
168 pci_write_config_byte(dev,
169 PCI_INTERRUPT_LINE,
170 9);
171 irq = 9;
172 }
173
174 }
175
176 return irq;
177}
178
179/* Do platform specific device initialization at pci_enable_device() time */
180int pcibios_plat_dev_init(struct pci_dev *dev)
181{
182 return 0;
183}
184
185void ddb_pci_reset_bus(void)
186{
187 u32 temp;
188
189 /*
190 * I am not sure about the "official" procedure, the following
191 * steps work as far as I know:
192 * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
193 * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
194 * The same is true for both PCI channels.
195 */
196 temp = ddb_in32(DDB_PCICTL0_H);
197 temp |= 0x80000000;
198 ddb_out32(DDB_PCICTL0_H, temp);
199 temp &= ~0xc0000000;
200 ddb_out32(DDB_PCICTL0_H, temp);
201
202 temp = ddb_in32(DDB_PCICTL1_H);
203 temp |= 0x80000000;
204 ddb_out32(DDB_PCICTL1_H, temp);
205 temp &= ~0xc0000000;
206 ddb_out32(DDB_PCICTL1_H, temp);
207}
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index d0513b1dc3e7..c0f052b37b9e 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -86,16 +86,6 @@
86#define MACH_COBALT_27 0 /* Proto "27" hardware */ 86#define MACH_COBALT_27 0 /* Proto "27" hardware */
87 87
88/* 88/*
89 * Valid machtype for group NEC DDB
90 */
91#define MACH_GROUP_NEC_DDB 8 /* NEC DDB */
92#define MACH_NEC_DDB5074 0 /* NEC DDB Vrc-5074 */
93#define MACH_NEC_DDB5476 1 /* NEC DDB Vrc-5476 */
94#define MACH_NEC_DDB5477 2 /* NEC DDB Vrc-5477 */
95#define MACH_NEC_ROCKHOPPER 3 /* Rockhopper base board */
96#define MACH_NEC_ROCKHOPPERII 4 /* Rockhopper II base board */
97
98/*
99 * Valid machtype for group BAGET 89 * Valid machtype for group BAGET
100 */ 90 */
101#define MACH_GROUP_BAGET 9 /* Baget */ 91#define MACH_GROUP_BAGET 9 /* Baget */
diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h
deleted file mode 100644
index 6cf177caf6d5..000000000000
--- a/include/asm-mips/ddb5xxx/ddb5477.h
+++ /dev/null
@@ -1,342 +0,0 @@
1/***********************************************************************
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: jsun@mvista.com or jsun@junsun.net
5 *
6 * include/asm-mips/ddb5xxx/ddb5477.h
7 * DDB 5477 specific definitions and macros.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 ***********************************************************************
15 */
16
17#ifndef __ASM_DDB5XXX_DDB5477_H
18#define __ASM_DDB5XXX_DDB5477_H
19
20#include <irq.h>
21
22/*
23 * This contains macros that are specific to DDB5477 or renamed from
24 * DDB5476.
25 */
26
27/*
28 * renamed PADRs
29 */
30#define DDB_LCS0 DDB_DCS2
31#define DDB_LCS1 DDB_DCS3
32#define DDB_LCS2 DDB_DCS4
33#define DDB_VRC5477 DDB_INTCS
34
35/*
36 * New CPU interface registers
37 */
38#define DDB_INTCTRL0 0x0400 /* Interrupt Control 0 */
39#define DDB_INTCTRL1 0x0404 /* Interrupt Control 1 */
40#define DDB_INTCTRL2 0x0408 /* Interrupt Control 2 */
41#define DDB_INTCTRL3 0x040c /* Interrupt Control 3 */
42
43#define DDB_INT0STAT 0x0420 /* INT0 Status [R] */
44#define DDB_INT1STAT 0x0428 /* INT1 Status [R] */
45#define DDB_INT2STAT 0x0430 /* INT2 Status [R] */
46#define DDB_INT3STAT 0x0438 /* INT3 Status [R] */
47#define DDB_INT4STAT 0x0440 /* INT4 Status [R] */
48#define DDB_NMISTAT 0x0450 /* NMI Status [R] */
49
50#define DDB_INTCLR32 0x0468 /* Interrupt Clear */
51
52#define DDB_INTPPES0 0x0470 /* PCI0 Interrupt Control */
53#define DDB_INTPPES1 0x0478 /* PCI1 Interrupt Control */
54
55#undef DDB_CPUSTAT /* duplicate in Vrc-5477 */
56#define DDB_CPUSTAT 0x0480 /* CPU Status [R] */
57#define DDB_BUSCTRL 0x0488 /* Internal Bus Control */
58
59
60/*
61 * Timer registers
62 */
63#define DDB_REFCTRL_L DDB_T0CTRL
64#define DDB_REFCTRL_H (DDB_T0CTRL+4)
65#define DDB_REFCNTR DDB_T0CNTR
66#define DDB_SPT0CTRL_L DDB_T1CTRL
67#define DDB_SPT0CTRL_H (DDB_T1CTRL+4)
68#define DDB_SPT1CTRL_L DDB_T2CTRL
69#define DDB_SPT1CTRL_H (DDB_T2CTRL+4)
70#define DDB_SPT1CNTR DDB_T1CTRL
71#define DDB_WDTCTRL_L DDB_T3CTRL
72#define DDB_WDTCTRL_H (DDB_T3CTRL+4)
73#define DDB_WDTCNTR DDB_T3CNTR
74
75/*
76 * DMA registers are moved. We don't care about it for now. TODO.
77 */
78
79/*
80 * BARs for ext PCI (PCI0)
81 */
82#undef DDB_BARC
83#undef DDB_BARB
84
85#define DDB_BARC0 0x0210 /* PCI0 Control */
86#define DDB_BARM010 0x0218 /* PCI0 SDRAM bank01 */
87#define DDB_BARM230 0x0220 /* PCI0 SDRAM bank23 */
88#define DDB_BAR00 0x0240 /* PCI0 LDCS0 */
89#define DDB_BAR10 0x0248 /* PCI0 LDCS1 */
90#define DDB_BAR20 0x0250 /* PCI0 LDCS2 */
91#define DDB_BAR30 0x0258 /* PCI0 LDCS3 */
92#define DDB_BAR40 0x0260 /* PCI0 LDCS4 */
93#define DDB_BAR50 0x0268 /* PCI0 LDCS5 */
94#define DDB_BARB0 0x0280 /* PCI0 BOOT */
95#define DDB_BARP00 0x0290 /* PCI0 for IOPCI Window0 */
96#define DDB_BARP10 0x0298 /* PCI0 for IOPCI Window1 */
97
98/*
99 * BARs for IOPIC (PCI1)
100 */
101#define DDB_BARC1 0x0610 /* PCI1 Control */
102#define DDB_BARM011 0x0618 /* PCI1 SDRAM bank01 */
103#define DDB_BARM231 0x0620 /* PCI1 SDRAM bank23 */
104#define DDB_BAR01 0x0640 /* PCI1 LDCS0 */
105#define DDB_BAR11 0x0648 /* PCI1 LDCS1 */
106#define DDB_BAR21 0x0650 /* PCI1 LDCS2 */
107#define DDB_BAR31 0x0658 /* PCI1 LDCS3 */
108#define DDB_BAR41 0x0660 /* PCI1 LDCS4 */
109#define DDB_BAR51 0x0668 /* PCI1 LDCS5 */
110#define DDB_BARB1 0x0680 /* PCI1 BOOT */
111#define DDB_BARP01 0x0690 /* PCI1 for ext PCI Window0 */
112#define DDB_BARP11 0x0698 /* PCI1 for ext PCI Window1 */
113
114/*
115 * Other registers for ext PCI (PCI0)
116 */
117#define DDB_PCIINIT00 0x02f0 /* PCI0 Initiator 0 */
118#define DDB_PCIINIT10 0x02f8 /* PCI0 Initiator 1 */
119
120#define DDB_PCISWP0 0x02b0 /* PCI0 Swap */
121#define DDB_PCIERR0 0x02b8 /* PCI0 Error */
122
123#define DDB_PCICTL0_L 0x02e0 /* PCI0 Control-L */
124#define DDB_PCICTL0_H 0x02e4 /* PCI0 Control-H */
125#define DDB_PCIARB0_L 0x02e8 /* PCI0 Arbitration-L */
126#define DDB_PCIARB0_H 0x02ec /* PCI0 Arbitration-H */
127
128/*
129 * Other registers for IOPCI (PCI1)
130 */
131#define DDB_IOPCIW0 0x00d0 /* PCI Address Window 0 [R/W] */
132#define DDB_IOPCIW1 0x00d8 /* PCI Address Window 1 [R/W] */
133
134#define DDB_PCIINIT01 0x06f0 /* PCI1 Initiator 0 */
135#define DDB_PCIINIT11 0x06f8 /* PCI1 Initiator 1 */
136
137#define DDB_PCISWP1 0x06b0 /* PCI1 Swap */
138#define DDB_PCIERR1 0x06b8 /* PCI1 Error */
139
140#define DDB_PCICTL1_L 0x06e0 /* PCI1 Control-L */
141#define DDB_PCICTL1_H 0x06e4 /* PCI1 Control-H */
142#define DDB_PCIARB1_L 0x06e8 /* PCI1 Arbitration-L */
143#define DDB_PCIARB1_H 0x06ec /* PCI1 Arbitration-H */
144
145/*
146 * Local Bus
147 */
148#define DDB_LCST0 0x0110 /* LB Chip Select Timing 0 */
149#define DDB_LCST1 0x0118 /* LB Chip Select Timing 1 */
150#undef DDB_LCST2
151#define DDB_LCST2 0x0120 /* LB Chip Select Timing 2 */
152#undef DDB_LCST3
153#undef DDB_LCST4
154#undef DDB_LCST5
155#undef DDB_LCST6
156#undef DDB_LCST7
157#undef DDB_LCST8
158#define DDB_ERRADR 0x0150 /* Error Address Register */
159#define DDB_ERRCS 0x0160
160#define DDB_BTM 0x0170 /* Boot Time Mode value */
161
162/*
163 * MISC registers
164 */
165#define DDB_GIUFUNSEL 0x4040 /* select dual-func pins */
166#define DDB_PIBMISC 0x0750 /* USB buffer enable / power saving */
167
168/*
169 * Memory map (physical address)
170 *
171 * Note most of the following address must be properly aligned by the
172 * corresponding size. For example, if PCI_IO_SIZE is 16MB, then
173 * PCI_IO_BASE must be aligned along 16MB boundary.
174 */
175
176/* the actual ram size is detected at run-time */
177#define DDB_SDRAM_BASE 0x00000000
178#define DDB_MAX_SDRAM_SIZE 0x08000000 /* less than 128MB */
179
180#define DDB_PCI0_MEM_BASE 0x08000000
181#define DDB_PCI0_MEM_SIZE 0x08000000 /* 128 MB */
182
183#define DDB_PCI1_MEM_BASE 0x10000000
184#define DDB_PCI1_MEM_SIZE 0x08000000 /* 128 MB */
185
186#define DDB_PCI0_CONFIG_BASE 0x18000000
187#define DDB_PCI0_CONFIG_SIZE 0x01000000 /* 16 MB */
188
189#define DDB_PCI1_CONFIG_BASE 0x19000000
190#define DDB_PCI1_CONFIG_SIZE 0x01000000 /* 16 MB */
191
192#define DDB_PCI_IO_BASE 0x1a000000 /* we concatenate two IOs */
193#define DDB_PCI0_IO_BASE 0x1a000000
194#define DDB_PCI0_IO_SIZE 0x01000000 /* 16 MB */
195#define DDB_PCI1_IO_BASE 0x1b000000
196#define DDB_PCI1_IO_SIZE 0x01000000 /* 16 MB */
197
198#define DDB_LCS0_BASE 0x1c000000 /* flash memory */
199#define DDB_LCS0_SIZE 0x01000000 /* 16 MB */
200
201#define DDB_LCS1_BASE 0x1d000000 /* misc */
202#define DDB_LCS1_SIZE 0x01000000 /* 16 MB */
203
204#define DDB_LCS2_BASE 0x1e000000 /* Mezzanine */
205#define DDB_LCS2_SIZE 0x01000000 /* 16 MB */
206
207#define DDB_VRC5477_BASE 0x1fa00000 /* VRC5477 control regs */
208#define DDB_VRC5477_SIZE 0x00200000 /* 2MB */
209
210#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */
211#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */
212
213#define DDB_LED DDB_LCS1_BASE + 0x10000
214
215
216/*
217 * DDB5477 specific functions
218 */
219#ifndef __ASSEMBLY__
220extern void ddb5477_irq_setup(void);
221
222/* route irq to cpu int pin */
223extern void ll_vrc5477_irq_route(int vrc5477_irq, int ip);
224
225/* low-level routine for enabling vrc5477 irq, bypassing high-level */
226extern void ll_vrc5477_irq_enable(int vrc5477_irq);
227extern void ll_vrc5477_irq_disable(int vrc5477_irq);
228#endif /* !__ASSEMBLY__ */
229
230/* PCI intr ack share PCIW0 with PCI IO */
231#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE
232
233/*
234 * Interrupt mapping
235 *
236 * We have three interrupt controllers:
237 *
238 * . CPU itself - 8 sources
239 * . i8259 - 16 sources
240 * . vrc5477 - 32 sources
241 *
242 * They connected as follows:
243 * all vrc5477 interrupts are routed to cpu IP2 (by software setting)
244 * all i8359 are routed to INTC in vrc5477 (by hardware connection)
245 *
246 * All VRC5477 PCI interrupts are level-triggered (no ack needed).
247 * All PCI irq but INTC are active low.
248 */
249
250/*
251 * irq number block assignment
252 */
253
254#define NUM_CPU_IRQ 8
255#define NUM_VRC5477_IRQ 32
256
257#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE
258#define VRC5477_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ)
259
260/*
261 * vrc5477 irq defs
262 */
263
264#define VRC5477_IRQ_CPCE (0 + VRC5477_IRQ_BASE) /* cpu parity error */
265#define VRC5477_IRQ_CNTD (1 + VRC5477_IRQ_BASE) /* cpu no target */
266#define VRC5477_IRQ_I2C (2 + VRC5477_IRQ_BASE) /* I2C */
267#define VRC5477_IRQ_DMA (3 + VRC5477_IRQ_BASE) /* DMA */
268#define VRC5477_IRQ_UART0 (4 + VRC5477_IRQ_BASE)
269#define VRC5477_IRQ_WDOG (5 + VRC5477_IRQ_BASE) /* watchdog timer */
270#define VRC5477_IRQ_SPT1 (6 + VRC5477_IRQ_BASE) /* special purpose timer 1 */
271#define VRC5477_IRQ_LBRT (7 + VRC5477_IRQ_BASE) /* local bus read timeout */
272#define VRC5477_IRQ_INTA (8 + VRC5477_IRQ_BASE) /* PCI INT #A */
273#define VRC5477_IRQ_INTB (9 + VRC5477_IRQ_BASE) /* PCI INT #B */
274#define VRC5477_IRQ_INTC (10 + VRC5477_IRQ_BASE) /* PCI INT #C */
275#define VRC5477_IRQ_INTD (11 + VRC5477_IRQ_BASE) /* PCI INT #D */
276#define VRC5477_IRQ_INTE (12 + VRC5477_IRQ_BASE) /* PCI INT #E */
277#define VRC5477_IRQ_RESERVED_13 (13 + VRC5477_IRQ_BASE) /* reserved */
278#define VRC5477_IRQ_PCIS (14 + VRC5477_IRQ_BASE) /* PCI SERR # */
279#define VRC5477_IRQ_PCI (15 + VRC5477_IRQ_BASE) /* PCI internal error */
280#define VRC5477_IRQ_IOPCI_INTA (16 + VRC5477_IRQ_BASE) /* USB-H */
281#define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */
282#define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */
283#define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */
284#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE)
285#define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */
286#define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */
287#define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */
288#define VRC5477_IRQ_GPT2 (24 + VRC5477_IRQ_BASE) /* general purpose timer 2 */
289#define VRC5477_IRQ_GPT3 (25 + VRC5477_IRQ_BASE) /* general purpose timer 3 */
290#define VRC5477_IRQ_GPIO (26 + VRC5477_IRQ_BASE)
291#define VRC5477_IRQ_SIO0 (27 + VRC5477_IRQ_BASE)
292#define VRC5477_IRQ_SIO1 (28 + VRC5477_IRQ_BASE)
293#define VRC5477_IRQ_RESERVED_29 (29 + VRC5477_IRQ_BASE) /* reserved */
294#define VRC5477_IRQ_IOPCISERR (30 + VRC5477_IRQ_BASE) /* IO PCI SERR # */
295#define VRC5477_IRQ_IOPCI (31 + VRC5477_IRQ_BASE)
296
297/*
298 * i2859 irq assignment
299 */
300#define I8259_IRQ_RESERVED_0 (0 + I8259A_IRQ_BASE)
301#define I8259_IRQ_KEYBOARD (1 + I8259A_IRQ_BASE) /* M1543 default */
302#define I8259_IRQ_CASCADE (2 + I8259A_IRQ_BASE)
303#define I8259_IRQ_UART_B (3 + I8259A_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */
304#define I8259_IRQ_UART_A (4 + I8259A_IRQ_BASE) /* M1543 default */
305#define I8259_IRQ_PARALLEL (5 + I8259A_IRQ_BASE) /* M1543 default */
306#define I8259_IRQ_RESERVED_6 (6 + I8259A_IRQ_BASE)
307#define I8259_IRQ_RESERVED_7 (7 + I8259A_IRQ_BASE)
308#define I8259_IRQ_RTC (8 + I8259A_IRQ_BASE) /* who set this? */
309#define I8259_IRQ_USB (9 + I8259A_IRQ_BASE) /* ddb_setup */
310#define I8259_IRQ_PMU (10 + I8259A_IRQ_BASE) /* ddb_setup */
311#define I8259_IRQ_RESERVED_11 (11 + I8259A_IRQ_BASE)
312#define I8259_IRQ_RESERVED_12 (12 + I8259A_IRQ_BASE) /* m1543_irq_setup */
313#define I8259_IRQ_RESERVED_13 (13 + I8259A_IRQ_BASE)
314#define I8259_IRQ_HDC1 (14 + I8259A_IRQ_BASE) /* default and ddb_setup */
315#define I8259_IRQ_HDC2 (15 + I8259A_IRQ_BASE) /* default */
316
317
318/*
319 * misc
320 */
321#define VRC5477_I8259_CASCADE (VRC5477_IRQ_INTC - VRC5477_IRQ_BASE)
322#define CPU_VRC5477_CASCADE 2
323
324/*
325 * debug routines
326 */
327#ifndef __ASSEMBLY__
328#if defined(CONFIG_RUNTIME_DEBUG)
329extern void vrc5477_show_pdar_regs(void);
330extern void vrc5477_show_pci_regs(void);
331extern void vrc5477_show_bar_regs(void);
332extern void vrc5477_show_int_regs(void);
333extern void vrc5477_show_all_regs(void);
334#endif
335
336/*
337 * RAM size
338 */
339extern int board_ram_size;
340#endif /* !__ASSEMBLY__ */
341
342#endif /* __ASM_DDB5XXX_DDB5477_H */
diff --git a/include/asm-mips/ddb5xxx/ddb5xxx.h b/include/asm-mips/ddb5xxx/ddb5xxx.h
deleted file mode 100644
index e97fcc8d548b..000000000000
--- a/include/asm-mips/ddb5xxx/ddb5xxx.h
+++ /dev/null
@@ -1,263 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: jsun@mvista.com or jsun@junsun.net
4 *
5 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
6 * Sony Software Development Center Europe (SDCE), Brussels
7 *
8 * include/asm-mips/ddb5xxx/ddb5xxx.h
9 * Common header for all NEC DDB 5xxx boards, including 5074, 5476, 5477.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#ifndef __ASM_DDB5XXX_DDB5XXX_H
19#define __ASM_DDB5XXX_DDB5XXX_H
20
21#include <linux/types.h>
22
23/*
24 * This file is based on the following documentation:
25 *
26 * NEC Vrc 5074 System Controller Data Sheet, June 1998
27 *
28 * [jsun] It is modified so that this file only contains the macros
29 * that are true for all DDB 5xxx boards. The modification is based on
30 *
31 * uPD31577(VRC5477) VR5432-SDRAM/PCI Bridge (Luke)
32 * Preliminary Specification Decoment, Rev 1.1, 27 Dec, 2000
33 *
34 */
35
36
37#define DDB_BASE 0xbfa00000
38#define DDB_SIZE 0x00200000 /* 2 MB */
39
40
41/*
42 * Physical Device Address Registers (PDARs)
43 */
44
45#define DDB_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */
46#define DDB_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */
47#define DDB_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */
48#define DDB_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */
49#define DDB_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */
50#define DDB_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */
51#define DDB_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */
52#define DDB_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */
53#define DDB_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */
54#define DDB_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */
55#define DDB_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */
56#define DDB_INTCS 0x0070 /* Controller Internal Registers and Devices */
57 /* [R/W] */
58#define DDB_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */
59/* Vrc5477 has two more, IOPCIW0, IOPCIW1 */
60
61/*
62 * CPU Interface Registers
63 */
64#define DDB_CPUSTAT 0x0080 /* CPU Status [R/W] */
65#define DDB_INTCTRL 0x0088 /* Interrupt Control [R/W] */
66#define DDB_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */
67#define DDB_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */
68 /* Enable [R/W] */
69#define DDB_INTCLR 0x00A0 /* Interrupt Clear [R/W] */
70#define DDB_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */
71
72
73/*
74 * Memory-Interface Registers
75 */
76#define DDB_MEMCTRL 0x00C0 /* Memory Control */
77#define DDB_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */
78#define DDB_CHKERR 0x00D0 /* Memory Check Error Status [R] */
79
80
81/*
82 * PCI-Bus Registers
83 */
84#define DDB_PCICTRL 0x00E0 /* PCI Control [R/W] */
85#define DDB_PCIARB 0x00E8 /* PCI Arbiter [R/W] */
86#define DDB_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */
87#define DDB_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */
88#define DDB_PCIERR 0x00B8 /* PCI Error [R/W] */
89
90
91/*
92 * Local-Bus Registers
93 */
94#define DDB_LCNFG 0x0100 /* Local Bus Configuration [R/W] */
95#define DDB_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */
96#define DDB_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */
97#define DDB_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */
98#define DDB_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */
99#define DDB_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */
100#define DDB_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */
101#define DDB_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */
102#define DDB_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */
103 /* Enables [R/W] */
104#define DDB_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */
105#define DDB_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */
106
107
108/*
109 * DMA Registers
110 */
111#define DDB_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */
112#define DDB_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */
113#define DDB_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */
114#define DDB_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */
115#define DDB_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */
116#define DDB_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */
117
118
119/*
120 * Timer Registers
121 */
122#define DDB_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */
123#define DDB_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */
124#define DDB_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */
125#define DDB_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */
126#define DDB_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */
127#define DDB_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */
128#define DDB_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */
129#define DDB_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */
130
131
132/*
133 * PCI Configuration Space Registers
134 */
135#define DDB_PCI_BASE 0x0200
136
137#define DDB_VID 0x0200 /* PCI Vendor ID [R] */
138#define DDB_DID 0x0202 /* PCI Device ID [R] */
139#define DDB_PCICMD 0x0204 /* PCI Command [R/W] */
140#define DDB_PCISTS 0x0206 /* PCI Status [R/W] */
141#define DDB_REVID 0x0208 /* PCI Revision ID [R] */
142#define DDB_CLASS 0x0209 /* PCI Class Code [R] */
143#define DDB_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */
144#define DDB_MLTIM 0x020D /* PCI Latency Timer [R/W] */
145#define DDB_HTYPE 0x020E /* PCI Header Type [R] */
146#define DDB_BIST 0x020F /* BIST [R] (unimplemented) */
147#define DDB_BARC 0x0210 /* PCI Base Address Register Control [R/W] */
148#define DDB_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */
149#define DDB_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */
150#define DDB_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */
151 /* (unimplemented) */
152#define DDB_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */
153#define DDB_SSID 0x022E /* PCI Sub-System ID [R/W] */
154#define DDB_ROM 0x0230 /* Expansion ROM Base Address [R] */
155 /* (unimplemented) */
156#define DDB_INTLIN 0x023C /* PCI Interrupt Line [R/W] */
157#define DDB_INTPIN 0x023D /* PCI Interrupt Pin [R] */
158#define DDB_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */
159#define DDB_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */
160#define DDB_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */
161#define DDB_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */
162#define DDB_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */
163#define DDB_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */
164#define DDB_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */
165#define DDB_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */
166#define DDB_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */
167#define DDB_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */
168
169
170/*
171 * Nile 4 Register Access
172 */
173
174static inline void ddb_sync(void)
175{
176 volatile u32 *p = (volatile u32 *)0xbfc00000;
177 (void)(*p);
178}
179
180static inline void ddb_out32(u32 offset, u32 val)
181{
182 *(volatile u32 *)(DDB_BASE+offset) = val;
183 ddb_sync();
184}
185
186static inline u32 ddb_in32(u32 offset)
187{
188 u32 val = *(volatile u32 *)(DDB_BASE+offset);
189 ddb_sync();
190 return val;
191}
192
193static inline void ddb_out16(u32 offset, u16 val)
194{
195 *(volatile u16 *)(DDB_BASE+offset) = val;
196 ddb_sync();
197}
198
199static inline u16 ddb_in16(u32 offset)
200{
201 u16 val = *(volatile u16 *)(DDB_BASE+offset);
202 ddb_sync();
203 return val;
204}
205
206static inline void ddb_out8(u32 offset, u8 val)
207{
208 *(volatile u8 *)(DDB_BASE+offset) = val;
209 ddb_sync();
210}
211
212static inline u8 ddb_in8(u32 offset)
213{
214 u8 val = *(volatile u8 *)(DDB_BASE+offset);
215 ddb_sync();
216 return val;
217}
218
219
220/*
221 * Physical Device Address Registers
222 */
223
224extern u32
225ddb_calc_pdar(u32 phys, u32 size, int width, int on_memory_bus, int pci_visible);
226extern void
227ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width,
228 int on_memory_bus, int pci_visible);
229
230/*
231 * PCI Master Registers
232 */
233
234#define DDB_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */
235#define DDB_PCICMD_IO 1 /* PCI I/O Space */
236#define DDB_PCICMD_MEM 3 /* PCI Memory Space */
237#define DDB_PCICMD_CFG 5 /* PCI Configuration Space */
238
239/*
240 * additional options for pci init reg (no shifting needed)
241 */
242#define DDB_PCI_CFGTYPE1 0x200 /* for pci init0/1 regs */
243#define DDB_PCI_ACCESS_32 0x10 /* for pci init0/1 regs */
244
245
246extern void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options);
247
248/*
249 * we need to reset pci bus when we start up and shutdown
250 */
251extern void ddb_pci_reset_bus(void);
252
253
254/*
255 * include the board dependent part
256 */
257#if defined(CONFIG_DDB5477)
258#include <asm/ddb5xxx/ddb5477.h>
259#else
260#error "Unknown DDB board!"
261#endif
262
263#endif /* __ASM_DDB5XXX_DDB5XXX_H */