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-rw-r--r--arch/arm/mach-integrator/headsmp.S37
-rw-r--r--arch/arm/mach-integrator/platsmp.c192
-rw-r--r--include/asm-arm/arch-integrator/smp.h19
3 files changed, 248 insertions, 0 deletions
diff --git a/arch/arm/mach-integrator/headsmp.S b/arch/arm/mach-integrator/headsmp.S
new file mode 100644
index 000000000000..ceaa88e30d70
--- /dev/null
+++ b/arch/arm/mach-integrator/headsmp.S
@@ -0,0 +1,37 @@
1/*
2 * linux/arch/arm/mach-integrator/headsmp.S
3 *
4 * Copyright (c) 2003 ARM Limited
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/linkage.h>
12#include <linux/init.h>
13
14 __INIT
15
16/*
17 * Integrator specific entry point for secondary CPUs. This provides
18 * a "holding pen" into which all secondary cores are held until we're
19 * ready for them to initialise.
20 */
21ENTRY(integrator_secondary_startup)
22 adr r4, 1f
23 ldmia r4, {r5, r6}
24 sub r4, r4, r5
25 ldr r6, [r6, r4]
26pen: ldr r7, [r6]
27 cmp r7, r0
28 bne pen
29
30 /*
31 * we've been released from the holding pen: secondary_stack
32 * should now contain the SVC stack for this core
33 */
34 b secondary_startup
35
361: .long .
37 .long phys_pen_release
diff --git a/arch/arm/mach-integrator/platsmp.c b/arch/arm/mach-integrator/platsmp.c
new file mode 100644
index 000000000000..ead15dfcb53d
--- /dev/null
+++ b/arch/arm/mach-integrator/platsmp.c
@@ -0,0 +1,192 @@
1/*
2 * linux/arch/arm/mach-cintegrator/platsmp.c
3 *
4 * Copyright (C) 2002 ARM Ltd.
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/errno.h>
15#include <linux/mm.h>
16
17#include <asm/atomic.h>
18#include <asm/delay.h>
19#include <asm/mmu_context.h>
20#include <asm/procinfo.h>
21#include <asm/ptrace.h>
22#include <asm/smp.h>
23
24extern void integrator_secondary_startup(void);
25
26/*
27 * control for which core is the next to come out of the secondary
28 * boot "holding pen"
29 */
30volatile int __initdata pen_release = -1;
31unsigned long __initdata phys_pen_release = 0;
32
33static DEFINE_SPINLOCK(boot_lock);
34
35void __init platform_secondary_init(unsigned int cpu)
36{
37 /*
38 * the primary core may have used a "cross call" soft interrupt
39 * to get this processor out of WFI in the BootMonitor - make
40 * sure that we are no longer being sent this soft interrupt
41 */
42 smp_cross_call_done(cpumask_of_cpu(cpu));
43
44 /*
45 * if any interrupts are already enabled for the primary
46 * core (e.g. timer irq), then they will not have been enabled
47 * for us: do so
48 */
49 secondary_scan_irqs();
50
51 /*
52 * let the primary processor know we're out of the
53 * pen, then head off into the C entry point
54 */
55 pen_release = -1;
56
57 /*
58 * Synchronise with the boot thread.
59 */
60 spin_lock(&boot_lock);
61 spin_unlock(&boot_lock);
62}
63
64int __init boot_secondary(unsigned int cpu, struct task_struct *idle)
65{
66 unsigned long timeout;
67
68 /*
69 * set synchronisation state between this boot processor
70 * and the secondary one
71 */
72 spin_lock(&boot_lock);
73
74 /*
75 * The secondary processor is waiting to be released from
76 * the holding pen - release it, then wait for it to flag
77 * that it has been released by resetting pen_release.
78 *
79 * Note that "pen_release" is the hardware CPU ID, whereas
80 * "cpu" is Linux's internal ID.
81 */
82 pen_release = cpu;
83
84 /*
85 * XXX
86 *
87 * This is a later addition to the booting protocol: the
88 * bootMonitor now puts secondary cores into WFI, so
89 * poke_milo() no longer gets the cores moving; we need
90 * to send a soft interrupt to wake the secondary core.
91 * Use smp_cross_call() for this, since there's little
92 * point duplicating the code here
93 */
94 smp_cross_call(cpumask_of_cpu(cpu));
95
96 timeout = jiffies + (1 * HZ);
97 while (time_before(jiffies, timeout)) {
98 if (pen_release == -1)
99 break;
100
101 udelay(10);
102 }
103
104 /*
105 * now the secondary core is starting up let it run its
106 * calibrations, then wait for it to finish
107 */
108 spin_unlock(&boot_lock);
109
110 return pen_release != -1 ? -ENOSYS : 0;
111}
112
113static void __init poke_milo(void)
114{
115 extern void secondary_startup(void);
116
117 /* nobody is to be released from the pen yet */
118 pen_release = -1;
119
120 phys_pen_release = virt_to_phys(&pen_release);
121
122 /*
123 * write the address of secondary startup into the system-wide
124 * flags register, then clear the bottom two bits, which is what
125 * BootMonitor is waiting for
126 */
127#if 1
128#define CINTEGRATOR_HDR_FLAGSS_OFFSET 0x30
129 __raw_writel(virt_to_phys(integrator_secondary_startup),
130 (IO_ADDRESS(INTEGRATOR_HDR_BASE) +
131 CINTEGRATOR_HDR_FLAGSS_OFFSET));
132#define CINTEGRATOR_HDR_FLAGSC_OFFSET 0x34
133 __raw_writel(3,
134 (IO_ADDRESS(INTEGRATOR_HDR_BASE) +
135 CINTEGRATOR_HDR_FLAGSC_OFFSET));
136#endif
137
138 mb();
139}
140
141void __init smp_prepare_cpus(unsigned int max_cpus)
142{
143 unsigned int ncores = get_core_count();
144 unsigned int cpu = smp_processor_id();
145 int i;
146
147 /* sanity check */
148 if (ncores == 0) {
149 printk(KERN_ERR
150 "Integrator/CP: strange CM count of 0? Default to 1\n");
151
152 ncores = 1;
153 }
154
155 if (ncores > NR_CPUS) {
156 printk(KERN_WARNING
157 "Integrator/CP: no. of cores (%d) greater than configured "
158 "maximum of %d - clipping\n",
159 ncores, NR_CPUS);
160 ncores = NR_CPUS;
161 }
162
163 /*
164 * start with some more config for the Boot CPU, now that
165 * the world is a bit more alive (which was not the case
166 * when smp_prepare_boot_cpu() was called)
167 */
168 smp_store_cpu_info(cpu);
169
170 /*
171 * are we trying to boot more cores than exist?
172 */
173 if (max_cpus > ncores)
174 max_cpus = ncores;
175
176 /*
177 * Initialise the present mask - this tells us which CPUs should
178 * be present.
179 */
180 for (i = 0; i < max_cpus; i++) {
181 cpu_set(i, cpu_present_mask);
182 }
183
184 /*
185 * Do we need any more CPUs? If so, then let them know where
186 * to start. Note that, on modern versions of MILO, the "poke"
187 * doesn't actually do anything until each individual core is
188 * sent a soft interrupt to get it out of WFI
189 */
190 if (max_cpus > 1)
191 poke_milo();
192}
diff --git a/include/asm-arm/arch-integrator/smp.h b/include/asm-arm/arch-integrator/smp.h
new file mode 100644
index 000000000000..0ec7093f7c37
--- /dev/null
+++ b/include/asm-arm/arch-integrator/smp.h
@@ -0,0 +1,19 @@
1#ifndef ASMARM_ARCH_SMP_H
2#define ASMARM_ARCH_SMP_H
3
4#include <linux/config.h>
5
6#include <asm/arch/hardware.h>
7#include <asm/io.h>
8
9#define hard_smp_processor_id() \
10 ({ \
11 unsigned int cpunum; \
12 __asm__("mrc p15, 0, %0, c0, c0, 5" \
13 : "=r" (cpunum)); \
14 cpunum &= 0x0F; \
15 })
16
17extern void secondary_scan_irqs(void);
18
19#endif