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-rw-r--r--arch/blackfin/mach-bf518/include/mach/anomaly.h21
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h22
-rw-r--r--arch/blackfin/mach-bf533/include/mach/anomaly.h10
-rw-r--r--arch/blackfin/mach-bf537/include/mach/anomaly.h11
-rw-r--r--arch/blackfin/mach-bf538/include/mach/anomaly.h16
-rw-r--r--arch/blackfin/mach-bf548/include/mach/anomaly.h16
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h13
7 files changed, 85 insertions, 24 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index 2829dd0400f1..24918c5f7ea1 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -5,13 +5,13 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2009 Analog Devices Inc. 8 * Copyright 2004-2010 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision C, 06/12/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List 14 * - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ 17/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
@@ -24,6 +24,8 @@
24 24
25/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ 25/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
26#define ANOMALY_05000074 (1) 26#define ANOMALY_05000074 (1)
27/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
28#define ANOMALY_05000119 (1)
27/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
28#define ANOMALY_05000122 (1) 30#define ANOMALY_05000122 (1)
29/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 31/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
@@ -52,6 +54,8 @@
52#define ANOMALY_05000430 (__SILICON_REVISION__ < 1) 54#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
53/* Incorrect Use of Stack in Lockbox Firmware During Authentication */ 55/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
54#define ANOMALY_05000431 (1) 56#define ANOMALY_05000431 (1)
57/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
58#define ANOMALY_05000434 (1)
55/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ 59/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
56#define ANOMALY_05000435 (__SILICON_REVISION__ < 1) 60#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
57/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ 61/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
@@ -74,14 +78,21 @@
74#define ANOMALY_05000461 (1) 78#define ANOMALY_05000461 (1)
75/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ 79/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
76#define ANOMALY_05000462 (1) 80#define ANOMALY_05000462 (1)
77/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 81/* PLL Latches Incorrect Settings During Reset */
82#define ANOMALY_05000469 (1)
83/* Incorrect Default MSEL Value in PLL_CTL */
84#define ANOMALY_05000472 (1)
85/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
78#define ANOMALY_05000473 (1) 86#define ANOMALY_05000473 (1)
79/* TESTSET Instruction Cannot Be Interrupted */ 87/* TESTSET Instruction Cannot Be Interrupted */
80#define ANOMALY_05000477 (1) 88#define ANOMALY_05000477 (1)
89/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
90#define ANOMALY_05000481 (1)
91/* IFLUSH sucks at life */
92#define ANOMALY_05000491 (1)
81 93
82/* Anomalies that don't exist on this proc */ 94/* Anomalies that don't exist on this proc */
83#define ANOMALY_05000099 (0) 95#define ANOMALY_05000099 (0)
84#define ANOMALY_05000119 (0)
85#define ANOMALY_05000120 (0) 96#define ANOMALY_05000120 (0)
86#define ANOMALY_05000125 (0) 97#define ANOMALY_05000125 (0)
87#define ANOMALY_05000149 (0) 98#define ANOMALY_05000149 (0)
@@ -94,6 +105,7 @@
94#define ANOMALY_05000198 (0) 105#define ANOMALY_05000198 (0)
95#define ANOMALY_05000202 (0) 106#define ANOMALY_05000202 (0)
96#define ANOMALY_05000215 (0) 107#define ANOMALY_05000215 (0)
108#define ANOMALY_05000219 (0)
97#define ANOMALY_05000220 (0) 109#define ANOMALY_05000220 (0)
98#define ANOMALY_05000227 (0) 110#define ANOMALY_05000227 (0)
99#define ANOMALY_05000230 (0) 111#define ANOMALY_05000230 (0)
@@ -143,5 +155,6 @@
143#define ANOMALY_05000467 (0) 155#define ANOMALY_05000467 (0)
144#define ANOMALY_05000474 (0) 156#define ANOMALY_05000474 (0)
145#define ANOMALY_05000475 (0) 157#define ANOMALY_05000475 (0)
158#define ANOMALY_05000485 (0)
146 159
147#endif 160#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index 02040df8ec80..9358afa05c90 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -5,13 +5,13 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2009 Analog Devices Inc. 8 * Copyright 2004-2010 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision D, 08/14/2009; ADSP-BF526 Blackfin Processor Anomaly List 14 * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
15 * - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List 15 * - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List
16 */ 16 */
17 17
@@ -41,7 +41,7 @@
41/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ 41/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
42#define ANOMALY_05000074 (1) 42#define ANOMALY_05000074 (1)
43/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 43/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
44#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ 44#define ANOMALY_05000119 (1)
45/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 45/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
46#define ANOMALY_05000122 (1) 46#define ANOMALY_05000122 (1)
47/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 47/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
@@ -168,6 +168,8 @@
168#define ANOMALY_05000431 (1) 168#define ANOMALY_05000431 (1)
169/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ 169/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
170#define ANOMALY_05000432 (_ANOMALY_BF526(< 1)) 170#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
171/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
172#define ANOMALY_05000434 (1)
171/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ 173/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
172#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0)) 174#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
173/* Preboot Cannot be Used to Alter the PLL_DIV Register */ 175/* Preboot Cannot be Used to Alter the PLL_DIV Register */
@@ -204,10 +206,22 @@
204#define ANOMALY_05000467 (1) 206#define ANOMALY_05000467 (1)
205/* PLL Latches Incorrect Settings During Reset */ 207/* PLL Latches Incorrect Settings During Reset */
206#define ANOMALY_05000469 (1) 208#define ANOMALY_05000469 (1)
209/* Incorrect Default MSEL Value in PLL_CTL */
210#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
207/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 211/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
208#define ANOMALY_05000473 (1) 212#define ANOMALY_05000473 (1)
213/* Possible Lockup Condition whem Modifying PLL from External Memory */
214#define ANOMALY_05000475 (1)
209/* TESTSET Instruction Cannot Be Interrupted */ 215/* TESTSET Instruction Cannot Be Interrupted */
210#define ANOMALY_05000477 (1) 216#define ANOMALY_05000477 (1)
217/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
218#define ANOMALY_05000481 (1)
219/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
220#define ANOMALY_05000483 (1)
221/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
222#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
223/* IFLUSH sucks at life */
224#define ANOMALY_05000491 (1)
211 225
212/* Anomalies that don't exist on this proc */ 226/* Anomalies that don't exist on this proc */
213#define ANOMALY_05000099 (0) 227#define ANOMALY_05000099 (0)
@@ -223,6 +237,7 @@
223#define ANOMALY_05000198 (0) 237#define ANOMALY_05000198 (0)
224#define ANOMALY_05000202 (0) 238#define ANOMALY_05000202 (0)
225#define ANOMALY_05000215 (0) 239#define ANOMALY_05000215 (0)
240#define ANOMALY_05000219 (0)
226#define ANOMALY_05000220 (0) 241#define ANOMALY_05000220 (0)
227#define ANOMALY_05000227 (0) 242#define ANOMALY_05000227 (0)
228#define ANOMALY_05000230 (0) 243#define ANOMALY_05000230 (0)
@@ -259,6 +274,5 @@
259#define ANOMALY_05000447 (0) 274#define ANOMALY_05000447 (0)
260#define ANOMALY_05000448 (0) 275#define ANOMALY_05000448 (0)
261#define ANOMALY_05000474 (0) 276#define ANOMALY_05000474 (0)
262#define ANOMALY_05000475 (0)
263 277
264#endif 278#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 9b3f7a27714d..78f872187918 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -5,7 +5,7 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2009 Analog Devices Inc. 8 * Copyright 2004-2010 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
@@ -208,8 +208,14 @@
208#define ANOMALY_05000461 (1) 208#define ANOMALY_05000461 (1)
209/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 209/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
210#define ANOMALY_05000473 (1) 210#define ANOMALY_05000473 (1)
211/* Possible Lockup Condition whem Modifying PLL from External Memory */
212#define ANOMALY_05000475 (1)
211/* TESTSET Instruction Cannot Be Interrupted */ 213/* TESTSET Instruction Cannot Be Interrupted */
212#define ANOMALY_05000477 (1) 214#define ANOMALY_05000477 (1)
215/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
216#define ANOMALY_05000481 (1)
217/* IFLUSH sucks at life */
218#define ANOMALY_05000491 (1)
213 219
214/* These anomalies have been "phased" out of analog.com anomaly sheets and are 220/* These anomalies have been "phased" out of analog.com anomaly sheets and are
215 * here to show running on older silicon just isn't feasible. 221 * here to show running on older silicon just isn't feasible.
@@ -358,6 +364,6 @@
358#define ANOMALY_05000465 (0) 364#define ANOMALY_05000465 (0)
359#define ANOMALY_05000467 (0) 365#define ANOMALY_05000467 (0)
360#define ANOMALY_05000474 (0) 366#define ANOMALY_05000474 (0)
361#define ANOMALY_05000475 (0) 367#define ANOMALY_05000485 (0)
362 368
363#endif 369#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index d2c427bc6656..43df6afd22ad 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -5,7 +5,7 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2009 Analog Devices Inc. 8 * Copyright 2004-2010 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
@@ -162,8 +162,14 @@
162#define ANOMALY_05000461 (1) 162#define ANOMALY_05000461 (1)
163/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 163/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
164#define ANOMALY_05000473 (1) 164#define ANOMALY_05000473 (1)
165/* Possible Lockup Condition whem Modifying PLL from External Memory */
166#define ANOMALY_05000475 (1)
165/* TESTSET Instruction Cannot Be Interrupted */ 167/* TESTSET Instruction Cannot Be Interrupted */
166#define ANOMALY_05000477 (1) 168#define ANOMALY_05000477 (1)
169/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
170#define ANOMALY_05000481 (1)
171/* IFLUSH sucks at life */
172#define ANOMALY_05000491 (1)
167 173
168/* Anomalies that don't exist on this proc */ 174/* Anomalies that don't exist on this proc */
169#define ANOMALY_05000099 (0) 175#define ANOMALY_05000099 (0)
@@ -179,6 +185,7 @@
179#define ANOMALY_05000198 (0) 185#define ANOMALY_05000198 (0)
180#define ANOMALY_05000202 (0) 186#define ANOMALY_05000202 (0)
181#define ANOMALY_05000215 (0) 187#define ANOMALY_05000215 (0)
188#define ANOMALY_05000219 (0)
182#define ANOMALY_05000220 (0) 189#define ANOMALY_05000220 (0)
183#define ANOMALY_05000227 (0) 190#define ANOMALY_05000227 (0)
184#define ANOMALY_05000230 (0) 191#define ANOMALY_05000230 (0)
@@ -211,6 +218,6 @@
211#define ANOMALY_05000465 (0) 218#define ANOMALY_05000465 (0)
212#define ANOMALY_05000467 (0) 219#define ANOMALY_05000467 (0)
213#define ANOMALY_05000474 (0) 220#define ANOMALY_05000474 (0)
214#define ANOMALY_05000475 (0) 221#define ANOMALY_05000485 (0)
215 222
216#endif 223#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
index d882b7e6f59b..8774b481c78e 100644
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -5,14 +5,14 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2009 Analog Devices Inc. 8 * Copyright 2004-2010 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision G, 09/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List 14 * - Revision H, 07/10/2009; ADSP-BF538/BF538F Blackfin Processor Anomaly List
15 * - Revision L, 09/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List 15 * - Revision M, 07/10/2009; ADSP-BF539/BF539F Blackfin Processor Anomaly List
16 */ 16 */
17 17
18#ifndef _MACH_ANOMALY_H_ 18#ifndef _MACH_ANOMALY_H_
@@ -132,10 +132,18 @@
132#define ANOMALY_05000443 (1) 132#define ANOMALY_05000443 (1)
133/* False Hardware Error when RETI Points to Invalid Memory */ 133/* False Hardware Error when RETI Points to Invalid Memory */
134#define ANOMALY_05000461 (1) 134#define ANOMALY_05000461 (1)
135/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
136#define ANOMALY_05000462 (1)
135/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 137/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
136#define ANOMALY_05000473 (1) 138#define ANOMALY_05000473 (1)
139/* Possible Lockup Condition whem Modifying PLL from External Memory */
140#define ANOMALY_05000475 (1)
137/* TESTSET Instruction Cannot Be Interrupted */ 141/* TESTSET Instruction Cannot Be Interrupted */
138#define ANOMALY_05000477 (1) 142#define ANOMALY_05000477 (1)
143/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
144#define ANOMALY_05000481 (1)
145/* IFLUSH sucks at life */
146#define ANOMALY_05000491 (1)
139 147
140/* Anomalies that don't exist on this proc */ 148/* Anomalies that don't exist on this proc */
141#define ANOMALY_05000099 (0) 149#define ANOMALY_05000099 (0)
@@ -185,6 +193,6 @@
185#define ANOMALY_05000465 (0) 193#define ANOMALY_05000465 (0)
186#define ANOMALY_05000467 (0) 194#define ANOMALY_05000467 (0)
187#define ANOMALY_05000474 (0) 195#define ANOMALY_05000474 (0)
188#define ANOMALY_05000475 (0) 196#define ANOMALY_05000485 (0)
189 197
190#endif 198#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index 7d08c7524498..4070079e2c00 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -5,7 +5,7 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2009 Analog Devices Inc. 8 * Copyright 2004-2010 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
@@ -28,7 +28,7 @@
28#define ANOMALY_05000119 (1) 28#define ANOMALY_05000119 (1)
29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
30#define ANOMALY_05000122 (1) 30#define ANOMALY_05000122 (1)
31/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */ 31/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
32#define ANOMALY_05000220 (1) 32#define ANOMALY_05000220 (1)
33/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 33/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
34#define ANOMALY_05000245 (1) 34#define ANOMALY_05000245 (1)
@@ -210,10 +210,16 @@
210#define ANOMALY_05000473 (1) 210#define ANOMALY_05000473 (1)
211/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */ 211/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */
212#define ANOMALY_05000474 (1) 212#define ANOMALY_05000474 (1)
213/* Core Hang With L2/L3 Configured in Writeback Cache Mode */
214#define ANOMALY_05000475 (1)
215/* TESTSET Instruction Cannot Be Interrupted */ 213/* TESTSET Instruction Cannot Be Interrupted */
216#define ANOMALY_05000477 (1) 214#define ANOMALY_05000477 (1)
215/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
216#define ANOMALY_05000481 (1)
217/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
218#define ANOMALY_05000483 (1)
219/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
220#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
221/* IFLUSH sucks at life */
222#define ANOMALY_05000491 (1)
217 223
218/* Anomalies that don't exist on this proc */ 224/* Anomalies that don't exist on this proc */
219#define ANOMALY_05000099 (0) 225#define ANOMALY_05000099 (0)
@@ -229,6 +235,7 @@
229#define ANOMALY_05000198 (0) 235#define ANOMALY_05000198 (0)
230#define ANOMALY_05000202 (0) 236#define ANOMALY_05000202 (0)
231#define ANOMALY_05000215 (0) 237#define ANOMALY_05000215 (0)
238#define ANOMALY_05000219 (0)
232#define ANOMALY_05000227 (0) 239#define ANOMALY_05000227 (0)
233#define ANOMALY_05000230 (0) 240#define ANOMALY_05000230 (0)
234#define ANOMALY_05000231 (0) 241#define ANOMALY_05000231 (0)
@@ -263,5 +270,6 @@
263#define ANOMALY_05000412 (0) 270#define ANOMALY_05000412 (0)
264#define ANOMALY_05000432 (0) 271#define ANOMALY_05000432 (0)
265#define ANOMALY_05000435 (0) 272#define ANOMALY_05000435 (0)
273#define ANOMALY_05000475 (0)
266 274
267#endif 275#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 5ddc981e9937..4c108c99cb6e 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -5,7 +5,7 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2009 Analog Devices Inc. 8 * Copyright 2004-2010 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
@@ -152,8 +152,8 @@
152#define ANOMALY_05000215 (__SILICON_REVISION__ < 5) 152#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
153/* NMI Event at Boot Time Results in Unpredictable State */ 153/* NMI Event at Boot Time Results in Unpredictable State */
154#define ANOMALY_05000219 (__SILICON_REVISION__ < 5) 154#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
155/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */ 155/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
156#define ANOMALY_05000220 (__SILICON_REVISION__ < 5) 156#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
157/* Incorrect Pulse-Width of UART Start Bit */ 157/* Incorrect Pulse-Width of UART Start Bit */
158#define ANOMALY_05000225 (__SILICON_REVISION__ < 5) 158#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
159/* Scratchpad Memory Bank Reads May Return Incorrect Data */ 159/* Scratchpad Memory Bank Reads May Return Incorrect Data */
@@ -290,10 +290,14 @@
290#define ANOMALY_05000461 (1) 290#define ANOMALY_05000461 (1)
291/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 291/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
292#define ANOMALY_05000473 (1) 292#define ANOMALY_05000473 (1)
293/* Core Hang With L2/L3 Configured in Writeback Cache Mode */ 293/* Possible Lockup Condition whem Modifying PLL from External Memory */
294#define ANOMALY_05000475 (__SILICON_REVISION__ < 4) 294#define ANOMALY_05000475 (__SILICON_REVISION__ < 4)
295/* TESTSET Instruction Cannot Be Interrupted */ 295/* TESTSET Instruction Cannot Be Interrupted */
296#define ANOMALY_05000477 (1) 296#define ANOMALY_05000477 (1)
297/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
298#define ANOMALY_05000481 (1)
299/* IFLUSH sucks at life */
300#define ANOMALY_05000491 (1)
297 301
298/* Anomalies that don't exist on this proc */ 302/* Anomalies that don't exist on this proc */
299#define ANOMALY_05000119 (0) 303#define ANOMALY_05000119 (0)
@@ -319,5 +323,6 @@
319#define ANOMALY_05000465 (0) 323#define ANOMALY_05000465 (0)
320#define ANOMALY_05000467 (0) 324#define ANOMALY_05000467 (0)
321#define ANOMALY_05000474 (0) 325#define ANOMALY_05000474 (0)
326#define ANOMALY_05000485 (0)
322 327
323#endif 328#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-02 18:29:21 -0400