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-rw-r--r--crypto/fcrypt.c8
-rw-r--r--drivers/crypto/talitos.h82
2 files changed, 45 insertions, 45 deletions
diff --git a/crypto/fcrypt.c b/crypto/fcrypt.c
index 1302f4cae337..b82d61f4e26c 100644
--- a/crypto/fcrypt.c
+++ b/crypto/fcrypt.c
@@ -73,7 +73,7 @@ do { \
73 * /afs/transarc.com/public/afsps/afs.rel31b.export-src/rxkad/sboxes.h 73 * /afs/transarc.com/public/afsps/afs.rel31b.export-src/rxkad/sboxes.h
74 */ 74 */
75#undef Z 75#undef Z
76#define Z(x) __constant_cpu_to_be32(x << 3) 76#define Z(x) cpu_to_be32(x << 3)
77static const __be32 sbox0[256] = { 77static const __be32 sbox0[256] = {
78 Z(0xea), Z(0x7f), Z(0xb2), Z(0x64), Z(0x9d), Z(0xb0), Z(0xd9), Z(0x11), 78 Z(0xea), Z(0x7f), Z(0xb2), Z(0x64), Z(0x9d), Z(0xb0), Z(0xd9), Z(0x11),
79 Z(0xcd), Z(0x86), Z(0x86), Z(0x91), Z(0x0a), Z(0xb2), Z(0x93), Z(0x06), 79 Z(0xcd), Z(0x86), Z(0x86), Z(0x91), Z(0x0a), Z(0xb2), Z(0x93), Z(0x06),
@@ -110,7 +110,7 @@ static const __be32 sbox0[256] = {
110}; 110};
111 111
112#undef Z 112#undef Z
113#define Z(x) __constant_cpu_to_be32((x << 27) | (x >> 5)) 113#define Z(x) cpu_to_be32((x << 27) | (x >> 5))
114static const __be32 sbox1[256] = { 114static const __be32 sbox1[256] = {
115 Z(0x77), Z(0x14), Z(0xa6), Z(0xfe), Z(0xb2), Z(0x5e), Z(0x8c), Z(0x3e), 115 Z(0x77), Z(0x14), Z(0xa6), Z(0xfe), Z(0xb2), Z(0x5e), Z(0x8c), Z(0x3e),
116 Z(0x67), Z(0x6c), Z(0xa1), Z(0x0d), Z(0xc2), Z(0xa2), Z(0xc1), Z(0x85), 116 Z(0x67), Z(0x6c), Z(0xa1), Z(0x0d), Z(0xc2), Z(0xa2), Z(0xc1), Z(0x85),
@@ -147,7 +147,7 @@ static const __be32 sbox1[256] = {
147}; 147};
148 148
149#undef Z 149#undef Z
150#define Z(x) __constant_cpu_to_be32(x << 11) 150#define Z(x) cpu_to_be32(x << 11)
151static const __be32 sbox2[256] = { 151static const __be32 sbox2[256] = {
152 Z(0xf0), Z(0x37), Z(0x24), Z(0x53), Z(0x2a), Z(0x03), Z(0x83), Z(0x86), 152 Z(0xf0), Z(0x37), Z(0x24), Z(0x53), Z(0x2a), Z(0x03), Z(0x83), Z(0x86),
153 Z(0xd1), Z(0xec), Z(0x50), Z(0xf0), Z(0x42), Z(0x78), Z(0x2f), Z(0x6d), 153 Z(0xd1), Z(0xec), Z(0x50), Z(0xf0), Z(0x42), Z(0x78), Z(0x2f), Z(0x6d),
@@ -184,7 +184,7 @@ static const __be32 sbox2[256] = {
184}; 184};
185 185
186#undef Z 186#undef Z
187#define Z(x) __constant_cpu_to_be32(x << 19) 187#define Z(x) cpu_to_be32(x << 19)
188static const __be32 sbox3[256] = { 188static const __be32 sbox3[256] = {
189 Z(0xa9), Z(0x2a), Z(0x48), Z(0x51), Z(0x84), Z(0x7e), Z(0x49), Z(0xe2), 189 Z(0xa9), Z(0x2a), Z(0x48), Z(0x51), Z(0x84), Z(0x7e), Z(0x49), Z(0xe2),
190 Z(0xb5), Z(0xb7), Z(0x42), Z(0x33), Z(0x7d), Z(0x5d), Z(0xa6), Z(0x12), 190 Z(0xb5), Z(0xb7), Z(0x42), Z(0x33), Z(0x7d), Z(0x5d), Z(0xa6), Z(0x12),
diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos.h
index 125560a1d5f7..575981f0cfda 100644
--- a/drivers/crypto/talitos.h
+++ b/drivers/crypto/talitos.h
@@ -134,34 +134,34 @@
134 */ 134 */
135 135
136/* written back when done */ 136/* written back when done */
137#define DESC_HDR_DONE __constant_cpu_to_be32(0xff000000) 137#define DESC_HDR_DONE cpu_to_be32(0xff000000)
138#define DESC_HDR_LO_ICCR1_MASK __constant_cpu_to_be32(0x00180000) 138#define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
139#define DESC_HDR_LO_ICCR1_PASS __constant_cpu_to_be32(0x00080000) 139#define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
140#define DESC_HDR_LO_ICCR1_FAIL __constant_cpu_to_be32(0x00100000) 140#define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
141 141
142/* primary execution unit select */ 142/* primary execution unit select */
143#define DESC_HDR_SEL0_MASK __constant_cpu_to_be32(0xf0000000) 143#define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
144#define DESC_HDR_SEL0_AFEU __constant_cpu_to_be32(0x10000000) 144#define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
145#define DESC_HDR_SEL0_DEU __constant_cpu_to_be32(0x20000000) 145#define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
146#define DESC_HDR_SEL0_MDEUA __constant_cpu_to_be32(0x30000000) 146#define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
147#define DESC_HDR_SEL0_MDEUB __constant_cpu_to_be32(0xb0000000) 147#define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
148#define DESC_HDR_SEL0_RNG __constant_cpu_to_be32(0x40000000) 148#define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
149#define DESC_HDR_SEL0_PKEU __constant_cpu_to_be32(0x50000000) 149#define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
150#define DESC_HDR_SEL0_AESU __constant_cpu_to_be32(0x60000000) 150#define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
151#define DESC_HDR_SEL0_KEU __constant_cpu_to_be32(0x70000000) 151#define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
152#define DESC_HDR_SEL0_CRCU __constant_cpu_to_be32(0x80000000) 152#define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
153 153
154/* primary execution unit mode (MODE0) and derivatives */ 154/* primary execution unit mode (MODE0) and derivatives */
155#define DESC_HDR_MODE0_ENCRYPT __constant_cpu_to_be32(0x00100000) 155#define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
156#define DESC_HDR_MODE0_AESU_CBC __constant_cpu_to_be32(0x00200000) 156#define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
157#define DESC_HDR_MODE0_DEU_CBC __constant_cpu_to_be32(0x00400000) 157#define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
158#define DESC_HDR_MODE0_DEU_3DES __constant_cpu_to_be32(0x00200000) 158#define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
159#define DESC_HDR_MODE0_MDEU_INIT __constant_cpu_to_be32(0x01000000) 159#define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
160#define DESC_HDR_MODE0_MDEU_HMAC __constant_cpu_to_be32(0x00800000) 160#define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
161#define DESC_HDR_MODE0_MDEU_PAD __constant_cpu_to_be32(0x00400000) 161#define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
162#define DESC_HDR_MODE0_MDEU_MD5 __constant_cpu_to_be32(0x00200000) 162#define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
163#define DESC_HDR_MODE0_MDEU_SHA256 __constant_cpu_to_be32(0x00100000) 163#define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
164#define DESC_HDR_MODE0_MDEU_SHA1 __constant_cpu_to_be32(0x00000000) 164#define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
165#define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \ 165#define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \
166 DESC_HDR_MODE0_MDEU_HMAC) 166 DESC_HDR_MODE0_MDEU_HMAC)
167#define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \ 167#define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
@@ -170,19 +170,19 @@
170 DESC_HDR_MODE0_MDEU_HMAC) 170 DESC_HDR_MODE0_MDEU_HMAC)
171 171
172/* secondary execution unit select (SEL1) */ 172/* secondary execution unit select (SEL1) */
173#define DESC_HDR_SEL1_MASK __constant_cpu_to_be32(0x000f0000) 173#define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
174#define DESC_HDR_SEL1_MDEUA __constant_cpu_to_be32(0x00030000) 174#define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
175#define DESC_HDR_SEL1_MDEUB __constant_cpu_to_be32(0x000b0000) 175#define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
176#define DESC_HDR_SEL1_CRCU __constant_cpu_to_be32(0x00080000) 176#define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
177 177
178/* secondary execution unit mode (MODE1) and derivatives */ 178/* secondary execution unit mode (MODE1) and derivatives */
179#define DESC_HDR_MODE1_MDEU_CICV __constant_cpu_to_be32(0x00004000) 179#define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
180#define DESC_HDR_MODE1_MDEU_INIT __constant_cpu_to_be32(0x00001000) 180#define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
181#define DESC_HDR_MODE1_MDEU_HMAC __constant_cpu_to_be32(0x00000800) 181#define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
182#define DESC_HDR_MODE1_MDEU_PAD __constant_cpu_to_be32(0x00000400) 182#define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
183#define DESC_HDR_MODE1_MDEU_MD5 __constant_cpu_to_be32(0x00000200) 183#define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
184#define DESC_HDR_MODE1_MDEU_SHA256 __constant_cpu_to_be32(0x00000100) 184#define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
185#define DESC_HDR_MODE1_MDEU_SHA1 __constant_cpu_to_be32(0x00000000) 185#define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
186#define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \ 186#define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \
187 DESC_HDR_MODE1_MDEU_HMAC) 187 DESC_HDR_MODE1_MDEU_HMAC)
188#define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \ 188#define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
@@ -191,16 +191,16 @@
191 DESC_HDR_MODE1_MDEU_HMAC) 191 DESC_HDR_MODE1_MDEU_HMAC)
192 192
193/* direction of overall data flow (DIR) */ 193/* direction of overall data flow (DIR) */
194#define DESC_HDR_DIR_INBOUND __constant_cpu_to_be32(0x00000002) 194#define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
195 195
196/* request done notification (DN) */ 196/* request done notification (DN) */
197#define DESC_HDR_DONE_NOTIFY __constant_cpu_to_be32(0x00000001) 197#define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
198 198
199/* descriptor types */ 199/* descriptor types */
200#define DESC_HDR_TYPE_AESU_CTR_NONSNOOP __constant_cpu_to_be32(0 << 3) 200#define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
201#define DESC_HDR_TYPE_IPSEC_ESP __constant_cpu_to_be32(1 << 3) 201#define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
202#define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU __constant_cpu_to_be32(2 << 3) 202#define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
203#define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU __constant_cpu_to_be32(4 << 3) 203#define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)
204 204
205/* link table extent field bits */ 205/* link table extent field bits */
206#define DESC_PTR_LNKTBL_JUMP 0x80 206#define DESC_PTR_LNKTBL_JUMP 0x80
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 06:16:38 -0500