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-rw-r--r--Documentation/arm/memory.txt8
-rw-r--r--Documentation/arm/tcm.txt30
-rw-r--r--arch/arm/Kconfig7
-rw-r--r--arch/arm/include/asm/mach/map.h2
-rw-r--r--arch/arm/include/asm/memory.h9
-rw-r--r--arch/arm/include/asm/system.h2
-rw-r--r--arch/arm/kernel/machine_kexec.c10
-rw-r--r--arch/arm/kernel/process.c29
-rw-r--r--arch/arm/kernel/smp.c17
-rw-r--r--arch/arm/kernel/smp_twd.c3
-rw-r--r--arch/arm/kernel/tcm.c118
-rw-r--r--arch/arm/mach-integrator/pci_v3.c8
-rw-r--r--arch/arm/mach-iop13xx/pci.c2
-rw-r--r--arch/arm/mach-ixp2000/pci.c2
-rw-r--r--arch/arm/mach-ixp23xx/pci.c2
-rw-r--r--arch/arm/mach-ixp4xx/common-pci.c3
-rw-r--r--arch/arm/mach-ks8695/pci.c4
-rw-r--r--arch/arm/mach-u300/include/mach/memory.h8
-rw-r--r--arch/arm/mm/alignment.c16
-rw-r--r--arch/arm/mm/dma-mapping.c15
-rw-r--r--arch/arm/mm/fault.c56
-rw-r--r--arch/arm/mm/init.c13
-rw-r--r--arch/arm/mm/ioremap.c74
-rw-r--r--arch/arm/mm/mmu.c13
-rw-r--r--arch/arm/mm/proc-arm1020.S6
-rw-r--r--arch/arm/mm/proc-arm1020e.S6
-rw-r--r--arch/arm/mm/proc-arm1022.S6
-rw-r--r--arch/arm/mm/proc-arm1026.S6
-rw-r--r--arch/arm/mm/proc-arm6_7.S2
-rw-r--r--arch/arm/mm/proc-arm720.S6
-rw-r--r--arch/arm/mm/proc-arm740.S6
-rw-r--r--arch/arm/mm/proc-arm7tdmi.S2
-rw-r--r--arch/arm/mm/proc-arm920.S10
-rw-r--r--arch/arm/mm/proc-arm922.S10
-rw-r--r--arch/arm/mm/proc-arm925.S6
-rw-r--r--arch/arm/mm/proc-arm926.S6
-rw-r--r--arch/arm/mm/proc-arm940.S6
-rw-r--r--arch/arm/mm/proc-arm946.S6
-rw-r--r--arch/arm/mm/proc-arm9tdmi.S2
-rw-r--r--arch/arm/mm/proc-fa526.S6
-rw-r--r--arch/arm/mm/proc-feroceon.S7
-rw-r--r--arch/arm/mm/proc-mohawk.S6
-rw-r--r--arch/arm/mm/proc-sa110.S8
-rw-r--r--arch/arm/mm/proc-sa1100.S6
-rw-r--r--arch/arm/mm/proc-v6.S5
-rw-r--r--arch/arm/mm/proc-v7.S5
-rw-r--r--arch/arm/mm/proc-xsc3.S6
-rw-r--r--arch/arm/mm/proc-xscale.S6
-rw-r--r--arch/arm/mm/vmregion.c5
-rw-r--r--arch/arm/mm/vmregion.h2
-rw-r--r--arch/arm/plat-iop/pci.c2
-rw-r--r--drivers/gpio/pl061.c4
-rw-r--r--drivers/mmc/host/mmci.c148
-rw-r--r--drivers/mmc/host/mmci.h39
-rw-r--r--drivers/rtc/rtc-pl031.c2
-rw-r--r--drivers/serial/amba-pl010.c2
-rw-r--r--drivers/serial/amba-pl011.c90
-rw-r--r--include/linux/amba/mmci.h10
-rw-r--r--include/linux/amba/serial.h3
-rw-r--r--lib/atomic64_test.c2
60 files changed, 475 insertions, 426 deletions
diff --git a/Documentation/arm/memory.txt b/Documentation/arm/memory.txt
index eb0fae18ffb1..771d48d3b335 100644
--- a/Documentation/arm/memory.txt
+++ b/Documentation/arm/memory.txt
@@ -33,7 +33,13 @@ ffff0000 ffff0fff CPU vector page.
33 33
34fffe0000 fffeffff XScale cache flush area. This is used 34fffe0000 fffeffff XScale cache flush area. This is used
35 in proc-xscale.S to flush the whole data 35 in proc-xscale.S to flush the whole data
36 cache. Free for other usage on non-XScale. 36 cache. (XScale does not have TCM.)
37
38fffe8000 fffeffff DTCM mapping area for platforms with
39 DTCM mounted inside the CPU.
40
41fffe0000 fffe7fff ITCM mapping area for platforms with
42 ITCM mounted inside the CPU.
37 43
38fff00000 fffdffff Fixmap mapping region. Addresses provided 44fff00000 fffdffff Fixmap mapping region. Addresses provided
39 by fix_to_virt() will be located here. 45 by fix_to_virt() will be located here.
diff --git a/Documentation/arm/tcm.txt b/Documentation/arm/tcm.txt
index 77fd9376e6d7..7c15871c1885 100644
--- a/Documentation/arm/tcm.txt
+++ b/Documentation/arm/tcm.txt
@@ -19,8 +19,8 @@ defines a CPUID_TCM register that you can read out from the
19system control coprocessor. Documentation from ARM can be found 19system control coprocessor. Documentation from ARM can be found
20at http://infocenter.arm.com, search for "TCM Status Register" 20at http://infocenter.arm.com, search for "TCM Status Register"
21to see documents for all CPUs. Reading this register you can 21to see documents for all CPUs. Reading this register you can
22determine if ITCM (bit 0) and/or DTCM (bit 16) is present in the 22determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
23machine. 23in the machine.
24 24
25There is further a TCM region register (search for "TCM Region 25There is further a TCM region register (search for "TCM Region
26Registers" at the ARM site) that can report and modify the location 26Registers" at the ARM site) that can report and modify the location
@@ -35,7 +35,15 @@ The TCM memory can then be remapped to another address again using
35the MMU, but notice that the TCM if often used in situations where 35the MMU, but notice that the TCM if often used in situations where
36the MMU is turned off. To avoid confusion the current Linux 36the MMU is turned off. To avoid confusion the current Linux
37implementation will map the TCM 1 to 1 from physical to virtual 37implementation will map the TCM 1 to 1 from physical to virtual
38memory in the location specified by the machine. 38memory in the location specified by the kernel. Currently Linux
39will map ITCM to 0xfffe0000 and on, and DTCM to 0xfffe8000 and
40on, supporting a maximum of 32KiB of ITCM and 32KiB of DTCM.
41
42Newer versions of the region registers also support dividing these
43TCMs in two separate banks, so for example an 8KiB ITCM is divided
44into two 4KiB banks with its own control registers. The idea is to
45be able to lock and hide one of the banks for use by the secure
46world (TrustZone).
39 47
40TCM is used for a few things: 48TCM is used for a few things:
41 49
@@ -65,18 +73,18 @@ in <asm/tcm.h>. Using this interface it is possible to:
65 memory. Such a heap is great for things like saving 73 memory. Such a heap is great for things like saving
66 device state when shutting off device power domains. 74 device state when shutting off device power domains.
67 75
68A machine that has TCM memory shall select HAVE_TCM in 76A machine that has TCM memory shall select HAVE_TCM from
69arch/arm/Kconfig for itself, and then the 77arch/arm/Kconfig for itself. Code that needs to use TCM shall
70rest of the functionality will depend on the physical 78#include <asm/tcm.h>
71location and size of ITCM and DTCM to be defined in
72mach/memory.h for the machine. Code that needs to use
73TCM shall #include <asm/tcm.h> If the TCM is not located
74at the place given in memory.h it will be moved using
75the TCM Region registers.
76 79
77Functions to go into itcm can be tagged like this: 80Functions to go into itcm can be tagged like this:
78int __tcmfunc foo(int bar); 81int __tcmfunc foo(int bar);
79 82
83Since these are marked to become long_calls and you may want
84to have functions called locally inside the TCM without
85wasting space, there is also the __tcmlocalfunc prefix that
86will make the call relative.
87
80Variables to go into dtcm can be tagged like this: 88Variables to go into dtcm can be tagged like this:
81int __tcmdata foo; 89int __tcmdata foo;
82 90
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4047f5724da3..ba1ac08b4e02 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -57,7 +57,7 @@ config GENERIC_CLOCKEVENTS
57config GENERIC_CLOCKEVENTS_BROADCAST 57config GENERIC_CLOCKEVENTS_BROADCAST
58 bool 58 bool
59 depends on GENERIC_CLOCKEVENTS 59 depends on GENERIC_CLOCKEVENTS
60 default y if SMP && !LOCAL_TIMERS 60 default y if SMP
61 61
62config HAVE_TCM 62config HAVE_TCM
63 bool 63 bool
@@ -1263,8 +1263,7 @@ config HW_PERF_EVENTS
1263 disabled, perf events will use software events only. 1263 disabled, perf events will use software events only.
1264 1264
1265config SPARSE_IRQ 1265config SPARSE_IRQ
1266 bool "Support sparse irq numbering" 1266 def_bool n
1267 depends on EXPERIMENTAL
1268 help 1267 help
1269 This enables support for sparse irqs. This is useful in general 1268 This enables support for sparse irqs. This is useful in general
1270 as most CPUs have a fairly sparse array of IRQ vectors, which 1269 as most CPUs have a fairly sparse array of IRQ vectors, which
@@ -1272,8 +1271,6 @@ config SPARSE_IRQ
1272 number of off-chip IRQs will want to treat this as 1271 number of off-chip IRQs will want to treat this as
1273 experimental until they have been independently verified. 1272 experimental until they have been independently verified.
1274 1273
1275 If you don't know what to do here, say N.
1276
1277source "mm/Kconfig" 1274source "mm/Kconfig"
1278 1275
1279config FORCE_MAX_ZONEORDER 1276config FORCE_MAX_ZONEORDER
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index 742c2aaeb020..d2fedb5aeb1f 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -27,6 +27,8 @@ struct map_desc {
27#define MT_MEMORY 9 27#define MT_MEMORY 9
28#define MT_ROM 10 28#define MT_ROM 10
29#define MT_MEMORY_NONCACHED 11 29#define MT_MEMORY_NONCACHED 11
30#define MT_MEMORY_DTCM 12
31#define MT_MEMORY_ITCM 13
30 32
31#ifdef CONFIG_MMU 33#ifdef CONFIG_MMU
32extern void iotable_init(struct map_desc *, int); 34extern void iotable_init(struct map_desc *, int);
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 82df0ae71bb4..23c2e8e5c0fa 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -124,6 +124,15 @@
124#endif /* !CONFIG_MMU */ 124#endif /* !CONFIG_MMU */
125 125
126/* 126/*
127 * We fix the TCM memories max 32 KiB ITCM resp DTCM at these
128 * locations
129 */
130#ifdef CONFIG_HAVE_TCM
131#define ITCM_OFFSET UL(0xfffe0000)
132#define DTCM_OFFSET UL(0xfffe8000)
133#endif
134
135/*
127 * Physical vs virtual RAM address space conversion. These are 136 * Physical vs virtual RAM address space conversion. These are
128 * private definitions which should NOT be used outside memory.h 137 * private definitions which should NOT be used outside memory.h
129 * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. 138 * files. Use virt_to_phys/phys_to_virt/__pa/__va instead.
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 5f4f48002734..8ba1ccf82a02 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -83,7 +83,7 @@ void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
83 83
84void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, 84void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
85 struct pt_regs *), 85 struct pt_regs *),
86 int sig, const char *name); 86 int sig, int code, const char *name);
87 87
88#define xchg(ptr,x) \ 88#define xchg(ptr,x) \
89 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) 89 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 81e989858d42..1fc74cbd1a19 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -37,10 +37,6 @@ void machine_kexec_cleanup(struct kimage *image)
37{ 37{
38} 38}
39 39
40void machine_shutdown(void)
41{
42}
43
44void machine_crash_shutdown(struct pt_regs *regs) 40void machine_crash_shutdown(struct pt_regs *regs)
45{ 41{
46 local_irq_disable(); 42 local_irq_disable();
@@ -78,7 +74,11 @@ void machine_kexec(struct kimage *image)
78 (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE); 74 (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
79 printk(KERN_INFO "Bye!\n"); 75 printk(KERN_INFO "Bye!\n");
80 76
81 cpu_proc_fin(); 77 local_irq_disable();
78 local_fiq_disable();
82 setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/ 79 setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
80 flush_cache_all();
81 cpu_proc_fin();
82 flush_cache_all();
83 cpu_reset(reboot_code_buffer_phys); 83 cpu_reset(reboot_code_buffer_phys);
84} 84}
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index a4a9cc88bec7..2e2ec97cc50c 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -29,6 +29,7 @@
29#include <linux/utsname.h> 29#include <linux/utsname.h>
30#include <linux/uaccess.h> 30#include <linux/uaccess.h>
31 31
32#include <asm/cacheflush.h>
32#include <asm/leds.h> 33#include <asm/leds.h>
33#include <asm/processor.h> 34#include <asm/processor.h>
34#include <asm/system.h> 35#include <asm/system.h>
@@ -84,10 +85,9 @@ __setup("hlt", hlt_setup);
84 85
85void arm_machine_restart(char mode, const char *cmd) 86void arm_machine_restart(char mode, const char *cmd)
86{ 87{
87 /* 88 /* Disable interrupts first */
88 * Clean and disable cache, and turn off interrupts 89 local_irq_disable();
89 */ 90 local_fiq_disable();
90 cpu_proc_fin();
91 91
92 /* 92 /*
93 * Tell the mm system that we are going to reboot - 93 * Tell the mm system that we are going to reboot -
@@ -96,6 +96,15 @@ void arm_machine_restart(char mode, const char *cmd)
96 */ 96 */
97 setup_mm_for_reboot(mode); 97 setup_mm_for_reboot(mode);
98 98
99 /* Clean and invalidate caches */
100 flush_cache_all();
101
102 /* Turn off caching */
103 cpu_proc_fin();
104
105 /* Push out any further dirty data, and ensure cache is empty */
106 flush_cache_all();
107
99 /* 108 /*
100 * Now call the architecture specific reboot code. 109 * Now call the architecture specific reboot code.
101 */ 110 */
@@ -189,19 +198,29 @@ int __init reboot_setup(char *str)
189 198
190__setup("reboot=", reboot_setup); 199__setup("reboot=", reboot_setup);
191 200
192void machine_halt(void) 201void machine_shutdown(void)
193{ 202{
203#ifdef CONFIG_SMP
204 smp_send_stop();
205#endif
194} 206}
195 207
208void machine_halt(void)
209{
210 machine_shutdown();
211 while (1);
212}
196 213
197void machine_power_off(void) 214void machine_power_off(void)
198{ 215{
216 machine_shutdown();
199 if (pm_power_off) 217 if (pm_power_off)
200 pm_power_off(); 218 pm_power_off();
201} 219}
202 220
203void machine_restart(char *cmd) 221void machine_restart(char *cmd)
204{ 222{
223 machine_shutdown();
205 arm_pm_restart(reboot_mode, cmd); 224 arm_pm_restart(reboot_mode, cmd);
206} 225}
207 226
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index b8c3d0f689d9..40dc74f2b27f 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -429,7 +429,11 @@ static void smp_timer_broadcast(const struct cpumask *mask)
429{ 429{
430 send_ipi_message(mask, IPI_TIMER); 430 send_ipi_message(mask, IPI_TIMER);
431} 431}
432#else
433#define smp_timer_broadcast NULL
434#endif
432 435
436#ifndef CONFIG_LOCAL_TIMERS
433static void broadcast_timer_set_mode(enum clock_event_mode mode, 437static void broadcast_timer_set_mode(enum clock_event_mode mode,
434 struct clock_event_device *evt) 438 struct clock_event_device *evt)
435{ 439{
@@ -444,7 +448,6 @@ static void local_timer_setup(struct clock_event_device *evt)
444 evt->rating = 400; 448 evt->rating = 400;
445 evt->mult = 1; 449 evt->mult = 1;
446 evt->set_mode = broadcast_timer_set_mode; 450 evt->set_mode = broadcast_timer_set_mode;
447 evt->broadcast = smp_timer_broadcast;
448 451
449 clockevents_register_device(evt); 452 clockevents_register_device(evt);
450} 453}
@@ -456,6 +459,7 @@ void __cpuinit percpu_timer_setup(void)
456 struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu); 459 struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
457 460
458 evt->cpumask = cpumask_of(cpu); 461 evt->cpumask = cpumask_of(cpu);
462 evt->broadcast = smp_timer_broadcast;
459 463
460 local_timer_setup(evt); 464 local_timer_setup(evt);
461} 465}
@@ -467,10 +471,13 @@ static DEFINE_SPINLOCK(stop_lock);
467 */ 471 */
468static void ipi_cpu_stop(unsigned int cpu) 472static void ipi_cpu_stop(unsigned int cpu)
469{ 473{
470 spin_lock(&stop_lock); 474 if (system_state == SYSTEM_BOOTING ||
471 printk(KERN_CRIT "CPU%u: stopping\n", cpu); 475 system_state == SYSTEM_RUNNING) {
472 dump_stack(); 476 spin_lock(&stop_lock);
473 spin_unlock(&stop_lock); 477 printk(KERN_CRIT "CPU%u: stopping\n", cpu);
478 dump_stack();
479 spin_unlock(&stop_lock);
480 }
474 481
475 set_cpu_online(cpu, false); 482 set_cpu_online(cpu, false);
476 483
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 7c5f0c024db7..35882fbf37f9 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -132,7 +132,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
132 twd_calibrate_rate(); 132 twd_calibrate_rate();
133 133
134 clk->name = "local_timer"; 134 clk->name = "local_timer";
135 clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; 135 clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
136 CLOCK_EVT_FEAT_C3STOP;
136 clk->rating = 350; 137 clk->rating = 350;
137 clk->set_mode = twd_set_mode; 138 clk->set_mode = twd_set_mode;
138 clk->set_next_event = twd_set_next_event; 139 clk->set_next_event = twd_set_next_event;
diff --git a/arch/arm/kernel/tcm.c b/arch/arm/kernel/tcm.c
index e50303868f1b..26685c2f7a49 100644
--- a/arch/arm/kernel/tcm.c
+++ b/arch/arm/kernel/tcm.c
@@ -13,38 +13,35 @@
13#include <linux/ioport.h> 13#include <linux/ioport.h>
14#include <linux/genalloc.h> 14#include <linux/genalloc.h>
15#include <linux/string.h> /* memcpy */ 15#include <linux/string.h> /* memcpy */
16#include <asm/page.h> /* PAGE_SHIFT */
17#include <asm/cputype.h> 16#include <asm/cputype.h>
18#include <asm/mach/map.h> 17#include <asm/mach/map.h>
19#include <mach/memory.h> 18#include <mach/memory.h>
20#include "tcm.h" 19#include "tcm.h"
21 20
22/* Scream and warn about misuse */
23#if !defined(ITCM_OFFSET) || !defined(ITCM_END) || \
24 !defined(DTCM_OFFSET) || !defined(DTCM_END)
25#error "TCM support selected but offsets not defined!"
26#endif
27
28static struct gen_pool *tcm_pool; 21static struct gen_pool *tcm_pool;
29 22
30/* TCM section definitions from the linker */ 23/* TCM section definitions from the linker */
31extern char __itcm_start, __sitcm_text, __eitcm_text; 24extern char __itcm_start, __sitcm_text, __eitcm_text;
32extern char __dtcm_start, __sdtcm_data, __edtcm_data; 25extern char __dtcm_start, __sdtcm_data, __edtcm_data;
33 26
27/* These will be increased as we run */
28u32 dtcm_end = DTCM_OFFSET;
29u32 itcm_end = ITCM_OFFSET;
30
34/* 31/*
35 * TCM memory resources 32 * TCM memory resources
36 */ 33 */
37static struct resource dtcm_res = { 34static struct resource dtcm_res = {
38 .name = "DTCM RAM", 35 .name = "DTCM RAM",
39 .start = DTCM_OFFSET, 36 .start = DTCM_OFFSET,
40 .end = DTCM_END, 37 .end = DTCM_OFFSET,
41 .flags = IORESOURCE_MEM 38 .flags = IORESOURCE_MEM
42}; 39};
43 40
44static struct resource itcm_res = { 41static struct resource itcm_res = {
45 .name = "ITCM RAM", 42 .name = "ITCM RAM",
46 .start = ITCM_OFFSET, 43 .start = ITCM_OFFSET,
47 .end = ITCM_END, 44 .end = ITCM_OFFSET,
48 .flags = IORESOURCE_MEM 45 .flags = IORESOURCE_MEM
49}; 46};
50 47
@@ -52,8 +49,8 @@ static struct map_desc dtcm_iomap[] __initdata = {
52 { 49 {
53 .virtual = DTCM_OFFSET, 50 .virtual = DTCM_OFFSET,
54 .pfn = __phys_to_pfn(DTCM_OFFSET), 51 .pfn = __phys_to_pfn(DTCM_OFFSET),
55 .length = (DTCM_END - DTCM_OFFSET + 1), 52 .length = 0,
56 .type = MT_UNCACHED 53 .type = MT_MEMORY_DTCM
57 } 54 }
58}; 55};
59 56
@@ -61,8 +58,8 @@ static struct map_desc itcm_iomap[] __initdata = {
61 { 58 {
62 .virtual = ITCM_OFFSET, 59 .virtual = ITCM_OFFSET,
63 .pfn = __phys_to_pfn(ITCM_OFFSET), 60 .pfn = __phys_to_pfn(ITCM_OFFSET),
64 .length = (ITCM_END - ITCM_OFFSET + 1), 61 .length = 0,
65 .type = MT_UNCACHED 62 .type = MT_MEMORY_ITCM
66 } 63 }
67}; 64};
68 65
@@ -93,14 +90,24 @@ void tcm_free(void *addr, size_t len)
93} 90}
94EXPORT_SYMBOL(tcm_free); 91EXPORT_SYMBOL(tcm_free);
95 92
96 93static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks,
97static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size) 94 u32 *offset)
98{ 95{
99 const int tcm_sizes[16] = { 0, -1, -1, 4, 8, 16, 32, 64, 128, 96 const int tcm_sizes[16] = { 0, -1, -1, 4, 8, 16, 32, 64, 128,
100 256, 512, 1024, -1, -1, -1, -1 }; 97 256, 512, 1024, -1, -1, -1, -1 };
101 u32 tcm_region; 98 u32 tcm_region;
102 int tcm_size; 99 int tcm_size;
103 100
101 /*
102 * If there are more than one TCM bank of this type,
103 * select the TCM bank to operate on in the TCM selection
104 * register.
105 */
106 if (banks > 1)
107 asm("mcr p15, 0, %0, c9, c2, 0"
108 : /* No output operands */
109 : "r" (bank));
110
104 /* Read the special TCM region register c9, 0 */ 111 /* Read the special TCM region register c9, 0 */
105 if (!type) 112 if (!type)
106 asm("mrc p15, 0, %0, c9, c1, 0" 113 asm("mrc p15, 0, %0, c9, c1, 0"
@@ -111,26 +118,24 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
111 118
112 tcm_size = tcm_sizes[(tcm_region >> 2) & 0x0f]; 119 tcm_size = tcm_sizes[(tcm_region >> 2) & 0x0f];
113 if (tcm_size < 0) { 120 if (tcm_size < 0) {
114 pr_err("CPU: %sTCM of unknown size!\n", 121 pr_err("CPU: %sTCM%d of unknown size\n",
115 type ? "I" : "D"); 122 type ? "I" : "D", bank);
123 return -EINVAL;
124 } else if (tcm_size > 32) {
125 pr_err("CPU: %sTCM%d larger than 32k found\n",
126 type ? "I" : "D", bank);
127 return -EINVAL;
116 } else { 128 } else {
117 pr_info("CPU: found %sTCM %dk @ %08x, %senabled\n", 129 pr_info("CPU: found %sTCM%d %dk @ %08x, %senabled\n",
118 type ? "I" : "D", 130 type ? "I" : "D",
131 bank,
119 tcm_size, 132 tcm_size,
120 (tcm_region & 0xfffff000U), 133 (tcm_region & 0xfffff000U),
121 (tcm_region & 1) ? "" : "not "); 134 (tcm_region & 1) ? "" : "not ");
122 } 135 }
123 136
124 if (tcm_size != expected_size) {
125 pr_crit("CPU: %sTCM was detected %dk but expected %dk!\n",
126 type ? "I" : "D",
127 tcm_size,
128 expected_size);
129 /* Adjust to the expected size? what can we do... */
130 }
131
132 /* Force move the TCM bank to where we want it, enable */ 137 /* Force move the TCM bank to where we want it, enable */
133 tcm_region = offset | (tcm_region & 0x00000ffeU) | 1; 138 tcm_region = *offset | (tcm_region & 0x00000ffeU) | 1;
134 139
135 if (!type) 140 if (!type)
136 asm("mcr p15, 0, %0, c9, c1, 0" 141 asm("mcr p15, 0, %0, c9, c1, 0"
@@ -141,10 +146,15 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
141 : /* No output operands */ 146 : /* No output operands */
142 : "r" (tcm_region)); 147 : "r" (tcm_region));
143 148
144 pr_debug("CPU: moved %sTCM %dk to %08x, enabled\n", 149 /* Increase offset */
145 type ? "I" : "D", 150 *offset += (tcm_size << 10);
146 tcm_size, 151
147 (tcm_region & 0xfffff000U)); 152 pr_info("CPU: moved %sTCM%d %dk to %08x, enabled\n",
153 type ? "I" : "D",
154 bank,
155 tcm_size,
156 (tcm_region & 0xfffff000U));
157 return 0;
148} 158}
149 159
150/* 160/*
@@ -153,34 +163,52 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
153void __init tcm_init(void) 163void __init tcm_init(void)
154{ 164{
155 u32 tcm_status = read_cpuid_tcmstatus(); 165 u32 tcm_status = read_cpuid_tcmstatus();
166 u8 dtcm_banks = (tcm_status >> 16) & 0x03;
167 u8 itcm_banks = (tcm_status & 0x03);
156 char *start; 168 char *start;
157 char *end; 169 char *end;
158 char *ram; 170 char *ram;
171 int ret;
172 int i;
159 173
160 /* Setup DTCM if present */ 174 /* Setup DTCM if present */
161 if (tcm_status & (1 << 16)) { 175 if (dtcm_banks > 0) {
162 setup_tcm_bank(0, DTCM_OFFSET, 176 for (i = 0; i < dtcm_banks; i++) {
163 (DTCM_END - DTCM_OFFSET + 1) >> 10); 177 ret = setup_tcm_bank(0, i, dtcm_banks, &dtcm_end);
178 if (ret)
179 return;
180 }
181 dtcm_res.end = dtcm_end - 1;
164 request_resource(&iomem_resource, &dtcm_res); 182 request_resource(&iomem_resource, &dtcm_res);
183 dtcm_iomap[0].length = dtcm_end - DTCM_OFFSET;
165 iotable_init(dtcm_iomap, 1); 184 iotable_init(dtcm_iomap, 1);
166 /* Copy data from RAM to DTCM */ 185 /* Copy data from RAM to DTCM */
167 start = &__sdtcm_data; 186 start = &__sdtcm_data;
168 end = &__edtcm_data; 187 end = &__edtcm_data;
169 ram = &__dtcm_start; 188 ram = &__dtcm_start;
189 /* This means you compiled more code than fits into DTCM */
190 BUG_ON((end - start) > (dtcm_end - DTCM_OFFSET));
170 memcpy(start, ram, (end-start)); 191 memcpy(start, ram, (end-start));
171 pr_debug("CPU DTCM: copied data from %p - %p\n", start, end); 192 pr_debug("CPU DTCM: copied data from %p - %p\n", start, end);
172 } 193 }
173 194
174 /* Setup ITCM if present */ 195 /* Setup ITCM if present */
175 if (tcm_status & 1) { 196 if (itcm_banks > 0) {
176 setup_tcm_bank(1, ITCM_OFFSET, 197 for (i = 0; i < itcm_banks; i++) {
177 (ITCM_END - ITCM_OFFSET + 1) >> 10); 198 ret = setup_tcm_bank(1, i, itcm_banks, &itcm_end);
199 if (ret)
200 return;
201 }
202 itcm_res.end = itcm_end - 1;
178 request_resource(&iomem_resource, &itcm_res); 203 request_resource(&iomem_resource, &itcm_res);
204 itcm_iomap[0].length = itcm_end - ITCM_OFFSET;
179 iotable_init(itcm_iomap, 1); 205 iotable_init(itcm_iomap, 1);
180 /* Copy code from RAM to ITCM */ 206 /* Copy code from RAM to ITCM */
181 start = &__sitcm_text; 207 start = &__sitcm_text;
182 end = &__eitcm_text; 208 end = &__eitcm_text;
183 ram = &__itcm_start; 209 ram = &__itcm_start;
210 /* This means you compiled more code than fits into ITCM */
211 BUG_ON((end - start) > (itcm_end - ITCM_OFFSET));
184 memcpy(start, ram, (end-start)); 212 memcpy(start, ram, (end-start));
185 pr_debug("CPU ITCM: copied code from %p - %p\n", start, end); 213 pr_debug("CPU ITCM: copied code from %p - %p\n", start, end);
186 } 214 }
@@ -208,10 +236,10 @@ static int __init setup_tcm_pool(void)
208 pr_debug("Setting up TCM memory pool\n"); 236 pr_debug("Setting up TCM memory pool\n");
209 237
210 /* Add the rest of DTCM to the TCM pool */ 238 /* Add the rest of DTCM to the TCM pool */
211 if (tcm_status & (1 << 16)) { 239 if (tcm_status & (0x03 << 16)) {
212 if (dtcm_pool_start < DTCM_END) { 240 if (dtcm_pool_start < dtcm_end) {
213 ret = gen_pool_add(tcm_pool, dtcm_pool_start, 241 ret = gen_pool_add(tcm_pool, dtcm_pool_start,
214 DTCM_END - dtcm_pool_start + 1, -1); 242 dtcm_end - dtcm_pool_start, -1);
215 if (ret) { 243 if (ret) {
216 pr_err("CPU DTCM: could not add DTCM " \ 244 pr_err("CPU DTCM: could not add DTCM " \
217 "remainder to pool!\n"); 245 "remainder to pool!\n");
@@ -219,16 +247,16 @@ static int __init setup_tcm_pool(void)
219 } 247 }
220 pr_debug("CPU DTCM: Added %08x bytes @ %08x to " \ 248 pr_debug("CPU DTCM: Added %08x bytes @ %08x to " \
221 "the TCM memory pool\n", 249 "the TCM memory pool\n",
222 DTCM_END - dtcm_pool_start + 1, 250 dtcm_end - dtcm_pool_start,
223 dtcm_pool_start); 251 dtcm_pool_start);
224 } 252 }
225 } 253 }
226 254
227 /* Add the rest of ITCM to the TCM pool */ 255 /* Add the rest of ITCM to the TCM pool */
228 if (tcm_status & 1) { 256 if (tcm_status & 0x03) {
229 if (itcm_pool_start < ITCM_END) { 257 if (itcm_pool_start < itcm_end) {
230 ret = gen_pool_add(tcm_pool, itcm_pool_start, 258 ret = gen_pool_add(tcm_pool, itcm_pool_start,
231 ITCM_END - itcm_pool_start + 1, -1); 259 itcm_end - itcm_pool_start, -1);
232 if (ret) { 260 if (ret) {
233 pr_err("CPU ITCM: could not add ITCM " \ 261 pr_err("CPU ITCM: could not add ITCM " \
234 "remainder to pool!\n"); 262 "remainder to pool!\n");
@@ -236,7 +264,7 @@ static int __init setup_tcm_pool(void)
236 } 264 }
237 pr_debug("CPU ITCM: Added %08x bytes @ %08x to " \ 265 pr_debug("CPU ITCM: Added %08x bytes @ %08x to " \
238 "the TCM memory pool\n", 266 "the TCM memory pool\n",
239 ITCM_END - itcm_pool_start + 1, 267 itcm_end - itcm_pool_start,
240 itcm_pool_start); 268 itcm_pool_start);
241 } 269 }
242 } 270 }
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index 9cef0590d5aa..6467d99fa2ee 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -505,10 +505,10 @@ void __init pci_v3_preinit(void)
505 /* 505 /*
506 * Hook in our fault handler for PCI errors 506 * Hook in our fault handler for PCI errors
507 */ 507 */
508 hook_fault_code(4, v3_pci_fault, SIGBUS, "external abort on linefetch"); 508 hook_fault_code(4, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
509 hook_fault_code(6, v3_pci_fault, SIGBUS, "external abort on linefetch"); 509 hook_fault_code(6, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
510 hook_fault_code(8, v3_pci_fault, SIGBUS, "external abort on non-linefetch"); 510 hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
511 hook_fault_code(10, v3_pci_fault, SIGBUS, "external abort on non-linefetch"); 511 hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
512 512
513 spin_lock_irqsave(&v3_lock, flags); 513 spin_lock_irqsave(&v3_lock, flags);
514 514
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 6d5a90813d31..773ea0c95b9f 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -987,7 +987,7 @@ void __init iop13xx_pci_init(void)
987 iop13xx_atux_setup(); 987 iop13xx_atux_setup();
988 } 988 }
989 989
990 hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 990 hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 0,
991 "imprecise external abort"); 991 "imprecise external abort");
992} 992}
993 993
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index 90771cad06f8..f797c5f538b0 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -209,7 +209,7 @@ ixp2000_pci_preinit(void)
209 "the needed workaround has not been configured in"); 209 "the needed workaround has not been configured in");
210#endif 210#endif
211 211
212 hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS, 212 hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS, 0,
213 "PCI config cycle to non-existent device"); 213 "PCI config cycle to non-existent device");
214} 214}
215 215
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index 4b0e598a91c9..563819a83292 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -229,7 +229,7 @@ void __init ixp23xx_pci_preinit(void)
229{ 229{
230 ixp23xx_pci_common_init(); 230 ixp23xx_pci_common_init();
231 231
232 hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 232 hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0,
233 "PCI config cycle to non-existent device"); 233 "PCI config cycle to non-existent device");
234 234
235 *IXP23XX_PCI_ADDR_EXT = 0x0000e000; 235 *IXP23XX_PCI_ADDR_EXT = 0x0000e000;
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 333d04c53650..61cd4d64b985 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -382,7 +382,8 @@ void __init ixp4xx_pci_preinit(void)
382 382
383 383
384 /* hook in our fault handler for PCI errors */ 384 /* hook in our fault handler for PCI errors */
385 hook_fault_code(16+6, abort_handler, SIGBUS, "imprecise external abort"); 385 hook_fault_code(16+6, abort_handler, SIGBUS, 0,
386 "imprecise external abort");
386 387
387 pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n"); 388 pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
388 389
diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c
index 78499667eb7b..5fcd082a17f9 100644
--- a/arch/arm/mach-ks8695/pci.c
+++ b/arch/arm/mach-ks8695/pci.c
@@ -268,8 +268,8 @@ static void __init ks8695_pci_preinit(void)
268 __raw_writel(0, KS8695_PCI_VA + KS8695_PIOBAC); 268 __raw_writel(0, KS8695_PCI_VA + KS8695_PIOBAC);
269 269
270 /* hook in fault handlers */ 270 /* hook in fault handlers */
271 hook_fault_code(8, ks8695_pci_fault, SIGBUS, "external abort on non-linefetch"); 271 hook_fault_code(8, ks8695_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
272 hook_fault_code(10, ks8695_pci_fault, SIGBUS, "external abort on non-linefetch"); 272 hook_fault_code(10, ks8695_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
273} 273}
274 274
275static void ks8695_show_pciregs(void) 275static void ks8695_show_pciregs(void)
diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h
index ab000df7fc03..bf134bcc129d 100644
--- a/arch/arm/mach-u300/include/mach/memory.h
+++ b/arch/arm/mach-u300/include/mach/memory.h
@@ -35,14 +35,6 @@
35#endif 35#endif
36 36
37/* 37/*
38 * TCM memory whereabouts
39 */
40#define ITCM_OFFSET 0xffff2000
41#define ITCM_END 0xffff3fff
42#define DTCM_OFFSET 0xffff4000
43#define DTCM_END 0xffff5fff
44
45/*
46 * We enable a real big DMA buffer if need be. 38 * We enable a real big DMA buffer if need be.
47 */ 39 */
48#define CONSISTENT_DMA_SIZE SZ_4M 40#define CONSISTENT_DMA_SIZE SZ_4M
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 6f98c358989a..d073b64ae87e 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -924,8 +924,20 @@ static int __init alignment_init(void)
924 ai_usermode = UM_FIXUP; 924 ai_usermode = UM_FIXUP;
925 } 925 }
926 926
927 hook_fault_code(1, do_alignment, SIGILL, "alignment exception"); 927 hook_fault_code(1, do_alignment, SIGBUS, BUS_ADRALN,
928 hook_fault_code(3, do_alignment, SIGILL, "alignment exception"); 928 "alignment exception");
929
930 /*
931 * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section
932 * fault, not as alignment error.
933 *
934 * TODO: handle ARMv6K properly. Runtime check for 'K' extension is
935 * needed.
936 */
937 if (cpu_architecture() <= CPU_ARCH_ARMv6) {
938 hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN,
939 "alignment exception");
940 }
929 941
930 return 0; 942 return 0;
931} 943}
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 9e7742f0a102..c704eed63c5d 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -183,6 +183,8 @@ static void *
183__dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot) 183__dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot)
184{ 184{
185 struct arm_vmregion *c; 185 struct arm_vmregion *c;
186 size_t align;
187 int bit;
186 188
187 if (!consistent_pte[0]) { 189 if (!consistent_pte[0]) {
188 printk(KERN_ERR "%s: not initialised\n", __func__); 190 printk(KERN_ERR "%s: not initialised\n", __func__);
@@ -191,9 +193,20 @@ __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot)
191 } 193 }
192 194
193 /* 195 /*
196 * Align the virtual region allocation - maximum alignment is
197 * a section size, minimum is a page size. This helps reduce
198 * fragmentation of the DMA space, and also prevents allocations
199 * smaller than a section from crossing a section boundary.
200 */
201 bit = fls(size - 1) + 1;
202 if (bit > SECTION_SHIFT)
203 bit = SECTION_SHIFT;
204 align = 1 << bit;
205
206 /*
194 * Allocate a virtual address in the consistent mapping region. 207 * Allocate a virtual address in the consistent mapping region.
195 */ 208 */
196 c = arm_vmregion_alloc(&consistent_head, size, 209 c = arm_vmregion_alloc(&consistent_head, align, size,
197 gfp & ~(__GFP_DMA | __GFP_HIGHMEM)); 210 gfp & ~(__GFP_DMA | __GFP_HIGHMEM));
198 if (c) { 211 if (c) {
199 pte_t *pte; 212 pte_t *pte;
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index cbfb2edcf7d1..23b0b03af5ea 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -413,7 +413,16 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
413 pmd_k = pmd_offset(pgd_k, addr); 413 pmd_k = pmd_offset(pgd_k, addr);
414 pmd = pmd_offset(pgd, addr); 414 pmd = pmd_offset(pgd, addr);
415 415
416 if (pmd_none(*pmd_k)) 416 /*
417 * On ARM one Linux PGD entry contains two hardware entries (see page
418 * tables layout in pgtable.h). We normally guarantee that we always
419 * fill both L1 entries. But create_mapping() doesn't follow the rule.
420 * It can create inidividual L1 entries, so here we have to call
421 * pmd_none() check for the entry really corresponded to address, not
422 * for the first of pair.
423 */
424 index = (addr >> SECTION_SHIFT) & 1;
425 if (pmd_none(pmd_k[index]))
417 goto bad_area; 426 goto bad_area;
418 427
419 copy_pmd(pmd, pmd_k); 428 copy_pmd(pmd, pmd_k);
@@ -463,15 +472,10 @@ static struct fsr_info {
463 * defines these to be "precise" aborts. 472 * defines these to be "precise" aborts.
464 */ 473 */
465 { do_bad, SIGSEGV, 0, "vector exception" }, 474 { do_bad, SIGSEGV, 0, "vector exception" },
466 { do_bad, SIGILL, BUS_ADRALN, "alignment exception" }, 475 { do_bad, SIGBUS, BUS_ADRALN, "alignment exception" },
467 { do_bad, SIGKILL, 0, "terminal exception" }, 476 { do_bad, SIGKILL, 0, "terminal exception" },
468 { do_bad, SIGILL, BUS_ADRALN, "alignment exception" }, 477 { do_bad, SIGBUS, BUS_ADRALN, "alignment exception" },
469/* Do we need runtime check ? */
470#if __LINUX_ARM_ARCH__ < 6
471 { do_bad, SIGBUS, 0, "external abort on linefetch" }, 478 { do_bad, SIGBUS, 0, "external abort on linefetch" },
472#else
473 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "I-cache maintenance fault" },
474#endif
475 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "section translation fault" }, 479 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "section translation fault" },
476 { do_bad, SIGBUS, 0, "external abort on linefetch" }, 480 { do_bad, SIGBUS, 0, "external abort on linefetch" },
477 { do_page_fault, SIGSEGV, SEGV_MAPERR, "page translation fault" }, 481 { do_page_fault, SIGSEGV, SEGV_MAPERR, "page translation fault" },
@@ -508,13 +512,15 @@ static struct fsr_info {
508 512
509void __init 513void __init
510hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *), 514hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *),
511 int sig, const char *name) 515 int sig, int code, const char *name)
512{ 516{
513 if (nr >= 0 && nr < ARRAY_SIZE(fsr_info)) { 517 if (nr < 0 || nr >= ARRAY_SIZE(fsr_info))
514 fsr_info[nr].fn = fn; 518 BUG();
515 fsr_info[nr].sig = sig; 519
516 fsr_info[nr].name = name; 520 fsr_info[nr].fn = fn;
517 } 521 fsr_info[nr].sig = sig;
522 fsr_info[nr].code = code;
523 fsr_info[nr].name = name;
518} 524}
519 525
520/* 526/*
@@ -594,3 +600,25 @@ do_PrefetchAbort(unsigned long addr, unsigned int ifsr, struct pt_regs *regs)
594 arm_notify_die("", regs, &info, ifsr, 0); 600 arm_notify_die("", regs, &info, ifsr, 0);
595} 601}
596 602
603static int __init exceptions_init(void)
604{
605 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
606 hook_fault_code(4, do_translation_fault, SIGSEGV, SEGV_MAPERR,
607 "I-cache maintenance fault");
608 }
609
610 if (cpu_architecture() >= CPU_ARCH_ARMv7) {
611 /*
612 * TODO: Access flag faults introduced in ARMv6K.
613 * Runtime check for 'K' extension is needed
614 */
615 hook_fault_code(3, do_bad, SIGSEGV, SEGV_MAPERR,
616 "section access flag fault");
617 hook_fault_code(6, do_bad, SIGSEGV, SEGV_MAPERR,
618 "section access flag fault");
619 }
620
621 return 0;
622}
623
624arch_initcall(exceptions_init);
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 599d121c81e7..240b68d511dc 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -432,6 +432,11 @@ void __init mem_init(void)
432{ 432{
433 unsigned long reserved_pages, free_pages; 433 unsigned long reserved_pages, free_pages;
434 int i; 434 int i;
435#ifdef CONFIG_HAVE_TCM
436 /* These pointers are filled in on TCM detection */
437 extern u32 dtcm_end;
438 extern u32 itcm_end;
439#endif
435 440
436 max_mapnr = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map; 441 max_mapnr = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map;
437 442
@@ -503,6 +508,10 @@ void __init mem_init(void)
503 508
504 printk(KERN_NOTICE "Virtual kernel memory layout:\n" 509 printk(KERN_NOTICE "Virtual kernel memory layout:\n"
505 " vector : 0x%08lx - 0x%08lx (%4ld kB)\n" 510 " vector : 0x%08lx - 0x%08lx (%4ld kB)\n"
511#ifdef CONFIG_HAVE_TCM
512 " DTCM : 0x%08lx - 0x%08lx (%4ld kB)\n"
513 " ITCM : 0x%08lx - 0x%08lx (%4ld kB)\n"
514#endif
506 " fixmap : 0x%08lx - 0x%08lx (%4ld kB)\n" 515 " fixmap : 0x%08lx - 0x%08lx (%4ld kB)\n"
507#ifdef CONFIG_MMU 516#ifdef CONFIG_MMU
508 " DMA : 0x%08lx - 0x%08lx (%4ld MB)\n" 517 " DMA : 0x%08lx - 0x%08lx (%4ld MB)\n"
@@ -519,6 +528,10 @@ void __init mem_init(void)
519 528
520 MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) + 529 MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) +
521 (PAGE_SIZE)), 530 (PAGE_SIZE)),
531#ifdef CONFIG_HAVE_TCM
532 MLK(DTCM_OFFSET, (unsigned long) dtcm_end),
533 MLK(ITCM_OFFSET, (unsigned long) itcm_end),
534#endif
522 MLK(FIXADDR_START, FIXADDR_TOP), 535 MLK(FIXADDR_START, FIXADDR_TOP),
523#ifdef CONFIG_MMU 536#ifdef CONFIG_MMU
524 MLM(CONSISTENT_BASE, CONSISTENT_END), 537 MLM(CONSISTENT_BASE, CONSISTENT_END),
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 03f11935ed08..ab506272b2d3 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -42,78 +42,11 @@
42 */ 42 */
43#define VM_ARM_SECTION_MAPPING 0x80000000 43#define VM_ARM_SECTION_MAPPING 0x80000000
44 44
45static int remap_area_pte(pmd_t *pmd, unsigned long addr, unsigned long end,
46 unsigned long phys_addr, const struct mem_type *type)
47{
48 pgprot_t prot = __pgprot(type->prot_pte);
49 pte_t *pte;
50
51 pte = pte_alloc_kernel(pmd, addr);
52 if (!pte)
53 return -ENOMEM;
54
55 do {
56 if (!pte_none(*pte))
57 goto bad;
58
59 set_pte_ext(pte, pfn_pte(phys_addr >> PAGE_SHIFT, prot), 0);
60 phys_addr += PAGE_SIZE;
61 } while (pte++, addr += PAGE_SIZE, addr != end);
62 return 0;
63
64 bad:
65 printk(KERN_CRIT "remap_area_pte: page already exists\n");
66 BUG();
67}
68
69static inline int remap_area_pmd(pgd_t *pgd, unsigned long addr,
70 unsigned long end, unsigned long phys_addr,
71 const struct mem_type *type)
72{
73 unsigned long next;
74 pmd_t *pmd;
75 int ret = 0;
76
77 pmd = pmd_alloc(&init_mm, pgd, addr);
78 if (!pmd)
79 return -ENOMEM;
80
81 do {
82 next = pmd_addr_end(addr, end);
83 ret = remap_area_pte(pmd, addr, next, phys_addr, type);
84 if (ret)
85 return ret;
86 phys_addr += next - addr;
87 } while (pmd++, addr = next, addr != end);
88 return ret;
89}
90
91static int remap_area_pages(unsigned long start, unsigned long pfn,
92 size_t size, const struct mem_type *type)
93{
94 unsigned long addr = start;
95 unsigned long next, end = start + size;
96 unsigned long phys_addr = __pfn_to_phys(pfn);
97 pgd_t *pgd;
98 int err = 0;
99
100 BUG_ON(addr >= end);
101 pgd = pgd_offset_k(addr);
102 do {
103 next = pgd_addr_end(addr, end);
104 err = remap_area_pmd(pgd, addr, next, phys_addr, type);
105 if (err)
106 break;
107 phys_addr += next - addr;
108 } while (pgd++, addr = next, addr != end);
109
110 return err;
111}
112
113int ioremap_page(unsigned long virt, unsigned long phys, 45int ioremap_page(unsigned long virt, unsigned long phys,
114 const struct mem_type *mtype) 46 const struct mem_type *mtype)
115{ 47{
116 return remap_area_pages(virt, __phys_to_pfn(phys), PAGE_SIZE, mtype); 48 return ioremap_page_range(virt, virt + PAGE_SIZE, phys,
49 __pgprot(mtype->prot_pte));
117} 50}
118EXPORT_SYMBOL(ioremap_page); 51EXPORT_SYMBOL(ioremap_page);
119 52
@@ -300,7 +233,8 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
300 err = remap_area_sections(addr, pfn, size, type); 233 err = remap_area_sections(addr, pfn, size, type);
301 } else 234 } else
302#endif 235#endif
303 err = remap_area_pages(addr, pfn, size, type); 236 err = ioremap_page_range(addr, addr + size, __pfn_to_phys(pfn),
237 __pgprot(type->prot_pte));
304 238
305 if (err) { 239 if (err) {
306 vunmap((void *)addr); 240 vunmap((void *)addr);
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index d5541adc3520..6e1c4f6a2b3f 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -257,6 +257,19 @@ static struct mem_type mem_types[] = {
257 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 257 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
258 .domain = DOMAIN_KERNEL, 258 .domain = DOMAIN_KERNEL,
259 }, 259 },
260 [MT_MEMORY_DTCM] = {
261 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG |
262 L_PTE_DIRTY | L_PTE_WRITE,
263 .prot_l1 = PMD_TYPE_TABLE,
264 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
265 .domain = DOMAIN_KERNEL,
266 },
267 [MT_MEMORY_ITCM] = {
268 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
269 L_PTE_USER | L_PTE_EXEC,
270 .prot_l1 = PMD_TYPE_TABLE,
271 .domain = DOMAIN_IO,
272 },
260}; 273};
261 274
262const struct mem_type *get_mem_type(unsigned int type) 275const struct mem_type *get_mem_type(unsigned int type)
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 72507c630ceb..203a4e944d9e 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -79,15 +79,11 @@ ENTRY(cpu_arm1020_proc_init)
79 * cpu_arm1020_proc_fin() 79 * cpu_arm1020_proc_fin()
80 */ 80 */
81ENTRY(cpu_arm1020_proc_fin) 81ENTRY(cpu_arm1020_proc_fin)
82 stmfd sp!, {lr}
83 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
84 msr cpsr_c, ip
85 bl arm1020_flush_kern_cache_all
86 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
87 bic r0, r0, #0x1000 @ ...i............ 83 bic r0, r0, #0x1000 @ ...i............
88 bic r0, r0, #0x000e @ ............wca. 84 bic r0, r0, #0x000e @ ............wca.
89 mcr p15, 0, r0, c1, c0, 0 @ disable caches 85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
90 ldmfd sp!, {pc} 86 mov pc, lr
91 87
92/* 88/*
93 * cpu_arm1020_reset(loc) 89 * cpu_arm1020_reset(loc)
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index d27829805609..1a511e765909 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -79,15 +79,11 @@ ENTRY(cpu_arm1020e_proc_init)
79 * cpu_arm1020e_proc_fin() 79 * cpu_arm1020e_proc_fin()
80 */ 80 */
81ENTRY(cpu_arm1020e_proc_fin) 81ENTRY(cpu_arm1020e_proc_fin)
82 stmfd sp!, {lr}
83 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
84 msr cpsr_c, ip
85 bl arm1020e_flush_kern_cache_all
86 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
87 bic r0, r0, #0x1000 @ ...i............ 83 bic r0, r0, #0x1000 @ ...i............
88 bic r0, r0, #0x000e @ ............wca. 84 bic r0, r0, #0x000e @ ............wca.
89 mcr p15, 0, r0, c1, c0, 0 @ disable caches 85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
90 ldmfd sp!, {pc} 86 mov pc, lr
91 87
92/* 88/*
93 * cpu_arm1020e_reset(loc) 89 * cpu_arm1020e_reset(loc)
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index ce13e4a827de..1ffa4eb9c34f 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -68,15 +68,11 @@ ENTRY(cpu_arm1022_proc_init)
68 * cpu_arm1022_proc_fin() 68 * cpu_arm1022_proc_fin()
69 */ 69 */
70ENTRY(cpu_arm1022_proc_fin) 70ENTRY(cpu_arm1022_proc_fin)
71 stmfd sp!, {lr}
72 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
73 msr cpsr_c, ip
74 bl arm1022_flush_kern_cache_all
75 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 71 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
76 bic r0, r0, #0x1000 @ ...i............ 72 bic r0, r0, #0x1000 @ ...i............
77 bic r0, r0, #0x000e @ ............wca. 73 bic r0, r0, #0x000e @ ............wca.
78 mcr p15, 0, r0, c1, c0, 0 @ disable caches 74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
79 ldmfd sp!, {pc} 75 mov pc, lr
80 76
81/* 77/*
82 * cpu_arm1022_reset(loc) 78 * cpu_arm1022_reset(loc)
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 636672a29c6d..5697c34b95b0 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -68,15 +68,11 @@ ENTRY(cpu_arm1026_proc_init)
68 * cpu_arm1026_proc_fin() 68 * cpu_arm1026_proc_fin()
69 */ 69 */
70ENTRY(cpu_arm1026_proc_fin) 70ENTRY(cpu_arm1026_proc_fin)
71 stmfd sp!, {lr}
72 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
73 msr cpsr_c, ip
74 bl arm1026_flush_kern_cache_all
75 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 71 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
76 bic r0, r0, #0x1000 @ ...i............ 72 bic r0, r0, #0x1000 @ ...i............
77 bic r0, r0, #0x000e @ ............wca. 73 bic r0, r0, #0x000e @ ............wca.
78 mcr p15, 0, r0, c1, c0, 0 @ disable caches 74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
79 ldmfd sp!, {pc} 75 mov pc, lr
80 76
81/* 77/*
82 * cpu_arm1026_reset(loc) 78 * cpu_arm1026_reset(loc)
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 795dc615f43b..64e0b327c7c5 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -184,8 +184,6 @@ ENTRY(cpu_arm7_proc_init)
184 184
185ENTRY(cpu_arm6_proc_fin) 185ENTRY(cpu_arm6_proc_fin)
186ENTRY(cpu_arm7_proc_fin) 186ENTRY(cpu_arm7_proc_fin)
187 mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
188 msr cpsr_c, r0
189 mov r0, #0x31 @ ....S..DP...M 187 mov r0, #0x31 @ ....S..DP...M
190 mcr p15, 0, r0, c1, c0, 0 @ disable caches 188 mcr p15, 0, r0, c1, c0, 0 @ disable caches
191 mov pc, lr 189 mov pc, lr
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 0b62de244666..9d96824134fc 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -54,15 +54,11 @@ ENTRY(cpu_arm720_proc_init)
54 mov pc, lr 54 mov pc, lr
55 55
56ENTRY(cpu_arm720_proc_fin) 56ENTRY(cpu_arm720_proc_fin)
57 stmfd sp!, {lr}
58 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
59 msr cpsr_c, ip
60 mrc p15, 0, r0, c1, c0, 0 57 mrc p15, 0, r0, c1, c0, 0
61 bic r0, r0, #0x1000 @ ...i............ 58 bic r0, r0, #0x1000 @ ...i............
62 bic r0, r0, #0x000e @ ............wca. 59 bic r0, r0, #0x000e @ ............wca.
63 mcr p15, 0, r0, c1, c0, 0 @ disable caches 60 mcr p15, 0, r0, c1, c0, 0 @ disable caches
64 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache 61 mov pc, lr
65 ldmfd sp!, {pc}
66 62
67/* 63/*
68 * Function: arm720_proc_do_idle(void) 64 * Function: arm720_proc_do_idle(void)
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 01860cdeb2ec..6c1a9ab059ae 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -36,15 +36,11 @@ ENTRY(cpu_arm740_switch_mm)
36 * cpu_arm740_proc_fin() 36 * cpu_arm740_proc_fin()
37 */ 37 */
38ENTRY(cpu_arm740_proc_fin) 38ENTRY(cpu_arm740_proc_fin)
39 stmfd sp!, {lr}
40 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
41 msr cpsr_c, ip
42 mrc p15, 0, r0, c1, c0, 0 39 mrc p15, 0, r0, c1, c0, 0
43 bic r0, r0, #0x3f000000 @ bank/f/lock/s 40 bic r0, r0, #0x3f000000 @ bank/f/lock/s
44 bic r0, r0, #0x0000000c @ w-buffer/cache 41 bic r0, r0, #0x0000000c @ w-buffer/cache
45 mcr p15, 0, r0, c1, c0, 0 @ disable caches 42 mcr p15, 0, r0, c1, c0, 0 @ disable caches
46 mcr p15, 0, r0, c7, c0, 0 @ invalidate cache 43 mov pc, lr
47 ldmfd sp!, {pc}
48 44
49/* 45/*
50 * cpu_arm740_reset(loc) 46 * cpu_arm740_reset(loc)
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index 1201b9863829..6a850dbba22e 100644
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -36,8 +36,6 @@ ENTRY(cpu_arm7tdmi_switch_mm)
36 * cpu_arm7tdmi_proc_fin() 36 * cpu_arm7tdmi_proc_fin()
37 */ 37 */
38ENTRY(cpu_arm7tdmi_proc_fin) 38ENTRY(cpu_arm7tdmi_proc_fin)
39 mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
40 msr cpsr_c, r0
41 mov pc, lr 39 mov pc, lr
42 40
43/* 41/*
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 8be81992645d..86f80aa56216 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -69,19 +69,11 @@ ENTRY(cpu_arm920_proc_init)
69 * cpu_arm920_proc_fin() 69 * cpu_arm920_proc_fin()
70 */ 70 */
71ENTRY(cpu_arm920_proc_fin) 71ENTRY(cpu_arm920_proc_fin)
72 stmfd sp!, {lr}
73 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
74 msr cpsr_c, ip
75#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
76 bl arm920_flush_kern_cache_all
77#else
78 bl v4wt_flush_kern_cache_all
79#endif
80 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 72 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
81 bic r0, r0, #0x1000 @ ...i............ 73 bic r0, r0, #0x1000 @ ...i............
82 bic r0, r0, #0x000e @ ............wca. 74 bic r0, r0, #0x000e @ ............wca.
83 mcr p15, 0, r0, c1, c0, 0 @ disable caches 75 mcr p15, 0, r0, c1, c0, 0 @ disable caches
84 ldmfd sp!, {pc} 76 mov pc, lr
85 77
86/* 78/*
87 * cpu_arm920_reset(loc) 79 * cpu_arm920_reset(loc)
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index c0ff8e4b1074..f76ce9b62883 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -71,19 +71,11 @@ ENTRY(cpu_arm922_proc_init)
71 * cpu_arm922_proc_fin() 71 * cpu_arm922_proc_fin()
72 */ 72 */
73ENTRY(cpu_arm922_proc_fin) 73ENTRY(cpu_arm922_proc_fin)
74 stmfd sp!, {lr}
75 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
76 msr cpsr_c, ip
77#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
78 bl arm922_flush_kern_cache_all
79#else
80 bl v4wt_flush_kern_cache_all
81#endif
82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 74 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
83 bic r0, r0, #0x1000 @ ...i............ 75 bic r0, r0, #0x1000 @ ...i............
84 bic r0, r0, #0x000e @ ............wca. 76 bic r0, r0, #0x000e @ ............wca.
85 mcr p15, 0, r0, c1, c0, 0 @ disable caches 77 mcr p15, 0, r0, c1, c0, 0 @ disable caches
86 ldmfd sp!, {pc} 78 mov pc, lr
87 79
88/* 80/*
89 * cpu_arm922_reset(loc) 81 * cpu_arm922_reset(loc)
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 3c6cffe400f6..657bd3f7c153 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -92,15 +92,11 @@ ENTRY(cpu_arm925_proc_init)
92 * cpu_arm925_proc_fin() 92 * cpu_arm925_proc_fin()
93 */ 93 */
94ENTRY(cpu_arm925_proc_fin) 94ENTRY(cpu_arm925_proc_fin)
95 stmfd sp!, {lr}
96 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
97 msr cpsr_c, ip
98 bl arm925_flush_kern_cache_all
99 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 95 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
100 bic r0, r0, #0x1000 @ ...i............ 96 bic r0, r0, #0x1000 @ ...i............
101 bic r0, r0, #0x000e @ ............wca. 97 bic r0, r0, #0x000e @ ............wca.
102 mcr p15, 0, r0, c1, c0, 0 @ disable caches 98 mcr p15, 0, r0, c1, c0, 0 @ disable caches
103 ldmfd sp!, {pc} 99 mov pc, lr
104 100
105/* 101/*
106 * cpu_arm925_reset(loc) 102 * cpu_arm925_reset(loc)
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 75b707c9cce1..73f1f3c68910 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -61,15 +61,11 @@ ENTRY(cpu_arm926_proc_init)
61 * cpu_arm926_proc_fin() 61 * cpu_arm926_proc_fin()
62 */ 62 */
63ENTRY(cpu_arm926_proc_fin) 63ENTRY(cpu_arm926_proc_fin)
64 stmfd sp!, {lr}
65 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
66 msr cpsr_c, ip
67 bl arm926_flush_kern_cache_all
68 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 64 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
69 bic r0, r0, #0x1000 @ ...i............ 65 bic r0, r0, #0x1000 @ ...i............
70 bic r0, r0, #0x000e @ ............wca. 66 bic r0, r0, #0x000e @ ............wca.
71 mcr p15, 0, r0, c1, c0, 0 @ disable caches 67 mcr p15, 0, r0, c1, c0, 0 @ disable caches
72 ldmfd sp!, {pc} 68 mov pc, lr
73 69
74/* 70/*
75 * cpu_arm926_reset(loc) 71 * cpu_arm926_reset(loc)
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 1af1657819eb..fffb061a45a5 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -37,15 +37,11 @@ ENTRY(cpu_arm940_switch_mm)
37 * cpu_arm940_proc_fin() 37 * cpu_arm940_proc_fin()
38 */ 38 */
39ENTRY(cpu_arm940_proc_fin) 39ENTRY(cpu_arm940_proc_fin)
40 stmfd sp!, {lr}
41 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
42 msr cpsr_c, ip
43 bl arm940_flush_kern_cache_all
44 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 40 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
45 bic r0, r0, #0x00001000 @ i-cache 41 bic r0, r0, #0x00001000 @ i-cache
46 bic r0, r0, #0x00000004 @ d-cache 42 bic r0, r0, #0x00000004 @ d-cache
47 mcr p15, 0, r0, c1, c0, 0 @ disable caches 43 mcr p15, 0, r0, c1, c0, 0 @ disable caches
48 ldmfd sp!, {pc} 44 mov pc, lr
49 45
50/* 46/*
51 * cpu_arm940_reset(loc) 47 * cpu_arm940_reset(loc)
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 1664b6aaff79..249a6053760a 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -44,15 +44,11 @@ ENTRY(cpu_arm946_switch_mm)
44 * cpu_arm946_proc_fin() 44 * cpu_arm946_proc_fin()
45 */ 45 */
46ENTRY(cpu_arm946_proc_fin) 46ENTRY(cpu_arm946_proc_fin)
47 stmfd sp!, {lr}
48 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
49 msr cpsr_c, ip
50 bl arm946_flush_kern_cache_all
51 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 47 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
52 bic r0, r0, #0x00001000 @ i-cache 48 bic r0, r0, #0x00001000 @ i-cache
53 bic r0, r0, #0x00000004 @ d-cache 49 bic r0, r0, #0x00000004 @ d-cache
54 mcr p15, 0, r0, c1, c0, 0 @ disable caches 50 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 ldmfd sp!, {pc} 51 mov pc, lr
56 52
57/* 53/*
58 * cpu_arm946_reset(loc) 54 * cpu_arm946_reset(loc)
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index 28545c29dbcd..db475667fac2 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -36,8 +36,6 @@ ENTRY(cpu_arm9tdmi_switch_mm)
36 * cpu_arm9tdmi_proc_fin() 36 * cpu_arm9tdmi_proc_fin()
37 */ 37 */
38ENTRY(cpu_arm9tdmi_proc_fin) 38ENTRY(cpu_arm9tdmi_proc_fin)
39 mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
40 msr cpsr_c, r0
41 mov pc, lr 39 mov pc, lr
42 40
43/* 41/*
diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
index 08f5ac237ad4..7803fdf70029 100644
--- a/arch/arm/mm/proc-fa526.S
+++ b/arch/arm/mm/proc-fa526.S
@@ -39,17 +39,13 @@ ENTRY(cpu_fa526_proc_init)
39 * cpu_fa526_proc_fin() 39 * cpu_fa526_proc_fin()
40 */ 40 */
41ENTRY(cpu_fa526_proc_fin) 41ENTRY(cpu_fa526_proc_fin)
42 stmfd sp!, {lr}
43 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
44 msr cpsr_c, ip
45 bl fa_flush_kern_cache_all
46 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 42 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
47 bic r0, r0, #0x1000 @ ...i............ 43 bic r0, r0, #0x1000 @ ...i............
48 bic r0, r0, #0x000e @ ............wca. 44 bic r0, r0, #0x000e @ ............wca.
49 mcr p15, 0, r0, c1, c0, 0 @ disable caches 45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
50 nop 46 nop
51 nop 47 nop
52 ldmfd sp!, {pc} 48 mov pc, lr
53 49
54/* 50/*
55 * cpu_fa526_reset(loc) 51 * cpu_fa526_reset(loc)
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index 53e632343849..b304d0104a4e 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -75,11 +75,6 @@ ENTRY(cpu_feroceon_proc_init)
75 * cpu_feroceon_proc_fin() 75 * cpu_feroceon_proc_fin()
76 */ 76 */
77ENTRY(cpu_feroceon_proc_fin) 77ENTRY(cpu_feroceon_proc_fin)
78 stmfd sp!, {lr}
79 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
80 msr cpsr_c, ip
81 bl feroceon_flush_kern_cache_all
82
83#if defined(CONFIG_CACHE_FEROCEON_L2) && \ 78#if defined(CONFIG_CACHE_FEROCEON_L2) && \
84 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) 79 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
85 mov r0, #0 80 mov r0, #0
@@ -91,7 +86,7 @@ ENTRY(cpu_feroceon_proc_fin)
91 bic r0, r0, #0x1000 @ ...i............ 86 bic r0, r0, #0x1000 @ ...i............
92 bic r0, r0, #0x000e @ ............wca. 87 bic r0, r0, #0x000e @ ............wca.
93 mcr p15, 0, r0, c1, c0, 0 @ disable caches 88 mcr p15, 0, r0, c1, c0, 0 @ disable caches
94 ldmfd sp!, {pc} 89 mov pc, lr
95 90
96/* 91/*
97 * cpu_feroceon_reset(loc) 92 * cpu_feroceon_reset(loc)
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index caa31154e7db..5f6892fcc167 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -51,15 +51,11 @@ ENTRY(cpu_mohawk_proc_init)
51 * cpu_mohawk_proc_fin() 51 * cpu_mohawk_proc_fin()
52 */ 52 */
53ENTRY(cpu_mohawk_proc_fin) 53ENTRY(cpu_mohawk_proc_fin)
54 stmfd sp!, {lr}
55 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
56 msr cpsr_c, ip
57 bl mohawk_flush_kern_cache_all
58 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 54 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
59 bic r0, r0, #0x1800 @ ...iz........... 55 bic r0, r0, #0x1800 @ ...iz...........
60 bic r0, r0, #0x0006 @ .............ca. 56 bic r0, r0, #0x0006 @ .............ca.
61 mcr p15, 0, r0, c1, c0, 0 @ disable caches 57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 ldmfd sp!, {pc} 58 mov pc, lr
63 59
64/* 60/*
65 * cpu_mohawk_reset(loc) 61 * cpu_mohawk_reset(loc)
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 7b706b389906..a201eb04b5e1 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -44,17 +44,13 @@ ENTRY(cpu_sa110_proc_init)
44 * cpu_sa110_proc_fin() 44 * cpu_sa110_proc_fin()
45 */ 45 */
46ENTRY(cpu_sa110_proc_fin) 46ENTRY(cpu_sa110_proc_fin)
47 stmfd sp!, {lr} 47 mov r0, #0
48 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
49 msr cpsr_c, ip
50 bl v4wb_flush_kern_cache_all @ clean caches
511: mov r0, #0
52 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching 48 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
53 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 49 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
54 bic r0, r0, #0x1000 @ ...i............ 50 bic r0, r0, #0x1000 @ ...i............
55 bic r0, r0, #0x000e @ ............wca. 51 bic r0, r0, #0x000e @ ............wca.
56 mcr p15, 0, r0, c1, c0, 0 @ disable caches 52 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 ldmfd sp!, {pc} 53 mov pc, lr
58 54
59/* 55/*
60 * cpu_sa110_reset(loc) 56 * cpu_sa110_reset(loc)
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 5c47760c2064..7ddc4805bf97 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -55,16 +55,12 @@ ENTRY(cpu_sa1100_proc_init)
55 * - Clean and turn off caches. 55 * - Clean and turn off caches.
56 */ 56 */
57ENTRY(cpu_sa1100_proc_fin) 57ENTRY(cpu_sa1100_proc_fin)
58 stmfd sp!, {lr}
59 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
60 msr cpsr_c, ip
61 bl v4wb_flush_kern_cache_all
62 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching 58 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
63 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 59 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
64 bic r0, r0, #0x1000 @ ...i............ 60 bic r0, r0, #0x1000 @ ...i............
65 bic r0, r0, #0x000e @ ............wca. 61 bic r0, r0, #0x000e @ ............wca.
66 mcr p15, 0, r0, c1, c0, 0 @ disable caches 62 mcr p15, 0, r0, c1, c0, 0 @ disable caches
67 ldmfd sp!, {pc} 63 mov pc, lr
68 64
69/* 65/*
70 * cpu_sa1100_reset(loc) 66 * cpu_sa1100_reset(loc)
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 2f5a3c23a0fe..22aac8515196 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -42,14 +42,11 @@ ENTRY(cpu_v6_proc_init)
42 mov pc, lr 42 mov pc, lr
43 43
44ENTRY(cpu_v6_proc_fin) 44ENTRY(cpu_v6_proc_fin)
45 stmfd sp!, {lr}
46 cpsid if @ disable interrupts
47 bl v6_flush_kern_cache_all
48 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 45 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
49 bic r0, r0, #0x1000 @ ...i............ 46 bic r0, r0, #0x1000 @ ...i............
50 bic r0, r0, #0x0006 @ .............ca. 47 bic r0, r0, #0x0006 @ .............ca.
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches 48 mcr p15, 0, r0, c1, c0, 0 @ disable caches
52 ldmfd sp!, {pc} 49 mov pc, lr
53 50
54/* 51/*
55 * cpu_v6_reset(loc) 52 * cpu_v6_reset(loc)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 8071bcd4c995..6a8506d99ee9 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -45,14 +45,11 @@ ENTRY(cpu_v7_proc_init)
45ENDPROC(cpu_v7_proc_init) 45ENDPROC(cpu_v7_proc_init)
46 46
47ENTRY(cpu_v7_proc_fin) 47ENTRY(cpu_v7_proc_fin)
48 stmfd sp!, {lr}
49 cpsid if @ disable interrupts
50 bl v7_flush_kern_cache_all
51 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 48 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
52 bic r0, r0, #0x1000 @ ...i............ 49 bic r0, r0, #0x1000 @ ...i............
53 bic r0, r0, #0x0006 @ .............ca. 50 bic r0, r0, #0x0006 @ .............ca.
54 mcr p15, 0, r0, c1, c0, 0 @ disable caches 51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 ldmfd sp!, {pc} 52 mov pc, lr
56ENDPROC(cpu_v7_proc_fin) 53ENDPROC(cpu_v7_proc_fin)
57 54
58/* 55/*
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index e5797f1c1db7..361a51e49030 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -90,15 +90,11 @@ ENTRY(cpu_xsc3_proc_init)
90 * cpu_xsc3_proc_fin() 90 * cpu_xsc3_proc_fin()
91 */ 91 */
92ENTRY(cpu_xsc3_proc_fin) 92ENTRY(cpu_xsc3_proc_fin)
93 str lr, [sp, #-4]!
94 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
95 msr cpsr_c, r0
96 bl xsc3_flush_kern_cache_all @ clean caches
97 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 93 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
98 bic r0, r0, #0x1800 @ ...IZ........... 94 bic r0, r0, #0x1800 @ ...IZ...........
99 bic r0, r0, #0x0006 @ .............CA. 95 bic r0, r0, #0x0006 @ .............CA.
100 mcr p15, 0, r0, c1, c0, 0 @ disable caches 96 mcr p15, 0, r0, c1, c0, 0 @ disable caches
101 ldr pc, [sp], #4 97 mov pc, lr
102 98
103/* 99/*
104 * cpu_xsc3_reset(loc) 100 * cpu_xsc3_reset(loc)
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 63037e2162f2..14075979bcba 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -124,15 +124,11 @@ ENTRY(cpu_xscale_proc_init)
124 * cpu_xscale_proc_fin() 124 * cpu_xscale_proc_fin()
125 */ 125 */
126ENTRY(cpu_xscale_proc_fin) 126ENTRY(cpu_xscale_proc_fin)
127 str lr, [sp, #-4]!
128 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
129 msr cpsr_c, r0
130 bl xscale_flush_kern_cache_all @ clean caches
131 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
132 bic r0, r0, #0x1800 @ ...IZ........... 128 bic r0, r0, #0x1800 @ ...IZ...........
133 bic r0, r0, #0x0006 @ .............CA. 129 bic r0, r0, #0x0006 @ .............CA.
134 mcr p15, 0, r0, c1, c0, 0 @ disable caches 130 mcr p15, 0, r0, c1, c0, 0 @ disable caches
135 ldr pc, [sp], #4 131 mov pc, lr
136 132
137/* 133/*
138 * cpu_xscale_reset(loc) 134 * cpu_xscale_reset(loc)
diff --git a/arch/arm/mm/vmregion.c b/arch/arm/mm/vmregion.c
index 19e09bdb1b8a..935993e1b1ef 100644
--- a/arch/arm/mm/vmregion.c
+++ b/arch/arm/mm/vmregion.c
@@ -35,7 +35,8 @@
35 */ 35 */
36 36
37struct arm_vmregion * 37struct arm_vmregion *
38arm_vmregion_alloc(struct arm_vmregion_head *head, size_t size, gfp_t gfp) 38arm_vmregion_alloc(struct arm_vmregion_head *head, size_t align,
39 size_t size, gfp_t gfp)
39{ 40{
40 unsigned long addr = head->vm_start, end = head->vm_end - size; 41 unsigned long addr = head->vm_start, end = head->vm_end - size;
41 unsigned long flags; 42 unsigned long flags;
@@ -58,7 +59,7 @@ arm_vmregion_alloc(struct arm_vmregion_head *head, size_t size, gfp_t gfp)
58 goto nospc; 59 goto nospc;
59 if ((addr + size) <= c->vm_start) 60 if ((addr + size) <= c->vm_start)
60 goto found; 61 goto found;
61 addr = c->vm_end; 62 addr = ALIGN(c->vm_end, align);
62 if (addr > end) 63 if (addr > end)
63 goto nospc; 64 goto nospc;
64 } 65 }
diff --git a/arch/arm/mm/vmregion.h b/arch/arm/mm/vmregion.h
index 6b2cdbdf3a85..15e9f044db9f 100644
--- a/arch/arm/mm/vmregion.h
+++ b/arch/arm/mm/vmregion.h
@@ -21,7 +21,7 @@ struct arm_vmregion {
21 int vm_active; 21 int vm_active;
22}; 22};
23 23
24struct arm_vmregion *arm_vmregion_alloc(struct arm_vmregion_head *, size_t, gfp_t); 24struct arm_vmregion *arm_vmregion_alloc(struct arm_vmregion_head *, size_t, size_t, gfp_t);
25struct arm_vmregion *arm_vmregion_find(struct arm_vmregion_head *, unsigned long); 25struct arm_vmregion *arm_vmregion_find(struct arm_vmregion_head *, unsigned long);
26struct arm_vmregion *arm_vmregion_find_remove(struct arm_vmregion_head *, unsigned long); 26struct arm_vmregion *arm_vmregion_find_remove(struct arm_vmregion_head *, unsigned long);
27void arm_vmregion_free(struct arm_vmregion_head *, struct arm_vmregion *); 27void arm_vmregion_free(struct arm_vmregion_head *, struct arm_vmregion *);
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index ce31f316ac75..43f2b158237c 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -359,7 +359,7 @@ static void __init iop3xx_atu_debug(void)
359 DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD); 359 DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
360 DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR); 360 DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
361 361
362 hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort"); 362 hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, 0, "imprecise external abort");
363} 363}
364 364
365/* for platforms that might be host-bus-adapters */ 365/* for platforms that might be host-bus-adapters */
diff --git a/drivers/gpio/pl061.c b/drivers/gpio/pl061.c
index ee568c8fcbd0..5005990f751f 100644
--- a/drivers/gpio/pl061.c
+++ b/drivers/gpio/pl061.c
@@ -232,7 +232,7 @@ static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
232 desc->chip->unmask(irq); 232 desc->chip->unmask(irq);
233} 233}
234 234
235static int __init pl061_probe(struct amba_device *dev, struct amba_id *id) 235static int pl061_probe(struct amba_device *dev, struct amba_id *id)
236{ 236{
237 struct pl061_platform_data *pdata; 237 struct pl061_platform_data *pdata;
238 struct pl061_gpio *chip; 238 struct pl061_gpio *chip;
@@ -333,7 +333,7 @@ free_mem:
333 return ret; 333 return ret;
334} 334}
335 335
336static struct amba_id pl061_ids[] __initdata = { 336static struct amba_id pl061_ids[] = {
337 { 337 {
338 .id = 0x00041061, 338 .id = 0x00041061,
339 .mask = 0x000fffff, 339 .mask = 0x000fffff,
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 4917af96bae1..7edae83603dd 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -26,7 +26,6 @@
26#include <linux/amba/mmci.h> 26#include <linux/amba/mmci.h>
27#include <linux/regulator/consumer.h> 27#include <linux/regulator/consumer.h>
28 28
29#include <asm/cacheflush.h>
30#include <asm/div64.h> 29#include <asm/div64.h>
31#include <asm/io.h> 30#include <asm/io.h>
32#include <asm/sizes.h> 31#include <asm/sizes.h>
@@ -37,12 +36,39 @@
37 36
38static unsigned int fmax = 515633; 37static unsigned int fmax = 515633;
39 38
39/**
40 * struct variant_data - MMCI variant-specific quirks
41 * @clkreg: default value for MCICLOCK register
42 * @clkreg_enable: enable value for MMCICLOCK register
43 * @datalength_bits: number of bits in the MMCIDATALENGTH register
44 */
45struct variant_data {
46 unsigned int clkreg;
47 unsigned int clkreg_enable;
48 unsigned int datalength_bits;
49};
50
51static struct variant_data variant_arm = {
52 .datalength_bits = 16,
53};
54
55static struct variant_data variant_u300 = {
56 .clkreg_enable = 1 << 13, /* HWFCEN */
57 .datalength_bits = 16,
58};
59
60static struct variant_data variant_ux500 = {
61 .clkreg = MCI_CLK_ENABLE,
62 .clkreg_enable = 1 << 14, /* HWFCEN */
63 .datalength_bits = 24,
64};
40/* 65/*
41 * This must be called with host->lock held 66 * This must be called with host->lock held
42 */ 67 */
43static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 68static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
44{ 69{
45 u32 clk = 0; 70 struct variant_data *variant = host->variant;
71 u32 clk = variant->clkreg;
46 72
47 if (desired) { 73 if (desired) {
48 if (desired >= host->mclk) { 74 if (desired >= host->mclk) {
@@ -54,8 +80,8 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
54 clk = 255; 80 clk = 255;
55 host->cclk = host->mclk / (2 * (clk + 1)); 81 host->cclk = host->mclk / (2 * (clk + 1));
56 } 82 }
57 if (host->hw_designer == AMBA_VENDOR_ST) 83
58 clk |= MCI_ST_FCEN; /* Bug fix in ST IP block */ 84 clk |= variant->clkreg_enable;
59 clk |= MCI_CLK_ENABLE; 85 clk |= MCI_CLK_ENABLE;
60 /* This hasn't proven to be worthwhile */ 86 /* This hasn't proven to be worthwhile */
61 /* clk |= MCI_CLK_PWRSAVE; */ 87 /* clk |= MCI_CLK_PWRSAVE; */
@@ -98,6 +124,18 @@ static void mmci_stop_data(struct mmci_host *host)
98 host->data = NULL; 124 host->data = NULL;
99} 125}
100 126
127static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
128{
129 unsigned int flags = SG_MITER_ATOMIC;
130
131 if (data->flags & MMC_DATA_READ)
132 flags |= SG_MITER_TO_SG;
133 else
134 flags |= SG_MITER_FROM_SG;
135
136 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
137}
138
101static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 139static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
102{ 140{
103 unsigned int datactrl, timeout, irqmask; 141 unsigned int datactrl, timeout, irqmask;
@@ -109,7 +147,7 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
109 data->blksz, data->blocks, data->flags); 147 data->blksz, data->blocks, data->flags);
110 148
111 host->data = data; 149 host->data = data;
112 host->size = data->blksz; 150 host->size = data->blksz * data->blocks;
113 host->data_xfered = 0; 151 host->data_xfered = 0;
114 152
115 mmci_init_sg(host, data); 153 mmci_init_sg(host, data);
@@ -210,8 +248,17 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
210 * We hit an error condition. Ensure that any data 248 * We hit an error condition. Ensure that any data
211 * partially written to a page is properly coherent. 249 * partially written to a page is properly coherent.
212 */ 250 */
213 if (host->sg_len && data->flags & MMC_DATA_READ) 251 if (data->flags & MMC_DATA_READ) {
214 flush_dcache_page(sg_page(host->sg_ptr)); 252 struct sg_mapping_iter *sg_miter = &host->sg_miter;
253 unsigned long flags;
254
255 local_irq_save(flags);
256 if (sg_miter_next(sg_miter)) {
257 flush_dcache_page(sg_miter->page);
258 sg_miter_stop(sg_miter);
259 }
260 local_irq_restore(flags);
261 }
215 } 262 }
216 if (status & MCI_DATAEND) { 263 if (status & MCI_DATAEND) {
217 mmci_stop_data(host); 264 mmci_stop_data(host);
@@ -314,15 +361,18 @@ static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int rem
314static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 361static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
315{ 362{
316 struct mmci_host *host = dev_id; 363 struct mmci_host *host = dev_id;
364 struct sg_mapping_iter *sg_miter = &host->sg_miter;
317 void __iomem *base = host->base; 365 void __iomem *base = host->base;
366 unsigned long flags;
318 u32 status; 367 u32 status;
319 368
320 status = readl(base + MMCISTATUS); 369 status = readl(base + MMCISTATUS);
321 370
322 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 371 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
323 372
373 local_irq_save(flags);
374
324 do { 375 do {
325 unsigned long flags;
326 unsigned int remain, len; 376 unsigned int remain, len;
327 char *buffer; 377 char *buffer;
328 378
@@ -336,11 +386,11 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
336 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 386 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
337 break; 387 break;
338 388
339 /* 389 if (!sg_miter_next(sg_miter))
340 * Map the current scatter buffer. 390 break;
341 */ 391
342 buffer = mmci_kmap_atomic(host, &flags) + host->sg_off; 392 buffer = sg_miter->addr;
343 remain = host->sg_ptr->length - host->sg_off; 393 remain = sg_miter->length;
344 394
345 len = 0; 395 len = 0;
346 if (status & MCI_RXACTIVE) 396 if (status & MCI_RXACTIVE)
@@ -348,31 +398,24 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
348 if (status & MCI_TXACTIVE) 398 if (status & MCI_TXACTIVE)
349 len = mmci_pio_write(host, buffer, remain, status); 399 len = mmci_pio_write(host, buffer, remain, status);
350 400
351 /* 401 sg_miter->consumed = len;
352 * Unmap the buffer.
353 */
354 mmci_kunmap_atomic(host, buffer, &flags);
355 402
356 host->sg_off += len;
357 host->size -= len; 403 host->size -= len;
358 remain -= len; 404 remain -= len;
359 405
360 if (remain) 406 if (remain)
361 break; 407 break;
362 408
363 /*
364 * If we were reading, and we have completed this
365 * page, ensure that the data cache is coherent.
366 */
367 if (status & MCI_RXACTIVE) 409 if (status & MCI_RXACTIVE)
368 flush_dcache_page(sg_page(host->sg_ptr)); 410 flush_dcache_page(sg_miter->page);
369
370 if (!mmci_next_sg(host))
371 break;
372 411
373 status = readl(base + MMCISTATUS); 412 status = readl(base + MMCISTATUS);
374 } while (1); 413 } while (1);
375 414
415 sg_miter_stop(sg_miter);
416
417 local_irq_restore(flags);
418
376 /* 419 /*
377 * If we're nearing the end of the read, switch to 420 * If we're nearing the end of the read, switch to
378 * "any data available" mode. 421 * "any data available" mode.
@@ -477,16 +520,9 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
477 /* This implicitly enables the regulator */ 520 /* This implicitly enables the regulator */
478 mmc_regulator_set_ocr(host->vcc, ios->vdd); 521 mmc_regulator_set_ocr(host->vcc, ios->vdd);
479#endif 522#endif
480 /* 523 if (host->plat->vdd_handler)
481 * The translate_vdd function is not used if you have 524 pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd,
482 * an external regulator, or your design is really weird. 525 ios->power_mode);
483 * Using it would mean sending in power control BOTH using
484 * a regulator AND the 4 MMCIPWR bits. If we don't have
485 * a regulator, we might have some other platform specific
486 * power control behind this translate function.
487 */
488 if (!host->vcc && host->plat->translate_vdd)
489 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
490 /* The ST version does not have this, fall through to POWER_ON */ 526 /* The ST version does not have this, fall through to POWER_ON */
491 if (host->hw_designer != AMBA_VENDOR_ST) { 527 if (host->hw_designer != AMBA_VENDOR_ST) {
492 pwr |= MCI_PWR_UP; 528 pwr |= MCI_PWR_UP;
@@ -551,21 +587,10 @@ static const struct mmc_host_ops mmci_ops = {
551 .get_cd = mmci_get_cd, 587 .get_cd = mmci_get_cd,
552}; 588};
553 589
554static void mmci_check_status(unsigned long data)
555{
556 struct mmci_host *host = (struct mmci_host *)data;
557 unsigned int status = mmci_get_cd(host->mmc);
558
559 if (status ^ host->oldstat)
560 mmc_detect_change(host->mmc, 0);
561
562 host->oldstat = status;
563 mod_timer(&host->timer, jiffies + HZ);
564}
565
566static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) 590static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
567{ 591{
568 struct mmci_platform_data *plat = dev->dev.platform_data; 592 struct mmci_platform_data *plat = dev->dev.platform_data;
593 struct variant_data *variant = id->data;
569 struct mmci_host *host; 594 struct mmci_host *host;
570 struct mmc_host *mmc; 595 struct mmc_host *mmc;
571 int ret; 596 int ret;
@@ -609,6 +634,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
609 goto clk_free; 634 goto clk_free;
610 635
611 host->plat = plat; 636 host->plat = plat;
637 host->variant = variant;
612 host->mclk = clk_get_rate(host->clk); 638 host->mclk = clk_get_rate(host->clk);
613 /* 639 /*
614 * According to the spec, mclk is max 100 MHz, 640 * According to the spec, mclk is max 100 MHz,
@@ -669,6 +695,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
669 if (host->vcc == NULL) 695 if (host->vcc == NULL)
670 mmc->ocr_avail = plat->ocr_mask; 696 mmc->ocr_avail = plat->ocr_mask;
671 mmc->caps = plat->capabilities; 697 mmc->caps = plat->capabilities;
698 mmc->caps |= MMC_CAP_NEEDS_POLL;
672 699
673 /* 700 /*
674 * We can do SGIO 701 * We can do SGIO
@@ -677,10 +704,11 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
677 mmc->max_phys_segs = NR_SG; 704 mmc->max_phys_segs = NR_SG;
678 705
679 /* 706 /*
680 * Since we only have a 16-bit data length register, we must 707 * Since only a certain number of bits are valid in the data length
681 * ensure that we don't exceed 2^16-1 bytes in a single request. 708 * register, we must ensure that we don't exceed 2^num-1 bytes in a
709 * single request.
682 */ 710 */
683 mmc->max_req_size = 65535; 711 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
684 712
685 /* 713 /*
686 * Set the maximum segment size. Since we aren't doing DMA 714 * Set the maximum segment size. Since we aren't doing DMA
@@ -734,7 +762,6 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
734 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 762 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
735 763
736 amba_set_drvdata(dev, mmc); 764 amba_set_drvdata(dev, mmc);
737 host->oldstat = mmci_get_cd(host->mmc);
738 765
739 mmc_add_host(mmc); 766 mmc_add_host(mmc);
740 767
@@ -742,12 +769,6 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
742 mmc_hostname(mmc), amba_rev(dev), amba_config(dev), 769 mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
743 (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); 770 (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);
744 771
745 init_timer(&host->timer);
746 host->timer.data = (unsigned long)host;
747 host->timer.function = mmci_check_status;
748 host->timer.expires = jiffies + HZ;
749 add_timer(&host->timer);
750
751 return 0; 772 return 0;
752 773
753 irq0_free: 774 irq0_free:
@@ -781,8 +802,6 @@ static int __devexit mmci_remove(struct amba_device *dev)
781 if (mmc) { 802 if (mmc) {
782 struct mmci_host *host = mmc_priv(mmc); 803 struct mmci_host *host = mmc_priv(mmc);
783 804
784 del_timer_sync(&host->timer);
785
786 mmc_remove_host(mmc); 805 mmc_remove_host(mmc);
787 806
788 writel(0, host->base + MMCIMASK0); 807 writel(0, host->base + MMCIMASK0);
@@ -856,19 +875,28 @@ static struct amba_id mmci_ids[] = {
856 { 875 {
857 .id = 0x00041180, 876 .id = 0x00041180,
858 .mask = 0x000fffff, 877 .mask = 0x000fffff,
878 .data = &variant_arm,
859 }, 879 },
860 { 880 {
861 .id = 0x00041181, 881 .id = 0x00041181,
862 .mask = 0x000fffff, 882 .mask = 0x000fffff,
883 .data = &variant_arm,
863 }, 884 },
864 /* ST Micro variants */ 885 /* ST Micro variants */
865 { 886 {
866 .id = 0x00180180, 887 .id = 0x00180180,
867 .mask = 0x00ffffff, 888 .mask = 0x00ffffff,
889 .data = &variant_u300,
868 }, 890 },
869 { 891 {
870 .id = 0x00280180, 892 .id = 0x00280180,
871 .mask = 0x00ffffff, 893 .mask = 0x00ffffff,
894 .data = &variant_u300,
895 },
896 {
897 .id = 0x00480180,
898 .mask = 0x00ffffff,
899 .data = &variant_ux500,
872 }, 900 },
873 { 0, 0 }, 901 { 0, 0 },
874}; 902};
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index d77062e5e3af..68970cfb81e1 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -28,8 +28,6 @@
28#define MCI_4BIT_BUS (1 << 11) 28#define MCI_4BIT_BUS (1 << 11)
29/* 8bit wide buses supported in ST Micro versions */ 29/* 8bit wide buses supported in ST Micro versions */
30#define MCI_ST_8BIT_BUS (1 << 12) 30#define MCI_ST_8BIT_BUS (1 << 12)
31/* HW flow control on the ST Micro version */
32#define MCI_ST_FCEN (1 << 13)
33 31
34#define MMCIARGUMENT 0x008 32#define MMCIARGUMENT 0x008
35#define MMCICOMMAND 0x00c 33#define MMCICOMMAND 0x00c
@@ -145,6 +143,7 @@
145#define NR_SG 16 143#define NR_SG 16
146 144
147struct clk; 145struct clk;
146struct variant_data;
148 147
149struct mmci_host { 148struct mmci_host {
150 void __iomem *base; 149 void __iomem *base;
@@ -164,6 +163,7 @@ struct mmci_host {
164 unsigned int cclk; 163 unsigned int cclk;
165 u32 pwr; 164 u32 pwr;
166 struct mmci_platform_data *plat; 165 struct mmci_platform_data *plat;
166 struct variant_data *variant;
167 167
168 u8 hw_designer; 168 u8 hw_designer;
169 u8 hw_revision:4; 169 u8 hw_revision:4;
@@ -171,42 +171,9 @@ struct mmci_host {
171 struct timer_list timer; 171 struct timer_list timer;
172 unsigned int oldstat; 172 unsigned int oldstat;
173 173
174 unsigned int sg_len;
175
176 /* pio stuff */ 174 /* pio stuff */
177 struct scatterlist *sg_ptr; 175 struct sg_mapping_iter sg_miter;
178 unsigned int sg_off;
179 unsigned int size; 176 unsigned int size;
180 struct regulator *vcc; 177 struct regulator *vcc;
181}; 178};
182 179
183static inline void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
184{
185 /*
186 * Ideally, we want the higher levels to pass us a scatter list.
187 */
188 host->sg_len = data->sg_len;
189 host->sg_ptr = data->sg;
190 host->sg_off = 0;
191}
192
193static inline int mmci_next_sg(struct mmci_host *host)
194{
195 host->sg_ptr++;
196 host->sg_off = 0;
197 return --host->sg_len;
198}
199
200static inline char *mmci_kmap_atomic(struct mmci_host *host, unsigned long *flags)
201{
202 struct scatterlist *sg = host->sg_ptr;
203
204 local_irq_save(*flags);
205 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
206}
207
208static inline void mmci_kunmap_atomic(struct mmci_host *host, void *buffer, unsigned long *flags)
209{
210 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
211 local_irq_restore(*flags);
212}
diff --git a/drivers/rtc/rtc-pl031.c b/drivers/rtc/rtc-pl031.c
index 3587d9922f28..71bbefc3544e 100644
--- a/drivers/rtc/rtc-pl031.c
+++ b/drivers/rtc/rtc-pl031.c
@@ -456,7 +456,7 @@ static struct rtc_class_ops stv2_pl031_ops = {
456 .irq_set_freq = pl031_irq_set_freq, 456 .irq_set_freq = pl031_irq_set_freq,
457}; 457};
458 458
459static struct amba_id pl031_ids[] __initdata = { 459static struct amba_id pl031_ids[] = {
460 { 460 {
461 .id = 0x00041031, 461 .id = 0x00041031,
462 .mask = 0x000fffff, 462 .mask = 0x000fffff,
diff --git a/drivers/serial/amba-pl010.c b/drivers/serial/amba-pl010.c
index b09a638d051f..50441ffe8e38 100644
--- a/drivers/serial/amba-pl010.c
+++ b/drivers/serial/amba-pl010.c
@@ -782,7 +782,7 @@ static int pl010_resume(struct amba_device *dev)
782 return 0; 782 return 0;
783} 783}
784 784
785static struct amba_id pl010_ids[] __initdata = { 785static struct amba_id pl010_ids[] = {
786 { 786 {
787 .id = 0x00041010, 787 .id = 0x00041010,
788 .mask = 0x000fffff, 788 .mask = 0x000fffff,
diff --git a/drivers/serial/amba-pl011.c b/drivers/serial/amba-pl011.c
index eb4cb480b93e..6ca7a44f29c2 100644
--- a/drivers/serial/amba-pl011.c
+++ b/drivers/serial/amba-pl011.c
@@ -69,9 +69,12 @@
69struct uart_amba_port { 69struct uart_amba_port {
70 struct uart_port port; 70 struct uart_port port;
71 struct clk *clk; 71 struct clk *clk;
72 unsigned int im; /* interrupt mask */ 72 unsigned int im; /* interrupt mask */
73 unsigned int old_status; 73 unsigned int old_status;
74 unsigned int ifls; /* vendor-specific */ 74 unsigned int ifls; /* vendor-specific */
75 unsigned int lcrh_tx; /* vendor-specific */
76 unsigned int lcrh_rx; /* vendor-specific */
77 bool oversampling; /* vendor-specific */
75 bool autorts; 78 bool autorts;
76}; 79};
77 80
@@ -79,16 +82,25 @@ struct uart_amba_port {
79struct vendor_data { 82struct vendor_data {
80 unsigned int ifls; 83 unsigned int ifls;
81 unsigned int fifosize; 84 unsigned int fifosize;
85 unsigned int lcrh_tx;
86 unsigned int lcrh_rx;
87 bool oversampling;
82}; 88};
83 89
84static struct vendor_data vendor_arm = { 90static struct vendor_data vendor_arm = {
85 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 91 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
86 .fifosize = 16, 92 .fifosize = 16,
93 .lcrh_tx = UART011_LCRH,
94 .lcrh_rx = UART011_LCRH,
95 .oversampling = false,
87}; 96};
88 97
89static struct vendor_data vendor_st = { 98static struct vendor_data vendor_st = {
90 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, 99 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
91 .fifosize = 64, 100 .fifosize = 64,
101 .lcrh_tx = ST_UART011_LCRH_TX,
102 .lcrh_rx = ST_UART011_LCRH_RX,
103 .oversampling = true,
92}; 104};
93 105
94static void pl011_stop_tx(struct uart_port *port) 106static void pl011_stop_tx(struct uart_port *port)
@@ -327,12 +339,12 @@ static void pl011_break_ctl(struct uart_port *port, int break_state)
327 unsigned int lcr_h; 339 unsigned int lcr_h;
328 340
329 spin_lock_irqsave(&uap->port.lock, flags); 341 spin_lock_irqsave(&uap->port.lock, flags);
330 lcr_h = readw(uap->port.membase + UART011_LCRH); 342 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
331 if (break_state == -1) 343 if (break_state == -1)
332 lcr_h |= UART01x_LCRH_BRK; 344 lcr_h |= UART01x_LCRH_BRK;
333 else 345 else
334 lcr_h &= ~UART01x_LCRH_BRK; 346 lcr_h &= ~UART01x_LCRH_BRK;
335 writew(lcr_h, uap->port.membase + UART011_LCRH); 347 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
336 spin_unlock_irqrestore(&uap->port.lock, flags); 348 spin_unlock_irqrestore(&uap->port.lock, flags);
337} 349}
338 350
@@ -393,7 +405,17 @@ static int pl011_startup(struct uart_port *port)
393 writew(cr, uap->port.membase + UART011_CR); 405 writew(cr, uap->port.membase + UART011_CR);
394 writew(0, uap->port.membase + UART011_FBRD); 406 writew(0, uap->port.membase + UART011_FBRD);
395 writew(1, uap->port.membase + UART011_IBRD); 407 writew(1, uap->port.membase + UART011_IBRD);
396 writew(0, uap->port.membase + UART011_LCRH); 408 writew(0, uap->port.membase + uap->lcrh_rx);
409 if (uap->lcrh_tx != uap->lcrh_rx) {
410 int i;
411 /*
412 * Wait 10 PCLKs before writing LCRH_TX register,
413 * to get this delay write read only register 10 times
414 */
415 for (i = 0; i < 10; ++i)
416 writew(0xff, uap->port.membase + UART011_MIS);
417 writew(0, uap->port.membase + uap->lcrh_tx);
418 }
397 writew(0, uap->port.membase + UART01x_DR); 419 writew(0, uap->port.membase + UART01x_DR);
398 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) 420 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
399 barrier(); 421 barrier();
@@ -422,10 +444,19 @@ static int pl011_startup(struct uart_port *port)
422 return retval; 444 return retval;
423} 445}
424 446
447static void pl011_shutdown_channel(struct uart_amba_port *uap,
448 unsigned int lcrh)
449{
450 unsigned long val;
451
452 val = readw(uap->port.membase + lcrh);
453 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
454 writew(val, uap->port.membase + lcrh);
455}
456
425static void pl011_shutdown(struct uart_port *port) 457static void pl011_shutdown(struct uart_port *port)
426{ 458{
427 struct uart_amba_port *uap = (struct uart_amba_port *)port; 459 struct uart_amba_port *uap = (struct uart_amba_port *)port;
428 unsigned long val;
429 460
430 /* 461 /*
431 * disable all interrupts 462 * disable all interrupts
@@ -450,9 +481,9 @@ static void pl011_shutdown(struct uart_port *port)
450 /* 481 /*
451 * disable break condition and fifos 482 * disable break condition and fifos
452 */ 483 */
453 val = readw(uap->port.membase + UART011_LCRH); 484 pl011_shutdown_channel(uap, uap->lcrh_rx);
454 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); 485 if (uap->lcrh_rx != uap->lcrh_tx)
455 writew(val, uap->port.membase + UART011_LCRH); 486 pl011_shutdown_channel(uap, uap->lcrh_tx);
456 487
457 /* 488 /*
458 * Shut down the clock producer 489 * Shut down the clock producer
@@ -472,8 +503,13 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
472 /* 503 /*
473 * Ask the core to calculate the divisor for us. 504 * Ask the core to calculate the divisor for us.
474 */ 505 */
475 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 506 baud = uart_get_baud_rate(port, termios, old, 0,
476 quot = port->uartclk * 4 / baud; 507 port->uartclk/(uap->oversampling ? 8 : 16));
508
509 if (baud > port->uartclk/16)
510 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
511 else
512 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
477 513
478 switch (termios->c_cflag & CSIZE) { 514 switch (termios->c_cflag & CSIZE) {
479 case CS5: 515 case CS5:
@@ -552,6 +588,13 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
552 uap->autorts = false; 588 uap->autorts = false;
553 } 589 }
554 590
591 if (uap->oversampling) {
592 if (baud > port->uartclk/16)
593 old_cr |= ST_UART011_CR_OVSFACT;
594 else
595 old_cr &= ~ST_UART011_CR_OVSFACT;
596 }
597
555 /* Set baud rate */ 598 /* Set baud rate */
556 writew(quot & 0x3f, port->membase + UART011_FBRD); 599 writew(quot & 0x3f, port->membase + UART011_FBRD);
557 writew(quot >> 6, port->membase + UART011_IBRD); 600 writew(quot >> 6, port->membase + UART011_IBRD);
@@ -561,7 +604,17 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
561 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L 604 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
562 * ----------^----------^----------^----------^----- 605 * ----------^----------^----------^----------^-----
563 */ 606 */
564 writew(lcr_h, port->membase + UART011_LCRH); 607 writew(lcr_h, port->membase + uap->lcrh_rx);
608 if (uap->lcrh_rx != uap->lcrh_tx) {
609 int i;
610 /*
611 * Wait 10 PCLKs before writing LCRH_TX register,
612 * to get this delay write read only register 10 times
613 */
614 for (i = 0; i < 10; ++i)
615 writew(0xff, uap->port.membase + UART011_MIS);
616 writew(lcr_h, port->membase + uap->lcrh_tx);
617 }
565 writew(old_cr, port->membase + UART011_CR); 618 writew(old_cr, port->membase + UART011_CR);
566 619
567 spin_unlock_irqrestore(&port->lock, flags); 620 spin_unlock_irqrestore(&port->lock, flags);
@@ -688,7 +741,7 @@ pl011_console_get_options(struct uart_amba_port *uap, int *baud,
688 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { 741 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
689 unsigned int lcr_h, ibrd, fbrd; 742 unsigned int lcr_h, ibrd, fbrd;
690 743
691 lcr_h = readw(uap->port.membase + UART011_LCRH); 744 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
692 745
693 *parity = 'n'; 746 *parity = 'n';
694 if (lcr_h & UART01x_LCRH_PEN) { 747 if (lcr_h & UART01x_LCRH_PEN) {
@@ -707,6 +760,12 @@ pl011_console_get_options(struct uart_amba_port *uap, int *baud,
707 fbrd = readw(uap->port.membase + UART011_FBRD); 760 fbrd = readw(uap->port.membase + UART011_FBRD);
708 761
709 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); 762 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
763
764 if (uap->oversampling) {
765 if (readw(uap->port.membase + UART011_CR)
766 & ST_UART011_CR_OVSFACT)
767 *baud *= 2;
768 }
710 } 769 }
711} 770}
712 771
@@ -800,6 +859,9 @@ static int pl011_probe(struct amba_device *dev, struct amba_id *id)
800 } 859 }
801 860
802 uap->ifls = vendor->ifls; 861 uap->ifls = vendor->ifls;
862 uap->lcrh_rx = vendor->lcrh_rx;
863 uap->lcrh_tx = vendor->lcrh_tx;
864 uap->oversampling = vendor->oversampling;
803 uap->port.dev = &dev->dev; 865 uap->port.dev = &dev->dev;
804 uap->port.mapbase = dev->res.start; 866 uap->port.mapbase = dev->res.start;
805 uap->port.membase = base; 867 uap->port.membase = base;
@@ -868,7 +930,7 @@ static int pl011_resume(struct amba_device *dev)
868} 930}
869#endif 931#endif
870 932
871static struct amba_id pl011_ids[] __initdata = { 933static struct amba_id pl011_ids[] = {
872 { 934 {
873 .id = 0x00041011, 935 .id = 0x00041011,
874 .mask = 0x000fffff, 936 .mask = 0x000fffff,
diff --git a/include/linux/amba/mmci.h b/include/linux/amba/mmci.h
index 7e466fe72025..ca84ce70d5d5 100644
--- a/include/linux/amba/mmci.h
+++ b/include/linux/amba/mmci.h
@@ -15,9 +15,10 @@
15 * @ocr_mask: available voltages on the 4 pins from the block, this 15 * @ocr_mask: available voltages on the 4 pins from the block, this
16 * is ignored if a regulator is used, see the MMC_VDD_* masks in 16 * is ignored if a regulator is used, see the MMC_VDD_* masks in
17 * mmc/host.h 17 * mmc/host.h
18 * @translate_vdd: a callback function to translate a MMC_VDD_* 18 * @vdd_handler: a callback function to translate a MMC_VDD_*
19 * mask into a value to be binary or:ed and written into the 19 * mask into a value to be binary (or set some other custom bits
20 * MMCIPWR register of the block 20 * in MMCIPWR) or:ed and written into the MMCIPWR register of the
21 * block. May also control external power based on the power_mode.
21 * @status: if no GPIO read function was given to the block in 22 * @status: if no GPIO read function was given to the block in
22 * gpio_wp (below) this function will be called to determine 23 * gpio_wp (below) this function will be called to determine
23 * whether a card is present in the MMC slot or not 24 * whether a card is present in the MMC slot or not
@@ -29,7 +30,8 @@
29struct mmci_platform_data { 30struct mmci_platform_data {
30 unsigned int f_max; 31 unsigned int f_max;
31 unsigned int ocr_mask; 32 unsigned int ocr_mask;
32 u32 (*translate_vdd)(struct device *, unsigned int); 33 u32 (*vdd_handler)(struct device *, unsigned int vdd,
34 unsigned char power_mode);
33 unsigned int (*status)(struct device *); 35 unsigned int (*status)(struct device *);
34 int gpio_wp; 36 int gpio_wp;
35 int gpio_cd; 37 int gpio_cd;
diff --git a/include/linux/amba/serial.h b/include/linux/amba/serial.h
index 5a5a7fd62490..e1b634b635f2 100644
--- a/include/linux/amba/serial.h
+++ b/include/linux/amba/serial.h
@@ -38,10 +38,12 @@
38#define UART01x_FR 0x18 /* Flag register (Read only). */ 38#define UART01x_FR 0x18 /* Flag register (Read only). */
39#define UART010_IIR 0x1C /* Interrupt indentification register (Read). */ 39#define UART010_IIR 0x1C /* Interrupt indentification register (Read). */
40#define UART010_ICR 0x1C /* Interrupt clear register (Write). */ 40#define UART010_ICR 0x1C /* Interrupt clear register (Write). */
41#define ST_UART011_LCRH_RX 0x1C /* Rx line control register. */
41#define UART01x_ILPR 0x20 /* IrDA low power counter register. */ 42#define UART01x_ILPR 0x20 /* IrDA low power counter register. */
42#define UART011_IBRD 0x24 /* Integer baud rate divisor register. */ 43#define UART011_IBRD 0x24 /* Integer baud rate divisor register. */
43#define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */ 44#define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */
44#define UART011_LCRH 0x2c /* Line control register. */ 45#define UART011_LCRH 0x2c /* Line control register. */
46#define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */
45#define UART011_CR 0x30 /* Control register. */ 47#define UART011_CR 0x30 /* Control register. */
46#define UART011_IFLS 0x34 /* Interrupt fifo level select. */ 48#define UART011_IFLS 0x34 /* Interrupt fifo level select. */
47#define UART011_IMSC 0x38 /* Interrupt mask. */ 49#define UART011_IMSC 0x38 /* Interrupt mask. */
@@ -84,6 +86,7 @@
84#define UART010_CR_TIE 0x0020 86#define UART010_CR_TIE 0x0020
85#define UART010_CR_RIE 0x0010 87#define UART010_CR_RIE 0x0010
86#define UART010_CR_MSIE 0x0008 88#define UART010_CR_MSIE 0x0008
89#define ST_UART011_CR_OVSFACT 0x0008 /* Oversampling factor */
87#define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */ 90#define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */
88#define UART01x_CR_SIREN 0x0002 /* SIR enable */ 91#define UART01x_CR_SIREN 0x0002 /* SIR enable */
89#define UART01x_CR_UARTEN 0x0001 /* UART enable */ 92#define UART01x_CR_UARTEN 0x0001 /* UART enable */
diff --git a/lib/atomic64_test.c b/lib/atomic64_test.c
index 250ed11d3ed2..44524cc8c32a 100644
--- a/lib/atomic64_test.c
+++ b/lib/atomic64_test.c
@@ -114,7 +114,7 @@ static __init int test_atomic64(void)
114 BUG_ON(v.counter != r); 114 BUG_ON(v.counter != r);
115 115
116#if defined(CONFIG_X86) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 116#if defined(CONFIG_X86) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
117 defined(CONFIG_S390) || defined(_ASM_GENERIC_ATOMIC64_H) 117 defined(CONFIG_S390) || defined(_ASM_GENERIC_ATOMIC64_H) || defined(CONFIG_ARM)
118 INIT(onestwos); 118 INIT(onestwos);
119 BUG_ON(atomic64_dec_if_positive(&v) != (onestwos - 1)); 119 BUG_ON(atomic64_dec_if_positive(&v) != (onestwos - 1));
120 r -= one; 120 r -= one;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 23:40:46 -0500