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-rw-r--r--arch/avr32/Kconfig3
-rw-r--r--arch/avr32/mach-at32ap/at32ap7000.c4
-rw-r--r--arch/avr32/mach-at32ap/hsmc.c1
-rw-r--r--arch/avr32/mach-at32ap/intc.c4
-rw-r--r--arch/mips/Kconfig11
-rw-r--r--arch/mips/Makefile2
-rw-r--r--arch/mips/kernel/cevt-bcm1480.c6
-rw-r--r--arch/mips/kernel/cevt-sb1250.c6
-rw-r--r--arch/mips/kernel/cpu-probe.c5
-rw-r--r--arch/mips/kernel/csrc-sb1250.c2
-rw-r--r--arch/mips/kernel/genex.S2
-rw-r--r--arch/mips/kernel/irq-rm7000.c2
-rw-r--r--arch/mips/kernel/irq-rm9000.c2
-rw-r--r--arch/mips/kernel/irq_cpu.c2
-rw-r--r--arch/mips/kernel/proc.c2
-rw-r--r--arch/mips/kernel/scall64-n32.S2
-rw-r--r--arch/mips/kernel/traps.c68
-rw-r--r--arch/mips/kernel/vpe.c14
-rw-r--r--arch/mips/lasat/interrupt.c22
-rw-r--r--arch/mips/mm/c-r4k.c7
-rw-r--r--arch/mips/mm/cerr-sb1.c6
-rw-r--r--arch/mips/mm/init.c2
-rw-r--r--arch/mips/pci/fixup-sni.c23
-rw-r--r--arch/mips/pci/pci-lasat.c32
-rw-r--r--arch/mips/pci/pci-vr41xx.c1
-rw-r--r--arch/mips/qemu/Makefile3
-rw-r--r--arch/mips/qemu/q-console.c26
-rw-r--r--arch/mips/qemu/q-firmware.c6
-rw-r--r--arch/mips/qemu/q-setup.c3
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c21
-rw-r--r--arch/mips/sni/pcimt.c2
-rw-r--r--drivers/i2c/busses/i2c-pasemi.c7
-rw-r--r--drivers/i2c/chips/eeprom.c37
-rw-r--r--drivers/i2c/i2c-core.c3
-rw-r--r--drivers/i2c/i2c-dev.c86
-rw-r--r--drivers/net/skge.c51
-rw-r--r--include/asm-avr32/sysreg.h2
-rw-r--r--include/asm-mips/cpu-info.h1
-rw-r--r--include/asm-mips/lasat/lasatint.h5
-rw-r--r--include/asm-mips/mach-lasat/irq.h13
-rw-r--r--include/asm-mips/timex.h2
-rw-r--r--include/linux/i2c.h5
-rw-r--r--include/pcmcia/cs_types.h2
-rw-r--r--kernel/exit.c3
-rw-r--r--kernel/sched.c62
-rw-r--r--kernel/sched_fair.c2
-rw-r--r--mm/slob.c3
47 files changed, 338 insertions, 238 deletions
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index bbecbd8469b5..4f402c924504 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -19,9 +19,6 @@ config AVR32
19 There is an AVR32 Linux project with a web page at 19 There is an AVR32 Linux project with a web page at
20 http://avr32linux.org/. 20 http://avr32linux.org/.
21 21
22config UID16
23 bool
24
25config GENERIC_GPIO 22config GENERIC_GPIO
26 bool 23 bool
27 default y 24 default y
diff --git a/arch/avr32/mach-at32ap/at32ap7000.c b/arch/avr32/mach-at32ap/at32ap7000.c
index a9d9ec081e3d..7c4388f4f17f 100644
--- a/arch/avr32/mach-at32ap/at32ap7000.c
+++ b/arch/avr32/mach-at32ap/at32ap7000.c
@@ -474,7 +474,7 @@ static struct resource at32ap700x_rtc0_resource[] = {
474static struct resource at32_wdt0_resource[] = { 474static struct resource at32_wdt0_resource[] = {
475 { 475 {
476 .start = 0xfff000b0, 476 .start = 0xfff000b0,
477 .end = 0xfff000bf, 477 .end = 0xfff000cf,
478 .flags = IORESOURCE_MEM, 478 .flags = IORESOURCE_MEM,
479 }, 479 },
480}; 480};
@@ -690,7 +690,7 @@ static struct resource atmel_usart0_resource[] = {
690 IRQ(6), 690 IRQ(6),
691}; 691};
692DEFINE_DEV_DATA(atmel_usart, 0); 692DEFINE_DEV_DATA(atmel_usart, 0);
693DEV_CLK(usart, atmel_usart0, pba, 4); 693DEV_CLK(usart, atmel_usart0, pba, 3);
694 694
695static struct atmel_uart_data atmel_usart1_data = { 695static struct atmel_uart_data atmel_usart1_data = {
696 .use_dma_tx = 1, 696 .use_dma_tx = 1,
diff --git a/arch/avr32/mach-at32ap/hsmc.c b/arch/avr32/mach-at32ap/hsmc.c
index 704607fbcc69..fa427ed42787 100644
--- a/arch/avr32/mach-at32ap/hsmc.c
+++ b/arch/avr32/mach-at32ap/hsmc.c
@@ -7,7 +7,6 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10#define DEBUG
11#include <linux/clk.h> 10#include <linux/clk.h>
12#include <linux/err.h> 11#include <linux/err.h>
13#include <linux/init.h> 12#include <linux/init.h>
diff --git a/arch/avr32/mach-at32ap/intc.c b/arch/avr32/mach-at32ap/intc.c
index dd5c009cf224..0b286cd53028 100644
--- a/arch/avr32/mach-at32ap/intc.c
+++ b/arch/avr32/mach-at32ap/intc.c
@@ -13,6 +13,7 @@
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15 15
16#include <asm/intc.h>
16#include <asm/io.h> 17#include <asm/io.h>
17 18
18#include "intc.h" 19#include "intc.h"
@@ -136,7 +137,8 @@ fail:
136 panic("Interrupt controller initialization failed!\n"); 137 panic("Interrupt controller initialization failed!\n");
137} 138}
138 139
139unsigned long intc_get_pending(int group) 140unsigned long intc_get_pending(unsigned int group)
140{ 141{
141 return intc_readl(&intc0, INTREQ0 + 4 * group); 142 return intc_readl(&intc0, INTREQ0 + 4 * group);
142} 143}
144EXPORT_SYMBOL_GPL(intc_get_pending);
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 2c7d6c240b73..2f2ce0c28bc0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -361,10 +361,10 @@ config QEMU
361 select PCSPEAKER 361 select PCSPEAKER
362 select SWAP_IO_SPACE 362 select SWAP_IO_SPACE
363 select SYS_HAS_CPU_MIPS32_R1 363 select SYS_HAS_CPU_MIPS32_R1
364 select SYS_HAS_EARLY_PRINTK
364 select SYS_SUPPORTS_32BIT_KERNEL 365 select SYS_SUPPORTS_32BIT_KERNEL
365 select SYS_SUPPORTS_BIG_ENDIAN 366 select SYS_SUPPORTS_BIG_ENDIAN
366 select SYS_SUPPORTS_LITTLE_ENDIAN 367 select SYS_SUPPORTS_LITTLE_ENDIAN
367 select ARCH_SPARSEMEM_ENABLE
368 select GENERIC_HARDIRQS_NO__DO_IRQ 368 select GENERIC_HARDIRQS_NO__DO_IRQ
369 select NR_CPUS_DEFAULT_1 369 select NR_CPUS_DEFAULT_1
370 select SYS_SUPPORTS_SMP 370 select SYS_SUPPORTS_SMP
@@ -1409,7 +1409,6 @@ config MIPS_MT_SMP
1409 depends on SYS_SUPPORTS_MULTITHREADING 1409 depends on SYS_SUPPORTS_MULTITHREADING
1410 select CPU_MIPSR2_IRQ_VI 1410 select CPU_MIPSR2_IRQ_VI
1411 select CPU_MIPSR2_IRQ_EI 1411 select CPU_MIPSR2_IRQ_EI
1412 select CPU_MIPSR2_SRS
1413 select MIPS_MT 1412 select MIPS_MT
1414 select NR_CPUS_DEFAULT_2 1413 select NR_CPUS_DEFAULT_2
1415 select SMP 1414 select SMP
@@ -1426,7 +1425,6 @@ config MIPS_MT_SMTC
1426 select GENERIC_CLOCKEVENTS_BROADCAST 1425 select GENERIC_CLOCKEVENTS_BROADCAST
1427 select CPU_MIPSR2_IRQ_VI 1426 select CPU_MIPSR2_IRQ_VI
1428 select CPU_MIPSR2_IRQ_EI 1427 select CPU_MIPSR2_IRQ_EI
1429 select CPU_MIPSR2_SRS
1430 select MIPS_MT 1428 select MIPS_MT
1431 select NR_CPUS_DEFAULT_8 1429 select NR_CPUS_DEFAULT_8
1432 select SMP 1430 select SMP
@@ -1453,7 +1451,6 @@ config MIPS_VPE_LOADER
1453 depends on SYS_SUPPORTS_MULTITHREADING 1451 depends on SYS_SUPPORTS_MULTITHREADING
1454 select CPU_MIPSR2_IRQ_VI 1452 select CPU_MIPSR2_IRQ_VI
1455 select CPU_MIPSR2_IRQ_EI 1453 select CPU_MIPSR2_IRQ_EI
1456 select CPU_MIPSR2_SRS
1457 select MIPS_MT 1454 select MIPS_MT
1458 help 1455 help
1459 Includes a loader for loading an elf relocatable object 1456 Includes a loader for loading an elf relocatable object
@@ -1582,12 +1579,6 @@ config CPU_MIPSR2_IRQ_VI
1582config CPU_MIPSR2_IRQ_EI 1579config CPU_MIPSR2_IRQ_EI
1583 bool 1580 bool
1584 1581
1585#
1586# Shadow registers are an R2 feature
1587#
1588config CPU_MIPSR2_SRS
1589 bool
1590
1591config CPU_HAS_SYNC 1582config CPU_HAS_SYNC
1592 bool 1583 bool
1593 depends on !CPU_R3000 1584 depends on !CPU_R3000
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 23c17755eca0..a1f8d8b96b03 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -44,7 +44,7 @@ endif
44 44
45ifneq ($(SUBARCH),$(ARCH)) 45ifneq ($(SUBARCH),$(ARCH))
46 ifeq ($(CROSS_COMPILE),) 46 ifeq ($(CROSS_COMPILE),)
47 CROSS_COMPILE := $(call cc-cross-prefix, $(tool-archpref)-linux- $(tool-archpref)-gnu-linux- $(tool-archpref)-unknown-gnu-linux-) 47 CROSS_COMPILE := $(call cc-cross-prefix, $(tool-archpref)-linux- $(tool-archpref)-linux-gnu- $(tool-archpref)-unknown-linux-gnu-)
48 endif 48 endif
49endif 49endif
50 50
diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c
index 21e6d63eb4d1..0a57f86945f1 100644
--- a/arch/mips/kernel/cevt-bcm1480.c
+++ b/arch/mips/kernel/cevt-bcm1480.c
@@ -75,6 +75,7 @@ static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
75 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 75 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
76 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); 76 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
77 77
78 __raw_writeq(0, cfg);
78 __raw_writeq(delta - 1, init); 79 __raw_writeq(delta - 1, init);
79 __raw_writeq(M_SCD_TIMER_ENABLE, cfg); 80 __raw_writeq(M_SCD_TIMER_ENABLE, cfg);
80 81
@@ -122,7 +123,7 @@ void __cpuinit sb1480_clockevent_init(void)
122 CLOCK_EVT_FEAT_ONESHOT; 123 CLOCK_EVT_FEAT_ONESHOT;
123 clockevent_set_clock(cd, V_SCD_TIMER_FREQ); 124 clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
124 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd); 125 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
125 cd->min_delta_ns = clockevent_delta2ns(1, cd); 126 cd->min_delta_ns = clockevent_delta2ns(2, cd);
126 cd->rating = 200; 127 cd->rating = 200;
127 cd->irq = irq; 128 cd->irq = irq;
128 cd->cpumask = cpumask_of_cpu(cpu); 129 cd->cpumask = cpumask_of_cpu(cpu);
@@ -143,7 +144,10 @@ void __cpuinit sb1480_clockevent_init(void)
143 144
144 action->handler = sibyte_counter_handler; 145 action->handler = sibyte_counter_handler;
145 action->flags = IRQF_DISABLED | IRQF_PERCPU; 146 action->flags = IRQF_DISABLED | IRQF_PERCPU;
147 action->mask = cpumask_of_cpu(cpu);
146 action->name = name; 148 action->name = name;
147 action->dev_id = cd; 149 action->dev_id = cd;
150
151 irq_set_affinity(irq, cpumask_of_cpu(cpu));
148 setup_irq(irq, action); 152 setup_irq(irq, action);
149} 153}
diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c
index e2029d0fc39b..63ac3ad462bc 100644
--- a/arch/mips/kernel/cevt-sb1250.c
+++ b/arch/mips/kernel/cevt-sb1250.c
@@ -73,6 +73,7 @@ static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
73 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 73 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
74 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); 74 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
75 75
76 __raw_writeq(0, cfg);
76 __raw_writeq(delta - 1, init); 77 __raw_writeq(delta - 1, init);
77 __raw_writeq(M_SCD_TIMER_ENABLE, cfg); 78 __raw_writeq(M_SCD_TIMER_ENABLE, cfg);
78 79
@@ -121,7 +122,7 @@ void __cpuinit sb1250_clockevent_init(void)
121 CLOCK_EVT_FEAT_ONESHOT; 122 CLOCK_EVT_FEAT_ONESHOT;
122 clockevent_set_clock(cd, V_SCD_TIMER_FREQ); 123 clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
123 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd); 124 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
124 cd->min_delta_ns = clockevent_delta2ns(1, cd); 125 cd->min_delta_ns = clockevent_delta2ns(2, cd);
125 cd->rating = 200; 126 cd->rating = 200;
126 cd->irq = irq; 127 cd->irq = irq;
127 cd->cpumask = cpumask_of_cpu(cpu); 128 cd->cpumask = cpumask_of_cpu(cpu);
@@ -142,7 +143,10 @@ void __cpuinit sb1250_clockevent_init(void)
142 143
143 action->handler = sibyte_counter_handler; 144 action->handler = sibyte_counter_handler;
144 action->flags = IRQF_DISABLED | IRQF_PERCPU; 145 action->flags = IRQF_DISABLED | IRQF_PERCPU;
146 action->mask = cpumask_of_cpu(cpu);
145 action->name = name; 147 action->name = name;
146 action->dev_id = cd; 148 action->dev_id = cd;
149
150 irq_set_affinity(irq, cpumask_of_cpu(cpu));
147 setup_irq(irq, action); 151 setup_irq(irq, action);
148} 152}
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c8c47a2d1972..5c2794391bf5 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -943,6 +943,11 @@ __init void cpu_probe(void)
943 } 943 }
944 944
945 __cpu_name[cpu] = cpu_to_name(c); 945 __cpu_name[cpu] = cpu_to_name(c);
946
947 if (cpu_has_mips_r2)
948 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
949 else
950 c->srsets = 1;
946} 951}
947 952
948__init void cpu_report(void) 953__init void cpu_report(void)
diff --git a/arch/mips/kernel/csrc-sb1250.c b/arch/mips/kernel/csrc-sb1250.c
index ebb16e668877..92212bbb8e45 100644
--- a/arch/mips/kernel/csrc-sb1250.c
+++ b/arch/mips/kernel/csrc-sb1250.c
@@ -43,7 +43,7 @@ static cycle_t sb1250_hpt_read(void)
43} 43}
44 44
45struct clocksource bcm1250_clocksource = { 45struct clocksource bcm1250_clocksource = {
46 .name = "MIPS", 46 .name = "bcm1250-counter-3",
47 .rating = 200, 47 .rating = 200,
48 .read = sb1250_hpt_read, 48 .read = sb1250_hpt_read,
49 .mask = CLOCKSOURCE_MASK(23), 49 .mask = CLOCKSOURCE_MASK(23),
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index c0f19d638b98..e76a76bf0b3d 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -146,7 +146,7 @@ NESTED(handle_int, PT_SIZE, sp)
146 and k0, ST0_IEP 146 and k0, ST0_IEP
147 bnez k0, 1f 147 bnez k0, 1f
148 148
149 mfc0 k0, EP0_EPC 149 mfc0 k0, CP0_EPC
150 .set noreorder 150 .set noreorder
151 j k0 151 j k0
152 rfe 152 rfe
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index 250732883488..971adf6ef4f4 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -44,5 +44,5 @@ void __init rm7k_cpu_irq_init(void)
44 44
45 for (i = base; i < base + 4; i++) 45 for (i = base; i < base + 4; i++)
46 set_irq_chip_and_handler(i, &rm7k_irq_controller, 46 set_irq_chip_and_handler(i, &rm7k_irq_controller,
47 handle_level_irq); 47 handle_percpu_irq);
48} 48}
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index ae83d2df6f31..7b04583bd800 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -104,5 +104,5 @@ void __init rm9k_cpu_irq_init(void)
104 104
105 rm9000_perfcount_irq = base + 1; 105 rm9000_perfcount_irq = base + 1;
106 set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq, 106 set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
107 handle_level_irq); 107 handle_percpu_irq);
108} 108}
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 7b66e03b5899..0ee2567b780d 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -116,5 +116,5 @@ void __init mips_cpu_irq_init(void)
116 116
117 for (i = irq_base + 2; i < irq_base + 8; i++) 117 for (i = irq_base + 2; i < irq_base + 8; i++)
118 set_irq_chip_and_handler(i, &mips_cpu_irq_controller, 118 set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
119 handle_level_irq); 119 handle_percpu_irq);
120} 120}
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index efd2d1314123..6e6e947cce1e 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -60,6 +60,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
60 cpu_has_dsp ? " dsp" : "", 60 cpu_has_dsp ? " dsp" : "",
61 cpu_has_mipsmt ? " mt" : "" 61 cpu_has_mipsmt ? " mt" : ""
62 ); 62 );
63 seq_printf(m, "shadow register sets\t: %d\n",
64 cpu_data[n].srsets);
63 65
64 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", 66 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
65 cpu_has_vce ? "%u" : "not available"); 67 cpu_has_vce ? "%u" : "not available");
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 118be24224f2..01993ec3368b 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -293,7 +293,7 @@ EXPORT(sysn32_call_table)
293 PTR sys_ni_syscall /* 6170, was get_kernel_syms */ 293 PTR sys_ni_syscall /* 6170, was get_kernel_syms */
294 PTR sys_ni_syscall /* was query_module */ 294 PTR sys_ni_syscall /* was query_module */
295 PTR sys_quotactl 295 PTR sys_quotactl
296 PTR sys_nfsservctl 296 PTR compat_sys_nfsservctl
297 PTR sys_ni_syscall /* res. for getpmsg */ 297 PTR sys_ni_syscall /* res. for getpmsg */
298 PTR sys_ni_syscall /* 6175 for putpmsg */ 298 PTR sys_ni_syscall /* 6175 for putpmsg */
299 PTR sys_ni_syscall /* res. for afs_syscall */ 299 PTR sys_ni_syscall /* res. for afs_syscall */
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index fa500787152d..23e73d0650a3 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1100,59 +1100,6 @@ void *set_except_vector(int n, void *addr)
1100 return (void *)old_handler; 1100 return (void *)old_handler;
1101} 1101}
1102 1102
1103#ifdef CONFIG_CPU_MIPSR2_SRS
1104/*
1105 * MIPSR2 shadow register set allocation
1106 * FIXME: SMP...
1107 */
1108
1109static struct shadow_registers {
1110 /*
1111 * Number of shadow register sets supported
1112 */
1113 unsigned long sr_supported;
1114 /*
1115 * Bitmap of allocated shadow registers
1116 */
1117 unsigned long sr_allocated;
1118} shadow_registers;
1119
1120static void mips_srs_init(void)
1121{
1122 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1123 printk(KERN_INFO "%ld MIPSR2 register sets available\n",
1124 shadow_registers.sr_supported);
1125 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
1126}
1127
1128int mips_srs_max(void)
1129{
1130 return shadow_registers.sr_supported;
1131}
1132
1133int mips_srs_alloc(void)
1134{
1135 struct shadow_registers *sr = &shadow_registers;
1136 int set;
1137
1138again:
1139 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
1140 if (set >= sr->sr_supported)
1141 return -1;
1142
1143 if (test_and_set_bit(set, &sr->sr_allocated))
1144 goto again;
1145
1146 return set;
1147}
1148
1149void mips_srs_free(int set)
1150{
1151 struct shadow_registers *sr = &shadow_registers;
1152
1153 clear_bit(set, &sr->sr_allocated);
1154}
1155
1156static asmlinkage void do_default_vi(void) 1103static asmlinkage void do_default_vi(void)
1157{ 1104{
1158 show_regs(get_irq_regs()); 1105 show_regs(get_irq_regs());
@@ -1163,6 +1110,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1163{ 1110{
1164 unsigned long handler; 1111 unsigned long handler;
1165 unsigned long old_handler = vi_handlers[n]; 1112 unsigned long old_handler = vi_handlers[n];
1113 int srssets = current_cpu_data.srsets;
1166 u32 *w; 1114 u32 *w;
1167 unsigned char *b; 1115 unsigned char *b;
1168 1116
@@ -1178,7 +1126,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1178 1126
1179 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1127 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1180 1128
1181 if (srs >= mips_srs_max()) 1129 if (srs >= srssets)
1182 panic("Shadow register set %d not supported", srs); 1130 panic("Shadow register set %d not supported", srs);
1183 1131
1184 if (cpu_has_veic) { 1132 if (cpu_has_veic) {
@@ -1186,7 +1134,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1186 board_bind_eic_interrupt(n, srs); 1134 board_bind_eic_interrupt(n, srs);
1187 } else if (cpu_has_vint) { 1135 } else if (cpu_has_vint) {
1188 /* SRSMap is only defined if shadow sets are implemented */ 1136 /* SRSMap is only defined if shadow sets are implemented */
1189 if (mips_srs_max() > 1) 1137 if (srssets > 1)
1190 change_c0_srsmap(0xf << n*4, srs << n*4); 1138 change_c0_srsmap(0xf << n*4, srs << n*4);
1191 } 1139 }
1192 1140
@@ -1253,14 +1201,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
1253 return set_vi_srs_handler(n, addr, 0); 1201 return set_vi_srs_handler(n, addr, 0);
1254} 1202}
1255 1203
1256#else
1257
1258static inline void mips_srs_init(void)
1259{
1260}
1261
1262#endif /* CONFIG_CPU_MIPSR2_SRS */
1263
1264/* 1204/*
1265 * This is used by native signal handling 1205 * This is used by native signal handling
1266 */ 1206 */
@@ -1503,8 +1443,6 @@ void __init trap_init(void)
1503 else 1443 else
1504 ebase = CAC_BASE; 1444 ebase = CAC_BASE;
1505 1445
1506 mips_srs_init();
1507
1508 per_cpu_trap_init(); 1446 per_cpu_trap_init();
1509 1447
1510 /* 1448 /*
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 436a64ff3989..38bd33fa2a23 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -1003,6 +1003,7 @@ static void cleanup_tc(struct tc *tc)
1003 write_tc_c0_tcstatus(tmp); 1003 write_tc_c0_tcstatus(tmp);
1004 1004
1005 write_tc_c0_tchalt(TCHALT_H); 1005 write_tc_c0_tchalt(TCHALT_H);
1006 mips_ihb();
1006 1007
1007 /* bind it to anything other than VPE1 */ 1008 /* bind it to anything other than VPE1 */
1008// write_tc_c0_tcbind(read_tc_c0_tcbind() & ~TCBIND_CURVPE); // | TCBIND_CURVPE 1009// write_tc_c0_tcbind(read_tc_c0_tcbind() & ~TCBIND_CURVPE); // | TCBIND_CURVPE
@@ -1235,9 +1236,12 @@ int vpe_free(vpe_handle vpe)
1235 settc(t->index); 1236 settc(t->index);
1236 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA); 1237 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA);
1237 1238
1238 /* mark the TC unallocated and halt'ed */ 1239 /* halt the TC */
1239 write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A);
1240 write_tc_c0_tchalt(TCHALT_H); 1240 write_tc_c0_tchalt(TCHALT_H);
1241 mips_ihb();
1242
1243 /* mark the TC unallocated */
1244 write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A);
1241 1245
1242 v->state = VPE_STATE_UNUSED; 1246 v->state = VPE_STATE_UNUSED;
1243 1247
@@ -1533,14 +1537,16 @@ static int __init vpe_module_init(void)
1533 t->pvpe = get_vpe(0); /* set the parent vpe */ 1537 t->pvpe = get_vpe(0); /* set the parent vpe */
1534 } 1538 }
1535 1539
1540 /* halt the TC */
1541 write_tc_c0_tchalt(TCHALT_H);
1542 mips_ihb();
1543
1536 tmp = read_tc_c0_tcstatus(); 1544 tmp = read_tc_c0_tcstatus();
1537 1545
1538 /* mark not activated and not dynamically allocatable */ 1546 /* mark not activated and not dynamically allocatable */
1539 tmp &= ~(TCSTATUS_A | TCSTATUS_DA); 1547 tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
1540 tmp |= TCSTATUS_IXMT; /* interrupt exempt */ 1548 tmp |= TCSTATUS_IXMT; /* interrupt exempt */
1541 write_tc_c0_tcstatus(tmp); 1549 write_tc_c0_tcstatus(tmp);
1542
1543 write_tc_c0_tchalt(TCHALT_H);
1544 } 1550 }
1545 } 1551 }
1546 1552
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index ba9692be3564..cfeab669782f 100644
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -19,17 +19,14 @@
19 * Lasat boards. 19 * Lasat boards.
20 */ 20 */
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/irq.h>
23#include <linux/sched.h>
24#include <linux/slab.h>
25#include <linux/interrupt.h> 22#include <linux/interrupt.h>
26#include <linux/kernel_stat.h> 23#include <linux/irq.h>
27 24
28#include <asm/bootinfo.h> 25#include <asm/bootinfo.h>
29#include <asm/irq_cpu.h> 26#include <asm/irq_cpu.h>
30#include <asm/lasat/lasatint.h> 27#include <asm/lasat/lasatint.h>
31#include <asm/time.h> 28
32#include <asm/gdb-stub.h> 29#include <irq.h>
33 30
34static volatile int *lasat_int_status; 31static volatile int *lasat_int_status;
35static volatile int *lasat_int_mask; 32static volatile int *lasat_int_mask;
@@ -97,12 +94,18 @@ asmlinkage void plat_irq_dispatch(void)
97 94
98 /* if int_status == 0, then the interrupt has already been cleared */ 95 /* if int_status == 0, then the interrupt has already been cleared */
99 if (int_status) { 96 if (int_status) {
100 irq = LASATINT_BASE + ls1bit32(int_status); 97 irq = LASAT_IRQ_BASE + ls1bit32(int_status);
101 98
102 do_IRQ(irq); 99 do_IRQ(irq);
103 } 100 }
104} 101}
105 102
103static struct irqaction cascade = {
104 .handler = no_action,
105 .mask = CPU_MASK_NONE,
106 .name = "cascade",
107};
108
106void __init arch_init_irq(void) 109void __init arch_init_irq(void)
107{ 110{
108 int i; 111 int i;
@@ -127,6 +130,9 @@ void __init arch_init_irq(void)
127 } 130 }
128 131
129 mips_cpu_irq_init(); 132 mips_cpu_irq_init();
130 for (i = LASATINT_BASE; i <= LASATINT_END; i++) 133
134 for (i = LASAT_IRQ_BASE; i <= LASAT_IRQ_END; i++)
131 set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq); 135 set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
136
137 setup_irq(LASAT_CASCADE_IRQ, &cascade);
132} 138}
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 6806d58211b2..9355f1c9325f 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -7,6 +7,7 @@
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) 7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */ 9 */
10#include <linux/hardirq.h>
10#include <linux/init.h> 11#include <linux/init.h>
11#include <linux/highmem.h> 12#include <linux/highmem.h>
12#include <linux/kernel.h> 13#include <linux/kernel.h>
@@ -507,7 +508,11 @@ static inline void local_r4k_flush_data_cache_page(void * addr)
507 508
508static void r4k_flush_data_cache_page(unsigned long addr) 509static void r4k_flush_data_cache_page(unsigned long addr)
509{ 510{
510 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1); 511 if (in_atomic())
512 local_r4k_flush_data_cache_page((void *)addr);
513 else
514 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr,
515 1, 1);
511} 516}
512 517
513struct flush_icache_range_args { 518struct flush_icache_range_args {
diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index e7f539e3284b..1bd1f18ac23c 100644
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -154,7 +154,7 @@ static void check_bus_watcher(void)
154 if (status & ~(1UL << 31)) { 154 if (status & ~(1UL << 31)) {
155 l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); 155 l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS));
156#ifdef DUMP_L2_ECC_TAG_ON_ERROR 156#ifdef DUMP_L2_ECC_TAG_ON_ERROR
157 l2_tag = in64(IO_SPACE_BASE | A_L2_ECC_TAG); 157 l2_tag = in64(IOADDR(A_L2_ECC_TAG));
158#endif 158#endif
159 memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); 159 memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));
160 printk("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); 160 printk("Bus watcher error counters: %08x %08x\n", l2_err, memio_err);
@@ -183,9 +183,9 @@ asmlinkage void sb1_cache_error(void)
183#ifdef CONFIG_SIBYTE_BW_TRACE 183#ifdef CONFIG_SIBYTE_BW_TRACE
184 /* Freeze the trace buffer now */ 184 /* Freeze the trace buffer now */
185#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 185#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
186 csr_out32(M_BCM1480_SCD_TRACE_CFG_FREEZE, IO_SPACE_BASE | A_SCD_TRACE_CFG); 186 csr_out32(M_BCM1480_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));
187#else 187#else
188 csr_out32(M_SCD_TRACE_CFG_FREEZE, IO_SPACE_BASE | A_SCD_TRACE_CFG); 188 csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));
189#endif 189#endif
190 printk("Trace buffer frozen\n"); 190 printk("Trace buffer frozen\n");
191#endif 191#endif
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 110ee7656b41..ec3b9e9f30f4 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -426,7 +426,7 @@ void __init mem_init(void)
426 426
427#ifdef CONFIG_HIGHMEM 427#ifdef CONFIG_HIGHMEM
428 for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) { 428 for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
429 struct page *page = mem_map + tmp; 429 struct page *page = pfn_to_page(tmp);
430 430
431 if (!page_is_ram(tmp)) { 431 if (!page_is_ram(tmp)) {
432 SetPageReserved(page); 432 SetPageReserved(page);
diff --git a/arch/mips/pci/fixup-sni.c b/arch/mips/pci/fixup-sni.c
index a45bedd17233..5c8a79bb2661 100644
--- a/arch/mips/pci/fixup-sni.c
+++ b/arch/mips/pci/fixup-sni.c
@@ -113,6 +113,16 @@ static char irq_tab_pcit[13][5] __initdata = {
113 { 0, INTA, INTB, INTC, INTD }, /* Slot 5 */ 113 { 0, INTA, INTB, INTC, INTD }, /* Slot 5 */
114}; 114};
115 115
116static char irq_tab_pcit_cplus[13][5] __initdata = {
117 /* INTA INTB INTC INTD */
118 { 0, 0, 0, 0, 0 }, /* HOST bridge */
119 { 0, INTB, INTC, INTD, INTA }, /* PCI Slot 9 */
120 { 0, 0, 0, 0, 0 }, /* PCI-EISA */
121 { 0, 0, 0, 0, 0 }, /* Unused */
122 { 0, INTA, INTB, INTC, INTD }, /* PCI-PCI bridge */
123 { 0, INTB, INTC, INTD, INTA }, /* fixup */
124};
125
116static inline int is_rm300_revd(void) 126static inline int is_rm300_revd(void)
117{ 127{
118 unsigned char csmsr = *(volatile unsigned char *)PCIMT_CSMSR; 128 unsigned char csmsr = *(volatile unsigned char *)PCIMT_CSMSR;
@@ -123,8 +133,19 @@ static inline int is_rm300_revd(void)
123int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 133int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
124{ 134{
125 switch (sni_brd_type) { 135 switch (sni_brd_type) {
126 case SNI_BRD_PCI_TOWER:
127 case SNI_BRD_PCI_TOWER_CPLUS: 136 case SNI_BRD_PCI_TOWER_CPLUS:
137 if (slot == 4) {
138 /*
139 * SNI messed up interrupt wiring for onboard
140 * PCI bus 1; we need to fix this up here
141 */
142 while (dev && dev->bus->number != 1)
143 dev = dev->bus->self;
144 if (dev && dev->devfn >= PCI_DEVFN(4, 0))
145 slot = 5;
146 }
147 return irq_tab_pcit_cplus[slot][pin];
148 case SNI_BRD_PCI_TOWER:
128 return irq_tab_pcit[slot][pin]; 149 return irq_tab_pcit[slot][pin];
129 150
130 case SNI_BRD_PCI_MTOWER: 151 case SNI_BRD_PCI_MTOWER:
diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c
index 174f314933b5..e70ae3236e0b 100644
--- a/arch/mips/pci/pci-lasat.c
+++ b/arch/mips/pci/pci-lasat.c
@@ -5,12 +5,14 @@
5 * 5 *
6 * Copyright (C) 2000, 2001, 04 Keith M Wesolowski 6 * Copyright (C) 2000, 2001, 04 Keith M Wesolowski
7 */ 7 */
8#include <linux/kernel.h>
9#include <linux/init.h> 8#include <linux/init.h>
9#include <linux/kernel.h>
10#include <linux/pci.h> 10#include <linux/pci.h>
11#include <linux/types.h> 11#include <linux/types.h>
12
12#include <asm/bootinfo.h> 13#include <asm/bootinfo.h>
13#include <asm/lasat/lasatint.h> 14
15#include <irq.h>
14 16
15extern struct pci_ops nile4_pci_ops; 17extern struct pci_ops nile4_pci_ops;
16extern struct pci_ops gt64xxx_pci0_ops; 18extern struct pci_ops gt64xxx_pci0_ops;
@@ -55,15 +57,15 @@ static int __init lasat_pci_setup(void)
55 57
56arch_initcall(lasat_pci_setup); 58arch_initcall(lasat_pci_setup);
57 59
58#define LASATINT_ETH1 (LASATINT_BASE + 0) 60#define LASAT_IRQ_ETH1 (LASAT_IRQ_BASE + 0)
59#define LASATINT_ETH0 (LASATINT_BASE + 1) 61#define LASAT_IRQ_ETH0 (LASAT_IRQ_BASE + 1)
60#define LASATINT_HDC (LASATINT_BASE + 2) 62#define LASAT_IRQ_HDC (LASAT_IRQ_BASE + 2)
61#define LASATINT_COMP (LASATINT_BASE + 3) 63#define LASAT_IRQ_COMP (LASAT_IRQ_BASE + 3)
62#define LASATINT_HDLC (LASATINT_BASE + 4) 64#define LASAT_IRQ_HDLC (LASAT_IRQ_BASE + 4)
63#define LASATINT_PCIA (LASATINT_BASE + 5) 65#define LASAT_IRQ_PCIA (LASAT_IRQ_BASE + 5)
64#define LASATINT_PCIB (LASATINT_BASE + 6) 66#define LASAT_IRQ_PCIB (LASAT_IRQ_BASE + 6)
65#define LASATINT_PCIC (LASATINT_BASE + 7) 67#define LASAT_IRQ_PCIC (LASAT_IRQ_BASE + 7)
66#define LASATINT_PCID (LASATINT_BASE + 8) 68#define LASAT_IRQ_PCID (LASAT_IRQ_BASE + 8)
67 69
68int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 70int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
69{ 71{
@@ -71,13 +73,13 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
71 case 1: 73 case 1:
72 case 2: 74 case 2:
73 case 3: 75 case 3:
74 return LASATINT_PCIA + (((slot-1) + (pin-1)) % 4); 76 return LASAT_IRQ_PCIA + (((slot-1) + (pin-1)) % 4);
75 case 4: 77 case 4:
76 return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */ 78 return LASAT_IRQ_ETH1; /* Ethernet 1 (LAN 2) */
77 case 5: 79 case 5:
78 return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */ 80 return LASAT_IRQ_ETH0; /* Ethernet 0 (LAN 1) */
79 case 6: 81 case 6:
80 return LASATINT_HDC; /* IDE controller */ 82 return LASAT_IRQ_HDC; /* IDE controller */
81 default: 83 default:
82 return 0xff; /* Illegal */ 84 return 0xff; /* Illegal */
83 } 85 }
diff --git a/arch/mips/pci/pci-vr41xx.c b/arch/mips/pci/pci-vr41xx.c
index 240df9e33813..33c4f683d067 100644
--- a/arch/mips/pci/pci-vr41xx.c
+++ b/arch/mips/pci/pci-vr41xx.c
@@ -154,6 +154,7 @@ static int __init vr41xx_pciu_init(void)
154 pciu_write(PCICLKSELREG, QUARTER_VTCLOCK); 154 pciu_write(PCICLKSELREG, QUARTER_VTCLOCK);
155 else { 155 else {
156 printk(KERN_ERR "PCI Clock is over 33MHz.\n"); 156 printk(KERN_ERR "PCI Clock is over 33MHz.\n");
157 iounmap(pciu_base);
157 return -EINVAL; 158 return -EINVAL;
158 } 159 }
159 160
diff --git a/arch/mips/qemu/Makefile b/arch/mips/qemu/Makefile
index cec24c117f6e..2ba4ef34b4a7 100644
--- a/arch/mips/qemu/Makefile
+++ b/arch/mips/qemu/Makefile
@@ -4,6 +4,7 @@
4 4
5obj-y = q-firmware.o q-irq.o q-mem.o q-setup.o q-reset.o 5obj-y = q-firmware.o q-irq.o q-mem.o q-setup.o q-reset.o
6 6
7obj-$(CONFIG_SMP) += q-smp.o 7obj-$(CONFIG_EARLY_PRINTK) += q-console.o
8obj-$(CONFIG_SMP) += q-smp.o
8 9
9EXTRA_CFLAGS += -Werror 10EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/qemu/q-console.c b/arch/mips/qemu/q-console.c
new file mode 100644
index 000000000000..81101ae5017a
--- /dev/null
+++ b/arch/mips/qemu/q-console.c
@@ -0,0 +1,26 @@
1#include <linux/console.h>
2#include <linux/init.h>
3#include <linux/serial_reg.h>
4#include <asm/io.h>
5
6#define PORT(offset) (0x3f8 + (offset))
7
8static inline unsigned int serial_in(int offset)
9{
10 return inb(PORT(offset));
11}
12
13static inline void serial_out(int offset, int value)
14{
15 outb(value, PORT(offset));
16}
17
18int prom_putchar(char c)
19{
20 while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0)
21 ;
22
23 serial_out(UART_TX, c);
24
25 return 1;
26}
diff --git a/arch/mips/qemu/q-firmware.c b/arch/mips/qemu/q-firmware.c
index c2239b417587..3ed43f416cd1 100644
--- a/arch/mips/qemu/q-firmware.c
+++ b/arch/mips/qemu/q-firmware.c
@@ -2,6 +2,9 @@
2#include <linux/string.h> 2#include <linux/string.h>
3#include <asm/addrspace.h> 3#include <asm/addrspace.h>
4#include <asm/bootinfo.h> 4#include <asm/bootinfo.h>
5#include <asm/io.h>
6
7#define QEMU_PORT_BASE 0xb4000000
5 8
6void __init prom_init(void) 9void __init prom_init(void)
7{ 10{
@@ -15,4 +18,7 @@ void __init prom_init(void)
15 } else { 18 } else {
16 add_memory_region(0x0<<20, 0x10<<20, BOOT_MEM_RAM); 19 add_memory_region(0x0<<20, 0x10<<20, BOOT_MEM_RAM);
17 } 20 }
21
22
23 set_io_port_base(QEMU_PORT_BASE);
18} 24}
diff --git a/arch/mips/qemu/q-setup.c b/arch/mips/qemu/q-setup.c
index 23d34c1917c0..969cedc8d8b9 100644
--- a/arch/mips/qemu/q-setup.c
+++ b/arch/mips/qemu/q-setup.c
@@ -6,8 +6,6 @@
6 6
7extern void qemu_reboot_setup(void); 7extern void qemu_reboot_setup(void);
8 8
9#define QEMU_PORT_BASE 0xb4000000
10
11const char *get_system_type(void) 9const char *get_system_type(void)
12{ 10{
13 return "Qemu"; 11 return "Qemu";
@@ -20,6 +18,5 @@ void __init plat_time_init(void)
20 18
21void __init plat_mem_setup(void) 19void __init plat_mem_setup(void)
22{ 20{
23 set_io_port_base(QEMU_PORT_BASE);
24 qemu_reboot_setup(); 21 qemu_reboot_setup();
25} 22}
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index e28d626255a3..db372a0f106d 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -370,11 +370,11 @@ void __init arch_init_irq(void)
370#endif 370#endif
371 /* Setup uart 1 settings, mapper */ 371 /* Setup uart 1 settings, mapper */
372 /* QQQ FIXME */ 372 /* QQQ FIXME */
373 __raw_writeq(M_DUART_IMR_BRK, IO_SPACE_BASE + A_DUART_IMRREG(kgdb_port)); 373 __raw_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port)));
374 374
375 __raw_writeq(IMR_IP6_VAL, 375 __raw_writeq(IMR_IP6_VAL,
376 IO_SPACE_BASE + A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + 376 IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
377 (kgdb_irq<<3)); 377 (kgdb_irq << 3)));
378 bcm1480_unmask_irq(0, kgdb_irq); 378 bcm1480_unmask_irq(0, kgdb_irq);
379 379
380#ifdef CONFIG_GDB_CONSOLE 380#ifdef CONFIG_GDB_CONSOLE
@@ -412,18 +412,6 @@ static void bcm1480_kgdb_interrupt(void)
412 412
413extern void bcm1480_mailbox_interrupt(void); 413extern void bcm1480_mailbox_interrupt(void);
414 414
415static inline void dispatch_ip4(void)
416{
417 int cpu = smp_processor_id();
418 int irq = K_BCM1480_INT_TIMER_0 + cpu;
419
420 /* Reset the timer */
421 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
422 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
423
424 do_IRQ(irq);
425}
426
427static inline void dispatch_ip2(void) 415static inline void dispatch_ip2(void)
428{ 416{
429 unsigned long long mask_h, mask_l; 417 unsigned long long mask_h, mask_l;
@@ -451,6 +439,7 @@ static inline void dispatch_ip2(void)
451 439
452asmlinkage void plat_irq_dispatch(void) 440asmlinkage void plat_irq_dispatch(void)
453{ 441{
442 unsigned int cpu = smp_processor_id();
454 unsigned int pending; 443 unsigned int pending;
455 444
456#ifdef CONFIG_SIBYTE_BCM1480_PROF 445#ifdef CONFIG_SIBYTE_BCM1480_PROF
@@ -467,7 +456,7 @@ asmlinkage void plat_irq_dispatch(void)
467#endif 456#endif
468 457
469 if (pending & CAUSEF_IP4) 458 if (pending & CAUSEF_IP4)
470 dispatch_ip4(); 459 do_IRQ(K_BCM1480_INT_TIMER_0 + cpu);
471#ifdef CONFIG_SMP 460#ifdef CONFIG_SMP
472 else if (pending & CAUSEF_IP3) 461 else if (pending & CAUSEF_IP3)
473 bcm1480_mailbox_interrupt(); 462 bcm1480_mailbox_interrupt();
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index 4df070f2ff5d..834650f371e0 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -244,7 +244,7 @@ static void pcimt_hwint1(void)
244 if (pend & IT_EISA) { 244 if (pend & IT_EISA) {
245 int irq; 245 int irq;
246 /* 246 /*
247 * Note: ASIC PCI's builtin interrupt achknowledge feature is 247 * Note: ASIC PCI's builtin interrupt acknowledge feature is
248 * broken. Using it may result in loss of some or all i8259 248 * broken. Using it may result in loss of some or all i8259
249 * interrupts, so don't use PCIMT_INT_ACKNOWLEDGE ... 249 * interrupts, so don't use PCIMT_INT_ACKNOWLEDGE ...
250 */ 250 */
diff --git a/drivers/i2c/busses/i2c-pasemi.c b/drivers/i2c/busses/i2c-pasemi.c
index 58e32714afb5..ca18e0be4901 100644
--- a/drivers/i2c/busses/i2c-pasemi.c
+++ b/drivers/i2c/busses/i2c-pasemi.c
@@ -51,6 +51,7 @@ struct pasemi_smbus {
51#define MRXFIFO_DATA_M 0x000000ff 51#define MRXFIFO_DATA_M 0x000000ff
52 52
53#define SMSTA_XEN 0x08000000 53#define SMSTA_XEN 0x08000000
54#define SMSTA_MTN 0x00200000
54 55
55#define CTL_MRR 0x00000400 56#define CTL_MRR 0x00000400
56#define CTL_MTR 0x00000200 57#define CTL_MTR 0x00000200
@@ -98,6 +99,10 @@ static unsigned int pasemi_smb_waitready(struct pasemi_smbus *smbus)
98 status = reg_read(smbus, REG_SMSTA); 99 status = reg_read(smbus, REG_SMSTA);
99 } 100 }
100 101
102 /* Got NACK? */
103 if (status & SMSTA_MTN)
104 return -ENXIO;
105
101 if (timeout < 0) { 106 if (timeout < 0) {
102 dev_warn(&smbus->dev->dev, "Timeout, status 0x%08x\n", status); 107 dev_warn(&smbus->dev->dev, "Timeout, status 0x%08x\n", status);
103 reg_write(smbus, REG_SMSTA, status); 108 reg_write(smbus, REG_SMSTA, status);
@@ -364,7 +369,7 @@ static int __devinit pasemi_smb_probe(struct pci_dev *dev,
364 smbus->adapter.algo = &smbus_algorithm; 369 smbus->adapter.algo = &smbus_algorithm;
365 smbus->adapter.algo_data = smbus; 370 smbus->adapter.algo_data = smbus;
366 371
367 /* set up the driverfs linkage to our parent device */ 372 /* set up the sysfs linkage to our parent device */
368 smbus->adapter.dev.parent = &dev->dev; 373 smbus->adapter.dev.parent = &dev->dev;
369 374
370 reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR | 375 reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
diff --git a/drivers/i2c/chips/eeprom.c b/drivers/i2c/chips/eeprom.c
index d3da1fb05b9b..1a7eeebac506 100644
--- a/drivers/i2c/chips/eeprom.c
+++ b/drivers/i2c/chips/eeprom.c
@@ -128,13 +128,20 @@ static ssize_t eeprom_read(struct kobject *kobj, struct bin_attribute *bin_attr,
128 for (slice = off >> 5; slice <= (off + count - 1) >> 5; slice++) 128 for (slice = off >> 5; slice <= (off + count - 1) >> 5; slice++)
129 eeprom_update_client(client, slice); 129 eeprom_update_client(client, slice);
130 130
131 /* Hide Vaio security settings to regular users (16 first bytes) */ 131 /* Hide Vaio private settings to regular users:
132 if (data->nature == VAIO && off < 16 && !capable(CAP_SYS_ADMIN)) { 132 - BIOS passwords: bytes 0x00 to 0x0f
133 size_t in_row1 = 16 - off; 133 - UUID: bytes 0x10 to 0x1f
134 in_row1 = min(in_row1, count); 134 - Serial number: 0xc0 to 0xdf */
135 memset(buf, 0, in_row1); 135 if (data->nature == VAIO && !capable(CAP_SYS_ADMIN)) {
136 if (count - in_row1 > 0) 136 int i;
137 memcpy(buf + in_row1, &data->data[16], count - in_row1); 137
138 for (i = 0; i < count; i++) {
139 if ((off + i <= 0x1f) ||
140 (off + i >= 0xc0 && off + i <= 0xdf))
141 buf[i] = 0;
142 else
143 buf[i] = data->data[off + i];
144 }
138 } else { 145 } else {
139 memcpy(buf, &data->data[off], count); 146 memcpy(buf, &data->data[off], count);
140 } 147 }
@@ -197,14 +204,18 @@ static int eeprom_detect(struct i2c_adapter *adapter, int address, int kind)
197 goto exit_kfree; 204 goto exit_kfree;
198 205
199 /* Detect the Vaio nature of EEPROMs. 206 /* Detect the Vaio nature of EEPROMs.
200 We use the "PCG-" prefix as the signature. */ 207 We use the "PCG-" or "VGN-" prefix as the signature. */
201 if (address == 0x57) { 208 if (address == 0x57) {
202 if (i2c_smbus_read_byte_data(new_client, 0x80) == 'P' 209 char name[4];
203 && i2c_smbus_read_byte(new_client) == 'C' 210
204 && i2c_smbus_read_byte(new_client) == 'G' 211 name[0] = i2c_smbus_read_byte_data(new_client, 0x80);
205 && i2c_smbus_read_byte(new_client) == '-') { 212 name[1] = i2c_smbus_read_byte(new_client);
213 name[2] = i2c_smbus_read_byte(new_client);
214 name[3] = i2c_smbus_read_byte(new_client);
215
216 if (!memcmp(name, "PCG-", 4) || !memcmp(name, "VGN-", 4)) {
206 dev_info(&new_client->dev, "Vaio EEPROM detected, " 217 dev_info(&new_client->dev, "Vaio EEPROM detected, "
207 "enabling password protection\n"); 218 "enabling privacy protection\n");
208 data->nature = VAIO; 219 data->nature = VAIO;
209 } 220 }
210 } 221 }
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index 1a4e8dc03b36..b5e13e405e72 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -673,7 +673,7 @@ static int __i2c_check_addr(struct i2c_adapter *adapter, unsigned int addr)
673 return 0; 673 return 0;
674} 674}
675 675
676int i2c_check_addr(struct i2c_adapter *adapter, int addr) 676static int i2c_check_addr(struct i2c_adapter *adapter, int addr)
677{ 677{
678 int rval; 678 int rval;
679 679
@@ -683,7 +683,6 @@ int i2c_check_addr(struct i2c_adapter *adapter, int addr)
683 683
684 return rval; 684 return rval;
685} 685}
686EXPORT_SYMBOL(i2c_check_addr);
687 686
688int i2c_attach_client(struct i2c_client *client) 687int i2c_attach_client(struct i2c_client *client)
689{ 688{
diff --git a/drivers/i2c/i2c-dev.c b/drivers/i2c/i2c-dev.c
index 5a15e50748de..c21ae20ae362 100644
--- a/drivers/i2c/i2c-dev.c
+++ b/drivers/i2c/i2c-dev.c
@@ -38,6 +38,15 @@
38 38
39static struct i2c_driver i2cdev_driver; 39static struct i2c_driver i2cdev_driver;
40 40
41/*
42 * An i2c_dev represents an i2c_adapter ... an I2C or SMBus master, not a
43 * slave (i2c_client) with which messages will be exchanged. It's coupled
44 * with a character special file which is accessed by user mode drivers.
45 *
46 * The list of i2c_dev structures is parallel to the i2c_adapter lists
47 * maintained by the driver model, and is updated using notifications
48 * delivered to the i2cdev_driver.
49 */
41struct i2c_dev { 50struct i2c_dev {
42 struct list_head list; 51 struct list_head list;
43 struct i2c_adapter *adap; 52 struct i2c_adapter *adap;
@@ -103,6 +112,25 @@ static ssize_t show_adapter_name(struct device *dev,
103} 112}
104static DEVICE_ATTR(name, S_IRUGO, show_adapter_name, NULL); 113static DEVICE_ATTR(name, S_IRUGO, show_adapter_name, NULL);
105 114
115/* ------------------------------------------------------------------------- */
116
117/*
118 * After opening an instance of this character special file, a file
119 * descriptor starts out associated only with an i2c_adapter (and bus).
120 *
121 * Using the I2C_RDWR ioctl(), you can then *immediately* issue i2c_msg
122 * traffic to any devices on the bus used by that adapter. That's because
123 * the i2c_msg vectors embed all the addressing information they need, and
124 * are submitted directly to an i2c_adapter. However, SMBus-only adapters
125 * don't support that interface.
126 *
127 * To use read()/write() system calls on that file descriptor, or to use
128 * SMBus interfaces (and work with SMBus-only hosts!), you must first issue
129 * an I2C_SLAVE (or I2C_SLAVE_FORCE) ioctl. That configures an anonymous
130 * (never registered) i2c_client so it holds the addressing information
131 * needed by those system calls and by this SMBus interface.
132 */
133
106static ssize_t i2cdev_read (struct file *file, char __user *buf, size_t count, 134static ssize_t i2cdev_read (struct file *file, char __user *buf, size_t count,
107 loff_t *offset) 135 loff_t *offset)
108{ 136{
@@ -154,6 +182,29 @@ static ssize_t i2cdev_write (struct file *file, const char __user *buf, size_t c
154 return ret; 182 return ret;
155} 183}
156 184
185/* This address checking function differs from the one in i2c-core
186 in that it considers an address with a registered device, but no
187 bounded driver, as NOT busy. */
188static int i2cdev_check_addr(struct i2c_adapter *adapter, unsigned int addr)
189{
190 struct list_head *item;
191 struct i2c_client *client;
192 int res = 0;
193
194 mutex_lock(&adapter->clist_lock);
195 list_for_each(item, &adapter->clients) {
196 client = list_entry(item, struct i2c_client, list);
197 if (client->addr == addr) {
198 if (client->driver)
199 res = -EBUSY;
200 break;
201 }
202 }
203 mutex_unlock(&adapter->clist_lock);
204
205 return res;
206}
207
157static int i2cdev_ioctl(struct inode *inode, struct file *file, 208static int i2cdev_ioctl(struct inode *inode, struct file *file,
158 unsigned int cmd, unsigned long arg) 209 unsigned int cmd, unsigned long arg)
159{ 210{
@@ -172,11 +223,22 @@ static int i2cdev_ioctl(struct inode *inode, struct file *file,
172 switch ( cmd ) { 223 switch ( cmd ) {
173 case I2C_SLAVE: 224 case I2C_SLAVE:
174 case I2C_SLAVE_FORCE: 225 case I2C_SLAVE_FORCE:
226 /* NOTE: devices set up to work with "new style" drivers
227 * can't use I2C_SLAVE, even when the device node is not
228 * bound to a driver. Only I2C_SLAVE_FORCE will work.
229 *
230 * Setting the PEC flag here won't affect kernel drivers,
231 * which will be using the i2c_client node registered with
232 * the driver model core. Likewise, when that client has
233 * the PEC flag already set, the i2c-dev driver won't see
234 * (or use) this setting.
235 */
175 if ((arg > 0x3ff) || 236 if ((arg > 0x3ff) ||
176 (((client->flags & I2C_M_TEN) == 0) && arg > 0x7f)) 237 (((client->flags & I2C_M_TEN) == 0) && arg > 0x7f))
177 return -EINVAL; 238 return -EINVAL;
178 if ((cmd == I2C_SLAVE) && i2c_check_addr(client->adapter,arg)) 239 if (cmd == I2C_SLAVE && i2cdev_check_addr(client->adapter, arg))
179 return -EBUSY; 240 return -EBUSY;
241 /* REVISIT: address could become busy later */
180 client->addr = arg; 242 client->addr = arg;
181 return 0; 243 return 0;
182 case I2C_TENBIT: 244 case I2C_TENBIT:
@@ -386,6 +448,13 @@ static int i2cdev_open(struct inode *inode, struct file *file)
386 if (!adap) 448 if (!adap)
387 return -ENODEV; 449 return -ENODEV;
388 450
451 /* This creates an anonymous i2c_client, which may later be
452 * pointed to some address using I2C_SLAVE or I2C_SLAVE_FORCE.
453 *
454 * This client is ** NEVER REGISTERED ** with the driver model
455 * or I2C core code!! It just holds private copies of addressing
456 * information and maybe a PEC flag.
457 */
389 client = kzalloc(sizeof(*client), GFP_KERNEL); 458 client = kzalloc(sizeof(*client), GFP_KERNEL);
390 if (!client) { 459 if (!client) {
391 i2c_put_adapter(adap); 460 i2c_put_adapter(adap);
@@ -394,7 +463,6 @@ static int i2cdev_open(struct inode *inode, struct file *file)
394 snprintf(client->name, I2C_NAME_SIZE, "i2c-dev %d", adap->nr); 463 snprintf(client->name, I2C_NAME_SIZE, "i2c-dev %d", adap->nr);
395 client->driver = &i2cdev_driver; 464 client->driver = &i2cdev_driver;
396 465
397 /* registered with adapter, passed as client to user */
398 client->adapter = adap; 466 client->adapter = adap;
399 file->private_data = client; 467 file->private_data = client;
400 468
@@ -422,6 +490,14 @@ static const struct file_operations i2cdev_fops = {
422 .release = i2cdev_release, 490 .release = i2cdev_release,
423}; 491};
424 492
493/* ------------------------------------------------------------------------- */
494
495/*
496 * The legacy "i2cdev_driver" is used primarily to get notifications when
497 * I2C adapters are added or removed, so that each one gets an i2c_dev
498 * and is thus made available to userspace driver code.
499 */
500
425static struct class *i2c_dev_class; 501static struct class *i2c_dev_class;
426 502
427static int i2cdev_attach_adapter(struct i2c_adapter *adap) 503static int i2cdev_attach_adapter(struct i2c_adapter *adap)
@@ -486,6 +562,12 @@ static struct i2c_driver i2cdev_driver = {
486 .detach_client = i2cdev_detach_client, 562 .detach_client = i2cdev_detach_client,
487}; 563};
488 564
565/* ------------------------------------------------------------------------- */
566
567/*
568 * module load/unload record keeping
569 */
570
489static int __init i2c_dev_init(void) 571static int __init i2c_dev_init(void)
490{ 572{
491 int res; 573 int res;
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index b9961dc47606..6d62250fba07 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -2512,31 +2512,32 @@ static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2512 return err; 2512 return err;
2513} 2513}
2514 2514
2515/* Assign Ram Buffer allocation to queue */ 2515static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2516static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, u32 space)
2517{ 2516{
2518 u32 end; 2517 u32 end;
2519 2518
2520 /* convert from K bytes to qwords used for hw register */ 2519 start /= 8;
2521 start *= 1024/8; 2520 len /= 8;
2522 space *= 1024/8; 2521 end = start + len - 1;
2523 end = start + space - 1;
2524 2522
2525 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 2523 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2526 skge_write32(hw, RB_ADDR(q, RB_START), start); 2524 skge_write32(hw, RB_ADDR(q, RB_START), start);
2527 skge_write32(hw, RB_ADDR(q, RB_END), end);
2528 skge_write32(hw, RB_ADDR(q, RB_WP), start); 2525 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2529 skge_write32(hw, RB_ADDR(q, RB_RP), start); 2526 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2527 skge_write32(hw, RB_ADDR(q, RB_END), end);
2530 2528
2531 if (q == Q_R1 || q == Q_R2) { 2529 if (q == Q_R1 || q == Q_R2) {
2532 u32 tp = space - space/4;
2533
2534 /* Set thresholds on receive queue's */ 2530 /* Set thresholds on receive queue's */
2535 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); 2531 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2536 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); 2532 start + (2*len)/3);
2537 } else if (hw->chip_id != CHIP_ID_GENESIS) 2533 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2538 /* Genesis Tx Fifo is too small for normal store/forward */ 2534 start + (len/3));
2535 } else {
2536 /* Enable store & forward on Tx queue's because
2537 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2538 */
2539 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); 2539 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2540 }
2540 2541
2541 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); 2542 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2542} 2543}
@@ -2564,7 +2565,7 @@ static int skge_up(struct net_device *dev)
2564 struct skge_port *skge = netdev_priv(dev); 2565 struct skge_port *skge = netdev_priv(dev);
2565 struct skge_hw *hw = skge->hw; 2566 struct skge_hw *hw = skge->hw;
2566 int port = skge->port; 2567 int port = skge->port;
2567 u32 ramaddr, ramsize, rxspace; 2568 u32 chunk, ram_addr;
2568 size_t rx_size, tx_size; 2569 size_t rx_size, tx_size;
2569 int err; 2570 int err;
2570 2571
@@ -2619,15 +2620,14 @@ static int skge_up(struct net_device *dev)
2619 spin_unlock_bh(&hw->phy_lock); 2620 spin_unlock_bh(&hw->phy_lock);
2620 2621
2621 /* Configure RAMbuffers */ 2622 /* Configure RAMbuffers */
2622 ramsize = (hw->ram_size - hw->ram_offset) / hw->ports; 2623 chunk = hw->ram_size / ((hw->ports + 1)*2);
2623 ramaddr = hw->ram_offset + port * ramsize; 2624 ram_addr = hw->ram_offset + 2 * chunk * port;
2624 rxspace = 8 + (2*(ramsize - 16))/3;
2625
2626 skge_ramset(hw, rxqaddr[port], ramaddr, rxspace);
2627 skge_ramset(hw, txqaddr[port], ramaddr + rxspace, ramsize - rxspace);
2628 2625
2626 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2629 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean); 2627 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2628
2630 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean); 2629 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2630 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2631 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use); 2631 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2632 2632
2633 /* Start receiver BMU */ 2633 /* Start receiver BMU */
@@ -3591,12 +3591,15 @@ static int skge_reset(struct skge_hw *hw)
3591 if (hw->chip_id == CHIP_ID_GENESIS) { 3591 if (hw->chip_id == CHIP_ID_GENESIS) {
3592 if (t8 == 3) { 3592 if (t8 == 3) {
3593 /* special case: 4 x 64k x 36, offset = 0x80000 */ 3593 /* special case: 4 x 64k x 36, offset = 0x80000 */
3594 hw->ram_size = 1024; 3594 hw->ram_size = 0x100000;
3595 hw->ram_offset = 512; 3595 hw->ram_offset = 0x80000;
3596 } else 3596 } else
3597 hw->ram_size = t8 * 512; 3597 hw->ram_size = t8 * 512;
3598 } else /* Yukon */ 3598 }
3599 hw->ram_size = t8 ? t8 * 4 : 128; 3599 else if (t8 == 0)
3600 hw->ram_size = 0x20000;
3601 else
3602 hw->ram_size = t8 * 4096;
3600 3603
3601 hw->intr_mask = IS_HW_ERR; 3604 hw->intr_mask = IS_HW_ERR;
3602 3605
diff --git a/include/asm-avr32/sysreg.h b/include/asm-avr32/sysreg.h
index c02bc8304b13..dd21182b60e0 100644
--- a/include/asm-avr32/sysreg.h
+++ b/include/asm-avr32/sysreg.h
@@ -215,6 +215,8 @@
215#define SYSREG_IRP_SIZE 6 215#define SYSREG_IRP_SIZE 6
216 216
217/* Bitfields in PCCR */ 217/* Bitfields in PCCR */
218#define SYSREG_PCCR_E_OFFSET 0
219#define SYSREG_PCCR_E_SIZE 1
218#define SYSREG_PCCR_R_OFFSET 1 220#define SYSREG_PCCR_R_OFFSET 1
219#define SYSREG_PCCR_R_SIZE 1 221#define SYSREG_PCCR_R_SIZE 1
220#define SYSREG_PCCR_C_OFFSET 2 222#define SYSREG_PCCR_C_OFFSET 2
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index 94f1c8172360..ed5c02c6afbb 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -54,6 +54,7 @@ struct cpuinfo_mips {
54 struct cache_desc dcache; /* Primary D or combined I/D cache */ 54 struct cache_desc dcache; /* Primary D or combined I/D cache */
55 struct cache_desc scache; /* Secondary cache */ 55 struct cache_desc scache; /* Secondary cache */
56 struct cache_desc tcache; /* Tertiary/split secondary cache */ 56 struct cache_desc tcache; /* Tertiary/split secondary cache */
57 int srsets; /* Shadow register sets */
57#if defined(CONFIG_MIPS_MT_SMTC) 58#if defined(CONFIG_MIPS_MT_SMTC)
58 /* 59 /*
59 * In the MIPS MT "SMTC" model, each TC is considered 60 * In the MIPS MT "SMTC" model, each TC is considered
diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h
index 581dc45685a2..e0d2458b43d0 100644
--- a/include/asm-mips/lasat/lasatint.h
+++ b/include/asm-mips/lasat/lasatint.h
@@ -1,11 +1,6 @@
1#ifndef __ASM_LASAT_LASATINT_H 1#ifndef __ASM_LASAT_LASATINT_H
2#define __ASM_LASAT_LASATINT_H 2#define __ASM_LASAT_LASATINT_H
3 3
4#include <linux/irq.h>
5
6#define LASATINT_BASE MIPS_CPU_IRQ_BASE
7#define LASATINT_END (LASATINT_BASE + 16)
8
9/* lasat 100 */ 4/* lasat 100 */
10#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000)) 5#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000))
11#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000)) 6#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000))
diff --git a/include/asm-mips/mach-lasat/irq.h b/include/asm-mips/mach-lasat/irq.h
new file mode 100644
index 000000000000..da75f89f3723
--- /dev/null
+++ b/include/asm-mips/mach-lasat/irq.h
@@ -0,0 +1,13 @@
1#ifndef _ASM_MACH_LASAT_IRQ_H
2#define _ASM_MACH_LASAT_IRQ_H
3
4#define LASAT_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 0)
5
6#define LASAT_IRQ_BASE 8
7#define LASAT_IRQ_END 23
8
9#define NR_IRQS 24
10
11#include_next <irq.h>
12
13#endif /* _ASM_MACH_LASAT_IRQ_H */
diff --git a/include/asm-mips/timex.h b/include/asm-mips/timex.h
index 5816ad1569d6..6529704aa73a 100644
--- a/include/asm-mips/timex.h
+++ b/include/asm-mips/timex.h
@@ -35,7 +35,7 @@ typedef unsigned int cycles_t;
35 35
36static inline cycles_t get_cycles(void) 36static inline cycles_t get_cycles(void)
37{ 37{
38 return read_c0_count(); 38 return 0;
39} 39}
40 40
41#endif /* __KERNEL__ */ 41#endif /* __KERNEL__ */
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 8033e6b33271..a100c9f8eb7c 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -400,11 +400,6 @@ extern int i2c_release_client(struct i2c_client *);
400extern void i2c_clients_command(struct i2c_adapter *adap, 400extern void i2c_clients_command(struct i2c_adapter *adap,
401 unsigned int cmd, void *arg); 401 unsigned int cmd, void *arg);
402 402
403/* returns -EBUSY if address has been taken, 0 if not. Note that the only
404 other place at which this is called is within i2c_attach_client; so
405 you can cheat by simply not registering. Not recommended, of course! */
406extern int i2c_check_addr (struct i2c_adapter *adapter, int addr);
407
408/* Detect function. It iterates over all possible addresses itself. 403/* Detect function. It iterates over all possible addresses itself.
409 * It will only call found_proc if some client is connected at the 404 * It will only call found_proc if some client is connected at the
410 * specific address (unless a 'force' matched); 405 * specific address (unless a 'force' matched);
diff --git a/include/pcmcia/cs_types.h b/include/pcmcia/cs_types.h
index c1d1629fcd27..5f388035687d 100644
--- a/include/pcmcia/cs_types.h
+++ b/include/pcmcia/cs_types.h
@@ -21,7 +21,7 @@
21#include <sys/types.h> 21#include <sys/types.h>
22#endif 22#endif
23 23
24#if defined(__arm__) || defined(__mips__) 24#if defined(__arm__) || defined(__mips__) || defined(__avr32__)
25/* This (ioaddr_t) is exposed to userspace & hence cannot be changed. */ 25/* This (ioaddr_t) is exposed to userspace & hence cannot be changed. */
26typedef u_int ioaddr_t; 26typedef u_int ioaddr_t;
27#else 27#else
diff --git a/kernel/exit.c b/kernel/exit.c
index f1aec27f1df0..cd0f1d4137a7 100644
--- a/kernel/exit.c
+++ b/kernel/exit.c
@@ -1386,8 +1386,7 @@ static int wait_task_stopped(struct task_struct *p, int delayed_group_leader,
1386 int why = (p->ptrace & PT_PTRACED) ? CLD_TRAPPED : CLD_STOPPED; 1386 int why = (p->ptrace & PT_PTRACED) ? CLD_TRAPPED : CLD_STOPPED;
1387 1387
1388 exit_code = p->exit_code; 1388 exit_code = p->exit_code;
1389 if (unlikely(!exit_code) || 1389 if (unlikely(!exit_code) || unlikely(p->exit_state))
1390 unlikely(p->state & TASK_TRACED))
1391 goto bail_ref; 1390 goto bail_ref;
1392 return wait_noreap_copyout(p, pid, uid, 1391 return wait_noreap_copyout(p, pid, uid,
1393 why, (exit_code << 8) | 0x7f, 1392 why, (exit_code << 8) | 0x7f,
diff --git a/kernel/sched.c b/kernel/sched.c
index 4fb3532dd7e8..38933cafea8a 100644
--- a/kernel/sched.c
+++ b/kernel/sched.c
@@ -216,15 +216,15 @@ static inline struct task_group *task_group(struct task_struct *p)
216} 216}
217 217
218/* Change a task's cfs_rq and parent entity if it moves across CPUs/groups */ 218/* Change a task's cfs_rq and parent entity if it moves across CPUs/groups */
219static inline void set_task_cfs_rq(struct task_struct *p) 219static inline void set_task_cfs_rq(struct task_struct *p, unsigned int cpu)
220{ 220{
221 p->se.cfs_rq = task_group(p)->cfs_rq[task_cpu(p)]; 221 p->se.cfs_rq = task_group(p)->cfs_rq[cpu];
222 p->se.parent = task_group(p)->se[task_cpu(p)]; 222 p->se.parent = task_group(p)->se[cpu];
223} 223}
224 224
225#else 225#else
226 226
227static inline void set_task_cfs_rq(struct task_struct *p) { } 227static inline void set_task_cfs_rq(struct task_struct *p, unsigned int cpu) { }
228 228
229#endif /* CONFIG_FAIR_GROUP_SCHED */ 229#endif /* CONFIG_FAIR_GROUP_SCHED */
230 230
@@ -455,18 +455,18 @@ static void update_rq_clock(struct rq *rq)
455 */ 455 */
456enum { 456enum {
457 SCHED_FEAT_NEW_FAIR_SLEEPERS = 1, 457 SCHED_FEAT_NEW_FAIR_SLEEPERS = 1,
458 SCHED_FEAT_START_DEBIT = 2, 458 SCHED_FEAT_WAKEUP_PREEMPT = 2,
459 SCHED_FEAT_TREE_AVG = 4, 459 SCHED_FEAT_START_DEBIT = 4,
460 SCHED_FEAT_APPROX_AVG = 8, 460 SCHED_FEAT_TREE_AVG = 8,
461 SCHED_FEAT_WAKEUP_PREEMPT = 16, 461 SCHED_FEAT_APPROX_AVG = 16,
462}; 462};
463 463
464const_debug unsigned int sysctl_sched_features = 464const_debug unsigned int sysctl_sched_features =
465 SCHED_FEAT_NEW_FAIR_SLEEPERS * 1 | 465 SCHED_FEAT_NEW_FAIR_SLEEPERS * 1 |
466 SCHED_FEAT_WAKEUP_PREEMPT * 1 |
466 SCHED_FEAT_START_DEBIT * 1 | 467 SCHED_FEAT_START_DEBIT * 1 |
467 SCHED_FEAT_TREE_AVG * 0 | 468 SCHED_FEAT_TREE_AVG * 0 |
468 SCHED_FEAT_APPROX_AVG * 0 | 469 SCHED_FEAT_APPROX_AVG * 0;
469 SCHED_FEAT_WAKEUP_PREEMPT * 1;
470 470
471#define sched_feat(x) (sysctl_sched_features & SCHED_FEAT_##x) 471#define sched_feat(x) (sysctl_sched_features & SCHED_FEAT_##x)
472 472
@@ -1022,10 +1022,16 @@ unsigned long weighted_cpuload(const int cpu)
1022 1022
1023static inline void __set_task_cpu(struct task_struct *p, unsigned int cpu) 1023static inline void __set_task_cpu(struct task_struct *p, unsigned int cpu)
1024{ 1024{
1025 set_task_cfs_rq(p, cpu);
1025#ifdef CONFIG_SMP 1026#ifdef CONFIG_SMP
1027 /*
1028 * After ->cpu is set up to a new value, task_rq_lock(p, ...) can be
1029 * successfuly executed on another CPU. We must ensure that updates of
1030 * per-task data have been completed by this moment.
1031 */
1032 smp_wmb();
1026 task_thread_info(p)->cpu = cpu; 1033 task_thread_info(p)->cpu = cpu;
1027#endif 1034#endif
1028 set_task_cfs_rq(p);
1029} 1035}
1030 1036
1031#ifdef CONFIG_SMP 1037#ifdef CONFIG_SMP
@@ -3390,10 +3396,8 @@ void account_system_time(struct task_struct *p, int hardirq_offset,
3390 struct rq *rq = this_rq(); 3396 struct rq *rq = this_rq();
3391 cputime64_t tmp; 3397 cputime64_t tmp;
3392 3398
3393 if (p->flags & PF_VCPU) { 3399 if ((p->flags & PF_VCPU) && (irq_count() - hardirq_offset == 0))
3394 account_guest_time(p, cputime); 3400 return account_guest_time(p, cputime);
3395 return;
3396 }
3397 3401
3398 p->stime = cputime_add(p->stime, cputime); 3402 p->stime = cputime_add(p->stime, cputime);
3399 3403
@@ -5278,23 +5282,9 @@ static void migrate_live_tasks(int src_cpu)
5278} 5282}
5279 5283
5280/* 5284/*
5281 * activate_idle_task - move idle task to the _front_ of runqueue.
5282 */
5283static void activate_idle_task(struct task_struct *p, struct rq *rq)
5284{
5285 update_rq_clock(rq);
5286
5287 if (p->state == TASK_UNINTERRUPTIBLE)
5288 rq->nr_uninterruptible--;
5289
5290 enqueue_task(rq, p, 0);
5291 inc_nr_running(p, rq);
5292}
5293
5294/*
5295 * Schedules idle task to be the next runnable task on current CPU. 5285 * Schedules idle task to be the next runnable task on current CPU.
5296 * It does so by boosting its priority to highest possible and adding it to 5286 * It does so by boosting its priority to highest possible.
5297 * the _front_ of the runqueue. Used by CPU offline code. 5287 * Used by CPU offline code.
5298 */ 5288 */
5299void sched_idle_next(void) 5289void sched_idle_next(void)
5300{ 5290{
@@ -5314,8 +5304,8 @@ void sched_idle_next(void)
5314 5304
5315 __setscheduler(rq, p, SCHED_FIFO, MAX_RT_PRIO-1); 5305 __setscheduler(rq, p, SCHED_FIFO, MAX_RT_PRIO-1);
5316 5306
5317 /* Add idle task to the _front_ of its priority queue: */ 5307 update_rq_clock(rq);
5318 activate_idle_task(p, rq); 5308 activate_task(rq, p, 0);
5319 5309
5320 spin_unlock_irqrestore(&rq->lock, flags); 5310 spin_unlock_irqrestore(&rq->lock, flags);
5321} 5311}
@@ -7089,8 +7079,10 @@ void sched_move_task(struct task_struct *tsk)
7089 7079
7090 rq = task_rq_lock(tsk, &flags); 7080 rq = task_rq_lock(tsk, &flags);
7091 7081
7092 if (tsk->sched_class != &fair_sched_class) 7082 if (tsk->sched_class != &fair_sched_class) {
7083 set_task_cfs_rq(tsk, task_cpu(tsk));
7093 goto done; 7084 goto done;
7085 }
7094 7086
7095 update_rq_clock(rq); 7087 update_rq_clock(rq);
7096 7088
@@ -7103,7 +7095,7 @@ void sched_move_task(struct task_struct *tsk)
7103 tsk->sched_class->put_prev_task(rq, tsk); 7095 tsk->sched_class->put_prev_task(rq, tsk);
7104 } 7096 }
7105 7097
7106 set_task_cfs_rq(tsk); 7098 set_task_cfs_rq(tsk, task_cpu(tsk));
7107 7099
7108 if (on_rq) { 7100 if (on_rq) {
7109 if (unlikely(running)) 7101 if (unlikely(running))
diff --git a/kernel/sched_fair.c b/kernel/sched_fair.c
index d3c03070872d..ee00da284b12 100644
--- a/kernel/sched_fair.c
+++ b/kernel/sched_fair.c
@@ -43,7 +43,7 @@ unsigned int sysctl_sched_min_granularity = 1000000ULL;
43/* 43/*
44 * is kept at sysctl_sched_latency / sysctl_sched_min_granularity 44 * is kept at sysctl_sched_latency / sysctl_sched_min_granularity
45 */ 45 */
46unsigned int sched_nr_latency = 20; 46static unsigned int sched_nr_latency = 20;
47 47
48/* 48/*
49 * After fork, child runs first. (default) If set to 0 then 49 * After fork, child runs first. (default) If set to 0 then
diff --git a/mm/slob.c b/mm/slob.c
index 5bc2ceb692ec..08a9bd91a1aa 100644
--- a/mm/slob.c
+++ b/mm/slob.c
@@ -321,7 +321,8 @@ static void *slob_alloc(size_t size, gfp_t gfp, int align, int node)
321 /* Improve fragment distribution and reduce our average 321 /* Improve fragment distribution and reduce our average
322 * search time by starting our next search here. (see 322 * search time by starting our next search here. (see
323 * Knuth vol 1, sec 2.5, pg 449) */ 323 * Knuth vol 1, sec 2.5, pg 449) */
324 if (free_slob_pages.next != prev->next) 324 if (prev != free_slob_pages.prev &&
325 free_slob_pages.next != prev->next)
325 list_move_tail(&free_slob_pages, prev->next); 326 list_move_tail(&free_slob_pages, prev->next);
326 break; 327 break;
327 } 328 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-06 22:34:51 -0500