diff options
-rw-r--r-- | arch/blackfin/Kconfig | 5 | ||||
-rw-r--r-- | arch/blackfin/mach-bf533/boards/H8606.c | 4 | ||||
-rw-r--r-- | arch/blackfin/mach-bf533/boards/generic_board.c | 4 | ||||
-rw-r--r-- | arch/blackfin/mach-bf561/boards/generic_board.c | 4 | ||||
-rw-r--r-- | arch/blackfin/mach-bf561/boards/tepla.c | 4 | ||||
-rw-r--r-- | arch/blackfin/mach-common/ints-priority-dc.c | 21 | ||||
-rw-r--r-- | arch/blackfin/mach-common/ints-priority-sc.c | 28 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf527/irq.h | 4 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf533/irq.h | 4 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf537/irq.h | 4 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/irq.h | 4 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf561/irq.h | 4 |
12 files changed, 18 insertions, 72 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 7b03f9241d66..2e5ce848513e 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig | |||
@@ -65,11 +65,6 @@ config GENERIC_CALIBRATE_DELAY | |||
65 | bool | 65 | bool |
66 | default y | 66 | default y |
67 | 67 | ||
68 | config IRQCHIP_DEMUX_GPIO | ||
69 | bool | ||
70 | depends on (BF52x || BF53x || BF561 || BF54x) | ||
71 | default y | ||
72 | |||
73 | source "init/Kconfig" | 68 | source "init/Kconfig" |
74 | source "kernel/Kconfig.preempt" | 69 | source "kernel/Kconfig.preempt" |
75 | 70 | ||
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c index b79669a84aca..caf0a86665e3 100644 --- a/arch/blackfin/mach-bf533/boards/H8606.c +++ b/arch/blackfin/mach-bf533/boards/H8606.c | |||
@@ -94,10 +94,6 @@ static struct resource smc91x_resources[] = { | |||
94 | .end = IRQ_PROG_INTB, | 94 | .end = IRQ_PROG_INTB, |
95 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | 95 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, |
96 | }, { | 96 | }, { |
97 | /* | ||
98 | * denotes the flag pin and is used directly if | ||
99 | * CONFIG_IRQCHIP_DEMUX_GPIO is defined. | ||
100 | */ | ||
101 | .start = IRQ_PF7, | 97 | .start = IRQ_PF7, |
102 | .end = IRQ_PF7, | 98 | .end = IRQ_PF7, |
103 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | 99 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, |
diff --git a/arch/blackfin/mach-bf533/boards/generic_board.c b/arch/blackfin/mach-bf533/boards/generic_board.c index 310b7772c458..e359a0d6467f 100644 --- a/arch/blackfin/mach-bf533/boards/generic_board.c +++ b/arch/blackfin/mach-bf533/boards/generic_board.c | |||
@@ -58,10 +58,6 @@ static struct resource smc91x_resources[] = { | |||
58 | .end = IRQ_PROG_INTB, | 58 | .end = IRQ_PROG_INTB, |
59 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | 59 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, |
60 | }, { | 60 | }, { |
61 | /* | ||
62 | * denotes the flag pin and is used directly if | ||
63 | * CONFIG_IRQCHIP_DEMUX_GPIO is defined. | ||
64 | */ | ||
65 | .start = IRQ_PF7, | 61 | .start = IRQ_PF7, |
66 | .end = IRQ_PF7, | 62 | .end = IRQ_PF7, |
67 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | 63 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, |
diff --git a/arch/blackfin/mach-bf561/boards/generic_board.c b/arch/blackfin/mach-bf561/boards/generic_board.c index 46816be4b2ba..fc80c5d059f8 100644 --- a/arch/blackfin/mach-bf561/boards/generic_board.c +++ b/arch/blackfin/mach-bf561/boards/generic_board.c | |||
@@ -48,10 +48,6 @@ static struct resource smc91x_resources[] = { | |||
48 | .end = IRQ_PROG_INTB, | 48 | .end = IRQ_PROG_INTB, |
49 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | 49 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, |
50 | }, { | 50 | }, { |
51 | /* | ||
52 | * denotes the flag pin and is used directly if | ||
53 | * CONFIG_IRQCHIP_DEMUX_GPIO is defined. | ||
54 | */ | ||
55 | .start = IRQ_PF9, | 51 | .start = IRQ_PF9, |
56 | .end = IRQ_PF9, | 52 | .end = IRQ_PF9, |
57 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | 53 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, |
diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c index 4a17c6da2a59..ec6a2207c202 100644 --- a/arch/blackfin/mach-bf561/boards/tepla.c +++ b/arch/blackfin/mach-bf561/boards/tepla.c | |||
@@ -31,10 +31,6 @@ static struct resource smc91x_resources[] = { | |||
31 | .end = IRQ_PROG_INTB, | 31 | .end = IRQ_PROG_INTB, |
32 | .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL, | 32 | .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL, |
33 | }, { | 33 | }, { |
34 | /* | ||
35 | * denotes the flag pin and is used directly if | ||
36 | * CONFIG_IRQCHIP_DEMUX_GPIO is defined. | ||
37 | */ | ||
38 | .start = IRQ_PF7, | 34 | .start = IRQ_PF7, |
39 | .end = IRQ_PF7, | 35 | .end = IRQ_PF7, |
40 | .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL, | 36 | .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL, |
diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c index c2f05fabedc1..4882f0e801a9 100644 --- a/arch/blackfin/mach-common/ints-priority-dc.c +++ b/arch/blackfin/mach-common/ints-priority-dc.c | |||
@@ -181,7 +181,6 @@ static struct irq_chip bf561_internal_irqchip = { | |||
181 | .unmask = bf561_internal_unmask_irq, | 181 | .unmask = bf561_internal_unmask_irq, |
182 | }; | 182 | }; |
183 | 183 | ||
184 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO | ||
185 | static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; | 184 | static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; |
186 | static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; | 185 | static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; |
187 | 186 | ||
@@ -362,8 +361,6 @@ static void bf561_demux_gpio_irq(unsigned int inta_irq, | |||
362 | 361 | ||
363 | } | 362 | } |
364 | 363 | ||
365 | #endif /* CONFIG_IRQCHIP_DEMUX_GPIO */ | ||
366 | |||
367 | void __init init_exception_vectors(void) | 364 | void __init init_exception_vectors(void) |
368 | { | 365 | { |
369 | SSYNC(); | 366 | SSYNC(); |
@@ -413,26 +410,21 @@ int __init init_arch_irq(void) | |||
413 | set_irq_chip(irq, &bf561_core_irqchip); | 410 | set_irq_chip(irq, &bf561_core_irqchip); |
414 | else | 411 | else |
415 | set_irq_chip(irq, &bf561_internal_irqchip); | 412 | set_irq_chip(irq, &bf561_internal_irqchip); |
416 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO | 413 | |
417 | if ((irq != IRQ_PROG0_INTA) && | 414 | if ((irq != IRQ_PROG0_INTA) && |
418 | (irq != IRQ_PROG1_INTA) && (irq != IRQ_PROG2_INTA)) { | 415 | (irq != IRQ_PROG1_INTA) && |
419 | #endif | 416 | (irq != IRQ_PROG2_INTA)) |
420 | set_irq_handler(irq, handle_simple_irq); | 417 | set_irq_handler(irq, handle_simple_irq); |
421 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO | 418 | else |
422 | } else { | ||
423 | set_irq_chained_handler(irq, bf561_demux_gpio_irq); | 419 | set_irq_chained_handler(irq, bf561_demux_gpio_irq); |
424 | } | ||
425 | #endif | ||
426 | |||
427 | } | 420 | } |
428 | 421 | ||
429 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO | ||
430 | for (irq = IRQ_PF0; irq <= IRQ_PF47; irq++) { | 422 | for (irq = IRQ_PF0; irq <= IRQ_PF47; irq++) { |
431 | set_irq_chip(irq, &bf561_gpio_irqchip); | 423 | set_irq_chip(irq, &bf561_gpio_irqchip); |
432 | /* if configured as edge, then will be changed to do_edge_IRQ */ | 424 | /* if configured as edge, then will be changed to do_edge_IRQ */ |
433 | set_irq_handler(irq, handle_level_irq); | 425 | set_irq_handler(irq, handle_level_irq); |
434 | } | 426 | } |
435 | #endif | 427 | |
436 | bfin_write_IMASK(0); | 428 | bfin_write_IMASK(0); |
437 | CSYNC(); | 429 | CSYNC(); |
438 | ilat = bfin_read_ILAT(); | 430 | ilat = bfin_read_ILAT(); |
@@ -457,9 +449,8 @@ int __init init_arch_irq(void) | |||
457 | } | 449 | } |
458 | 450 | ||
459 | #ifdef CONFIG_DO_IRQ_L1 | 451 | #ifdef CONFIG_DO_IRQ_L1 |
460 | void do_irq(int vec, struct pt_regs *fp)__attribute__((l1_text)); | 452 | __attribute__((l1_text)) |
461 | #endif | 453 | #endif |
462 | |||
463 | void do_irq(int vec, struct pt_regs *fp) | 454 | void do_irq(int vec, struct pt_regs *fp) |
464 | { | 455 | { |
465 | if (vec == EVT_IVTMR_P) { | 456 | if (vec == EVT_IVTMR_P) { |
diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c index 2d2b63567b30..147f0731087a 100644 --- a/arch/blackfin/mach-common/ints-priority-sc.c +++ b/arch/blackfin/mach-common/ints-priority-sc.c | |||
@@ -308,7 +308,7 @@ static void bfin_demux_error_irq(unsigned int int_err_irq, | |||
308 | } | 308 | } |
309 | #endif /* BF537_GENERIC_ERROR_INT_DEMUX */ | 309 | #endif /* BF537_GENERIC_ERROR_INT_DEMUX */ |
310 | 310 | ||
311 | #if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && !defined(CONFIG_BF54x) | 311 | #if !defined(CONFIG_BF54x) |
312 | 312 | ||
313 | static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; | 313 | static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; |
314 | static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; | 314 | static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; |
@@ -464,7 +464,7 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq, | |||
464 | } | 464 | } |
465 | } | 465 | } |
466 | 466 | ||
467 | #else /* CONFIG_IRQCHIP_DEMUX_GPIO */ | 467 | #else /* CONFIG_BF54x */ |
468 | 468 | ||
469 | #define NR_PINT_SYS_IRQS 4 | 469 | #define NR_PINT_SYS_IRQS 4 |
470 | #define NR_PINT_BITS 32 | 470 | #define NR_PINT_BITS 32 |
@@ -726,7 +726,7 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq, | |||
726 | } | 726 | } |
727 | 727 | ||
728 | } | 728 | } |
729 | #endif /* CONFIG_IRQCHIP_DEMUX_GPIO */ | 729 | #endif |
730 | 730 | ||
731 | void __init init_exception_vectors(void) | 731 | void __init init_exception_vectors(void) |
732 | { | 732 | { |
@@ -766,10 +766,10 @@ int __init init_arch_irq(void) | |||
766 | bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); | 766 | bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); |
767 | bfin_write_SIC_IWR0(IWR_ENABLE_ALL); | 767 | bfin_write_SIC_IWR0(IWR_ENABLE_ALL); |
768 | bfin_write_SIC_IWR1(IWR_ENABLE_ALL); | 768 | bfin_write_SIC_IWR1(IWR_ENABLE_ALL); |
769 | #ifdef CONFIG_BF54x | 769 | # ifdef CONFIG_BF54x |
770 | bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); | 770 | bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); |
771 | bfin_write_SIC_IWR2(IWR_ENABLE_ALL); | 771 | bfin_write_SIC_IWR2(IWR_ENABLE_ALL); |
772 | #endif | 772 | # endif |
773 | #else | 773 | #else |
774 | bfin_write_SIC_IMASK(SIC_UNMASK_ALL); | 774 | bfin_write_SIC_IMASK(SIC_UNMASK_ALL); |
775 | bfin_write_SIC_IWR(IWR_ENABLE_ALL); | 775 | bfin_write_SIC_IWR(IWR_ENABLE_ALL); |
@@ -778,13 +778,13 @@ int __init init_arch_irq(void) | |||
778 | 778 | ||
779 | local_irq_disable(); | 779 | local_irq_disable(); |
780 | 780 | ||
781 | #if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && defined(CONFIG_BF54x) | 781 | #ifdef CONFIG_BF54x |
782 | #ifdef CONFIG_PINTx_REASSIGN | 782 | # ifdef CONFIG_PINTx_REASSIGN |
783 | pint[0]->assign = CONFIG_PINT0_ASSIGN; | 783 | pint[0]->assign = CONFIG_PINT0_ASSIGN; |
784 | pint[1]->assign = CONFIG_PINT1_ASSIGN; | 784 | pint[1]->assign = CONFIG_PINT1_ASSIGN; |
785 | pint[2]->assign = CONFIG_PINT2_ASSIGN; | 785 | pint[2]->assign = CONFIG_PINT2_ASSIGN; |
786 | pint[3]->assign = CONFIG_PINT3_ASSIGN; | 786 | pint[3]->assign = CONFIG_PINT3_ASSIGN; |
787 | #endif | 787 | # endif |
788 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ | 788 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
789 | init_pint_lut(); | 789 | init_pint_lut(); |
790 | #endif | 790 | #endif |
@@ -799,18 +799,17 @@ int __init init_arch_irq(void) | |||
799 | #endif | 799 | #endif |
800 | 800 | ||
801 | switch (irq) { | 801 | switch (irq) { |
802 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO | ||
803 | #if defined(CONFIG_BF53x) | 802 | #if defined(CONFIG_BF53x) |
804 | case IRQ_PROG_INTA: | 803 | case IRQ_PROG_INTA: |
805 | set_irq_chained_handler(irq, | 804 | set_irq_chained_handler(irq, |
806 | bfin_demux_gpio_irq); | 805 | bfin_demux_gpio_irq); |
807 | break; | 806 | break; |
808 | #if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) | 807 | # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) |
809 | case IRQ_MAC_RX: | 808 | case IRQ_MAC_RX: |
810 | set_irq_chained_handler(irq, | 809 | set_irq_chained_handler(irq, |
811 | bfin_demux_gpio_irq); | 810 | bfin_demux_gpio_irq); |
812 | break; | 811 | break; |
813 | #endif | 812 | # endif |
814 | #elif defined(CONFIG_BF54x) | 813 | #elif defined(CONFIG_BF54x) |
815 | case IRQ_PINT0: | 814 | case IRQ_PINT0: |
816 | set_irq_chained_handler(irq, | 815 | set_irq_chained_handler(irq, |
@@ -842,7 +841,6 @@ int __init init_arch_irq(void) | |||
842 | bfin_demux_gpio_irq); | 841 | bfin_demux_gpio_irq); |
843 | break; | 842 | break; |
844 | #endif | 843 | #endif |
845 | #endif | ||
846 | default: | 844 | default: |
847 | set_irq_handler(irq, handle_simple_irq); | 845 | set_irq_handler(irq, handle_simple_irq); |
848 | break; | 846 | break; |
@@ -861,7 +859,6 @@ int __init init_arch_irq(void) | |||
861 | } | 859 | } |
862 | #endif | 860 | #endif |
863 | 861 | ||
864 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO | ||
865 | #ifndef CONFIG_BF54x | 862 | #ifndef CONFIG_BF54x |
866 | for (irq = IRQ_PF0; irq < NR_IRQS; irq++) { | 863 | for (irq = IRQ_PF0; irq < NR_IRQS; irq++) { |
867 | #else | 864 | #else |
@@ -871,7 +868,7 @@ int __init init_arch_irq(void) | |||
871 | /* if configured as edge, then will be changed to do_edge_IRQ */ | 868 | /* if configured as edge, then will be changed to do_edge_IRQ */ |
872 | set_irq_handler(irq, handle_level_irq); | 869 | set_irq_handler(irq, handle_level_irq); |
873 | } | 870 | } |
874 | #endif | 871 | |
875 | bfin_write_IMASK(0); | 872 | bfin_write_IMASK(0); |
876 | CSYNC(); | 873 | CSYNC(); |
877 | ilat = bfin_read_ILAT(); | 874 | ilat = bfin_read_ILAT(); |
@@ -896,9 +893,8 @@ int __init init_arch_irq(void) | |||
896 | } | 893 | } |
897 | 894 | ||
898 | #ifdef CONFIG_DO_IRQ_L1 | 895 | #ifdef CONFIG_DO_IRQ_L1 |
899 | void do_irq(int vec, struct pt_regs *fp) __attribute__((l1_text)); | 896 | __attribute__((l1_text)) |
900 | #endif | 897 | #endif |
901 | |||
902 | void do_irq(int vec, struct pt_regs *fp) | 898 | void do_irq(int vec, struct pt_regs *fp) |
903 | { | 899 | { |
904 | if (vec == EVT_IVTMR_P) { | 900 | if (vec == EVT_IVTMR_P) { |
diff --git a/include/asm-blackfin/mach-bf527/irq.h b/include/asm-blackfin/mach-bf527/irq.h index 304f5bcfebe4..4e2b3f2020e5 100644 --- a/include/asm-blackfin/mach-bf527/irq.h +++ b/include/asm-blackfin/mach-bf527/irq.h | |||
@@ -176,11 +176,7 @@ | |||
176 | 176 | ||
177 | #define GPIO_IRQ_BASE IRQ_PF0 | 177 | #define GPIO_IRQ_BASE IRQ_PF0 |
178 | 178 | ||
179 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO | ||
180 | #define NR_IRQS (IRQ_PH15+1) | 179 | #define NR_IRQS (IRQ_PH15+1) |
181 | #else | ||
182 | #define NR_IRQS (SYS_IRQS+1) | ||
183 | #endif | ||
184 | 180 | ||
185 | #define IVG7 7 | 181 | #define IVG7 7 |
186 | #define IVG8 8 | 182 | #define IVG8 8 |
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h index 452fb825d891..832e6f6122da 100644 --- a/include/asm-blackfin/mach-bf533/irq.h +++ b/include/asm-blackfin/mach-bf533/irq.h | |||
@@ -130,11 +130,7 @@ Core Emulation ** | |||
130 | 130 | ||
131 | #define GPIO_IRQ_BASE IRQ_PF0 | 131 | #define GPIO_IRQ_BASE IRQ_PF0 |
132 | 132 | ||
133 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO | ||
134 | #define NR_IRQS (IRQ_PF15+1) | 133 | #define NR_IRQS (IRQ_PF15+1) |
135 | #else | ||
136 | #define NR_IRQS SYS_IRQS | ||
137 | #endif | ||
138 | 134 | ||
139 | #define IVG7 7 | 135 | #define IVG7 7 |
140 | #define IVG8 8 | 136 | #define IVG8 8 |
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h index 36c44bc1a917..be6f2ff77f31 100644 --- a/include/asm-blackfin/mach-bf537/irq.h +++ b/include/asm-blackfin/mach-bf537/irq.h | |||
@@ -162,11 +162,7 @@ Core Emulation ** | |||
162 | 162 | ||
163 | #define GPIO_IRQ_BASE IRQ_PF0 | 163 | #define GPIO_IRQ_BASE IRQ_PF0 |
164 | 164 | ||
165 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO | ||
166 | #define NR_IRQS (IRQ_PH15+1) | 165 | #define NR_IRQS (IRQ_PH15+1) |
167 | #else | ||
168 | #define NR_IRQS (IRQ_UART1_ERROR+1) | ||
169 | #endif | ||
170 | 166 | ||
171 | #define IVG7 7 | 167 | #define IVG7 7 |
172 | #define IVG8 8 | 168 | #define IVG8 8 |
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h index 3b08cf9bd6f3..9fb7bc5399a8 100644 --- a/include/asm-blackfin/mach-bf548/irq.h +++ b/include/asm-blackfin/mach-bf548/irq.h | |||
@@ -338,11 +338,7 @@ Events (highest priority) EMU 0 | |||
338 | 338 | ||
339 | #define GPIO_IRQ_BASE IRQ_PA0 | 339 | #define GPIO_IRQ_BASE IRQ_PA0 |
340 | 340 | ||
341 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO | ||
342 | #define NR_IRQS (IRQ_PJ15+1) | 341 | #define NR_IRQS (IRQ_PJ15+1) |
343 | #else | ||
344 | #define NR_IRQS (SYS_IRQS+1) | ||
345 | #endif | ||
346 | 342 | ||
347 | /* For compatibility reasons with existing code */ | 343 | /* For compatibility reasons with existing code */ |
348 | 344 | ||
diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h index 12789927db3d..83f0383957d2 100644 --- a/include/asm-blackfin/mach-bf561/irq.h +++ b/include/asm-blackfin/mach-bf561/irq.h | |||
@@ -291,11 +291,7 @@ | |||
291 | 291 | ||
292 | #define GPIO_IRQ_BASE IRQ_PF0 | 292 | #define GPIO_IRQ_BASE IRQ_PF0 |
293 | 293 | ||
294 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO | ||
295 | #define NR_IRQS (IRQ_PF47 + 1) | 294 | #define NR_IRQS (IRQ_PF47 + 1) |
296 | #else | ||
297 | #define NR_IRQS SYS_IRQS | ||
298 | #endif | ||
299 | 295 | ||
300 | #define IVG7 7 | 296 | #define IVG7 7 |
301 | #define IVG8 8 | 297 | #define IVG8 8 |