diff options
-rw-r--r-- | arch/blackfin/include/asm/ipipe.h | 100 | ||||
-rw-r--r-- | arch/blackfin/include/asm/ipipe_base.h | 12 | ||||
-rw-r--r-- | arch/blackfin/include/asm/irq.h | 36 | ||||
-rw-r--r-- | arch/blackfin/include/asm/thread_info.h | 2 | ||||
-rw-r--r-- | arch/blackfin/kernel/ipipe.c | 176 | ||||
-rw-r--r-- | arch/blackfin/kernel/irqchip.c | 14 | ||||
-rw-r--r-- | arch/blackfin/kernel/time.c | 5 | ||||
-rw-r--r-- | arch/blackfin/mach-common/entry.S | 61 | ||||
-rw-r--r-- | arch/blackfin/mach-common/interrupt.S | 12 | ||||
-rw-r--r-- | arch/blackfin/mach-common/ints-priority.c | 126 |
10 files changed, 241 insertions, 303 deletions
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h index 76f53d8b9a0d..343b56361ec9 100644 --- a/arch/blackfin/include/asm/ipipe.h +++ b/arch/blackfin/include/asm/ipipe.h | |||
@@ -35,9 +35,9 @@ | |||
35 | #include <asm/atomic.h> | 35 | #include <asm/atomic.h> |
36 | #include <asm/traps.h> | 36 | #include <asm/traps.h> |
37 | 37 | ||
38 | #define IPIPE_ARCH_STRING "1.8-00" | 38 | #define IPIPE_ARCH_STRING "1.9-00" |
39 | #define IPIPE_MAJOR_NUMBER 1 | 39 | #define IPIPE_MAJOR_NUMBER 1 |
40 | #define IPIPE_MINOR_NUMBER 8 | 40 | #define IPIPE_MINOR_NUMBER 9 |
41 | #define IPIPE_PATCH_NUMBER 0 | 41 | #define IPIPE_PATCH_NUMBER 0 |
42 | 42 | ||
43 | #ifdef CONFIG_SMP | 43 | #ifdef CONFIG_SMP |
@@ -83,9 +83,9 @@ struct ipipe_sysinfo { | |||
83 | "%2 = CYCLES2\n" \ | 83 | "%2 = CYCLES2\n" \ |
84 | "CC = %2 == %0\n" \ | 84 | "CC = %2 == %0\n" \ |
85 | "if ! CC jump 1b\n" \ | 85 | "if ! CC jump 1b\n" \ |
86 | : "=r" (((unsigned long *)&t)[1]), \ | 86 | : "=d,a" (((unsigned long *)&t)[1]), \ |
87 | "=r" (((unsigned long *)&t)[0]), \ | 87 | "=d,a" (((unsigned long *)&t)[0]), \ |
88 | "=r" (__cy2) \ | 88 | "=d,a" (__cy2) \ |
89 | : /*no input*/ : "CC"); \ | 89 | : /*no input*/ : "CC"); \ |
90 | t; \ | 90 | t; \ |
91 | }) | 91 | }) |
@@ -118,35 +118,40 @@ void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, | |||
118 | 118 | ||
119 | #define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq)) | 119 | #define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq)) |
120 | 120 | ||
121 | #define __ipipe_lock_root() \ | 121 | static inline int __ipipe_check_tickdev(const char *devname) |
122 | set_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags) | 122 | { |
123 | return 1; | ||
124 | } | ||
123 | 125 | ||
124 | #define __ipipe_unlock_root() \ | 126 | static inline void __ipipe_lock_root(void) |
125 | clear_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags) | 127 | { |
128 | set_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)); | ||
129 | } | ||
130 | |||
131 | static inline void __ipipe_unlock_root(void) | ||
132 | { | ||
133 | clear_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)); | ||
134 | } | ||
126 | 135 | ||
127 | void __ipipe_enable_pipeline(void); | 136 | void __ipipe_enable_pipeline(void); |
128 | 137 | ||
129 | #define __ipipe_hook_critical_ipi(ipd) do { } while (0) | 138 | #define __ipipe_hook_critical_ipi(ipd) do { } while (0) |
130 | 139 | ||
131 | #define __ipipe_sync_pipeline(syncmask) \ | 140 | #define __ipipe_sync_pipeline ___ipipe_sync_pipeline |
132 | do { \ | 141 | void ___ipipe_sync_pipeline(unsigned long syncmask); |
133 | struct ipipe_domain *ipd = ipipe_current_domain; \ | ||
134 | if (likely(ipd != ipipe_root_domain || !test_bit(IPIPE_ROOTLOCK_FLAG, &ipd->flags))) \ | ||
135 | __ipipe_sync_stage(syncmask); \ | ||
136 | } while (0) | ||
137 | 142 | ||
138 | void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs); | 143 | void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs); |
139 | 144 | ||
140 | int __ipipe_get_irq_priority(unsigned irq); | 145 | int __ipipe_get_irq_priority(unsigned irq); |
141 | 146 | ||
142 | int __ipipe_get_irqthread_priority(unsigned irq); | ||
143 | |||
144 | void __ipipe_stall_root_raw(void); | 147 | void __ipipe_stall_root_raw(void); |
145 | 148 | ||
146 | void __ipipe_unstall_root_raw(void); | 149 | void __ipipe_unstall_root_raw(void); |
147 | 150 | ||
148 | void __ipipe_serial_debug(const char *fmt, ...); | 151 | void __ipipe_serial_debug(const char *fmt, ...); |
149 | 152 | ||
153 | asmlinkage void __ipipe_call_irqtail(unsigned long addr); | ||
154 | |||
150 | DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs); | 155 | DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs); |
151 | 156 | ||
152 | extern unsigned long __ipipe_core_clock; | 157 | extern unsigned long __ipipe_core_clock; |
@@ -162,42 +167,25 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul) | |||
162 | 167 | ||
163 | #define __ipipe_run_irqtail() /* Must be a macro */ \ | 168 | #define __ipipe_run_irqtail() /* Must be a macro */ \ |
164 | do { \ | 169 | do { \ |
165 | asmlinkage void __ipipe_call_irqtail(void); \ | ||
166 | unsigned long __pending; \ | 170 | unsigned long __pending; \ |
167 | CSYNC(); \ | 171 | CSYNC(); \ |
168 | __pending = bfin_read_IPEND(); \ | 172 | __pending = bfin_read_IPEND(); \ |
169 | if (__pending & 0x8000) { \ | 173 | if (__pending & 0x8000) { \ |
170 | __pending &= ~0x8010; \ | 174 | __pending &= ~0x8010; \ |
171 | if (__pending && (__pending & (__pending - 1)) == 0) \ | 175 | if (__pending && (__pending & (__pending - 1)) == 0) \ |
172 | __ipipe_call_irqtail(); \ | 176 | __ipipe_call_irqtail(__ipipe_irq_tail_hook); \ |
173 | } \ | 177 | } \ |
174 | } while (0) | 178 | } while (0) |
175 | 179 | ||
176 | #define __ipipe_run_isr(ipd, irq) \ | 180 | #define __ipipe_run_isr(ipd, irq) \ |
177 | do { \ | 181 | do { \ |
178 | if (ipd == ipipe_root_domain) { \ | 182 | if (ipd == ipipe_root_domain) { \ |
179 | /* \ | 183 | local_irq_enable_hw(); \ |
180 | * Note: the I-pipe implements a threaded interrupt model on \ | 184 | if (ipipe_virtual_irq_p(irq)) \ |
181 | * this arch for Linux external IRQs. The interrupt handler we \ | ||
182 | * call here only wakes up the associated IRQ thread. \ | ||
183 | */ \ | ||
184 | if (ipipe_virtual_irq_p(irq)) { \ | ||
185 | /* No irqtail here; virtual interrupts have no effect \ | ||
186 | on IPEND so there is no need for processing \ | ||
187 | deferral. */ \ | ||
188 | local_irq_enable_nohead(ipd); \ | ||
189 | ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ | 185 | ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ |
190 | local_irq_disable_nohead(ipd); \ | 186 | else \ |
191 | } else \ | ||
192 | /* \ | ||
193 | * No need to run the irqtail here either; \ | ||
194 | * we can't be preempted by hw IRQs, so \ | ||
195 | * non-Linux IRQs cannot stack over the short \ | ||
196 | * thread wakeup code. Which in turn means \ | ||
197 | * that no irqtail condition could be pending \ | ||
198 | * for domains above Linux in the pipeline. \ | ||
199 | */ \ | ||
200 | ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \ | 187 | ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \ |
188 | local_irq_disable_hw(); \ | ||
201 | } else { \ | 189 | } else { \ |
202 | __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ | 190 | __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ |
203 | local_irq_enable_nohead(ipd); \ | 191 | local_irq_enable_nohead(ipd); \ |
@@ -217,42 +205,24 @@ void ipipe_init_irq_threads(void); | |||
217 | 205 | ||
218 | int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); | 206 | int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); |
219 | 207 | ||
220 | #define IS_SYSIRQ(irq) ((irq) > IRQ_CORETMR && (irq) <= SYS_IRQS) | 208 | #ifdef CONFIG_GENERIC_CLOCKEVENTS |
221 | #define IS_GPIOIRQ(irq) ((irq) >= GPIO_IRQ_BASE && (irq) < NR_IRQS) | 209 | #define IRQ_SYSTMR IRQ_CORETMR |
222 | 210 | #define IRQ_PRIOTMR IRQ_CORETMR | |
211 | #else | ||
223 | #define IRQ_SYSTMR IRQ_TIMER0 | 212 | #define IRQ_SYSTMR IRQ_TIMER0 |
224 | #define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 | 213 | #define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 |
214 | #endif | ||
225 | 215 | ||
226 | #if defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) | 216 | #ifdef CONFIG_BF561 |
227 | #define PRIO_GPIODEMUX(irq) CONFIG_PFA | ||
228 | #elif defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) | ||
229 | #define PRIO_GPIODEMUX(irq) CONFIG_IRQ_PROG_INTA | ||
230 | #elif defined(CONFIG_BF52x) | ||
231 | #define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PORTF_INTA ? CONFIG_IRQ_PORTF_INTA : \ | ||
232 | (irq) == IRQ_PORTG_INTA ? CONFIG_IRQ_PORTG_INTA : \ | ||
233 | (irq) == IRQ_PORTH_INTA ? CONFIG_IRQ_PORTH_INTA : \ | ||
234 | -1) | ||
235 | #elif defined(CONFIG_BF561) | ||
236 | #define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PROG0_INTA ? CONFIG_IRQ_PROG0_INTA : \ | ||
237 | (irq) == IRQ_PROG1_INTA ? CONFIG_IRQ_PROG1_INTA : \ | ||
238 | (irq) == IRQ_PROG2_INTA ? CONFIG_IRQ_PROG2_INTA : \ | ||
239 | -1) | ||
240 | #define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val) | 217 | #define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val) |
241 | #define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val) | 218 | #define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val) |
242 | #define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val) | 219 | #define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val) |
243 | #define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS() | 220 | #define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS() |
244 | #elif defined(CONFIG_BF54x) | 221 | #elif defined(CONFIG_BF54x) |
245 | #define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PINT0 ? CONFIG_IRQ_PINT0 : \ | ||
246 | (irq) == IRQ_PINT1 ? CONFIG_IRQ_PINT1 : \ | ||
247 | (irq) == IRQ_PINT2 ? CONFIG_IRQ_PINT2 : \ | ||
248 | (irq) == IRQ_PINT3 ? CONFIG_IRQ_PINT3 : \ | ||
249 | -1) | ||
250 | #define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val) | 222 | #define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val) |
251 | #define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val) | 223 | #define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val) |
252 | #define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val) | 224 | #define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val) |
253 | #define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val) | 225 | #define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val) |
254 | #else | ||
255 | # error "no PRIO_GPIODEMUX() for this part" | ||
256 | #endif | 226 | #endif |
257 | 227 | ||
258 | #define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0) | 228 | #define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0) |
@@ -275,4 +245,6 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); | |||
275 | 245 | ||
276 | #endif /* !CONFIG_IPIPE */ | 246 | #endif /* !CONFIG_IPIPE */ |
277 | 247 | ||
248 | #define ipipe_update_tick_evtdev(evtdev) do { } while (0) | ||
249 | |||
278 | #endif /* !__ASM_BLACKFIN_IPIPE_H */ | 250 | #endif /* !__ASM_BLACKFIN_IPIPE_H */ |
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h index cb1025aeabcf..3e8acbd1a3be 100644 --- a/arch/blackfin/include/asm/ipipe_base.h +++ b/arch/blackfin/include/asm/ipipe_base.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* -*- linux-c -*- | 1 | /* -*- linux-c -*- |
2 | * include/asm-blackfin/_baseipipe.h | 2 | * include/asm-blackfin/ipipe_base.h |
3 | * | 3 | * |
4 | * Copyright (C) 2007 Philippe Gerum. | 4 | * Copyright (C) 2007 Philippe Gerum. |
5 | * | 5 | * |
@@ -27,8 +27,9 @@ | |||
27 | #define IPIPE_NR_XIRQS NR_IRQS | 27 | #define IPIPE_NR_XIRQS NR_IRQS |
28 | #define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */ | 28 | #define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */ |
29 | 29 | ||
30 | /* Blackfin-specific, global domain flags */ | 30 | /* Blackfin-specific, per-cpu pipeline status */ |
31 | #define IPIPE_ROOTLOCK_FLAG 1 /* Lock pipeline for root */ | 31 | #define IPIPE_SYNCDEFER_FLAG 15 |
32 | #define IPIPE_SYNCDEFER_MASK (1L << IPIPE_SYNCDEFER_MASK) | ||
32 | 33 | ||
33 | /* Blackfin traps -- i.e. exception vector numbers */ | 34 | /* Blackfin traps -- i.e. exception vector numbers */ |
34 | #define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */ | 35 | #define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */ |
@@ -48,11 +49,6 @@ | |||
48 | 49 | ||
49 | #ifndef __ASSEMBLY__ | 50 | #ifndef __ASSEMBLY__ |
50 | 51 | ||
51 | #include <linux/bitops.h> | ||
52 | |||
53 | extern int test_bit(int nr, const void *addr); | ||
54 | |||
55 | |||
56 | extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ | 52 | extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ |
57 | 53 | ||
58 | static inline void __ipipe_stall_root(void) | 54 | static inline void __ipipe_stall_root(void) |
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h index 3d977909ce7d..7645e85a5f6f 100644 --- a/arch/blackfin/include/asm/irq.h +++ b/arch/blackfin/include/asm/irq.h | |||
@@ -61,20 +61,38 @@ void __ipipe_restore_root(unsigned long flags); | |||
61 | #define raw_irqs_disabled_flags(flags) (!irqs_enabled_from_flags_hw(flags)) | 61 | #define raw_irqs_disabled_flags(flags) (!irqs_enabled_from_flags_hw(flags)) |
62 | #define local_test_iflag_hw(x) irqs_enabled_from_flags_hw(x) | 62 | #define local_test_iflag_hw(x) irqs_enabled_from_flags_hw(x) |
63 | 63 | ||
64 | #define local_save_flags(x) \ | 64 | #define local_save_flags(x) \ |
65 | do { \ | 65 | do { \ |
66 | (x) = __ipipe_test_root() ? \ | 66 | (x) = __ipipe_test_root() ? \ |
67 | __all_masked_irq_flags : bfin_irq_flags; \ | 67 | __all_masked_irq_flags : bfin_irq_flags; \ |
68 | barrier(); \ | ||
68 | } while (0) | 69 | } while (0) |
69 | 70 | ||
70 | #define local_irq_save(x) \ | 71 | #define local_irq_save(x) \ |
71 | do { \ | 72 | do { \ |
72 | (x) = __ipipe_test_and_stall_root(); \ | 73 | (x) = __ipipe_test_and_stall_root() ? \ |
74 | __all_masked_irq_flags : bfin_irq_flags; \ | ||
75 | barrier(); \ | ||
76 | } while (0) | ||
77 | |||
78 | static inline void local_irq_restore(unsigned long x) | ||
79 | { | ||
80 | barrier(); | ||
81 | __ipipe_restore_root(x == __all_masked_irq_flags); | ||
82 | } | ||
83 | |||
84 | #define local_irq_disable() \ | ||
85 | do { \ | ||
86 | __ipipe_stall_root(); \ | ||
87 | barrier(); \ | ||
73 | } while (0) | 88 | } while (0) |
74 | 89 | ||
75 | #define local_irq_restore(x) __ipipe_restore_root(x) | 90 | static inline void local_irq_enable(void) |
76 | #define local_irq_disable() __ipipe_stall_root() | 91 | { |
77 | #define local_irq_enable() __ipipe_unstall_root() | 92 | barrier(); |
93 | __ipipe_unstall_root(); | ||
94 | } | ||
95 | |||
78 | #define irqs_disabled() __ipipe_test_root() | 96 | #define irqs_disabled() __ipipe_test_root() |
79 | 97 | ||
80 | #define local_save_flags_hw(x) \ | 98 | #define local_save_flags_hw(x) \ |
diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h index e721ce55956c..2920087516f2 100644 --- a/arch/blackfin/include/asm/thread_info.h +++ b/arch/blackfin/include/asm/thread_info.h | |||
@@ -122,6 +122,7 @@ static inline struct thread_info *current_thread_info(void) | |||
122 | #define TIF_MEMDIE 4 | 122 | #define TIF_MEMDIE 4 |
123 | #define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ | 123 | #define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ |
124 | #define TIF_FREEZE 6 /* is freezing for suspend */ | 124 | #define TIF_FREEZE 6 /* is freezing for suspend */ |
125 | #define TIF_IRQ_SYNC 7 /* sync pipeline stage */ | ||
125 | 126 | ||
126 | /* as above, but as bit values */ | 127 | /* as above, but as bit values */ |
127 | #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) | 128 | #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) |
@@ -130,6 +131,7 @@ static inline struct thread_info *current_thread_info(void) | |||
130 | #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) | 131 | #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) |
131 | #define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) | 132 | #define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) |
132 | #define _TIF_FREEZE (1<<TIF_FREEZE) | 133 | #define _TIF_FREEZE (1<<TIF_FREEZE) |
134 | #define _TIF_IRQ_SYNC (1<<TIF_IRQ_SYNC) | ||
133 | 135 | ||
134 | #define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ | 136 | #define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ |
135 | 137 | ||
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c index 339be5a3ae6a..a5de8d45424c 100644 --- a/arch/blackfin/kernel/ipipe.c +++ b/arch/blackfin/kernel/ipipe.c | |||
@@ -35,14 +35,8 @@ | |||
35 | #include <asm/atomic.h> | 35 | #include <asm/atomic.h> |
36 | #include <asm/io.h> | 36 | #include <asm/io.h> |
37 | 37 | ||
38 | static int create_irq_threads; | ||
39 | |||
40 | DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs); | 38 | DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs); |
41 | 39 | ||
42 | static DEFINE_PER_CPU(unsigned long, pending_irqthread_mask); | ||
43 | |||
44 | static DEFINE_PER_CPU(int [IVG13 + 1], pending_irq_count); | ||
45 | |||
46 | asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); | 40 | asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); |
47 | 41 | ||
48 | static void __ipipe_no_irqtail(void); | 42 | static void __ipipe_no_irqtail(void); |
@@ -93,6 +87,7 @@ void __ipipe_enable_pipeline(void) | |||
93 | */ | 87 | */ |
94 | void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) | 88 | void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) |
95 | { | 89 | { |
90 | struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); | ||
96 | struct ipipe_domain *this_domain, *next_domain; | 91 | struct ipipe_domain *this_domain, *next_domain; |
97 | struct list_head *head, *pos; | 92 | struct list_head *head, *pos; |
98 | int m_ack, s = -1; | 93 | int m_ack, s = -1; |
@@ -104,7 +99,6 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) | |||
104 | * interrupt. | 99 | * interrupt. |
105 | */ | 100 | */ |
106 | m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR); | 101 | m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR); |
107 | |||
108 | this_domain = ipipe_current_domain; | 102 | this_domain = ipipe_current_domain; |
109 | 103 | ||
110 | if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control))) | 104 | if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control))) |
@@ -114,49 +108,28 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) | |||
114 | next_domain = list_entry(head, struct ipipe_domain, p_link); | 108 | next_domain = list_entry(head, struct ipipe_domain, p_link); |
115 | if (likely(test_bit(IPIPE_WIRED_FLAG, &next_domain->irqs[irq].control))) { | 109 | if (likely(test_bit(IPIPE_WIRED_FLAG, &next_domain->irqs[irq].control))) { |
116 | if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) | 110 | if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) |
117 | next_domain->irqs[irq].acknowledge(irq, irq_desc + irq); | 111 | next_domain->irqs[irq].acknowledge(irq, irq_to_desc(irq)); |
118 | if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)) | 112 | if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status)) |
119 | s = __test_and_set_bit(IPIPE_STALL_FLAG, | 113 | s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status); |
120 | &ipipe_root_cpudom_var(status)); | ||
121 | __ipipe_dispatch_wired(next_domain, irq); | 114 | __ipipe_dispatch_wired(next_domain, irq); |
122 | goto finalize; | 115 | goto out; |
123 | return; | ||
124 | } | 116 | } |
125 | } | 117 | } |
126 | 118 | ||
127 | /* Ack the interrupt. */ | 119 | /* Ack the interrupt. */ |
128 | 120 | ||
129 | pos = head; | 121 | pos = head; |
130 | |||
131 | while (pos != &__ipipe_pipeline) { | 122 | while (pos != &__ipipe_pipeline) { |
132 | next_domain = list_entry(pos, struct ipipe_domain, p_link); | 123 | next_domain = list_entry(pos, struct ipipe_domain, p_link); |
133 | /* | ||
134 | * For each domain handling the incoming IRQ, mark it | ||
135 | * as pending in its log. | ||
136 | */ | ||
137 | if (test_bit(IPIPE_HANDLE_FLAG, &next_domain->irqs[irq].control)) { | 124 | if (test_bit(IPIPE_HANDLE_FLAG, &next_domain->irqs[irq].control)) { |
138 | /* | ||
139 | * Domains that handle this IRQ are polled for | ||
140 | * acknowledging it by decreasing priority | ||
141 | * order. The interrupt must be made pending | ||
142 | * _first_ in the domain's status flags before | ||
143 | * the PIC is unlocked. | ||
144 | */ | ||
145 | __ipipe_set_irq_pending(next_domain, irq); | 125 | __ipipe_set_irq_pending(next_domain, irq); |
146 | |||
147 | if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) { | 126 | if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) { |
148 | next_domain->irqs[irq].acknowledge(irq, irq_desc + irq); | 127 | next_domain->irqs[irq].acknowledge(irq, irq_to_desc(irq)); |
149 | m_ack = 1; | 128 | m_ack = 1; |
150 | } | 129 | } |
151 | } | 130 | } |
152 | |||
153 | /* | ||
154 | * If the domain does not want the IRQ to be passed | ||
155 | * down the interrupt pipe, exit the loop now. | ||
156 | */ | ||
157 | if (!test_bit(IPIPE_PASS_FLAG, &next_domain->irqs[irq].control)) | 131 | if (!test_bit(IPIPE_PASS_FLAG, &next_domain->irqs[irq].control)) |
158 | break; | 132 | break; |
159 | |||
160 | pos = next_domain->p_link.next; | 133 | pos = next_domain->p_link.next; |
161 | } | 134 | } |
162 | 135 | ||
@@ -166,18 +139,24 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) | |||
166 | * immediately to the current domain if the interrupt has been | 139 | * immediately to the current domain if the interrupt has been |
167 | * marked as 'sticky'. This search does not go beyond the | 140 | * marked as 'sticky'. This search does not go beyond the |
168 | * current domain in the pipeline. We also enforce the | 141 | * current domain in the pipeline. We also enforce the |
169 | * additional root stage lock (blackfin-specific). */ | 142 | * additional root stage lock (blackfin-specific). |
143 | */ | ||
144 | if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status)) | ||
145 | s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status); | ||
170 | 146 | ||
171 | if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)) | 147 | /* |
172 | s = __test_and_set_bit(IPIPE_STALL_FLAG, | 148 | * If the interrupt preempted the head domain, then do not |
173 | &ipipe_root_cpudom_var(status)); | 149 | * even try to walk the pipeline, unless an interrupt is |
174 | finalize: | 150 | * pending for it. |
151 | */ | ||
152 | if (test_bit(IPIPE_AHEAD_FLAG, &this_domain->flags) && | ||
153 | ipipe_head_cpudom_var(irqpend_himask) == 0) | ||
154 | goto out; | ||
175 | 155 | ||
176 | __ipipe_walk_pipeline(head); | 156 | __ipipe_walk_pipeline(head); |
177 | 157 | out: | |
178 | if (!s) | 158 | if (!s) |
179 | __clear_bit(IPIPE_STALL_FLAG, | 159 | __clear_bit(IPIPE_STALL_FLAG, &p->status); |
180 | &ipipe_root_cpudom_var(status)); | ||
181 | } | 160 | } |
182 | 161 | ||
183 | int __ipipe_check_root(void) | 162 | int __ipipe_check_root(void) |
@@ -187,7 +166,7 @@ int __ipipe_check_root(void) | |||
187 | 166 | ||
188 | void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq) | 167 | void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq) |
189 | { | 168 | { |
190 | struct irq_desc *desc = irq_desc + irq; | 169 | struct irq_desc *desc = irq_to_desc(irq); |
191 | int prio = desc->ic_prio; | 170 | int prio = desc->ic_prio; |
192 | 171 | ||
193 | desc->depth = 0; | 172 | desc->depth = 0; |
@@ -199,7 +178,7 @@ EXPORT_SYMBOL(__ipipe_enable_irqdesc); | |||
199 | 178 | ||
200 | void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq) | 179 | void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq) |
201 | { | 180 | { |
202 | struct irq_desc *desc = irq_desc + irq; | 181 | struct irq_desc *desc = irq_to_desc(irq); |
203 | int prio = desc->ic_prio; | 182 | int prio = desc->ic_prio; |
204 | 183 | ||
205 | if (ipd != &ipipe_root && | 184 | if (ipd != &ipipe_root && |
@@ -236,15 +215,18 @@ int __ipipe_syscall_root(struct pt_regs *regs) | |||
236 | { | 215 | { |
237 | unsigned long flags; | 216 | unsigned long flags; |
238 | 217 | ||
239 | /* We need to run the IRQ tail hook whenever we don't | 218 | /* |
219 | * We need to run the IRQ tail hook whenever we don't | ||
240 | * propagate a syscall to higher domains, because we know that | 220 | * propagate a syscall to higher domains, because we know that |
241 | * important operations might be pending there (e.g. Xenomai | 221 | * important operations might be pending there (e.g. Xenomai |
242 | * deferred rescheduling). */ | 222 | * deferred rescheduling). |
223 | */ | ||
243 | 224 | ||
244 | if (!__ipipe_syscall_watched_p(current, regs->orig_p0)) { | 225 | if (regs->orig_p0 < NR_syscalls) { |
245 | void (*hook)(void) = (void (*)(void))__ipipe_irq_tail_hook; | 226 | void (*hook)(void) = (void (*)(void))__ipipe_irq_tail_hook; |
246 | hook(); | 227 | hook(); |
247 | return 0; | 228 | if ((current->flags & PF_EVNOTIFY) == 0) |
229 | return 0; | ||
248 | } | 230 | } |
249 | 231 | ||
250 | /* | 232 | /* |
@@ -312,112 +294,46 @@ int ipipe_trigger_irq(unsigned irq) | |||
312 | { | 294 | { |
313 | unsigned long flags; | 295 | unsigned long flags; |
314 | 296 | ||
297 | #ifdef CONFIG_IPIPE_DEBUG | ||
315 | if (irq >= IPIPE_NR_IRQS || | 298 | if (irq >= IPIPE_NR_IRQS || |
316 | (ipipe_virtual_irq_p(irq) | 299 | (ipipe_virtual_irq_p(irq) |
317 | && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map))) | 300 | && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map))) |
318 | return -EINVAL; | 301 | return -EINVAL; |
302 | #endif | ||
319 | 303 | ||
320 | local_irq_save_hw(flags); | 304 | local_irq_save_hw(flags); |
321 | |||
322 | __ipipe_handle_irq(irq, NULL); | 305 | __ipipe_handle_irq(irq, NULL); |
323 | |||
324 | local_irq_restore_hw(flags); | 306 | local_irq_restore_hw(flags); |
325 | 307 | ||
326 | return 1; | 308 | return 1; |
327 | } | 309 | } |
328 | 310 | ||
329 | /* Move Linux IRQ to threads. */ | 311 | asmlinkage void __ipipe_sync_root(void) |
330 | |||
331 | static int do_irqd(void *__desc) | ||
332 | { | 312 | { |
333 | struct irq_desc *desc = __desc; | 313 | unsigned long flags; |
334 | unsigned irq = desc - irq_desc; | ||
335 | int thrprio = desc->thr_prio; | ||
336 | int thrmask = 1 << thrprio; | ||
337 | int cpu = smp_processor_id(); | ||
338 | cpumask_t cpumask; | ||
339 | |||
340 | sigfillset(¤t->blocked); | ||
341 | current->flags |= PF_NOFREEZE; | ||
342 | cpumask = cpumask_of_cpu(cpu); | ||
343 | set_cpus_allowed(current, cpumask); | ||
344 | ipipe_setscheduler_root(current, SCHED_FIFO, 50 + thrprio); | ||
345 | |||
346 | while (!kthread_should_stop()) { | ||
347 | local_irq_disable(); | ||
348 | if (!(desc->status & IRQ_SCHEDULED)) { | ||
349 | set_current_state(TASK_INTERRUPTIBLE); | ||
350 | resched: | ||
351 | local_irq_enable(); | ||
352 | schedule(); | ||
353 | local_irq_disable(); | ||
354 | } | ||
355 | __set_current_state(TASK_RUNNING); | ||
356 | /* | ||
357 | * If higher priority interrupt servers are ready to | ||
358 | * run, reschedule immediately. We need this for the | ||
359 | * GPIO demux IRQ handler to unmask the interrupt line | ||
360 | * _last_, after all GPIO IRQs have run. | ||
361 | */ | ||
362 | if (per_cpu(pending_irqthread_mask, cpu) & ~(thrmask|(thrmask-1))) | ||
363 | goto resched; | ||
364 | if (--per_cpu(pending_irq_count[thrprio], cpu) == 0) | ||
365 | per_cpu(pending_irqthread_mask, cpu) &= ~thrmask; | ||
366 | desc->status &= ~IRQ_SCHEDULED; | ||
367 | desc->thr_handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); | ||
368 | local_irq_enable(); | ||
369 | } | ||
370 | __set_current_state(TASK_RUNNING); | ||
371 | return 0; | ||
372 | } | ||
373 | 314 | ||
374 | static void kick_irqd(unsigned irq, void *cookie) | 315 | BUG_ON(irqs_disabled()); |
375 | { | ||
376 | struct irq_desc *desc = irq_desc + irq; | ||
377 | int thrprio = desc->thr_prio; | ||
378 | int thrmask = 1 << thrprio; | ||
379 | int cpu = smp_processor_id(); | ||
380 | |||
381 | if (!(desc->status & IRQ_SCHEDULED)) { | ||
382 | desc->status |= IRQ_SCHEDULED; | ||
383 | per_cpu(pending_irqthread_mask, cpu) |= thrmask; | ||
384 | ++per_cpu(pending_irq_count[thrprio], cpu); | ||
385 | wake_up_process(desc->thread); | ||
386 | } | ||
387 | } | ||
388 | 316 | ||
389 | int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc) | 317 | local_irq_save_hw(flags); |
390 | { | ||
391 | if (desc->thread || !create_irq_threads) | ||
392 | return 0; | ||
393 | |||
394 | desc->thread = kthread_create(do_irqd, desc, "IRQ %d", irq); | ||
395 | if (desc->thread == NULL) { | ||
396 | printk(KERN_ERR "irqd: could not create IRQ thread %d!\n", irq); | ||
397 | return -ENOMEM; | ||
398 | } | ||
399 | 318 | ||
400 | wake_up_process(desc->thread); | 319 | clear_thread_flag(TIF_IRQ_SYNC); |
401 | 320 | ||
402 | desc->thr_handler = ipipe_root_domain->irqs[irq].handler; | 321 | if (ipipe_root_cpudom_var(irqpend_himask) != 0) |
403 | ipipe_root_domain->irqs[irq].handler = &kick_irqd; | 322 | __ipipe_sync_pipeline(IPIPE_IRQMASK_ANY); |
404 | 323 | ||
405 | return 0; | 324 | local_irq_restore_hw(flags); |
406 | } | 325 | } |
407 | 326 | ||
408 | void __init ipipe_init_irq_threads(void) | 327 | void ___ipipe_sync_pipeline(unsigned long syncmask) |
409 | { | 328 | { |
410 | unsigned irq; | 329 | struct ipipe_domain *ipd = ipipe_current_domain; |
411 | struct irq_desc *desc; | ||
412 | |||
413 | create_irq_threads = 1; | ||
414 | 330 | ||
415 | for (irq = 0; irq < NR_IRQS; irq++) { | 331 | if (ipd == ipipe_root_domain) { |
416 | desc = irq_desc + irq; | 332 | if (test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status))) |
417 | if (desc->action != NULL || | 333 | return; |
418 | (desc->status & IRQ_NOREQUEST) != 0) | ||
419 | ipipe_start_irq_thread(irq, desc); | ||
420 | } | 334 | } |
335 | |||
336 | __ipipe_sync_stage(syncmask); | ||
421 | } | 337 | } |
422 | 338 | ||
423 | EXPORT_SYMBOL(show_stack); | 339 | EXPORT_SYMBOL(show_stack); |
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c index 75724eee6494..7fd126564846 100644 --- a/arch/blackfin/kernel/irqchip.c +++ b/arch/blackfin/kernel/irqchip.c | |||
@@ -144,11 +144,15 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) | |||
144 | #endif | 144 | #endif |
145 | generic_handle_irq(irq); | 145 | generic_handle_irq(irq); |
146 | 146 | ||
147 | #ifndef CONFIG_IPIPE /* Useless and bugous over the I-pipe: IRQs are threaded. */ | 147 | #ifndef CONFIG_IPIPE |
148 | /* If we're the only interrupt running (ignoring IRQ15 which is for | 148 | /* |
149 | syscalls), lower our priority to IRQ14 so that softirqs run at | 149 | * If we're the only interrupt running (ignoring IRQ15 which |
150 | that level. If there's another, lower-level interrupt, irq_exit | 150 | * is for syscalls), lower our priority to IRQ14 so that |
151 | will defer softirqs to that. */ | 151 | * softirqs run at that level. If there's another, |
152 | * lower-level interrupt, irq_exit will defer softirqs to | ||
153 | * that. If the interrupt pipeline is enabled, we are already | ||
154 | * running at IRQ14 priority, so we don't need this code. | ||
155 | */ | ||
152 | CSYNC(); | 156 | CSYNC(); |
153 | pending = bfin_read_IPEND() & ~0x8000; | 157 | pending = bfin_read_IPEND() & ~0x8000; |
154 | other_ints = pending & (pending - 1); | 158 | other_ints = pending & (pending - 1); |
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c index 172b4c588467..1bbacfbd4c5d 100644 --- a/arch/blackfin/kernel/time.c +++ b/arch/blackfin/kernel/time.c | |||
@@ -134,7 +134,10 @@ irqreturn_t timer_interrupt(int irq, void *dummy) | |||
134 | 134 | ||
135 | write_seqlock(&xtime_lock); | 135 | write_seqlock(&xtime_lock); |
136 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE) | 136 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE) |
137 | /* FIXME: Here TIMIL0 is not set when IPIPE enabled, why? */ | 137 | /* |
138 | * TIMIL0 is latched in __ipipe_grab_irq() when the I-Pipe is | ||
139 | * enabled. | ||
140 | */ | ||
138 | if (get_gptimer_status(0) & TIMER_STATUS_TIMIL0) { | 141 | if (get_gptimer_status(0) & TIMER_STATUS_TIMIL0) { |
139 | #endif | 142 | #endif |
140 | do_timer(1); | 143 | do_timer(1); |
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index 88de053bbe8e..21e65a339a22 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S | |||
@@ -600,6 +600,19 @@ ENTRY(_system_call) | |||
600 | p2 = [p2]; | 600 | p2 = [p2]; |
601 | 601 | ||
602 | [p2+(TASK_THREAD+THREAD_KSP)] = sp; | 602 | [p2+(TASK_THREAD+THREAD_KSP)] = sp; |
603 | #ifdef CONFIG_IPIPE | ||
604 | r0 = sp; | ||
605 | SP += -12; | ||
606 | call ___ipipe_syscall_root; | ||
607 | SP += 12; | ||
608 | cc = r0 == 1; | ||
609 | if cc jump .Lsyscall_really_exit; | ||
610 | cc = r0 == -1; | ||
611 | if cc jump .Lresume_userspace; | ||
612 | r3 = [sp + PT_R3]; | ||
613 | r4 = [sp + PT_R4]; | ||
614 | p0 = [sp + PT_ORIG_P0]; | ||
615 | #endif /* CONFIG_IPIPE */ | ||
603 | 616 | ||
604 | /* Check the System Call */ | 617 | /* Check the System Call */ |
605 | r7 = __NR_syscall; | 618 | r7 = __NR_syscall; |
@@ -654,6 +667,17 @@ ENTRY(_system_call) | |||
654 | r7 = r7 & r4; | 667 | r7 = r7 & r4; |
655 | 668 | ||
656 | .Lsyscall_resched: | 669 | .Lsyscall_resched: |
670 | #ifdef CONFIG_IPIPE | ||
671 | cc = BITTST(r7, TIF_IRQ_SYNC); | ||
672 | if !cc jump .Lsyscall_no_irqsync; | ||
673 | [--sp] = reti; | ||
674 | r0 = [sp++]; | ||
675 | SP += -12; | ||
676 | call ___ipipe_sync_root; | ||
677 | SP += 12; | ||
678 | jump .Lresume_userspace_1; | ||
679 | .Lsyscall_no_irqsync: | ||
680 | #endif | ||
657 | cc = BITTST(r7, TIF_NEED_RESCHED); | 681 | cc = BITTST(r7, TIF_NEED_RESCHED); |
658 | if !cc jump .Lsyscall_sigpending; | 682 | if !cc jump .Lsyscall_sigpending; |
659 | 683 | ||
@@ -685,6 +709,10 @@ ENTRY(_system_call) | |||
685 | .Lsyscall_really_exit: | 709 | .Lsyscall_really_exit: |
686 | r5 = [sp + PT_RESERVED]; | 710 | r5 = [sp + PT_RESERVED]; |
687 | rets = r5; | 711 | rets = r5; |
712 | #ifdef CONFIG_IPIPE | ||
713 | [--sp] = reti; | ||
714 | r5 = [sp++]; | ||
715 | #endif /* CONFIG_IPIPE */ | ||
688 | rts; | 716 | rts; |
689 | ENDPROC(_system_call) | 717 | ENDPROC(_system_call) |
690 | 718 | ||
@@ -771,6 +799,15 @@ _new_old_task: | |||
771 | ENDPROC(_resume) | 799 | ENDPROC(_resume) |
772 | 800 | ||
773 | ENTRY(_ret_from_exception) | 801 | ENTRY(_ret_from_exception) |
802 | #ifdef CONFIG_IPIPE | ||
803 | [--sp] = rets; | ||
804 | SP += -12; | ||
805 | call ___ipipe_check_root | ||
806 | SP += 12 | ||
807 | rets = [sp++]; | ||
808 | cc = r0 == 0; | ||
809 | if cc jump 4f; /* not on behalf of Linux, get out */ | ||
810 | #endif /* CONFIG_IPIPE */ | ||
774 | p2.l = lo(IPEND); | 811 | p2.l = lo(IPEND); |
775 | p2.h = hi(IPEND); | 812 | p2.h = hi(IPEND); |
776 | 813 | ||
@@ -827,6 +864,28 @@ ENTRY(_ret_from_exception) | |||
827 | rts; | 864 | rts; |
828 | ENDPROC(_ret_from_exception) | 865 | ENDPROC(_ret_from_exception) |
829 | 866 | ||
867 | #ifdef CONFIG_IPIPE | ||
868 | |||
869 | _sync_root_irqs: | ||
870 | [--sp] = reti; /* Reenable interrupts */ | ||
871 | r0 = [sp++]; | ||
872 | jump.l ___ipipe_sync_root | ||
873 | |||
874 | _resume_kernel_from_int: | ||
875 | r0.l = _sync_root_irqs | ||
876 | r0.h = _sync_root_irqs | ||
877 | [--sp] = rets; | ||
878 | [--sp] = ( r7:4, p5:3 ); | ||
879 | SP += -12; | ||
880 | call ___ipipe_call_irqtail | ||
881 | SP += 12; | ||
882 | ( r7:4, p5:3 ) = [sp++]; | ||
883 | rets = [sp++]; | ||
884 | rts | ||
885 | #else | ||
886 | #define _resume_kernel_from_int 2f | ||
887 | #endif | ||
888 | |||
830 | ENTRY(_return_from_int) | 889 | ENTRY(_return_from_int) |
831 | /* If someone else already raised IRQ 15, do nothing. */ | 890 | /* If someone else already raised IRQ 15, do nothing. */ |
832 | csync; | 891 | csync; |
@@ -848,7 +907,7 @@ ENTRY(_return_from_int) | |||
848 | r1 = r0 - r1; | 907 | r1 = r0 - r1; |
849 | r2 = r0 & r1; | 908 | r2 = r0 & r1; |
850 | cc = r2 == 0; | 909 | cc = r2 == 0; |
851 | if !cc jump 2f; | 910 | if !cc jump _resume_kernel_from_int; |
852 | 911 | ||
853 | /* Lower the interrupt level to 15. */ | 912 | /* Lower the interrupt level to 15. */ |
854 | p0.l = lo(EVT15); | 913 | p0.l = lo(EVT15); |
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S index 43c4eb9acb65..0069c2dd4625 100644 --- a/arch/blackfin/mach-common/interrupt.S +++ b/arch/blackfin/mach-common/interrupt.S | |||
@@ -235,6 +235,7 @@ ENDPROC(_evt_system_call) | |||
235 | 235 | ||
236 | #ifdef CONFIG_IPIPE | 236 | #ifdef CONFIG_IPIPE |
237 | ENTRY(___ipipe_call_irqtail) | 237 | ENTRY(___ipipe_call_irqtail) |
238 | p0 = r0; | ||
238 | r0.l = 1f; | 239 | r0.l = 1f; |
239 | r0.h = 1f; | 240 | r0.h = 1f; |
240 | reti = r0; | 241 | reti = r0; |
@@ -242,9 +243,6 @@ ENTRY(___ipipe_call_irqtail) | |||
242 | 1: | 243 | 1: |
243 | [--sp] = rets; | 244 | [--sp] = rets; |
244 | [--sp] = ( r7:4, p5:3 ); | 245 | [--sp] = ( r7:4, p5:3 ); |
245 | p0.l = ___ipipe_irq_tail_hook; | ||
246 | p0.h = ___ipipe_irq_tail_hook; | ||
247 | p0 = [p0]; | ||
248 | sp += -12; | 246 | sp += -12; |
249 | call (p0); | 247 | call (p0); |
250 | sp += 12; | 248 | sp += 12; |
@@ -259,7 +257,7 @@ ENTRY(___ipipe_call_irqtail) | |||
259 | p0.h = hi(EVT14); | 257 | p0.h = hi(EVT14); |
260 | [p0] = r0; | 258 | [p0] = r0; |
261 | csync; | 259 | csync; |
262 | r0 = 0x401f; | 260 | r0 = 0x401f (z); |
263 | sti r0; | 261 | sti r0; |
264 | raise 14; | 262 | raise 14; |
265 | [--sp] = reti; /* IRQs on. */ | 263 | [--sp] = reti; /* IRQs on. */ |
@@ -277,11 +275,7 @@ ENTRY(___ipipe_call_irqtail) | |||
277 | p0.h = _bfin_irq_flags; | 275 | p0.h = _bfin_irq_flags; |
278 | r0 = [p0]; | 276 | r0 = [p0]; |
279 | sti r0; | 277 | sti r0; |
280 | #if 0 /* FIXME: this actually raises scheduling latencies */ | ||
281 | /* Reenable interrupts */ | ||
282 | [--sp] = reti; | ||
283 | r0 = [sp++]; | ||
284 | #endif | ||
285 | rts; | 278 | rts; |
286 | ENDPROC(___ipipe_call_irqtail) | 279 | ENDPROC(___ipipe_call_irqtail) |
280 | |||
287 | #endif /* CONFIG_IPIPE */ | 281 | #endif /* CONFIG_IPIPE */ |
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index 202494568c6c..a7d7b2dd4059 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c | |||
@@ -161,11 +161,15 @@ static void bfin_core_unmask_irq(unsigned int irq) | |||
161 | 161 | ||
162 | static void bfin_internal_mask_irq(unsigned int irq) | 162 | static void bfin_internal_mask_irq(unsigned int irq) |
163 | { | 163 | { |
164 | unsigned long flags; | ||
165 | |||
164 | #ifdef CONFIG_BF53x | 166 | #ifdef CONFIG_BF53x |
167 | local_irq_save_hw(flags); | ||
165 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & | 168 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & |
166 | ~(1 << SIC_SYSIRQ(irq))); | 169 | ~(1 << SIC_SYSIRQ(irq))); |
167 | #else | 170 | #else |
168 | unsigned mask_bank, mask_bit; | 171 | unsigned mask_bank, mask_bit; |
172 | local_irq_save_hw(flags); | ||
169 | mask_bank = SIC_SYSIRQ(irq) / 32; | 173 | mask_bank = SIC_SYSIRQ(irq) / 32; |
170 | mask_bit = SIC_SYSIRQ(irq) % 32; | 174 | mask_bit = SIC_SYSIRQ(irq) % 32; |
171 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & | 175 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & |
@@ -175,15 +179,20 @@ static void bfin_internal_mask_irq(unsigned int irq) | |||
175 | ~(1 << mask_bit)); | 179 | ~(1 << mask_bit)); |
176 | #endif | 180 | #endif |
177 | #endif | 181 | #endif |
182 | local_irq_restore_hw(flags); | ||
178 | } | 183 | } |
179 | 184 | ||
180 | static void bfin_internal_unmask_irq(unsigned int irq) | 185 | static void bfin_internal_unmask_irq(unsigned int irq) |
181 | { | 186 | { |
187 | unsigned long flags; | ||
188 | |||
182 | #ifdef CONFIG_BF53x | 189 | #ifdef CONFIG_BF53x |
190 | local_irq_save_hw(flags); | ||
183 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | | 191 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | |
184 | (1 << SIC_SYSIRQ(irq))); | 192 | (1 << SIC_SYSIRQ(irq))); |
185 | #else | 193 | #else |
186 | unsigned mask_bank, mask_bit; | 194 | unsigned mask_bank, mask_bit; |
195 | local_irq_save_hw(flags); | ||
187 | mask_bank = SIC_SYSIRQ(irq) / 32; | 196 | mask_bank = SIC_SYSIRQ(irq) / 32; |
188 | mask_bit = SIC_SYSIRQ(irq) % 32; | 197 | mask_bit = SIC_SYSIRQ(irq) % 32; |
189 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | | 198 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | |
@@ -193,6 +202,7 @@ static void bfin_internal_unmask_irq(unsigned int irq) | |||
193 | (1 << mask_bit)); | 202 | (1 << mask_bit)); |
194 | #endif | 203 | #endif |
195 | #endif | 204 | #endif |
205 | local_irq_restore_hw(flags); | ||
196 | } | 206 | } |
197 | 207 | ||
198 | #ifdef CONFIG_PM | 208 | #ifdef CONFIG_PM |
@@ -390,7 +400,7 @@ static void bfin_demux_error_irq(unsigned int int_err_irq, | |||
390 | static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) | 400 | static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) |
391 | { | 401 | { |
392 | #ifdef CONFIG_IPIPE | 402 | #ifdef CONFIG_IPIPE |
393 | _set_irq_handler(irq, handle_edge_irq); | 403 | _set_irq_handler(irq, handle_level_irq); |
394 | #else | 404 | #else |
395 | struct irq_desc *desc = irq_desc + irq; | 405 | struct irq_desc *desc = irq_desc + irq; |
396 | /* May not call generic set_irq_handler() due to spinlock | 406 | /* May not call generic set_irq_handler() due to spinlock |
@@ -1055,13 +1065,18 @@ int __init init_arch_irq(void) | |||
1055 | #endif | 1065 | #endif |
1056 | default: | 1066 | default: |
1057 | #ifdef CONFIG_IPIPE | 1067 | #ifdef CONFIG_IPIPE |
1058 | /* | 1068 | /* |
1059 | * We want internal interrupt sources to be masked, because | 1069 | * We want internal interrupt sources to be |
1060 | * ISRs may trigger interrupts recursively (e.g. DMA), but | 1070 | * masked, because ISRs may trigger interrupts |
1061 | * interrupts are _not_ masked at CPU level. So let's handle | 1071 | * recursively (e.g. DMA), but interrupts are |
1062 | * them as level interrupts. | 1072 | * _not_ masked at CPU level. So let's handle |
1063 | */ | 1073 | * most of them as level interrupts, except |
1064 | set_irq_handler(irq, handle_level_irq); | 1074 | * the timer interrupt which is special. |
1075 | */ | ||
1076 | if (irq == IRQ_SYSTMR || irq == IRQ_CORETMR) | ||
1077 | set_irq_handler(irq, handle_simple_irq); | ||
1078 | else | ||
1079 | set_irq_handler(irq, handle_level_irq); | ||
1065 | #else /* !CONFIG_IPIPE */ | 1080 | #else /* !CONFIG_IPIPE */ |
1066 | set_irq_handler(irq, handle_simple_irq); | 1081 | set_irq_handler(irq, handle_simple_irq); |
1067 | #endif /* !CONFIG_IPIPE */ | 1082 | #endif /* !CONFIG_IPIPE */ |
@@ -1123,9 +1138,8 @@ int __init init_arch_irq(void) | |||
1123 | 1138 | ||
1124 | #ifdef CONFIG_IPIPE | 1139 | #ifdef CONFIG_IPIPE |
1125 | for (irq = 0; irq < NR_IRQS; irq++) { | 1140 | for (irq = 0; irq < NR_IRQS; irq++) { |
1126 | struct irq_desc *desc = irq_desc + irq; | 1141 | struct irq_desc *desc = irq_to_desc(irq); |
1127 | desc->ic_prio = __ipipe_get_irq_priority(irq); | 1142 | desc->ic_prio = __ipipe_get_irq_priority(irq); |
1128 | desc->thr_prio = __ipipe_get_irqthread_priority(irq); | ||
1129 | } | 1143 | } |
1130 | #endif /* CONFIG_IPIPE */ | 1144 | #endif /* CONFIG_IPIPE */ |
1131 | 1145 | ||
@@ -1208,76 +1222,21 @@ int __ipipe_get_irq_priority(unsigned irq) | |||
1208 | return IVG15; | 1222 | return IVG15; |
1209 | } | 1223 | } |
1210 | 1224 | ||
1211 | int __ipipe_get_irqthread_priority(unsigned irq) | ||
1212 | { | ||
1213 | int ient, prio; | ||
1214 | int demux_irq; | ||
1215 | |||
1216 | /* The returned priority value is rescaled to [0..IVG13+1] | ||
1217 | * with 0 being the lowest effective priority level. */ | ||
1218 | |||
1219 | if (irq <= IRQ_CORETMR) | ||
1220 | return IVG13 - irq + 1; | ||
1221 | |||
1222 | /* GPIO IRQs are given the priority of the demux | ||
1223 | * interrupt. */ | ||
1224 | if (IS_GPIOIRQ(irq)) { | ||
1225 | #if defined(CONFIG_BF54x) | ||
1226 | u32 bank = PINT_2_BANK(irq2pint_lut[irq - SYS_IRQS]); | ||
1227 | demux_irq = (bank == 0 ? IRQ_PINT0 : | ||
1228 | bank == 1 ? IRQ_PINT1 : | ||
1229 | bank == 2 ? IRQ_PINT2 : | ||
1230 | IRQ_PINT3); | ||
1231 | #elif defined(CONFIG_BF561) | ||
1232 | demux_irq = (irq >= IRQ_PF32 ? IRQ_PROG2_INTA : | ||
1233 | irq >= IRQ_PF16 ? IRQ_PROG1_INTA : | ||
1234 | IRQ_PROG0_INTA); | ||
1235 | #elif defined(CONFIG_BF52x) | ||
1236 | demux_irq = (irq >= IRQ_PH0 ? IRQ_PORTH_INTA : | ||
1237 | irq >= IRQ_PG0 ? IRQ_PORTG_INTA : | ||
1238 | IRQ_PORTF_INTA); | ||
1239 | #else | ||
1240 | demux_irq = irq; | ||
1241 | #endif | ||
1242 | return IVG13 - PRIO_GPIODEMUX(demux_irq) + 1; | ||
1243 | } | ||
1244 | |||
1245 | /* The GPIO demux interrupt is given a lower priority | ||
1246 | * than the GPIO IRQs, so that its threaded handler | ||
1247 | * unmasks the interrupt line after the decoded IRQs | ||
1248 | * have been processed. */ | ||
1249 | prio = PRIO_GPIODEMUX(irq); | ||
1250 | /* demux irq? */ | ||
1251 | if (prio != -1) | ||
1252 | return IVG13 - prio; | ||
1253 | |||
1254 | for (ient = 0; ient < NR_PERI_INTS; ient++) { | ||
1255 | struct ivgx *ivg = ivg_table + ient; | ||
1256 | if (ivg->irqno == irq) { | ||
1257 | for (prio = 0; prio <= IVG13-IVG7; prio++) { | ||
1258 | if (ivg7_13[prio].ifirst <= ivg && | ||
1259 | ivg7_13[prio].istop > ivg) | ||
1260 | return IVG7 - prio; | ||
1261 | } | ||
1262 | } | ||
1263 | } | ||
1264 | |||
1265 | return 0; | ||
1266 | } | ||
1267 | |||
1268 | /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */ | 1225 | /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */ |
1269 | #ifdef CONFIG_DO_IRQ_L1 | 1226 | #ifdef CONFIG_DO_IRQ_L1 |
1270 | __attribute__((l1_text)) | 1227 | __attribute__((l1_text)) |
1271 | #endif | 1228 | #endif |
1272 | asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) | 1229 | asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) |
1273 | { | 1230 | { |
1231 | struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); | ||
1232 | struct ipipe_domain *this_domain = ipipe_current_domain; | ||
1274 | struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; | 1233 | struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; |
1275 | struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; | 1234 | struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; |
1276 | int irq; | 1235 | int irq, s; |
1277 | 1236 | ||
1278 | if (likely(vec == EVT_IVTMR_P)) { | 1237 | if (likely(vec == EVT_IVTMR_P)) { |
1279 | irq = IRQ_CORETMR; | 1238 | irq = IRQ_CORETMR; |
1280 | goto handle_irq; | 1239 | goto core_tick; |
1281 | } | 1240 | } |
1282 | 1241 | ||
1283 | SSYNC(); | 1242 | SSYNC(); |
@@ -1319,24 +1278,39 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) | |||
1319 | irq = ivg->irqno; | 1278 | irq = ivg->irqno; |
1320 | 1279 | ||
1321 | if (irq == IRQ_SYSTMR) { | 1280 | if (irq == IRQ_SYSTMR) { |
1281 | #ifdef CONFIG_GENERIC_CLOCKEVENTS | ||
1282 | core_tick: | ||
1283 | #else | ||
1322 | bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ | 1284 | bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ |
1285 | #endif | ||
1323 | /* This is basically what we need from the register frame. */ | 1286 | /* This is basically what we need from the register frame. */ |
1324 | __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend; | 1287 | __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend; |
1325 | __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc; | 1288 | __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc; |
1326 | if (!ipipe_root_domain_p) | 1289 | if (this_domain != ipipe_root_domain) |
1327 | __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; | ||
1328 | else | ||
1329 | __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10; | 1290 | __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10; |
1291 | else | ||
1292 | __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; | ||
1330 | } | 1293 | } |
1331 | 1294 | ||
1332 | handle_irq: | 1295 | #ifndef CONFIG_GENERIC_CLOCKEVENTS |
1296 | core_tick: | ||
1297 | #endif | ||
1298 | if (this_domain == ipipe_root_domain) { | ||
1299 | s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status); | ||
1300 | barrier(); | ||
1301 | } | ||
1333 | 1302 | ||
1334 | ipipe_trace_irq_entry(irq); | 1303 | ipipe_trace_irq_entry(irq); |
1335 | __ipipe_handle_irq(irq, regs); | 1304 | __ipipe_handle_irq(irq, regs); |
1336 | ipipe_trace_irq_exit(irq); | 1305 | ipipe_trace_irq_exit(irq); |
1337 | 1306 | ||
1338 | if (ipipe_root_domain_p) | 1307 | if (this_domain == ipipe_root_domain) { |
1339 | return !test_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status)); | 1308 | set_thread_flag(TIF_IRQ_SYNC); |
1309 | if (!s) { | ||
1310 | __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status); | ||
1311 | return !test_bit(IPIPE_STALL_FLAG, &p->status); | ||
1312 | } | ||
1313 | } | ||
1340 | 1314 | ||
1341 | return 0; | 1315 | return 0; |
1342 | } | 1316 | } |