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-rw-r--r--arch/arm/include/asm/pgtable.h8
-rw-r--r--arch/arm/mm/mmu.c4
-rw-r--r--arch/arm/mm/proc-macros.S30
-rw-r--r--arch/arm/mm/proc-v6.S4
-rw-r--r--arch/arm/mm/proc-v7.S4
-rw-r--r--arch/arm/mm/proc-xsc3.S4
-rw-r--r--arch/arm/mm/proc-xscale.S4
7 files changed, 40 insertions, 18 deletions
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 8f039a08b00c..dfeff814a942 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -175,8 +175,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
175/* 175/*
176 * These are the memory types, defined to be compatible with 176 * These are the memory types, defined to be compatible with
177 * pre-ARMv6 CPUs cacheable and bufferable bits: XXCB 177 * pre-ARMv6 CPUs cacheable and bufferable bits: XXCB
178 * (note: build_mem_type_table modifies these bits
179 * to work with our existing proc-*.S setup.)
180 */ 178 */
181#define L_PTE_MT_UNCACHED (0x00 << 2) /* 0000 */ 179#define L_PTE_MT_UNCACHED (0x00 << 2) /* 0000 */
182#define L_PTE_MT_BUFFERABLE (0x01 << 2) /* 0001 */ 180#define L_PTE_MT_BUFFERABLE (0x01 << 2) /* 0001 */
@@ -184,12 +182,10 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
184#define L_PTE_MT_WRITEBACK (0x03 << 2) /* 0011 */ 182#define L_PTE_MT_WRITEBACK (0x03 << 2) /* 0011 */
185#define L_PTE_MT_MINICACHE (0x06 << 2) /* 0110 (sa1100, xscale) */ 183#define L_PTE_MT_MINICACHE (0x06 << 2) /* 0110 (sa1100, xscale) */
186#define L_PTE_MT_WRITEALLOC (0x07 << 2) /* 0111 */ 184#define L_PTE_MT_WRITEALLOC (0x07 << 2) /* 0111 */
187#define L_PTE_MT_DEV_SHARED (0x04 << 2) /* 0100 (pre-v6) */ 185#define L_PTE_MT_DEV_SHARED (0x04 << 2) /* 0100 */
188#define L_PTE_MT_DEV_SHARED2 (0x05 << 2) /* 0101 (v6) */
189#define L_PTE_MT_DEV_NONSHARED (0x0c << 2) /* 1100 */ 186#define L_PTE_MT_DEV_NONSHARED (0x0c << 2) /* 1100 */
190#define L_PTE_MT_DEV_IXP2000 (0x0d << 2) /* 1101 */ 187#define L_PTE_MT_DEV_IXP2000 (0x0d << 2) /* 1101 */
191#define L_PTE_MT_DEV_WC (0x09 << 2) /* 1001 (pre-v6) */ 188#define L_PTE_MT_DEV_WC (0x09 << 2) /* 1001 */
192#define L_PTE_MT_DEV_WC2 (0x08 << 2) /* 1000 (v6) */
193#define L_PTE_MT_DEV_CACHED (0x0b << 2) /* 1011 */ 189#define L_PTE_MT_DEV_CACHED (0x0b << 2) /* 1011 */
194#define L_PTE_MT_MASK (0x0f << 2) 190#define L_PTE_MT_MASK (0x0f << 2)
195 191
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index cfc0add4874e..04602288da2c 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -194,7 +194,6 @@ static struct mem_type mem_types[] = {
194 }, 194 },
195 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ 195 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
196 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, 196 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
197 .prot_pte_ext = PTE_EXT_TEX(2),
198 .prot_l1 = PMD_TYPE_TABLE, 197 .prot_l1 = PMD_TYPE_TABLE,
199 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_TEX(2), 198 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_TEX(2),
200 .domain = DOMAIN_IO, 199 .domain = DOMAIN_IO,
@@ -289,8 +288,6 @@ static void __init build_mem_type_table(void)
289 * in xsc3 parlance, Uncached Normal in ARMv6 parlance). 288 * in xsc3 parlance, Uncached Normal in ARMv6 parlance).
290 */ 289 */
291 if (cpu_is_xsc3() || cpu_arch >= CPU_ARCH_ARMv6) { 290 if (cpu_is_xsc3() || cpu_arch >= CPU_ARCH_ARMv6) {
292 mem_types[MT_DEVICE_WC].prot_pte_ext |= PTE_EXT_TEX(1);
293 mem_types[MT_DEVICE_WC].prot_pte &= ~L_PTE_BUFFERABLE;
294 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); 291 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
295 mem_types[MT_DEVICE_WC].prot_sect &= ~PMD_SECT_BUFFERABLE; 292 mem_types[MT_DEVICE_WC].prot_sect &= ~PMD_SECT_BUFFERABLE;
296 } 293 }
@@ -351,7 +348,6 @@ static void __init build_mem_type_table(void)
351 /* 348 /*
352 * Mark the device area as "shared device" 349 * Mark the device area as "shared device"
353 */ 350 */
354 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
355 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; 351 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
356 352
357#ifdef CONFIG_SMP 353#ifdef CONFIG_SMP
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index d1be25313d7b..64e593020857 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -104,14 +104,38 @@
104 * 11x0 0 1 0 r/w r/o 104 * 11x0 0 1 0 r/w r/o
105 * 1111 0 1 1 r/w r/w 105 * 1111 0 1 1 r/w r/w
106 */ 106 */
107 .macro armv6_set_pte_ext 107 .macro armv6_mt_table pfx
108\pfx\()_mt_table:
109 .long 0x00 @ L_PTE_MT_UNCACHED
110 .long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
111 .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
112 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
113 .long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
114 .long 0x00 @ unused
115 .long 0x00 @ L_PTE_MT_MINICACHE (not present)
116 .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
117 .long 0x00 @ unused
118 .long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
119 .long 0x00 @ unused
120 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
121 .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
122 .long 0x00 @ L_PTE_MT_DEV_IXP2000
123 .long 0x00 @ unused
124 .long 0x00 @ unused
125 .endm
126
127 .macro armv6_set_pte_ext pfx
108 str r1, [r0], #-2048 @ linux version 128 str r1, [r0], #-2048 @ linux version
109 129
110 bic r3, r1, #0x000003f0 130 bic r3, r1, #0x000003fc
111 bic r3, r3, #PTE_TYPE_MASK 131 bic r3, r3, #PTE_TYPE_MASK
112 orr r3, r3, r2 132 orr r3, r3, r2
113 orr r3, r3, #PTE_EXT_AP0 | 2 133 orr r3, r3, #PTE_EXT_AP0 | 2
114 134
135 adr ip, \pfx\()_mt_table
136 and r2, r1, #L_PTE_MT_MASK
137 ldr r2, [ip, r2]
138
115 tst r1, #L_PTE_WRITE 139 tst r1, #L_PTE_WRITE
116 tstne r1, #L_PTE_DIRTY 140 tstne r1, #L_PTE_DIRTY
117 orreq r3, r3, #PTE_EXT_APX 141 orreq r3, r3, #PTE_EXT_APX
@@ -124,6 +148,8 @@
124 tst r1, #L_PTE_EXEC 148 tst r1, #L_PTE_EXEC
125 orreq r3, r3, #PTE_EXT_XN 149 orreq r3, r3, #PTE_EXT_XN
126 150
151 orr r3, r3, r2
152
127 tst r1, #L_PTE_YOUNG 153 tst r1, #L_PTE_YOUNG
128 tstne r1, #L_PTE_PRESENT 154 tstne r1, #L_PTE_PRESENT
129 moveq r3, #0 155 moveq r3, #0
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 70c623534021..ab457757e851 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -115,9 +115,11 @@ ENTRY(cpu_v6_switch_mm)
115 * - pte - PTE value to store 115 * - pte - PTE value to store
116 * - ext - value for extended PTE bits 116 * - ext - value for extended PTE bits
117 */ 117 */
118 armv6_mt_table cpu_v6
119
118ENTRY(cpu_v6_set_pte_ext) 120ENTRY(cpu_v6_set_pte_ext)
119#ifdef CONFIG_MMU 121#ifdef CONFIG_MMU
120 armv6_set_pte_ext 122 armv6_set_pte_ext cpu_v6
121#endif 123#endif
122 mov pc, lr 124 mov pc, lr
123 125
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 172e2eeb6ddb..7c34c892b82b 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -100,9 +100,11 @@ ENTRY(cpu_v7_switch_mm)
100 * - pte - PTE value to store 100 * - pte - PTE value to store
101 * - ext - value for extended PTE bits 101 * - ext - value for extended PTE bits
102 */ 102 */
103 armv6_mt_table cpu_v7
104
103ENTRY(cpu_v7_set_pte_ext) 105ENTRY(cpu_v7_set_pte_ext)
104#ifdef CONFIG_MMU 106#ifdef CONFIG_MMU
105 armv6_set_pte_ext 107 armv6_set_pte_ext cpu_v7
106#endif 108#endif
107 mov pc, lr 109 mov pc, lr
108 110
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 96e47fc7fd6f..9c5318e476f3 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -354,10 +354,10 @@ cpu_xsc3_mt_table:
354 .long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH 354 .long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
355 .long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK 355 .long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
356 .long 0x00 @ L_PTE_MT_DEV_SHARED 356 .long 0x00 @ L_PTE_MT_DEV_SHARED
357 .long 0x00 @ L_PTE_MT_DEV_SHARED2 357 .long 0x00 @ unused
358 .long 0x00 @ L_PTE_MT_MINICACHE (not present) 358 .long 0x00 @ L_PTE_MT_MINICACHE (not present)
359 .long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?) 359 .long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?)
360 .long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC2 360 .long 0x00 @ unused
361 .long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC 361 .long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
362 .long 0x00 @ unused 362 .long 0x00 @ unused
363 .long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED 363 .long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 6fa525364bb7..1e0c3bb19058 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -435,10 +435,10 @@ cpu_xscale_mt_table:
435 .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH 435 .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
436 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK 436 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
437 .long 0x00 @ L_PTE_MT_DEV_SHARED 437 .long 0x00 @ L_PTE_MT_DEV_SHARED
438 .long 0x00 @ L_PTE_MT_DEV_SHARED2 438 .long 0x00 @ unused
439 .long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE 439 .long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE
440 .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC 440 .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
441 .long PTE_BUFFERABLE @ L_PTE_MT_DEV_WC2 441 .long 0x00 @ unused
442 .long PTE_BUFFERABLE @ L_PTE_MT_DEV_WC 442 .long PTE_BUFFERABLE @ L_PTE_MT_DEV_WC
443 .long 0x00 @ unused 443 .long 0x00 @ unused
444 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED 444 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 19:41:27 -0500