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-rw-r--r--arch/mips/pmc-sierra/msp71xx/Makefile11
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_elb.c46
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c179
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_irq.c124
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c134
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c109
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_prom.c566
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_setup.c256
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_time.c94
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_usb.c150
-rw-r--r--include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h151
-rw-r--r--include/asm-mips/pmc-sierra/msp71xx/msp_int.h43
-rw-r--r--include/asm-mips/pmc-sierra/msp71xx/msp_prom.h176
-rw-r--r--include/asm-mips/pmc-sierra/msp71xx/msp_regops.h236
-rw-r--r--include/asm-mips/pmc-sierra/msp71xx/msp_regs.h667
-rw-r--r--include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h141
16 files changed, 3083 insertions, 0 deletions
diff --git a/arch/mips/pmc-sierra/msp71xx/Makefile b/arch/mips/pmc-sierra/msp71xx/Makefile
new file mode 100644
index 000000000000..4bba79c1cc79
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for the PMC-Sierra MSP SOCs
3#
4obj-y += msp_prom.o msp_setup.o msp_irq.o \
5 msp_time.o msp_serial.o msp_elb.o
6obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o
7obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o
8obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o
9obj-$(CONFIG_PCI) += msp_pci.o
10obj-$(CONFIG_MSPETH) += msp_eth.o
11obj-$(CONFIG_USB_MSP71XX) += msp_usb.o
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_elb.c b/arch/mips/pmc-sierra/msp71xx/msp_elb.c
new file mode 100644
index 000000000000..3e9641007216
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_elb.c
@@ -0,0 +1,46 @@
1/*
2 * Sets up the proper Chip Select configuration registers. It is assumed that
3 * PMON sets up the ADDR and MASK registers properly.
4 *
5 * Copyright 2005-2006 PMC-Sierra, Inc.
6 * Author: Marc St-Jean, Marc_St-Jean@pmc-sierra.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/kernel.h>
30#include <linux/init.h>
31#include <msp_regs.h>
32
33static int __init msp_elb_setup(void)
34{
35#if defined(CONFIG_PMC_MSP7120_GW) \
36 || defined(CONFIG_PMC_MSP7120_EVAL)
37 /*
38 * Force all CNFG to be identical and equal to CS0,
39 * according to OPS doc
40 */
41 *CS1_CNFG_REG = *CS2_CNFG_REG = *CS3_CNFG_REG = *CS0_CNFG_REG;
42#endif
43 return 0;
44}
45
46subsys_initcall(msp_elb_setup);
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
new file mode 100644
index 000000000000..6fa85728158b
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
@@ -0,0 +1,179 @@
1/*
2 * Sets up interrupt handlers for various hardware switches which are
3 * connected to interrupt lines.
4 *
5 * Copyright 2005-2207 PMC-Sierra, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/kernel.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31
32#include <msp_int.h>
33#include <msp_regs.h>
34#include <msp_regops.h>
35#ifdef CONFIG_PMCTWILED
36#include <msp_led_macros.h>
37#endif
38
39/* For hwbutton_interrupt->initial_state */
40#define HWBUTTON_HI 0x1
41#define HWBUTTON_LO 0x2
42
43/*
44 * This struct describes a hardware button
45 */
46struct hwbutton_interrupt {
47 char *name; /* Name of button */
48 int irq; /* Actual LINUX IRQ */
49 int eirq; /* Extended IRQ number (0-7) */
50 int initial_state; /* The "normal" state of the switch */
51 void (*handle_hi)(void *); /* Handler: switch input has gone HI */
52 void (*handle_lo)(void *); /* Handler: switch input has gone LO */
53 void *data; /* Optional data to pass to handler */
54};
55
56#ifdef CONFIG_PMC_MSP7120_GW
57extern void msp_restart(char *);
58
59static void softreset_push(void *data)
60{
61 printk(KERN_WARNING "SOFTRESET switch was pushed\n");
62
63 /*
64 * In the future you could move this to the release handler,
65 * timing the difference between the 'push' and 'release', and only
66 * doing this ungraceful restart if the button has been down for
67 * a certain amount of time; otherwise doing a graceful restart.
68 */
69
70 msp_restart(NULL);
71}
72
73static void softreset_release(void *data)
74{
75 printk(KERN_WARNING "SOFTRESET switch was released\n");
76
77 /* Do nothing */
78}
79
80static void standby_on(void *data)
81{
82 printk(KERN_WARNING "STANDBY switch was set to ON (not implemented)\n");
83
84 /* TODO: Put board in standby mode */
85#ifdef CONFIG_PMCTWILED
86 msp_led_turn_off(MSP_LED_PWRSTANDBY_GREEN);
87 msp_led_turn_on(MSP_LED_PWRSTANDBY_RED);
88#endif
89}
90
91static void standby_off(void *data)
92{
93 printk(KERN_WARNING
94 "STANDBY switch was set to OFF (not implemented)\n");
95
96 /* TODO: Take out of standby mode */
97#ifdef CONFIG_PMCTWILED
98 msp_led_turn_on(MSP_LED_PWRSTANDBY_GREEN);
99 msp_led_turn_off(MSP_LED_PWRSTANDBY_RED);
100#endif
101}
102
103static struct hwbutton_interrupt softreset_sw = {
104 .name = "Softreset button",
105 .irq = MSP_INT_EXT0,
106 .eirq = 0,
107 .initial_state = HWBUTTON_HI,
108 .handle_hi = softreset_release,
109 .handle_lo = softreset_push,
110 .data = NULL,
111};
112
113static struct hwbutton_interrupt standby_sw = {
114 .name = "Standby switch",
115 .irq = MSP_INT_EXT1,
116 .eirq = 1,
117 .initial_state = HWBUTTON_HI,
118 .handle_hi = standby_off,
119 .handle_lo = standby_on,
120 .data = NULL,
121};
122#endif /* CONFIG_PMC_MSP7120_GW */
123
124static irqreturn_t hwbutton_handler(int irq, void *data)
125{
126 struct hwbutton_interrupt *hirq = data;
127 unsigned long cic_ext = *CIC_EXT_CFG_REG;
128
129 if (irq != hirq->irq)
130 return IRQ_NONE;
131
132 if (CIC_EXT_IS_ACTIVE_HI(cic_ext, hirq->eirq)) {
133 /* Interrupt: pin is now HI */
134 CIC_EXT_SET_ACTIVE_LO(cic_ext, hirq->eirq);
135 hirq->handle_hi(hirq->data);
136 } else {
137 /* Interrupt: pin is now LO */
138 CIC_EXT_SET_ACTIVE_HI(cic_ext, hirq->eirq);
139 hirq->handle_lo(hirq->data);
140 }
141
142 /*
143 * Invert the POLARITY of this level interrupt to ack the interrupt
144 * Thus next state change will invoke the opposite message
145 */
146 *CIC_EXT_CFG_REG = cic_ext;
147
148 return IRQ_HANDLED;
149}
150
151static int msp_hwbutton_register(struct hwbutton_interrupt *hirq)
152{
153 unsigned long cic_ext;
154
155 if (hirq->handle_hi == NULL || hirq->handle_lo == NULL)
156 return -EINVAL;
157
158 cic_ext = *CIC_EXT_CFG_REG;
159 CIC_EXT_SET_TRIGGER_LEVEL(cic_ext, hirq->eirq);
160 if (hirq->initial_state == HWBUTTON_HI)
161 CIC_EXT_SET_ACTIVE_LO(cic_ext, hirq->eirq);
162 else
163 CIC_EXT_SET_ACTIVE_HI(cic_ext, hirq->eirq);
164 *CIC_EXT_CFG_REG = cic_ext;
165
166 return request_irq(hirq->irq, hwbutton_handler, SA_INTERRUPT,
167 hirq->name, (void *)hirq);
168}
169
170static int __init msp_hwbutton_setup(void)
171{
172#ifdef CONFIG_PMC_MSP7120_GW
173 msp_hwbutton_register(&softreset_sw);
174 msp_hwbutton_register(&standby_sw);
175#endif
176 return 0;
177}
178
179subsys_initcall(msp_hwbutton_setup);
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq.c b/arch/mips/pmc-sierra/msp71xx/msp_irq.c
new file mode 100644
index 000000000000..734d598a2e3a
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq.c
@@ -0,0 +1,124 @@
1/*
2 * IRQ vector handles
3 *
4 * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <linux/interrupt.h>
15#include <linux/ptrace.h>
16#include <linux/time.h>
17
18#include <asm/irq_cpu.h>
19
20#include <msp_int.h>
21
22extern void msp_int_handle(void);
23
24/* SLP bases systems */
25extern void msp_slp_irq_init(void);
26extern void msp_slp_irq_dispatch(void);
27
28/* CIC based systems */
29extern void msp_cic_irq_init(void);
30extern void msp_cic_irq_dispatch(void);
31
32/*
33 * The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded
34 * hierarchical system. The first level are the direct MIPS interrupts
35 * and are assigned the interrupt range 0-7. The second level is the SLM
36 * interrupt controller and is assigned the range 8-39. The third level
37 * comprises the Peripherial block, the PCI block, the PCI MSI block and
38 * the SLP. The PCI interrupts and the SLP errors are handled by the
39 * relevant subsystems so the core interrupt code needs only concern
40 * itself with the Peripheral block. These are assigned interrupts in
41 * the range 40-71.
42 */
43
44asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
45{
46 u32 pending;
47
48 pending = read_c0_status() & read_c0_cause();
49
50 /*
51 * jump to the correct interrupt routine
52 * These are arranged in priority order and the timer
53 * comes first!
54 */
55
56#ifdef CONFIG_IRQ_MSP_CIC /* break out the CIC stuff for now */
57 if (pending & C_IRQ4) /* do the peripherals first, that's the timer */
58 msp_cic_irq_dispatch();
59
60 else if (pending & C_IRQ0)
61 do_IRQ(MSP_INT_MAC0);
62
63 else if (pending & C_IRQ1)
64 do_IRQ(MSP_INT_MAC1);
65
66 else if (pending & C_IRQ2)
67 do_IRQ(MSP_INT_USB);
68
69 else if (pending & C_IRQ3)
70 do_IRQ(MSP_INT_SAR);
71
72 else if (pending & C_IRQ5)
73 do_IRQ(MSP_INT_SEC);
74
75#else
76 if (pending & C_IRQ5)
77 do_IRQ(MSP_INT_TIMER);
78
79 else if (pending & C_IRQ0)
80 do_IRQ(MSP_INT_MAC0);
81
82 else if (pending & C_IRQ1)
83 do_IRQ(MSP_INT_MAC1);
84
85 else if (pending & C_IRQ3)
86 do_IRQ(MSP_INT_VE);
87
88 else if (pending & C_IRQ4)
89 msp_slp_irq_dispatch();
90#endif
91
92 else if (pending & C_SW0) /* do software after hardware */
93 do_IRQ(MSP_INT_SW0);
94
95 else if (pending & C_SW1)
96 do_IRQ(MSP_INT_SW1);
97}
98
99static struct irqaction cascade_msp = {
100 .handler = no_action,
101 .name = "MSP cascade"
102};
103
104
105void __init arch_init_irq(void)
106{
107 /* initialize the 1st-level CPU based interrupt controller */
108 mips_cpu_irq_init();
109
110#ifdef CONFIG_IRQ_MSP_CIC
111 msp_cic_irq_init();
112
113 /* setup the cascaded interrupts */
114 setup_irq(MSP_INT_CIC, &cascade_msp);
115 setup_irq(MSP_INT_PER, &cascade_msp);
116#else
117 /* setup the 2nd-level SLP register based interrupt controller */
118 msp_slp_irq_init();
119
120 /* setup the cascaded SLP/PER interrupts */
121 setup_irq(MSP_INT_SLP, &cascade_msp);
122 setup_irq(MSP_INT_PER, &cascade_msp);
123#endif
124}
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
new file mode 100644
index 000000000000..5175357d0a25
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
@@ -0,0 +1,134 @@
1/*
2 * This file define the irq handler for MSP SLM subsystem interrupts.
3 *
4 * Copyright 2005-2007 PMC-Sierra, Inc, derived from irq_cpu.c
5 * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/bitops.h>
17
18#include <asm/system.h>
19
20#include <msp_cic_int.h>
21#include <msp_regs.h>
22
23/*
24 * NOTE: We are only enabling support for VPE0 right now.
25 */
26
27static inline void unmask_msp_cic_irq(unsigned int irq)
28{
29
30 /* check for PER interrupt range */
31 if (irq < MSP_PER_INTBASE)
32 *CIC_VPE0_MSK_REG |= (1 << (irq - MSP_CIC_INTBASE));
33 else
34 *PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE));
35}
36
37static inline void mask_msp_cic_irq(unsigned int irq)
38{
39 /* check for PER interrupt range */
40 if (irq < MSP_PER_INTBASE)
41 *CIC_VPE0_MSK_REG &= ~(1 << (irq - MSP_CIC_INTBASE));
42 else
43 *PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE));
44}
45
46/*
47 * While we ack the interrupt interrupts are disabled and thus we don't need
48 * to deal with concurrency issues. Same for msp_cic_irq_end.
49 */
50static inline void ack_msp_cic_irq(unsigned int irq)
51{
52 mask_msp_cic_irq(irq);
53
54 /*
55 * only really necessary for 18, 16-14 and sometimes 3:0 (since
56 * these can be edge sensitive) but it doesn't hurt for the others.
57 */
58
59 /* check for PER interrupt range */
60 if (irq < MSP_PER_INTBASE)
61 *CIC_STS_REG = (1 << (irq - MSP_CIC_INTBASE));
62 else
63 *PER_INT_STS_REG = (1 << (irq - MSP_PER_INTBASE));
64}
65
66static struct irq_chip msp_cic_irq_controller = {
67 .name = "MSP_CIC",
68 .ack = ack_msp_cic_irq,
69 .mask = ack_msp_cic_irq,
70 .mask_ack = ack_msp_cic_irq,
71 .unmask = unmask_msp_cic_irq,
72};
73
74
75void __init msp_cic_irq_init(void)
76{
77 int i;
78
79 /* Mask/clear interrupts. */
80 *CIC_VPE0_MSK_REG = 0x00000000;
81 *PER_INT_MSK_REG = 0x00000000;
82 *CIC_STS_REG = 0xFFFFFFFF;
83 *PER_INT_STS_REG = 0xFFFFFFFF;
84
85#if defined(CONFIG_PMC_MSP7120_GW) || \
86 defined(CONFIG_PMC_MSP7120_EVAL)
87 /*
88 * The MSP7120 RG and EVBD boards use IRQ[6:4] for PCI.
89 * These inputs map to EXT_INT_POL[6:4] inside the CIC.
90 * They are to be active low, level sensitive.
91 */
92 *CIC_EXT_CFG_REG &= 0xFFFF8F8F;
93#endif
94
95 /* initialize all the IRQ descriptors */
96 for (i = MSP_CIC_INTBASE; i < MSP_PER_INTBASE + 32; i++)
97 set_irq_chip_and_handler(i, &msp_cic_irq_controller,
98 handle_level_irq);
99}
100
101void msp_cic_irq_dispatch(void)
102{
103 u32 pending;
104 int intbase;
105
106 intbase = MSP_CIC_INTBASE;
107 pending = *CIC_STS_REG & *CIC_VPE0_MSK_REG;
108
109 /* check for PER interrupt */
110 if (pending == (1 << (MSP_INT_PER - MSP_CIC_INTBASE))) {
111 intbase = MSP_PER_INTBASE;
112 pending = *PER_INT_STS_REG & *PER_INT_MSK_REG;
113 }
114
115 /* check for spurious interrupt */
116 if (pending == 0x00000000) {
117 printk(KERN_ERR
118 "Spurious %s interrupt? status %08x, mask %08x\n",
119 (intbase == MSP_CIC_INTBASE) ? "CIC" : "PER",
120 (intbase == MSP_CIC_INTBASE) ?
121 *CIC_STS_REG : *PER_INT_STS_REG,
122 (intbase == MSP_CIC_INTBASE) ?
123 *CIC_VPE0_MSK_REG : *PER_INT_MSK_REG);
124 return;
125 }
126
127 /* check for the timer and dispatch it first */
128 if ((intbase == MSP_CIC_INTBASE) &&
129 (pending & (1 << (MSP_INT_VPE0_TIMER - MSP_CIC_INTBASE))))
130 do_IRQ(MSP_INT_VPE0_TIMER);
131 else
132 do_IRQ(ffs(pending) + intbase - 1);
133}
134
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
new file mode 100644
index 000000000000..f5f1b8d2bb9a
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
@@ -0,0 +1,109 @@
1/*
2 * This file define the irq handler for MSP SLM subsystem interrupts.
3 *
4 * Copyright 2005-2006 PMC-Sierra, Inc, derived from irq_cpu.c
5 * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/bitops.h>
17
18#include <asm/mipsregs.h>
19#include <asm/system.h>
20
21#include <msp_slp_int.h>
22#include <msp_regs.h>
23
24static inline void unmask_msp_slp_irq(unsigned int irq)
25{
26 /* check for PER interrupt range */
27 if (irq < MSP_PER_INTBASE)
28 *SLP_INT_MSK_REG |= (1 << (irq - MSP_SLP_INTBASE));
29 else
30 *PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE));
31}
32
33static inline void mask_msp_slp_irq(unsigned int irq)
34{
35 /* check for PER interrupt range */
36 if (irq < MSP_PER_INTBASE)
37 *SLP_INT_MSK_REG &= ~(1 << (irq - MSP_SLP_INTBASE));
38 else
39 *PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE));
40}
41
42/*
43 * While we ack the interrupt interrupts are disabled and thus we don't need
44 * to deal with concurrency issues. Same for msp_slp_irq_end.
45 */
46static inline void ack_msp_slp_irq(unsigned int irq)
47{
48 mask_slp_irq(irq);
49
50 /*
51 * only really necessary for 18, 16-14 and sometimes 3:0 (since
52 * these can be edge sensitive) but it doesn't hurt for the others.
53 */
54
55 /* check for PER interrupt range */
56 if (irq < MSP_PER_INTBASE)
57 *SLP_INT_STS_REG = (1 << (irq - MSP_SLP_INTBASE));
58 else
59 *PER_INT_STS_REG = (1 << (irq - MSP_PER_INTBASE));
60}
61
62static struct irq_chip msp_slp_irq_controller = {
63 .name = "MSP_SLP",
64 .ack = ack_msp_slp_irq,
65 .mask = ack_msp_slp_irq,
66 .mask_ack = ack_msp_slp_irq,
67 .unmask = unmask_msp_slp_irq,
68};
69
70void __init msp_slp_irq_init(void)
71{
72 int i;
73
74 /* Mask/clear interrupts. */
75 *SLP_INT_MSK_REG = 0x00000000;
76 *PER_INT_MSK_REG = 0x00000000;
77 *SLP_INT_STS_REG = 0xFFFFFFFF;
78 *PER_INT_STS_REG = 0xFFFFFFFF;
79
80 /* initialize all the IRQ descriptors */
81 for (i = MSP_SLP_INTBASE; i < MSP_PER_INTBASE + 32; i++)
82 set_irq_chip_and_handler(i, &msp_slp_irq_controller
83 handle_level_irq);
84}
85
86void msp_slp_irq_dispatch(void)
87{
88 u32 pending;
89 int intbase;
90
91 intbase = MSP_SLP_INTBASE;
92 pending = *SLP_INT_STS_REG & *SLP_INT_MSK_REG;
93
94 /* check for PER interrupt */
95 if (pending == (1 << (MSP_INT_PER - MSP_SLP_INTBASE))) {
96 intbase = MSP_PER_INTBASE;
97 pending = *PER_INT_STS_REG & *PER_INT_MSK_REG;
98 }
99
100 /* check for spurious interrupt */
101 if (pending == 0x00000000) {
102 printk(KERN_ERR "Spurious %s interrupt?\n",
103 (intbase == MSP_SLP_INTBASE) ? "SLP" : "PER");
104 return;
105 }
106
107 /* dispatch the irq */
108 do_IRQ(ffs(pending) + intbase - 1);
109}
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_prom.c b/arch/mips/pmc-sierra/msp71xx/msp_prom.c
new file mode 100644
index 000000000000..e5bd5481d8db
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_prom.c
@@ -0,0 +1,566 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * PROM library initialisation code, assuming a version of
4 * pmon is the boot code.
5 *
6 * Copyright 2000,2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This file was derived from Carsten Langgaard's
11 * arch/mips/mips-boards/xx files.
12 *
13 * Carsten Langgaard, carstenl@mips.com
14 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 */
36
37#include <linux/module.h>
38#include <linux/kernel.h>
39#include <linux/init.h>
40#include <linux/string.h>
41#include <linux/interrupt.h>
42#include <linux/mm.h>
43#ifdef CONFIG_CRAMFS
44#include <linux/cramfs_fs.h>
45#endif
46#ifdef CONFIG_SQUASHFS
47#include <linux/squashfs_fs.h>
48#endif
49
50#include <asm/addrspace.h>
51#include <asm/bootinfo.h>
52#include <asm-generic/sections.h>
53#include <asm/page.h>
54
55#include <msp_prom.h>
56#include <msp_regs.h>
57
58/* global PROM environment variables and pointers */
59int prom_argc;
60char **prom_argv, **prom_envp;
61int *prom_vec;
62
63/* debug flag */
64int init_debug = 1;
65
66/* memory blocks */
67struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
68
69/* default feature sets */
70static char msp_default_features[] =
71#if defined(CONFIG_PMC_MSP4200_EVAL) \
72 || defined(CONFIG_PMC_MSP4200_GW)
73 "ERER";
74#elif defined(CONFIG_PMC_MSP7120_EVAL) \
75 || defined(CONFIG_PMC_MSP7120_GW)
76 "EMEMSP";
77#elif defined(CONFIG_PMC_MSP7120_FPGA)
78 "EMEM";
79#endif
80
81/* conversion functions */
82static inline unsigned char str2hexnum(unsigned char c)
83{
84 if (c >= '0' && c <= '9')
85 return c - '0';
86 if (c >= 'a' && c <= 'f')
87 return c - 'a' + 10;
88 return 0; /* foo */
89}
90
91static inline int str2eaddr(unsigned char *ea, unsigned char *str)
92{
93 int index = 0;
94 unsigned char num = 0;
95
96 while (*str != '\0') {
97 if ((*str == '.') || (*str == ':')) {
98 ea[index++] = num;
99 num = 0;
100 str++;
101 } else {
102 num = num << 4;
103 num |= str2hexnum(*str++);
104 }
105 }
106
107 if (index == 5) {
108 ea[index++] = num;
109 return 0;
110 } else
111 return -1;
112}
113EXPORT_SYMBOL(str2eaddr);
114
115static inline unsigned long str2hex(unsigned char *str)
116{
117 int value = 0;
118
119 while (*str) {
120 value = value << 4;
121 value |= str2hexnum(*str++);
122 }
123
124 return value;
125}
126
127/* function to query the system information */
128const char *get_system_type(void)
129{
130#if defined(CONFIG_PMC_MSP4200_EVAL)
131 return "PMC-Sierra MSP4200 Eval Board";
132#elif defined(CONFIG_PMC_MSP4200_GW)
133 return "PMC-Sierra MSP4200 VoIP Gateway";
134#elif defined(CONFIG_PMC_MSP7120_EVAL)
135 return "PMC-Sierra MSP7120 Eval Board";
136#elif defined(CONFIG_PMC_MSP7120_GW)
137 return "PMC-Sierra MSP7120 Residential Gateway";
138#elif defined(CONFIG_PMC_MSP7120_FPGA)
139 return "PMC-Sierra MSP7120 FPGA";
140#else
141 #error "What is the type of *your* MSP?"
142#endif
143}
144
145int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr)
146{
147 char *ethaddr_str;
148
149 ethaddr_str = prom_getenv(ethaddr_name);
150 if (!ethaddr_str) {
151 printk(KERN_WARNING "%s not set in boot prom\n", ethaddr_name);
152 return -1;
153 }
154
155 if (str2eaddr(ethernet_addr, ethaddr_str) == -1) {
156 printk(KERN_WARNING "%s badly formatted-<%s>\n",
157 ethaddr_name, ethaddr_str);
158 return -1;
159 }
160
161 if (init_debug > 1) {
162 int i;
163 printk(KERN_DEBUG "get_ethernet_addr: for %s ", ethaddr_name);
164 for (i = 0; i < 5; i++)
165 printk(KERN_DEBUG "%02x:",
166 (unsigned char)*(ethernet_addr+i));
167 printk(KERN_DEBUG "%02x\n", *(ethernet_addr+i));
168 }
169
170 return 0;
171}
172EXPORT_SYMBOL(get_ethernet_addr);
173
174static char *get_features(void)
175{
176 char *feature = prom_getenv(FEATURES);
177
178 if (feature == NULL) {
179 /* default features based on MACHINE_TYPE */
180 feature = msp_default_features;
181 }
182
183 return feature;
184}
185
186static char test_feature(char c)
187{
188 char *feature = get_features();
189
190 while (*feature) {
191 if (*feature++ == c)
192 return *feature;
193 feature++;
194 }
195
196 return FEATURE_NOEXIST;
197}
198
199unsigned long get_deviceid(void)
200{
201 char *deviceid = prom_getenv(DEVICEID);
202
203 if (deviceid == NULL)
204 return *DEV_ID_REG;
205 else
206 return str2hex(deviceid);
207}
208
209char identify_pci(void)
210{
211 return test_feature(PCI_KEY);
212}
213EXPORT_SYMBOL(identify_pci);
214
215char identify_pcimux(void)
216{
217 return test_feature(PCIMUX_KEY);
218}
219
220char identify_sec(void)
221{
222 return test_feature(SEC_KEY);
223}
224EXPORT_SYMBOL(identify_sec);
225
226char identify_spad(void)
227{
228 return test_feature(SPAD_KEY);
229}
230EXPORT_SYMBOL(identify_spad);
231
232char identify_tdm(void)
233{
234 return test_feature(TDM_KEY);
235}
236EXPORT_SYMBOL(identify_tdm);
237
238char identify_zsp(void)
239{
240 return test_feature(ZSP_KEY);
241}
242EXPORT_SYMBOL(identify_zsp);
243
244static char identify_enetfeature(char key, unsigned long interface_num)
245{
246 char *feature = get_features();
247
248 while (*feature) {
249 if (*feature++ == key && interface_num-- == 0)
250 return *feature;
251 feature++;
252 }
253
254 return FEATURE_NOEXIST;
255}
256
257char identify_enet(unsigned long interface_num)
258{
259 return identify_enetfeature(ENET_KEY, interface_num);
260}
261EXPORT_SYMBOL(identify_enet);
262
263char identify_enetTxD(unsigned long interface_num)
264{
265 return identify_enetfeature(ENETTXD_KEY, interface_num);
266}
267EXPORT_SYMBOL(identify_enetTxD);
268
269unsigned long identify_family(void)
270{
271 unsigned long deviceid;
272
273 deviceid = get_deviceid();
274
275 return deviceid & CPU_DEVID_FAMILY;
276}
277EXPORT_SYMBOL(identify_family);
278
279unsigned long identify_revision(void)
280{
281 unsigned long deviceid;
282
283 deviceid = get_deviceid();
284
285 return deviceid & CPU_DEVID_REVISION;
286}
287EXPORT_SYMBOL(identify_revision);
288
289/* PROM environment functions */
290char *prom_getenv(char *env_name)
291{
292 /*
293 * Return a pointer to the given environment variable. prom_envp
294 * points to a null terminated array of pointers to variables.
295 * Environment variables are stored in the form of "memsize=64"
296 */
297
298 char **var = prom_envp;
299 int i = strlen(env_name);
300
301 while (*var) {
302 if (strncmp(env_name, *var, i) == 0) {
303 return (*var + strlen(env_name) + 1);
304 }
305 var++;
306 }
307
308 return NULL;
309}
310
311/* PROM commandline functions */
312char *prom_getcmdline(void)
313{
314 return &(arcs_cmdline[0]);
315}
316EXPORT_SYMBOL(prom_getcmdline);
317
318void __init prom_init_cmdline(void)
319{
320 char *cp;
321 int actr;
322
323 actr = 1; /* Always ignore argv[0] */
324
325 cp = &(arcs_cmdline[0]);
326 while (actr < prom_argc) {
327 strcpy(cp, prom_argv[actr]);
328 cp += strlen(prom_argv[actr]);
329 *cp++ = ' ';
330 actr++;
331 }
332 if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
333 --cp;
334 *cp = '\0';
335}
336
337/* memory allocation functions */
338static int __init prom_memtype_classify(unsigned int type)
339{
340 switch (type) {
341 case yamon_free:
342 return BOOT_MEM_RAM;
343 case yamon_prom:
344 return BOOT_MEM_ROM_DATA;
345 default:
346 return BOOT_MEM_RESERVED;
347 }
348}
349
350void __init prom_meminit(void)
351{
352 struct prom_pmemblock *p;
353
354 p = prom_getmdesc();
355
356 while (p->size) {
357 long type;
358 unsigned long base, size;
359
360 type = prom_memtype_classify(p->type);
361 base = p->base;
362 size = p->size;
363
364 add_memory_region(base, size, type);
365 p++;
366 }
367}
368
369void __init prom_free_prom_memory(void)
370{
371 int argc;
372 char **argv;
373 char **envp;
374 char *ptr;
375 int len = 0;
376 int i;
377 unsigned long addr;
378
379 /*
380 * preserve environment variables and command line from pmon/bbload
381 * first preserve the command line
382 */
383 for (argc = 0; argc < prom_argc; argc++) {
384 len += sizeof(char *); /* length of pointer */
385 len += strlen(prom_argv[argc]) + 1; /* length of string */
386 }
387 len += sizeof(char *); /* plus length of null pointer */
388
389 argv = kmalloc(len, GFP_KERNEL);
390 ptr = (char *) &argv[prom_argc + 1]; /* strings follow array */
391
392 for (argc = 0; argc < prom_argc; argc++) {
393 argv[argc] = ptr;
394 strcpy(ptr, prom_argv[argc]);
395 ptr += strlen(prom_argv[argc]) + 1;
396 }
397 argv[prom_argc] = NULL; /* end array with null pointer */
398 prom_argv = argv;
399
400 /* next preserve the environment variables */
401 len = 0;
402 i = 0;
403 for (envp = prom_envp; *envp != NULL; envp++) {
404 i++; /* count number of environment variables */
405 len += sizeof(char *); /* length of pointer */
406 len += strlen(*envp) + 1; /* length of string */
407 }
408 len += sizeof(char *); /* plus length of null pointer */
409
410 envp = kmalloc(len, GFP_KERNEL);
411 ptr = (char *) &envp[i+1];
412
413 for (argc = 0; argc < i; argc++) {
414 envp[argc] = ptr;
415 strcpy(ptr, prom_envp[argc]);
416 ptr += strlen(prom_envp[argc]) + 1;
417 }
418 envp[i] = NULL; /* end array with null pointer */
419 prom_envp = envp;
420
421 for (i = 0; i < boot_mem_map.nr_map; i++) {
422 if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
423 continue;
424
425 addr = boot_mem_map.map[i].addr;
426 free_init_pages("prom memory",
427 addr, addr + boot_mem_map.map[i].size);
428 }
429}
430
431struct prom_pmemblock *__init prom_getmdesc(void)
432{
433 static char memsz_env[] __initdata = "memsize";
434 static char heaptop_env[] __initdata = "heaptop";
435 char *str;
436 unsigned int memsize;
437 unsigned int heaptop;
438#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
439 void *ramroot_start;
440 unsigned long ramroot_size;
441#endif
442 int i;
443
444 str = prom_getenv(memsz_env);
445 if (!str) {
446 ppfinit("memsize not set in boot prom, "
447 "set to default (32Mb)\n");
448 memsize = 0x02000000;
449 } else {
450 memsize = simple_strtol(str, NULL, 0);
451
452 if (memsize == 0) {
453 /* if memsize is a bad size, use reasonable default */
454 memsize = 0x02000000;
455 }
456
457 /* convert to physical address (removing caching bits, etc) */
458 memsize = CPHYSADDR(memsize);
459 }
460
461 str = prom_getenv(heaptop_env);
462 if (!str) {
463 heaptop = CPHYSADDR((u32)&_text);
464 ppfinit("heaptop not set in boot prom, "
465 "set to default 0x%08x\n", heaptop);
466 } else {
467 heaptop = simple_strtol(str, NULL, 16);
468 if (heaptop == 0) {
469 /* heaptop conversion bad, might have 0xValue */
470 heaptop = simple_strtol(str, NULL, 0);
471
472 if (heaptop == 0) {
473 /* heaptop still bad, use reasonable default */
474 heaptop = CPHYSADDR((u32)&_text);
475 }
476 }
477
478 /* convert to physical address (removing caching bits, etc) */
479 heaptop = CPHYSADDR((u32)heaptop);
480 }
481
482 /* the base region */
483 i = 0;
484 mdesc[i].type = BOOT_MEM_RESERVED;
485 mdesc[i].base = 0x00000000;
486 mdesc[i].size = PAGE_ALIGN(0x300 + 0x80);
487 /* jtag interrupt vector + sizeof vector */
488
489 /* PMON data */
490 if (heaptop > mdesc[i].base + mdesc[i].size) {
491 i++; /* 1 */
492 mdesc[i].type = BOOT_MEM_ROM_DATA;
493 mdesc[i].base = mdesc[i-1].base + mdesc[i-1].size;
494 mdesc[i].size = heaptop - mdesc[i].base;
495 }
496
497 /* end of PMON data to start of kernel -- probably zero .. */
498 if (heaptop != CPHYSADDR((u32)_text)) {
499 i++; /* 2 */
500 mdesc[i].type = BOOT_MEM_RAM;
501 mdesc[i].base = heaptop;
502 mdesc[i].size = CPHYSADDR((u32)_text) - mdesc[i].base;
503 }
504
505 /* kernel proper */
506 i++; /* 3 */
507 mdesc[i].type = BOOT_MEM_RESERVED;
508 mdesc[i].base = CPHYSADDR((u32)_text);
509#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
510 if (get_ramroot(&ramroot_start, &ramroot_size)) {
511 /*
512 * Rootfs in RAM -- follows kernel
513 * Combine rootfs image with kernel block so a
514 * page (4k) isn't wasted between memory blocks
515 */
516 mdesc[i].size = CPHYSADDR(PAGE_ALIGN(
517 (u32)ramroot_start + ramroot_size)) - mdesc[i].base;
518 } else
519#endif
520 mdesc[i].size = CPHYSADDR(PAGE_ALIGN(
521 (u32)_end)) - mdesc[i].base;
522
523 /* Remainder of RAM -- under memsize */
524 i++; /* 5 */
525 mdesc[i].type = yamon_free;
526 mdesc[i].base = mdesc[i-1].base + mdesc[i-1].size;
527 mdesc[i].size = memsize - mdesc[i].base;
528
529 return &mdesc[0];
530}
531
532/* rootfs functions */
533#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
534bool get_ramroot(void **start, unsigned long *size)
535{
536 extern char _end[];
537
538 /* Check for start following the end of the kernel */
539 void *check_start = (void *)_end;
540
541 /* Check for supported rootfs types */
542#ifdef CONFIG_CRAMFS
543 if (*(__u32 *)check_start == CRAMFS_MAGIC) {
544 /* Get CRAMFS size */
545 *start = check_start;
546 *size = PAGE_ALIGN(((struct cramfs_super *)
547 check_start)->size);
548
549 return true;
550 }
551#endif
552#ifdef CONFIG_SQUASHFS
553 if (*((unsigned int *)check_start) == SQUASHFS_MAGIC) {
554 /* Get SQUASHFS size */
555 *start = check_start;
556 *size = PAGE_ALIGN(((struct squashfs_super_block *)
557 check_start)->bytes_used);
558
559 return true;
560 }
561#endif
562
563 return false;
564}
565EXPORT_SYMBOL(get_ramroot);
566#endif
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
new file mode 100644
index 000000000000..8f69b789be90
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
@@ -0,0 +1,256 @@
1/*
2 * The generic setup file for PMC-Sierra MSP processors
3 *
4 * Copyright 2005-2007 PMC-Sierra, Inc,
5 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <asm/bootinfo.h>
14#include <asm/cacheflush.h>
15#include <asm/r4kcache.h>
16#include <asm/reboot.h>
17#include <asm/time.h>
18
19#include <msp_prom.h>
20#include <msp_regs.h>
21
22#if defined(CONFIG_PMC_MSP7120_GW)
23#include <msp_regops.h>
24#include <msp_gpio.h>
25#define MSP_BOARD_RESET_GPIO 9
26#endif
27
28extern void msp_timer_init(void);
29extern void msp_serial_setup(void);
30extern void pmctwiled_setup(void);
31
32#if defined(CONFIG_PMC_MSP7120_EVAL) || \
33 defined(CONFIG_PMC_MSP7120_GW) || \
34 defined(CONFIG_PMC_MSP7120_FPGA)
35/*
36 * Performs the reset for MSP7120-based boards
37 */
38void msp7120_reset(void)
39{
40 void *start, *end, *iptr;
41 register int i;
42
43 /* Diasble all interrupts */
44 local_irq_disable();
45#ifdef CONFIG_SYS_SUPPORTS_MULTITHREADING
46 dvpe();
47#endif
48
49 /* Cache the reset code of this function */
50 __asm__ __volatile__ (
51 " .set push \n"
52 " .set mips3 \n"
53 " la %0,startpoint \n"
54 " la %1,endpoint \n"
55 " .set pop \n"
56 : "=r" (start), "=r" (end)
57 :
58 );
59
60 for (iptr = (void *)((unsigned int)start & ~(L1_CACHE_BYTES - 1));
61 iptr < end; iptr += L1_CACHE_BYTES)
62 cache_op(Fill, iptr);
63
64 __asm__ __volatile__ (
65 "startpoint: \n"
66 );
67
68 /* Put the DDRC into self-refresh mode */
69 DDRC_INDIRECT_WRITE(DDRC_CTL(10), 0xb, 1 << 16);
70
71 /*
72 * IMPORTANT!
73 * DO NOT do anything from here on out that might even
74 * think about fetching from RAM - i.e., don't call any
75 * non-inlined functions, and be VERY sure that any inline
76 * functions you do call do NOT access any sort of RAM
77 * anywhere!
78 */
79
80 /* Wait a bit for the DDRC to settle */
81 for (i = 0; i < 100000000; i++);
82
83#if defined(CONFIG_PMC_MSP7120_GW)
84 /*
85 * Set GPIO 9 HI, (tied to board reset logic)
86 * GPIO 9 is the 4th GPIO of register 3
87 *
88 * NOTE: We cannot use the higher-level msp_gpio_mode()/out()
89 * as GPIO char driver may not be enabled and it would look up
90 * data inRAM!
91 */
92 set_value_reg32(GPIO_CFG3_REG,
93 basic_mode_mask(MSP_BOARD_RESET_GPIO),
94 basic_mode(MSP_GPIO_OUTPUT, MSP_BOARD_RESET_GPIO));
95 set_reg32(GPIO_DATA3_REG,
96 basic_data_mask(MSP_BOARD_RESET_GPIO));
97
98 /*
99 * In case GPIO9 doesn't reset the board (jumper configurable!)
100 * fallback to device reset below.
101 */
102#endif
103 /* Set bit 1 of the MSP7120 reset register */
104 *RST_SET_REG = 0x00000001;
105
106 __asm__ __volatile__ (
107 "endpoint: \n"
108 );
109}
110#endif
111
112void msp_restart(char *command)
113{
114 printk(KERN_WARNING "Now rebooting .......\n");
115
116#if defined(CONFIG_PMC_MSP7120_EVAL) || \
117 defined(CONFIG_PMC_MSP7120_GW) || \
118 defined(CONFIG_PMC_MSP7120_FPGA)
119 msp7120_reset();
120#else
121 /* No chip-specific reset code, just jump to the ROM reset vector */
122 set_c0_status(ST0_BEV | ST0_ERL);
123 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
124 flush_cache_all();
125 write_c0_wired(0);
126
127 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
128#endif
129}
130
131void msp_halt(void)
132{
133 printk(KERN_WARNING "\n** You can safely turn off the power\n");
134 while (1)
135 /* If possible call official function to get CPU WARs */
136 if (cpu_wait)
137 (*cpu_wait)();
138 else
139 __asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0");
140}
141
142void msp_power_off(void)
143{
144 msp_halt();
145}
146
147void __init plat_mem_setup(void)
148{
149 _machine_restart = msp_restart;
150 _machine_halt = msp_halt;
151 pm_power_off = msp_power_off;
152
153 board_time_init = msp_timer_init;
154}
155
156void __init prom_init(void)
157{
158 unsigned long family;
159 unsigned long revision;
160
161 prom_argc = fw_arg0;
162 prom_argv = (char **)fw_arg1;
163 prom_envp = (char **)fw_arg2;
164
165 /*
166 * Someday we can use this with PMON2000 to get a
167 * platform call prom routines for output etc. without
168 * having to use grody hacks. For now it's unused.
169 *
170 * struct callvectors *cv = (struct callvectors *) fw_arg3;
171 */
172 family = identify_family();
173 revision = identify_revision();
174
175 switch (family) {
176 case FAMILY_FPGA:
177 if (FPGA_IS_MSP4200(revision)) {
178 /* Old-style revision ID */
179 mips_machgroup = MACH_GROUP_MSP;
180 mips_machtype = MACH_MSP4200_FPGA;
181 } else {
182 mips_machgroup = MACH_GROUP_MSP;
183 mips_machtype = MACH_MSP_OTHER;
184 }
185 break;
186
187 case FAMILY_MSP4200:
188 mips_machgroup = MACH_GROUP_MSP;
189#if defined(CONFIG_PMC_MSP4200_EVAL)
190 mips_machtype = MACH_MSP4200_EVAL;
191#elif defined(CONFIG_PMC_MSP4200_GW)
192 mips_machtype = MACH_MSP4200_GW;
193#else
194 mips_machtype = MACH_MSP_OTHER;
195#endif
196 break;
197
198 case FAMILY_MSP4200_FPGA:
199 mips_machgroup = MACH_GROUP_MSP;
200 mips_machtype = MACH_MSP4200_FPGA;
201 break;
202
203 case FAMILY_MSP7100:
204 mips_machgroup = MACH_GROUP_MSP;
205#if defined(CONFIG_PMC_MSP7120_EVAL)
206 mips_machtype = MACH_MSP7120_EVAL;
207#elif defined(CONFIG_PMC_MSP7120_GW)
208 mips_machtype = MACH_MSP7120_GW;
209#else
210 mips_machtype = MACH_MSP_OTHER;
211#endif
212 break;
213
214 case FAMILY_MSP7100_FPGA:
215 mips_machgroup = MACH_GROUP_MSP;
216 mips_machtype = MACH_MSP7120_FPGA;
217 break;
218
219 default:
220 /* we don't recognize the machine */
221 mips_machgroup = MACH_GROUP_UNKNOWN;
222 mips_machtype = MACH_UNKNOWN;
223 break;
224 }
225
226 /* make sure we have the right initialization routine - sanity */
227 if (mips_machgroup != MACH_GROUP_MSP) {
228 ppfinit("Unknown machine group in a "
229 "MSP initialization routine\n");
230 panic("***Bogosity factor five***, exiting\n");
231 }
232
233 prom_init_cmdline();
234
235 prom_meminit();
236
237 /*
238 * Sub-system setup follows.
239 * Setup functions can either be called here or using the
240 * subsys_initcall mechanism (i.e. see msp_pci_setup). The
241 * order in which they are called can be changed by using the
242 * link order in arch/mips/pmc-sierra/msp71xx/Makefile.
243 *
244 * NOTE: Please keep sub-system specific initialization code
245 * in separate specific files.
246 */
247 msp_serial_setup();
248
249#ifdef CONFIG_PMCTWILED
250 /*
251 * Setup LED states before the subsys_initcall loads other
252 * dependant drivers/modules.
253 */
254 pmctwiled_setup();
255#endif
256}
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c
new file mode 100644
index 000000000000..2a2beac5a4f8
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c
@@ -0,0 +1,94 @@
1/*
2 * Setting up the clock on MSP SOCs. No RTC typically.
3 *
4 * Carsten Langgaard, carstenl@mips.com
5 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 */
24
25#include <linux/init.h>
26#include <linux/kernel_stat.h>
27#include <linux/sched.h>
28#include <linux/spinlock.h>
29#include <linux/module.h>
30#include <linux/ptrace.h>
31
32#include <asm/mipsregs.h>
33#include <asm/time.h>
34
35#include <msp_prom.h>
36#include <msp_int.h>
37#include <msp_regs.h>
38
39void __init msp_timer_init(void)
40{
41 char *endp, *s;
42 unsigned long cpu_rate = 0;
43
44 if (cpu_rate == 0) {
45 s = prom_getenv("clkfreqhz");
46 cpu_rate = simple_strtoul(s, &endp, 10);
47 if (endp != NULL && *endp != 0) {
48 printk(KERN_ERR
49 "Clock rate in Hz parse error: %s\n", s);
50 cpu_rate = 0;
51 }
52 }
53
54 if (cpu_rate == 0) {
55 s = prom_getenv("clkfreq");
56 cpu_rate = 1000 * simple_strtoul(s, &endp, 10);
57 if (endp != NULL && *endp != 0) {
58 printk(KERN_ERR
59 "Clock rate in MHz parse error: %s\n", s);
60 cpu_rate = 0;
61 }
62 }
63
64 if (cpu_rate == 0) {
65#if defined(CONFIG_PMC_MSP7120_EVAL) \
66 || defined(CONFIG_PMC_MSP7120_GW)
67 cpu_rate = 400000000;
68#elif defined(CONFIG_PMC_MSP7120_FPGA)
69 cpu_rate = 25000000;
70#else
71 cpu_rate = 150000000;
72#endif
73 printk(KERN_ERR
74 "Failed to determine CPU clock rate, "
75 "assuming %ld hz ...\n", cpu_rate);
76 }
77
78 printk(KERN_WARNING "Clock rate set to %ld\n", cpu_rate);
79
80 /* timer frequency is 1/2 clock rate */
81 mips_hpt_frequency = cpu_rate/2;
82}
83
84
85void __init plat_timer_setup(struct irqaction *irq)
86{
87#ifdef CONFIG_IRQ_MSP_CIC
88 /* we are using the vpe0 counter for timer interrupts */
89 setup_irq(MSP_INT_VPE0_TIMER, irq);
90#else
91 /* we are using the mips counter for timer interrupts */
92 setup_irq(MSP_INT_TIMER, irq);
93#endif
94}
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_usb.c b/arch/mips/pmc-sierra/msp71xx/msp_usb.c
new file mode 100644
index 000000000000..21f9c70b6923
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_usb.c
@@ -0,0 +1,150 @@
1/*
2 * The setup file for USB related hardware on PMC-Sierra MSP processors.
3 *
4 * Copyright 2006-2007 PMC-Sierra, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/dma-mapping.h>
28#include <linux/init.h>
29#include <linux/ioport.h>
30#include <linux/platform_device.h>
31
32#include <asm/mipsregs.h>
33
34#include <msp_regs.h>
35#include <msp_int.h>
36#include <msp_prom.h>
37
38#if defined(CONFIG_USB_EHCI_HCD)
39static struct resource msp_usbhost_resources [] = {
40 [0] = {
41 .start = MSP_USB_BASE_START,
42 .end = MSP_USB_BASE_END,
43 .flags = IORESOURCE_MEM,
44 },
45 [1] = {
46 .start = MSP_INT_USB,
47 .end = MSP_INT_USB,
48 .flags = IORESOURCE_IRQ,
49 },
50};
51
52static u64 msp_usbhost_dma_mask = DMA_32BIT_MASK;
53
54static struct platform_device msp_usbhost_device = {
55 .name = "pmcmsp-ehci",
56 .id = 0,
57 .dev = {
58 .dma_mask = &msp_usbhost_dma_mask,
59 .coherent_dma_mask = DMA_32BIT_MASK,
60 },
61 .num_resources = ARRAY_SIZE (msp_usbhost_resources),
62 .resource = msp_usbhost_resources,
63};
64#endif /* CONFIG_USB_EHCI_HCD */
65
66#if defined(CONFIG_USB_GADGET)
67static struct resource msp_usbdev_resources [] = {
68 [0] = {
69 .start = MSP_USB_BASE,
70 .end = MSP_USB_BASE_END,
71 .flags = IORESOURCE_MEM,
72 },
73 [1] = {
74 .start = MSP_INT_USB,
75 .end = MSP_INT_USB,
76 .flags = IORESOURCE_IRQ,
77 },
78};
79
80static u64 msp_usbdev_dma_mask = DMA_32BIT_MASK;
81
82static struct platform_device msp_usbdev_device = {
83 .name = "msp71xx_udc",
84 .id = 0,
85 .dev = {
86 .dma_mask = &msp_usbdev_dma_mask,
87 .coherent_dma_mask = DMA_32BIT_MASK,
88 },
89 .num_resources = ARRAY_SIZE (msp_usbdev_resources),
90 .resource = msp_usbdev_resources,
91};
92#endif /* CONFIG_USB_GADGET */
93
94#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET)
95static struct platform_device *msp_devs[1];
96#endif
97
98
99static int __init msp_usb_setup(void)
100{
101#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET)
102 char *strp;
103 char envstr[32];
104 unsigned int val = 0;
105 int result = 0;
106
107 /*
108 * construct environment name usbmode
109 * set usbmode <host/device> as pmon environment var
110 */
111 snprintf((char *)&envstr[0], sizeof(envstr), "usbmode");
112
113#if defined(CONFIG_USB_EHCI_HCD)
114 /* default to host mode */
115 val = 1;
116#endif
117
118 /* get environment string */
119 strp = prom_getenv((char *)&envstr[0]);
120 if (strp) {
121 if (!strcmp(strp, "device"))
122 val = 0;
123 }
124
125 if (val) {
126#if defined(CONFIG_USB_EHCI_HCD)
127 /* get host mode device */
128 msp_devs[0] = &msp_usbhost_device;
129 ppfinit("platform add USB HOST done %s.\n",
130 msp_devs[0]->name);
131
132 result = platform_add_devices(msp_devs, ARRAY_SIZE (msp_devs));
133#endif /* CONFIG_USB_EHCI_HCD */
134 }
135#if defined(CONFIG_USB_GADGET)
136 else {
137 /* get device mode structure */
138 msp_devs[0] = &msp_usbdev_device;
139 ppfinit("platform add USB DEVICE done %s.\n",
140 msp_devs[0]->name);
141
142 result = platform_add_devices(msp_devs, ARRAY_SIZE (msp_devs));
143 }
144#endif /* CONFIG_USB_GADGET */
145#endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */
146
147 return result;
148}
149
150subsys_initcall(msp_usb_setup);
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h
new file mode 100644
index 000000000000..c84bcf9570b1
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h
@@ -0,0 +1,151 @@
1/*
2 * Defines for the MSP interrupt controller.
3 *
4 * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
5 * Author: Carsten Langgaard, carstenl@mips.com
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 */
24
25#ifndef _MSP_CIC_INT_H
26#define _MSP_CIC_INT_H
27
28/*
29 * The PMC-Sierra CIC interrupts are all centrally managed by the
30 * CIC sub-system.
31 * We attempt to keep the interrupt numbers as consistent as possible
32 * across all of the MSP devices, but some differences will creep in ...
33 * The interrupts which are directly forwarded to the MIPS core interrupts
34 * are assigned interrupts in the range 0-7, interrupts cascaded through
35 * the CIC are assigned interrupts 8-39. The cascade occurs on C_IRQ4
36 * (MSP_INT_CIC). Currently we don't really distinguish between VPE1
37 * and VPE0 (or thread contexts for that matter). Will have to fix.
38 * The PER interrupts are assigned interrupts in the range 40-71.
39*/
40
41
42/*
43 * IRQs directly forwarded to the CPU
44 */
45#define MSP_MIPS_INTBASE 0
46#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */
47#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */
48#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */
49#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */
50#define MSP_INT_USB 4 /* IRQ for USB, C_IRQ2 */
51#define MSP_INT_SAR 5 /* IRQ for ADSL2+ SAR, C_IRQ3 */
52#define MSP_INT_CIC 6 /* IRQ for CIC block, C_IRQ4 */
53#define MSP_INT_SEC 7 /* IRQ for Sec engine, C_IRQ5 */
54
55/*
56 * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
57 * These defines should be tied to the register definitions for the CIC
58 * interrupt routine. For now, just use hard-coded values.
59 */
60#define MSP_CIC_INTBASE (MSP_MIPS_INTBASE + 8)
61#define MSP_INT_EXT0 (MSP_CIC_INTBASE + 0)
62 /* External interrupt 0 */
63#define MSP_INT_EXT1 (MSP_CIC_INTBASE + 1)
64 /* External interrupt 1 */
65#define MSP_INT_EXT2 (MSP_CIC_INTBASE + 2)
66 /* External interrupt 2 */
67#define MSP_INT_EXT3 (MSP_CIC_INTBASE + 3)
68 /* External interrupt 3 */
69#define MSP_INT_CPUIF (MSP_CIC_INTBASE + 4)
70 /* CPU interface interrupt */
71#define MSP_INT_EXT4 (MSP_CIC_INTBASE + 5)
72 /* External interrupt 4 */
73#define MSP_INT_CIC_USB (MSP_CIC_INTBASE + 6)
74 /* Cascaded IRQ for USB */
75#define MSP_INT_MBOX (MSP_CIC_INTBASE + 7)
76 /* Sec engine mailbox IRQ */
77#define MSP_INT_EXT5 (MSP_CIC_INTBASE + 8)
78 /* External interrupt 5 */
79#define MSP_INT_TDM (MSP_CIC_INTBASE + 9)
80 /* TDM interrupt */
81#define MSP_INT_CIC_MAC0 (MSP_CIC_INTBASE + 10)
82 /* Cascaded IRQ for MAC 0 */
83#define MSP_INT_CIC_MAC1 (MSP_CIC_INTBASE + 11)
84 /* Cascaded IRQ for MAC 1 */
85#define MSP_INT_CIC_SEC (MSP_CIC_INTBASE + 12)
86 /* Cascaded IRQ for sec engine */
87#define MSP_INT_PER (MSP_CIC_INTBASE + 13)
88 /* Peripheral interrupt */
89#define MSP_INT_TIMER0 (MSP_CIC_INTBASE + 14)
90 /* SLP timer 0 */
91#define MSP_INT_TIMER1 (MSP_CIC_INTBASE + 15)
92 /* SLP timer 1 */
93#define MSP_INT_TIMER2 (MSP_CIC_INTBASE + 16)
94 /* SLP timer 2 */
95#define MSP_INT_VPE0_TIMER (MSP_CIC_INTBASE + 17)
96 /* VPE0 MIPS timer */
97#define MSP_INT_BLKCP (MSP_CIC_INTBASE + 18)
98 /* Block Copy */
99#define MSP_INT_UART0 (MSP_CIC_INTBASE + 19)
100 /* UART 0 */
101#define MSP_INT_PCI (MSP_CIC_INTBASE + 20)
102 /* PCI subsystem */
103#define MSP_INT_EXT6 (MSP_CIC_INTBASE + 21)
104 /* External interrupt 5 */
105#define MSP_INT_PCI_MSI (MSP_CIC_INTBASE + 22)
106 /* PCI Message Signal */
107#define MSP_INT_CIC_SAR (MSP_CIC_INTBASE + 23)
108 /* Cascaded ADSL2+ SAR IRQ */
109#define MSP_INT_DSL (MSP_CIC_INTBASE + 24)
110 /* ADSL2+ IRQ */
111#define MSP_INT_CIC_ERR (MSP_CIC_INTBASE + 25)
112 /* SLP error condition */
113#define MSP_INT_VPE1_TIMER (MSP_CIC_INTBASE + 26)
114 /* VPE1 MIPS timer */
115#define MSP_INT_VPE0_PC (MSP_CIC_INTBASE + 27)
116 /* VPE0 Performance counter */
117#define MSP_INT_VPE1_PC (MSP_CIC_INTBASE + 28)
118 /* VPE1 Performance counter */
119#define MSP_INT_EXT7 (MSP_CIC_INTBASE + 29)
120 /* External interrupt 5 */
121#define MSP_INT_VPE0_SW (MSP_CIC_INTBASE + 30)
122 /* VPE0 Software interrupt */
123#define MSP_INT_VPE1_SW (MSP_CIC_INTBASE + 31)
124 /* VPE0 Software interrupt */
125
126/*
127 * IRQs cascaded on CIC PER interrupt (MSP_INT_PER)
128 */
129#define MSP_PER_INTBASE (MSP_CIC_INTBASE + 32)
130/* Reserved 0-1 */
131#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)
132 /* UART 1 */
133/* Reserved 3-5 */
134#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)
135 /* 2-wire */
136#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)
137 /* Peripheral timer block out 0 */
138#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)
139 /* Peripheral timer block out 1 */
140/* Reserved 9 */
141#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)
142 /* SPI RX complete */
143#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)
144 /* SPI TX complete */
145#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)
146 /* GPIO */
147#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)
148 /* Peripheral error */
149/* Reserved 14-31 */
150
151#endif /* !_MSP_CIC_INT_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_int.h
new file mode 100644
index 000000000000..1d9f05474820
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_int.h
@@ -0,0 +1,43 @@
1/*
2 * Defines for the MSP interrupt handlers.
3 *
4 * Copyright (C) 2005, PMC-Sierra, Inc. All rights reserved.
5 * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 */
24
25#ifndef _MSP_INT_H
26#define _MSP_INT_H
27
28/*
29 * The PMC-Sierra MSP product line has at least two different interrupt
30 * controllers, the SLP register based scheme and the CIC interrupt
31 * controller block mechanism. This file distinguishes between them
32 * so that devices see a uniform interface.
33 */
34
35#if defined(CONFIG_IRQ_MSP_SLP)
36 #include "msp_slp_int.h"
37#elif defined(CONFIG_IRQ_MSP_CIC)
38 #include "msp_cic_int.h"
39#else
40 #error "What sort of interrupt controller does *your* MSP have?"
41#endif
42
43#endif /* !_MSP_INT_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h b/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h
new file mode 100644
index 000000000000..14ca7dc382a8
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h
@@ -0,0 +1,176 @@
1/*
2 * MIPS boards bootprom interface for the Linux kernel.
3 *
4 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
5 * Author: Carsten Langgaard, carstenl@mips.com
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 */
24
25#ifndef _ASM_MSP_PROM_H
26#define _ASM_MSP_PROM_H
27
28#include <linux/types.h>
29
30#define DEVICEID "deviceid"
31#define FEATURES "features"
32#define PROM_ENV "prom_env"
33#define PROM_ENV_FILE "/proc/"PROM_ENV
34#define PROM_ENV_SIZE 256
35
36#define CPU_DEVID_FAMILY 0x0000ff00
37#define CPU_DEVID_REVISION 0x000000ff
38
39#define FPGA_IS_POLO(revision) \
40 (((revision >= 0xb0) && (revision < 0xd0)))
41#define FPGA_IS_5000(revision) \
42 ((revision >= 0x80) && (revision <= 0x90))
43#define FPGA_IS_ZEUS(revision) ((revision < 0x7f))
44#define FPGA_IS_DUET(revision) \
45 (((revision >= 0xa0) && (revision < 0xb0)))
46#define FPGA_IS_MSP4200(revision) ((revision >= 0xd0))
47#define FPGA_IS_MSP7100(revision) ((revision >= 0xd0))
48
49#define MACHINE_TYPE_POLO "POLO"
50#define MACHINE_TYPE_DUET "DUET"
51#define MACHINE_TYPE_ZEUS "ZEUS"
52#define MACHINE_TYPE_MSP2000REVB "MSP2000REVB"
53#define MACHINE_TYPE_MSP5000 "MSP5000"
54#define MACHINE_TYPE_MSP4200 "MSP4200"
55#define MACHINE_TYPE_MSP7120 "MSP7120"
56#define MACHINE_TYPE_MSP7130 "MSP7130"
57#define MACHINE_TYPE_OTHER "OTHER"
58
59#define MACHINE_TYPE_POLO_FPGA "POLO-FPGA"
60#define MACHINE_TYPE_DUET_FPGA "DUET-FPGA"
61#define MACHINE_TYPE_ZEUS_FPGA "ZEUS_FPGA"
62#define MACHINE_TYPE_MSP2000REVB_FPGA "MSP2000REVB-FPGA"
63#define MACHINE_TYPE_MSP5000_FPGA "MSP5000-FPGA"
64#define MACHINE_TYPE_MSP4200_FPGA "MSP4200-FPGA"
65#define MACHINE_TYPE_MSP7100_FPGA "MSP7100-FPGA"
66#define MACHINE_TYPE_OTHER_FPGA "OTHER-FPGA"
67
68/* Device Family definitions */
69#define FAMILY_FPGA 0x0000
70#define FAMILY_ZEUS 0x1000
71#define FAMILY_POLO 0x2000
72#define FAMILY_DUET 0x4000
73#define FAMILY_TRIAD 0x5000
74#define FAMILY_MSP4200 0x4200
75#define FAMILY_MSP4200_FPGA 0x4f00
76#define FAMILY_MSP7100 0x7100
77#define FAMILY_MSP7100_FPGA 0x7f00
78
79/* Device Type definitions */
80#define TYPE_MSP7120 0x7120
81#define TYPE_MSP7130 0x7130
82
83#define ENET_KEY 'E'
84#define ENETTXD_KEY 'e'
85#define PCI_KEY 'P'
86#define PCIMUX_KEY 'p'
87#define SEC_KEY 'S'
88#define SPAD_KEY 'D'
89#define TDM_KEY 'T'
90#define ZSP_KEY 'Z'
91
92#define FEATURE_NOEXIST '-'
93#define FEATURE_EXIST '+'
94
95#define ENET_MII 'M'
96#define ENET_RMII 'R'
97
98#define ENETTXD_FALLING 'F'
99#define ENETTXD_RISING 'R'
100
101#define PCI_HOST 'H'
102#define PCI_PERIPHERAL 'P'
103
104#define PCIMUX_FULL 'F'
105#define PCIMUX_SINGLE 'S'
106
107#define SEC_DUET 'D'
108#define SEC_POLO 'P'
109#define SEC_SLOW 'S'
110#define SEC_TRIAD 'T'
111
112#define SPAD_POLO 'P'
113
114#define TDM_DUET 'D' /* DUET TDMs might exist */
115#define TDM_POLO 'P' /* POLO TDMs might exist */
116#define TDM_TRIAD 'T' /* TRIAD TDMs might exist */
117
118#define ZSP_DUET 'D' /* one DUET zsp engine */
119#define ZSP_TRIAD 'T' /* two TRIAD zsp engines */
120
121extern char *prom_getcmdline(void);
122extern char *prom_getenv(char *name);
123extern void prom_init_cmdline(void);
124extern void prom_meminit(void);
125extern void prom_fixup_mem_map(unsigned long start_mem,
126 unsigned long end_mem);
127
128#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
129extern bool get_ramroot(void **start, unsigned long *size);
130#endif
131
132extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr);
133extern unsigned long get_deviceid(void);
134extern char identify_enet(unsigned long interface_num);
135extern char identify_enetTxD(unsigned long interface_num);
136extern char identify_pci(void);
137extern char identify_sec(void);
138extern char identify_spad(void);
139extern char identify_sec(void);
140extern char identify_tdm(void);
141extern char identify_zsp(void);
142extern unsigned long identify_family(void);
143extern unsigned long identify_revision(void);
144
145/*
146 * The following macro calls prom_printf and puts the format string
147 * into an init section so it can be reclaimed.
148 */
149#define ppfinit(f, x...) \
150 do { \
151 static char _f[] __initdata = KERN_INFO f; \
152 printk(_f, ## x); \
153 } while (0)
154
155/* Memory descriptor management. */
156#define PROM_MAX_PMEMBLOCKS 7 /* 6 used */
157
158enum yamon_memtypes {
159 yamon_dontuse,
160 yamon_prom,
161 yamon_free,
162};
163
164struct prom_pmemblock {
165 unsigned long base; /* Within KSEG0. */
166 unsigned int size; /* In bytes. */
167 unsigned int type; /* free or prom memory */
168};
169
170extern int prom_argc;
171extern char **prom_argv;
172extern char **prom_envp;
173extern int *prom_vec;
174extern struct prom_pmemblock *prom_getmdesc(void);
175
176#endif /* !_ASM_MSP_PROM_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h
new file mode 100644
index 000000000000..60a5a38dd5b2
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h
@@ -0,0 +1,236 @@
1/*
2 * SMP/VPE-safe functions to access "registers" (see note).
3 *
4 * NOTES:
5* - These macros use ll/sc instructions, so it is your responsibility to
6 * ensure these are available on your platform before including this file.
7 * - The MIPS32 spec states that ll/sc results are undefined for uncached
8 * accesses. This means they can't be used on HW registers accessed
9 * through kseg1. Code which requires these macros for this purpose must
10 * front-end the registers with cached memory "registers" and have a single
11 * thread update the actual HW registers.
12 * - A maximum of 2k of code can be inserted between ll and sc. Every
13 * memory accesses between the instructions will increase the chance of
14 * sc failing and having to loop.
15 * - When using custom_read_reg32/custom_write_reg32 only perform the
16 * necessary logical operations on the register value in between these
17 * two calls. All other logic should be performed before the first call.
18 * - There is a bug on the R10000 chips which has a workaround. If you
19 * are affected by this bug, make sure to define the symbol 'R10000_LLSC_WAR'
20 * to be non-zero. If you are using this header from within linux, you may
21 * include <asm/war.h> before including this file to have this defined
22 * appropriately for you.
23 *
24 * Copyright 2005-2007 PMC-Sierra, Inc.
25 *
26 * This program is free software; you can redistribute it and/or modify it
27 * under the terms of the GNU General Public License as published by the
28 * Free Software Foundation; either version 2 of the License, or (at your
29 * option) any later version.
30 *
31 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
32 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
33 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
34 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
40 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * You should have received a copy of the GNU General Public License along
43 * with this program; if not, write to the Free Software Foundation, Inc., 675
44 * Mass Ave, Cambridge, MA 02139, USA.
45 */
46
47#ifndef __ASM_REGOPS_H__
48#define __ASM_REGOPS_H__
49
50#include <linux/types.h>
51
52#include <asm/war.h>
53
54#ifndef R10000_LLSC_WAR
55#define R10000_LLSC_WAR 0
56#endif
57
58#if R10000_LLSC_WAR == 1
59#define __beqz "beqzl "
60#else
61#define __beqz "beqz "
62#endif
63
64#ifndef _LINUX_TYPES_H
65typedef unsigned int u32;
66#endif
67
68/*
69 * Sets all the masked bits to the corresponding value bits
70 */
71static inline void set_value_reg32(volatile u32 *const addr,
72 u32 const mask,
73 u32 const value)
74{
75 u32 temp;
76
77 __asm__ __volatile__(
78 " .set push \n"
79 " .set mips3 \n"
80 "1: ll %0, %1 # set_value_reg32 \n"
81 " and %0, %2 \n"
82 " or %0, %3 \n"
83 " sc %0, %1 \n"
84 " "__beqz"%0, 1b \n"
85 " nop \n"
86 " .set pop \n"
87 : "=&r" (temp), "=m" (*addr)
88 : "ir" (~mask), "ir" (value), "m" (*addr));
89}
90
91/*
92 * Sets all the masked bits to '1'
93 */
94static inline void set_reg32(volatile u32 *const addr,
95 u32 const mask)
96{
97 u32 temp;
98
99 __asm__ __volatile__(
100 " .set push \n"
101 " .set mips3 \n"
102 "1: ll %0, %1 # set_reg32 \n"
103 " or %0, %2 \n"
104 " sc %0, %1 \n"
105 " "__beqz"%0, 1b \n"
106 " nop \n"
107 " .set pop \n"
108 : "=&r" (temp), "=m" (*addr)
109 : "ir" (mask), "m" (*addr));
110}
111
112/*
113 * Sets all the masked bits to '0'
114 */
115static inline void clear_reg32(volatile u32 *const addr,
116 u32 const mask)
117{
118 u32 temp;
119
120 __asm__ __volatile__(
121 " .set push \n"
122 " .set mips3 \n"
123 "1: ll %0, %1 # clear_reg32 \n"
124 " and %0, %2 \n"
125 " sc %0, %1 \n"
126 " "__beqz"%0, 1b \n"
127 " nop \n"
128 " .set pop \n"
129 : "=&r" (temp), "=m" (*addr)
130 : "ir" (~mask), "m" (*addr));
131}
132
133/*
134 * Toggles all masked bits from '0' to '1' and '1' to '0'
135 */
136static inline void toggle_reg32(volatile u32 *const addr,
137 u32 const mask)
138{
139 u32 temp;
140
141 __asm__ __volatile__(
142 " .set push \n"
143 " .set mips3 \n"
144 "1: ll %0, %1 # toggle_reg32 \n"
145 " xor %0, %2 \n"
146 " sc %0, %1 \n"
147 " "__beqz"%0, 1b \n"
148 " nop \n"
149 " .set pop \n"
150 : "=&r" (temp), "=m" (*addr)
151 : "ir" (mask), "m" (*addr));
152}
153
154/*
155 * Read all masked bits others are returned as '0'
156 */
157static inline u32 read_reg32(volatile u32 *const addr,
158 u32 const mask)
159{
160 u32 temp;
161
162 __asm__ __volatile__(
163 " .set push \n"
164 " .set noreorder \n"
165 " lw %0, %1 # read \n"
166 " and %0, %2 # mask \n"
167 " .set pop \n"
168 : "=&r" (temp)
169 : "m" (*addr), "ir" (mask));
170
171 return temp;
172}
173
174/*
175 * blocking_read_reg32 - Read address with blocking load
176 *
177 * Uncached writes need to be read back to ensure they reach RAM.
178 * The returned value must be 'used' to prevent from becoming a
179 * non-blocking load.
180 */
181static inline u32 blocking_read_reg32(volatile u32 *const addr)
182{
183 u32 temp;
184
185 __asm__ __volatile__(
186 " .set push \n"
187 " .set noreorder \n"
188 " lw %0, %1 # read \n"
189 " move %0, %0 # block \n"
190 " .set pop \n"
191 : "=&r" (temp)
192 : "m" (*addr));
193
194 return temp;
195}
196
197/*
198 * For special strange cases only:
199 *
200 * If you need custom processing within a ll/sc loop, use the following macros
201 * VERY CAREFULLY:
202 *
203 * u32 tmp; <-- Define a variable to hold the data
204 *
205 * custom_read_reg32(address, tmp); <-- Reads the address and put the value
206 * in the 'tmp' variable given
207 *
208 * From here on out, you are (basicly) atomic, so don't do anything too
209 * fancy!
210 * Also, this code may loop if the end of this block fails to write
211 * everything back safely due do the other CPU, so do NOT do anything
212 * with side-effects!
213 *
214 * custom_write_reg32(address, tmp); <-- Writes back 'tmp' safely.
215 */
216#define custom_read_reg32(address, tmp) \
217 __asm__ __volatile__( \
218 " .set push \n" \
219 " .set mips3 \n" \
220 "1: ll %0, %1 #custom_read_reg32 \n" \
221 " .set pop \n" \
222 : "=r" (tmp), "=m" (*address) \
223 : "m" (*address))
224
225#define custom_write_reg32(address, tmp) \
226 __asm__ __volatile__( \
227 " .set push \n" \
228 " .set mips3 \n" \
229 " sc %0, %1 #custom_write_reg32 \n" \
230 " "__beqz"%0, 1b \n" \
231 " nop \n" \
232 " .set pop \n" \
233 : "=&r" (tmp), "=m" (*address) \
234 : "0" (tmp), "m" (*address))
235
236#endif /* __ASM_REGOPS_H__ */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
new file mode 100644
index 000000000000..0b56f55206c6
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
@@ -0,0 +1,667 @@
1/*
2 * Defines for the address space, registers and register configuration
3 * (bit masks, access macros etc) for the PMC-Sierra line of MSP products.
4 * This file contains addess maps for all the devices in the line of
5 * products but only has register definitions and configuration masks for
6 * registers which aren't definitely associated with any device. Things
7 * like clock settings, reset access, the ELB etc. Individual device
8 * drivers will reference the appropriate XXX_BASE value defined here
9 * and have individual registers offset from that.
10 *
11 * Copyright (C) 2005-2007 PMC-Sierra, Inc. All rights reserved.
12 * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
13 *
14 * ########################################################################
15 *
16 * This program is free software; you can distribute it and/or modify it
17 * under the terms of the GNU General Public License (Version 2) as
18 * published by the Free Software Foundation.
19 *
20 * This program is distributed in the hope it will be useful, but WITHOUT
21 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 * for more details.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
28 *
29 * ########################################################################
30 */
31
32#include <asm/addrspace.h>
33#include <linux/types.h>
34
35#ifndef _ASM_MSP_REGS_H
36#define _ASM_MSP_REGS_H
37
38/*
39 ########################################################################
40 # Address space and device base definitions #
41 ########################################################################
42 */
43
44/*
45 ***************************************************************************
46 * System Logic and Peripherals (ELB, UART0, etc) device address space *
47 ***************************************************************************
48 */
49#define MSP_SLP_BASE 0x1c000000
50 /* System Logic and Peripherals */
51#define MSP_RST_BASE (MSP_SLP_BASE + 0x10)
52 /* System reset register base */
53#define MSP_RST_SIZE 0x0C /* System reset register space */
54
55#define MSP_WTIMER_BASE (MSP_SLP_BASE + 0x04C)
56 /* watchdog timer base */
57#define MSP_ITIMER_BASE (MSP_SLP_BASE + 0x054)
58 /* internal timer base */
59#define MSP_UART0_BASE (MSP_SLP_BASE + 0x100)
60 /* UART0 controller base */
61#define MSP_BCPY_CTRL_BASE (MSP_SLP_BASE + 0x120)
62 /* Block Copy controller base */
63#define MSP_BCPY_DESC_BASE (MSP_SLP_BASE + 0x160)
64 /* Block Copy descriptor base */
65
66/*
67 ***************************************************************************
68 * PCI address space *
69 ***************************************************************************
70 */
71#define MSP_PCI_BASE 0x19000000
72
73/*
74 ***************************************************************************
75 * MSbus device address space *
76 ***************************************************************************
77 */
78#define MSP_MSB_BASE 0x18000000
79 /* MSbus address start */
80#define MSP_PER_BASE (MSP_MSB_BASE + 0x400000)
81 /* Peripheral device registers */
82#define MSP_MAC0_BASE (MSP_MSB_BASE + 0x600000)
83 /* MAC A device registers */
84#define MSP_MAC1_BASE (MSP_MSB_BASE + 0x700000)
85 /* MAC B device registers */
86#define MSP_MAC_SIZE 0xE0 /* MAC register space */
87
88#define MSP_SEC_BASE (MSP_MSB_BASE + 0x800000)
89 /* Security Engine registers */
90#define MSP_MAC2_BASE (MSP_MSB_BASE + 0x900000)
91 /* MAC C device registers */
92#define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000)
93 /* ADSL2 device registers */
94#define MSP_USB_BASE (MSP_MSB_BASE + 0xB40000)
95 /* USB device registers */
96#define MSP_USB_BASE_START (MSP_MSB_BASE + 0xB40100)
97 /* USB device registers */
98#define MSP_USB_BASE_END (MSP_MSB_BASE + 0xB401FF)
99 /* USB device registers */
100#define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000)
101 /* CPU interface registers */
102
103/* Devices within the MSbus peripheral block */
104#define MSP_UART1_BASE (MSP_PER_BASE + 0x030)
105 /* UART1 controller base */
106#define MSP_SPI_BASE (MSP_PER_BASE + 0x058)
107 /* SPI/MPI control registers */
108#define MSP_TWI_BASE (MSP_PER_BASE + 0x090)
109 /* Two-wire control registers */
110#define MSP_PTIMER_BASE (MSP_PER_BASE + 0x0F0)
111 /* Programmable timer control */
112
113/*
114 ***************************************************************************
115 * Physical Memory configuration address space *
116 ***************************************************************************
117 */
118#define MSP_MEM_CFG_BASE 0x17f00000
119
120#define MSP_MEM_INDIRECT_CTL_10 0x10
121
122/*
123 * Notes:
124 * 1) The SPI registers are split into two blocks, one offset from the
125 * MSP_SPI_BASE by 0x00 and the other offset from the MSP_SPI_BASE by
126 * 0x68. The SPI driver definitions for the register must be aware
127 * of this.
128 * 2) The block copy engine register are divided into two regions, one
129 * for the control/configuration of the engine proper and one for the
130 * values of the descriptors used in the copy process. These have
131 * different base defines (CTRL_BASE vs DESC_BASE)
132 * 3) These constants are for physical addresses which means that they
133 * work correctly with "ioremap" and friends. This means that device
134 * drivers will need to remap these addresses using ioremap and perhaps
135 * the readw/writew macros. Or they could use the regptr() macro
136 * defined below, but the readw/writew calls are the correct thing.
137 * 4) The UARTs have an additional status register offset from the base
138 * address. This register isn't used in the standard 8250 driver but
139 * may be used in other software. Consult the hardware datasheet for
140 * offset details.
141 * 5) For some unknown reason the security engine (MSP_SEC_BASE) registers
142 * start at an offset of 0x84 from the base address but the block of
143 * registers before this is reserved for the security engine. The
144 * driver will have to be aware of this but it makes the register
145 * definitions line up better with the documentation.
146 */
147
148/*
149 ########################################################################
150 # System register definitions. Not associated with a specific device #
151 ########################################################################
152 */
153
154/*
155 * This macro maps the physical register number into uncached space
156 * and (for C code) casts it into a u32 pointer so it can be dereferenced
157 * Normally these would be accessed with ioremap and readX/writeX, but
158 * these are convenient for a lot of internal kernel code.
159 */
160#ifdef __ASSEMBLER__
161 #define regptr(addr) (KSEG1ADDR(addr))
162#else
163 #define regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr)))
164#endif
165
166/*
167 ***************************************************************************
168 * System Logic and Peripherals (RESET, ELB, etc) registers *
169 ***************************************************************************
170 */
171
172/* System Control register definitions */
173#define DEV_ID_REG regptr(MSP_SLP_BASE + 0x00)
174 /* Device-ID RO */
175#define FWR_ID_REG regptr(MSP_SLP_BASE + 0x04)
176 /* Firmware-ID Register RW */
177#define SYS_ID_REG0 regptr(MSP_SLP_BASE + 0x08)
178 /* System-ID Register-0 RW */
179#define SYS_ID_REG1 regptr(MSP_SLP_BASE + 0x0C)
180 /* System-ID Register-1 RW */
181
182/* System Reset register definitions */
183#define RST_STS_REG regptr(MSP_SLP_BASE + 0x10)
184 /* System Reset Status RO */
185#define RST_SET_REG regptr(MSP_SLP_BASE + 0x14)
186 /* System Set Reset WO */
187#define RST_CLR_REG regptr(MSP_SLP_BASE + 0x18)
188 /* System Clear Reset WO */
189
190/* System Clock Registers */
191#define PCI_SLP_REG regptr(MSP_SLP_BASE + 0x1C)
192 /* PCI clock generator RW */
193#define URT_SLP_REG regptr(MSP_SLP_BASE + 0x20)
194 /* UART clock generator RW */
195/* reserved (MSP_SLP_BASE + 0x24) */
196/* reserved (MSP_SLP_BASE + 0x28) */
197#define PLL1_SLP_REG regptr(MSP_SLP_BASE + 0x2C)
198 /* PLL1 clock generator RW */
199#define PLL0_SLP_REG regptr(MSP_SLP_BASE + 0x30)
200 /* PLL0 clock generator RW */
201#define MIPS_SLP_REG regptr(MSP_SLP_BASE + 0x34)
202 /* MIPS clock generator RW */
203#define VE_SLP_REG regptr(MSP_SLP_BASE + 0x38)
204 /* Voice Eng clock generator RW */
205/* reserved (MSP_SLP_BASE + 0x3C) */
206#define MSB_SLP_REG regptr(MSP_SLP_BASE + 0x40)
207 /* MS-Bus clock generator RW */
208#define SMAC_SLP_REG regptr(MSP_SLP_BASE + 0x44)
209 /* Sec & MAC clock generator RW */
210#define PERF_SLP_REG regptr(MSP_SLP_BASE + 0x48)
211 /* Per & TDM clock generator RW */
212
213/* Interrupt Controller Registers */
214#define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70)
215 /* Interrupt status register RW */
216#define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74)
217 /* Interrupt enable/mask RW */
218#define SE_MBOX_REG regptr(MSP_SLP_BASE + 0x78)
219 /* Security Engine mailbox RW */
220#define VE_MBOX_REG regptr(MSP_SLP_BASE + 0x7C)
221 /* Voice Engine mailbox RW */
222
223/* ELB Controller Registers */
224#define CS0_CNFG_REG regptr(MSP_SLP_BASE + 0x80)
225 /* ELB CS0 Configuration Reg */
226#define CS0_ADDR_REG regptr(MSP_SLP_BASE + 0x84)
227 /* ELB CS0 Base Address Reg */
228#define CS0_MASK_REG regptr(MSP_SLP_BASE + 0x88)
229 /* ELB CS0 Mask Register */
230#define CS0_ACCESS_REG regptr(MSP_SLP_BASE + 0x8C)
231 /* ELB CS0 access register */
232
233#define CS1_CNFG_REG regptr(MSP_SLP_BASE + 0x90)
234 /* ELB CS1 Configuration Reg */
235#define CS1_ADDR_REG regptr(MSP_SLP_BASE + 0x94)
236 /* ELB CS1 Base Address Reg */
237#define CS1_MASK_REG regptr(MSP_SLP_BASE + 0x98)
238 /* ELB CS1 Mask Register */
239#define CS1_ACCESS_REG regptr(MSP_SLP_BASE + 0x9C)
240 /* ELB CS1 access register */
241
242#define CS2_CNFG_REG regptr(MSP_SLP_BASE + 0xA0)
243 /* ELB CS2 Configuration Reg */
244#define CS2_ADDR_REG regptr(MSP_SLP_BASE + 0xA4)
245 /* ELB CS2 Base Address Reg */
246#define CS2_MASK_REG regptr(MSP_SLP_BASE + 0xA8)
247 /* ELB CS2 Mask Register */
248#define CS2_ACCESS_REG regptr(MSP_SLP_BASE + 0xAC)
249 /* ELB CS2 access register */
250
251#define CS3_CNFG_REG regptr(MSP_SLP_BASE + 0xB0)
252 /* ELB CS3 Configuration Reg */
253#define CS3_ADDR_REG regptr(MSP_SLP_BASE + 0xB4)
254 /* ELB CS3 Base Address Reg */
255#define CS3_MASK_REG regptr(MSP_SLP_BASE + 0xB8)
256 /* ELB CS3 Mask Register */
257#define CS3_ACCESS_REG regptr(MSP_SLP_BASE + 0xBC)
258 /* ELB CS3 access register */
259
260#define CS4_CNFG_REG regptr(MSP_SLP_BASE + 0xC0)
261 /* ELB CS4 Configuration Reg */
262#define CS4_ADDR_REG regptr(MSP_SLP_BASE + 0xC4)
263 /* ELB CS4 Base Address Reg */
264#define CS4_MASK_REG regptr(MSP_SLP_BASE + 0xC8)
265 /* ELB CS4 Mask Register */
266#define CS4_ACCESS_REG regptr(MSP_SLP_BASE + 0xCC)
267 /* ELB CS4 access register */
268
269#define CS5_CNFG_REG regptr(MSP_SLP_BASE + 0xD0)
270 /* ELB CS5 Configuration Reg */
271#define CS5_ADDR_REG regptr(MSP_SLP_BASE + 0xD4)
272 /* ELB CS5 Base Address Reg */
273#define CS5_MASK_REG regptr(MSP_SLP_BASE + 0xD8)
274 /* ELB CS5 Mask Register */
275#define CS5_ACCESS_REG regptr(MSP_SLP_BASE + 0xDC)
276 /* ELB CS5 access register */
277
278/* reserved 0xE0 - 0xE8 */
279#define ELB_1PC_EN_REG regptr(MSP_SLP_BASE + 0xEC)
280 /* ELB single PC card detect */
281
282/* reserved 0xF0 - 0xF8 */
283#define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC)
284 /* SDRAM read/ELB timing Reg */
285
286/* Extended UART status registers */
287#define UART0_STATUS_REG regptr(MSP_UART0_BASE + 0x0c0)
288 /* UART Status Register 0 */
289#define UART1_STATUS_REG regptr(MSP_UART1_BASE + 0x170)
290 /* UART Status Register 1 */
291
292/* Performance monitoring registers */
293#define PERF_MON_CTRL_REG regptr(MSP_SLP_BASE + 0x140)
294 /* Performance monitor control */
295#define PERF_MON_CLR_REG regptr(MSP_SLP_BASE + 0x144)
296 /* Performance monitor clear */
297#define PERF_MON_CNTH_REG regptr(MSP_SLP_BASE + 0x148)
298 /* Perf monitor counter high */
299#define PERF_MON_CNTL_REG regptr(MSP_SLP_BASE + 0x14C)
300 /* Perf monitor counter low */
301
302/* System control registers */
303#define SYS_CTRL_REG regptr(MSP_SLP_BASE + 0x150)
304 /* System control register */
305#define SYS_ERR1_REG regptr(MSP_SLP_BASE + 0x154)
306 /* System Error status 1 */
307#define SYS_ERR2_REG regptr(MSP_SLP_BASE + 0x158)
308 /* System Error status 2 */
309#define SYS_INT_CFG_REG regptr(MSP_SLP_BASE + 0x15C)
310 /* System Interrupt config */
311
312/* Voice Engine Memory configuration */
313#define VE_MEM_REG regptr(MSP_SLP_BASE + 0x17C)
314 /* Voice engine memory config */
315
316/* CPU/SLP Error Status registers */
317#define CPU_ERR1_REG regptr(MSP_SLP_BASE + 0x180)
318 /* CPU/SLP Error status 1 */
319#define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184)
320 /* CPU/SLP Error status 1 */
321
322#define EXTENDED_GPIO_REG regptr(MSP_SLP_BASE + 0x188)
323 /* Extended GPIO register */
324
325/* System Error registers */
326#define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190)
327 /* Int status for SLP errors */
328#define SLP_ERR_MSK_REG regptr(MSP_SLP_BASE + 0x194)
329 /* Int mask for SLP errors */
330#define SLP_ELB_ERST_REG regptr(MSP_SLP_BASE + 0x198)
331 /* External ELB reset */
332#define SLP_BOOT_STS_REG regptr(MSP_SLP_BASE + 0x19C)
333 /* Boot Status */
334
335/* Extended ELB addressing */
336#define CS0_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A0)
337 /* CS0 Extended address */
338#define CS1_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A4)
339 /* CS1 Extended address */
340#define CS2_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A8)
341 /* CS2 Extended address */
342#define CS3_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1AC)
343 /* CS3 Extended address */
344/* reserved 0x1B0 */
345#define CS5_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1B4)
346 /* CS5 Extended address */
347
348/* PLL Adjustment registers */
349#define PLL_LOCK_REG regptr(MSP_SLP_BASE + 0x200)
350 /* PLL0 lock status */
351#define PLL_ARST_REG regptr(MSP_SLP_BASE + 0x204)
352 /* PLL Analog reset status */
353#define PLL0_ADJ_REG regptr(MSP_SLP_BASE + 0x208)
354 /* PLL0 Adjustment value */
355#define PLL1_ADJ_REG regptr(MSP_SLP_BASE + 0x20C)
356 /* PLL1 Adjustment value */
357
358/*
359 ***************************************************************************
360 * Peripheral Register definitions *
361 ***************************************************************************
362 */
363
364/* Peripheral status */
365#define PER_CTRL_REG regptr(MSP_PER_BASE + 0x50)
366 /* Peripheral control register */
367#define PER_STS_REG regptr(MSP_PER_BASE + 0x54)
368 /* Peripheral status register */
369
370/* SPI/MPI Registers */
371#define SMPI_TX_SZ_REG regptr(MSP_PER_BASE + 0x58)
372 /* SPI/MPI Tx Size register */
373#define SMPI_RX_SZ_REG regptr(MSP_PER_BASE + 0x5C)
374 /* SPI/MPI Rx Size register */
375#define SMPI_CTL_REG regptr(MSP_PER_BASE + 0x60)
376 /* SPI/MPI Control register */
377#define SMPI_MS_REG regptr(MSP_PER_BASE + 0x64)
378 /* SPI/MPI Chip Select reg */
379#define SMPI_CORE_DATA_REG regptr(MSP_PER_BASE + 0xC0)
380 /* SPI/MPI Core Data reg */
381#define SMPI_CORE_CTRL_REG regptr(MSP_PER_BASE + 0xC4)
382 /* SPI/MPI Core Control reg */
383#define SMPI_CORE_STAT_REG regptr(MSP_PER_BASE + 0xC8)
384 /* SPI/MPI Core Status reg */
385#define SMPI_CORE_SSEL_REG regptr(MSP_PER_BASE + 0xCC)
386 /* SPI/MPI Core Ssel reg */
387#define SMPI_FIFO_REG regptr(MSP_PER_BASE + 0xD0)
388 /* SPI/MPI Data FIFO reg */
389
390/* Peripheral Block Error Registers */
391#define PER_ERR_STS_REG regptr(MSP_PER_BASE + 0x70)
392 /* Error Bit Status Register */
393#define PER_ERR_MSK_REG regptr(MSP_PER_BASE + 0x74)
394 /* Error Bit Mask Register */
395#define PER_HDR1_REG regptr(MSP_PER_BASE + 0x78)
396 /* Error Header 1 Register */
397#define PER_HDR2_REG regptr(MSP_PER_BASE + 0x7C)
398 /* Error Header 2 Register */
399
400/* Peripheral Block Interrupt Registers */
401#define PER_INT_STS_REG regptr(MSP_PER_BASE + 0x80)
402 /* Interrupt status register */
403#define PER_INT_MSK_REG regptr(MSP_PER_BASE + 0x84)
404 /* Interrupt Mask Register */
405#define GPIO_INT_STS_REG regptr(MSP_PER_BASE + 0x88)
406 /* GPIO interrupt status reg */
407#define GPIO_INT_MSK_REG regptr(MSP_PER_BASE + 0x8C)
408 /* GPIO interrupt MASK Reg */
409
410/* POLO GPIO registers */
411#define POLO_GPIO_DAT1_REG regptr(MSP_PER_BASE + 0x0E0)
412 /* Polo GPIO[8:0] data reg */
413#define POLO_GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x0E4)
414 /* Polo GPIO[7:0] config reg */
415#define POLO_GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x0E8)
416 /* Polo GPIO[15:8] config reg */
417#define POLO_GPIO_OD1_REG regptr(MSP_PER_BASE + 0x0EC)
418 /* Polo GPIO[31:0] output drive */
419#define POLO_GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x170)
420 /* Polo GPIO[23:16] config reg */
421#define POLO_GPIO_DAT2_REG regptr(MSP_PER_BASE + 0x174)
422 /* Polo GPIO[15:9] data reg */
423#define POLO_GPIO_DAT3_REG regptr(MSP_PER_BASE + 0x178)
424 /* Polo GPIO[23:16] data reg */
425#define POLO_GPIO_DAT4_REG regptr(MSP_PER_BASE + 0x17C)
426 /* Polo GPIO[31:24] data reg */
427#define POLO_GPIO_DAT5_REG regptr(MSP_PER_BASE + 0x180)
428 /* Polo GPIO[39:32] data reg */
429#define POLO_GPIO_DAT6_REG regptr(MSP_PER_BASE + 0x184)
430 /* Polo GPIO[47:40] data reg */
431#define POLO_GPIO_DAT7_REG regptr(MSP_PER_BASE + 0x188)
432 /* Polo GPIO[54:48] data reg */
433#define POLO_GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)
434 /* Polo GPIO[31:24] config reg */
435#define POLO_GPIO_CFG5_REG regptr(MSP_PER_BASE + 0x190)
436 /* Polo GPIO[39:32] config reg */
437#define POLO_GPIO_CFG6_REG regptr(MSP_PER_BASE + 0x194)
438 /* Polo GPIO[47:40] config reg */
439#define POLO_GPIO_CFG7_REG regptr(MSP_PER_BASE + 0x198)
440 /* Polo GPIO[54:48] config reg */
441#define POLO_GPIO_OD2_REG regptr(MSP_PER_BASE + 0x19C)
442 /* Polo GPIO[54:32] output drive */
443
444/* Generic GPIO registers */
445#define GPIO_DATA1_REG regptr(MSP_PER_BASE + 0x170)
446 /* GPIO[1:0] data register */
447#define GPIO_DATA2_REG regptr(MSP_PER_BASE + 0x174)
448 /* GPIO[5:2] data register */
449#define GPIO_DATA3_REG regptr(MSP_PER_BASE + 0x178)
450 /* GPIO[9:6] data register */
451#define GPIO_DATA4_REG regptr(MSP_PER_BASE + 0x17C)
452 /* GPIO[15:10] data register */
453#define GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x180)
454 /* GPIO[1:0] config register */
455#define GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x184)
456 /* GPIO[5:2] config register */
457#define GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x188)
458 /* GPIO[9:6] config register */
459#define GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)
460 /* GPIO[15:10] config register */
461#define GPIO_OD_REG regptr(MSP_PER_BASE + 0x190)
462 /* GPIO[15:0] output drive */
463
464/*
465 ***************************************************************************
466 * CPU Interface register definitions *
467 ***************************************************************************
468 */
469#define PCI_FLUSH_REG regptr(MSP_CPUIF_BASE + 0x00)
470 /* PCI-SDRAM queue flush trigger */
471#define OCP_ERR1_REG regptr(MSP_CPUIF_BASE + 0x04)
472 /* OCP Error Attribute 1 */
473#define OCP_ERR2_REG regptr(MSP_CPUIF_BASE + 0x08)
474 /* OCP Error Attribute 2 */
475#define OCP_STS_REG regptr(MSP_CPUIF_BASE + 0x0C)
476 /* OCP Error Status */
477#define CPUIF_PM_REG regptr(MSP_CPUIF_BASE + 0x10)
478 /* CPU policy configuration */
479#define CPUIF_CFG_REG regptr(MSP_CPUIF_BASE + 0x10)
480 /* Misc configuration options */
481
482/* Central Interrupt Controller Registers */
483#define MSP_CIC_BASE (MSP_CPUIF_BASE + 0x8000)
484 /* Central Interrupt registers */
485#define CIC_EXT_CFG_REG regptr(MSP_CIC_BASE + 0x00)
486 /* External interrupt config */
487#define CIC_STS_REG regptr(MSP_CIC_BASE + 0x04)
488 /* CIC Interrupt Status */
489#define CIC_VPE0_MSK_REG regptr(MSP_CIC_BASE + 0x08)
490 /* VPE0 Interrupt Mask */
491#define CIC_VPE1_MSK_REG regptr(MSP_CIC_BASE + 0x0C)
492 /* VPE1 Interrupt Mask */
493#define CIC_TC0_MSK_REG regptr(MSP_CIC_BASE + 0x10)
494 /* Thread Context 0 Int Mask */
495#define CIC_TC1_MSK_REG regptr(MSP_CIC_BASE + 0x14)
496 /* Thread Context 1 Int Mask */
497#define CIC_TC2_MSK_REG regptr(MSP_CIC_BASE + 0x18)
498 /* Thread Context 2 Int Mask */
499#define CIC_TC3_MSK_REG regptr(MSP_CIC_BASE + 0x18)
500 /* Thread Context 3 Int Mask */
501#define CIC_TC4_MSK_REG regptr(MSP_CIC_BASE + 0x18)
502 /* Thread Context 4 Int Mask */
503#define CIC_PCIMSI_STS_REG regptr(MSP_CIC_BASE + 0x18)
504#define CIC_PCIMSI_MSK_REG regptr(MSP_CIC_BASE + 0x18)
505#define CIC_PCIFLSH_REG regptr(MSP_CIC_BASE + 0x18)
506#define CIC_VPE0_SWINT_REG regptr(MSP_CIC_BASE + 0x08)
507
508
509/*
510 ***************************************************************************
511 * Memory controller registers *
512 ***************************************************************************
513 */
514#define MEM_CFG1_REG regptr(MSP_MEM_CFG_BASE + 0x00)
515#define MEM_SS_ADDR regptr(MSP_MEM_CFG_BASE + 0x00)
516#define MEM_SS_DATA regptr(MSP_MEM_CFG_BASE + 0x04)
517#define MEM_SS_WRITE regptr(MSP_MEM_CFG_BASE + 0x08)
518
519/*
520 ***************************************************************************
521 * PCI controller registers *
522 ***************************************************************************
523 */
524#define PCI_BASE_REG regptr(MSP_PCI_BASE + 0x00)
525#define PCI_CONFIG_SPACE_REG regptr(MSP_PCI_BASE + 0x800)
526#define PCI_JTAG_DEVID_REG regptr(MSP_SLP_BASE + 0x13c)
527
528/*
529 ########################################################################
530 # Register content & macro definitions #
531 ########################################################################
532 */
533
534/*
535 ***************************************************************************
536 * DEV_ID defines *
537 ***************************************************************************
538 */
539#define DEV_ID_PCI_DIS (1 << 26) /* Set if PCI disabled */
540#define DEV_ID_PCI_HOST (1 << 20) /* Set if PCI host */
541#define DEV_ID_SINGLE_PC (1 << 19) /* Set if single PC Card */
542#define DEV_ID_FAMILY (0xff << 8) /* family ID code */
543#define POLO_ZEUS_SUB_FAMILY (0x7 << 16) /* sub family for Polo/Zeus */
544
545#define MSPFPGA_ID (0x00 << 8) /* you are on your own here */
546#define MSP5000_ID (0x50 << 8)
547#define MSP4F00_ID (0x4f << 8) /* FPGA version of MSP4200 */
548#define MSP4E00_ID (0x4f << 8) /* FPGA version of MSP7120 */
549#define MSP4200_ID (0x42 << 8)
550#define MSP4000_ID (0x40 << 8)
551#define MSP2XXX_ID (0x20 << 8)
552#define MSPZEUS_ID (0x10 << 8)
553
554#define MSP2004_SUB_ID (0x0 << 16)
555#define MSP2005_SUB_ID (0x1 << 16)
556#define MSP2006_SUB_ID (0x1 << 16)
557#define MSP2007_SUB_ID (0x2 << 16)
558#define MSP2010_SUB_ID (0x3 << 16)
559#define MSP2015_SUB_ID (0x4 << 16)
560#define MSP2020_SUB_ID (0x5 << 16)
561#define MSP2100_SUB_ID (0x6 << 16)
562
563/*
564 ***************************************************************************
565 * RESET defines *
566 ***************************************************************************
567 */
568#define MSP_GR_RST (0x01 << 0) /* Global reset bit */
569#define MSP_MR_RST (0x01 << 1) /* MIPS reset bit */
570#define MSP_PD_RST (0x01 << 2) /* PVC DMA reset bit */
571#define MSP_PP_RST (0x01 << 3) /* PVC reset bit */
572/* reserved */
573#define MSP_EA_RST (0x01 << 6) /* Mac A reset bit */
574#define MSP_EB_RST (0x01 << 7) /* Mac B reset bit */
575#define MSP_SE_RST (0x01 << 8) /* Security Eng reset bit */
576#define MSP_PB_RST (0x01 << 9) /* Per block reset bit */
577#define MSP_EC_RST (0x01 << 10) /* Mac C reset bit */
578#define MSP_TW_RST (0x01 << 11) /* TWI reset bit */
579#define MSP_SPI_RST (0x01 << 12) /* SPI/MPI reset bit */
580#define MSP_U1_RST (0x01 << 13) /* UART1 reset bit */
581#define MSP_U0_RST (0x01 << 14) /* UART0 reset bit */
582
583/*
584 ***************************************************************************
585 * UART defines *
586 ***************************************************************************
587 */
588#ifndef CONFIG_MSP_FPGA
589#define MSP_BASE_BAUD 25000000
590#else
591#define MSP_BASE_BAUD 6000000
592#endif
593#define MSP_UART_REG_LEN 0x20
594
595/*
596 ***************************************************************************
597 * ELB defines *
598 ***************************************************************************
599 */
600#define PCCARD_32 0x02 /* Set if is PCCARD 32 (Cardbus) */
601#define SINGLE_PCCARD 0x01 /* Set to enable single PC card */
602
603/*
604 ***************************************************************************
605 * CIC defines *
606 ***************************************************************************
607 */
608
609/* CIC_EXT_CFG_REG */
610#define EXT_INT_POL(eirq) (1 << (eirq + 8))
611#define EXT_INT_EDGE(eirq) (1 << eirq)
612
613#define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq) (reg &= ~EXT_INT_EDGE(eirq))
614#define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq) (reg |= EXT_INT_EDGE(eirq))
615#define CIC_EXT_SET_ACTIVE_HI(reg, eirq) (reg |= EXT_INT_POL(eirq))
616#define CIC_EXT_SET_ACTIVE_LO(reg, eirq) (reg &= ~EXT_INT_POL(eirq))
617#define CIC_EXT_SET_ACTIVE_RISING CIC_EXT_SET_ACTIVE_HI
618#define CIC_EXT_SET_ACTIVE_FALLING CIC_EXT_SET_ACTIVE_LO
619
620#define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \
621 ((reg & EXT_INT_EDGE(eirq)) == 0)
622#define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq) (reg & EXT_INT_EDGE(eirq))
623#define CIC_EXT_IS_ACTIVE_HI(reg, eirq) (reg & EXT_INT_POL(eirq))
624#define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \
625 ((reg & EXT_INT_POL(eirq)) == 0)
626#define CIC_EXT_IS_ACTIVE_RISING CIC_EXT_IS_ACTIVE_HI
627#define CIC_EXT_IS_ACTIVE_FALLING CIC_EXT_IS_ACTIVE_LO
628
629/*
630 ***************************************************************************
631 * Memory Controller defines *
632 ***************************************************************************
633 */
634
635/* Indirect memory controller registers */
636#define DDRC_CFG(n) (n)
637#define DDRC_DEBUG(n) (0x04 + n)
638#define DDRC_CTL(n) (0x40 + n)
639
640/* Macro to perform DDRC indirect write */
641#define DDRC_INDIRECT_WRITE(reg, mask, value) \
642({ \
643 *MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \
644 *MEM_SS_DATA = (value); \
645 *MEM_SS_WRITE = 1; \
646})
647
648/*
649 ***************************************************************************
650 * SPI/MPI Mode *
651 ***************************************************************************
652 */
653#define SPI_MPI_RX_BUSY 0x00008000 /* SPI/MPI Receive Busy */
654#define SPI_MPI_FIFO_EMPTY 0x00004000 /* SPI/MPI Fifo Empty */
655#define SPI_MPI_TX_BUSY 0x00002000 /* SPI/MPI Transmit Busy */
656#define SPI_MPI_FIFO_FULL 0x00001000 /* SPI/MPU FIFO full */
657
658/*
659 ***************************************************************************
660 * SPI/MPI Control Register *
661 ***************************************************************************
662 */
663#define SPI_MPI_RX_START 0x00000004 /* Start receive command */
664#define SPI_MPI_FLUSH_Q 0x00000002 /* Flush SPI/MPI Queue */
665#define SPI_MPI_TX_START 0x00000001 /* Start Transmit Command */
666
667#endif /* !_ASM_MSP_REGS_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h
new file mode 100644
index 000000000000..96d4c8ce8c83
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h
@@ -0,0 +1,141 @@
1/*
2 * Defines for the MSP interrupt controller.
3 *
4 * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
5 * Author: Carsten Langgaard, carstenl@mips.com
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 */
24
25#ifndef _MSP_SLP_INT_H
26#define _MSP_SLP_INT_H
27
28/*
29 * The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded
30 * hierarchical system. The first level are the direct MIPS interrupts
31 * and are assigned the interrupt range 0-7. The second level is the SLM
32 * interrupt controller and is assigned the range 8-39. The third level
33 * comprises the Peripherial block, the PCI block, the PCI MSI block and
34 * the SLP. The PCI interrupts and the SLP errors are handled by the
35 * relevant subsystems so the core interrupt code needs only concern
36 * itself with the Peripheral block. These are assigned interrupts in
37 * the range 40-71.
38 */
39
40/*
41 * IRQs directly connected to CPU
42 */
43#define MSP_MIPS_INTBASE 0
44#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */
45#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */
46#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */
47#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */
48#define MSP_INT_C_IRQ2 4 /* Wired off, C_IRQ2 */
49#define MSP_INT_VE 5 /* IRQ for Voice Engine, C_IRQ3 */
50#define MSP_INT_SLP 6 /* IRQ for SLM block, C_IRQ4 */
51#define MSP_INT_TIMER 7 /* IRQ for the MIPS timer, C_IRQ5 */
52
53/*
54 * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
55 * These defines should be tied to the register definition for the SLM
56 * interrupt routine. For now, just use hard-coded values.
57 */
58#define MSP_SLP_INTBASE (MSP_MIPS_INTBASE + 8)
59#define MSP_INT_EXT0 (MSP_SLP_INTBASE + 0)
60 /* External interrupt 0 */
61#define MSP_INT_EXT1 (MSP_SLP_INTBASE + 1)
62 /* External interrupt 1 */
63#define MSP_INT_EXT2 (MSP_SLP_INTBASE + 2)
64 /* External interrupt 2 */
65#define MSP_INT_EXT3 (MSP_SLP_INTBASE + 3)
66 /* External interrupt 3 */
67/* Reserved 4-7 */
68
69/*
70 *************************************************************************
71 * DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER *
72 * Some MSP produces have this interrupt labelled as Voice and some are *
73 * SEC mbox ... *
74 *************************************************************************
75 */
76#define MSP_INT_SLP_VE (MSP_SLP_INTBASE + 8)
77 /* Cascaded IRQ for Voice Engine*/
78#define MSP_INT_SLP_TDM (MSP_SLP_INTBASE + 9)
79 /* TDM interrupt */
80#define MSP_INT_SLP_MAC0 (MSP_SLP_INTBASE + 10)
81 /* Cascaded IRQ for MAC 0 */
82#define MSP_INT_SLP_MAC1 (MSP_SLP_INTBASE + 11)
83 /* Cascaded IRQ for MAC 1 */
84#define MSP_INT_SEC (MSP_SLP_INTBASE + 12)
85 /* IRQ for security engine */
86#define MSP_INT_PER (MSP_SLP_INTBASE + 13)
87 /* Peripheral interrupt */
88#define MSP_INT_TIMER0 (MSP_SLP_INTBASE + 14)
89 /* SLP timer 0 */
90#define MSP_INT_TIMER1 (MSP_SLP_INTBASE + 15)
91 /* SLP timer 1 */
92#define MSP_INT_TIMER2 (MSP_SLP_INTBASE + 16)
93 /* SLP timer 2 */
94#define MSP_INT_SLP_TIMER (MSP_SLP_INTBASE + 17)
95 /* Cascaded MIPS timer */
96#define MSP_INT_BLKCP (MSP_SLP_INTBASE + 18)
97 /* Block Copy */
98#define MSP_INT_UART0 (MSP_SLP_INTBASE + 19)
99 /* UART 0 */
100#define MSP_INT_PCI (MSP_SLP_INTBASE + 20)
101 /* PCI subsystem */
102#define MSP_INT_PCI_DBELL (MSP_SLP_INTBASE + 21)
103 /* PCI doorbell */
104#define MSP_INT_PCI_MSI (MSP_SLP_INTBASE + 22)
105 /* PCI Message Signal */
106#define MSP_INT_PCI_BC0 (MSP_SLP_INTBASE + 23)
107 /* PCI Block Copy 0 */
108#define MSP_INT_PCI_BC1 (MSP_SLP_INTBASE + 24)
109 /* PCI Block Copy 1 */
110#define MSP_INT_SLP_ERR (MSP_SLP_INTBASE + 25)
111 /* SLP error condition */
112#define MSP_INT_MAC2 (MSP_SLP_INTBASE + 26)
113 /* IRQ for MAC2 */
114/* Reserved 26-31 */
115
116/*
117 * IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
118 */
119#define MSP_PER_INTBASE (MSP_SLP_INTBASE + 32)
120/* Reserved 0-1 */
121#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)
122 /* UART 1 */
123/* Reserved 3-5 */
124#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)
125 /* 2-wire */
126#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)
127 /* Peripheral timer block out 0 */
128#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)
129 /* Peripheral timer block out 1 */
130/* Reserved 9 */
131#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)
132 /* SPI RX complete */
133#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)
134 /* SPI TX complete */
135#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)
136 /* GPIO */
137#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)
138 /* Peripheral error */
139/* Reserved 14-31 */
140
141#endif /* !_MSP_SLP_INT_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 07:47:36 -0500