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-rw-r--r--arch/mips/mm/c-r4k.c2
-rw-r--r--include/asm-mips/mipsregs.h1
2 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index d5111d165434..069803f58f3b 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -862,7 +862,7 @@ static void __init probe_pcache(void)
862 break; 862 break;
863 863
864 case CPU_VR4133: 864 case CPU_VR4133:
865 write_c0_config(config & ~CONF_EB); 865 write_c0_config(config & ~VR41_CONF_P4K);
866 case CPU_VR4131: 866 case CPU_VR4131:
867 /* Workaround for cache instruction bug of VR4131 */ 867 /* Workaround for cache instruction bug of VR4131 */
868 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || 868 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 677668867b9d..1f318d707998 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -470,6 +470,7 @@
470 470
471/* Bits specific to the VR41xx. */ 471/* Bits specific to the VR41xx. */
472#define VR41_CONF_CS (_ULCAST_(1) << 12) 472#define VR41_CONF_CS (_ULCAST_(1) << 12)
473#define VR41_CONF_P4K (_ULCAST_(1) << 13)
473#define VR41_CONF_BP (_ULCAST_(1) << 16) 474#define VR41_CONF_BP (_ULCAST_(1) << 16)
474#define VR41_CONF_M16 (_ULCAST_(1) << 20) 475#define VR41_CONF_M16 (_ULCAST_(1) << 20)
475#define VR41_CONF_AD (_ULCAST_(1) << 23) 476#define VR41_CONF_AD (_ULCAST_(1) << 23)