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-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7366.c4
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c4
2 files changed, 2 insertions, 6 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index e10c64fd8095..f99db94cf8fb 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -158,8 +158,8 @@ static struct clk mstp_clks[] = {
158 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), 158 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
159 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), 159 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
160 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), 160 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
161 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 161 MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
162 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), 162 MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0),
163 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 163 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
164 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), 164 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
165 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 165 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 1d897ed256b0..8dab9e1bbd89 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -170,7 +170,6 @@ static struct platform_device veu1_device = {
170static struct sh_timer_config cmt_platform_data = { 170static struct sh_timer_config cmt_platform_data = {
171 .channel_offset = 0x60, 171 .channel_offset = 0x60,
172 .timer_bit = 5, 172 .timer_bit = 5,
173 .clk = "cmt0",
174 .clockevent_rating = 125, 173 .clockevent_rating = 125,
175 .clocksource_rating = 200, 174 .clocksource_rating = 200,
176}; 175};
@@ -200,7 +199,6 @@ static struct platform_device cmt_device = {
200static struct sh_timer_config tmu0_platform_data = { 199static struct sh_timer_config tmu0_platform_data = {
201 .channel_offset = 0x04, 200 .channel_offset = 0x04,
202 .timer_bit = 0, 201 .timer_bit = 0,
203 .clk = "tmu0",
204 .clockevent_rating = 200, 202 .clockevent_rating = 200,
205}; 203};
206 204
@@ -229,7 +227,6 @@ static struct platform_device tmu0_device = {
229static struct sh_timer_config tmu1_platform_data = { 227static struct sh_timer_config tmu1_platform_data = {
230 .channel_offset = 0x10, 228 .channel_offset = 0x10,
231 .timer_bit = 1, 229 .timer_bit = 1,
232 .clk = "tmu0",
233 .clocksource_rating = 200, 230 .clocksource_rating = 200,
234}; 231};
235 232
@@ -258,7 +255,6 @@ static struct platform_device tmu1_device = {
258static struct sh_timer_config tmu2_platform_data = { 255static struct sh_timer_config tmu2_platform_data = {
259 .channel_offset = 0x1c, 256 .channel_offset = 0x1c,
260 .timer_bit = 2, 257 .timer_bit = 2,
261 .clk = "tmu0",
262}; 258};
263 259
264static struct resource tmu2_resources[] = { 260static struct resource tmu2_resources[] = {