1 files changed, 60 insertions, 83 deletions
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 0ff5a6c53aa0..1e7aae2ce5ed 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -51,97 +51,74 @@ static void (*_omap_sram_idle)(u32 *addr, int save_state);
 static struct powerdomain *mpu_pwrdm;
-/* PRCM Interrupt Handler for wakeups */
+/*
-static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
+ * PRCM Interrupt Handler Helper Function
+ *
+ * The purpose of this function is to clear any wake-up events latched
+ * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
+ * may occur whilst attempting to clear a PM_WKST_x register and thus
+ * set another bit in this register. A while loop is used to ensure
+ * that any peripheral wake-up events occurring while attempting to
+ * clear the PM_WKST_x are detected and cleared.
+ */
+static void prcm_clear_mod_irqs(s16 module, u8 regs)
 {
-        u32 wkst, irqstatus_mpu;
+        u32 wkst, fclk, iclk;
-        u32 fclk, iclk;
+        u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
+        u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
+        u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
-        /* WKUP */
+        wkst = prm_read_mod_reg(module, wkst_off);
-        wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
        if (wkst) {
-                iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
+                iclk = cm_read_mod_reg(module, iclk_off);
-                fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
+                fclk = cm_read_mod_reg(module, fclk_off);
-                cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
+                while (wkst) {
-                cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
+                        cm_set_mod_reg_bits(wkst, module, iclk_off);
-                prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
+                        cm_set_mod_reg_bits(wkst, module, fclk_off);
-                while (prm_read_mod_reg(WKUP_MOD, PM_WKST))
+                        prm_write_mod_reg(wkst, module, wkst_off);
-                        cpu_relax();
+                        wkst = prm_read_mod_reg(module, wkst_off);
-                cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
+                }
-                cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
+                cm_write_mod_reg(iclk, module, iclk_off);
-        }
+                cm_write_mod_reg(fclk, module, fclk_off);
-        /* CORE */
-        wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
-        if (wkst) {
-                iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
-                fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
-                cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
-                cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
-                prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
-                while (prm_read_mod_reg(CORE_MOD, PM_WKST1))
-                        cpu_relax();
-                cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
-                cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
-        }
-        wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
-        if (wkst) {
-                iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
-                fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
-                cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
-                cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
-                prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
-                while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3))
-                        cpu_relax();
-                cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
-                cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
-        }
-        /* PER */
-        wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
-        if (wkst) {
-                iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
-                fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
-                cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
-                cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
-                prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
-                while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST))
-                        cpu_relax();
-                cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
-                cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
        }
+}
-        if (omap_rev() > OMAP3430_REV_ES1_0) {
+/*
-                /* USBHOST */
+ * PRCM Interrupt Handler
-                wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
+ *
-                if (wkst) {
+ * The PRM_IRQSTATUS_MPU register indicates if there are any pending
-                        iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+ * interrupts from the PRCM for the MPU. These bits must be cleared in
-                                               CM_ICLKEN);
+ * order to clear the PRCM interrupt. The PRCM interrupt handler is
-                        fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+ * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
-                                               CM_FCLKEN);
+ * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
-                        cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
+ * register indicates that a wake-up event is pending for the MPU and
-                                            CM_ICLKEN);
+ * this bit can only be cleared if the all the wake-up events latched
-                        cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
+ * in the various PM_WKST_x registers have been cleared. The interrupt
-                                            CM_FCLKEN);
+ * handler is implemented using a do-while loop so that if a wake-up
-                        prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,
+ * event occurred during the processing of the prcm interrupt handler
-                                          PM_WKST);
+ * (setting a bit in the corresponding PM_WKST_x register and thus
-                        while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+ * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
-                                                PM_WKST))
+ * this would be handled.
-                                cpu_relax();
+ */
-                        cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,
+static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
-                                         CM_ICLKEN);
+{
-                        cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,
+        u32 irqstatus_mpu;
-                                         CM_FCLKEN);
+        do {
+                prcm_clear_mod_irqs(WKUP_MOD, 1);
+                prcm_clear_mod_irqs(CORE_MOD, 1);
+                prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
+                if (omap_rev() > OMAP3430_REV_ES1_0) {
+                        prcm_clear_mod_irqs(CORE_MOD, 3);
+                        prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
                }
-        }
-        irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
+                irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
-                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+                                        OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-        prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
+                prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
-                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+                                        OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-        while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET))
+        } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
-                cpu_relax();
        return IRQ_HANDLED;
 }

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 0ff5a6c53aa0..1e7aae2ce5ed 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c
@@ -51,97 +51,74 @@ static void (_omap_sram_idle)(u32 addr, int save_state);
51		51
52	static struct powerdomain *mpu_pwrdm;	52	static struct powerdomain *mpu_pwrdm;
53		53
54	/* PRCM Interrupt Handler for wakeups */	54	/*
55	static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)	55	* PRCM Interrupt Handler Helper Function
		56	*
		57	* The purpose of this function is to clear any wake-up events latched
		58	* in the PRCM PM_WKST_x registers. It is possible that a wake-up event
		59	* may occur whilst attempting to clear a PM_WKST_x register and thus
		60	* set another bit in this register. A while loop is used to ensure
		61	* that any peripheral wake-up events occurring while attempting to
		62	* clear the PM_WKST_x are detected and cleared.
		63	*/
		64	static void prcm_clear_mod_irqs(s16 module, u8 regs)
56	{	65	{
57	u32 wkst, irqstatus_mpu;	66	u32 wkst, fclk, iclk;
58	u32 fclk, iclk;	67	u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
		68	u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
		69	u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
59		70
60	/* WKUP */	71	wkst = prm_read_mod_reg(module, wkst_off);
61	wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
62	if (wkst) {	72	if (wkst) {
63	iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);	73	iclk = cm_read_mod_reg(module, iclk_off);
64	fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);	74	fclk = cm_read_mod_reg(module, fclk_off);
65	cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);	75	while (wkst) {
66	cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);	76	cm_set_mod_reg_bits(wkst, module, iclk_off);
67	prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);	77	cm_set_mod_reg_bits(wkst, module, fclk_off);
68	while (prm_read_mod_reg(WKUP_MOD, PM_WKST))	78	prm_write_mod_reg(wkst, module, wkst_off);
69	cpu_relax();	79	wkst = prm_read_mod_reg(module, wkst_off);
70	cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);	80	}
71	cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);	81	cm_write_mod_reg(iclk, module, iclk_off);
72	}	82	cm_write_mod_reg(fclk, module, fclk_off);
73
74	/* CORE */
75	wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
76	if (wkst) {
77	iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
78	fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
79	cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
80	cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
81	prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
82	while (prm_read_mod_reg(CORE_MOD, PM_WKST1))
83	cpu_relax();
84	cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
85	cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
86	}
87	wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
88	if (wkst) {
89	iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
90	fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
91	cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
92	cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
93	prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
94	while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3))
95	cpu_relax();
96	cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
97	cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
98	}
99
100	/* PER */
101	wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
102	if (wkst) {
103	iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
104	fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
105	cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
106	cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
107	prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
108	while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST))
109	cpu_relax();
110	cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
111	cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
112	}	83	}
		84	}
113		85
114	if (omap_rev() > OMAP3430_REV_ES1_0) {	86	/*
115	/* USBHOST */	87	* PRCM Interrupt Handler
116	wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);	88	*
117	if (wkst) {	89	* The PRM_IRQSTATUS_MPU register indicates if there are any pending
118	iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,	90	* interrupts from the PRCM for the MPU. These bits must be cleared in
119	CM_ICLKEN);	91	* order to clear the PRCM interrupt. The PRCM interrupt handler is
120	fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,	92	* implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
121	CM_FCLKEN);	93	* the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
122	cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,	94	* register indicates that a wake-up event is pending for the MPU and
123	CM_ICLKEN);	95	* this bit can only be cleared if the all the wake-up events latched
124	cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,	96	* in the various PM_WKST_x registers have been cleared. The interrupt
125	CM_FCLKEN);	97	* handler is implemented using a do-while loop so that if a wake-up
126	prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,	98	* event occurred during the processing of the prcm interrupt handler
127	PM_WKST);	99	* (setting a bit in the corresponding PM_WKST_x register and thus
128	while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,	100	* preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
129	PM_WKST))	101	* this would be handled.
130	cpu_relax();	102	*/
131	cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,	103	static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
132	CM_ICLKEN);	104	{
133	cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,	105	u32 irqstatus_mpu;
134	CM_FCLKEN);	106
		107	do {
		108	prcm_clear_mod_irqs(WKUP_MOD, 1);
		109	prcm_clear_mod_irqs(CORE_MOD, 1);
		110	prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
		111	if (omap_rev() > OMAP3430_REV_ES1_0) {
		112	prcm_clear_mod_irqs(CORE_MOD, 3);
		113	prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
135	}	114	}
136	}
137		115
138	irqstatus_mpu = prm_read_mod_reg(OCP_MOD,	116	irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
139	OMAP3_PRM_IRQSTATUS_MPU_OFFSET);	117	OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
140	prm_write_mod_reg(irqstatus_mpu, OCP_MOD,	118	prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
141	OMAP3_PRM_IRQSTATUS_MPU_OFFSET);	119	OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
142		120
143	while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET))	121	} while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
144	cpu_relax();
145		122
146	return IRQ_HANDLED;	123	return IRQ_HANDLED;
147	}	124	}