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-rw-r--r--arch/arm/Kconfig3
-rw-r--r--arch/arm/common/sharpsl_pm.c3
-rw-r--r--arch/arm/configs/em_x270_defconfig1265
-rw-r--r--arch/arm/configs/xm_x270_defconfig (renamed from arch/arm/configs/cm_x270_defconfig)862
-rw-r--r--arch/arm/mach-pxa/Kconfig59
-rw-r--r--arch/arm/mach-pxa/Makefile1
-rw-r--r--arch/arm/mach-pxa/clock.c2
-rw-r--r--arch/arm/mach-pxa/cm-x270-pci.c26
-rw-r--r--arch/arm/mach-pxa/corgi.c1
-rw-r--r--arch/arm/mach-pxa/corgi_pm.c7
-rw-r--r--arch/arm/mach-pxa/devices.c69
-rw-r--r--arch/arm/mach-pxa/devices.h5
-rw-r--r--arch/arm/mach-pxa/em-x270.c1
-rw-r--r--arch/arm/mach-pxa/generic.c1
-rw-r--r--arch/arm/mach-pxa/lpd270.c47
-rw-r--r--arch/arm/mach-pxa/magician.c69
-rw-r--r--arch/arm/mach-pxa/mainstone.c63
-rw-r--r--arch/arm/mach-pxa/mfp-pxa2xx.c1
-rw-r--r--arch/arm/mach-pxa/pcm990-baseboard.c99
-rw-r--r--arch/arm/mach-pxa/poodle.c1
-rw-r--r--arch/arm/mach-pxa/pwm.c319
-rw-r--r--arch/arm/mach-pxa/pxa25x.c7
-rw-r--r--arch/arm/mach-pxa/pxa27x.c10
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c6
-rw-r--r--arch/arm/mach-pxa/spitz_pm.c7
-rw-r--r--arch/arm/mach-pxa/standby.S83
-rw-r--r--arch/arm/mach-pxa/trizeps4.c2
-rw-r--r--arch/arm/mach-pxa/zylonite.c26
-rw-r--r--arch/arm/mach-pxa/zylonite_pxa300.c4
-rw-r--r--arch/arm/mach-pxa/zylonite_pxa320.c2
-rw-r--r--drivers/i2c/busses/i2c-pxa.c29
-rw-r--r--drivers/pcmcia/pxa2xx_cm_x270.c15
-rw-r--r--drivers/pcmcia/pxa2xx_mainstone.c13
-rw-r--r--drivers/pcmcia/pxa2xx_sharpsl.c12
-rw-r--r--drivers/usb/gadget/pxa27x_udc.c5
-rw-r--r--drivers/usb/gadget/pxa27x_udc.h8
-rw-r--r--drivers/usb/gadget/pxa2xx_udc.c10
-rw-r--r--drivers/usb/host/ohci-pxa27x.c3
-rw-r--r--drivers/video/backlight/Kconfig7
-rw-r--r--drivers/video/backlight/Makefile1
-rw-r--r--drivers/video/backlight/pwm_bl.c185
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h570
-rw-r--r--include/asm-arm/arch-pxa/pxa25x-udc.h163
-rw-r--r--include/asm-arm/arch-pxa/pxa27x-udc.h257
-rw-r--r--include/asm-arm/arch-pxa/pxa2xx-regs.h162
-rw-r--r--include/asm-arm/arch-pxa/system.h1
-rw-r--r--include/asm-arm/arch-pxa/zylonite.h1
-rw-r--r--include/linux/pwm.h31
-rw-r--r--include/linux/pwm_backlight.h17
49 files changed, 2198 insertions, 2343 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b786e68914d4..c274dbb89a83 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -22,6 +22,9 @@ config ARM
22 Europe. There is an ARM Linux project with a web page at 22 Europe. There is an ARM Linux project with a web page at
23 <http://www.arm.linux.org.uk/>. 23 <http://www.arm.linux.org.uk/>.
24 24
25config HAVE_PWM
26 bool
27
25config SYS_SUPPORTS_APM_EMULATION 28config SYS_SUPPORTS_APM_EMULATION
26 bool 29 bool
27 30
diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c
index 5bba5255b119..8822b684d474 100644
--- a/arch/arm/common/sharpsl_pm.c
+++ b/arch/arm/common/sharpsl_pm.c
@@ -31,6 +31,7 @@
31#include <asm/irq.h> 31#include <asm/irq.h>
32#include <asm/arch/pm.h> 32#include <asm/arch/pm.h>
33#include <asm/arch/pxa-regs.h> 33#include <asm/arch/pxa-regs.h>
34#include <asm/arch/pxa2xx-regs.h>
34#include <asm/arch/sharpsl.h> 35#include <asm/arch/sharpsl.h>
35#include <asm/hardware/sharpsl_pm.h> 36#include <asm/hardware/sharpsl_pm.h>
36 37
@@ -157,6 +158,7 @@ static void sharpsl_battery_thread(struct work_struct *private_)
157 dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage, 158 dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage,
158 sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies); 159 sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies);
159 160
161#ifdef CONFIG_BACKLIGHT_CORGI
160 /* If battery is low. limit backlight intensity to save power. */ 162 /* If battery is low. limit backlight intensity to save power. */
161 if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE) 163 if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
162 && ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW) || 164 && ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW) ||
@@ -169,6 +171,7 @@ static void sharpsl_battery_thread(struct work_struct *private_)
169 sharpsl_pm.machinfo->backlight_limit(0); 171 sharpsl_pm.machinfo->backlight_limit(0);
170 sharpsl_pm.flags &= ~SHARPSL_BL_LIMIT; 172 sharpsl_pm.flags &= ~SHARPSL_BL_LIMIT;
171 } 173 }
174#endif
172 175
173 /* Suspend if critical battery level */ 176 /* Suspend if critical battery level */
174 if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE) 177 if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig
deleted file mode 100644
index 6bea0901bdf0..000000000000
--- a/arch/arm/configs/em_x270_defconfig
+++ /dev/null
@@ -1,1265 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22
4# Mon Jul 9 15:18:20 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10# CONFIG_GENERIC_CLOCKEVENTS is not set
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_ARCH_MTD_XIP=y
26CONFIG_VECTORS_BASE=0xffff0000
27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
28
29#
30# Code maturity level options
31#
32CONFIG_EXPERIMENTAL=y
33CONFIG_BROKEN_ON_SMP=y
34CONFIG_INIT_ENV_ARG_LIMIT=32
35
36#
37# General setup
38#
39CONFIG_LOCALVERSION="-em-x270"
40# CONFIG_LOCALVERSION_AUTO is not set
41CONFIG_SWAP=y
42CONFIG_SYSVIPC=y
43# CONFIG_IPC_NS is not set
44CONFIG_SYSVIPC_SYSCTL=y
45# CONFIG_POSIX_MQUEUE is not set
46# CONFIG_BSD_PROCESS_ACCT is not set
47# CONFIG_TASKSTATS is not set
48# CONFIG_UTS_NS is not set
49# CONFIG_AUDIT is not set
50CONFIG_IKCONFIG=y
51CONFIG_IKCONFIG_PROC=y
52CONFIG_LOG_BUF_SHIFT=17
53CONFIG_SYSFS_DEPRECATED=y
54# CONFIG_RELAY is not set
55CONFIG_BLK_DEV_INITRD=y
56CONFIG_INITRAMFS_SOURCE=""
57CONFIG_CC_OPTIMIZE_FOR_SIZE=y
58CONFIG_SYSCTL=y
59CONFIG_EMBEDDED=y
60CONFIG_UID16=y
61CONFIG_SYSCTL_SYSCALL=y
62CONFIG_KALLSYMS=y
63# CONFIG_KALLSYMS_ALL is not set
64# CONFIG_KALLSYMS_EXTRA_PASS is not set
65CONFIG_HOTPLUG=y
66CONFIG_PRINTK=y
67CONFIG_BUG=y
68CONFIG_ELF_CORE=y
69CONFIG_BASE_FULL=y
70CONFIG_FUTEX=y
71CONFIG_ANON_INODES=y
72CONFIG_EPOLL=y
73CONFIG_SIGNALFD=y
74CONFIG_TIMERFD=y
75CONFIG_EVENTFD=y
76CONFIG_SHMEM=y
77CONFIG_VM_EVENT_COUNTERS=y
78CONFIG_SLAB=y
79# CONFIG_SLUB is not set
80# CONFIG_SLOB is not set
81CONFIG_RT_MUTEXES=y
82# CONFIG_TINY_SHMEM is not set
83CONFIG_BASE_SMALL=0
84
85#
86# Loadable module support
87#
88CONFIG_MODULES=y
89CONFIG_MODULE_UNLOAD=y
90CONFIG_MODULE_FORCE_UNLOAD=y
91# CONFIG_MODVERSIONS is not set
92# CONFIG_MODULE_SRCVERSION_ALL is not set
93CONFIG_KMOD=y
94
95#
96# Block layer
97#
98CONFIG_BLOCK=y
99# CONFIG_LBD is not set
100# CONFIG_BLK_DEV_IO_TRACE is not set
101# CONFIG_LSF is not set
102
103#
104# IO Schedulers
105#
106CONFIG_IOSCHED_NOOP=y
107CONFIG_IOSCHED_AS=y
108CONFIG_IOSCHED_DEADLINE=y
109CONFIG_IOSCHED_CFQ=y
110CONFIG_DEFAULT_AS=y
111# CONFIG_DEFAULT_DEADLINE is not set
112# CONFIG_DEFAULT_CFQ is not set
113# CONFIG_DEFAULT_NOOP is not set
114CONFIG_DEFAULT_IOSCHED="anticipatory"
115
116#
117# System Type
118#
119# CONFIG_ARCH_AAEC2000 is not set
120# CONFIG_ARCH_INTEGRATOR is not set
121# CONFIG_ARCH_REALVIEW is not set
122# CONFIG_ARCH_VERSATILE is not set
123# CONFIG_ARCH_AT91 is not set
124# CONFIG_ARCH_CLPS7500 is not set
125# CONFIG_ARCH_CLPS711X is not set
126# CONFIG_ARCH_CO285 is not set
127# CONFIG_ARCH_EBSA110 is not set
128# CONFIG_ARCH_EP93XX is not set
129# CONFIG_ARCH_FOOTBRIDGE is not set
130# CONFIG_ARCH_NETX is not set
131# CONFIG_ARCH_H720X is not set
132# CONFIG_ARCH_IMX is not set
133# CONFIG_ARCH_IOP13XX is not set
134# CONFIG_ARCH_IOP32X is not set
135# CONFIG_ARCH_IOP33X is not set
136# CONFIG_ARCH_IXP23XX is not set
137# CONFIG_ARCH_IXP2000 is not set
138# CONFIG_ARCH_IXP4XX is not set
139# CONFIG_ARCH_L7200 is not set
140# CONFIG_ARCH_KS8695 is not set
141# CONFIG_ARCH_NS9XXX is not set
142# CONFIG_ARCH_PNX4008 is not set
143CONFIG_ARCH_PXA=y
144# CONFIG_ARCH_RPC is not set
145# CONFIG_ARCH_SA1100 is not set
146# CONFIG_ARCH_S3C2410 is not set
147# CONFIG_ARCH_SHARK is not set
148# CONFIG_ARCH_LH7A40X is not set
149# CONFIG_ARCH_DAVINCI is not set
150# CONFIG_ARCH_OMAP is not set
151
152#
153# Intel PXA2xx Implementations
154#
155# CONFIG_ARCH_LUBBOCK is not set
156# CONFIG_MACH_LOGICPD_PXA270 is not set
157# CONFIG_MACH_MAINSTONE is not set
158# CONFIG_ARCH_PXA_IDP is not set
159# CONFIG_PXA_SHARPSL is not set
160# CONFIG_MACH_TRIZEPS4 is not set
161CONFIG_MACH_EM_X270=y
162CONFIG_PXA27x=y
163
164#
165# Processor Type
166#
167CONFIG_CPU_32=y
168CONFIG_CPU_XSCALE=y
169CONFIG_CPU_32v5=y
170CONFIG_CPU_ABRT_EV5T=y
171CONFIG_CPU_CACHE_VIVT=y
172CONFIG_CPU_TLB_V4WBI=y
173CONFIG_CPU_CP15=y
174CONFIG_CPU_CP15_MMU=y
175
176#
177# Processor Features
178#
179CONFIG_ARM_THUMB=y
180# CONFIG_CPU_DCACHE_DISABLE is not set
181# CONFIG_OUTER_CACHE is not set
182CONFIG_IWMMXT=y
183CONFIG_XSCALE_PMU=y
184
185#
186# Bus support
187#
188# CONFIG_ARCH_SUPPORTS_MSI is not set
189
190#
191# PCCARD (PCMCIA/CardBus) support
192#
193# CONFIG_PCCARD is not set
194
195#
196# Kernel Features
197#
198# CONFIG_TICK_ONESHOT is not set
199# CONFIG_PREEMPT is not set
200# CONFIG_NO_IDLE_HZ is not set
201CONFIG_HZ=100
202CONFIG_AEABI=y
203CONFIG_OABI_COMPAT=y
204# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
205CONFIG_SELECT_MEMORY_MODEL=y
206CONFIG_FLATMEM_MANUAL=y
207# CONFIG_DISCONTIGMEM_MANUAL is not set
208# CONFIG_SPARSEMEM_MANUAL is not set
209CONFIG_FLATMEM=y
210CONFIG_FLAT_NODE_MEM_MAP=y
211# CONFIG_SPARSEMEM_STATIC is not set
212CONFIG_SPLIT_PTLOCK_CPUS=4096
213# CONFIG_RESOURCES_64BIT is not set
214CONFIG_ZONE_DMA_FLAG=1
215CONFIG_ALIGNMENT_TRAP=y
216
217#
218# Boot options
219#
220CONFIG_ZBOOT_ROM_TEXT=0x0
221CONFIG_ZBOOT_ROM_BSS=0x0
222CONFIG_CMDLINE=""
223# CONFIG_XIP_KERNEL is not set
224# CONFIG_KEXEC is not set
225
226#
227# Floating point emulation
228#
229
230#
231# At least one emulation must be selected
232#
233CONFIG_FPE_NWFPE=y
234# CONFIG_FPE_NWFPE_XP is not set
235# CONFIG_FPE_FASTFPE is not set
236
237#
238# Userspace binary formats
239#
240CONFIG_BINFMT_ELF=y
241# CONFIG_BINFMT_AOUT is not set
242# CONFIG_BINFMT_MISC is not set
243
244#
245# Power management options
246#
247CONFIG_PM=y
248CONFIG_PM_LEGACY=y
249# CONFIG_PM_DEBUG is not set
250# CONFIG_PM_SYSFS_DEPRECATED is not set
251CONFIG_APM_EMULATION=m
252
253#
254# Networking
255#
256CONFIG_NET=y
257
258#
259# Networking options
260#
261CONFIG_PACKET=y
262# CONFIG_PACKET_MMAP is not set
263CONFIG_UNIX=y
264CONFIG_XFRM=y
265# CONFIG_XFRM_USER is not set
266# CONFIG_XFRM_SUB_POLICY is not set
267# CONFIG_XFRM_MIGRATE is not set
268# CONFIG_NET_KEY is not set
269CONFIG_INET=y
270# CONFIG_IP_MULTICAST is not set
271# CONFIG_IP_ADVANCED_ROUTER is not set
272CONFIG_IP_FIB_HASH=y
273CONFIG_IP_PNP=y
274CONFIG_IP_PNP_DHCP=y
275CONFIG_IP_PNP_BOOTP=y
276# CONFIG_IP_PNP_RARP is not set
277# CONFIG_NET_IPIP is not set
278# CONFIG_NET_IPGRE is not set
279# CONFIG_ARPD is not set
280# CONFIG_SYN_COOKIES is not set
281# CONFIG_INET_AH is not set
282# CONFIG_INET_ESP is not set
283# CONFIG_INET_IPCOMP is not set
284# CONFIG_INET_XFRM_TUNNEL is not set
285# CONFIG_INET_TUNNEL is not set
286CONFIG_INET_XFRM_MODE_TRANSPORT=y
287CONFIG_INET_XFRM_MODE_TUNNEL=y
288CONFIG_INET_XFRM_MODE_BEET=y
289CONFIG_INET_DIAG=y
290CONFIG_INET_TCP_DIAG=y
291# CONFIG_TCP_CONG_ADVANCED is not set
292CONFIG_TCP_CONG_CUBIC=y
293CONFIG_DEFAULT_TCP_CONG="cubic"
294# CONFIG_TCP_MD5SIG is not set
295# CONFIG_IPV6 is not set
296# CONFIG_INET6_XFRM_TUNNEL is not set
297# CONFIG_INET6_TUNNEL is not set
298# CONFIG_NETWORK_SECMARK is not set
299# CONFIG_NETFILTER is not set
300# CONFIG_IP_DCCP is not set
301# CONFIG_IP_SCTP is not set
302# CONFIG_TIPC is not set
303# CONFIG_ATM is not set
304# CONFIG_BRIDGE is not set
305# CONFIG_VLAN_8021Q is not set
306# CONFIG_DECNET is not set
307# CONFIG_LLC2 is not set
308# CONFIG_IPX is not set
309# CONFIG_ATALK is not set
310# CONFIG_X25 is not set
311# CONFIG_LAPB is not set
312# CONFIG_ECONET is not set
313# CONFIG_WAN_ROUTER is not set
314
315#
316# QoS and/or fair queueing
317#
318# CONFIG_NET_SCHED is not set
319
320#
321# Network testing
322#
323# CONFIG_NET_PKTGEN is not set
324# CONFIG_HAMRADIO is not set
325# CONFIG_IRDA is not set
326CONFIG_BT=m
327CONFIG_BT_L2CAP=m
328CONFIG_BT_SCO=m
329CONFIG_BT_RFCOMM=m
330# CONFIG_BT_RFCOMM_TTY is not set
331CONFIG_BT_BNEP=m
332# CONFIG_BT_BNEP_MC_FILTER is not set
333# CONFIG_BT_BNEP_PROTO_FILTER is not set
334CONFIG_BT_HIDP=m
335
336#
337# Bluetooth device drivers
338#
339CONFIG_BT_HCIUSB=m
340# CONFIG_BT_HCIUSB_SCO is not set
341CONFIG_BT_HCIUART=m
342# CONFIG_BT_HCIUART_H4 is not set
343# CONFIG_BT_HCIUART_BCSP is not set
344CONFIG_BT_HCIBCM203X=m
345CONFIG_BT_HCIBPA10X=m
346CONFIG_BT_HCIBFUSB=m
347# CONFIG_BT_HCIVHCI is not set
348# CONFIG_AF_RXRPC is not set
349
350#
351# Wireless
352#
353# CONFIG_CFG80211 is not set
354# CONFIG_WIRELESS_EXT is not set
355# CONFIG_MAC80211 is not set
356CONFIG_IEEE80211=m
357# CONFIG_IEEE80211_DEBUG is not set
358CONFIG_IEEE80211_CRYPT_WEP=m
359CONFIG_IEEE80211_CRYPT_CCMP=m
360# CONFIG_IEEE80211_CRYPT_TKIP is not set
361# CONFIG_IEEE80211_SOFTMAC is not set
362# CONFIG_RFKILL is not set
363
364#
365# Device Drivers
366#
367
368#
369# Generic Driver Options
370#
371CONFIG_STANDALONE=y
372CONFIG_PREVENT_FIRMWARE_BUILD=y
373CONFIG_FW_LOADER=y
374# CONFIG_DEBUG_DRIVER is not set
375# CONFIG_DEBUG_DEVRES is not set
376# CONFIG_SYS_HYPERVISOR is not set
377
378#
379# Connector - unified userspace <-> kernelspace linker
380#
381# CONFIG_CONNECTOR is not set
382CONFIG_MTD=y
383# CONFIG_MTD_DEBUG is not set
384CONFIG_MTD_CONCAT=y
385CONFIG_MTD_PARTITIONS=y
386# CONFIG_MTD_REDBOOT_PARTS is not set
387# CONFIG_MTD_CMDLINE_PARTS is not set
388# CONFIG_MTD_AFS_PARTS is not set
389
390#
391# User Modules And Translation Layers
392#
393CONFIG_MTD_CHAR=y
394CONFIG_MTD_BLKDEVS=y
395CONFIG_MTD_BLOCK=y
396# CONFIG_FTL is not set
397# CONFIG_NFTL is not set
398# CONFIG_INFTL is not set
399# CONFIG_RFD_FTL is not set
400# CONFIG_SSFDC is not set
401
402#
403# RAM/ROM/Flash chip drivers
404#
405# CONFIG_MTD_CFI is not set
406# CONFIG_MTD_JEDECPROBE is not set
407# CONFIG_MTD_CFI_NOSWAP is not set
408# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
409# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
410CONFIG_MTD_MAP_BANK_WIDTH_1=y
411CONFIG_MTD_MAP_BANK_WIDTH_2=y
412CONFIG_MTD_MAP_BANK_WIDTH_4=y
413# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
414# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
415# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
416CONFIG_MTD_CFI_I1=y
417CONFIG_MTD_CFI_I2=y
418# CONFIG_MTD_CFI_I4 is not set
419# CONFIG_MTD_CFI_I8 is not set
420# CONFIG_MTD_RAM is not set
421# CONFIG_MTD_ROM is not set
422# CONFIG_MTD_ABSENT is not set
423
424#
425# Mapping drivers for chip access
426#
427# CONFIG_MTD_COMPLEX_MAPPINGS is not set
428# CONFIG_MTD_SHARP_SL is not set
429# CONFIG_MTD_PLATRAM is not set
430
431#
432# Self-contained MTD device drivers
433#
434# CONFIG_MTD_SLRAM is not set
435# CONFIG_MTD_PHRAM is not set
436# CONFIG_MTD_MTDRAM is not set
437# CONFIG_MTD_BLOCK2MTD is not set
438
439#
440# Disk-On-Chip Device Drivers
441#
442# CONFIG_MTD_DOC2000 is not set
443# CONFIG_MTD_DOC2001 is not set
444# CONFIG_MTD_DOC2001PLUS is not set
445CONFIG_MTD_NAND=y
446# CONFIG_MTD_NAND_VERIFY_WRITE is not set
447# CONFIG_MTD_NAND_ECC_SMC is not set
448# CONFIG_MTD_NAND_MUSEUM_IDS is not set
449# CONFIG_MTD_NAND_H1900 is not set
450CONFIG_MTD_NAND_IDS=y
451# CONFIG_MTD_NAND_DISKONCHIP is not set
452# CONFIG_MTD_NAND_SHARPSL is not set
453# CONFIG_MTD_NAND_NANDSIM is not set
454CONFIG_MTD_NAND_PLATFORM=y
455# CONFIG_MTD_ONENAND is not set
456
457#
458# UBI - Unsorted block images
459#
460# CONFIG_MTD_UBI is not set
461
462#
463# Parallel port support
464#
465# CONFIG_PARPORT is not set
466
467#
468# Plug and Play support
469#
470# CONFIG_PNPACPI is not set
471
472#
473# Block devices
474#
475# CONFIG_BLK_DEV_COW_COMMON is not set
476CONFIG_BLK_DEV_LOOP=y
477# CONFIG_BLK_DEV_CRYPTOLOOP is not set
478# CONFIG_BLK_DEV_NBD is not set
479# CONFIG_BLK_DEV_UB is not set
480CONFIG_BLK_DEV_RAM=y
481CONFIG_BLK_DEV_RAM_COUNT=16
482CONFIG_BLK_DEV_RAM_SIZE=12000
483CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
484# CONFIG_CDROM_PKTCDVD is not set
485# CONFIG_ATA_OVER_ETH is not set
486# CONFIG_IDE is not set
487
488#
489# SCSI device support
490#
491# CONFIG_RAID_ATTRS is not set
492CONFIG_SCSI=y
493# CONFIG_SCSI_TGT is not set
494# CONFIG_SCSI_NETLINK is not set
495# CONFIG_SCSI_PROC_FS is not set
496
497#
498# SCSI support type (disk, tape, CD-ROM)
499#
500CONFIG_BLK_DEV_SD=y
501# CONFIG_CHR_DEV_ST is not set
502# CONFIG_CHR_DEV_OSST is not set
503# CONFIG_BLK_DEV_SR is not set
504# CONFIG_CHR_DEV_SG is not set
505# CONFIG_CHR_DEV_SCH is not set
506
507#
508# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
509#
510# CONFIG_SCSI_MULTI_LUN is not set
511# CONFIG_SCSI_CONSTANTS is not set
512# CONFIG_SCSI_LOGGING is not set
513# CONFIG_SCSI_SCAN_ASYNC is not set
514CONFIG_SCSI_WAIT_SCAN=m
515
516#
517# SCSI Transports
518#
519# CONFIG_SCSI_SPI_ATTRS is not set
520# CONFIG_SCSI_FC_ATTRS is not set
521# CONFIG_SCSI_ISCSI_ATTRS is not set
522# CONFIG_SCSI_SAS_ATTRS is not set
523# CONFIG_SCSI_SAS_LIBSAS is not set
524
525#
526# SCSI low-level drivers
527#
528# CONFIG_ISCSI_TCP is not set
529# CONFIG_SCSI_DEBUG is not set
530# CONFIG_ATA is not set
531
532#
533# Multi-device support (RAID and LVM)
534#
535# CONFIG_MD is not set
536
537#
538# Network device support
539#
540CONFIG_NETDEVICES=y
541# CONFIG_DUMMY is not set
542# CONFIG_BONDING is not set
543# CONFIG_EQUALIZER is not set
544# CONFIG_TUN is not set
545# CONFIG_PHYLIB is not set
546
547#
548# Ethernet (10 or 100Mbit)
549#
550CONFIG_NET_ETHERNET=y
551CONFIG_MII=y
552# CONFIG_SMC91X is not set
553CONFIG_DM9000=y
554# CONFIG_SMC911X is not set
555# CONFIG_NETDEV_1000 is not set
556# CONFIG_NETDEV_10000 is not set
557
558#
559# Wireless LAN
560#
561# CONFIG_WLAN_PRE80211 is not set
562# CONFIG_WLAN_80211 is not set
563
564#
565# USB Network Adapters
566#
567# CONFIG_USB_CATC is not set
568# CONFIG_USB_KAWETH is not set
569# CONFIG_USB_PEGASUS is not set
570# CONFIG_USB_RTL8150 is not set
571# CONFIG_USB_USBNET_MII is not set
572# CONFIG_USB_USBNET is not set
573# CONFIG_WAN is not set
574# CONFIG_PPP is not set
575# CONFIG_SLIP is not set
576# CONFIG_SHAPER is not set
577# CONFIG_NETCONSOLE is not set
578# CONFIG_NETPOLL is not set
579# CONFIG_NET_POLL_CONTROLLER is not set
580
581#
582# ISDN subsystem
583#
584# CONFIG_ISDN is not set
585
586#
587# Input device support
588#
589CONFIG_INPUT=y
590# CONFIG_INPUT_FF_MEMLESS is not set
591# CONFIG_INPUT_POLLDEV is not set
592
593#
594# Userland interfaces
595#
596CONFIG_INPUT_MOUSEDEV=y
597# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
598CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
599CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
600# CONFIG_INPUT_JOYDEV is not set
601# CONFIG_INPUT_TSDEV is not set
602CONFIG_INPUT_EVDEV=y
603# CONFIG_INPUT_EVBUG is not set
604
605#
606# Input Device Drivers
607#
608CONFIG_INPUT_KEYBOARD=y
609# CONFIG_KEYBOARD_ATKBD is not set
610# CONFIG_KEYBOARD_SUNKBD is not set
611# CONFIG_KEYBOARD_LKKBD is not set
612# CONFIG_KEYBOARD_XTKBD is not set
613# CONFIG_KEYBOARD_NEWTON is not set
614# CONFIG_KEYBOARD_STOWAWAY is not set
615CONFIG_KEYBOARD_PXA27x=m
616# CONFIG_KEYBOARD_GPIO is not set
617# CONFIG_INPUT_MOUSE is not set
618# CONFIG_INPUT_JOYSTICK is not set
619# CONFIG_INPUT_TABLET is not set
620CONFIG_INPUT_TOUCHSCREEN=y
621# CONFIG_TOUCHSCREEN_GUNZE is not set
622# CONFIG_TOUCHSCREEN_ELO is not set
623# CONFIG_TOUCHSCREEN_MTOUCH is not set
624# CONFIG_TOUCHSCREEN_MK712 is not set
625# CONFIG_TOUCHSCREEN_PENMOUNT is not set
626# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
627# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
628# CONFIG_TOUCHSCREEN_UCB1400 is not set
629# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
630# CONFIG_INPUT_MISC is not set
631
632#
633# Hardware I/O ports
634#
635CONFIG_SERIO=y
636# CONFIG_SERIO_SERPORT is not set
637CONFIG_SERIO_LIBPS2=y
638# CONFIG_SERIO_RAW is not set
639# CONFIG_GAMEPORT is not set
640
641#
642# Character devices
643#
644CONFIG_VT=y
645CONFIG_VT_CONSOLE=y
646CONFIG_HW_CONSOLE=y
647# CONFIG_VT_HW_CONSOLE_BINDING is not set
648# CONFIG_SERIAL_NONSTANDARD is not set
649
650#
651# Serial drivers
652#
653# CONFIG_SERIAL_8250 is not set
654
655#
656# Non-8250 serial port support
657#
658CONFIG_SERIAL_PXA=y
659CONFIG_SERIAL_PXA_CONSOLE=y
660CONFIG_SERIAL_CORE=y
661CONFIG_SERIAL_CORE_CONSOLE=y
662CONFIG_UNIX98_PTYS=y
663CONFIG_LEGACY_PTYS=y
664CONFIG_LEGACY_PTY_COUNT=256
665
666#
667# IPMI
668#
669# CONFIG_IPMI_HANDLER is not set
670# CONFIG_WATCHDOG is not set
671CONFIG_HW_RANDOM=m
672# CONFIG_NVRAM is not set
673# CONFIG_R3964 is not set
674# CONFIG_RAW_DRIVER is not set
675
676#
677# TPM devices
678#
679# CONFIG_TCG_TPM is not set
680# CONFIG_I2C is not set
681
682#
683# SPI support
684#
685# CONFIG_SPI is not set
686# CONFIG_SPI_MASTER is not set
687
688#
689# Dallas's 1-wire bus
690#
691# CONFIG_W1 is not set
692# CONFIG_HWMON is not set
693
694#
695# Misc devices
696#
697
698#
699# Multifunction device drivers
700#
701# CONFIG_MFD_SM501 is not set
702
703#
704# LED devices
705#
706# CONFIG_NEW_LEDS is not set
707
708#
709# LED drivers
710#
711
712#
713# LED Triggers
714#
715
716#
717# Multimedia devices
718#
719# CONFIG_VIDEO_DEV is not set
720# CONFIG_DVB_CORE is not set
721# CONFIG_DAB is not set
722
723#
724# Graphics support
725#
726# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
727
728#
729# Display device support
730#
731# CONFIG_DISPLAY_SUPPORT is not set
732# CONFIG_VGASTATE is not set
733CONFIG_FB=y
734# CONFIG_FIRMWARE_EDID is not set
735# CONFIG_FB_DDC is not set
736CONFIG_FB_CFB_FILLRECT=y
737CONFIG_FB_CFB_COPYAREA=y
738CONFIG_FB_CFB_IMAGEBLIT=y
739# CONFIG_FB_SYS_FILLRECT is not set
740# CONFIG_FB_SYS_COPYAREA is not set
741# CONFIG_FB_SYS_IMAGEBLIT is not set
742# CONFIG_FB_SYS_FOPS is not set
743CONFIG_FB_DEFERRED_IO=y
744# CONFIG_FB_SVGALIB is not set
745# CONFIG_FB_MACMODES is not set
746# CONFIG_FB_BACKLIGHT is not set
747# CONFIG_FB_MODE_HELPERS is not set
748# CONFIG_FB_TILEBLITTING is not set
749
750#
751# Frame buffer hardware drivers
752#
753# CONFIG_FB_S1D13XXX is not set
754CONFIG_FB_PXA=y
755# CONFIG_FB_PXA_PARAMETERS is not set
756# CONFIG_FB_MBX is not set
757# CONFIG_FB_VIRTUAL is not set
758
759#
760# Console display driver support
761#
762# CONFIG_VGA_CONSOLE is not set
763CONFIG_DUMMY_CONSOLE=y
764CONFIG_FRAMEBUFFER_CONSOLE=y
765# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
766# CONFIG_FONTS is not set
767CONFIG_FONT_8x8=y
768CONFIG_FONT_8x16=y
769CONFIG_LOGO=y
770CONFIG_LOGO_LINUX_MONO=y
771CONFIG_LOGO_LINUX_VGA16=y
772CONFIG_LOGO_LINUX_CLUT224=y
773
774#
775# Sound
776#
777CONFIG_SOUND=m
778
779#
780# Advanced Linux Sound Architecture
781#
782CONFIG_SND=m
783CONFIG_SND_TIMER=m
784CONFIG_SND_PCM=m
785# CONFIG_SND_SEQUENCER is not set
786CONFIG_SND_OSSEMUL=y
787CONFIG_SND_MIXER_OSS=m
788CONFIG_SND_PCM_OSS=m
789CONFIG_SND_PCM_OSS_PLUGINS=y
790# CONFIG_SND_DYNAMIC_MINORS is not set
791CONFIG_SND_SUPPORT_OLD_API=y
792CONFIG_SND_VERBOSE_PROCFS=y
793# CONFIG_SND_VERBOSE_PRINTK is not set
794# CONFIG_SND_DEBUG is not set
795
796#
797# Generic devices
798#
799CONFIG_SND_AC97_CODEC=m
800# CONFIG_SND_DUMMY is not set
801# CONFIG_SND_MTPAV is not set
802# CONFIG_SND_SERIAL_U16550 is not set
803# CONFIG_SND_MPU401 is not set
804
805#
806# ALSA ARM devices
807#
808CONFIG_SND_PXA2XX_PCM=m
809CONFIG_SND_PXA2XX_AC97=m
810
811#
812# USB devices
813#
814# CONFIG_SND_USB_AUDIO is not set
815# CONFIG_SND_USB_CAIAQ is not set
816
817#
818# System on Chip audio support
819#
820# CONFIG_SND_SOC is not set
821
822#
823# Open Sound System
824#
825# CONFIG_SOUND_PRIME is not set
826CONFIG_AC97_BUS=m
827
828#
829# HID Devices
830#
831CONFIG_HID=y
832# CONFIG_HID_DEBUG is not set
833
834#
835# USB Input Devices
836#
837CONFIG_USB_HID=y
838# CONFIG_USB_HIDINPUT_POWERBOOK is not set
839# CONFIG_HID_FF is not set
840# CONFIG_USB_HIDDEV is not set
841
842#
843# USB support
844#
845CONFIG_USB_ARCH_HAS_HCD=y
846CONFIG_USB_ARCH_HAS_OHCI=y
847# CONFIG_USB_ARCH_HAS_EHCI is not set
848CONFIG_USB=y
849# CONFIG_USB_DEBUG is not set
850
851#
852# Miscellaneous USB options
853#
854CONFIG_USB_DEVICEFS=y
855# CONFIG_USB_DEVICE_CLASS is not set
856# CONFIG_USB_DYNAMIC_MINORS is not set
857# CONFIG_USB_SUSPEND is not set
858# CONFIG_USB_OTG is not set
859
860#
861# USB Host Controller Drivers
862#
863# CONFIG_USB_ISP116X_HCD is not set
864CONFIG_USB_OHCI_HCD=y
865# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
866# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
867CONFIG_USB_OHCI_LITTLE_ENDIAN=y
868# CONFIG_USB_SL811_HCD is not set
869
870#
871# USB Device Class drivers
872#
873# CONFIG_USB_ACM is not set
874# CONFIG_USB_PRINTER is not set
875
876#
877# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
878#
879
880#
881# may also be needed; see USB_STORAGE Help for more information
882#
883CONFIG_USB_STORAGE=y
884# CONFIG_USB_STORAGE_DEBUG is not set
885# CONFIG_USB_STORAGE_DATAFAB is not set
886# CONFIG_USB_STORAGE_FREECOM is not set
887# CONFIG_USB_STORAGE_DPCM is not set
888# CONFIG_USB_STORAGE_USBAT is not set
889# CONFIG_USB_STORAGE_SDDR09 is not set
890# CONFIG_USB_STORAGE_SDDR55 is not set
891# CONFIG_USB_STORAGE_JUMPSHOT is not set
892# CONFIG_USB_STORAGE_ALAUDA is not set
893# CONFIG_USB_STORAGE_KARMA is not set
894# CONFIG_USB_LIBUSUAL is not set
895
896#
897# USB Imaging devices
898#
899# CONFIG_USB_MDC800 is not set
900# CONFIG_USB_MICROTEK is not set
901# CONFIG_USB_MON is not set
902
903#
904# USB port drivers
905#
906
907#
908# USB Serial Converter support
909#
910# CONFIG_USB_SERIAL is not set
911
912#
913# USB Miscellaneous drivers
914#
915# CONFIG_USB_EMI62 is not set
916# CONFIG_USB_EMI26 is not set
917# CONFIG_USB_ADUTUX is not set
918# CONFIG_USB_AUERSWALD is not set
919# CONFIG_USB_RIO500 is not set
920# CONFIG_USB_LEGOTOWER is not set
921# CONFIG_USB_LCD is not set
922# CONFIG_USB_BERRY_CHARGE is not set
923# CONFIG_USB_LED is not set
924# CONFIG_USB_CYPRESS_CY7C63 is not set
925# CONFIG_USB_CYTHERM is not set
926# CONFIG_USB_PHIDGET is not set
927# CONFIG_USB_IDMOUSE is not set
928# CONFIG_USB_FTDI_ELAN is not set
929# CONFIG_USB_APPLEDISPLAY is not set
930# CONFIG_USB_LD is not set
931# CONFIG_USB_TRANCEVIBRATOR is not set
932# CONFIG_USB_IOWARRIOR is not set
933# CONFIG_USB_TEST is not set
934
935#
936# USB DSL modem support
937#
938
939#
940# USB Gadget Support
941#
942# CONFIG_USB_GADGET is not set
943CONFIG_MMC=m
944# CONFIG_MMC_DEBUG is not set
945# CONFIG_MMC_UNSAFE_RESUME is not set
946
947#
948# MMC/SD Card Drivers
949#
950CONFIG_MMC_BLOCK=m
951
952#
953# MMC/SD Host Controller Drivers
954#
955CONFIG_MMC_PXA=m
956
957#
958# Real Time Clock
959#
960CONFIG_RTC_LIB=y
961CONFIG_RTC_CLASS=m
962
963#
964# RTC interfaces
965#
966CONFIG_RTC_INTF_SYSFS=y
967CONFIG_RTC_INTF_PROC=y
968CONFIG_RTC_INTF_DEV=y
969# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
970# CONFIG_RTC_DRV_TEST is not set
971
972#
973# I2C RTC drivers
974#
975
976#
977# SPI RTC drivers
978#
979
980#
981# Platform RTC drivers
982#
983# CONFIG_RTC_DRV_CMOS is not set
984# CONFIG_RTC_DRV_DS1553 is not set
985# CONFIG_RTC_DRV_DS1742 is not set
986# CONFIG_RTC_DRV_M48T86 is not set
987CONFIG_RTC_DRV_V3020=m
988
989#
990# on-CPU RTC drivers
991#
992CONFIG_RTC_DRV_SA1100=m
993
994#
995# File systems
996#
997CONFIG_EXT2_FS=y
998# CONFIG_EXT2_FS_XATTR is not set
999# CONFIG_EXT2_FS_XIP is not set
1000CONFIG_EXT3_FS=y
1001CONFIG_EXT3_FS_XATTR=y
1002# CONFIG_EXT3_FS_POSIX_ACL is not set
1003# CONFIG_EXT3_FS_SECURITY is not set
1004# CONFIG_EXT4DEV_FS is not set
1005CONFIG_JBD=y
1006# CONFIG_JBD_DEBUG is not set
1007CONFIG_FS_MBCACHE=y
1008# CONFIG_REISERFS_FS is not set
1009# CONFIG_JFS_FS is not set
1010# CONFIG_FS_POSIX_ACL is not set
1011# CONFIG_XFS_FS is not set
1012# CONFIG_GFS2_FS is not set
1013# CONFIG_OCFS2_FS is not set
1014# CONFIG_MINIX_FS is not set
1015# CONFIG_ROMFS_FS is not set
1016CONFIG_INOTIFY=y
1017CONFIG_INOTIFY_USER=y
1018# CONFIG_QUOTA is not set
1019CONFIG_DNOTIFY=y
1020# CONFIG_AUTOFS_FS is not set
1021# CONFIG_AUTOFS4_FS is not set
1022# CONFIG_FUSE_FS is not set
1023
1024#
1025# CD-ROM/DVD Filesystems
1026#
1027# CONFIG_ISO9660_FS is not set
1028# CONFIG_UDF_FS is not set
1029
1030#
1031# DOS/FAT/NT Filesystems
1032#
1033CONFIG_FAT_FS=y
1034CONFIG_MSDOS_FS=y
1035CONFIG_VFAT_FS=y
1036CONFIG_FAT_DEFAULT_CODEPAGE=437
1037CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1038# CONFIG_NTFS_FS is not set
1039
1040#
1041# Pseudo filesystems
1042#
1043CONFIG_PROC_FS=y
1044CONFIG_PROC_SYSCTL=y
1045CONFIG_SYSFS=y
1046CONFIG_TMPFS=y
1047# CONFIG_TMPFS_POSIX_ACL is not set
1048# CONFIG_HUGETLB_PAGE is not set
1049CONFIG_RAMFS=y
1050# CONFIG_CONFIGFS_FS is not set
1051
1052#
1053# Miscellaneous filesystems
1054#
1055# CONFIG_ADFS_FS is not set
1056# CONFIG_AFFS_FS is not set
1057# CONFIG_HFS_FS is not set
1058# CONFIG_HFSPLUS_FS is not set
1059# CONFIG_BEFS_FS is not set
1060# CONFIG_BFS_FS is not set
1061# CONFIG_EFS_FS is not set
1062CONFIG_JFFS2_FS=y
1063CONFIG_JFFS2_FS_DEBUG=0
1064CONFIG_JFFS2_FS_WRITEBUFFER=y
1065CONFIG_JFFS2_SUMMARY=y
1066# CONFIG_JFFS2_FS_XATTR is not set
1067# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1068CONFIG_JFFS2_ZLIB=y
1069CONFIG_JFFS2_RTIME=y
1070# CONFIG_JFFS2_RUBIN is not set
1071# CONFIG_CRAMFS is not set
1072# CONFIG_VXFS_FS is not set
1073# CONFIG_HPFS_FS is not set
1074# CONFIG_QNX4FS_FS is not set
1075# CONFIG_SYSV_FS is not set
1076# CONFIG_UFS_FS is not set
1077
1078#
1079# Network File Systems
1080#
1081CONFIG_NFS_FS=y
1082CONFIG_NFS_V3=y
1083# CONFIG_NFS_V3_ACL is not set
1084# CONFIG_NFS_V4 is not set
1085# CONFIG_NFS_DIRECTIO is not set
1086# CONFIG_NFSD is not set
1087CONFIG_ROOT_NFS=y
1088CONFIG_LOCKD=y
1089CONFIG_LOCKD_V4=y
1090CONFIG_NFS_COMMON=y
1091CONFIG_SUNRPC=y
1092# CONFIG_SUNRPC_BIND34 is not set
1093# CONFIG_RPCSEC_GSS_KRB5 is not set
1094# CONFIG_RPCSEC_GSS_SPKM3 is not set
1095CONFIG_SMB_FS=y
1096# CONFIG_SMB_NLS_DEFAULT is not set
1097# CONFIG_CIFS is not set
1098# CONFIG_NCP_FS is not set
1099# CONFIG_CODA_FS is not set
1100# CONFIG_AFS_FS is not set
1101# CONFIG_9P_FS is not set
1102
1103#
1104# Partition Types
1105#
1106# CONFIG_PARTITION_ADVANCED is not set
1107CONFIG_MSDOS_PARTITION=y
1108
1109#
1110# Native Language Support
1111#
1112CONFIG_NLS=y
1113CONFIG_NLS_DEFAULT="iso8859-1"
1114CONFIG_NLS_CODEPAGE_437=y
1115# CONFIG_NLS_CODEPAGE_737 is not set
1116# CONFIG_NLS_CODEPAGE_775 is not set
1117# CONFIG_NLS_CODEPAGE_850 is not set
1118# CONFIG_NLS_CODEPAGE_852 is not set
1119# CONFIG_NLS_CODEPAGE_855 is not set
1120# CONFIG_NLS_CODEPAGE_857 is not set
1121# CONFIG_NLS_CODEPAGE_860 is not set
1122# CONFIG_NLS_CODEPAGE_861 is not set
1123# CONFIG_NLS_CODEPAGE_862 is not set
1124# CONFIG_NLS_CODEPAGE_863 is not set
1125# CONFIG_NLS_CODEPAGE_864 is not set
1126# CONFIG_NLS_CODEPAGE_865 is not set
1127# CONFIG_NLS_CODEPAGE_866 is not set
1128# CONFIG_NLS_CODEPAGE_869 is not set
1129# CONFIG_NLS_CODEPAGE_936 is not set
1130# CONFIG_NLS_CODEPAGE_950 is not set
1131# CONFIG_NLS_CODEPAGE_932 is not set
1132# CONFIG_NLS_CODEPAGE_949 is not set
1133# CONFIG_NLS_CODEPAGE_874 is not set
1134# CONFIG_NLS_ISO8859_8 is not set
1135# CONFIG_NLS_CODEPAGE_1250 is not set
1136# CONFIG_NLS_CODEPAGE_1251 is not set
1137# CONFIG_NLS_ASCII is not set
1138CONFIG_NLS_ISO8859_1=y
1139# CONFIG_NLS_ISO8859_2 is not set
1140# CONFIG_NLS_ISO8859_3 is not set
1141# CONFIG_NLS_ISO8859_4 is not set
1142# CONFIG_NLS_ISO8859_5 is not set
1143# CONFIG_NLS_ISO8859_6 is not set
1144# CONFIG_NLS_ISO8859_7 is not set
1145# CONFIG_NLS_ISO8859_9 is not set
1146# CONFIG_NLS_ISO8859_13 is not set
1147# CONFIG_NLS_ISO8859_14 is not set
1148# CONFIG_NLS_ISO8859_15 is not set
1149# CONFIG_NLS_KOI8_R is not set
1150# CONFIG_NLS_KOI8_U is not set
1151CONFIG_NLS_UTF8=y
1152
1153#
1154# Distributed Lock Manager
1155#
1156# CONFIG_DLM is not set
1157
1158#
1159# Profiling support
1160#
1161# CONFIG_PROFILING is not set
1162
1163#
1164# Kernel hacking
1165#
1166# CONFIG_PRINTK_TIME is not set
1167CONFIG_ENABLE_MUST_CHECK=y
1168CONFIG_MAGIC_SYSRQ=y
1169# CONFIG_UNUSED_SYMBOLS is not set
1170# CONFIG_DEBUG_FS is not set
1171# CONFIG_HEADERS_CHECK is not set
1172CONFIG_DEBUG_KERNEL=y
1173# CONFIG_DEBUG_SHIRQ is not set
1174# CONFIG_DETECT_SOFTLOCKUP is not set
1175# CONFIG_SCHEDSTATS is not set
1176# CONFIG_TIMER_STATS is not set
1177# CONFIG_DEBUG_SLAB is not set
1178# CONFIG_DEBUG_RT_MUTEXES is not set
1179# CONFIG_RT_MUTEX_TESTER is not set
1180# CONFIG_DEBUG_SPINLOCK is not set
1181# CONFIG_DEBUG_MUTEXES is not set
1182# CONFIG_DEBUG_LOCK_ALLOC is not set
1183# CONFIG_PROVE_LOCKING is not set
1184# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1185# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1186# CONFIG_DEBUG_KOBJECT is not set
1187# CONFIG_DEBUG_BUGVERBOSE is not set
1188CONFIG_DEBUG_INFO=y
1189# CONFIG_DEBUG_VM is not set
1190# CONFIG_DEBUG_LIST is not set
1191CONFIG_FRAME_POINTER=y
1192CONFIG_FORCED_INLINING=y
1193# CONFIG_RCU_TORTURE_TEST is not set
1194# CONFIG_FAULT_INJECTION is not set
1195CONFIG_DEBUG_USER=y
1196CONFIG_DEBUG_ERRORS=y
1197CONFIG_DEBUG_LL=y
1198# CONFIG_DEBUG_ICEDCC is not set
1199
1200#
1201# Security options
1202#
1203# CONFIG_KEYS is not set
1204# CONFIG_SECURITY is not set
1205
1206#
1207# Cryptographic options
1208#
1209CONFIG_CRYPTO=y
1210CONFIG_CRYPTO_ALGAPI=m
1211CONFIG_CRYPTO_BLKCIPHER=m
1212CONFIG_CRYPTO_MANAGER=m
1213# CONFIG_CRYPTO_HMAC is not set
1214# CONFIG_CRYPTO_XCBC is not set
1215# CONFIG_CRYPTO_NULL is not set
1216# CONFIG_CRYPTO_MD4 is not set
1217# CONFIG_CRYPTO_MD5 is not set
1218# CONFIG_CRYPTO_SHA1 is not set
1219# CONFIG_CRYPTO_SHA256 is not set
1220# CONFIG_CRYPTO_SHA512 is not set
1221# CONFIG_CRYPTO_WP512 is not set
1222# CONFIG_CRYPTO_TGR192 is not set
1223# CONFIG_CRYPTO_GF128MUL is not set
1224CONFIG_CRYPTO_ECB=m
1225CONFIG_CRYPTO_CBC=m
1226CONFIG_CRYPTO_PCBC=m
1227# CONFIG_CRYPTO_LRW is not set
1228# CONFIG_CRYPTO_CRYPTD is not set
1229# CONFIG_CRYPTO_DES is not set
1230# CONFIG_CRYPTO_FCRYPT is not set
1231# CONFIG_CRYPTO_BLOWFISH is not set
1232# CONFIG_CRYPTO_TWOFISH is not set
1233# CONFIG_CRYPTO_SERPENT is not set
1234CONFIG_CRYPTO_AES=m
1235# CONFIG_CRYPTO_CAST5 is not set
1236# CONFIG_CRYPTO_CAST6 is not set
1237# CONFIG_CRYPTO_TEA is not set
1238CONFIG_CRYPTO_ARC4=m
1239# CONFIG_CRYPTO_KHAZAD is not set
1240# CONFIG_CRYPTO_ANUBIS is not set
1241# CONFIG_CRYPTO_DEFLATE is not set
1242# CONFIG_CRYPTO_MICHAEL_MIC is not set
1243# CONFIG_CRYPTO_CRC32C is not set
1244# CONFIG_CRYPTO_CAMELLIA is not set
1245# CONFIG_CRYPTO_TEST is not set
1246
1247#
1248# Hardware crypto devices
1249#
1250
1251#
1252# Library routines
1253#
1254CONFIG_BITREVERSE=y
1255# CONFIG_CRC_CCITT is not set
1256# CONFIG_CRC16 is not set
1257# CONFIG_CRC_ITU_T is not set
1258CONFIG_CRC32=y
1259# CONFIG_LIBCRC32C is not set
1260CONFIG_ZLIB_INFLATE=y
1261CONFIG_ZLIB_DEFLATE=y
1262CONFIG_PLIST=y
1263CONFIG_HAS_IOMEM=y
1264CONFIG_HAS_IOPORT=y
1265CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/cm_x270_defconfig b/arch/arm/configs/xm_x270_defconfig
index 5cab08397ae7..7b3576e41e36 100644
--- a/arch/arm/configs/cm_x270_defconfig
+++ b/arch/arm/configs/xm_x270_defconfig
@@ -1,13 +1,13 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22 3# Linux kernel version: 2.6.25
4# Wed Jul 18 14:11:48 2007 4# Sun May 11 15:12:52 2008
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y 8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y 9CONFIG_GENERIC_TIME=y
10# CONFIG_GENERIC_CLOCKEVENTS is not set 10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y 11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set 12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y 13CONFIG_GENERIC_HARDIRQS=y
@@ -21,21 +21,18 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set 21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y 22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y 23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ARCH_SUPPORTS_AOUT=y
24CONFIG_ZONE_DMA=y 25CONFIG_ZONE_DMA=y
25CONFIG_ARCH_MTD_XIP=y 26CONFIG_ARCH_MTD_XIP=y
26CONFIG_VECTORS_BASE=0xffff0000 27CONFIG_VECTORS_BASE=0xffff0000
27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 28CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
28 29
29# 30#
30# Code maturity level options 31# General setup
31# 32#
32CONFIG_EXPERIMENTAL=y 33CONFIG_EXPERIMENTAL=y
33CONFIG_BROKEN_ON_SMP=y 34CONFIG_BROKEN_ON_SMP=y
34CONFIG_INIT_ENV_ARG_LIMIT=32 35CONFIG_INIT_ENV_ARG_LIMIT=32
35
36#
37# General setup
38#
39CONFIG_LOCALVERSION="" 36CONFIG_LOCALVERSION=""
40# CONFIG_LOCALVERSION_AUTO is not set 37# CONFIG_LOCALVERSION_AUTO is not set
41CONFIG_SWAP=y 38CONFIG_SWAP=y
@@ -44,13 +41,20 @@ CONFIG_SYSVIPC_SYSCTL=y
44# CONFIG_POSIX_MQUEUE is not set 41# CONFIG_POSIX_MQUEUE is not set
45# CONFIG_BSD_PROCESS_ACCT is not set 42# CONFIG_BSD_PROCESS_ACCT is not set
46# CONFIG_TASKSTATS is not set 43# CONFIG_TASKSTATS is not set
47# CONFIG_USER_NS is not set
48# CONFIG_AUDIT is not set 44# CONFIG_AUDIT is not set
49CONFIG_IKCONFIG=y 45CONFIG_IKCONFIG=y
50CONFIG_IKCONFIG_PROC=y 46CONFIG_IKCONFIG_PROC=y
51CONFIG_LOG_BUF_SHIFT=17 47CONFIG_LOG_BUF_SHIFT=14
48# CONFIG_CGROUPS is not set
49CONFIG_GROUP_SCHED=y
50CONFIG_FAIR_GROUP_SCHED=y
51# CONFIG_RT_GROUP_SCHED is not set
52CONFIG_USER_SCHED=y
53# CONFIG_CGROUP_SCHED is not set
52CONFIG_SYSFS_DEPRECATED=y 54CONFIG_SYSFS_DEPRECATED=y
55CONFIG_SYSFS_DEPRECATED_V2=y
53# CONFIG_RELAY is not set 56# CONFIG_RELAY is not set
57# CONFIG_NAMESPACES is not set
54CONFIG_BLK_DEV_INITRD=y 58CONFIG_BLK_DEV_INITRD=y
55CONFIG_INITRAMFS_SOURCE="" 59CONFIG_INITRAMFS_SOURCE=""
56CONFIG_CC_OPTIMIZE_FOR_SIZE=y 60CONFIG_CC_OPTIMIZE_FOR_SIZE=y
@@ -58,6 +62,7 @@ CONFIG_SYSCTL=y
58CONFIG_EMBEDDED=y 62CONFIG_EMBEDDED=y
59CONFIG_UID16=y 63CONFIG_UID16=y
60CONFIG_SYSCTL_SYSCALL=y 64CONFIG_SYSCTL_SYSCALL=y
65CONFIG_SYSCTL_SYSCALL_CHECK=y
61CONFIG_KALLSYMS=y 66CONFIG_KALLSYMS=y
62# CONFIG_KALLSYMS_ALL is not set 67# CONFIG_KALLSYMS_ALL is not set
63# CONFIG_KALLSYMS_EXTRA_PASS is not set 68# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -65,24 +70,34 @@ CONFIG_HOTPLUG=y
65CONFIG_PRINTK=y 70CONFIG_PRINTK=y
66CONFIG_BUG=y 71CONFIG_BUG=y
67CONFIG_ELF_CORE=y 72CONFIG_ELF_CORE=y
73# CONFIG_COMPAT_BRK is not set
68CONFIG_BASE_FULL=y 74CONFIG_BASE_FULL=y
69CONFIG_FUTEX=y 75CONFIG_FUTEX=y
70CONFIG_ANON_INODES=y 76CONFIG_ANON_INODES=y
71# CONFIG_EPOLL is not set 77CONFIG_EPOLL=y
72# CONFIG_SIGNALFD is not set 78CONFIG_SIGNALFD=y
73# CONFIG_TIMERFD is not set 79CONFIG_TIMERFD=y
74# CONFIG_EVENTFD is not set 80CONFIG_EVENTFD=y
75CONFIG_SHMEM=y 81CONFIG_SHMEM=y
76CONFIG_VM_EVENT_COUNTERS=y 82# CONFIG_VM_EVENT_COUNTERS is not set
77CONFIG_SLAB=y 83# CONFIG_SLUB_DEBUG is not set
78# CONFIG_SLUB is not set 84# CONFIG_SLAB is not set
85CONFIG_SLUB=y
79# CONFIG_SLOB is not set 86# CONFIG_SLOB is not set
87# CONFIG_PROFILING is not set
88# CONFIG_MARKERS is not set
89CONFIG_HAVE_OPROFILE=y
90# CONFIG_KPROBES is not set
91CONFIG_HAVE_KPROBES=y
92CONFIG_HAVE_KRETPROBES=y
93# CONFIG_HAVE_DMA_ATTRS is not set
94# CONFIG_PROC_PAGE_MONITOR is not set
80CONFIG_RT_MUTEXES=y 95CONFIG_RT_MUTEXES=y
81# CONFIG_TINY_SHMEM is not set 96# CONFIG_TINY_SHMEM is not set
82CONFIG_BASE_SMALL=0 97CONFIG_BASE_SMALL=0
83CONFIG_MODULES=y 98CONFIG_MODULES=y
84CONFIG_MODULE_UNLOAD=y 99CONFIG_MODULE_UNLOAD=y
85CONFIG_MODULE_FORCE_UNLOAD=y 100# CONFIG_MODULE_FORCE_UNLOAD is not set
86# CONFIG_MODVERSIONS is not set 101# CONFIG_MODVERSIONS is not set
87# CONFIG_MODULE_SRCVERSION_ALL is not set 102# CONFIG_MODULE_SRCVERSION_ALL is not set
88CONFIG_KMOD=y 103CONFIG_KMOD=y
@@ -99,11 +114,12 @@ CONFIG_IOSCHED_NOOP=y
99CONFIG_IOSCHED_AS=y 114CONFIG_IOSCHED_AS=y
100CONFIG_IOSCHED_DEADLINE=y 115CONFIG_IOSCHED_DEADLINE=y
101CONFIG_IOSCHED_CFQ=y 116CONFIG_IOSCHED_CFQ=y
102CONFIG_DEFAULT_AS=y 117# CONFIG_DEFAULT_AS is not set
103# CONFIG_DEFAULT_DEADLINE is not set 118# CONFIG_DEFAULT_DEADLINE is not set
104# CONFIG_DEFAULT_CFQ is not set 119CONFIG_DEFAULT_CFQ=y
105# CONFIG_DEFAULT_NOOP is not set 120# CONFIG_DEFAULT_NOOP is not set
106CONFIG_DEFAULT_IOSCHED="anticipatory" 121CONFIG_DEFAULT_IOSCHED="cfq"
122CONFIG_CLASSIC_RCU=y
107 123
108# 124#
109# System Type 125# System Type
@@ -131,6 +147,8 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
131# CONFIG_ARCH_L7200 is not set 147# CONFIG_ARCH_L7200 is not set
132# CONFIG_ARCH_KS8695 is not set 148# CONFIG_ARCH_KS8695 is not set
133# CONFIG_ARCH_NS9XXX is not set 149# CONFIG_ARCH_NS9XXX is not set
150# CONFIG_ARCH_MXC is not set
151# CONFIG_ARCH_ORION5X is not set
134# CONFIG_ARCH_PNX4008 is not set 152# CONFIG_ARCH_PNX4008 is not set
135CONFIG_ARCH_PXA=y 153CONFIG_ARCH_PXA=y
136# CONFIG_ARCH_RPC is not set 154# CONFIG_ARCH_RPC is not set
@@ -140,19 +158,41 @@ CONFIG_ARCH_PXA=y
140# CONFIG_ARCH_LH7A40X is not set 158# CONFIG_ARCH_LH7A40X is not set
141# CONFIG_ARCH_DAVINCI is not set 159# CONFIG_ARCH_DAVINCI is not set
142# CONFIG_ARCH_OMAP is not set 160# CONFIG_ARCH_OMAP is not set
161# CONFIG_ARCH_MSM7X00A is not set
143CONFIG_DMABOUNCE=y 162CONFIG_DMABOUNCE=y
144 163
145# 164#
146# Intel PXA2xx Implementations 165# Intel PXA2xx/PXA3xx Implementations
147# 166#
167
168#
169# Select target boards
170#
171# CONFIG_ARCH_GUMSTIX is not set
148# CONFIG_ARCH_LUBBOCK is not set 172# CONFIG_ARCH_LUBBOCK is not set
149# CONFIG_MACH_LOGICPD_PXA270 is not set 173# CONFIG_MACH_LOGICPD_PXA270 is not set
150# CONFIG_MACH_MAINSTONE is not set 174# CONFIG_MACH_MAINSTONE is not set
151# CONFIG_ARCH_PXA_IDP is not set 175# CONFIG_ARCH_PXA_IDP is not set
152# CONFIG_PXA_SHARPSL is not set 176# CONFIG_PXA_SHARPSL is not set
177# CONFIG_ARCH_PXA_ESERIES is not set
153# CONFIG_MACH_TRIZEPS4 is not set 178# CONFIG_MACH_TRIZEPS4 is not set
179CONFIG_MACH_EM_X270=y
180# CONFIG_MACH_COLIBRI is not set
181# CONFIG_MACH_ZYLONITE is not set
182# CONFIG_MACH_LITTLETON is not set
154CONFIG_MACH_ARMCORE=y 183CONFIG_MACH_ARMCORE=y
184# CONFIG_MACH_MAGICIAN is not set
185# CONFIG_MACH_PCM027 is not set
155CONFIG_PXA27x=y 186CONFIG_PXA27x=y
187# CONFIG_PXA_PWM is not set
188
189#
190# Boot options
191#
192
193#
194# Power management
195#
156 196
157# 197#
158# Processor Type 198# Processor Type
@@ -161,6 +201,7 @@ CONFIG_CPU_32=y
161CONFIG_CPU_XSCALE=y 201CONFIG_CPU_XSCALE=y
162CONFIG_CPU_32v5=y 202CONFIG_CPU_32v5=y
163CONFIG_CPU_ABRT_EV5T=y 203CONFIG_CPU_ABRT_EV5T=y
204CONFIG_CPU_PABRT_NOIFAR=y
164CONFIG_CPU_CACHE_VIVT=y 205CONFIG_CPU_CACHE_VIVT=y
165CONFIG_CPU_TLB_V4WBI=y 206CONFIG_CPU_TLB_V4WBI=y
166CONFIG_CPU_CP15=y 207CONFIG_CPU_CP15=y
@@ -182,21 +223,41 @@ CONFIG_PCI=y
182CONFIG_PCI_SYSCALL=y 223CONFIG_PCI_SYSCALL=y
183CONFIG_PCI_HOST_ITE8152=y 224CONFIG_PCI_HOST_ITE8152=y
184# CONFIG_ARCH_SUPPORTS_MSI is not set 225# CONFIG_ARCH_SUPPORTS_MSI is not set
226CONFIG_PCI_LEGACY=y
185# CONFIG_PCI_DEBUG is not set 227# CONFIG_PCI_DEBUG is not set
228CONFIG_PCCARD=m
229# CONFIG_PCMCIA_DEBUG is not set
230CONFIG_PCMCIA=m
231CONFIG_PCMCIA_LOAD_CIS=y
232CONFIG_PCMCIA_IOCTL=y
233CONFIG_CARDBUS=y
186 234
187# 235#
188# PCCARD (PCMCIA/CardBus) support 236# PC-card bridges
189# 237#
190# CONFIG_PCCARD is not set 238CONFIG_YENTA=m
239# CONFIG_YENTA_O2 is not set
240# CONFIG_YENTA_RICOH is not set
241CONFIG_YENTA_TI=y
242# CONFIG_YENTA_ENE_TUNE is not set
243# CONFIG_YENTA_TOSHIBA is not set
244# CONFIG_PD6729 is not set
245# CONFIG_I82092 is not set
246CONFIG_PCMCIA_PXA2XX=m
247CONFIG_PCCARD_NONSTATIC=m
191 248
192# 249#
193# Kernel Features 250# Kernel Features
194# 251#
195# CONFIG_TICK_ONESHOT is not set 252CONFIG_TICK_ONESHOT=y
196# CONFIG_PREEMPT is not set 253CONFIG_NO_HZ=y
197# CONFIG_NO_IDLE_HZ is not set 254# CONFIG_NO_IDLE_HZ is not set
255# CONFIG_HIGH_RES_TIMERS is not set
256CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
257# CONFIG_PREEMPT is not set
198CONFIG_HZ=100 258CONFIG_HZ=100
199# CONFIG_AEABI is not set 259CONFIG_AEABI=y
260CONFIG_OABI_COMPAT=y
200# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 261# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
201CONFIG_SELECT_MEMORY_MODEL=y 262CONFIG_SELECT_MEMORY_MODEL=y
202CONFIG_FLATMEM_MANUAL=y 263CONFIG_FLATMEM_MANUAL=y
@@ -205,6 +266,8 @@ CONFIG_FLATMEM_MANUAL=y
205CONFIG_FLATMEM=y 266CONFIG_FLATMEM=y
206CONFIG_FLAT_NODE_MEM_MAP=y 267CONFIG_FLAT_NODE_MEM_MAP=y
207# CONFIG_SPARSEMEM_STATIC is not set 268# CONFIG_SPARSEMEM_STATIC is not set
269# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
270CONFIG_PAGEFLAGS_EXTENDED=y
208CONFIG_SPLIT_PTLOCK_CPUS=4096 271CONFIG_SPLIT_PTLOCK_CPUS=4096
209# CONFIG_RESOURCES_64BIT is not set 272# CONFIG_RESOURCES_64BIT is not set
210CONFIG_ZONE_DMA_FLAG=1 273CONFIG_ZONE_DMA_FLAG=1
@@ -217,11 +280,16 @@ CONFIG_ALIGNMENT_TRAP=y
217# 280#
218CONFIG_ZBOOT_ROM_TEXT=0x0 281CONFIG_ZBOOT_ROM_TEXT=0x0
219CONFIG_ZBOOT_ROM_BSS=0x0 282CONFIG_ZBOOT_ROM_BSS=0x0
220CONFIG_CMDLINE="" 283CONFIG_CMDLINE="root=1f03 mem=32M"
221# CONFIG_XIP_KERNEL is not set 284# CONFIG_XIP_KERNEL is not set
222# CONFIG_KEXEC is not set 285# CONFIG_KEXEC is not set
223 286
224# 287#
288# CPU Frequency scaling
289#
290# CONFIG_CPU_FREQ is not set
291
292#
225# Floating point emulation 293# Floating point emulation
226# 294#
227 295
@@ -238,16 +306,17 @@ CONFIG_FPE_NWFPE=y
238CONFIG_BINFMT_ELF=y 306CONFIG_BINFMT_ELF=y
239# CONFIG_BINFMT_AOUT is not set 307# CONFIG_BINFMT_AOUT is not set
240# CONFIG_BINFMT_MISC is not set 308# CONFIG_BINFMT_MISC is not set
241# CONFIG_ARTHUR is not set
242 309
243# 310#
244# Power management options 311# Power management options
245# 312#
246CONFIG_PM=y 313CONFIG_PM=y
247# CONFIG_PM_LEGACY is not set
248# CONFIG_PM_DEBUG is not set 314# CONFIG_PM_DEBUG is not set
249# CONFIG_PM_SYSFS_DEPRECATED is not set 315CONFIG_PM_SLEEP=y
250# CONFIG_APM_EMULATION is not set 316CONFIG_SUSPEND=y
317CONFIG_SUSPEND_FREEZER=y
318CONFIG_APM_EMULATION=m
319CONFIG_ARCH_SUSPEND_POSSIBLE=y
251 320
252# 321#
253# Networking 322# Networking
@@ -258,15 +327,16 @@ CONFIG_NET=y
258# Networking options 327# Networking options
259# 328#
260CONFIG_PACKET=y 329CONFIG_PACKET=y
261# CONFIG_PACKET_MMAP is not set 330CONFIG_PACKET_MMAP=y
262CONFIG_UNIX=y 331CONFIG_UNIX=y
263CONFIG_XFRM=y 332CONFIG_XFRM=y
264# CONFIG_XFRM_USER is not set 333# CONFIG_XFRM_USER is not set
265# CONFIG_XFRM_SUB_POLICY is not set 334# CONFIG_XFRM_SUB_POLICY is not set
266# CONFIG_XFRM_MIGRATE is not set 335# CONFIG_XFRM_MIGRATE is not set
336# CONFIG_XFRM_STATISTICS is not set
267# CONFIG_NET_KEY is not set 337# CONFIG_NET_KEY is not set
268CONFIG_INET=y 338CONFIG_INET=y
269# CONFIG_IP_MULTICAST is not set 339CONFIG_IP_MULTICAST=y
270# CONFIG_IP_ADVANCED_ROUTER is not set 340# CONFIG_IP_ADVANCED_ROUTER is not set
271CONFIG_IP_FIB_HASH=y 341CONFIG_IP_FIB_HASH=y
272CONFIG_IP_PNP=y 342CONFIG_IP_PNP=y
@@ -275,6 +345,7 @@ CONFIG_IP_PNP_BOOTP=y
275# CONFIG_IP_PNP_RARP is not set 345# CONFIG_IP_PNP_RARP is not set
276# CONFIG_NET_IPIP is not set 346# CONFIG_NET_IPIP is not set
277# CONFIG_NET_IPGRE is not set 347# CONFIG_NET_IPGRE is not set
348# CONFIG_IP_MROUTE is not set
278# CONFIG_ARPD is not set 349# CONFIG_ARPD is not set
279# CONFIG_SYN_COOKIES is not set 350# CONFIG_SYN_COOKIES is not set
280# CONFIG_INET_AH is not set 351# CONFIG_INET_AH is not set
@@ -285,15 +356,13 @@ CONFIG_IP_PNP_BOOTP=y
285CONFIG_INET_XFRM_MODE_TRANSPORT=y 356CONFIG_INET_XFRM_MODE_TRANSPORT=y
286CONFIG_INET_XFRM_MODE_TUNNEL=y 357CONFIG_INET_XFRM_MODE_TUNNEL=y
287CONFIG_INET_XFRM_MODE_BEET=y 358CONFIG_INET_XFRM_MODE_BEET=y
288CONFIG_INET_DIAG=y 359# CONFIG_INET_LRO is not set
289CONFIG_INET_TCP_DIAG=y 360# CONFIG_INET_DIAG is not set
290# CONFIG_TCP_CONG_ADVANCED is not set 361# CONFIG_TCP_CONG_ADVANCED is not set
291CONFIG_TCP_CONG_CUBIC=y 362CONFIG_TCP_CONG_CUBIC=y
292CONFIG_DEFAULT_TCP_CONG="cubic" 363CONFIG_DEFAULT_TCP_CONG="cubic"
293# CONFIG_TCP_MD5SIG is not set 364# CONFIG_TCP_MD5SIG is not set
294# CONFIG_IPV6 is not set 365# CONFIG_IPV6 is not set
295# CONFIG_INET6_XFRM_TUNNEL is not set
296# CONFIG_INET6_TUNNEL is not set
297# CONFIG_NETWORK_SECMARK is not set 366# CONFIG_NETWORK_SECMARK is not set
298# CONFIG_NETFILTER is not set 367# CONFIG_NETFILTER is not set
299# CONFIG_IP_DCCP is not set 368# CONFIG_IP_DCCP is not set
@@ -310,10 +379,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
310# CONFIG_LAPB is not set 379# CONFIG_LAPB is not set
311# CONFIG_ECONET is not set 380# CONFIG_ECONET is not set
312# CONFIG_WAN_ROUTER is not set 381# CONFIG_WAN_ROUTER is not set
313
314#
315# QoS and/or fair queueing
316#
317# CONFIG_NET_SCHED is not set 382# CONFIG_NET_SCHED is not set
318 383
319# 384#
@@ -321,8 +386,33 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
321# 386#
322# CONFIG_NET_PKTGEN is not set 387# CONFIG_NET_PKTGEN is not set
323# CONFIG_HAMRADIO is not set 388# CONFIG_HAMRADIO is not set
389# CONFIG_CAN is not set
324# CONFIG_IRDA is not set 390# CONFIG_IRDA is not set
325# CONFIG_BT is not set 391CONFIG_BT=m
392CONFIG_BT_L2CAP=m
393CONFIG_BT_SCO=m
394CONFIG_BT_RFCOMM=m
395# CONFIG_BT_RFCOMM_TTY is not set
396CONFIG_BT_BNEP=m
397# CONFIG_BT_BNEP_MC_FILTER is not set
398# CONFIG_BT_BNEP_PROTO_FILTER is not set
399CONFIG_BT_HIDP=m
400
401#
402# Bluetooth device drivers
403#
404CONFIG_BT_HCIUSB=m
405CONFIG_BT_HCIUSB_SCO=y
406# CONFIG_BT_HCIBTSDIO is not set
407# CONFIG_BT_HCIUART is not set
408# CONFIG_BT_HCIBCM203X is not set
409# CONFIG_BT_HCIBPA10X is not set
410# CONFIG_BT_HCIBFUSB is not set
411# CONFIG_BT_HCIDTL1 is not set
412# CONFIG_BT_HCIBT3C is not set
413# CONFIG_BT_HCIBLUECARD is not set
414# CONFIG_BT_HCIBTUART is not set
415# CONFIG_BT_HCIVHCI is not set
326# CONFIG_AF_RXRPC is not set 416# CONFIG_AF_RXRPC is not set
327 417
328# 418#
@@ -331,12 +421,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
331# CONFIG_CFG80211 is not set 421# CONFIG_CFG80211 is not set
332CONFIG_WIRELESS_EXT=y 422CONFIG_WIRELESS_EXT=y
333# CONFIG_MAC80211 is not set 423# CONFIG_MAC80211 is not set
334CONFIG_IEEE80211=m 424# CONFIG_IEEE80211 is not set
335# CONFIG_IEEE80211_DEBUG is not set
336CONFIG_IEEE80211_CRYPT_WEP=m
337CONFIG_IEEE80211_CRYPT_CCMP=m
338# CONFIG_IEEE80211_CRYPT_TKIP is not set
339# CONFIG_IEEE80211_SOFTMAC is not set
340# CONFIG_RFKILL is not set 425# CONFIG_RFKILL is not set
341# CONFIG_NET_9P is not set 426# CONFIG_NET_9P is not set
342 427
@@ -347,38 +432,47 @@ CONFIG_IEEE80211_CRYPT_CCMP=m
347# 432#
348# Generic Driver Options 433# Generic Driver Options
349# 434#
435CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
350CONFIG_STANDALONE=y 436CONFIG_STANDALONE=y
351CONFIG_PREVENT_FIRMWARE_BUILD=y 437CONFIG_PREVENT_FIRMWARE_BUILD=y
352CONFIG_FW_LOADER=y 438CONFIG_FW_LOADER=m
353# CONFIG_DEBUG_DRIVER is not set 439# CONFIG_DEBUG_DRIVER is not set
354# CONFIG_DEBUG_DEVRES is not set 440# CONFIG_DEBUG_DEVRES is not set
355# CONFIG_SYS_HYPERVISOR is not set 441# CONFIG_SYS_HYPERVISOR is not set
356# CONFIG_CONNECTOR is not set 442# CONFIG_CONNECTOR is not set
357CONFIG_MTD=m 443CONFIG_MTD=y
358# CONFIG_MTD_DEBUG is not set 444# CONFIG_MTD_DEBUG is not set
359# CONFIG_MTD_CONCAT is not set 445# CONFIG_MTD_CONCAT is not set
360CONFIG_MTD_PARTITIONS=y 446CONFIG_MTD_PARTITIONS=y
361# CONFIG_MTD_REDBOOT_PARTS is not set 447# CONFIG_MTD_REDBOOT_PARTS is not set
448CONFIG_MTD_CMDLINE_PARTS=y
362# CONFIG_MTD_AFS_PARTS is not set 449# CONFIG_MTD_AFS_PARTS is not set
450# CONFIG_MTD_AR7_PARTS is not set
363 451
364# 452#
365# User Modules And Translation Layers 453# User Modules And Translation Layers
366# 454#
367CONFIG_MTD_CHAR=m 455CONFIG_MTD_CHAR=y
368CONFIG_MTD_BLKDEVS=m 456CONFIG_MTD_BLKDEVS=y
369CONFIG_MTD_BLOCK=m 457CONFIG_MTD_BLOCK=y
370# CONFIG_MTD_BLOCK_RO is not set
371# CONFIG_FTL is not set 458# CONFIG_FTL is not set
372# CONFIG_NFTL is not set 459# CONFIG_NFTL is not set
373# CONFIG_INFTL is not set 460# CONFIG_INFTL is not set
374# CONFIG_RFD_FTL is not set 461# CONFIG_RFD_FTL is not set
375# CONFIG_SSFDC is not set 462# CONFIG_SSFDC is not set
463# CONFIG_MTD_OOPS is not set
376 464
377# 465#
378# RAM/ROM/Flash chip drivers 466# RAM/ROM/Flash chip drivers
379# 467#
380# CONFIG_MTD_CFI is not set 468CONFIG_MTD_CFI=y
381# CONFIG_MTD_JEDECPROBE is not set 469CONFIG_MTD_JEDECPROBE=y
470CONFIG_MTD_GEN_PROBE=y
471CONFIG_MTD_CFI_ADV_OPTIONS=y
472CONFIG_MTD_CFI_NOSWAP=y
473# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
474# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
475# CONFIG_MTD_CFI_GEOMETRY is not set
382CONFIG_MTD_MAP_BANK_WIDTH_1=y 476CONFIG_MTD_MAP_BANK_WIDTH_1=y
383CONFIG_MTD_MAP_BANK_WIDTH_2=y 477CONFIG_MTD_MAP_BANK_WIDTH_2=y
384CONFIG_MTD_MAP_BANK_WIDTH_4=y 478CONFIG_MTD_MAP_BANK_WIDTH_4=y
@@ -389,15 +483,29 @@ CONFIG_MTD_CFI_I1=y
389CONFIG_MTD_CFI_I2=y 483CONFIG_MTD_CFI_I2=y
390# CONFIG_MTD_CFI_I4 is not set 484# CONFIG_MTD_CFI_I4 is not set
391# CONFIG_MTD_CFI_I8 is not set 485# CONFIG_MTD_CFI_I8 is not set
486# CONFIG_MTD_OTP is not set
487CONFIG_MTD_CFI_INTELEXT=y
488CONFIG_MTD_CFI_AMDSTD=y
489CONFIG_MTD_CFI_STAA=y
490CONFIG_MTD_CFI_UTIL=y
392# CONFIG_MTD_RAM is not set 491# CONFIG_MTD_RAM is not set
393# CONFIG_MTD_ROM is not set 492# CONFIG_MTD_ROM is not set
394# CONFIG_MTD_ABSENT is not set 493# CONFIG_MTD_ABSENT is not set
494# CONFIG_MTD_XIP is not set
395 495
396# 496#
397# Mapping drivers for chip access 497# Mapping drivers for chip access
398# 498#
399# CONFIG_MTD_COMPLEX_MAPPINGS is not set 499# CONFIG_MTD_COMPLEX_MAPPINGS is not set
500CONFIG_MTD_PHYSMAP=y
501CONFIG_MTD_PHYSMAP_START=0x0
502CONFIG_MTD_PHYSMAP_LEN=0x400000
503CONFIG_MTD_PHYSMAP_BANKWIDTH=2
504CONFIG_MTD_PXA2XX=y
505# CONFIG_MTD_ARM_INTEGRATOR is not set
506# CONFIG_MTD_IMPA7 is not set
400# CONFIG_MTD_SHARP_SL is not set 507# CONFIG_MTD_SHARP_SL is not set
508# CONFIG_MTD_INTEL_VR_NOR is not set
401# CONFIG_MTD_PLATRAM is not set 509# CONFIG_MTD_PLATRAM is not set
402 510
403# 511#
@@ -415,18 +523,19 @@ CONFIG_MTD_CFI_I2=y
415# CONFIG_MTD_DOC2000 is not set 523# CONFIG_MTD_DOC2000 is not set
416# CONFIG_MTD_DOC2001 is not set 524# CONFIG_MTD_DOC2001 is not set
417# CONFIG_MTD_DOC2001PLUS is not set 525# CONFIG_MTD_DOC2001PLUS is not set
418CONFIG_MTD_NAND=m 526CONFIG_MTD_NAND=y
419# CONFIG_MTD_NAND_VERIFY_WRITE is not set 527# CONFIG_MTD_NAND_VERIFY_WRITE is not set
420# CONFIG_MTD_NAND_ECC_SMC is not set 528# CONFIG_MTD_NAND_ECC_SMC is not set
421# CONFIG_MTD_NAND_MUSEUM_IDS is not set 529# CONFIG_MTD_NAND_MUSEUM_IDS is not set
422# CONFIG_MTD_NAND_H1900 is not set 530# CONFIG_MTD_NAND_H1900 is not set
423CONFIG_MTD_NAND_IDS=m 531CONFIG_MTD_NAND_IDS=y
424# CONFIG_MTD_NAND_DISKONCHIP is not set 532# CONFIG_MTD_NAND_DISKONCHIP is not set
425# CONFIG_MTD_NAND_SHARPSL is not set 533# CONFIG_MTD_NAND_SHARPSL is not set
426# CONFIG_MTD_NAND_CAFE is not set 534# CONFIG_MTD_NAND_CAFE is not set
427CONFIG_MTD_NAND_CM_X270=m 535CONFIG_MTD_NAND_CM_X270=y
428# CONFIG_MTD_NAND_NANDSIM is not set 536# CONFIG_MTD_NAND_NANDSIM is not set
429# CONFIG_MTD_NAND_PLATFORM is not set 537CONFIG_MTD_NAND_PLATFORM=y
538# CONFIG_MTD_ALAUDA is not set
430# CONFIG_MTD_ONENAND is not set 539# CONFIG_MTD_ONENAND is not set
431 540
432# 541#
@@ -447,36 +556,13 @@ CONFIG_BLK_DEV_LOOP=y
447# CONFIG_BLK_DEV_UB is not set 556# CONFIG_BLK_DEV_UB is not set
448CONFIG_BLK_DEV_RAM=y 557CONFIG_BLK_DEV_RAM=y
449CONFIG_BLK_DEV_RAM_COUNT=16 558CONFIG_BLK_DEV_RAM_COUNT=16
450CONFIG_BLK_DEV_RAM_SIZE=12000 559CONFIG_BLK_DEV_RAM_SIZE=4096
451CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 560# CONFIG_BLK_DEV_XIP is not set
452# CONFIG_CDROM_PKTCDVD is not set 561# CONFIG_CDROM_PKTCDVD is not set
453# CONFIG_ATA_OVER_ETH is not set 562# CONFIG_ATA_OVER_ETH is not set
454CONFIG_IDE=m 563# CONFIG_MISC_DEVICES is not set
455CONFIG_IDE_MAX_HWIFS=4 564CONFIG_HAVE_IDE=y
456CONFIG_BLK_DEV_IDE=m 565# CONFIG_IDE is not set
457
458#
459# Please see Documentation/ide.txt for help/info on IDE drives
460#
461# CONFIG_BLK_DEV_IDE_SATA is not set
462CONFIG_BLK_DEV_IDEDISK=m
463# CONFIG_IDEDISK_MULTI_MODE is not set
464CONFIG_BLK_DEV_IDECD=m
465# CONFIG_BLK_DEV_IDETAPE is not set
466# CONFIG_BLK_DEV_IDEFLOPPY is not set
467# CONFIG_BLK_DEV_IDESCSI is not set
468# CONFIG_IDE_TASK_IOCTL is not set
469CONFIG_IDE_PROC_FS=y
470
471#
472# IDE chipset support/bugfixes
473#
474# CONFIG_IDE_GENERIC is not set
475# CONFIG_BLK_DEV_IDEPCI is not set
476# CONFIG_IDEPCI_PCIBUS_ORDER is not set
477# CONFIG_IDE_ARM is not set
478# CONFIG_BLK_DEV_IDEDMA is not set
479# CONFIG_BLK_DEV_HD is not set
480 566
481# 567#
482# SCSI device support 568# SCSI device support
@@ -486,7 +572,7 @@ CONFIG_SCSI=y
486CONFIG_SCSI_DMA=y 572CONFIG_SCSI_DMA=y
487# CONFIG_SCSI_TGT is not set 573# CONFIG_SCSI_TGT is not set
488# CONFIG_SCSI_NETLINK is not set 574# CONFIG_SCSI_NETLINK is not set
489# CONFIG_SCSI_PROC_FS is not set 575CONFIG_SCSI_PROC_FS=y
490 576
491# 577#
492# SCSI support type (disk, tape, CD-ROM) 578# SCSI support type (disk, tape, CD-ROM)
@@ -513,12 +599,9 @@ CONFIG_SCSI_WAIT_SCAN=m
513# CONFIG_SCSI_SPI_ATTRS is not set 599# CONFIG_SCSI_SPI_ATTRS is not set
514# CONFIG_SCSI_FC_ATTRS is not set 600# CONFIG_SCSI_FC_ATTRS is not set
515# CONFIG_SCSI_ISCSI_ATTRS is not set 601# CONFIG_SCSI_ISCSI_ATTRS is not set
516# CONFIG_SCSI_SAS_ATTRS is not set
517# CONFIG_SCSI_SAS_LIBSAS is not set 602# CONFIG_SCSI_SAS_LIBSAS is not set
518 603# CONFIG_SCSI_SRP_ATTRS is not set
519# 604CONFIG_SCSI_LOWLEVEL=y
520# SCSI low-level drivers
521#
522# CONFIG_ISCSI_TCP is not set 605# CONFIG_ISCSI_TCP is not set
523# CONFIG_BLK_DEV_3W_XXXX_RAID is not set 606# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
524# CONFIG_SCSI_3W_9XXX is not set 607# CONFIG_SCSI_3W_9XXX is not set
@@ -529,6 +612,7 @@ CONFIG_SCSI_WAIT_SCAN=m
529# CONFIG_SCSI_AIC79XX is not set 612# CONFIG_SCSI_AIC79XX is not set
530# CONFIG_SCSI_AIC94XX is not set 613# CONFIG_SCSI_AIC94XX is not set
531# CONFIG_SCSI_DPT_I2O is not set 614# CONFIG_SCSI_DPT_I2O is not set
615# CONFIG_SCSI_ADVANSYS is not set
532# CONFIG_SCSI_ARCMSR is not set 616# CONFIG_SCSI_ARCMSR is not set
533# CONFIG_MEGARAID_NEWGEN is not set 617# CONFIG_MEGARAID_NEWGEN is not set
534# CONFIG_MEGARAID_LEGACY is not set 618# CONFIG_MEGARAID_LEGACY is not set
@@ -539,8 +623,10 @@ CONFIG_SCSI_WAIT_SCAN=m
539# CONFIG_SCSI_IPS is not set 623# CONFIG_SCSI_IPS is not set
540# CONFIG_SCSI_INITIO is not set 624# CONFIG_SCSI_INITIO is not set
541# CONFIG_SCSI_INIA100 is not set 625# CONFIG_SCSI_INIA100 is not set
626# CONFIG_SCSI_MVSAS is not set
542# CONFIG_SCSI_STEX is not set 627# CONFIG_SCSI_STEX is not set
543# CONFIG_SCSI_SYM53C8XX_2 is not set 628# CONFIG_SCSI_SYM53C8XX_2 is not set
629# CONFIG_SCSI_IPR is not set
544# CONFIG_SCSI_QLOGIC_1280 is not set 630# CONFIG_SCSI_QLOGIC_1280 is not set
545# CONFIG_SCSI_QLA_FC is not set 631# CONFIG_SCSI_QLA_FC is not set
546# CONFIG_SCSI_QLA_ISCSI is not set 632# CONFIG_SCSI_QLA_ISCSI is not set
@@ -550,16 +636,69 @@ CONFIG_SCSI_WAIT_SCAN=m
550# CONFIG_SCSI_NSP32 is not set 636# CONFIG_SCSI_NSP32 is not set
551# CONFIG_SCSI_DEBUG is not set 637# CONFIG_SCSI_DEBUG is not set
552# CONFIG_SCSI_SRP is not set 638# CONFIG_SCSI_SRP is not set
553# CONFIG_ATA is not set 639# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
640CONFIG_ATA=m
641# CONFIG_ATA_NONSTANDARD is not set
642# CONFIG_SATA_PMP is not set
643# CONFIG_SATA_AHCI is not set
644# CONFIG_SATA_SIL24 is not set
645CONFIG_ATA_SFF=y
646# CONFIG_SATA_SVW is not set
647# CONFIG_ATA_PIIX is not set
648# CONFIG_SATA_MV is not set
649# CONFIG_SATA_NV is not set
650# CONFIG_PDC_ADMA is not set
651# CONFIG_SATA_QSTOR is not set
652# CONFIG_SATA_PROMISE is not set
653# CONFIG_SATA_SX4 is not set
654# CONFIG_SATA_SIL is not set
655# CONFIG_SATA_SIS is not set
656# CONFIG_SATA_ULI is not set
657# CONFIG_SATA_VIA is not set
658# CONFIG_SATA_VITESSE is not set
659# CONFIG_SATA_INIC162X is not set
660# CONFIG_PATA_ALI is not set
661# CONFIG_PATA_AMD is not set
662# CONFIG_PATA_ARTOP is not set
663# CONFIG_PATA_ATIIXP is not set
664# CONFIG_PATA_CMD640_PCI is not set
665# CONFIG_PATA_CMD64X is not set
666# CONFIG_PATA_CS5520 is not set
667# CONFIG_PATA_CS5530 is not set
668# CONFIG_PATA_CYPRESS is not set
669# CONFIG_PATA_EFAR is not set
670# CONFIG_ATA_GENERIC is not set
671# CONFIG_PATA_HPT366 is not set
672# CONFIG_PATA_HPT37X is not set
673# CONFIG_PATA_HPT3X2N is not set
674# CONFIG_PATA_HPT3X3 is not set
675# CONFIG_PATA_IT821X is not set
676# CONFIG_PATA_IT8213 is not set
677# CONFIG_PATA_JMICRON is not set
678# CONFIG_PATA_TRIFLEX is not set
679# CONFIG_PATA_MARVELL is not set
680# CONFIG_PATA_MPIIX is not set
681# CONFIG_PATA_OLDPIIX is not set
682# CONFIG_PATA_NETCELL is not set
683# CONFIG_PATA_NINJA32 is not set
684# CONFIG_PATA_NS87410 is not set
685# CONFIG_PATA_NS87415 is not set
686# CONFIG_PATA_OPTI is not set
687# CONFIG_PATA_OPTIDMA is not set
688CONFIG_PATA_PCMCIA=m
689# CONFIG_PATA_PDC_OLD is not set
690# CONFIG_PATA_RADISYS is not set
691# CONFIG_PATA_RZ1000 is not set
692# CONFIG_PATA_SC1200 is not set
693# CONFIG_PATA_SERVERWORKS is not set
694# CONFIG_PATA_PDC2027X is not set
695# CONFIG_PATA_SIL680 is not set
696# CONFIG_PATA_SIS is not set
697# CONFIG_PATA_VIA is not set
698# CONFIG_PATA_WINBOND is not set
699# CONFIG_PATA_PLATFORM is not set
554# CONFIG_MD is not set 700# CONFIG_MD is not set
555
556#
557# Fusion MPT device support
558#
559# CONFIG_FUSION is not set 701# CONFIG_FUSION is not set
560# CONFIG_FUSION_SPI is not set
561# CONFIG_FUSION_FC is not set
562# CONFIG_FUSION_SAS is not set
563 702
564# 703#
565# IEEE 1394 (FireWire) support 704# IEEE 1394 (FireWire) support
@@ -574,6 +713,7 @@ CONFIG_NETDEVICES=y
574# CONFIG_MACVLAN is not set 713# CONFIG_MACVLAN is not set
575# CONFIG_EQUALIZER is not set 714# CONFIG_EQUALIZER is not set
576# CONFIG_TUN is not set 715# CONFIG_TUN is not set
716# CONFIG_VETH is not set
577# CONFIG_ARCNET is not set 717# CONFIG_ARCNET is not set
578# CONFIG_PHYLIB is not set 718# CONFIG_PHYLIB is not set
579CONFIG_NET_ETHERNET=y 719CONFIG_NET_ETHERNET=y
@@ -585,64 +725,65 @@ CONFIG_MII=y
585# CONFIG_NET_VENDOR_3COM is not set 725# CONFIG_NET_VENDOR_3COM is not set
586# CONFIG_SMC91X is not set 726# CONFIG_SMC91X is not set
587CONFIG_DM9000=y 727CONFIG_DM9000=y
728CONFIG_DM9000_DEBUGLEVEL=1
588# CONFIG_SMC911X is not set 729# CONFIG_SMC911X is not set
589# CONFIG_NET_TULIP is not set 730# CONFIG_NET_TULIP is not set
590# CONFIG_HP100 is not set 731# CONFIG_HP100 is not set
732# CONFIG_IBM_NEW_EMAC_ZMII is not set
733# CONFIG_IBM_NEW_EMAC_RGMII is not set
734# CONFIG_IBM_NEW_EMAC_TAH is not set
735# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
591CONFIG_NET_PCI=y 736CONFIG_NET_PCI=y
592# CONFIG_PCNET32 is not set 737# CONFIG_PCNET32 is not set
593# CONFIG_AMD8111_ETH is not set 738# CONFIG_AMD8111_ETH is not set
594# CONFIG_ADAPTEC_STARFIRE is not set 739# CONFIG_ADAPTEC_STARFIRE is not set
595# CONFIG_B44 is not set 740# CONFIG_B44 is not set
596# CONFIG_FORCEDETH is not set 741# CONFIG_FORCEDETH is not set
597# CONFIG_DGRS is not set
598# CONFIG_EEPRO100 is not set 742# CONFIG_EEPRO100 is not set
599# CONFIG_E100 is not set 743# CONFIG_E100 is not set
600# CONFIG_FEALNX is not set 744# CONFIG_FEALNX is not set
601# CONFIG_NATSEMI is not set 745# CONFIG_NATSEMI is not set
602# CONFIG_NE2K_PCI is not set 746# CONFIG_NE2K_PCI is not set
603# CONFIG_8139CP is not set 747# CONFIG_8139CP is not set
604CONFIG_8139TOO=m 748CONFIG_8139TOO=y
605# CONFIG_8139TOO_PIO is not set 749# CONFIG_8139TOO_PIO is not set
606# CONFIG_8139TOO_TUNE_TWISTER is not set 750# CONFIG_8139TOO_TUNE_TWISTER is not set
607# CONFIG_8139TOO_8129 is not set 751# CONFIG_8139TOO_8129 is not set
608# CONFIG_8139_OLD_RX_RESET is not set 752# CONFIG_8139_OLD_RX_RESET is not set
753# CONFIG_R6040 is not set
609# CONFIG_SIS900 is not set 754# CONFIG_SIS900 is not set
610# CONFIG_EPIC100 is not set 755# CONFIG_EPIC100 is not set
611# CONFIG_SUNDANCE is not set 756# CONFIG_SUNDANCE is not set
612# CONFIG_TLAN is not set 757# CONFIG_TLAN is not set
613# CONFIG_VIA_RHINE is not set 758# CONFIG_VIA_RHINE is not set
614# CONFIG_SC92031 is not set 759# CONFIG_SC92031 is not set
615CONFIG_NETDEV_1000=y 760# CONFIG_NETDEV_1000 is not set
616# CONFIG_ACENIC is not set 761# CONFIG_NETDEV_10000 is not set
617# CONFIG_DL2K is not set
618# CONFIG_E1000 is not set
619# CONFIG_NS83820 is not set
620# CONFIG_HAMACHI is not set
621# CONFIG_YELLOWFIN is not set
622# CONFIG_R8169 is not set
623# CONFIG_SIS190 is not set
624# CONFIG_SKGE is not set
625# CONFIG_SKY2 is not set
626# CONFIG_VIA_VELOCITY is not set
627# CONFIG_TIGON3 is not set
628# CONFIG_BNX2 is not set
629# CONFIG_QLA3XXX is not set
630# CONFIG_ATL1 is not set
631CONFIG_NETDEV_10000=y
632# CONFIG_CHELSIO_T1 is not set
633# CONFIG_CHELSIO_T3 is not set
634# CONFIG_IXGB is not set
635# CONFIG_S2IO is not set
636# CONFIG_MYRI10GE is not set
637# CONFIG_NETXEN_NIC is not set
638# CONFIG_MLX4_CORE is not set
639# CONFIG_TR is not set 762# CONFIG_TR is not set
640 763
641# 764#
642# Wireless LAN 765# Wireless LAN
643# 766#
644# CONFIG_WLAN_PRE80211 is not set 767# CONFIG_WLAN_PRE80211 is not set
645# CONFIG_WLAN_80211 is not set 768CONFIG_WLAN_80211=y
769# CONFIG_PCMCIA_RAYCS is not set
770# CONFIG_IPW2100 is not set
771# CONFIG_IPW2200 is not set
772CONFIG_LIBERTAS=m
773# CONFIG_LIBERTAS_USB is not set
774# CONFIG_LIBERTAS_CS is not set
775CONFIG_LIBERTAS_SDIO=m
776# CONFIG_LIBERTAS_DEBUG is not set
777# CONFIG_HERMES is not set
778# CONFIG_ATMEL is not set
779# CONFIG_AIRO_CS is not set
780# CONFIG_PCMCIA_WL3501 is not set
781# CONFIG_PRISM54 is not set
782# CONFIG_USB_ZD1201 is not set
783# CONFIG_USB_NET_RNDIS_WLAN is not set
784# CONFIG_IWLWIFI is not set
785# CONFIG_IWLWIFI_LEDS is not set
786# CONFIG_HOSTAP is not set
646 787
647# 788#
648# USB Network Adapters 789# USB Network Adapters
@@ -651,15 +792,24 @@ CONFIG_NETDEV_10000=y
651# CONFIG_USB_KAWETH is not set 792# CONFIG_USB_KAWETH is not set
652# CONFIG_USB_PEGASUS is not set 793# CONFIG_USB_PEGASUS is not set
653# CONFIG_USB_RTL8150 is not set 794# CONFIG_USB_RTL8150 is not set
654# CONFIG_USB_USBNET_MII is not set
655# CONFIG_USB_USBNET is not set 795# CONFIG_USB_USBNET is not set
796# CONFIG_NET_PCMCIA is not set
656# CONFIG_WAN is not set 797# CONFIG_WAN is not set
657# CONFIG_FDDI is not set 798# CONFIG_FDDI is not set
658# CONFIG_HIPPI is not set 799# CONFIG_HIPPI is not set
659# CONFIG_PPP is not set 800CONFIG_PPP=m
801CONFIG_PPP_MULTILINK=y
802CONFIG_PPP_FILTER=y
803CONFIG_PPP_ASYNC=m
804# CONFIG_PPP_SYNC_TTY is not set
805CONFIG_PPP_DEFLATE=m
806CONFIG_PPP_BSDCOMP=m
807# CONFIG_PPP_MPPE is not set
808# CONFIG_PPPOE is not set
809# CONFIG_PPPOL2TP is not set
660# CONFIG_SLIP is not set 810# CONFIG_SLIP is not set
811CONFIG_SLHC=m
661# CONFIG_NET_FC is not set 812# CONFIG_NET_FC is not set
662# CONFIG_SHAPER is not set
663# CONFIG_NETCONSOLE is not set 813# CONFIG_NETCONSOLE is not set
664# CONFIG_NETPOLL is not set 814# CONFIG_NETPOLL is not set
665# CONFIG_NET_POLL_CONTROLLER is not set 815# CONFIG_NET_POLL_CONTROLLER is not set
@@ -675,20 +825,32 @@ CONFIG_INPUT=y
675# 825#
676# Userland interfaces 826# Userland interfaces
677# 827#
678# CONFIG_INPUT_MOUSEDEV is not set 828CONFIG_INPUT_MOUSEDEV=y
829CONFIG_INPUT_MOUSEDEV_PSAUX=y
830CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
831CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
679# CONFIG_INPUT_JOYDEV is not set 832# CONFIG_INPUT_JOYDEV is not set
680# CONFIG_INPUT_TSDEV is not set
681CONFIG_INPUT_EVDEV=y 833CONFIG_INPUT_EVDEV=y
682# CONFIG_INPUT_EVBUG is not set 834# CONFIG_INPUT_EVBUG is not set
835# CONFIG_INPUT_APMPOWER is not set
683 836
684# 837#
685# Input Device Drivers 838# Input Device Drivers
686# 839#
687# CONFIG_INPUT_KEYBOARD is not set 840CONFIG_INPUT_KEYBOARD=y
841CONFIG_KEYBOARD_ATKBD=y
842# CONFIG_KEYBOARD_SUNKBD is not set
843# CONFIG_KEYBOARD_LKKBD is not set
844# CONFIG_KEYBOARD_XTKBD is not set
845# CONFIG_KEYBOARD_NEWTON is not set
846# CONFIG_KEYBOARD_STOWAWAY is not set
847CONFIG_KEYBOARD_PXA27x=m
848# CONFIG_KEYBOARD_GPIO is not set
688# CONFIG_INPUT_MOUSE is not set 849# CONFIG_INPUT_MOUSE is not set
689# CONFIG_INPUT_JOYSTICK is not set 850# CONFIG_INPUT_JOYSTICK is not set
690# CONFIG_INPUT_TABLET is not set 851# CONFIG_INPUT_TABLET is not set
691CONFIG_INPUT_TOUCHSCREEN=y 852CONFIG_INPUT_TOUCHSCREEN=y
853# CONFIG_TOUCHSCREEN_FUJITSU is not set
692# CONFIG_TOUCHSCREEN_GUNZE is not set 854# CONFIG_TOUCHSCREEN_GUNZE is not set
693# CONFIG_TOUCHSCREEN_ELO is not set 855# CONFIG_TOUCHSCREEN_ELO is not set
694# CONFIG_TOUCHSCREEN_MTOUCH is not set 856# CONFIG_TOUCHSCREEN_MTOUCH is not set
@@ -697,13 +859,22 @@ CONFIG_INPUT_TOUCHSCREEN=y
697# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set 859# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
698# CONFIG_TOUCHSCREEN_TOUCHWIN is not set 860# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
699CONFIG_TOUCHSCREEN_UCB1400=m 861CONFIG_TOUCHSCREEN_UCB1400=m
862CONFIG_TOUCHSCREEN_WM97XX=m
863# CONFIG_TOUCHSCREEN_WM9705 is not set
864CONFIG_TOUCHSCREEN_WM9712=y
865# CONFIG_TOUCHSCREEN_WM9713 is not set
866# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
700# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set 867# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
701# CONFIG_INPUT_MISC is not set 868# CONFIG_INPUT_MISC is not set
702 869
703# 870#
704# Hardware I/O ports 871# Hardware I/O ports
705# 872#
706# CONFIG_SERIO is not set 873CONFIG_SERIO=y
874# CONFIG_SERIO_SERPORT is not set
875# CONFIG_SERIO_PCIPS2 is not set
876CONFIG_SERIO_LIBPS2=y
877# CONFIG_SERIO_RAW is not set
707# CONFIG_GAMEPORT is not set 878# CONFIG_GAMEPORT is not set
708 879
709# 880#
@@ -713,7 +884,9 @@ CONFIG_VT=y
713CONFIG_VT_CONSOLE=y 884CONFIG_VT_CONSOLE=y
714CONFIG_HW_CONSOLE=y 885CONFIG_HW_CONSOLE=y
715# CONFIG_VT_HW_CONSOLE_BINDING is not set 886# CONFIG_VT_HW_CONSOLE_BINDING is not set
887CONFIG_DEVKMEM=y
716# CONFIG_SERIAL_NONSTANDARD is not set 888# CONFIG_SERIAL_NONSTANDARD is not set
889# CONFIG_NOZOMI is not set
717 890
718# 891#
719# Serial drivers 892# Serial drivers
@@ -730,83 +903,141 @@ CONFIG_SERIAL_CORE_CONSOLE=y
730# CONFIG_SERIAL_JSM is not set 903# CONFIG_SERIAL_JSM is not set
731CONFIG_UNIX98_PTYS=y 904CONFIG_UNIX98_PTYS=y
732CONFIG_LEGACY_PTYS=y 905CONFIG_LEGACY_PTYS=y
733CONFIG_LEGACY_PTY_COUNT=256 906CONFIG_LEGACY_PTY_COUNT=16
734# CONFIG_IPMI_HANDLER is not set 907# CONFIG_IPMI_HANDLER is not set
735# CONFIG_WATCHDOG is not set 908# CONFIG_HW_RANDOM is not set
736CONFIG_HW_RANDOM=m
737# CONFIG_NVRAM is not set 909# CONFIG_NVRAM is not set
738# CONFIG_R3964 is not set 910# CONFIG_R3964 is not set
739# CONFIG_APPLICOM is not set 911# CONFIG_APPLICOM is not set
740# CONFIG_DRM is not set 912
913#
914# PCMCIA character devices
915#
916# CONFIG_SYNCLINK_CS is not set
917# CONFIG_CARDMAN_4000 is not set
918# CONFIG_CARDMAN_4040 is not set
919# CONFIG_IPWIRELESS is not set
741# CONFIG_RAW_DRIVER is not set 920# CONFIG_RAW_DRIVER is not set
742# CONFIG_TCG_TPM is not set 921# CONFIG_TCG_TPM is not set
743CONFIG_DEVPORT=y 922CONFIG_DEVPORT=y
744# CONFIG_I2C is not set 923CONFIG_I2C=y
924CONFIG_I2C_BOARDINFO=y
925CONFIG_I2C_CHARDEV=m
926
927#
928# I2C Hardware Bus support
929#
930# CONFIG_I2C_ALI1535 is not set
931# CONFIG_I2C_ALI1563 is not set
932# CONFIG_I2C_ALI15X3 is not set
933# CONFIG_I2C_AMD756 is not set
934# CONFIG_I2C_AMD8111 is not set
935# CONFIG_I2C_GPIO is not set
936# CONFIG_I2C_I801 is not set
937# CONFIG_I2C_I810 is not set
938CONFIG_I2C_PXA=y
939# CONFIG_I2C_PXA_SLAVE is not set
940# CONFIG_I2C_PIIX4 is not set
941# CONFIG_I2C_NFORCE2 is not set
942# CONFIG_I2C_OCORES is not set
943# CONFIG_I2C_PARPORT_LIGHT is not set
944# CONFIG_I2C_PROSAVAGE is not set
945# CONFIG_I2C_SAVAGE4 is not set
946# CONFIG_I2C_SIMTEC is not set
947# CONFIG_I2C_SIS5595 is not set
948# CONFIG_I2C_SIS630 is not set
949# CONFIG_I2C_SIS96X is not set
950# CONFIG_I2C_TAOS_EVM is not set
951# CONFIG_I2C_STUB is not set
952# CONFIG_I2C_TINY_USB is not set
953# CONFIG_I2C_VIA is not set
954# CONFIG_I2C_VIAPRO is not set
955# CONFIG_I2C_VOODOO3 is not set
956# CONFIG_I2C_PCA_PLATFORM is not set
957
958#
959# Miscellaneous I2C Chip support
960#
961# CONFIG_DS1682 is not set
962# CONFIG_SENSORS_EEPROM is not set
963# CONFIG_SENSORS_PCF8574 is not set
964# CONFIG_PCF8575 is not set
965# CONFIG_SENSORS_PCF8591 is not set
966# CONFIG_TPS65010 is not set
967# CONFIG_SENSORS_MAX6875 is not set
968# CONFIG_SENSORS_TSL2550 is not set
969# CONFIG_I2C_DEBUG_CORE is not set
970# CONFIG_I2C_DEBUG_ALGO is not set
971# CONFIG_I2C_DEBUG_BUS is not set
972# CONFIG_I2C_DEBUG_CHIP is not set
973# CONFIG_SPI is not set
974CONFIG_HAVE_GPIO_LIB=y
745 975
746# 976#
747# SPI support 977# GPIO Support
748# 978#
749# CONFIG_SPI is not set 979# CONFIG_DEBUG_GPIO is not set
750# CONFIG_SPI_MASTER is not set
751# CONFIG_W1 is not set
752# CONFIG_HWMON is not set
753CONFIG_MISC_DEVICES=y
754# CONFIG_PHANTOM is not set
755# CONFIG_EEPROM_93CX6 is not set
756# CONFIG_SGI_IOC4 is not set
757# CONFIG_TIFM_CORE is not set
758 980
759# 981#
760# Multifunction device drivers 982# I2C GPIO expanders:
761# 983#
762# CONFIG_MFD_SM501 is not set 984# CONFIG_GPIO_PCA953X is not set
985# CONFIG_GPIO_PCF857X is not set
763 986
764# 987#
765# LED devices 988# SPI GPIO expanders:
766# 989#
767CONFIG_NEW_LEDS=y 990# CONFIG_W1 is not set
768CONFIG_LEDS_CLASS=y 991# CONFIG_POWER_SUPPLY is not set
992# CONFIG_HWMON is not set
993# CONFIG_WATCHDOG is not set
769 994
770# 995#
771# LED drivers 996# Sonics Silicon Backplane
772# 997#
773CONFIG_LEDS_CM_X270=y 998CONFIG_SSB_POSSIBLE=y
999# CONFIG_SSB is not set
774 1000
775# 1001#
776# LED Triggers 1002# Multifunction device drivers
777# 1003#
778CONFIG_LEDS_TRIGGERS=y 1004# CONFIG_MFD_SM501 is not set
779# CONFIG_LEDS_TRIGGER_TIMER is not set 1005# CONFIG_MFD_ASIC3 is not set
780# CONFIG_LEDS_TRIGGER_IDE_DISK is not set 1006# CONFIG_HTC_EGPIO is not set
781CONFIG_LEDS_TRIGGER_HEARTBEAT=y 1007# CONFIG_HTC_PASIC3 is not set
782 1008
783# 1009#
784# Multimedia devices 1010# Multimedia devices
785# 1011#
1012
1013#
1014# Multimedia core support
1015#
786# CONFIG_VIDEO_DEV is not set 1016# CONFIG_VIDEO_DEV is not set
787# CONFIG_DVB_CORE is not set 1017# CONFIG_DVB_CORE is not set
788CONFIG_DAB=y
789# CONFIG_USB_DABUSB is not set
790 1018
791# 1019#
792# Graphics support 1020# Multimedia drivers
793# 1021#
794# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 1022# CONFIG_DAB is not set
795 1023
796# 1024#
797# Display device support 1025# Graphics support
798# 1026#
799# CONFIG_DISPLAY_SUPPORT is not set 1027# CONFIG_DRM is not set
800# CONFIG_VGASTATE is not set 1028# CONFIG_VGASTATE is not set
1029# CONFIG_VIDEO_OUTPUT_CONTROL is not set
801CONFIG_FB=y 1030CONFIG_FB=y
802# CONFIG_FIRMWARE_EDID is not set 1031# CONFIG_FIRMWARE_EDID is not set
803# CONFIG_FB_DDC is not set 1032# CONFIG_FB_DDC is not set
804CONFIG_FB_CFB_FILLRECT=y 1033CONFIG_FB_CFB_FILLRECT=y
805CONFIG_FB_CFB_COPYAREA=y 1034CONFIG_FB_CFB_COPYAREA=y
806CONFIG_FB_CFB_IMAGEBLIT=y 1035CONFIG_FB_CFB_IMAGEBLIT=y
1036# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
807# CONFIG_FB_SYS_FILLRECT is not set 1037# CONFIG_FB_SYS_FILLRECT is not set
808# CONFIG_FB_SYS_COPYAREA is not set 1038# CONFIG_FB_SYS_COPYAREA is not set
809# CONFIG_FB_SYS_IMAGEBLIT is not set 1039# CONFIG_FB_SYS_IMAGEBLIT is not set
1040# CONFIG_FB_FOREIGN_ENDIAN is not set
810# CONFIG_FB_SYS_FOPS is not set 1041# CONFIG_FB_SYS_FOPS is not set
811CONFIG_FB_DEFERRED_IO=y 1042CONFIG_FB_DEFERRED_IO=y
812# CONFIG_FB_SVGALIB is not set 1043# CONFIG_FB_SVGALIB is not set
@@ -842,9 +1073,17 @@ CONFIG_FB_DEFERRED_IO=y
842# CONFIG_FB_ARK is not set 1073# CONFIG_FB_ARK is not set
843# CONFIG_FB_PM3 is not set 1074# CONFIG_FB_PM3 is not set
844CONFIG_FB_PXA=y 1075CONFIG_FB_PXA=y
845# CONFIG_FB_PXA_PARAMETERS is not set 1076# CONFIG_FB_PXA_SMARTPANEL is not set
1077CONFIG_FB_PXA_PARAMETERS=y
846CONFIG_FB_MBX=m 1078CONFIG_FB_MBX=m
1079# CONFIG_FB_AM200EPD is not set
847# CONFIG_FB_VIRTUAL is not set 1080# CONFIG_FB_VIRTUAL is not set
1081# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1082
1083#
1084# Display device support
1085#
1086# CONFIG_DISPLAY_SUPPORT is not set
848 1087
849# 1088#
850# Console display driver support 1089# Console display driver support
@@ -904,10 +1143,12 @@ CONFIG_SND_AC97_CODEC=m
904# CONFIG_SND_AU8810 is not set 1143# CONFIG_SND_AU8810 is not set
905# CONFIG_SND_AU8820 is not set 1144# CONFIG_SND_AU8820 is not set
906# CONFIG_SND_AU8830 is not set 1145# CONFIG_SND_AU8830 is not set
1146# CONFIG_SND_AW2 is not set
907# CONFIG_SND_AZT3328 is not set 1147# CONFIG_SND_AZT3328 is not set
908# CONFIG_SND_BT87X is not set 1148# CONFIG_SND_BT87X is not set
909# CONFIG_SND_CA0106 is not set 1149# CONFIG_SND_CA0106 is not set
910# CONFIG_SND_CMIPCI is not set 1150# CONFIG_SND_CMIPCI is not set
1151# CONFIG_SND_OXYGEN is not set
911# CONFIG_SND_CS4281 is not set 1152# CONFIG_SND_CS4281 is not set
912# CONFIG_SND_CS46XX is not set 1153# CONFIG_SND_CS46XX is not set
913# CONFIG_SND_DARLA20 is not set 1154# CONFIG_SND_DARLA20 is not set
@@ -932,6 +1173,7 @@ CONFIG_SND_AC97_CODEC=m
932# CONFIG_SND_HDA_INTEL is not set 1173# CONFIG_SND_HDA_INTEL is not set
933# CONFIG_SND_HDSP is not set 1174# CONFIG_SND_HDSP is not set
934# CONFIG_SND_HDSPM is not set 1175# CONFIG_SND_HDSPM is not set
1176# CONFIG_SND_HIFIER is not set
935# CONFIG_SND_ICE1712 is not set 1177# CONFIG_SND_ICE1712 is not set
936# CONFIG_SND_ICE1724 is not set 1178# CONFIG_SND_ICE1724 is not set
937# CONFIG_SND_INTEL8X0 is not set 1179# CONFIG_SND_INTEL8X0 is not set
@@ -949,6 +1191,7 @@ CONFIG_SND_AC97_CODEC=m
949# CONFIG_SND_TRIDENT is not set 1191# CONFIG_SND_TRIDENT is not set
950# CONFIG_SND_VIA82XX is not set 1192# CONFIG_SND_VIA82XX is not set
951# CONFIG_SND_VIA82XX_MODEM is not set 1193# CONFIG_SND_VIA82XX_MODEM is not set
1194# CONFIG_SND_VIRTUOSO is not set
952# CONFIG_SND_VX222 is not set 1195# CONFIG_SND_VX222 is not set
953# CONFIG_SND_YMFPCI is not set 1196# CONFIG_SND_YMFPCI is not set
954# CONFIG_SND_AC97_POWER_SAVE is not set 1197# CONFIG_SND_AC97_POWER_SAVE is not set
@@ -966,18 +1209,33 @@ CONFIG_SND_PXA2XX_AC97=m
966# CONFIG_SND_USB_CAIAQ is not set 1209# CONFIG_SND_USB_CAIAQ is not set
967 1210
968# 1211#
1212# PCMCIA devices
1213#
1214# CONFIG_SND_VXPOCKET is not set
1215# CONFIG_SND_PDAUDIOCF is not set
1216
1217#
969# System on Chip audio support 1218# System on Chip audio support
970# 1219#
971# CONFIG_SND_SOC is not set 1220# CONFIG_SND_SOC is not set
972 1221
973# 1222#
1223# ALSA SoC audio for Freescale SOCs
1224#
1225
1226#
1227# SoC Audio for the Texas Instruments OMAP
1228#
1229
1230#
974# Open Sound System 1231# Open Sound System
975# 1232#
976# CONFIG_SOUND_PRIME is not set 1233# CONFIG_SOUND_PRIME is not set
977CONFIG_AC97_BUS=m 1234CONFIG_AC97_BUS=m
978CONFIG_HID_SUPPORT=y 1235CONFIG_HID_SUPPORT=y
979CONFIG_HID=y 1236CONFIG_HID=y
980# CONFIG_HID_DEBUG is not set 1237CONFIG_HID_DEBUG=y
1238# CONFIG_HIDRAW is not set
981 1239
982# 1240#
983# USB Input Devices 1241# USB Input Devices
@@ -992,6 +1250,7 @@ CONFIG_USB_ARCH_HAS_OHCI=y
992CONFIG_USB_ARCH_HAS_EHCI=y 1250CONFIG_USB_ARCH_HAS_EHCI=y
993CONFIG_USB=y 1251CONFIG_USB=y
994# CONFIG_USB_DEBUG is not set 1252# CONFIG_USB_DEBUG is not set
1253# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
995 1254
996# 1255#
997# Miscellaneous USB options 1256# Miscellaneous USB options
@@ -1000,8 +1259,9 @@ CONFIG_USB_DEVICEFS=y
1000# CONFIG_USB_DEVICE_CLASS is not set 1259# CONFIG_USB_DEVICE_CLASS is not set
1001# CONFIG_USB_DYNAMIC_MINORS is not set 1260# CONFIG_USB_DYNAMIC_MINORS is not set
1002# CONFIG_USB_SUSPEND is not set 1261# CONFIG_USB_SUSPEND is not set
1003# CONFIG_USB_PERSIST is not set
1004# CONFIG_USB_OTG is not set 1262# CONFIG_USB_OTG is not set
1263# CONFIG_USB_OTG_WHITELIST is not set
1264# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1005 1265
1006# 1266#
1007# USB Host Controller Drivers 1267# USB Host Controller Drivers
@@ -1033,13 +1293,16 @@ CONFIG_USB_STORAGE=y
1033# CONFIG_USB_STORAGE_DEBUG is not set 1293# CONFIG_USB_STORAGE_DEBUG is not set
1034# CONFIG_USB_STORAGE_DATAFAB is not set 1294# CONFIG_USB_STORAGE_DATAFAB is not set
1035# CONFIG_USB_STORAGE_FREECOM is not set 1295# CONFIG_USB_STORAGE_FREECOM is not set
1296# CONFIG_USB_STORAGE_ISD200 is not set
1036# CONFIG_USB_STORAGE_DPCM is not set 1297# CONFIG_USB_STORAGE_DPCM is not set
1037# CONFIG_USB_STORAGE_USBAT is not set 1298# CONFIG_USB_STORAGE_USBAT is not set
1038# CONFIG_USB_STORAGE_SDDR09 is not set 1299# CONFIG_USB_STORAGE_SDDR09 is not set
1039# CONFIG_USB_STORAGE_SDDR55 is not set 1300# CONFIG_USB_STORAGE_SDDR55 is not set
1040# CONFIG_USB_STORAGE_JUMPSHOT is not set 1301# CONFIG_USB_STORAGE_JUMPSHOT is not set
1041# CONFIG_USB_STORAGE_ALAUDA is not set 1302# CONFIG_USB_STORAGE_ALAUDA is not set
1303# CONFIG_USB_STORAGE_ONETOUCH is not set
1042# CONFIG_USB_STORAGE_KARMA is not set 1304# CONFIG_USB_STORAGE_KARMA is not set
1305# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1043# CONFIG_USB_LIBUSUAL is not set 1306# CONFIG_USB_LIBUSUAL is not set
1044 1307
1045# 1308#
@@ -1052,10 +1315,6 @@ CONFIG_USB_MON=y
1052# 1315#
1053# USB port drivers 1316# USB port drivers
1054# 1317#
1055
1056#
1057# USB Serial Converter support
1058#
1059# CONFIG_USB_SERIAL is not set 1318# CONFIG_USB_SERIAL is not set
1060 1319
1061# 1320#
@@ -1080,14 +1339,6 @@ CONFIG_USB_MON=y
1080# CONFIG_USB_TRANCEVIBRATOR is not set 1339# CONFIG_USB_TRANCEVIBRATOR is not set
1081# CONFIG_USB_IOWARRIOR is not set 1340# CONFIG_USB_IOWARRIOR is not set
1082# CONFIG_USB_TEST is not set 1341# CONFIG_USB_TEST is not set
1083
1084#
1085# USB DSL modem support
1086#
1087
1088#
1089# USB Gadget Support
1090#
1091# CONFIG_USB_GADGET is not set 1342# CONFIG_USB_GADGET is not set
1092CONFIG_MMC=m 1343CONFIG_MMC=m
1093# CONFIG_MMC_DEBUG is not set 1344# CONFIG_MMC_DEBUG is not set
@@ -1098,6 +1349,7 @@ CONFIG_MMC=m
1098# 1349#
1099CONFIG_MMC_BLOCK=m 1350CONFIG_MMC_BLOCK=m
1100CONFIG_MMC_BLOCK_BOUNCE=y 1351CONFIG_MMC_BLOCK_BOUNCE=y
1352# CONFIG_SDIO_UART is not set
1101 1353
1102# 1354#
1103# MMC/SD Host Controller Drivers 1355# MMC/SD Host Controller Drivers
@@ -1105,10 +1357,22 @@ CONFIG_MMC_BLOCK_BOUNCE=y
1105CONFIG_MMC_PXA=m 1357CONFIG_MMC_PXA=m
1106# CONFIG_MMC_SDHCI is not set 1358# CONFIG_MMC_SDHCI is not set
1107# CONFIG_MMC_TIFM_SD is not set 1359# CONFIG_MMC_TIFM_SD is not set
1360CONFIG_NEW_LEDS=y
1361CONFIG_LEDS_CLASS=y
1108 1362
1109# 1363#
1110# Real Time Clock 1364# LED drivers
1365#
1366# CONFIG_LEDS_GPIO is not set
1367CONFIG_LEDS_CM_X270=y
1368
1369#
1370# LED Triggers
1111# 1371#
1372CONFIG_LEDS_TRIGGERS=y
1373# CONFIG_LEDS_TRIGGER_TIMER is not set
1374CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1375# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
1112CONFIG_RTC_LIB=y 1376CONFIG_RTC_LIB=y
1113CONFIG_RTC_CLASS=y 1377CONFIG_RTC_CLASS=y
1114CONFIG_RTC_HCTOSYS=y 1378CONFIG_RTC_HCTOSYS=y
@@ -1125,11 +1389,32 @@ CONFIG_RTC_INTF_DEV=y
1125# CONFIG_RTC_DRV_TEST is not set 1389# CONFIG_RTC_DRV_TEST is not set
1126 1390
1127# 1391#
1392# I2C RTC drivers
1393#
1394# CONFIG_RTC_DRV_DS1307 is not set
1395# CONFIG_RTC_DRV_DS1374 is not set
1396# CONFIG_RTC_DRV_DS1672 is not set
1397# CONFIG_RTC_DRV_MAX6900 is not set
1398# CONFIG_RTC_DRV_RS5C372 is not set
1399# CONFIG_RTC_DRV_ISL1208 is not set
1400# CONFIG_RTC_DRV_X1205 is not set
1401# CONFIG_RTC_DRV_PCF8563 is not set
1402# CONFIG_RTC_DRV_PCF8583 is not set
1403# CONFIG_RTC_DRV_M41T80 is not set
1404# CONFIG_RTC_DRV_S35390A is not set
1405
1406#
1407# SPI RTC drivers
1408#
1409
1410#
1128# Platform RTC drivers 1411# Platform RTC drivers
1129# 1412#
1130# CONFIG_RTC_DRV_CMOS is not set 1413# CONFIG_RTC_DRV_CMOS is not set
1414# CONFIG_RTC_DRV_DS1511 is not set
1131# CONFIG_RTC_DRV_DS1553 is not set 1415# CONFIG_RTC_DRV_DS1553 is not set
1132# CONFIG_RTC_DRV_DS1742 is not set 1416# CONFIG_RTC_DRV_DS1742 is not set
1417# CONFIG_RTC_DRV_STK17TA8 is not set
1133# CONFIG_RTC_DRV_M48T86 is not set 1418# CONFIG_RTC_DRV_M48T86 is not set
1134# CONFIG_RTC_DRV_M48T59 is not set 1419# CONFIG_RTC_DRV_M48T59 is not set
1135CONFIG_RTC_DRV_V3020=y 1420CONFIG_RTC_DRV_V3020=y
@@ -1138,19 +1423,7 @@ CONFIG_RTC_DRV_V3020=y
1138# on-CPU RTC drivers 1423# on-CPU RTC drivers
1139# 1424#
1140CONFIG_RTC_DRV_SA1100=y 1425CONFIG_RTC_DRV_SA1100=y
1141 1426# CONFIG_UIO is not set
1142#
1143# DMA Engine support
1144#
1145# CONFIG_DMA_ENGINE is not set
1146
1147#
1148# DMA Clients
1149#
1150
1151#
1152# DMA Devices
1153#
1154 1427
1155# 1428#
1156# File systems 1429# File systems
@@ -1164,20 +1437,16 @@ CONFIG_EXT3_FS_XATTR=y
1164# CONFIG_EXT3_FS_SECURITY is not set 1437# CONFIG_EXT3_FS_SECURITY is not set
1165# CONFIG_EXT4DEV_FS is not set 1438# CONFIG_EXT4DEV_FS is not set
1166CONFIG_JBD=y 1439CONFIG_JBD=y
1167# CONFIG_JBD_DEBUG is not set
1168CONFIG_FS_MBCACHE=y 1440CONFIG_FS_MBCACHE=y
1169# CONFIG_REISERFS_FS is not set 1441# CONFIG_REISERFS_FS is not set
1170# CONFIG_JFS_FS is not set 1442# CONFIG_JFS_FS is not set
1171# CONFIG_FS_POSIX_ACL is not set 1443# CONFIG_FS_POSIX_ACL is not set
1172# CONFIG_XFS_FS is not set 1444# CONFIG_XFS_FS is not set
1173# CONFIG_GFS2_FS is not set
1174# CONFIG_OCFS2_FS is not set 1445# CONFIG_OCFS2_FS is not set
1175# CONFIG_MINIX_FS is not set 1446CONFIG_DNOTIFY=y
1176# CONFIG_ROMFS_FS is not set
1177CONFIG_INOTIFY=y 1447CONFIG_INOTIFY=y
1178CONFIG_INOTIFY_USER=y 1448CONFIG_INOTIFY_USER=y
1179# CONFIG_QUOTA is not set 1449# CONFIG_QUOTA is not set
1180CONFIG_DNOTIFY=y
1181# CONFIG_AUTOFS_FS is not set 1450# CONFIG_AUTOFS_FS is not set
1182# CONFIG_AUTOFS4_FS is not set 1451# CONFIG_AUTOFS4_FS is not set
1183# CONFIG_FUSE_FS is not set 1452# CONFIG_FUSE_FS is not set
@@ -1191,9 +1460,9 @@ CONFIG_DNOTIFY=y
1191# 1460#
1192# DOS/FAT/NT Filesystems 1461# DOS/FAT/NT Filesystems
1193# 1462#
1194CONFIG_FAT_FS=y 1463CONFIG_FAT_FS=m
1195CONFIG_MSDOS_FS=y 1464# CONFIG_MSDOS_FS is not set
1196CONFIG_VFAT_FS=y 1465CONFIG_VFAT_FS=m
1197CONFIG_FAT_DEFAULT_CODEPAGE=437 1466CONFIG_FAT_DEFAULT_CODEPAGE=437
1198CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" 1467CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1199# CONFIG_NTFS_FS is not set 1468# CONFIG_NTFS_FS is not set
@@ -1207,7 +1476,6 @@ CONFIG_SYSFS=y
1207CONFIG_TMPFS=y 1476CONFIG_TMPFS=y
1208# CONFIG_TMPFS_POSIX_ACL is not set 1477# CONFIG_TMPFS_POSIX_ACL is not set
1209# CONFIG_HUGETLB_PAGE is not set 1478# CONFIG_HUGETLB_PAGE is not set
1210CONFIG_RAMFS=y
1211# CONFIG_CONFIGFS_FS is not set 1479# CONFIG_CONFIGFS_FS is not set
1212 1480
1213# 1481#
@@ -1220,22 +1488,30 @@ CONFIG_RAMFS=y
1220# CONFIG_BEFS_FS is not set 1488# CONFIG_BEFS_FS is not set
1221# CONFIG_BFS_FS is not set 1489# CONFIG_BFS_FS is not set
1222# CONFIG_EFS_FS is not set 1490# CONFIG_EFS_FS is not set
1223# CONFIG_JFFS2_FS is not set 1491CONFIG_JFFS2_FS=y
1492CONFIG_JFFS2_FS_DEBUG=0
1493CONFIG_JFFS2_FS_WRITEBUFFER=y
1494# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1495CONFIG_JFFS2_SUMMARY=y
1496# CONFIG_JFFS2_FS_XATTR is not set
1497# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1498CONFIG_JFFS2_ZLIB=y
1499# CONFIG_JFFS2_LZO is not set
1500CONFIG_JFFS2_RTIME=y
1501# CONFIG_JFFS2_RUBIN is not set
1224# CONFIG_CRAMFS is not set 1502# CONFIG_CRAMFS is not set
1225# CONFIG_VXFS_FS is not set 1503# CONFIG_VXFS_FS is not set
1504# CONFIG_MINIX_FS is not set
1226# CONFIG_HPFS_FS is not set 1505# CONFIG_HPFS_FS is not set
1227# CONFIG_QNX4FS_FS is not set 1506# CONFIG_QNX4FS_FS is not set
1507# CONFIG_ROMFS_FS is not set
1228# CONFIG_SYSV_FS is not set 1508# CONFIG_SYSV_FS is not set
1229# CONFIG_UFS_FS is not set 1509# CONFIG_UFS_FS is not set
1230 1510CONFIG_NETWORK_FILESYSTEMS=y
1231#
1232# Network File Systems
1233#
1234CONFIG_NFS_FS=y 1511CONFIG_NFS_FS=y
1235CONFIG_NFS_V3=y 1512CONFIG_NFS_V3=y
1236# CONFIG_NFS_V3_ACL is not set 1513# CONFIG_NFS_V3_ACL is not set
1237# CONFIG_NFS_V4 is not set 1514# CONFIG_NFS_V4 is not set
1238# CONFIG_NFS_DIRECTIO is not set
1239# CONFIG_NFSD is not set 1515# CONFIG_NFSD is not set
1240CONFIG_ROOT_NFS=y 1516CONFIG_ROOT_NFS=y
1241CONFIG_LOCKD=y 1517CONFIG_LOCKD=y
@@ -1245,9 +1521,13 @@ CONFIG_SUNRPC=y
1245# CONFIG_SUNRPC_BIND34 is not set 1521# CONFIG_SUNRPC_BIND34 is not set
1246# CONFIG_RPCSEC_GSS_KRB5 is not set 1522# CONFIG_RPCSEC_GSS_KRB5 is not set
1247# CONFIG_RPCSEC_GSS_SPKM3 is not set 1523# CONFIG_RPCSEC_GSS_SPKM3 is not set
1248CONFIG_SMB_FS=y 1524# CONFIG_SMB_FS is not set
1249# CONFIG_SMB_NLS_DEFAULT is not set 1525CONFIG_CIFS=m
1250# CONFIG_CIFS is not set 1526# CONFIG_CIFS_STATS is not set
1527# CONFIG_CIFS_WEAK_PW_HASH is not set
1528# CONFIG_CIFS_XATTR is not set
1529# CONFIG_CIFS_DEBUG2 is not set
1530# CONFIG_CIFS_EXPERIMENTAL is not set
1251# CONFIG_NCP_FS is not set 1531# CONFIG_NCP_FS is not set
1252# CONFIG_CODA_FS is not set 1532# CONFIG_CODA_FS is not set
1253# CONFIG_AFS_FS is not set 1533# CONFIG_AFS_FS is not set
@@ -1255,15 +1535,27 @@ CONFIG_SMB_FS=y
1255# 1535#
1256# Partition Types 1536# Partition Types
1257# 1537#
1258# CONFIG_PARTITION_ADVANCED is not set 1538CONFIG_PARTITION_ADVANCED=y
1539# CONFIG_ACORN_PARTITION is not set
1540# CONFIG_OSF_PARTITION is not set
1541# CONFIG_AMIGA_PARTITION is not set
1542# CONFIG_ATARI_PARTITION is not set
1543# CONFIG_MAC_PARTITION is not set
1259CONFIG_MSDOS_PARTITION=y 1544CONFIG_MSDOS_PARTITION=y
1260 1545# CONFIG_BSD_DISKLABEL is not set
1261# 1546# CONFIG_MINIX_SUBPARTITION is not set
1262# Native Language Support 1547# CONFIG_SOLARIS_X86_PARTITION is not set
1263# 1548# CONFIG_UNIXWARE_DISKLABEL is not set
1264CONFIG_NLS=y 1549# CONFIG_LDM_PARTITION is not set
1550# CONFIG_SGI_PARTITION is not set
1551# CONFIG_ULTRIX_PARTITION is not set
1552# CONFIG_SUN_PARTITION is not set
1553# CONFIG_KARMA_PARTITION is not set
1554# CONFIG_EFI_PARTITION is not set
1555# CONFIG_SYSV68_PARTITION is not set
1556CONFIG_NLS=m
1265CONFIG_NLS_DEFAULT="iso8859-1" 1557CONFIG_NLS_DEFAULT="iso8859-1"
1266CONFIG_NLS_CODEPAGE_437=y 1558CONFIG_NLS_CODEPAGE_437=m
1267# CONFIG_NLS_CODEPAGE_737 is not set 1559# CONFIG_NLS_CODEPAGE_737 is not set
1268# CONFIG_NLS_CODEPAGE_775 is not set 1560# CONFIG_NLS_CODEPAGE_775 is not set
1269# CONFIG_NLS_CODEPAGE_850 is not set 1561# CONFIG_NLS_CODEPAGE_850 is not set
@@ -1287,7 +1579,7 @@ CONFIG_NLS_CODEPAGE_437=y
1287# CONFIG_NLS_CODEPAGE_1250 is not set 1579# CONFIG_NLS_CODEPAGE_1250 is not set
1288# CONFIG_NLS_CODEPAGE_1251 is not set 1580# CONFIG_NLS_CODEPAGE_1251 is not set
1289# CONFIG_NLS_ASCII is not set 1581# CONFIG_NLS_ASCII is not set
1290CONFIG_NLS_ISO8859_1=y 1582CONFIG_NLS_ISO8859_1=m
1291# CONFIG_NLS_ISO8859_2 is not set 1583# CONFIG_NLS_ISO8859_2 is not set
1292# CONFIG_NLS_ISO8859_3 is not set 1584# CONFIG_NLS_ISO8859_3 is not set
1293# CONFIG_NLS_ISO8859_4 is not set 1585# CONFIG_NLS_ISO8859_4 is not set
@@ -1300,53 +1592,52 @@ CONFIG_NLS_ISO8859_1=y
1300# CONFIG_NLS_ISO8859_15 is not set 1592# CONFIG_NLS_ISO8859_15 is not set
1301# CONFIG_NLS_KOI8_R is not set 1593# CONFIG_NLS_KOI8_R is not set
1302# CONFIG_NLS_KOI8_U is not set 1594# CONFIG_NLS_KOI8_U is not set
1303# CONFIG_NLS_UTF8 is not set 1595CONFIG_NLS_UTF8=m
1304
1305#
1306# Distributed Lock Manager
1307#
1308# CONFIG_DLM is not set 1596# CONFIG_DLM is not set
1309 1597
1310# 1598#
1311# Profiling support
1312#
1313# CONFIG_PROFILING is not set
1314
1315#
1316# Kernel hacking 1599# Kernel hacking
1317# 1600#
1318# CONFIG_PRINTK_TIME is not set 1601# CONFIG_PRINTK_TIME is not set
1602CONFIG_ENABLE_WARN_DEPRECATED=y
1319CONFIG_ENABLE_MUST_CHECK=y 1603CONFIG_ENABLE_MUST_CHECK=y
1320CONFIG_MAGIC_SYSRQ=y 1604CONFIG_FRAME_WARN=0
1605# CONFIG_MAGIC_SYSRQ is not set
1321# CONFIG_UNUSED_SYMBOLS is not set 1606# CONFIG_UNUSED_SYMBOLS is not set
1322# CONFIG_DEBUG_FS is not set 1607# CONFIG_DEBUG_FS is not set
1323# CONFIG_HEADERS_CHECK is not set 1608# CONFIG_HEADERS_CHECK is not set
1324CONFIG_DEBUG_KERNEL=y 1609CONFIG_DEBUG_KERNEL=y
1325# CONFIG_DEBUG_SHIRQ is not set 1610# CONFIG_DEBUG_SHIRQ is not set
1326# CONFIG_DETECT_SOFTLOCKUP is not set 1611# CONFIG_DETECT_SOFTLOCKUP is not set
1327CONFIG_SCHED_DEBUG=y 1612# CONFIG_SCHED_DEBUG is not set
1328# CONFIG_SCHEDSTATS is not set 1613# CONFIG_SCHEDSTATS is not set
1329# CONFIG_TIMER_STATS is not set 1614# CONFIG_TIMER_STATS is not set
1330# CONFIG_DEBUG_SLAB is not set 1615# CONFIG_DEBUG_OBJECTS is not set
1331# CONFIG_DEBUG_RT_MUTEXES is not set 1616# CONFIG_DEBUG_RT_MUTEXES is not set
1332# CONFIG_RT_MUTEX_TESTER is not set 1617# CONFIG_RT_MUTEX_TESTER is not set
1333# CONFIG_DEBUG_SPINLOCK is not set 1618# CONFIG_DEBUG_SPINLOCK is not set
1334# CONFIG_DEBUG_MUTEXES is not set 1619# CONFIG_DEBUG_MUTEXES is not set
1335# CONFIG_DEBUG_LOCK_ALLOC is not set 1620# CONFIG_DEBUG_LOCK_ALLOC is not set
1336# CONFIG_PROVE_LOCKING is not set 1621# CONFIG_PROVE_LOCKING is not set
1622# CONFIG_LOCK_STAT is not set
1337# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1623# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1338# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1624# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1339# CONFIG_DEBUG_KOBJECT is not set 1625# CONFIG_DEBUG_KOBJECT is not set
1340# CONFIG_DEBUG_BUGVERBOSE is not set 1626# CONFIG_DEBUG_BUGVERBOSE is not set
1341CONFIG_DEBUG_INFO=y 1627# CONFIG_DEBUG_INFO is not set
1342# CONFIG_DEBUG_VM is not set 1628# CONFIG_DEBUG_VM is not set
1629# CONFIG_DEBUG_WRITECOUNT is not set
1343# CONFIG_DEBUG_LIST is not set 1630# CONFIG_DEBUG_LIST is not set
1631# CONFIG_DEBUG_SG is not set
1344CONFIG_FRAME_POINTER=y 1632CONFIG_FRAME_POINTER=y
1345CONFIG_FORCED_INLINING=y 1633# CONFIG_BOOT_PRINTK_DELAY is not set
1346# CONFIG_RCU_TORTURE_TEST is not set 1634# CONFIG_RCU_TORTURE_TEST is not set
1635# CONFIG_BACKTRACE_SELF_TEST is not set
1347# CONFIG_FAULT_INJECTION is not set 1636# CONFIG_FAULT_INJECTION is not set
1637# CONFIG_SAMPLES is not set
1348CONFIG_DEBUG_USER=y 1638CONFIG_DEBUG_USER=y
1349CONFIG_DEBUG_ERRORS=y 1639CONFIG_DEBUG_ERRORS=y
1640# CONFIG_DEBUG_STACK_USAGE is not set
1350CONFIG_DEBUG_LL=y 1641CONFIG_DEBUG_LL=y
1351# CONFIG_DEBUG_ICEDCC is not set 1642# CONFIG_DEBUG_ICEDCC is not set
1352 1643
@@ -1355,55 +1646,96 @@ CONFIG_DEBUG_LL=y
1355# 1646#
1356# CONFIG_KEYS is not set 1647# CONFIG_KEYS is not set
1357# CONFIG_SECURITY is not set 1648# CONFIG_SECURITY is not set
1649# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1358CONFIG_CRYPTO=y 1650CONFIG_CRYPTO=y
1359CONFIG_CRYPTO_ALGAPI=m 1651
1360CONFIG_CRYPTO_BLKCIPHER=m 1652#
1361CONFIG_CRYPTO_MANAGER=m 1653# Crypto core or helper
1654#
1655# CONFIG_CRYPTO_MANAGER is not set
1656# CONFIG_CRYPTO_GF128MUL is not set
1657# CONFIG_CRYPTO_NULL is not set
1658# CONFIG_CRYPTO_CRYPTD is not set
1659# CONFIG_CRYPTO_AUTHENC is not set
1660# CONFIG_CRYPTO_TEST is not set
1661
1662#
1663# Authenticated Encryption with Associated Data
1664#
1665# CONFIG_CRYPTO_CCM is not set
1666# CONFIG_CRYPTO_GCM is not set
1667# CONFIG_CRYPTO_SEQIV is not set
1668
1669#
1670# Block modes
1671#
1672# CONFIG_CRYPTO_CBC is not set
1673# CONFIG_CRYPTO_CTR is not set
1674# CONFIG_CRYPTO_CTS is not set
1675# CONFIG_CRYPTO_ECB is not set
1676# CONFIG_CRYPTO_LRW is not set
1677# CONFIG_CRYPTO_PCBC is not set
1678# CONFIG_CRYPTO_XTS is not set
1679
1680#
1681# Hash modes
1682#
1362# CONFIG_CRYPTO_HMAC is not set 1683# CONFIG_CRYPTO_HMAC is not set
1363# CONFIG_CRYPTO_XCBC is not set 1684# CONFIG_CRYPTO_XCBC is not set
1364# CONFIG_CRYPTO_NULL is not set 1685
1686#
1687# Digest
1688#
1689# CONFIG_CRYPTO_CRC32C is not set
1365# CONFIG_CRYPTO_MD4 is not set 1690# CONFIG_CRYPTO_MD4 is not set
1366# CONFIG_CRYPTO_MD5 is not set 1691# CONFIG_CRYPTO_MD5 is not set
1692# CONFIG_CRYPTO_MICHAEL_MIC is not set
1367# CONFIG_CRYPTO_SHA1 is not set 1693# CONFIG_CRYPTO_SHA1 is not set
1368# CONFIG_CRYPTO_SHA256 is not set 1694# CONFIG_CRYPTO_SHA256 is not set
1369# CONFIG_CRYPTO_SHA512 is not set 1695# CONFIG_CRYPTO_SHA512 is not set
1370# CONFIG_CRYPTO_WP512 is not set
1371# CONFIG_CRYPTO_TGR192 is not set 1696# CONFIG_CRYPTO_TGR192 is not set
1372# CONFIG_CRYPTO_GF128MUL is not set 1697# CONFIG_CRYPTO_WP512 is not set
1373CONFIG_CRYPTO_ECB=m 1698
1374CONFIG_CRYPTO_CBC=m 1699#
1375CONFIG_CRYPTO_PCBC=m 1700# Ciphers
1376# CONFIG_CRYPTO_LRW is not set 1701#
1377# CONFIG_CRYPTO_CRYPTD is not set 1702# CONFIG_CRYPTO_AES is not set
1378# CONFIG_CRYPTO_DES is not set 1703# CONFIG_CRYPTO_ANUBIS is not set
1379# CONFIG_CRYPTO_FCRYPT is not set 1704# CONFIG_CRYPTO_ARC4 is not set
1380# CONFIG_CRYPTO_BLOWFISH is not set 1705# CONFIG_CRYPTO_BLOWFISH is not set
1381# CONFIG_CRYPTO_TWOFISH is not set 1706# CONFIG_CRYPTO_CAMELLIA is not set
1382# CONFIG_CRYPTO_SERPENT is not set
1383CONFIG_CRYPTO_AES=m
1384# CONFIG_CRYPTO_CAST5 is not set 1707# CONFIG_CRYPTO_CAST5 is not set
1385# CONFIG_CRYPTO_CAST6 is not set 1708# CONFIG_CRYPTO_CAST6 is not set
1386# CONFIG_CRYPTO_TEA is not set 1709# CONFIG_CRYPTO_DES is not set
1387CONFIG_CRYPTO_ARC4=m 1710# CONFIG_CRYPTO_FCRYPT is not set
1388# CONFIG_CRYPTO_KHAZAD is not set 1711# CONFIG_CRYPTO_KHAZAD is not set
1389# CONFIG_CRYPTO_ANUBIS is not set 1712# CONFIG_CRYPTO_SALSA20 is not set
1713# CONFIG_CRYPTO_SEED is not set
1714# CONFIG_CRYPTO_SERPENT is not set
1715# CONFIG_CRYPTO_TEA is not set
1716# CONFIG_CRYPTO_TWOFISH is not set
1717
1718#
1719# Compression
1720#
1390# CONFIG_CRYPTO_DEFLATE is not set 1721# CONFIG_CRYPTO_DEFLATE is not set
1391# CONFIG_CRYPTO_MICHAEL_MIC is not set 1722# CONFIG_CRYPTO_LZO is not set
1392# CONFIG_CRYPTO_CRC32C is not set 1723# CONFIG_CRYPTO_HW is not set
1393# CONFIG_CRYPTO_CAMELLIA is not set
1394# CONFIG_CRYPTO_TEST is not set
1395CONFIG_CRYPTO_HW=y
1396 1724
1397# 1725#
1398# Library routines 1726# Library routines
1399# 1727#
1400CONFIG_BITREVERSE=y 1728CONFIG_BITREVERSE=y
1401# CONFIG_CRC_CCITT is not set 1729# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1730# CONFIG_GENERIC_FIND_NEXT_BIT is not set
1731CONFIG_CRC_CCITT=m
1402# CONFIG_CRC16 is not set 1732# CONFIG_CRC16 is not set
1403# CONFIG_CRC_ITU_T is not set 1733# CONFIG_CRC_ITU_T is not set
1404CONFIG_CRC32=y 1734CONFIG_CRC32=y
1405# CONFIG_CRC7 is not set 1735# CONFIG_CRC7 is not set
1406# CONFIG_LIBCRC32C is not set 1736# CONFIG_LIBCRC32C is not set
1737CONFIG_ZLIB_INFLATE=y
1738CONFIG_ZLIB_DEFLATE=y
1407CONFIG_PLIST=y 1739CONFIG_PLIST=y
1408CONFIG_HAS_IOMEM=y 1740CONFIG_HAS_IOMEM=y
1409CONFIG_HAS_IOPORT=y 1741CONFIG_HAS_IOPORT=y
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 5da7a6820492..914bb33dab92 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -20,8 +20,7 @@ endmenu
20 20
21endif 21endif
22 22
23choice 23menu "Select target boards"
24 prompt "Select target board"
25 24
26config ARCH_GUMSTIX 25config ARCH_GUMSTIX
27 bool "Gumstix XScale boards" 26 bool "Gumstix XScale boards"
@@ -37,10 +36,12 @@ config ARCH_LUBBOCK
37config MACH_LOGICPD_PXA270 36config MACH_LOGICPD_PXA270
38 bool "LogicPD PXA270 Card Engine Development Platform" 37 bool "LogicPD PXA270 Card Engine Development Platform"
39 select PXA27x 38 select PXA27x
39 select HAVE_PWM
40 40
41config MACH_MAINSTONE 41config MACH_MAINSTONE
42 bool "Intel HCDDBBVA0 Development Platform" 42 bool "Intel HCDDBBVA0 Development Platform"
43 select PXA27x 43 select PXA27x
44 select HAVE_PWM
44 45
45config ARCH_PXA_IDP 46config ARCH_PXA_IDP
46 bool "Accelent Xscale IDP" 47 bool "Accelent Xscale IDP"
@@ -116,6 +117,7 @@ config MACH_COLIBRI
116config MACH_ZYLONITE 117config MACH_ZYLONITE
117 bool "PXA3xx Development Platform" 118 bool "PXA3xx Development Platform"
118 select PXA3xx 119 select PXA3xx
120 select HAVE_PWM
119 121
120config MACH_LITTLETON 122config MACH_LITTLETON
121 bool "PXA3xx Form Factor Platform (aka Littleton)" 123 bool "PXA3xx Form Factor Platform (aka Littleton)"
@@ -138,7 +140,7 @@ config MACH_PCM027
138 select PXA27x 140 select PXA27x
139 select IWMMXT 141 select IWMMXT
140 142
141endchoice 143endmenu
142 144
143choice 145choice
144 prompt "Used baseboard" 146 prompt "Used baseboard"
@@ -146,25 +148,24 @@ choice
146 148
147config MACH_PCM990_BASEBOARD 149config MACH_PCM990_BASEBOARD
148 bool "PHYTEC PCM-990 development board" 150 bool "PHYTEC PCM-990 development board"
151 select HAVE_PWM
149 152
150endchoice 153endchoice
151 154
152if PXA_SHARPSL
153
154choice 155choice
155 prompt "Select target Sharp Zaurus device range" 156 prompt "display on pcm990"
157 depends on MACH_PCM990_BASEBOARD
156 158
157config PXA_SHARPSL_25x 159config PCM990_DISPLAY_SHARP
158 bool "Sharp PXA25x models (SL-5600, SL-C7xx and SL-C6000x)" 160 bool "sharp lq084v1dg21 stn display"
159 select PXA25x
160 161
161config PXA_SHARPSL_27x 162config PCM990_DISPLAY_NEC
162 bool "Sharp PXA270 models (SL-Cxx00)" 163 bool "nec nl6448bc20_18d tft display"
163 select PXA27x
164 164
165endchoice 165config PCM990_DISPLAY_NONE
166 bool "no display"
166 167
167endif 168endchoice
168 169
169if ARCH_GUMSTIX 170if ARCH_GUMSTIX
170 171
@@ -199,28 +200,33 @@ endmenu
199 200
200config MACH_POODLE 201config MACH_POODLE
201 bool "Enable Sharp SL-5600 (Poodle) Support" 202 bool "Enable Sharp SL-5600 (Poodle) Support"
202 depends on PXA_SHARPSL_25x 203 depends on PXA_SHARPSL
204 select PXA25x
203 select SHARP_LOCOMO 205 select SHARP_LOCOMO
204 select PXA_SSP 206 select PXA_SSP
205 207
206config MACH_CORGI 208config MACH_CORGI
207 bool "Enable Sharp SL-C700 (Corgi) Support" 209 bool "Enable Sharp SL-C700 (Corgi) Support"
208 depends on PXA_SHARPSL_25x 210 depends on PXA_SHARPSL
211 select PXA25x
209 select PXA_SHARP_C7xx 212 select PXA_SHARP_C7xx
210 213
211config MACH_SHEPHERD 214config MACH_SHEPHERD
212 bool "Enable Sharp SL-C750 (Shepherd) Support" 215 bool "Enable Sharp SL-C750 (Shepherd) Support"
213 depends on PXA_SHARPSL_25x 216 depends on PXA_SHARPSL
217 select PXA25x
214 select PXA_SHARP_C7xx 218 select PXA_SHARP_C7xx
215 219
216config MACH_HUSKY 220config MACH_HUSKY
217 bool "Enable Sharp SL-C760 (Husky) Support" 221 bool "Enable Sharp SL-C760 (Husky) Support"
218 depends on PXA_SHARPSL_25x 222 depends on PXA_SHARPSL
223 select PXA25x
219 select PXA_SHARP_C7xx 224 select PXA_SHARP_C7xx
220 225
221config MACH_AKITA 226config MACH_AKITA
222 bool "Enable Sharp SL-1000 (Akita) Support" 227 bool "Enable Sharp SL-1000 (Akita) Support"
223 depends on PXA_SHARPSL_27x 228 depends on PXA_SHARPSL
229 select PXA27x
224 select PXA_SHARP_Cxx00 230 select PXA_SHARP_Cxx00
225 select MACH_SPITZ 231 select MACH_SPITZ
226 select I2C 232 select I2C
@@ -228,17 +234,20 @@ config MACH_AKITA
228 234
229config MACH_SPITZ 235config MACH_SPITZ
230 bool "Enable Sharp Zaurus SL-3000 (Spitz) Support" 236 bool "Enable Sharp Zaurus SL-3000 (Spitz) Support"
231 depends on PXA_SHARPSL_27x 237 depends on PXA_SHARPSL
238 select PXA27x
232 select PXA_SHARP_Cxx00 239 select PXA_SHARP_Cxx00
233 240
234config MACH_BORZOI 241config MACH_BORZOI
235 bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support" 242 bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support"
236 depends on PXA_SHARPSL_27x 243 depends on PXA_SHARPSL
244 select PXA27x
237 select PXA_SHARP_Cxx00 245 select PXA_SHARP_Cxx00
238 246
239config MACH_TOSA 247config MACH_TOSA
240 bool "Enable Sharp SL-6000x (Tosa) Support" 248 bool "Enable Sharp SL-6000x (Tosa) Support"
241 depends on PXA_SHARPSL_25x 249 depends on PXA_SHARPSL
250 select PXA25x
242 251
243config PXA25x 252config PXA25x
244 bool 253 bool
@@ -273,4 +282,10 @@ config PXA_SSP
273 tristate 282 tristate
274 help 283 help
275 Enable support for PXA2xx SSP ports 284 Enable support for PXA2xx SSP ports
285
286config PXA_PWM
287 tristate
288 default BACKLIGHT_PWM
289 help
290 Enable support for PXA2xx/PXA3xx PWM controllers
276endif 291endif
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 0e6d05bb81aa..02cbc3cfbe01 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
10 10
11# Generic drivers that other drivers may depend upon 11# Generic drivers that other drivers may depend upon
12obj-$(CONFIG_PXA_SSP) += ssp.o 12obj-$(CONFIG_PXA_SSP) += ssp.o
13obj-$(CONFIG_PXA_PWM) += pwm.o
13 14
14# SoC-specific code 15# SoC-specific code
15obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa25x.o 16obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa25x.o
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index 68afc396b4a1..b4d04955dcb0 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -12,7 +12,7 @@
12#include <linux/platform_device.h> 12#include <linux/platform_device.h>
13#include <linux/delay.h> 13#include <linux/delay.h>
14 14
15#include <asm/arch/pxa-regs.h> 15#include <asm/arch/pxa2xx-regs.h>
16#include <asm/arch/pxa2xx-gpio.h> 16#include <asm/arch/pxa2xx-gpio.h>
17#include <asm/hardware.h> 17#include <asm/hardware.h>
18 18
diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x270-pci.c
index ac7f05f9f3eb..319c9ff3ab9a 100644
--- a/arch/arm/mach-pxa/cm-x270-pci.c
+++ b/arch/arm/mach-pxa/cm-x270-pci.c
@@ -41,18 +41,20 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
41{ 41{
42 unsigned int sz = SZ_64M >> PAGE_SHIFT; 42 unsigned int sz = SZ_64M >> PAGE_SHIFT;
43 43
44 pr_info("Adjusting zones for CM-x270\n"); 44 if (machine_is_armcore()) {
45 45 pr_info("Adjusting zones for CM-x270\n");
46 /* 46
47 * Only adjust if > 64M on current system 47 /*
48 */ 48 * Only adjust if > 64M on current system
49 if (node || (zone_size[0] <= sz)) 49 */
50 return; 50 if (node || (zone_size[0] <= sz))
51 51 return;
52 zone_size[1] = zone_size[0] - sz; 52
53 zone_size[0] = sz; 53 zone_size[1] = zone_size[0] - sz;
54 zhole_size[1] = zhole_size[0]; 54 zone_size[0] = sz;
55 zhole_size[0] = 0; 55 zhole_size[1] = zhole_size[0];
56 zhole_size[0] = 0;
57 }
56} 58}
57 59
58static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) 60static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index b757dd756655..b37671b71886 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -36,6 +36,7 @@
36#include <asm/mach/irq.h> 36#include <asm/mach/irq.h>
37 37
38#include <asm/arch/pxa-regs.h> 38#include <asm/arch/pxa-regs.h>
39#include <asm/arch/pxa2xx-regs.h>
39#include <asm/arch/pxa2xx-gpio.h> 40#include <asm/arch/pxa2xx-gpio.h>
40#include <asm/arch/irda.h> 41#include <asm/arch/irda.h>
41#include <asm/arch/mmc.h> 42#include <asm/arch/mmc.h>
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
index 0a85f706e887..e91c0f26c412 100644
--- a/arch/arm/mach-pxa/corgi_pm.c
+++ b/arch/arm/mach-pxa/corgi_pm.c
@@ -26,6 +26,7 @@
26#include <asm/arch/sharpsl.h> 26#include <asm/arch/sharpsl.h>
27#include <asm/arch/corgi.h> 27#include <asm/arch/corgi.h>
28#include <asm/arch/pxa-regs.h> 28#include <asm/arch/pxa-regs.h>
29#include <asm/arch/pxa2xx-regs.h>
29#include <asm/arch/pxa2xx-gpio.h> 30#include <asm/arch/pxa2xx-gpio.h>
30#include "sharpsl.h" 31#include "sharpsl.h"
31 32
@@ -204,7 +205,9 @@ static struct sharpsl_charger_machinfo corgi_pm_machinfo = {
204 .read_devdata = corgipm_read_devdata, 205 .read_devdata = corgipm_read_devdata,
205 .charger_wakeup = corgi_charger_wakeup, 206 .charger_wakeup = corgi_charger_wakeup,
206 .should_wakeup = corgi_should_wakeup, 207 .should_wakeup = corgi_should_wakeup,
208#ifdef CONFIG_BACKLIGHT_CORGI
207 .backlight_limit = corgibl_limit_intensity, 209 .backlight_limit = corgibl_limit_intensity,
210#endif
208 .charge_on_volt = SHARPSL_CHARGE_ON_VOLT, 211 .charge_on_volt = SHARPSL_CHARGE_ON_VOLT,
209 .charge_on_temp = SHARPSL_CHARGE_ON_TEMP, 212 .charge_on_temp = SHARPSL_CHARGE_ON_TEMP,
210 .charge_acin_high = SHARPSL_CHARGE_ON_ACIN_HIGH, 213 .charge_acin_high = SHARPSL_CHARGE_ON_ACIN_HIGH,
@@ -226,6 +229,10 @@ static int __devinit corgipm_init(void)
226{ 229{
227 int ret; 230 int ret;
228 231
232 if (!machine_is_corgi() && !machine_is_shepherd()
233 && !machine_is_husky())
234 return -ENODEV;
235
229 corgipm_device = platform_device_alloc("sharpsl-pm", -1); 236 corgipm_device = platform_device_alloc("sharpsl-pm", -1);
230 if (!corgipm_device) 237 if (!corgipm_device)
231 return -ENOMEM; 238 return -ENOMEM;
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index d6c05b6eab35..4a1eebb42e49 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -10,11 +10,13 @@
10#include <asm/arch/mmc.h> 10#include <asm/arch/mmc.h>
11#include <asm/arch/irda.h> 11#include <asm/arch/irda.h>
12#include <asm/arch/i2c.h> 12#include <asm/arch/i2c.h>
13#include <asm/arch/mfp-pxa27x.h>
13#include <asm/arch/ohci.h> 14#include <asm/arch/ohci.h>
14#include <asm/arch/pxa27x_keypad.h> 15#include <asm/arch/pxa27x_keypad.h>
15#include <asm/arch/camera.h> 16#include <asm/arch/camera.h>
16 17
17#include "devices.h" 18#include "devices.h"
19#include "generic.h"
18 20
19void __init pxa_register_device(struct platform_device *dev, void *data) 21void __init pxa_register_device(struct platform_device *dev, void *data)
20{ 22{
@@ -233,8 +235,15 @@ struct platform_device pxa_device_i2c = {
233 .num_resources = ARRAY_SIZE(pxai2c_resources), 235 .num_resources = ARRAY_SIZE(pxai2c_resources),
234}; 236};
235 237
238static unsigned long pxa27x_i2c_mfp_cfg[] = {
239 GPIO117_I2C_SCL,
240 GPIO118_I2C_SDA,
241};
242
236void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info) 243void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
237{ 244{
245 if (cpu_is_pxa27x())
246 pxa2xx_mfp_config(ARRAY_AND_SIZE(pxa27x_i2c_mfp_cfg));
238 pxa_register_device(&pxa_device_i2c, info); 247 pxa_register_device(&pxa_device_i2c, info);
239} 248}
240 249
@@ -280,6 +289,36 @@ struct platform_device pxa_device_rtc = {
280 289
281#ifdef CONFIG_PXA25x 290#ifdef CONFIG_PXA25x
282 291
292static struct resource pxa25x_resource_pwm0[] = {
293 [0] = {
294 .start = 0x40b00000,
295 .end = 0x40b0000f,
296 .flags = IORESOURCE_MEM,
297 },
298};
299
300struct platform_device pxa25x_device_pwm0 = {
301 .name = "pxa25x-pwm",
302 .id = 0,
303 .resource = pxa25x_resource_pwm0,
304 .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
305};
306
307static struct resource pxa25x_resource_pwm1[] = {
308 [0] = {
309 .start = 0x40c00000,
310 .end = 0x40c0000f,
311 .flags = IORESOURCE_MEM,
312 },
313};
314
315struct platform_device pxa25x_device_pwm1 = {
316 .name = "pxa25x-pwm",
317 .id = 1,
318 .resource = pxa25x_resource_pwm1,
319 .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
320};
321
283static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32); 322static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
284 323
285static struct resource pxa25x_resource_ssp[] = { 324static struct resource pxa25x_resource_ssp[] = {
@@ -568,6 +607,36 @@ struct platform_device pxa27x_device_ssp3 = {
568 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3), 607 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
569}; 608};
570 609
610static struct resource pxa27x_resource_pwm0[] = {
611 [0] = {
612 .start = 0x40b00000,
613 .end = 0x40b0001f,
614 .flags = IORESOURCE_MEM,
615 },
616};
617
618struct platform_device pxa27x_device_pwm0 = {
619 .name = "pxa27x-pwm",
620 .id = 0,
621 .resource = pxa27x_resource_pwm0,
622 .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
623};
624
625static struct resource pxa27x_resource_pwm1[] = {
626 [0] = {
627 .start = 0x40c00000,
628 .end = 0x40c0001f,
629 .flags = IORESOURCE_MEM,
630 },
631};
632
633struct platform_device pxa27x_device_pwm1 = {
634 .name = "pxa27x-pwm",
635 .id = 1,
636 .resource = pxa27x_resource_pwm1,
637 .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
638};
639
571static struct resource pxa27x_resource_camera[] = { 640static struct resource pxa27x_resource_camera[] = {
572 [0] = { 641 [0] = {
573 .start = 0x50000000, 642 .start = 0x50000000,
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index fcab017f27ee..e620a3373d42 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -24,4 +24,9 @@ extern struct platform_device pxa27x_device_ssp2;
24extern struct platform_device pxa27x_device_ssp3; 24extern struct platform_device pxa27x_device_ssp3;
25extern struct platform_device pxa3xx_device_ssp4; 25extern struct platform_device pxa3xx_device_ssp4;
26 26
27extern struct platform_device pxa25x_device_pwm0;
28extern struct platform_device pxa25x_device_pwm1;
29extern struct platform_device pxa27x_device_pwm0;
30extern struct platform_device pxa27x_device_pwm1;
31
27void __init pxa_register_device(struct platform_device *dev, void *data); 32void __init pxa_register_device(struct platform_device *dev, void *data);
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index edc4f07a230d..1269ac991505 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -24,6 +24,7 @@
24 24
25#include <asm/arch/pxa-regs.h> 25#include <asm/arch/pxa-regs.h>
26#include <asm/arch/pxa2xx-gpio.h> 26#include <asm/arch/pxa2xx-gpio.h>
27#include <asm/arch/pxa27x-udc.h>
27#include <asm/arch/pxafb.h> 28#include <asm/arch/pxafb.h>
28#include <asm/arch/ohci.h> 29#include <asm/arch/ohci.h>
29#include <asm/arch/mmc.h> 30#include <asm/arch/mmc.h>
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 44617938f3f1..c2f102339f57 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -26,6 +26,7 @@
26#include <asm/mach/map.h> 26#include <asm/mach/map.h>
27 27
28#include <asm/arch/pxa-regs.h> 28#include <asm/arch/pxa-regs.h>
29#include <asm/arch/pxa2xx-regs.h> /* for __pxa_set_cken */
29 30
30#include "generic.h" 31#include "generic.h"
31 32
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index a20e4b1649d6..183b587672a6 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -23,6 +23,7 @@
23#include <linux/ioport.h> 23#include <linux/ioport.h>
24#include <linux/mtd/mtd.h> 24#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h> 25#include <linux/mtd/partitions.h>
26#include <linux/pwm_backlight.h>
26 27
27#include <asm/types.h> 28#include <asm/types.h>
28#include <asm/setup.h> 29#include <asm/setup.h>
@@ -134,9 +135,12 @@ static struct sys_device lpd270_irq_device = {
134 135
135static int __init lpd270_irq_device_init(void) 136static int __init lpd270_irq_device_init(void)
136{ 137{
137 int ret = sysdev_class_register(&lpd270_irq_sysclass); 138 int ret = -ENODEV;
138 if (ret == 0) 139 if (machine_is_logicpd_pxa270()) {
139 ret = sysdev_register(&lpd270_irq_device); 140 ret = sysdev_class_register(&lpd270_irq_sysclass);
141 if (ret == 0)
142 ret = sysdev_register(&lpd270_irq_device);
143 }
140 return ret; 144 return ret;
141} 145}
142 146
@@ -233,21 +237,20 @@ static struct platform_device lpd270_flash_device[2] = {
233 }, 237 },
234}; 238};
235 239
236static void lpd270_backlight_power(int on) 240static struct platform_pwm_backlight_data lpd270_backlight_data = {
237{ 241 .pwm_id = 0,
238 if (on) { 242 .max_brightness = 1,
239 pxa_gpio_mode(GPIO16_PWM0_MD); 243 .dft_brightness = 1,
240 pxa_set_cken(CKEN_PWM0, 1); 244 .pwm_period_ns = 78770,
241 PWM_CTRL0 = 0; 245};
242 PWM_PWDUTY0 = 0x3ff; 246
243 PWM_PERVAL0 = 0x3ff; 247static struct platform_device lpd270_backlight_device = {
244 } else { 248 .name = "pwm-backlight",
245 PWM_CTRL0 = 0; 249 .dev = {
246 PWM_PWDUTY0 = 0x0; 250 .parent = &pxa27x_device_pwm0.dev,
247 PWM_PERVAL0 = 0x3FF; 251 .platform_data = &lpd270_backlight_data,
248 pxa_set_cken(CKEN_PWM0, 0); 252 },
249 } 253};
250}
251 254
252/* 5.7" TFT QVGA (LoLo display number 1) */ 255/* 5.7" TFT QVGA (LoLo display number 1) */
253static struct pxafb_mode_info sharp_lq057q3dc02_mode = { 256static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
@@ -269,7 +272,6 @@ static struct pxafb_mach_info sharp_lq057q3dc02 = {
269 .num_modes = 1, 272 .num_modes = 1,
270 .lccr0 = 0x07800080, 273 .lccr0 = 0x07800080,
271 .lccr3 = 0x00400000, 274 .lccr3 = 0x00400000,
272 .pxafb_backlight_power = lpd270_backlight_power,
273}; 275};
274 276
275/* 12.1" TFT SVGA (LoLo display number 2) */ 277/* 12.1" TFT SVGA (LoLo display number 2) */
@@ -292,7 +294,6 @@ static struct pxafb_mach_info sharp_lq121s1dg31 = {
292 .num_modes = 1, 294 .num_modes = 1,
293 .lccr0 = 0x07800080, 295 .lccr0 = 0x07800080,
294 .lccr3 = 0x00400000, 296 .lccr3 = 0x00400000,
295 .pxafb_backlight_power = lpd270_backlight_power,
296}; 297};
297 298
298/* 3.6" TFT QVGA (LoLo display number 3) */ 299/* 3.6" TFT QVGA (LoLo display number 3) */
@@ -315,7 +316,6 @@ static struct pxafb_mach_info sharp_lq036q1da01 = {
315 .num_modes = 1, 316 .num_modes = 1,
316 .lccr0 = 0x07800080, 317 .lccr0 = 0x07800080,
317 .lccr3 = 0x00400000, 318 .lccr3 = 0x00400000,
318 .pxafb_backlight_power = lpd270_backlight_power,
319}; 319};
320 320
321/* 6.4" TFT VGA (LoLo display number 5) */ 321/* 6.4" TFT VGA (LoLo display number 5) */
@@ -338,7 +338,6 @@ static struct pxafb_mach_info sharp_lq64d343 = {
338 .num_modes = 1, 338 .num_modes = 1,
339 .lccr0 = 0x07800080, 339 .lccr0 = 0x07800080,
340 .lccr3 = 0x00400000, 340 .lccr3 = 0x00400000,
341 .pxafb_backlight_power = lpd270_backlight_power,
342}; 341};
343 342
344/* 10.4" TFT VGA (LoLo display number 7) */ 343/* 10.4" TFT VGA (LoLo display number 7) */
@@ -361,7 +360,6 @@ static struct pxafb_mach_info sharp_lq10d368 = {
361 .num_modes = 1, 360 .num_modes = 1,
362 .lccr0 = 0x07800080, 361 .lccr0 = 0x07800080,
363 .lccr3 = 0x00400000, 362 .lccr3 = 0x00400000,
364 .pxafb_backlight_power = lpd270_backlight_power,
365}; 363};
366 364
367/* 3.5" TFT QVGA (LoLo display number 8) */ 365/* 3.5" TFT QVGA (LoLo display number 8) */
@@ -384,7 +382,6 @@ static struct pxafb_mach_info sharp_lq035q7db02_20 = {
384 .num_modes = 1, 382 .num_modes = 1,
385 .lccr0 = 0x07800080, 383 .lccr0 = 0x07800080,
386 .lccr3 = 0x00400000, 384 .lccr3 = 0x00400000,
387 .pxafb_backlight_power = lpd270_backlight_power,
388}; 385};
389 386
390static struct pxafb_mach_info *lpd270_lcd_to_use; 387static struct pxafb_mach_info *lpd270_lcd_to_use;
@@ -414,6 +411,7 @@ __setup("lcd=", lpd270_set_lcd);
414 411
415static struct platform_device *platform_devices[] __initdata = { 412static struct platform_device *platform_devices[] __initdata = {
416 &smc91x_device, 413 &smc91x_device,
414 &lpd270_backlight_device,
417 &lpd270_audio_device, 415 &lpd270_audio_device,
418 &lpd270_flash_device[0], 416 &lpd270_flash_device[0],
419 &lpd270_flash_device[1], 417 &lpd270_flash_device[1],
@@ -454,6 +452,7 @@ static void __init lpd270_init(void)
454 * On LogicPD PXA270, we route AC97_SYSCLK via GPIO45. 452 * On LogicPD PXA270, we route AC97_SYSCLK via GPIO45.
455 */ 453 */
456 pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD); 454 pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
455 pxa_gpio_mode(GPIO16_PWM0_MD);
457 456
458 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 457 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
459 458
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index badba064dc04..01b2fa790217 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -25,6 +25,7 @@
25#include <linux/mtd/map.h> 25#include <linux/mtd/map.h>
26#include <linux/mtd/physmap.h> 26#include <linux/mtd/physmap.h>
27#include <linux/pda_power.h> 27#include <linux/pda_power.h>
28#include <linux/pwm_backlight.h>
28 29
29#include <asm/gpio.h> 30#include <asm/gpio.h>
30#include <asm/hardware.h> 31#include <asm/hardware.h>
@@ -33,12 +34,14 @@
33#include <asm/arch/magician.h> 34#include <asm/arch/magician.h>
34#include <asm/arch/mfp-pxa27x.h> 35#include <asm/arch/mfp-pxa27x.h>
35#include <asm/arch/pxa-regs.h> 36#include <asm/arch/pxa-regs.h>
37#include <asm/arch/pxa2xx-regs.h>
36#include <asm/arch/pxafb.h> 38#include <asm/arch/pxafb.h>
37#include <asm/arch/i2c.h> 39#include <asm/arch/i2c.h>
38#include <asm/arch/mmc.h> 40#include <asm/arch/mmc.h>
39#include <asm/arch/irda.h> 41#include <asm/arch/irda.h>
40#include <asm/arch/ohci.h> 42#include <asm/arch/ohci.h>
41 43
44#include "devices.h"
42#include "generic.h" 45#include "generic.h"
43 46
44static unsigned long magician_pin_config[] = { 47static unsigned long magician_pin_config[] = {
@@ -348,40 +351,58 @@ static struct pxafb_mach_info samsung_info = {
348 * Backlight 351 * Backlight
349 */ 352 */
350 353
351static void magician_set_bl_intensity(int intensity) 354static int magician_backlight_init(struct device *dev)
352{ 355{
353 if (intensity) { 356 int ret;
354 PWM_CTRL0 = 1; 357
355 PWM_PERVAL0 = 0xc8; 358 ret = gpio_request(EGPIO_MAGICIAN_BL_POWER, "BL_POWER");
356 if (intensity > 0xc7) { 359 if (ret)
357 PWM_PWDUTY0 = intensity - 0x48; 360 goto err;
358 gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 1); 361 ret = gpio_request(EGPIO_MAGICIAN_BL_POWER2, "BL_POWER2");
359 } else { 362 if (ret)
360 PWM_PWDUTY0 = intensity; 363 goto err2;
361 gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 0); 364 return 0;
362 } 365
363 gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 1); 366err2:
364 pxa_set_cken(CKEN_PWM0, 1); 367 gpio_free(EGPIO_MAGICIAN_BL_POWER);
368err:
369 return ret;
370}
371
372static int magician_backlight_notify(int brightness)
373{
374 gpio_set_value(EGPIO_MAGICIAN_BL_POWER, brightness);
375 if (brightness >= 200) {
376 gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 1);
377 return brightness - 72;
365 } else { 378 } else {
366 /* PWM_PWDUTY0 = intensity; */ 379 gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 0);
367 gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 0); 380 return brightness;
368 pxa_set_cken(CKEN_PWM0, 0);
369 } 381 }
370} 382}
371 383
372static struct generic_bl_info backlight_info = { 384static void magician_backlight_exit(struct device *dev)
373 .default_intensity = 0x64, 385{
374 .limit_mask = 0x0b, 386 gpio_free(EGPIO_MAGICIAN_BL_POWER);
375 .max_intensity = 0xc7+0x48, 387 gpio_free(EGPIO_MAGICIAN_BL_POWER2);
376 .set_bl_intensity = magician_set_bl_intensity, 388}
389
390static struct platform_pwm_backlight_data backlight_data = {
391 .pwm_id = 0,
392 .max_brightness = 272,
393 .dft_brightness = 100,
394 .pwm_period_ns = 30923,
395 .init = magician_backlight_init,
396 .notify = magician_backlight_notify,
397 .exit = magician_backlight_exit,
377}; 398};
378 399
379static struct platform_device backlight = { 400static struct platform_device backlight = {
380 .name = "generic-bl", 401 .name = "pwm-backlight",
381 .dev = { 402 .dev = {
382 .platform_data = &backlight_info, 403 .parent = &pxa27x_device_pwm0.dev,
404 .platform_data = &backlight_data,
383 }, 405 },
384 .id = -1,
385}; 406};
386 407
387/* 408/*
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 7399fb34da4e..266594426e8b 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -23,9 +23,9 @@
23#include <linux/ioport.h> 23#include <linux/ioport.h>
24#include <linux/mtd/mtd.h> 24#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h> 25#include <linux/mtd/partitions.h>
26#include <linux/backlight.h>
27#include <linux/input.h> 26#include <linux/input.h>
28#include <linux/gpio_keys.h> 27#include <linux/gpio_keys.h>
28#include <linux/pwm_backlight.h>
29 29
30#include <asm/types.h> 30#include <asm/types.h>
31#include <asm/setup.h> 31#include <asm/setup.h>
@@ -349,56 +349,27 @@ static struct platform_device mst_flash_device[2] = {
349 }, 349 },
350}; 350};
351 351
352#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 352#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
353static int mainstone_backlight_update_status(struct backlight_device *bl) 353static struct platform_pwm_backlight_data mainstone_backlight_data = {
354{ 354 .pwm_id = 0,
355 int brightness = bl->props.brightness; 355 .max_brightness = 1023,
356 356 .dft_brightness = 1023,
357 if (bl->props.power != FB_BLANK_UNBLANK || 357 .pwm_period_ns = 78770,
358 bl->props.fb_blank != FB_BLANK_UNBLANK) 358};
359 brightness = 0;
360
361 if (brightness != 0)
362 pxa_set_cken(CKEN_PWM0, 1);
363
364 PWM_CTRL0 = 0;
365 PWM_PWDUTY0 = brightness;
366 PWM_PERVAL0 = bl->props.max_brightness;
367
368 if (brightness == 0)
369 pxa_set_cken(CKEN_PWM0, 0);
370 return 0; /* pointless return value */
371}
372
373static int mainstone_backlight_get_brightness(struct backlight_device *bl)
374{
375 return PWM_PWDUTY0;
376}
377 359
378static /*const*/ struct backlight_ops mainstone_backlight_ops = { 360static struct platform_device mainstone_backlight_device = {
379 .update_status = mainstone_backlight_update_status, 361 .name = "pwm-backlight",
380 .get_brightness = mainstone_backlight_get_brightness, 362 .dev = {
363 .parent = &pxa27x_device_pwm0.dev,
364 .platform_data = &mainstone_backlight_data,
365 },
381}; 366};
382 367
383static void __init mainstone_backlight_register(void) 368static void __init mainstone_backlight_register(void)
384{ 369{
385 struct backlight_device *bl; 370 int ret = platform_device_register(&mainstone_backlight_device);
386 371 if (ret)
387 bl = backlight_device_register("mainstone-bl", &pxa_device_fb.dev, 372 printk(KERN_ERR "mainstone: failed to register backlight device: %d\n", ret);
388 NULL, &mainstone_backlight_ops);
389 if (IS_ERR(bl)) {
390 printk(KERN_ERR "mainstone: unable to register backlight: %ld\n",
391 PTR_ERR(bl));
392 return;
393 }
394
395 /*
396 * broken design - register-then-setup interfaces are
397 * utterly broken by definition.
398 */
399 bl->props.max_brightness = 1023;
400 bl->props.brightness = 1023;
401 backlight_update_status(bl);
402} 373}
403#else 374#else
404#define mainstone_backlight_register() do { } while (0) 375#define mainstone_backlight_register() do { } while (0)
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index 22097a1707cc..d1cdb4ecb0b8 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -20,6 +20,7 @@
20 20
21#include <asm/arch/hardware.h> 21#include <asm/arch/hardware.h>
22#include <asm/arch/pxa-regs.h> 22#include <asm/arch/pxa-regs.h>
23#include <asm/arch/pxa2xx-regs.h>
23#include <asm/arch/mfp-pxa2xx.h> 24#include <asm/arch/mfp-pxa2xx.h>
24 25
25#include "generic.h" 26#include "generic.h"
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 49d951db0f3d..2564e16e4e2f 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -24,6 +24,7 @@
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/ide.h> 25#include <linux/ide.h>
26#include <linux/i2c.h> 26#include <linux/i2c.h>
27#include <linux/pwm_backlight.h>
27 28
28#include <media/soc_camera.h> 29#include <media/soc_camera.h>
29 30
@@ -36,9 +37,99 @@
36#include <asm/arch/mmc.h> 37#include <asm/arch/mmc.h>
37#include <asm/arch/ohci.h> 38#include <asm/arch/ohci.h>
38#include <asm/arch/pcm990_baseboard.h> 39#include <asm/arch/pcm990_baseboard.h>
40#include <asm/arch/pxafb.h>
41
42#include "devices.h"
43
44/*
45 * pcm990_lcd_power - control power supply to the LCD
46 * @on: 0 = switch off, 1 = switch on
47 *
48 * Called by the pxafb driver
49 */
50#ifndef CONFIG_PCM990_DISPLAY_NONE
51static void pcm990_lcd_power(int on, struct fb_var_screeninfo *var)
52{
53 if (on) {
54 /* enable LCD-Latches
55 * power on LCD
56 */
57 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) =
58 PCM990_CTRL_LCDPWR + PCM990_CTRL_LCDON;
59 } else {
60 /* disable LCD-Latches
61 * power off LCD
62 */
63 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) = 0x00;
64 }
65}
66#endif
67
68#if defined(CONFIG_PCM990_DISPLAY_SHARP)
69static struct pxafb_mode_info fb_info_sharp_lq084v1dg21 = {
70 .pixclock = 28000,
71 .xres = 640,
72 .yres = 480,
73 .bpp = 16,
74 .hsync_len = 20,
75 .left_margin = 103,
76 .right_margin = 47,
77 .vsync_len = 6,
78 .upper_margin = 28,
79 .lower_margin = 5,
80 .sync = 0,
81 .cmap_greyscale = 0,
82};
83
84static struct pxafb_mach_info pcm990_fbinfo __initdata = {
85 .modes = &fb_info_sharp_lq084v1dg21,
86 .num_modes = 1,
87 .lccr0 = LCCR0_PAS,
88 .lccr3 = LCCR3_PCP,
89 .pxafb_lcd_power = pcm990_lcd_power,
90};
91#elif defined(CONFIG_PCM990_DISPLAY_NEC)
92struct pxafb_mode_info fb_info_nec_nl6448bc20_18d = {
93 .pixclock = 39720,
94 .xres = 640,
95 .yres = 480,
96 .bpp = 16,
97 .hsync_len = 32,
98 .left_margin = 16,
99 .right_margin = 48,
100 .vsync_len = 2,
101 .upper_margin = 12,
102 .lower_margin = 17,
103 .sync = 0,
104 .cmap_greyscale = 0,
105};
106
107static struct pxafb_mach_info pcm990_fbinfo __initdata = {
108 .modes = &fb_info_nec_nl6448bc20_18d,
109 .num_modes = 1,
110 .lccr0 = LCCR0_Act,
111 .lccr3 = LCCR3_PixFlEdg,
112 .pxafb_lcd_power = pcm990_lcd_power,
113};
114#endif
115
116static struct platform_pwm_backlight_data pcm990_backlight_data = {
117 .pwm_id = 0,
118 .max_brightness = 1023,
119 .dft_brightness = 1023,
120 .pwm_period_ns = 78770,
121};
122
123static struct platform_device pcm990_backlight_device = {
124 .name = "pwm-backlight",
125 .dev = {
126 .parent = &pxa27x_device_pwm0.dev,
127 .platform_data = &pcm990_backlight_data,
128 },
129};
39 130
40/* 131/*
41 * The PCM-990 development baseboard uses PCM-027's hardeware in the 132 * The PCM-990 development baseboard uses PCM-027's hardware in the
42 * following way: 133 * following way:
43 * 134 *
44 * - LCD support is in use 135 * - LCD support is in use
@@ -393,6 +484,12 @@ void __init pcm990_baseboard_init(void)
393 /* register CPLD's IRQ controller */ 484 /* register CPLD's IRQ controller */
394 pcm990_init_irq(); 485 pcm990_init_irq();
395 486
487#ifndef CONFIG_PCM990_DISPLAY_NONE
488 set_pxa_fb_info(&pcm990_fbinfo);
489#endif
490 pxa_gpio_mode(GPIO16_PWM0_MD);
491 platform_device_register(&pcm990_backlight_device);
492
396 platform_device_register(&pxa27x_device_ac97); 493 platform_device_register(&pxa27x_device_ac97);
397 494
398 /* MMC */ 495 /* MMC */
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 0b30f25cff3c..f81c10cafd48 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -32,6 +32,7 @@
32#include <asm/mach/irq.h> 32#include <asm/mach/irq.h>
33 33
34#include <asm/arch/pxa-regs.h> 34#include <asm/arch/pxa-regs.h>
35#include <asm/arch/pxa2xx-regs.h>
35#include <asm/arch/pxa2xx-gpio.h> 36#include <asm/arch/pxa2xx-gpio.h>
36#include <asm/arch/mmc.h> 37#include <asm/arch/mmc.h>
37#include <asm/arch/udc.h> 38#include <asm/arch/udc.h>
diff --git a/arch/arm/mach-pxa/pwm.c b/arch/arm/mach-pxa/pwm.c
new file mode 100644
index 000000000000..ce28cd9fed16
--- /dev/null
+++ b/arch/arm/mach-pxa/pwm.c
@@ -0,0 +1,319 @@
1/*
2 * linux/arch/arm/mach-pxa/pwm.c
3 *
4 * simple driver for PWM (Pulse Width Modulator) controller
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * 2008-02-13 initial version
11 * eric miao <eric.miao@marvell.com>
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20#include <linux/pwm.h>
21
22#include <asm/div64.h>
23#include <asm/arch/pxa-regs.h>
24
25/* PWM registers and bits definitions */
26#define PWMCR (0x00)
27#define PWMDCR (0x04)
28#define PWMPCR (0x08)
29
30#define PWMCR_SD (1 << 6)
31#define PWMDCR_FD (1 << 10)
32
33struct pwm_device {
34 struct list_head node;
35 struct platform_device *pdev;
36
37 const char *label;
38 struct clk *clk;
39 int clk_enabled;
40 void __iomem *mmio_base;
41
42 unsigned int use_count;
43 unsigned int pwm_id;
44};
45
46/*
47 * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE
48 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
49 */
50int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
51{
52 unsigned long long c;
53 unsigned long period_cycles, prescale, pv, dc;
54
55 if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
56 return -EINVAL;
57
58 c = clk_get_rate(pwm->clk);
59 c = c * period_ns;
60 do_div(c, 1000000000);
61 period_cycles = c;
62
63 if (period_cycles < 0)
64 period_cycles = 1;
65 prescale = (period_cycles - 1) / 1024;
66 pv = period_cycles / (prescale + 1) - 1;
67
68 if (prescale > 63)
69 return -EINVAL;
70
71 if (duty_ns == period_ns)
72 dc = PWMDCR_FD;
73 else
74 dc = (pv + 1) * duty_ns / period_ns;
75
76 /* NOTE: the clock to PWM has to be enabled first
77 * before writing to the registers
78 */
79 clk_enable(pwm->clk);
80 __raw_writel(prescale, pwm->mmio_base + PWMCR);
81 __raw_writel(dc, pwm->mmio_base + PWMDCR);
82 __raw_writel(pv, pwm->mmio_base + PWMPCR);
83 clk_disable(pwm->clk);
84
85 return 0;
86}
87EXPORT_SYMBOL(pwm_config);
88
89int pwm_enable(struct pwm_device *pwm)
90{
91 int rc = 0;
92
93 if (!pwm->clk_enabled) {
94 rc = clk_enable(pwm->clk);
95 if (!rc)
96 pwm->clk_enabled = 1;
97 }
98 return rc;
99}
100EXPORT_SYMBOL(pwm_enable);
101
102void pwm_disable(struct pwm_device *pwm)
103{
104 if (pwm->clk_enabled) {
105 clk_disable(pwm->clk);
106 pwm->clk_enabled = 0;
107 }
108}
109EXPORT_SYMBOL(pwm_disable);
110
111static DEFINE_MUTEX(pwm_lock);
112static LIST_HEAD(pwm_list);
113
114struct pwm_device *pwm_request(int pwm_id, const char *label)
115{
116 struct pwm_device *pwm;
117 int found = 0;
118
119 mutex_lock(&pwm_lock);
120
121 list_for_each_entry(pwm, &pwm_list, node) {
122 if (pwm->pwm_id == pwm_id) {
123 found = 1;
124 break;
125 }
126 }
127
128 if (found) {
129 if (pwm->use_count == 0) {
130 pwm->use_count++;
131 pwm->label = label;
132 } else
133 pwm = ERR_PTR(-EBUSY);
134 } else
135 pwm = ERR_PTR(-ENOENT);
136
137 mutex_unlock(&pwm_lock);
138 return pwm;
139}
140EXPORT_SYMBOL(pwm_request);
141
142void pwm_free(struct pwm_device *pwm)
143{
144 mutex_lock(&pwm_lock);
145
146 if (pwm->use_count) {
147 pwm->use_count--;
148 pwm->label = NULL;
149 } else
150 pr_warning("PWM device already freed\n");
151
152 mutex_unlock(&pwm_lock);
153}
154EXPORT_SYMBOL(pwm_free);
155
156static inline void __add_pwm(struct pwm_device *pwm)
157{
158 mutex_lock(&pwm_lock);
159 list_add_tail(&pwm->node, &pwm_list);
160 mutex_unlock(&pwm_lock);
161}
162
163static struct pwm_device *pwm_probe(struct platform_device *pdev,
164 unsigned int pwm_id, struct pwm_device *parent_pwm)
165{
166 struct pwm_device *pwm;
167 struct resource *r;
168 int ret = 0;
169
170 pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
171 if (pwm == NULL) {
172 dev_err(&pdev->dev, "failed to allocate memory\n");
173 return ERR_PTR(-ENOMEM);
174 }
175
176 pwm->clk = clk_get(&pdev->dev, "PWMCLK");
177 if (IS_ERR(pwm->clk)) {
178 ret = PTR_ERR(pwm->clk);
179 goto err_free;
180 }
181 pwm->clk_enabled = 0;
182
183 pwm->use_count = 0;
184 pwm->pwm_id = pwm_id;
185 pwm->pdev = pdev;
186
187 if (parent_pwm != NULL) {
188 /* registers for the second PWM has offset of 0x10 */
189 pwm->mmio_base = parent_pwm->mmio_base + 0x10;
190 __add_pwm(pwm);
191 return pwm;
192 }
193
194 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
195 if (r == NULL) {
196 dev_err(&pdev->dev, "no memory resource defined\n");
197 ret = -ENODEV;
198 goto err_free_clk;
199 }
200
201 r = request_mem_region(r->start, r->end - r->start + 1, pdev->name);
202 if (r == NULL) {
203 dev_err(&pdev->dev, "failed to request memory resource\n");
204 ret = -EBUSY;
205 goto err_free_clk;
206 }
207
208 pwm->mmio_base = ioremap(r->start, r->end - r->start + 1);
209 if (pwm->mmio_base == NULL) {
210 dev_err(&pdev->dev, "failed to ioremap() registers\n");
211 ret = -ENODEV;
212 goto err_free_mem;
213 }
214
215 __add_pwm(pwm);
216 platform_set_drvdata(pdev, pwm);
217 return pwm;
218
219err_free_mem:
220 release_mem_region(r->start, r->end - r->start + 1);
221err_free_clk:
222 clk_put(pwm->clk);
223err_free:
224 kfree(pwm);
225 return ERR_PTR(ret);
226}
227
228static int __devinit pxa25x_pwm_probe(struct platform_device *pdev)
229{
230 struct pwm_device *pwm = pwm_probe(pdev, pdev->id, NULL);
231
232 if (IS_ERR(pwm))
233 return PTR_ERR(pwm);
234
235 return 0;
236}
237
238static int __devinit pxa27x_pwm_probe(struct platform_device *pdev)
239{
240 struct pwm_device *pwm;
241
242 pwm = pwm_probe(pdev, pdev->id, NULL);
243 if (IS_ERR(pwm))
244 return PTR_ERR(pwm);
245
246 pwm = pwm_probe(pdev, pdev->id + 2, pwm);
247 if (IS_ERR(pwm))
248 return PTR_ERR(pwm);
249
250 return 0;
251}
252
253static int __devexit pwm_remove(struct platform_device *pdev)
254{
255 struct pwm_device *pwm;
256 struct resource *r;
257
258 pwm = platform_get_drvdata(pdev);
259 if (pwm == NULL)
260 return -ENODEV;
261
262 mutex_lock(&pwm_lock);
263 list_del(&pwm->node);
264 mutex_unlock(&pwm_lock);
265
266 iounmap(pwm->mmio_base);
267
268 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
269 release_mem_region(r->start, r->end - r->start + 1);
270
271 clk_put(pwm->clk);
272 kfree(pwm);
273 return 0;
274}
275
276static struct platform_driver pxa25x_pwm_driver = {
277 .driver = {
278 .name = "pxa25x-pwm",
279 },
280 .probe = pxa25x_pwm_probe,
281 .remove = __devexit_p(pwm_remove),
282};
283
284static struct platform_driver pxa27x_pwm_driver = {
285 .driver = {
286 .name = "pxa27x-pwm",
287 },
288 .probe = pxa27x_pwm_probe,
289 .remove = __devexit_p(pwm_remove),
290};
291
292static int __init pwm_init(void)
293{
294 int ret = 0;
295
296 ret = platform_driver_register(&pxa25x_pwm_driver);
297 if (ret) {
298 printk(KERN_ERR "failed to register pxa25x_pwm_driver\n");
299 return ret;
300 }
301
302 ret = platform_driver_register(&pxa27x_pwm_driver);
303 if (ret) {
304 printk(KERN_ERR "failed to register pxa27x_pwm_driver\n");
305 return ret;
306 }
307
308 return ret;
309}
310arch_initcall(pwm_init);
311
312static void __exit pwm_exit(void)
313{
314 platform_driver_unregister(&pxa25x_pwm_driver);
315 platform_driver_unregister(&pxa27x_pwm_driver);
316}
317module_exit(pwm_exit);
318
319MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 09ee131d24a1..a1a7dd23ce5a 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -26,6 +26,7 @@
26#include <asm/hardware.h> 26#include <asm/hardware.h>
27#include <asm/arch/irqs.h> 27#include <asm/arch/irqs.h>
28#include <asm/arch/pxa-regs.h> 28#include <asm/arch/pxa-regs.h>
29#include <asm/arch/pxa2xx-regs.h>
29#include <asm/arch/mfp-pxa25x.h> 30#include <asm/arch/mfp-pxa25x.h>
30#include <asm/arch/pm.h> 31#include <asm/arch/pm.h>
31#include <asm/arch/dma.h> 32#include <asm/arch/dma.h>
@@ -133,12 +134,12 @@ static struct clk pxa25x_clks[] = {
133 INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev), 134 INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev),
134 INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev), 135 INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
135 INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev), 136 INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
137 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, &pxa25x_device_pwm0.dev),
138 INIT_CKEN("PWMCLK", PWM1, 3686400, 0, &pxa25x_device_pwm1.dev),
136 139
137 INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), 140 INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL),
138 141
139 /* 142 /*
140 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
141 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
142 INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), 143 INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL),
143 */ 144 */
144 INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), 145 INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
@@ -275,6 +276,8 @@ static struct platform_device *pxa25x_devices[] __initdata = {
275 &pxa25x_device_ssp, 276 &pxa25x_device_ssp,
276 &pxa25x_device_nssp, 277 &pxa25x_device_nssp,
277 &pxa25x_device_assp, 278 &pxa25x_device_assp,
279 &pxa25x_device_pwm0,
280 &pxa25x_device_pwm1,
278}; 281};
279 282
280static struct sys_device pxa25x_sysdev[] = { 283static struct sys_device pxa25x_sysdev[] = {
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 7e945836e129..4d7afae352a1 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -157,12 +157,13 @@ static struct clk pxa27x_clks[] = {
157 INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), 157 INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
158 INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), 158 INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
159 INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), 159 INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
160 INIT_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
161 INIT_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),
160 162
161 INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), 163 INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL),
162 INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL), 164 INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL),
163 165
164 /* 166 /*
165 INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL),
166 INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL), 167 INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL),
167 INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL), 168 INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
168 INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL), 169 INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
@@ -349,11 +350,14 @@ struct platform_device pxa27x_device_i2c_power = {
349 350
350void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info) 351void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info)
351{ 352{
353 local_irq_disable();
354 PCFR |= PCFR_PI2CEN;
355 local_irq_enable();
352 pxa27x_device_i2c_power.dev.platform_data = info; 356 pxa27x_device_i2c_power.dev.platform_data = info;
353} 357}
354 358
355static struct platform_device *devices[] __initdata = { 359static struct platform_device *devices[] __initdata = {
356 &pxa_device_udc, 360/* &pxa_device_udc, The UDC driver is PXA25x only */
357 &pxa_device_ffuart, 361 &pxa_device_ffuart,
358 &pxa_device_btuart, 362 &pxa_device_btuart,
359 &pxa_device_stuart, 363 &pxa_device_stuart,
@@ -363,6 +367,8 @@ static struct platform_device *devices[] __initdata = {
363 &pxa27x_device_ssp1, 367 &pxa27x_device_ssp1,
364 &pxa27x_device_ssp2, 368 &pxa27x_device_ssp2,
365 &pxa27x_device_ssp3, 369 &pxa27x_device_ssp3,
370 &pxa27x_device_pwm0,
371 &pxa27x_device_pwm1,
366}; 372};
367 373
368static struct sys_device pxa27x_sysdev[] = { 374static struct sys_device pxa27x_sysdev[] = {
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 644550bfa330..d26a9b02a559 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -239,6 +239,8 @@ static struct clk pxa3xx_clks[] = {
239 PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), 239 PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
240 PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), 240 PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
241 PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev), 241 PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
242 PXA3xx_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
243 PXA3xx_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),
242 244
243 PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev), 245 PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
244 PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev), 246 PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
@@ -520,7 +522,7 @@ void __init pxa3xx_init_irq(void)
520 */ 522 */
521 523
522static struct platform_device *devices[] __initdata = { 524static struct platform_device *devices[] __initdata = {
523 &pxa_device_udc, 525/* &pxa_device_udc, The UDC driver is PXA25x only */
524 &pxa_device_ffuart, 526 &pxa_device_ffuart,
525 &pxa_device_btuart, 527 &pxa_device_btuart,
526 &pxa_device_stuart, 528 &pxa_device_stuart,
@@ -530,6 +532,8 @@ static struct platform_device *devices[] __initdata = {
530 &pxa27x_device_ssp2, 532 &pxa27x_device_ssp2,
531 &pxa27x_device_ssp3, 533 &pxa27x_device_ssp3,
532 &pxa3xx_device_ssp4, 534 &pxa3xx_device_ssp4,
535 &pxa27x_device_pwm0,
536 &pxa27x_device_pwm1,
533}; 537};
534 538
535static struct sys_device pxa3xx_sysdev[] = { 539static struct sys_device pxa3xx_sysdev[] = {
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 23f050feb208..360354084ae4 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -26,6 +26,7 @@
26#include <asm/arch/sharpsl.h> 26#include <asm/arch/sharpsl.h>
27#include <asm/arch/spitz.h> 27#include <asm/arch/spitz.h>
28#include <asm/arch/pxa-regs.h> 28#include <asm/arch/pxa-regs.h>
29#include <asm/arch/pxa2xx-regs.h>
29#include <asm/arch/pxa2xx-gpio.h> 30#include <asm/arch/pxa2xx-gpio.h>
30#include "sharpsl.h" 31#include "sharpsl.h"
31 32
@@ -207,7 +208,9 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = {
207 .read_devdata = spitzpm_read_devdata, 208 .read_devdata = spitzpm_read_devdata,
208 .charger_wakeup = spitz_charger_wakeup, 209 .charger_wakeup = spitz_charger_wakeup,
209 .should_wakeup = spitz_should_wakeup, 210 .should_wakeup = spitz_should_wakeup,
211#ifdef CONFIG_BACKLIGHT_CORGI
210 .backlight_limit = corgibl_limit_intensity, 212 .backlight_limit = corgibl_limit_intensity,
213#endif
211 .charge_on_volt = SHARPSL_CHARGE_ON_VOLT, 214 .charge_on_volt = SHARPSL_CHARGE_ON_VOLT,
212 .charge_on_temp = SHARPSL_CHARGE_ON_TEMP, 215 .charge_on_temp = SHARPSL_CHARGE_ON_TEMP,
213 .charge_acin_high = SHARPSL_CHARGE_ON_ACIN_HIGH, 216 .charge_acin_high = SHARPSL_CHARGE_ON_ACIN_HIGH,
@@ -229,6 +232,10 @@ static int __devinit spitzpm_init(void)
229{ 232{
230 int ret; 233 int ret;
231 234
235 if (!machine_is_spitz() && !machine_is_akita()
236 && !machine_is_borzoi())
237 return -ENODEV;
238
232 spitzpm_device = platform_device_alloc("sharpsl-pm", -1); 239 spitzpm_device = platform_device_alloc("sharpsl-pm", -1);
233 if (!spitzpm_device) 240 if (!spitzpm_device)
234 return -ENOMEM; 241 return -ENOMEM;
diff --git a/arch/arm/mach-pxa/standby.S b/arch/arm/mach-pxa/standby.S
index 167412e6bec8..40bb70eff3fe 100644
--- a/arch/arm/mach-pxa/standby.S
+++ b/arch/arm/mach-pxa/standby.S
@@ -14,6 +14,7 @@
14#include <asm/hardware.h> 14#include <asm/hardware.h>
15 15
16#include <asm/arch/pxa-regs.h> 16#include <asm/arch/pxa-regs.h>
17#include <asm/arch/pxa2xx-regs.h>
17 18
18 .text 19 .text
19 20
@@ -35,20 +36,20 @@ ENTRY(pxa_cpu_standby)
35 36
36#ifdef CONFIG_PXA3xx 37#ifdef CONFIG_PXA3xx
37 38
38#define MDCNFG 0x0000 39#define PXA3_MDCNFG 0x0000
39#define MDCNFG_DMCEN (1 << 30) 40#define PXA3_MDCNFG_DMCEN (1 << 30)
40#define DDR_HCAL 0x0060 41#define PXA3_DDR_HCAL 0x0060
41#define DDR_HCAL_HCRNG 0x1f 42#define PXA3_DDR_HCAL_HCRNG 0x1f
42#define DDR_HCAL_HCPROG (1 << 28) 43#define PXA3_DDR_HCAL_HCPROG (1 << 28)
43#define DDR_HCAL_HCEN (1 << 31) 44#define PXA3_DDR_HCAL_HCEN (1 << 31)
44#define DMCIER 0x0070 45#define PXA3_DMCIER 0x0070
45#define DMCIER_EDLP (1 << 29) 46#define PXA3_DMCIER_EDLP (1 << 29)
46#define DMCISR 0x0078 47#define PXA3_DMCISR 0x0078
47#define RCOMP 0x0100 48#define PXA3_RCOMP 0x0100
48#define RCOMP_SWEVAL (1 << 31) 49#define PXA3_RCOMP_SWEVAL (1 << 31)
49 50
50ENTRY(pm_enter_standby_start) 51ENTRY(pm_enter_standby_start)
51 mov r1, #0xf6000000 @ DMEMC_REG_BASE (MDCNFG) 52 mov r1, #0xf6000000 @ DMEMC_REG_BASE (PXA3_MDCNFG)
52 add r1, r1, #0x00100000 53 add r1, r1, #0x00100000
53 54
54 /* 55 /*
@@ -59,54 +60,54 @@ ENTRY(pm_enter_standby_start)
59 * This also means that only the dynamic memory controller 60 * This also means that only the dynamic memory controller
60 * can be reliably accessed in the code following standby. 61 * can be reliably accessed in the code following standby.
61 */ 62 */
62 ldr r2, [r1] @ Dummy read MDCNFG 63 ldr r2, [r1] @ Dummy read PXA3_MDCNFG
63 64
64 mcr p14, 0, r0, c7, c0, 0 65 mcr p14, 0, r0, c7, c0, 0
65 .rept 8 66 .rept 8
66 nop 67 nop
67 .endr 68 .endr
68 69
69 ldr r0, [r1, #DDR_HCAL] @ Clear (and wait for) HCEN 70 ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
70 bic r0, r0, #DDR_HCAL_HCEN 71 bic r0, r0, #PXA3_DDR_HCAL_HCEN
71 str r0, [r1, #DDR_HCAL] 72 str r0, [r1, #PXA3_DDR_HCAL]
721: ldr r0, [r1, #DDR_HCAL] 731: ldr r0, [r1, #PXA3_DDR_HCAL]
73 tst r0, #DDR_HCAL_HCEN 74 tst r0, #PXA3_DDR_HCAL_HCEN
74 bne 1b 75 bne 1b
75 76
76 ldr r0, [r1, #RCOMP] @ Initiate RCOMP 77 ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
77 orr r0, r0, #RCOMP_SWEVAL 78 orr r0, r0, #PXA3_RCOMP_SWEVAL
78 str r0, [r1, #RCOMP] 79 str r0, [r1, #PXA3_RCOMP]
79 80
80 mov r0, #~0 @ Clear interrupts 81 mov r0, #~0 @ Clear interrupts
81 str r0, [r1, #DMCISR] 82 str r0, [r1, #PXA3_DMCISR]
82 83
83 ldr r0, [r1, #DMCIER] @ set DMIER[EDLP] 84 ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
84 orr r0, r0, #DMCIER_EDLP 85 orr r0, r0, #PXA3_DMCIER_EDLP
85 str r0, [r1, #DMCIER] 86 str r0, [r1, #PXA3_DMCIER]
86 87
87 ldr r0, [r1, #DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN 88 ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
88 bic r0, r0, #DDR_HCAL_HCRNG 89 bic r0, r0, #PXA3_DDR_HCAL_HCRNG
89 orr r0, r0, #DDR_HCAL_HCEN | DDR_HCAL_HCPROG 90 orr r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG
90 str r0, [r1, #DDR_HCAL] 91 str r0, [r1, #PXA3_DDR_HCAL]
91 92
921: ldr r0, [r1, #DMCISR] 931: ldr r0, [r1, #PXA3_DMCISR]
93 tst r0, #DMCIER_EDLP 94 tst r0, #PXA3_DMCIER_EDLP
94 beq 1b 95 beq 1b
95 96
96 ldr r0, [r1, #MDCNFG] @ set MDCNFG[DMCEN] 97 ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
97 orr r0, r0, #MDCNFG_DMCEN 98 orr r0, r0, #PXA3_MDCNFG_DMCEN
98 str r0, [r1, #MDCNFG] 99 str r0, [r1, #PXA3_MDCNFG]
991: ldr r0, [r1, #MDCNFG] 1001: ldr r0, [r1, #PXA3_MDCNFG]
100 tst r0, #MDCNFG_DMCEN 101 tst r0, #PXA3_MDCNFG_DMCEN
101 beq 1b 102 beq 1b
102 103
103 ldr r0, [r1, #DDR_HCAL] @ set DDR_HCAL[HCRNG] 104 ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG]
104 orr r0, r0, #2 @ HCRNG 105 orr r0, r0, #2 @ HCRNG
105 str r0, [r1, #DDR_HCAL] 106 str r0, [r1, #PXA3_DDR_HCAL]
106 107
107 ldr r0, [r1, #DMCIER] @ Clear the interrupt 108 ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt
108 bic r0, r0, #0x20000000 109 bic r0, r0, #0x20000000
109 str r0, [r1, #DMCIER] 110 str r0, [r1, #PXA3_DMCIER]
110 111
111 mov pc, lr 112 mov pc, lr
112ENTRY(pm_enter_standby_end) 113ENTRY(pm_enter_standby_end)
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 931885d86b91..bc7c465ef32b 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -41,6 +41,7 @@
41#include <asm/mach/flash.h> 41#include <asm/mach/flash.h>
42 42
43#include <asm/arch/pxa-regs.h> 43#include <asm/arch/pxa-regs.h>
44#include <asm/arch/pxa2xx-regs.h>
44#include <asm/arch/pxa2xx-gpio.h> 45#include <asm/arch/pxa2xx-gpio.h>
45#include <asm/arch/trizeps4.h> 46#include <asm/arch/trizeps4.h>
46#include <asm/arch/audio.h> 47#include <asm/arch/audio.h>
@@ -487,6 +488,7 @@ static void __init trizeps4_map_io(void)
487 ConXS_BCR = trizeps_conxs_bcr; 488 ConXS_BCR = trizeps_conxs_bcr;
488#endif 489#endif
489 490
491#warning FIXME - accessing PM registers directly is deprecated
490 PWER = 0x00000002; 492 PWER = 0x00000002;
491 PFER = 0x00000000; 493 PFER = 0x00000000;
492 PRER = 0x00000002; 494 PRER = 0x00000002;
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 4a0028087ea6..b13bb9385138 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -18,6 +18,7 @@
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/pwm_backlight.h>
21 22
22#include <asm/mach-types.h> 23#include <asm/mach-types.h>
23#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
@@ -28,12 +29,12 @@
28#include <asm/arch/mmc.h> 29#include <asm/arch/mmc.h>
29#include <asm/arch/pxa27x_keypad.h> 30#include <asm/arch/pxa27x_keypad.h>
30 31
32#include "devices.h"
31#include "generic.h" 33#include "generic.h"
32 34
33#define MAX_SLOTS 3 35#define MAX_SLOTS 3
34struct platform_mmc_slot zylonite_mmc_slot[MAX_SLOTS]; 36struct platform_mmc_slot zylonite_mmc_slot[MAX_SLOTS];
35 37
36int gpio_backlight;
37int gpio_eth_irq; 38int gpio_eth_irq;
38 39
39int wm9713_irq; 40int wm9713_irq;
@@ -62,10 +63,20 @@ static struct platform_device smc91x_device = {
62}; 63};
63 64
64#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) 65#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
65static void zylonite_backlight_power(int on) 66static struct platform_pwm_backlight_data zylonite_backlight_data = {
66{ 67 .pwm_id = 3,
67 gpio_set_value(gpio_backlight, on); 68 .max_brightness = 100,
68} 69 .dft_brightness = 100,
70 .pwm_period_ns = 10000,
71};
72
73static struct platform_device zylonite_backlight_device = {
74 .name = "pwm-backlight",
75 .dev = {
76 .parent = &pxa27x_device_pwm1.dev,
77 .platform_data = &zylonite_backlight_data,
78 },
79};
69 80
70static struct pxafb_mode_info toshiba_ltm035a776c_mode = { 81static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
71 .pixclock = 110000, 82 .pixclock = 110000,
@@ -98,7 +109,6 @@ static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
98static struct pxafb_mach_info zylonite_toshiba_lcd_info = { 109static struct pxafb_mach_info zylonite_toshiba_lcd_info = {
99 .num_modes = 1, 110 .num_modes = 1,
100 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, 111 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
101 .pxafb_backlight_power = zylonite_backlight_power,
102}; 112};
103 113
104static struct pxafb_mode_info sharp_ls037_modes[] = { 114static struct pxafb_mode_info sharp_ls037_modes[] = {
@@ -134,13 +144,11 @@ static struct pxafb_mach_info zylonite_sharp_lcd_info = {
134 .modes = sharp_ls037_modes, 144 .modes = sharp_ls037_modes,
135 .num_modes = 2, 145 .num_modes = 2,
136 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, 146 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
137 .pxafb_backlight_power = zylonite_backlight_power,
138}; 147};
139 148
140static void __init zylonite_init_lcd(void) 149static void __init zylonite_init_lcd(void)
141{ 150{
142 /* backlight GPIO: output, default on */ 151 platform_device_register(&zylonite_backlight_device);
143 gpio_direction_output(gpio_backlight, 1);
144 152
145 if (lcd_id & 0x20) { 153 if (lcd_id & 0x20) {
146 set_pxa_fb_info(&zylonite_sharp_lcd_info); 154 set_pxa_fb_info(&zylonite_sharp_lcd_info);
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
index 324fb9daae28..6f7ae972b8db 100644
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -50,6 +50,7 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
50 GPIO75_LCD_BIAS, 50 GPIO75_LCD_BIAS,
51 GPIO76_LCD_VSYNC, 51 GPIO76_LCD_VSYNC,
52 GPIO127_LCD_CS_N, 52 GPIO127_LCD_CS_N,
53 GPIO20_PWM3_OUT, /* backlight */
53 54
54 /* BTUART */ 55 /* BTUART */
55 GPIO111_UART2_RTS, 56 GPIO111_UART2_RTS,
@@ -200,9 +201,6 @@ void __init zylonite_pxa300_init(void)
200 /* detect LCD panel */ 201 /* detect LCD panel */
201 zylonite_detect_lcd_panel(); 202 zylonite_detect_lcd_panel();
202 203
203 /* GPIO pin assignment */
204 gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO20);
205
206 /* MMC card detect & write protect for controller 0 */ 204 /* MMC card detect & write protect for controller 0 */
207 zylonite_mmc_slot[0].gpio_cd = EXT_GPIO(0); 205 zylonite_mmc_slot[0].gpio_cd = EXT_GPIO(0);
208 zylonite_mmc_slot[0].gpio_wp = EXT_GPIO(2); 206 zylonite_mmc_slot[0].gpio_wp = EXT_GPIO(2);
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c
index 193d07903b06..2b4fc34919ac 100644
--- a/arch/arm/mach-pxa/zylonite_pxa320.c
+++ b/arch/arm/mach-pxa/zylonite_pxa320.c
@@ -49,6 +49,7 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
49 GPIO15_2_LCD_LCLK, 49 GPIO15_2_LCD_LCLK,
50 GPIO16_2_LCD_PCLK, 50 GPIO16_2_LCD_PCLK,
51 GPIO17_2_LCD_BIAS, 51 GPIO17_2_LCD_BIAS,
52 GPIO14_PWM3_OUT, /* backlight */
52 53
53 /* FFUART */ 54 /* FFUART */
54 GPIO41_UART1_RXD | MFP_LPM_EDGE_FALL, 55 GPIO41_UART1_RXD | MFP_LPM_EDGE_FALL,
@@ -187,7 +188,6 @@ void __init zylonite_pxa320_init(void)
187 zylonite_detect_lcd_panel(); 188 zylonite_detect_lcd_panel();
188 189
189 /* GPIO pin assignment */ 190 /* GPIO pin assignment */
190 gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO14);
191 gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO9); 191 gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO9);
192 192
193 /* MMC card detect & write protect for controller 0 */ 193 /* MMC card detect & write protect for controller 0 */
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index eb26d2aca8b4..dde6ce963a19 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -944,32 +944,6 @@ static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
944 .functionality = i2c_pxa_functionality, 944 .functionality = i2c_pxa_functionality,
945}; 945};
946 946
947static void i2c_pxa_enable(struct platform_device *dev)
948{
949 if (cpu_is_pxa27x()) {
950 switch (dev->id) {
951 case 0:
952 pxa_gpio_mode(GPIO117_I2CSCL_MD);
953 pxa_gpio_mode(GPIO118_I2CSDA_MD);
954 break;
955 case 1:
956 local_irq_disable();
957 PCFR |= PCFR_PI2CEN;
958 local_irq_enable();
959 break;
960 }
961 }
962}
963
964static void i2c_pxa_disable(struct platform_device *dev)
965{
966 if (cpu_is_pxa27x() && dev->id == 1) {
967 local_irq_disable();
968 PCFR &= ~PCFR_PI2CEN;
969 local_irq_enable();
970 }
971}
972
973#define res_len(r) ((r)->end - (r)->start + 1) 947#define res_len(r) ((r)->end - (r)->start + 1)
974static int i2c_pxa_probe(struct platform_device *dev) 948static int i2c_pxa_probe(struct platform_device *dev)
975{ 949{
@@ -1035,7 +1009,6 @@ static int i2c_pxa_probe(struct platform_device *dev)
1035#endif 1009#endif
1036 1010
1037 clk_enable(i2c->clk); 1011 clk_enable(i2c->clk);
1038 i2c_pxa_enable(dev);
1039 1012
1040 if (plat) { 1013 if (plat) {
1041 i2c->adap.class = plat->class; 1014 i2c->adap.class = plat->class;
@@ -1079,7 +1052,6 @@ eadapt:
1079 free_irq(irq, i2c); 1052 free_irq(irq, i2c);
1080ereqirq: 1053ereqirq:
1081 clk_disable(i2c->clk); 1054 clk_disable(i2c->clk);
1082 i2c_pxa_disable(dev);
1083 iounmap(i2c->reg_base); 1055 iounmap(i2c->reg_base);
1084eremap: 1056eremap:
1085 clk_put(i2c->clk); 1057 clk_put(i2c->clk);
@@ -1102,7 +1074,6 @@ static int __exit i2c_pxa_remove(struct platform_device *dev)
1102 1074
1103 clk_disable(i2c->clk); 1075 clk_disable(i2c->clk);
1104 clk_put(i2c->clk); 1076 clk_put(i2c->clk);
1105 i2c_pxa_disable(dev);
1106 1077
1107 iounmap(i2c->reg_base); 1078 iounmap(i2c->reg_base);
1108 release_mem_region(i2c->iobase, i2c->iosize); 1079 release_mem_region(i2c->iobase, i2c->iosize);
diff --git a/drivers/pcmcia/pxa2xx_cm_x270.c b/drivers/pcmcia/pxa2xx_cm_x270.c
index e7ab060ff118..f123fce65f2e 100644
--- a/drivers/pcmcia/pxa2xx_cm_x270.c
+++ b/drivers/pcmcia/pxa2xx_cm_x270.c
@@ -18,6 +18,7 @@
18 18
19#include <pcmcia/ss.h> 19#include <pcmcia/ss.h>
20#include <asm/hardware.h> 20#include <asm/hardware.h>
21#include <asm/mach-types.h>
21 22
22#include <asm/arch/pxa-regs.h> 23#include <asm/arch/pxa-regs.h>
23#include <asm/arch/pxa2xx-gpio.h> 24#include <asm/arch/pxa2xx-gpio.h>
@@ -130,7 +131,7 @@ static void cmx270_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
130} 131}
131 132
132 133
133static struct pcmcia_low_level cmx270_pcmcia_ops = { 134static struct pcmcia_low_level cmx270_pcmcia_ops __initdata = {
134 .owner = THIS_MODULE, 135 .owner = THIS_MODULE,
135 .hw_init = cmx270_pcmcia_hw_init, 136 .hw_init = cmx270_pcmcia_hw_init,
136 .hw_shutdown = cmx270_pcmcia_shutdown, 137 .hw_shutdown = cmx270_pcmcia_shutdown,
@@ -147,15 +148,21 @@ static int __init cmx270_pcmcia_init(void)
147{ 148{
148 int ret; 149 int ret;
149 150
151 if (!machine_is_armcore())
152 return -ENODEV;
153
150 cmx270_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); 154 cmx270_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
151 155
152 if (!cmx270_pcmcia_device) 156 if (!cmx270_pcmcia_device)
153 return -ENOMEM; 157 return -ENOMEM;
154 158
155 cmx270_pcmcia_device->dev.platform_data = &cmx270_pcmcia_ops; 159 ret = platform_device_add_data(cmx270_pcmcia_device, &cmx270_pcmcia_ops,
160 sizeof(cmx270_pcmcia_ops));
156 161
157 printk(KERN_INFO "Registering cm-x270 PCMCIA interface.\n"); 162 if (ret == 0) {
158 ret = platform_device_add(cmx270_pcmcia_device); 163 printk(KERN_INFO "Registering cm-x270 PCMCIA interface.\n");
164 ret = platform_device_add(cmx270_pcmcia_device);
165 }
159 166
160 if (ret) 167 if (ret)
161 platform_device_put(cmx270_pcmcia_device); 168 platform_device_put(cmx270_pcmcia_device);
diff --git a/drivers/pcmcia/pxa2xx_mainstone.c b/drivers/pcmcia/pxa2xx_mainstone.c
index 145b85e0f02c..92d1cc33808c 100644
--- a/drivers/pcmcia/pxa2xx_mainstone.c
+++ b/drivers/pcmcia/pxa2xx_mainstone.c
@@ -22,6 +22,7 @@
22#include <pcmcia/ss.h> 22#include <pcmcia/ss.h>
23 23
24#include <asm/hardware.h> 24#include <asm/hardware.h>
25#include <asm/mach-types.h>
25#include <asm/irq.h> 26#include <asm/irq.h>
26 27
27#include <asm/arch/pxa-regs.h> 28#include <asm/arch/pxa-regs.h>
@@ -136,7 +137,7 @@ static void mst_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
136{ 137{
137} 138}
138 139
139static struct pcmcia_low_level mst_pcmcia_ops = { 140static struct pcmcia_low_level mst_pcmcia_ops __initdata = {
140 .owner = THIS_MODULE, 141 .owner = THIS_MODULE,
141 .hw_init = mst_pcmcia_hw_init, 142 .hw_init = mst_pcmcia_hw_init,
142 .hw_shutdown = mst_pcmcia_hw_shutdown, 143 .hw_shutdown = mst_pcmcia_hw_shutdown,
@@ -153,13 +154,17 @@ static int __init mst_pcmcia_init(void)
153{ 154{
154 int ret; 155 int ret;
155 156
157 if (!machine_is_mainstone())
158 return -ENODEV;
159
156 mst_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); 160 mst_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
157 if (!mst_pcmcia_device) 161 if (!mst_pcmcia_device)
158 return -ENOMEM; 162 return -ENOMEM;
159 163
160 mst_pcmcia_device->dev.platform_data = &mst_pcmcia_ops; 164 ret = platform_device_add_data(mst_pcmcia_device, &mst_pcmcia_ops,
161 165 sizeof(mst_pcmcia_ops));
162 ret = platform_device_add(mst_pcmcia_device); 166 if (ret == 0)
167 ret = platform_device_add(mst_pcmcia_device);
163 168
164 if (ret) 169 if (ret)
165 platform_device_put(mst_pcmcia_device); 170 platform_device_put(mst_pcmcia_device);
diff --git a/drivers/pcmcia/pxa2xx_sharpsl.c b/drivers/pcmcia/pxa2xx_sharpsl.c
index d5c33bd78d68..d71f93d45833 100644
--- a/drivers/pcmcia/pxa2xx_sharpsl.c
+++ b/drivers/pcmcia/pxa2xx_sharpsl.c
@@ -222,7 +222,7 @@ static void sharpsl_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
222 sharpsl_pcmcia_init_reset(skt); 222 sharpsl_pcmcia_init_reset(skt);
223} 223}
224 224
225static struct pcmcia_low_level sharpsl_pcmcia_ops = { 225static struct pcmcia_low_level sharpsl_pcmcia_ops __initdata = {
226 .owner = THIS_MODULE, 226 .owner = THIS_MODULE,
227 .hw_init = sharpsl_pcmcia_hw_init, 227 .hw_init = sharpsl_pcmcia_hw_init,
228 .hw_shutdown = sharpsl_pcmcia_hw_shutdown, 228 .hw_shutdown = sharpsl_pcmcia_hw_shutdown,
@@ -261,10 +261,12 @@ static int __init sharpsl_pcmcia_init(void)
261 if (!sharpsl_pcmcia_device) 261 if (!sharpsl_pcmcia_device)
262 return -ENOMEM; 262 return -ENOMEM;
263 263
264 sharpsl_pcmcia_device->dev.platform_data = &sharpsl_pcmcia_ops; 264 ret = platform_device_add_data(sharpsl_pcmcia_device,
265 sharpsl_pcmcia_device->dev.parent = platform_scoop_config->devs[0].dev; 265 &sharpsl_pcmcia_ops, sizeof(sharpsl_pcmcia_ops));
266 266 if (ret == 0) {
267 ret = platform_device_add(sharpsl_pcmcia_device); 267 sharpsl_pcmcia_device->dev.parent = platform_scoop_config->devs[0].dev;
268 ret = platform_device_add(sharpsl_pcmcia_device);
269 }
268 270
269 if (ret) 271 if (ret)
270 platform_device_put(sharpsl_pcmcia_device); 272 platform_device_put(sharpsl_pcmcia_device);
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index 499b7a23f351..40d6b580f152 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -38,7 +38,7 @@
38#include <linux/usb.h> 38#include <linux/usb.h>
39#include <linux/usb/ch9.h> 39#include <linux/usb/ch9.h>
40#include <linux/usb/gadget.h> 40#include <linux/usb/gadget.h>
41 41#include <asm/arch/pxa2xx-regs.h> /* FIXME: for PSSR */
42#include <asm/arch/udc.h> 42#include <asm/arch/udc.h>
43 43
44#include "pxa27x_udc.h" 44#include "pxa27x_udc.h"
@@ -2359,7 +2359,8 @@ static int pxa_udc_resume(struct platform_device *_dev)
2359 * Software must configure the USB OTG pad, UDC, and UHC 2359 * Software must configure the USB OTG pad, UDC, and UHC
2360 * to the state they were in before entering sleep mode. 2360 * to the state they were in before entering sleep mode.
2361 */ 2361 */
2362 PSSR |= PSSR_OTGPH; 2362 if (cpu_is_pxa27x())
2363 PSSR |= PSSR_OTGPH;
2363 2364
2364 return 0; 2365 return 0;
2365} 2366}
diff --git a/drivers/usb/gadget/pxa27x_udc.h b/drivers/usb/gadget/pxa27x_udc.h
index 97453db924ff..1d1b7936ee11 100644
--- a/drivers/usb/gadget/pxa27x_udc.h
+++ b/drivers/usb/gadget/pxa27x_udc.h
@@ -484,12 +484,4 @@ static inline struct pxa_udc *to_gadget_udc(struct usb_gadget *gadget)
484#define ep_warn(ep, fmt, arg...) \ 484#define ep_warn(ep, fmt, arg...) \
485 dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg) 485 dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg)
486 486
487/*
488 * Cannot include pxa-regs.h, as register names are similar.
489 * So PSSR is redefined here. This should be removed once UDC registers will
490 * be gone from pxa-regs.h.
491 */
492#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status */
493#define PSSR_OTGPH (1 << 6) /* OTG Peripheral Hold */
494
495#endif /* __LINUX_USB_GADGET_PXA27X_H */ 487#endif /* __LINUX_USB_GADGET_PXA27X_H */
diff --git a/drivers/usb/gadget/pxa2xx_udc.c b/drivers/usb/gadget/pxa2xx_udc.c
index 08f699b1fc57..63db96adc0b0 100644
--- a/drivers/usb/gadget/pxa2xx_udc.c
+++ b/drivers/usb/gadget/pxa2xx_udc.c
@@ -46,19 +46,25 @@
46#include <linux/err.h> 46#include <linux/err.h>
47#include <linux/seq_file.h> 47#include <linux/seq_file.h>
48#include <linux/debugfs.h> 48#include <linux/debugfs.h>
49#include <linux/io.h>
49 50
50#include <asm/byteorder.h> 51#include <asm/byteorder.h>
51#include <asm/dma.h> 52#include <asm/dma.h>
52#include <asm/gpio.h> 53#include <asm/gpio.h>
53#include <asm/io.h>
54#include <asm/system.h> 54#include <asm/system.h>
55#include <asm/mach-types.h> 55#include <asm/mach-types.h>
56#include <asm/unaligned.h> 56#include <asm/unaligned.h>
57#include <asm/hardware.h>
58 57
59#include <linux/usb/ch9.h> 58#include <linux/usb/ch9.h>
60#include <linux/usb/gadget.h> 59#include <linux/usb/gadget.h>
61 60
61/*
62 * This driver is PXA25x only. Grab the right register definitions.
63 */
64#ifdef CONFIG_ARCH_PXA
65#include <asm/arch/pxa25x-udc.h>
66#endif
67
62#include <asm/mach/udc_pxa2xx.h> 68#include <asm/mach/udc_pxa2xx.h>
63 69
64 70
diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c
index 70b0d4b459e7..08b27d6bbd43 100644
--- a/drivers/usb/host/ohci-pxa27x.c
+++ b/drivers/usb/host/ohci-pxa27x.c
@@ -27,6 +27,7 @@
27#include <asm/mach-types.h> 27#include <asm/mach-types.h>
28#include <asm/hardware.h> 28#include <asm/hardware.h>
29#include <asm/arch/pxa-regs.h> 29#include <asm/arch/pxa-regs.h>
30#include <asm/arch/pxa2xx-regs.h> /* FIXME: for PSSR */
30#include <asm/arch/ohci.h> 31#include <asm/arch/ohci.h>
31 32
32#define PXA_UHC_MAX_PORTNUM 3 33#define PXA_UHC_MAX_PORTNUM 3
@@ -104,7 +105,7 @@ static int pxa27x_start_hc(struct device *dev)
104 UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); 105 UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
105 106
106 /* Clear any OTG Pin Hold */ 107 /* Clear any OTG Pin Hold */
107 if (PSSR & PSSR_OTGPH) 108 if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
108 PSSR |= PSSR_OTGPH; 109 PSSR |= PSSR_OTGPH;
109 110
110 return 0; 111 return 0;
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
index dcd8073c2369..30bf7f2f1635 100644
--- a/drivers/video/backlight/Kconfig
+++ b/drivers/video/backlight/Kconfig
@@ -112,3 +112,10 @@ config BACKLIGHT_CARILLO_RANCH
112 help 112 help
113 If you have a Intel LE80578 (Carillo Ranch) say Y to enable the 113 If you have a Intel LE80578 (Carillo Ranch) say Y to enable the
114 backlight driver. 114 backlight driver.
115
116config BACKLIGHT_PWM
117 tristate "Generic PWM based Backlight Driver"
118 depends on BACKLIGHT_CLASS_DEVICE && HAVE_PWM
119 help
120 If you have a LCD backlight adjustable by PWM, say Y to enable
121 this driver.
diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
index 33f6c7cecc73..b51a7cd12500 100644
--- a/drivers/video/backlight/Makefile
+++ b/drivers/video/backlight/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o
10obj-$(CONFIG_BACKLIGHT_OMAP1) += omap1_bl.o 10obj-$(CONFIG_BACKLIGHT_OMAP1) += omap1_bl.o
11obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o 11obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o
12obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o 12obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o
13obj-$(CONFIG_BACKLIGHT_PWM) += pwm_bl.o
diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
new file mode 100644
index 000000000000..6338d0e2fe07
--- /dev/null
+++ b/drivers/video/backlight/pwm_bl.c
@@ -0,0 +1,185 @@
1/*
2 * linux/drivers/video/backlight/pwm_bl.c
3 *
4 * simple PWM based backlight control, board code has to setup
5 * 1) pin configuration so PWM waveforms can output
6 * 2) platform_data casts to the PWM id (0/1/2/3 on PXA)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/fb.h>
18#include <linux/backlight.h>
19#include <linux/err.h>
20#include <linux/pwm.h>
21#include <linux/pwm_backlight.h>
22
23struct pwm_bl_data {
24 struct pwm_device *pwm;
25 unsigned int period;
26 int (*notify)(int brightness);
27};
28
29static int pwm_backlight_update_status(struct backlight_device *bl)
30{
31 struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
32 int brightness = bl->props.brightness;
33 int max = bl->props.max_brightness;
34
35 if (bl->props.power != FB_BLANK_UNBLANK)
36 brightness = 0;
37
38 if (bl->props.fb_blank != FB_BLANK_UNBLANK)
39 brightness = 0;
40
41 if (pb->notify)
42 brightness = pb->notify(brightness);
43
44 if (brightness == 0) {
45 pwm_config(pb->pwm, 0, pb->period);
46 pwm_disable(pb->pwm);
47 } else {
48 pwm_config(pb->pwm, brightness * pb->period / max, pb->period);
49 pwm_enable(pb->pwm);
50 }
51 return 0;
52}
53
54static int pwm_backlight_get_brightness(struct backlight_device *bl)
55{
56 return bl->props.brightness;
57}
58
59static struct backlight_ops pwm_backlight_ops = {
60 .update_status = pwm_backlight_update_status,
61 .get_brightness = pwm_backlight_get_brightness,
62};
63
64static int pwm_backlight_probe(struct platform_device *pdev)
65{
66 struct platform_pwm_backlight_data *data = pdev->dev.platform_data;
67 struct backlight_device *bl;
68 struct pwm_bl_data *pb;
69 int ret;
70
71 if (!data)
72 return -EINVAL;
73
74 if (data->init) {
75 ret = data->init(&pdev->dev);
76 if (ret < 0)
77 return ret;
78 }
79
80 pb = kzalloc(sizeof(*pb), GFP_KERNEL);
81 if (!pb) {
82 ret = -ENOMEM;
83 goto err_alloc;
84 }
85
86 pb->period = data->pwm_period_ns;
87 pb->notify = data->notify;
88
89 pb->pwm = pwm_request(data->pwm_id, "backlight");
90 if (IS_ERR(pb->pwm)) {
91 dev_err(&pdev->dev, "unable to request PWM for backlight\n");
92 ret = PTR_ERR(pb->pwm);
93 goto err_pwm;
94 }
95
96 bl = backlight_device_register(pdev->name, &pdev->dev,
97 pb, &pwm_backlight_ops);
98 if (IS_ERR(bl)) {
99 dev_err(&pdev->dev, "failed to register backlight\n");
100 ret = PTR_ERR(bl);
101 goto err_bl;
102 }
103
104 bl->props.max_brightness = data->max_brightness;
105 bl->props.brightness = data->dft_brightness;
106 backlight_update_status(bl);
107
108 platform_set_drvdata(pdev, bl);
109 return 0;
110
111err_bl:
112 pwm_free(pb->pwm);
113err_pwm:
114 kfree(pb);
115err_alloc:
116 if (data->exit)
117 data->exit(&pdev->dev);
118 return ret;
119}
120
121static int pwm_backlight_remove(struct platform_device *pdev)
122{
123 struct platform_pwm_backlight_data *data = pdev->dev.platform_data;
124 struct backlight_device *bl = platform_get_drvdata(pdev);
125 struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
126
127 backlight_device_unregister(bl);
128 pwm_config(pb->pwm, 0, pb->period);
129 pwm_disable(pb->pwm);
130 pwm_free(pb->pwm);
131 kfree(pb);
132 if (data->exit)
133 data->exit(&pdev->dev);
134 return 0;
135}
136
137#ifdef CONFIG_PM
138static int pwm_backlight_suspend(struct platform_device *pdev,
139 pm_message_t state)
140{
141 struct backlight_device *bl = platform_get_drvdata(pdev);
142 struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
143
144 pwm_config(pb->pwm, 0, pb->period);
145 pwm_disable(pb->pwm);
146 return 0;
147}
148
149static int pwm_backlight_resume(struct platform_device *pdev)
150{
151 struct backlight_device *bl = platform_get_drvdata(pdev);
152
153 backlight_update_status(bl);
154 return 0;
155}
156#else
157#define pwm_backlight_suspend NULL
158#define pwm_backlight_resume NULL
159#endif
160
161static struct platform_driver pwm_backlight_driver = {
162 .driver = {
163 .name = "pwm-backlight",
164 .owner = THIS_MODULE,
165 },
166 .probe = pwm_backlight_probe,
167 .remove = pwm_backlight_remove,
168 .suspend = pwm_backlight_suspend,
169 .resume = pwm_backlight_resume,
170};
171
172static int __init pwm_backlight_init(void)
173{
174 return platform_driver_register(&pwm_backlight_driver);
175}
176module_init(pwm_backlight_init);
177
178static void __exit pwm_backlight_exit(void)
179{
180 platform_driver_unregister(&pwm_backlight_driver);
181}
182module_exit(pwm_backlight_exit);
183
184MODULE_DESCRIPTION("PWM based Backlight Driver");
185MODULE_LICENSE("GPL");
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 4b2ea1e95c57..dce9308626b7 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -600,418 +600,6 @@
600 600
601 601
602/* 602/*
603 * USB Device Controller
604 * PXA25x and PXA27x USB device controller registers are different.
605 */
606#if defined(CONFIG_PXA25x)
607
608#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
609#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
610#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
611
612#define UDCCR __REG(0x40600000) /* UDC Control Register */
613#define UDCCR_UDE (1 << 0) /* UDC enable */
614#define UDCCR_UDA (1 << 1) /* UDC active */
615#define UDCCR_RSM (1 << 2) /* Device resume */
616#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
617#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
618#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
619#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
620#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
621
622#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
623#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
624#define UDCCS0_IPR (1 << 1) /* IN packet ready */
625#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
626#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
627#define UDCCS0_SST (1 << 4) /* Sent stall */
628#define UDCCS0_FST (1 << 5) /* Force stall */
629#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
630#define UDCCS0_SA (1 << 7) /* Setup active */
631
632/* Bulk IN - Endpoint 1,6,11 */
633#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
634#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
635#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
636
637#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
638#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
639#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
640#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
641#define UDCCS_BI_SST (1 << 4) /* Sent stall */
642#define UDCCS_BI_FST (1 << 5) /* Force stall */
643#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
644
645/* Bulk OUT - Endpoint 2,7,12 */
646#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
647#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
648#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
649
650#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
651#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
652#define UDCCS_BO_DME (1 << 3) /* DMA enable */
653#define UDCCS_BO_SST (1 << 4) /* Sent stall */
654#define UDCCS_BO_FST (1 << 5) /* Force stall */
655#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
656#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
657
658/* Isochronous IN - Endpoint 3,8,13 */
659#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
660#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
661#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
662
663#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
664#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
665#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
666#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
667#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
668
669/* Isochronous OUT - Endpoint 4,9,14 */
670#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
671#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
672#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
673
674#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
675#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
676#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */
677#define UDCCS_IO_DME (1 << 3) /* DMA enable */
678#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
679#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
680
681/* Interrupt IN - Endpoint 5,10,15 */
682#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
683#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
684#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
685
686#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
687#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
688#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
689#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
690#define UDCCS_INT_SST (1 << 4) /* Sent stall */
691#define UDCCS_INT_FST (1 << 5) /* Force stall */
692#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
693
694#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
695#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
696#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
697#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
698#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
699#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
700#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
701#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
702#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
703#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
704#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
705#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
706#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
707#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
708#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
709#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
710#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
711#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
712#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
713#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
714#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
715#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
716#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
717#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
718
719#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
720
721#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
722#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
723#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
724#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
725#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
726#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
727#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
728#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
729
730#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
731
732#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
733#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
734#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
735#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
736#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
737#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
738#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
739#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
740
741#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
742
743#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
744#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
745#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
746#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
747#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
748#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
749#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
750#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
751
752#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
753
754#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
755#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
756#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
757#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
758#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
759#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
760#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
761#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
762
763#elif defined(CONFIG_PXA27x)
764
765#define UDCCR __REG(0x40600000) /* UDC Control Register */
766#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
767#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
768 Protocol Port Support */
769#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
770 Support */
771#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
772 Enable */
773#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
774#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
775#define UDCCR_ACN_S 11
776#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
777#define UDCCR_AIN_S 8
778#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
779 Setting Number */
780#define UDCCR_AAISN_S 5
781#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
782 Configuration */
783#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
784 Error */
785#define UDCCR_UDR (1 << 2) /* UDC Resume */
786#define UDCCR_UDA (1 << 1) /* UDC Active */
787#define UDCCR_UDE (1 << 0) /* UDC Enable */
788
789#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
790#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
791#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
792#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
793
794#define UDC_INT_FIFOERROR (0x2)
795#define UDC_INT_PACKETCMP (0x1)
796
797#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
798#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
799#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
800#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
801#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
802#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
803
804#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
805#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
806#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
807#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
808#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
809#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
810#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
811#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
812
813#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
814#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
815#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
816#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
817 Rising Edge Interrupt Enable */
818#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
819 Falling Edge Interrupt Enable */
820#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
821 Interrupt Enable */
822#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
823 Interrupt Enable */
824#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
825 Interrupt Enable */
826#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
827 Interrupt Enable */
828#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
829 Interrupt Enable */
830#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
831 Interrupt Enable */
832#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
833 Edge Interrupt Enable */
834#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
835 Edge Interrupt Enable */
836#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
837 Interrupt Enable */
838#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
839 Interrupt Enable */
840
841#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
842
843#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
844#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
845#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
846#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
847#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
848#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
849#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
850#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
851#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
852#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
853#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
854#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
855#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
856#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
857
858#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
859#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
860#define UDCCSR0_SA (1 << 7) /* Setup Active */
861#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
862#define UDCCSR0_FST (1 << 5) /* Force Stall */
863#define UDCCSR0_SST (1 << 4) /* Sent Stall */
864#define UDCCSR0_DME (1 << 3) /* DMA Enable */
865#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
866#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
867#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
868
869#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
870#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
871#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
872#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
873#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
874#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
875#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
876#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
877#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
878#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
879#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
880#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
881#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
882#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
883#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
884#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
885#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
886#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
887#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
888#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
889#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
890#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
891#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
892
893#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
894#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
895#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
896#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
897#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
898#define UDCCSR_FST (1 << 5) /* Force STALL */
899#define UDCCSR_SST (1 << 4) /* Sent STALL */
900#define UDCCSR_DME (1 << 3) /* DMA Enable */
901#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
902#define UDCCSR_PC (1 << 1) /* Packet Complete */
903#define UDCCSR_FS (1 << 0) /* FIFO needs service */
904
905#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
906#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
907#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
908#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
909#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
910#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
911#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
912#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
913#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
914#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
915#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
916#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
917#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
918#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
919#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
920#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
921#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
922#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
923#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
924#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
925#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
926#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
927#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
928#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
929#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
930
931#define UDCDN(x) __REG2(0x40600300, (x)<<2)
932#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
933#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
934#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
935#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
936#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
937#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
938#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
939#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
940#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
941#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
942#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
943#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
944#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
945#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
946#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
947#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
948#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
949#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
950#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
951#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
952#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
953#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
954#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
955#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
956#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
957#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
958
959#define UDCCN(x) __REG2(0x40600400, (x)<<2)
960#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
961#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
962#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
963#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
964#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
965#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
966#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
967#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
968#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
969#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
970#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
971#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
972#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
973#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
974#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
975#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
976#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
977#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
978#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
979#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
980#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
981#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
982#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
983
984#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
985#define UDCCONR_CN_S (25)
986#define UDCCONR_IN (0x07 << 22) /* Interface Number */
987#define UDCCONR_IN_S (22)
988#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
989#define UDCCONR_AISN_S (19)
990#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
991#define UDCCONR_EN_S (15)
992#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
993#define UDCCONR_ET_S (13)
994#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
995#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
996#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
997#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
998#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
999#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
1000#define UDCCONR_MPS_S (2)
1001#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
1002#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
1003
1004
1005#define UDC_INT_FIFOERROR (0x2)
1006#define UDC_INT_PACKETCMP (0x1)
1007
1008#define UDC_FNR_MASK (0x7ff)
1009
1010#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
1011#define UDC_BCR_MASK (0x3ff)
1012#endif
1013
1014/*
1015 * Fast Infrared Communication Port 603 * Fast Infrared Communication Port
1016 */ 604 */
1017 605
@@ -1237,120 +825,9 @@
1237#endif 825#endif
1238 826
1239/* 827/*
1240 * Power Manager 828 * Power Manager - see pxa2xx-regs.h
1241 */ 829 */
1242 830
1243#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
1244#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
1245#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
1246#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
1247#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
1248#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
1249#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
1250#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
1251#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
1252#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
1253#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
1254#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
1255#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
1256
1257#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
1258#define PSTR __REG(0x40F00038) /*Power Manager Standby Config Register */
1259#define PSNR __REG(0x40F0003C) /*Power Manager Sense Config Register */
1260#define PVCR __REG(0x40F00040) /*Power Manager VoltageControl Register */
1261#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
1262#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
1263#define PCMD(x) __REG2(0x40F00080, (x)<<2)
1264#define PCMD0 __REG(0x40F00080 + 0 * 4)
1265#define PCMD1 __REG(0x40F00080 + 1 * 4)
1266#define PCMD2 __REG(0x40F00080 + 2 * 4)
1267#define PCMD3 __REG(0x40F00080 + 3 * 4)
1268#define PCMD4 __REG(0x40F00080 + 4 * 4)
1269#define PCMD5 __REG(0x40F00080 + 5 * 4)
1270#define PCMD6 __REG(0x40F00080 + 6 * 4)
1271#define PCMD7 __REG(0x40F00080 + 7 * 4)
1272#define PCMD8 __REG(0x40F00080 + 8 * 4)
1273#define PCMD9 __REG(0x40F00080 + 9 * 4)
1274#define PCMD10 __REG(0x40F00080 + 10 * 4)
1275#define PCMD11 __REG(0x40F00080 + 11 * 4)
1276#define PCMD12 __REG(0x40F00080 + 12 * 4)
1277#define PCMD13 __REG(0x40F00080 + 13 * 4)
1278#define PCMD14 __REG(0x40F00080 + 14 * 4)
1279#define PCMD15 __REG(0x40F00080 + 15 * 4)
1280#define PCMD16 __REG(0x40F00080 + 16 * 4)
1281#define PCMD17 __REG(0x40F00080 + 17 * 4)
1282#define PCMD18 __REG(0x40F00080 + 18 * 4)
1283#define PCMD19 __REG(0x40F00080 + 19 * 4)
1284#define PCMD20 __REG(0x40F00080 + 20 * 4)
1285#define PCMD21 __REG(0x40F00080 + 21 * 4)
1286#define PCMD22 __REG(0x40F00080 + 22 * 4)
1287#define PCMD23 __REG(0x40F00080 + 23 * 4)
1288#define PCMD24 __REG(0x40F00080 + 24 * 4)
1289#define PCMD25 __REG(0x40F00080 + 25 * 4)
1290#define PCMD26 __REG(0x40F00080 + 26 * 4)
1291#define PCMD27 __REG(0x40F00080 + 27 * 4)
1292#define PCMD28 __REG(0x40F00080 + 28 * 4)
1293#define PCMD29 __REG(0x40F00080 + 29 * 4)
1294#define PCMD30 __REG(0x40F00080 + 30 * 4)
1295#define PCMD31 __REG(0x40F00080 + 31 * 4)
1296
1297#define PCMD_MBC (1<<12)
1298#define PCMD_DCE (1<<11)
1299#define PCMD_LC (1<<10)
1300/* FIXME: PCMD_SQC need be checked. */
1301#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
1302 bit 9 should be 0 all day. */
1303#define PVCR_VCSA (0x1<<14)
1304#define PVCR_CommandDelay (0xf80)
1305#define PCFR_PI2C_EN (0x1 << 6)
1306
1307#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
1308#define PSSR_RDH (1 << 5) /* Read Disable Hold */
1309#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
1310#define PSSR_STS (1 << 3) /* Standby Mode Status */
1311#define PSSR_VFS (1 << 2) /* VDD Fault Status */
1312#define PSSR_BFS (1 << 1) /* Battery Fault Status */
1313#define PSSR_SSS (1 << 0) /* Software Sleep Status */
1314
1315#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
1316
1317#define PCFR_RO (1 << 15) /* RDH Override */
1318#define PCFR_PO (1 << 14) /* PH Override */
1319#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
1320#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
1321#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
1322#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
1323#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
1324#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
1325#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
1326#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
1327#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
1328#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
1329
1330#define RCSR_GPR (1 << 3) /* GPIO Reset */
1331#define RCSR_SMR (1 << 2) /* Sleep Mode */
1332#define RCSR_WDR (1 << 1) /* Watchdog Reset */
1333#define RCSR_HWR (1 << 0) /* Hardware Reset */
1334
1335#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
1336#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
1337#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
1338#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
1339#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
1340#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
1341#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
1342#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
1343#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
1344#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
1345#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
1346#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
1347#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
1348#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
1349#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
1350#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
1351#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
1352#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
1353
1354/* 831/*
1355 * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h 832 * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
1356 */ 833 */
@@ -1360,52 +837,9 @@
1360 */ 837 */
1361 838
1362/* 839/*
1363 * Core Clock 840 * Core Clock - see include/asm-arm/arch-pxa/pxa2xx-regs.h
1364 */ 841 */
1365 842
1366#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
1367#define CKEN __REG(0x41300004) /* Clock Enable Register */
1368#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
1369#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
1370
1371#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
1372#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
1373#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
1374
1375#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */
1376#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
1377#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
1378#define CKEN_MEMC (22) /* Memory Controller Clock Enable */
1379#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
1380#define CKEN_IM (20) /* Internal Memory Clock Enable */
1381#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
1382#define CKEN_USIM (18) /* USIM Unit Clock Enable */
1383#define CKEN_MSL (17) /* MSL Unit Clock Enable */
1384#define CKEN_LCD (16) /* LCD Unit Clock Enable */
1385#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
1386#define CKEN_I2C (14) /* I2C Unit Clock Enable */
1387#define CKEN_FICP (13) /* FICP Unit Clock Enable */
1388#define CKEN_MMC (12) /* MMC Unit Clock Enable */
1389#define CKEN_USB (11) /* USB Unit Clock Enable */
1390#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
1391#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
1392#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
1393#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
1394#define CKEN_I2S (8) /* I2S Unit Clock Enable */
1395#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
1396#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
1397#define CKEN_STUART (5) /* STUART Unit Clock Enable */
1398#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
1399#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
1400#define CKEN_SSP (3) /* SSP Unit Clock Enable */
1401#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
1402#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
1403#define CKEN_PWM1 (1) /* PWM1 Clock Enable */
1404#define CKEN_PWM0 (0) /* PWM0 Clock Enable */
1405
1406#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
1407#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
1408
1409#ifdef CONFIG_PXA27x 843#ifdef CONFIG_PXA27x
1410 844
1411/* Camera Interface */ 845/* Camera Interface */
diff --git a/include/asm-arm/arch-pxa/pxa25x-udc.h b/include/asm-arm/arch-pxa/pxa25x-udc.h
new file mode 100644
index 000000000000..840305916b6d
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa25x-udc.h
@@ -0,0 +1,163 @@
1#ifndef _ASM_ARCH_PXA25X_UDC_H
2#define _ASM_ARCH_PXA25X_UDC_H
3
4#ifdef _ASM_ARCH_PXA27X_UDC_H
5#error You can't include both PXA25x and PXA27x UDC support
6#endif
7
8#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
9#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
10#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
11
12#define UDCCR __REG(0x40600000) /* UDC Control Register */
13#define UDCCR_UDE (1 << 0) /* UDC enable */
14#define UDCCR_UDA (1 << 1) /* UDC active */
15#define UDCCR_RSM (1 << 2) /* Device resume */
16#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
17#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
18#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
19#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
20#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
21
22#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
23#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
24#define UDCCS0_IPR (1 << 1) /* IN packet ready */
25#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
26#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
27#define UDCCS0_SST (1 << 4) /* Sent stall */
28#define UDCCS0_FST (1 << 5) /* Force stall */
29#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
30#define UDCCS0_SA (1 << 7) /* Setup active */
31
32/* Bulk IN - Endpoint 1,6,11 */
33#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
34#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
35#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
36
37#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
38#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
39#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
40#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
41#define UDCCS_BI_SST (1 << 4) /* Sent stall */
42#define UDCCS_BI_FST (1 << 5) /* Force stall */
43#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
44
45/* Bulk OUT - Endpoint 2,7,12 */
46#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
47#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
48#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
49
50#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
51#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
52#define UDCCS_BO_DME (1 << 3) /* DMA enable */
53#define UDCCS_BO_SST (1 << 4) /* Sent stall */
54#define UDCCS_BO_FST (1 << 5) /* Force stall */
55#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
56#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
57
58/* Isochronous IN - Endpoint 3,8,13 */
59#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
60#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
61#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
62
63#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
64#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
65#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
66#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
67#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
68
69/* Isochronous OUT - Endpoint 4,9,14 */
70#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
71#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
72#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
73
74#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
75#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
76#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */
77#define UDCCS_IO_DME (1 << 3) /* DMA enable */
78#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
79#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
80
81/* Interrupt IN - Endpoint 5,10,15 */
82#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
83#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
84#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
85
86#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
87#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
88#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
89#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
90#define UDCCS_INT_SST (1 << 4) /* Sent stall */
91#define UDCCS_INT_FST (1 << 5) /* Force stall */
92#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
93
94#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
95#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
96#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
97#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
98#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
99#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
100#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
101#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
102#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
103#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
104#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
105#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
106#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
107#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
108#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
109#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
110#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
111#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
112#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
113#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
114#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
115#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
116#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
117#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
118
119#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
120
121#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
122#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
123#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
124#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
125#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
126#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
127#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
128#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
129
130#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
131
132#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
133#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
134#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
135#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
136#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
137#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
138#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
139#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
140
141#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
142
143#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
144#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
145#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
146#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
147#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
148#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
149#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
150#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
151
152#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
153
154#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
155#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
156#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
157#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
158#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
159#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
160#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
161#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
162
163#endif
diff --git a/include/asm-arm/arch-pxa/pxa27x-udc.h b/include/asm-arm/arch-pxa/pxa27x-udc.h
new file mode 100644
index 000000000000..bc1cf7d0773a
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa27x-udc.h
@@ -0,0 +1,257 @@
1#ifndef _ASM_ARCH_PXA27X_UDC_H
2#define _ASM_ARCH_PXA27X_UDC_H
3
4#ifdef _ASM_ARCH_PXA25X_UDC_H
5#error You cannot include both PXA25x and PXA27x UDC support
6#endif
7
8#define UDCCR __REG(0x40600000) /* UDC Control Register */
9#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
10#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
11 Protocol Port Support */
12#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
13 Support */
14#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
15 Enable */
16#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
17#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
18#define UDCCR_ACN_S 11
19#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
20#define UDCCR_AIN_S 8
21#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
22 Setting Number */
23#define UDCCR_AAISN_S 5
24#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
25 Configuration */
26#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
27 Error */
28#define UDCCR_UDR (1 << 2) /* UDC Resume */
29#define UDCCR_UDA (1 << 1) /* UDC Active */
30#define UDCCR_UDE (1 << 0) /* UDC Enable */
31
32#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
33#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
34#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
35#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
36
37#define UDC_INT_FIFOERROR (0x2)
38#define UDC_INT_PACKETCMP (0x1)
39
40#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
41#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
42#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
43#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
44#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
45#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
46
47#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
48#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
49#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
50#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
51#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
52#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
53#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
54#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
55
56#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
57#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
58#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
59#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
60 Rising Edge Interrupt Enable */
61#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
62 Falling Edge Interrupt Enable */
63#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
64 Interrupt Enable */
65#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
66 Interrupt Enable */
67#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
68 Interrupt Enable */
69#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
70 Interrupt Enable */
71#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
72 Interrupt Enable */
73#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
74 Interrupt Enable */
75#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
76 Edge Interrupt Enable */
77#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
78 Edge Interrupt Enable */
79#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
80 Interrupt Enable */
81#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
82 Interrupt Enable */
83
84#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
85#define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */
86
87#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
88#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
89#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
90#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
91#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
92#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
93#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
94#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
95#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
96#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
97#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
98#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
99#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
100#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
101
102#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
103#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
104#define UDCCSR0_SA (1 << 7) /* Setup Active */
105#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
106#define UDCCSR0_FST (1 << 5) /* Force Stall */
107#define UDCCSR0_SST (1 << 4) /* Sent Stall */
108#define UDCCSR0_DME (1 << 3) /* DMA Enable */
109#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
110#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
111#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
112
113#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
114#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
115#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
116#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
117#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
118#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
119#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
120#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
121#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
122#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
123#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
124#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
125#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
126#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
127#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
128#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
129#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
130#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
131#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
132#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
133#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
134#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
135#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
136
137#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
138#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
139#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
140#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
141#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
142#define UDCCSR_FST (1 << 5) /* Force STALL */
143#define UDCCSR_SST (1 << 4) /* Sent STALL */
144#define UDCCSR_DME (1 << 3) /* DMA Enable */
145#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
146#define UDCCSR_PC (1 << 1) /* Packet Complete */
147#define UDCCSR_FS (1 << 0) /* FIFO needs service */
148
149#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
150#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
151#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
152#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
153#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
154#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
155#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
156#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
157#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
158#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
159#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
160#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
161#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
162#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
163#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
164#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
165#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
166#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
167#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
168#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
169#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
170#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
171#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
172#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
173#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
174
175#define UDCDN(x) __REG2(0x40600300, (x)<<2)
176#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
177#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
178#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
179#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
180#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
181#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
182#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
183#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
184#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
185#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
186#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
187#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
188#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
189#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
190#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
191#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
192#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
193#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
194#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
195#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
196#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
197#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
198#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
199#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
200#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
201#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
202
203#define UDCCN(x) __REG2(0x40600400, (x)<<2)
204#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
205#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
206#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
207#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
208#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
209#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
210#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
211#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
212#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
213#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
214#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
215#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
216#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
217#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
218#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
219#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
220#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
221#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
222#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
223#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
224#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
225#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
226#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
227
228#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
229#define UDCCONR_CN_S (25)
230#define UDCCONR_IN (0x07 << 22) /* Interface Number */
231#define UDCCONR_IN_S (22)
232#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
233#define UDCCONR_AISN_S (19)
234#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
235#define UDCCONR_EN_S (15)
236#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
237#define UDCCONR_ET_S (13)
238#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
239#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
240#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
241#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
242#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
243#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
244#define UDCCONR_MPS_S (2)
245#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
246#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
247
248
249#define UDC_INT_FIFOERROR (0x2)
250#define UDC_INT_PACKETCMP (0x1)
251
252#define UDC_FNR_MASK (0x7ff)
253
254#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
255#define UDC_BCR_MASK (0x3ff)
256
257#endif
diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h b/include/asm-arm/arch-pxa/pxa2xx-regs.h
index 9553b54fa5bc..73e0a329cf7f 100644
--- a/include/asm-arm/arch-pxa/pxa2xx-regs.h
+++ b/include/asm-arm/arch-pxa/pxa2xx-regs.h
@@ -81,4 +81,166 @@
81 81
82#endif 82#endif
83 83
84
85/*
86 * Power Manager
87 */
88
89#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
90#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
91#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
92#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
93#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
94#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
95#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
96#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
97#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
98#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
99#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
100#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
101#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
102
103#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
104#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */
105#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */
106#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */
107#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
108#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
109#define PCMD(x) __REG2(0x40F00080, (x)<<2)
110#define PCMD0 __REG(0x40F00080 + 0 * 4)
111#define PCMD1 __REG(0x40F00080 + 1 * 4)
112#define PCMD2 __REG(0x40F00080 + 2 * 4)
113#define PCMD3 __REG(0x40F00080 + 3 * 4)
114#define PCMD4 __REG(0x40F00080 + 4 * 4)
115#define PCMD5 __REG(0x40F00080 + 5 * 4)
116#define PCMD6 __REG(0x40F00080 + 6 * 4)
117#define PCMD7 __REG(0x40F00080 + 7 * 4)
118#define PCMD8 __REG(0x40F00080 + 8 * 4)
119#define PCMD9 __REG(0x40F00080 + 9 * 4)
120#define PCMD10 __REG(0x40F00080 + 10 * 4)
121#define PCMD11 __REG(0x40F00080 + 11 * 4)
122#define PCMD12 __REG(0x40F00080 + 12 * 4)
123#define PCMD13 __REG(0x40F00080 + 13 * 4)
124#define PCMD14 __REG(0x40F00080 + 14 * 4)
125#define PCMD15 __REG(0x40F00080 + 15 * 4)
126#define PCMD16 __REG(0x40F00080 + 16 * 4)
127#define PCMD17 __REG(0x40F00080 + 17 * 4)
128#define PCMD18 __REG(0x40F00080 + 18 * 4)
129#define PCMD19 __REG(0x40F00080 + 19 * 4)
130#define PCMD20 __REG(0x40F00080 + 20 * 4)
131#define PCMD21 __REG(0x40F00080 + 21 * 4)
132#define PCMD22 __REG(0x40F00080 + 22 * 4)
133#define PCMD23 __REG(0x40F00080 + 23 * 4)
134#define PCMD24 __REG(0x40F00080 + 24 * 4)
135#define PCMD25 __REG(0x40F00080 + 25 * 4)
136#define PCMD26 __REG(0x40F00080 + 26 * 4)
137#define PCMD27 __REG(0x40F00080 + 27 * 4)
138#define PCMD28 __REG(0x40F00080 + 28 * 4)
139#define PCMD29 __REG(0x40F00080 + 29 * 4)
140#define PCMD30 __REG(0x40F00080 + 30 * 4)
141#define PCMD31 __REG(0x40F00080 + 31 * 4)
142
143#define PCMD_MBC (1<<12)
144#define PCMD_DCE (1<<11)
145#define PCMD_LC (1<<10)
146/* FIXME: PCMD_SQC need be checked. */
147#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
148 bit 9 should be 0 all day. */
149#define PVCR_VCSA (0x1<<14)
150#define PVCR_CommandDelay (0xf80)
151#define PCFR_PI2C_EN (0x1 << 6)
152
153#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
154#define PSSR_RDH (1 << 5) /* Read Disable Hold */
155#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
156#define PSSR_STS (1 << 3) /* Standby Mode Status */
157#define PSSR_VFS (1 << 2) /* VDD Fault Status */
158#define PSSR_BFS (1 << 1) /* Battery Fault Status */
159#define PSSR_SSS (1 << 0) /* Software Sleep Status */
160
161#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
162
163#define PCFR_RO (1 << 15) /* RDH Override */
164#define PCFR_PO (1 << 14) /* PH Override */
165#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
166#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
167#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
168#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
169#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
170#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
171#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
172#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
173#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
174#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
175
176#define RCSR_GPR (1 << 3) /* GPIO Reset */
177#define RCSR_SMR (1 << 2) /* Sleep Mode */
178#define RCSR_WDR (1 << 1) /* Watchdog Reset */
179#define RCSR_HWR (1 << 0) /* Hardware Reset */
180
181#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
182#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
183#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
184#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
185#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
186#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
187#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
188#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
189#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
190#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
191#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
192#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
193#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
194#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
195#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
196#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
197#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
198#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
199
200/*
201 * PXA2xx specific Core clock definitions
202 */
203#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
204#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
205#define CKEN __REG(0x41300004) /* Clock Enable Register */
206#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
207
208#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
209#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
210#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
211
212#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */
213#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
214#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
215#define CKEN_MEMC (22) /* Memory Controller Clock Enable */
216#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
217#define CKEN_IM (20) /* Internal Memory Clock Enable */
218#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
219#define CKEN_USIM (18) /* USIM Unit Clock Enable */
220#define CKEN_MSL (17) /* MSL Unit Clock Enable */
221#define CKEN_LCD (16) /* LCD Unit Clock Enable */
222#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
223#define CKEN_I2C (14) /* I2C Unit Clock Enable */
224#define CKEN_FICP (13) /* FICP Unit Clock Enable */
225#define CKEN_MMC (12) /* MMC Unit Clock Enable */
226#define CKEN_USB (11) /* USB Unit Clock Enable */
227#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
228#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
229#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
230#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
231#define CKEN_I2S (8) /* I2S Unit Clock Enable */
232#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
233#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
234#define CKEN_STUART (5) /* STUART Unit Clock Enable */
235#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
236#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
237#define CKEN_SSP (3) /* SSP Unit Clock Enable */
238#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
239#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
240#define CKEN_PWM1 (1) /* PWM1 Clock Enable */
241#define CKEN_PWM0 (0) /* PWM0 Clock Enable */
242
243#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
244#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
245
84#endif 246#endif
diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h
index 9aa6c2e939e8..ba7e132de1b3 100644
--- a/include/asm-arm/arch-pxa/system.h
+++ b/include/asm-arm/arch-pxa/system.h
@@ -12,6 +12,7 @@
12 12
13#include <asm/proc-fns.h> 13#include <asm/proc-fns.h>
14#include "hardware.h" 14#include "hardware.h"
15#include "pxa2xx-regs.h"
15#include "pxa-regs.h" 16#include "pxa-regs.h"
16 17
17static inline void arch_idle(void) 18static inline void arch_idle(void)
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
index 4881b80f0f90..de577de8d18c 100644
--- a/include/asm-arm/arch-pxa/zylonite.h
+++ b/include/asm-arm/arch-pxa/zylonite.h
@@ -15,7 +15,6 @@ struct platform_mmc_slot {
15 15
16extern struct platform_mmc_slot zylonite_mmc_slot[]; 16extern struct platform_mmc_slot zylonite_mmc_slot[];
17 17
18extern int gpio_backlight;
19extern int gpio_eth_irq; 18extern int gpio_eth_irq;
20 19
21extern int wm9713_irq; 20extern int wm9713_irq;
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
new file mode 100644
index 000000000000..3945f803d514
--- /dev/null
+++ b/include/linux/pwm.h
@@ -0,0 +1,31 @@
1#ifndef __LINUX_PWM_H
2#define __LINUX_PWM_H
3
4struct pwm_device;
5
6/*
7 * pwm_request - request a PWM device
8 */
9struct pwm_device *pwm_request(int pwm_id, const char *label);
10
11/*
12 * pwm_free - free a PWM device
13 */
14void pwm_free(struct pwm_device *pwm);
15
16/*
17 * pwm_config - change a PWM device configuration
18 */
19int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns);
20
21/*
22 * pwm_enable - start a PWM output toggling
23 */
24int pwm_enable(struct pwm_device *pwm);
25
26/*
27 * pwm_disable - stop a PWM output toggling
28 */
29void pwm_disable(struct pwm_device *pwm);
30
31#endif /* __ASM_ARCH_PWM_H */
diff --git a/include/linux/pwm_backlight.h b/include/linux/pwm_backlight.h
new file mode 100644
index 000000000000..7a9754c96775
--- /dev/null
+++ b/include/linux/pwm_backlight.h
@@ -0,0 +1,17 @@
1/*
2 * Generic PWM backlight driver data - see drivers/video/backlight/pwm_bl.c
3 */
4#ifndef __LINUX_PWM_BACKLIGHT_H
5#define __LINUX_PWM_BACKLIGHT_H
6
7struct platform_pwm_backlight_data {
8 int pwm_id;
9 unsigned int max_brightness;
10 unsigned int dft_brightness;
11 unsigned int pwm_period_ns;
12 int (*init)(struct device *dev);
13 int (*notify)(int brightness);
14 void (*exit)(struct device *dev);
15};
16
17#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-07 22:29:18 -0500