4 files changed, 11 insertions, 11 deletions

diff --git a/arch/i386/kernel/acpi/boot.c b/arch/i386/kernel/acpi/boot.c
index 447fa9e33ffb..1f378df14f34 100644
--- a/arch/i386/kernel/acpi/boot.c
+++ b/arch/i386/kernel/acpi/boot.c
@@ -464,7 +464,7 @@ int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
  * success: return IRQ number (>=0)
  * failure: return < 0
  */
-int acpi_register_gsi(u32 gsi, int edge_level, int active_high_low)
+int acpi_register_gsi(u32 gsi, int triggering, int polarity)
 {
         unsigned int irq;
         unsigned int plat_gsi = gsi;
@@ -476,14 +476,14 @@ int acpi_register_gsi(u32 gsi, int edge_level, int active_high_low)
         if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) {
                 extern void eisa_set_level_irq(unsigned int irq);
 
-                if (edge_level == ACPI_LEVEL_SENSITIVE)
+                if (triggering == ACPI_LEVEL_SENSITIVE)
                         eisa_set_level_irq(gsi);
         }
 #endif
 
 #ifdef CONFIG_X86_IO_APIC
         if (acpi_irq_model == ACPI_IRQ_MODEL_IOAPIC) {
-                plat_gsi = mp_register_gsi(gsi, edge_level, active_high_low);
+                plat_gsi = mp_register_gsi(gsi, triggering, polarity);
         }
 #endif
         acpi_gsi_to_irq(plat_gsi, &irq);
diff --git a/arch/i386/kernel/mpparse.c b/arch/i386/kernel/mpparse.c
index 1ca5269b1e86..d7cede83ba2e 100644
--- a/arch/i386/kernel/mpparse.c
+++ b/arch/i386/kernel/mpparse.c
@@ -1070,7 +1070,7 @@ void __init mp_config_acpi_legacy_irqs (void)
 
 #define MAX_GSI_NUM     4096
 
-int mp_register_gsi (u32 gsi, int edge_level, int active_high_low)
+int mp_register_gsi (u32 gsi, int triggering, int polarity)
 {
         int                     ioapic = -1;
         int                     ioapic_pin = 0;
@@ -1119,7 +1119,7 @@ int mp_register_gsi (u32 gsi, int edge_level, int active_high_low)
 
         mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
 
-        if (edge_level) {
+        if (triggering == ACPI_LEVEL_SENSITIVE) {
                 /*
                  * For PCI devices assign IRQs in order, avoiding gaps
                  * due to unused I/O APIC pins.
@@ -1141,8 +1141,8 @@ int mp_register_gsi (u32 gsi, int edge_level, int active_high_low)
         }
 
         io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
-                    edge_level == ACPI_EDGE_SENSITIVE ? 0 : 1,
-                    active_high_low == ACPI_ACTIVE_HIGH ? 0 : 1);
+                    triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
+                    polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
         return gsi;
 }
 
diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c
index 9ad94ddf6687..d2702c419cf8 100644
--- a/arch/ia64/kernel/acpi.c
+++ b/arch/ia64/kernel/acpi.c
@@ -567,16 +567,16 @@ void __init acpi_numa_arch_fixup(void)
  * success: return IRQ number (>=0)
  * failure: return < 0
  */
-int acpi_register_gsi(u32 gsi, int edge_level, int active_high_low)
+int acpi_register_gsi(u32 gsi, int triggering, int polarity)
 {
         if (has_8259 && gsi < 16)
                 return isa_irq_to_vector(gsi);
 
         return iosapic_register_intr(gsi,
-                                     (active_high_low ==
+                                     (polarity ==
                                       ACPI_ACTIVE_HIGH) ? IOSAPIC_POL_HIGH :
                                      IOSAPIC_POL_LOW,
-                                     (edge_level ==
+                                     (triggering ==
                                       ACPI_EDGE_SENSITIVE) ? IOSAPIC_EDGE :
                                      IOSAPIC_LEVEL);
 }
diff --git a/arch/x86_64/kernel/mpparse.c b/arch/x86_64/kernel/mpparse.c
index ba817e7454b2..dc49bfb6db0a 100644
--- a/arch/x86_64/kernel/mpparse.c
+++ b/arch/x86_64/kernel/mpparse.c
@@ -964,7 +964,7 @@ int mp_register_gsi(u32 gsi, int triggering, int polarity)
 
         mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
 
-        if (triggering) {
+        if (triggering == ACPI_LEVEL_SENSITIVE) {
                 /*
                  * For PCI devices assign IRQs in order, avoiding gaps
                  * due to unused I/O APIC pins.