diff options
| -rw-r--r-- | arch/x86/kernel/cpu/intel_cacheinfo.c | 43 |
1 files changed, 38 insertions, 5 deletions
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index a61c9e399ba9..a0c6c6ffed46 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c | |||
| @@ -13,10 +13,10 @@ | |||
| 13 | #include <linux/compiler.h> | 13 | #include <linux/compiler.h> |
| 14 | #include <linux/cpu.h> | 14 | #include <linux/cpu.h> |
| 15 | #include <linux/sched.h> | 15 | #include <linux/sched.h> |
| 16 | #include <linux/pci.h> | ||
| 16 | 17 | ||
| 17 | #include <asm/processor.h> | 18 | #include <asm/processor.h> |
| 18 | #include <asm/smp.h> | 19 | #include <asm/smp.h> |
| 19 | #include <asm/k8.h> | ||
| 20 | 20 | ||
| 21 | #define LVL_1_INST 1 | 21 | #define LVL_1_INST 1 |
| 22 | #define LVL_1_DATA 2 | 22 | #define LVL_1_DATA 2 |
| @@ -135,6 +135,12 @@ struct _cpuid4_info { | |||
| 135 | cpumask_t shared_cpu_map; /* future?: only cpus/node is needed */ | 135 | cpumask_t shared_cpu_map; /* future?: only cpus/node is needed */ |
| 136 | }; | 136 | }; |
| 137 | 137 | ||
| 138 | static struct pci_device_id k8_nb_id[] = { | ||
| 139 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) }, | ||
| 140 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1203) }, | ||
| 141 | {} | ||
| 142 | }; | ||
| 143 | |||
| 138 | unsigned short num_cache_leaves; | 144 | unsigned short num_cache_leaves; |
| 139 | 145 | ||
| 140 | /* AMD doesn't have CPUID4. Emulate it here to report the same | 146 | /* AMD doesn't have CPUID4. Emulate it here to report the same |
| @@ -655,16 +661,39 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) { | |||
| 655 | #define to_object(k) container_of(k, struct _index_kobject, kobj) | 661 | #define to_object(k) container_of(k, struct _index_kobject, kobj) |
| 656 | #define to_attr(a) container_of(a, struct _cache_attr, attr) | 662 | #define to_attr(a) container_of(a, struct _cache_attr, attr) |
| 657 | 663 | ||
| 664 | static struct pci_dev *get_k8_northbridge(int node) | ||
| 665 | { | ||
| 666 | struct pci_dev *dev = NULL; | ||
| 667 | int i; | ||
| 668 | |||
| 669 | for (i = 0; i <= node; i++) { | ||
| 670 | do { | ||
| 671 | dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev); | ||
| 672 | if (!dev) | ||
| 673 | break; | ||
| 674 | } while (!pci_match_id(&k8_nb_id[0], dev)); | ||
| 675 | if (!dev) | ||
| 676 | break; | ||
| 677 | } | ||
| 678 | return dev; | ||
| 679 | } | ||
| 680 | |||
| 658 | static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf) | 681 | static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf) |
| 659 | { | 682 | { |
| 660 | int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map)); | 683 | int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map)); |
| 661 | struct pci_dev *dev = k8_northbridges[node]; | 684 | struct pci_dev *dev = NULL; |
| 662 | ssize_t ret = 0; | 685 | ssize_t ret = 0; |
| 663 | int i; | 686 | int i; |
| 664 | 687 | ||
| 665 | if (!this_leaf->can_disable) | 688 | if (!this_leaf->can_disable) |
| 666 | return sprintf(buf, "Feature not enabled\n"); | 689 | return sprintf(buf, "Feature not enabled\n"); |
| 667 | 690 | ||
| 691 | dev = get_k8_northbridge(node); | ||
| 692 | if (!dev) { | ||
| 693 | printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n"); | ||
| 694 | return -EINVAL; | ||
| 695 | } | ||
| 696 | |||
| 668 | for (i = 0; i < 2; i++) { | 697 | for (i = 0; i < 2; i++) { |
| 669 | unsigned int reg; | 698 | unsigned int reg; |
| 670 | 699 | ||
| @@ -686,14 +715,12 @@ store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf, | |||
| 686 | size_t count) | 715 | size_t count) |
| 687 | { | 716 | { |
| 688 | int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map)); | 717 | int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map)); |
| 689 | struct pci_dev *dev = k8_northbridges[node]; | 718 | struct pci_dev *dev = NULL; |
| 690 | unsigned int ret, index, val; | 719 | unsigned int ret, index, val; |
| 691 | 720 | ||
| 692 | if (!this_leaf->can_disable) | 721 | if (!this_leaf->can_disable) |
| 693 | return 0; | 722 | return 0; |
| 694 | 723 | ||
| 695 | /* write the MSR value */ | ||
| 696 | |||
| 697 | if (strlen(buf) > 15) | 724 | if (strlen(buf) > 15) |
| 698 | return -EINVAL; | 725 | return -EINVAL; |
| 699 | 726 | ||
| @@ -704,6 +731,12 @@ store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf, | |||
| 704 | return -EINVAL; | 731 | return -EINVAL; |
| 705 | 732 | ||
| 706 | val |= 0xc0000000; | 733 | val |= 0xc0000000; |
| 734 | dev = get_k8_northbridge(node); | ||
| 735 | if (!dev) { | ||
| 736 | printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n"); | ||
| 737 | return -EINVAL; | ||
| 738 | } | ||
| 739 | |||
| 707 | pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000); | 740 | pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000); |
| 708 | wbinvd(); | 741 | wbinvd(); |
| 709 | pci_write_config_dword(dev, 0x1BC + index * 4, val); | 742 | pci_write_config_dword(dev, 0x1BC + index * 4, val); |
