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-rw-r--r--drivers/media/dvb/frontends/s5h1432.c45
-rw-r--r--drivers/media/dvb/frontends/s5h1432.h43
-rw-r--r--drivers/media/video/cx231xx/cx231xx-417.c675
-rw-r--r--drivers/media/video/cx231xx/cx231xx-avcore.c135
-rw-r--r--drivers/media/video/cx231xx/cx231xx-dif.h34
-rw-r--r--drivers/media/video/cx231xx/cx231xx.h12
6 files changed, 461 insertions, 483 deletions
diff --git a/drivers/media/dvb/frontends/s5h1432.c b/drivers/media/dvb/frontends/s5h1432.c
index 5fc3bf5f1c0b..0c6dcb90d168 100644
--- a/drivers/media/dvb/frontends/s5h1432.c
+++ b/drivers/media/dvb/frontends/s5h1432.c
@@ -1,23 +1,22 @@
1/* 1/*
2 Samsung s5h1432 DVB-T demodulator driver 2 * Samsung s5h1432 DVB-T demodulator driver
3 3 *
4 Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com> 4 * Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com>
5 5 *
6 This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or 8 * the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version. 9 * (at your option) any later version.
10 10 *
11 This program is distributed in the hope that it will be useful, 11 * This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details. 14 * GNU General Public License for more details.
15 15 *
16 You should have received a copy of the GNU General Public License 16 * You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 19 */
20*/
21 20
22#include <linux/kernel.h> 21#include <linux/kernel.h>
23#include <linux/init.h> 22#include <linux/init.h>
@@ -162,7 +161,7 @@ static int s5h1432_set_IF(struct dvb_frontend *fe, u32 ifFreqHz)
162 value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 * 161 value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 *
163 (u32) 32768) / (48 * 1000)); 162 (u32) 32768) / (48 * 1000));
164 printk(KERN_INFO 163 printk(KERN_INFO
165 "Default IFFreq %d :reg value = 0x%x \n", 164 "Default IFFreq %d :reg value = 0x%x\n",
166 ifFreqHz, value); 165 ifFreqHz, value);
167 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 166 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4,
168 (u8) value & 0xFF); 167 (u8) value & 0xFF);
@@ -379,7 +378,6 @@ error:
379 kfree(state); 378 kfree(state);
380 return NULL; 379 return NULL;
381} 380}
382
383EXPORT_SYMBOL(s5h1432_attach); 381EXPORT_SYMBOL(s5h1432_attach);
384 382
385static struct dvb_frontend_ops s5h1432_ops = { 383static struct dvb_frontend_ops s5h1432_ops = {
@@ -415,8 +413,3 @@ MODULE_PARM_DESC(debug, "Enable verbose debug messages");
415MODULE_DESCRIPTION("Samsung s5h1432 DVB-T Demodulator driver"); 413MODULE_DESCRIPTION("Samsung s5h1432 DVB-T Demodulator driver");
416MODULE_AUTHOR("Bill Liu"); 414MODULE_AUTHOR("Bill Liu");
417MODULE_LICENSE("GPL"); 415MODULE_LICENSE("GPL");
418
419/*
420 * Local variables:
421 * c-basic-offset: 8
422 */
diff --git a/drivers/media/dvb/frontends/s5h1432.h b/drivers/media/dvb/frontends/s5h1432.h
index 6ed654fb9b16..b57438c32546 100644
--- a/drivers/media/dvb/frontends/s5h1432.h
+++ b/drivers/media/dvb/frontends/s5h1432.h
@@ -1,23 +1,23 @@
1/* 1/*
2 Samsung s5h1432 VSB/QAM demodulator driver 2 * Samsung s5h1432 VSB/QAM demodulator driver
3 3 *
4 Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com> 4 * Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com>
5 5 *
6 This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or 8 * the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version. 9 * (at your option) any later version.
10 10 *
11 This program is distributed in the hope that it will be useful, 11 * This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details. 14 * GNU General Public License for more details.
15 15 *
16 You should have received a copy of the GNU General Public License 16 * You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 19 *
20*/ 20 */
21 21
22#ifndef __S5H1432_H__ 22#ifndef __S5H1432_H__
23#define __S5H1432_H__ 23#define __S5H1432_H__
@@ -89,8 +89,3 @@ static inline struct dvb_frontend *s5h1432_attach(const struct s5h1432_config
89#endif /* CONFIG_DVB_s5h1432 */ 89#endif /* CONFIG_DVB_s5h1432 */
90 90
91#endif /* __s5h1432_H__ */ 91#endif /* __s5h1432_H__ */
92
93/*
94 * Local variables:
95 * c-basic-offset: 8
96 */
diff --git a/drivers/media/video/cx231xx/cx231xx-417.c b/drivers/media/video/cx231xx/cx231xx-417.c
index 6fb2d1743569..a5b1b13d1fd6 100644
--- a/drivers/media/video/cx231xx/cx231xx-417.c
+++ b/drivers/media/video/cx231xx/cx231xx-417.c
@@ -43,7 +43,7 @@
43#define CX231xx_FIRM_IMAGE_SIZE 376836 43#define CX231xx_FIRM_IMAGE_SIZE 376836
44#define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw" 44#define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
45 45
46/* for polaris ITVC*/ 46/* for polaris ITVC */
47#define ITVC_WRITE_DIR 0x03FDFC00 47#define ITVC_WRITE_DIR 0x03FDFC00
48#define ITVC_READ_DIR 0x0001FC00 48#define ITVC_READ_DIR 0x0001FC00
49 49
@@ -66,8 +66,7 @@
66 66
67#define MCI_REGISTER_MODE 0x70 67#define MCI_REGISTER_MODE 0x70
68 68
69/*Read and write modes 69/* Read and write modes for polaris ITVC */
70 for polaris ITVC*/
71#define MCI_MODE_REGISTER_READ 0x000 70#define MCI_MODE_REGISTER_READ 0x000
72#define MCI_MODE_REGISTER_WRITE 0x100 71#define MCI_MODE_REGISTER_WRITE 0x100
73#define MCI_MODE_MEMORY_READ 0x000 72#define MCI_MODE_MEMORY_READ 0x000
@@ -250,20 +249,22 @@ enum cx231xx_mute_video_shift {
250#define IVTV_REG_VPU (0x9058) 249#define IVTV_REG_VPU (0x9058)
251#define IVTV_REG_APU (0xA064) 250#define IVTV_REG_APU (0xA064)
252 251
253/**** Bit definitions for MC417_RWD and MC417_OEN registers *** 252/*
254 bits 31-16 253 * Bit definitions for MC417_RWD and MC417_OEN registers
255+-----------+ 254 *
256| Reserved | 255 * bits 31-16
257+-----------+ 256 *+-----------+
258 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 257 *| Reserved |
259+-------+-------+-------+-------+-------+-------+-------+-------+ 258 *|+-----------+
260| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0| 259 *| bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
261+-------+-------+-------+-------+-------+-------+-------+-------+ 260 *|+-------+-------+-------+-------+-------+-------+-------+-------+
262 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 261 *|| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
263+-------+-------+-------+-------+-------+-------+-------+-------+ 262 *|+-------+-------+-------+-------+-------+-------+-------+-------+
264|MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0| 263 *| bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
265+-------+-------+-------+-------+-------+-------+-------+-------+ 264 *|+-------+-------+-------+-------+-------+-------+-------+-------+
266***/ 265 *||MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
266 *|+-------+-------+-------+-------+-------+-------+-------+-------+
267 */
267#define MC417_MIWR 0x8000 268#define MC417_MIWR 0x8000
268#define MC417_MIRD 0x4000 269#define MC417_MIRD 0x4000
269#define MC417_MICS 0x2000 270#define MC417_MICS 0x2000
@@ -272,12 +273,12 @@ enum cx231xx_mute_video_shift {
272#define MC417_MIDATA 0x00FF 273#define MC417_MIDATA 0x00FF
273 274
274 275
275/*** Bit definitions for MC417_CTL register **** 276/* Bit definitions for MC417_CTL register ****
276 bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0 277 *bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0
277+--------+-------------+--------+--------------+------------+ 278 *+--------+-------------+--------+--------------+------------+
278|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN| 279 *|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
279+--------+-------------+--------+--------------+------------+ 280 *+--------+-------------+--------+--------------+------------+
280***/ 281 */
281#define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030) 282#define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030)
282#define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006) 283#define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006)
283#define MC417_UART_GPIO_EN 0x00000001 284#define MC417_UART_GPIO_EN 0x00000001
@@ -320,299 +321,294 @@ int getITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 *pValue)
320} 321}
321int waitForMciComplete(struct cx231xx *dev) 322int waitForMciComplete(struct cx231xx *dev)
322{ 323{
323 u32 gpio; 324 u32 gpio;
324 u32 gpio_driection = 0; 325 u32 gpio_driection = 0;
325 u8 count = 0; 326 u8 count = 0;
326 getITVCReg(dev, gpio_driection, &gpio); 327 getITVCReg(dev, gpio_driection, &gpio);
327 328
328 while (!(gpio&0x020000)) { 329 while (!(gpio&0x020000)) {
329 msleep(10); 330 msleep(10);
330 331
331 getITVCReg(dev, gpio_driection, &gpio); 332 getITVCReg(dev, gpio_driection, &gpio);
332 333
333 if (count++ > 100) { 334 if (count++ > 100) {
334 dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio); 335 dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio);
335 return -1; 336 return -1;
337 }
336 } 338 }
337 }
338 return 0; 339 return 0;
339} 340}
341
340int mc417_register_write(struct cx231xx *dev, u16 address, u32 value) 342int mc417_register_write(struct cx231xx *dev, u16 address, u32 value)
341{ 343{
342 u32 temp; 344 u32 temp;
343 int status = 0; 345 int status = 0;
344 346
345 temp = 0x82|MCI_REGISTER_DATA_BYTE0|((value&0x000000FF)<<8); 347 temp = 0x82|MCI_REGISTER_DATA_BYTE0|((value&0x000000FF)<<8);
346 temp = temp<<10; 348 temp = temp<<10;
347 status = setITVCReg(dev, ITVC_WRITE_DIR, temp); 349 status = setITVCReg(dev, ITVC_WRITE_DIR, temp);
348 if (status < 0) 350 if (status < 0)
349 return status; 351 return status;
350 temp = temp|((0x05)<<10); 352 temp = temp|((0x05)<<10);
351 setITVCReg(dev, ITVC_WRITE_DIR, temp); 353 setITVCReg(dev, ITVC_WRITE_DIR, temp);
352 354
353 /*write data byte 1;*/ 355 /*write data byte 1;*/
354 temp = 0x82|MCI_REGISTER_DATA_BYTE1|(value&0x0000FF00); 356 temp = 0x82|MCI_REGISTER_DATA_BYTE1|(value&0x0000FF00);
355 temp = temp<<10; 357 temp = temp<<10;
356 setITVCReg(dev, ITVC_WRITE_DIR, temp); 358 setITVCReg(dev, ITVC_WRITE_DIR, temp);
357 temp = temp|((0x05)<<10); 359 temp = temp|((0x05)<<10);
358 setITVCReg(dev, ITVC_WRITE_DIR, temp); 360 setITVCReg(dev, ITVC_WRITE_DIR, temp);
359 361
360 /*write data byte 2;*/ 362 /*write data byte 2;*/
361 temp = 0x82|MCI_REGISTER_DATA_BYTE2|((value&0x00FF0000)>>8); 363 temp = 0x82|MCI_REGISTER_DATA_BYTE2|((value&0x00FF0000)>>8);
362 temp = temp<<10; 364 temp = temp<<10;
363 setITVCReg(dev, ITVC_WRITE_DIR, temp); 365 setITVCReg(dev, ITVC_WRITE_DIR, temp);
364 temp = temp|((0x05)<<10); 366 temp = temp|((0x05)<<10);
365 setITVCReg(dev, ITVC_WRITE_DIR, temp); 367 setITVCReg(dev, ITVC_WRITE_DIR, temp);
366 368
367 /*write data byte 3;*/ 369 /*write data byte 3;*/
368 temp = 0x82|MCI_REGISTER_DATA_BYTE3|((value&0xFF000000)>>16); 370 temp = 0x82|MCI_REGISTER_DATA_BYTE3|((value&0xFF000000)>>16);
369 temp = temp<<10; 371 temp = temp<<10;
370 setITVCReg(dev, ITVC_WRITE_DIR, temp); 372 setITVCReg(dev, ITVC_WRITE_DIR, temp);
371 temp = temp|((0x05)<<10); 373 temp = temp|((0x05)<<10);
372 setITVCReg(dev, ITVC_WRITE_DIR, temp); 374 setITVCReg(dev, ITVC_WRITE_DIR, temp);
373 375
374 /*write address byte 0;*/ 376 /*write address byte 0;*/
375 temp = 0x82|MCI_REGISTER_ADDRESS_BYTE0|((address&0x000000FF)<<8); 377 temp = 0x82|MCI_REGISTER_ADDRESS_BYTE0|((address&0x000000FF)<<8);
376 temp = temp<<10; 378 temp = temp<<10;
377 setITVCReg(dev, ITVC_WRITE_DIR, temp); 379 setITVCReg(dev, ITVC_WRITE_DIR, temp);
378 temp = temp|((0x05)<<10); 380 temp = temp|((0x05)<<10);
379 setITVCReg(dev, ITVC_WRITE_DIR, temp); 381 setITVCReg(dev, ITVC_WRITE_DIR, temp);
380 382
381 /*write address byte 1;*/ 383 /*write address byte 1;*/
382 temp = 0x82|MCI_REGISTER_ADDRESS_BYTE1|(address&0x0000FF00); 384 temp = 0x82|MCI_REGISTER_ADDRESS_BYTE1|(address&0x0000FF00);
383 temp = temp<<10; 385 temp = temp<<10;
384 setITVCReg(dev, ITVC_WRITE_DIR, temp); 386 setITVCReg(dev, ITVC_WRITE_DIR, temp);
385 temp = temp|((0x05)<<10); 387 temp = temp|((0x05)<<10);
386 setITVCReg(dev, ITVC_WRITE_DIR, temp); 388 setITVCReg(dev, ITVC_WRITE_DIR, temp);
387 389
388 /*Write that the mode is write.*/ 390 /*Write that the mode is write.*/
389 temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE; 391 temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE;
390 temp = temp<<10; 392 temp = temp<<10;
391 setITVCReg(dev, ITVC_WRITE_DIR, temp); 393 setITVCReg(dev, ITVC_WRITE_DIR, temp);
392 temp = temp|((0x05)<<10); 394 temp = temp|((0x05)<<10);
393 setITVCReg(dev, ITVC_WRITE_DIR, temp); 395 setITVCReg(dev, ITVC_WRITE_DIR, temp);
394 396
395 return waitForMciComplete(dev); 397 return waitForMciComplete(dev);
396
397} 398}
398 399
399
400int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value) 400int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value)
401{ 401{
402 /*write address byte 0;*/ 402 /*write address byte 0;*/
403 u32 temp; 403 u32 temp;
404 u32 return_value = 0; 404 u32 return_value = 0;
405 int ret = 0; 405 int ret = 0;
406 406
407 temp = 0x82|MCI_REGISTER_ADDRESS_BYTE0|((address&0x00FF)<<8); 407 temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
408 temp = temp<<10; 408 temp = temp << 10;
409 setITVCReg(dev, ITVC_WRITE_DIR, temp); 409 setITVCReg(dev, ITVC_WRITE_DIR, temp);
410 temp = temp|((0x05)<<10); 410 temp = temp | ((0x05) << 10);
411 setITVCReg(dev, ITVC_WRITE_DIR, temp); 411 setITVCReg(dev, ITVC_WRITE_DIR, temp);
412 412
413 /*write address byte 1;*/ 413 /*write address byte 1;*/
414 temp = 0x82|MCI_REGISTER_ADDRESS_BYTE1|(address&0xFF00); 414 temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0xFF00);
415 temp = temp<<10; 415 temp = temp << 10;
416 setITVCReg(dev, ITVC_WRITE_DIR, temp); 416 setITVCReg(dev, ITVC_WRITE_DIR, temp);
417 temp = temp|((0x05)<<10); 417 temp = temp | ((0x05) << 10);
418 setITVCReg(dev, ITVC_WRITE_DIR, temp); 418 setITVCReg(dev, ITVC_WRITE_DIR, temp);
419 419
420 /*write that the mode is read;*/ 420 /*write that the mode is read;*/
421 temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ; 421 temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ;
422 temp = temp<<10; 422 temp = temp << 10;
423 setITVCReg(dev, ITVC_WRITE_DIR, temp); 423 setITVCReg(dev, ITVC_WRITE_DIR, temp);
424 temp = temp|((0x05)<<10); 424 temp = temp | ((0x05) << 10);
425 setITVCReg(dev, ITVC_WRITE_DIR, temp); 425 setITVCReg(dev, ITVC_WRITE_DIR, temp);
426 426
427 /*wait for the MIRDY line to be asserted , 427 /*wait for the MIRDY line to be asserted ,
428 signalling that the read is done;*/ 428 signalling that the read is done;*/
429 ret = waitForMciComplete(dev); 429 ret = waitForMciComplete(dev);
430 430
431 431 /*switch the DATA- GPIO to input mode;*/
432 /*switch the DATA- GPIO to input mode;*/ 432
433 433 /*Read data byte 0;*/
434 /*Read data byte 0;*/ 434 temp = (0x82 | MCI_REGISTER_DATA_BYTE0) << 10;
435 temp = (0x82|MCI_REGISTER_DATA_BYTE0)<<10; 435 setITVCReg(dev, ITVC_READ_DIR, temp);
436 setITVCReg(dev, ITVC_READ_DIR, temp); 436 temp = ((0x81 | MCI_REGISTER_DATA_BYTE0) << 10);
437 temp = ((0x81|MCI_REGISTER_DATA_BYTE0)<<10); 437 setITVCReg(dev, ITVC_READ_DIR, temp);
438 setITVCReg(dev, ITVC_READ_DIR, temp); 438 getITVCReg(dev, ITVC_READ_DIR, &temp);
439 getITVCReg(dev, ITVC_READ_DIR, &temp); 439 return_value |= ((temp & 0x03FC0000) >> 18);
440 return_value |= ((temp&0x03FC0000)>>18); 440 setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
441 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); 441
442 442 /* Read data byte 1;*/
443 /* Read data byte 1;*/ 443 temp = (0x82 | MCI_REGISTER_DATA_BYTE1) << 10;
444 temp = (0x82|MCI_REGISTER_DATA_BYTE1)<<10; 444 setITVCReg(dev, ITVC_READ_DIR, temp);
445 setITVCReg(dev, ITVC_READ_DIR, temp); 445 temp = ((0x81 | MCI_REGISTER_DATA_BYTE1) << 10);
446 temp = ((0x81|MCI_REGISTER_DATA_BYTE1)<<10); 446 setITVCReg(dev, ITVC_READ_DIR, temp);
447 setITVCReg(dev, ITVC_READ_DIR, temp); 447 getITVCReg(dev, ITVC_READ_DIR, &temp);
448 getITVCReg(dev, ITVC_READ_DIR, &temp); 448
449 449 return_value |= ((temp & 0x03FC0000) >> 10);
450 return_value |= ((temp&0x03FC0000)>>10); 450 setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
451 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); 451
452 452 /*Read data byte 2;*/
453 /*Read data byte 2;*/ 453 temp = (0x82 | MCI_REGISTER_DATA_BYTE2) << 10;
454 temp = (0x82|MCI_REGISTER_DATA_BYTE2)<<10; 454 setITVCReg(dev, ITVC_READ_DIR, temp);
455 setITVCReg(dev, ITVC_READ_DIR, temp); 455 temp = ((0x81 | MCI_REGISTER_DATA_BYTE2) << 10);
456 temp = ((0x81|MCI_REGISTER_DATA_BYTE2)<<10); 456 setITVCReg(dev, ITVC_READ_DIR, temp);
457 setITVCReg(dev, ITVC_READ_DIR, temp); 457 getITVCReg(dev, ITVC_READ_DIR, &temp);
458 getITVCReg(dev, ITVC_READ_DIR, &temp); 458 return_value |= ((temp & 0x03FC0000) >> 2);
459 return_value |= ((temp&0x03FC0000)>>2); 459 setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
460 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); 460
461 461 /*Read data byte 3;*/
462 /*Read data byte 3;*/ 462 temp = (0x82 | MCI_REGISTER_DATA_BYTE3) << 10;
463 temp = (0x82|MCI_REGISTER_DATA_BYTE3)<<10; 463 setITVCReg(dev, ITVC_READ_DIR, temp);
464 setITVCReg(dev, ITVC_READ_DIR, temp); 464 temp = ((0x81 | MCI_REGISTER_DATA_BYTE3) << 10);
465 temp = ((0x81|MCI_REGISTER_DATA_BYTE3)<<10); 465 setITVCReg(dev, ITVC_READ_DIR, temp);
466 setITVCReg(dev, ITVC_READ_DIR, temp); 466 getITVCReg(dev, ITVC_READ_DIR, &temp);
467 getITVCReg(dev, ITVC_READ_DIR, &temp); 467 return_value |= ((temp & 0x03FC0000) << 6);
468 return_value |= ((temp&0x03FC0000)<<6); 468 setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
469 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
470 469
471 *value = return_value; 470 *value = return_value;
472 471
473 472
474 return ret; 473 return ret;
475} 474}
476 475
477int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value) 476int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value)
478{ 477{
478 /*write data byte 0;*/
479 479
480 /*write data byte 0;*/ 480 u32 temp;
481
482 u32 temp;
483 int ret = 0; 481 int ret = 0;
484 482
485 temp = 0x82|MCI_MEMORY_DATA_BYTE0|((value&0x000000FF)<<8); 483 temp = 0x82 | MCI_MEMORY_DATA_BYTE0|((value & 0x000000FF) << 8);
486 temp = temp<<10; 484 temp = temp << 10;
487 ret = setITVCReg(dev, ITVC_WRITE_DIR, temp); 485 ret = setITVCReg(dev, ITVC_WRITE_DIR, temp);
488 if (ret < 0) 486 if (ret < 0)
489 return ret; 487 return ret;
490 temp = temp|((0x05)<<10); 488 temp = temp | ((0x05) << 10);
491 setITVCReg(dev, ITVC_WRITE_DIR, temp); 489 setITVCReg(dev, ITVC_WRITE_DIR, temp);
492 490
493 /*write data byte 1;*/ 491 /*write data byte 1;*/
494 temp = 0x82|MCI_MEMORY_DATA_BYTE1|(value&0x0000FF00); 492 temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00);
495 temp = temp<<10; 493 temp = temp << 10;
496 setITVCReg(dev, ITVC_WRITE_DIR, temp); 494 setITVCReg(dev, ITVC_WRITE_DIR, temp);
497 temp = temp|((0x05)<<10); 495 temp = temp | ((0x05) << 10);
498 setITVCReg(dev, ITVC_WRITE_DIR, temp); 496 setITVCReg(dev, ITVC_WRITE_DIR, temp);
499 497
500 /*write data byte 2;*/ 498 /*write data byte 2;*/
501 temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8); 499 temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8);
502 temp = temp<<10; 500 temp = temp<<10;
503 setITVCReg(dev, ITVC_WRITE_DIR, temp); 501 setITVCReg(dev, ITVC_WRITE_DIR, temp);
504 temp = temp|((0x05)<<10); 502 temp = temp|((0x05)<<10);
505 setITVCReg(dev, ITVC_WRITE_DIR, temp); 503 setITVCReg(dev, ITVC_WRITE_DIR, temp);
506 504
507 /*write data byte 3;*/ 505 /*write data byte 3;*/
508 temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16); 506 temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16);
509 temp = temp<<10; 507 temp = temp<<10;
510 setITVCReg(dev, ITVC_WRITE_DIR, temp); 508 setITVCReg(dev, ITVC_WRITE_DIR, temp);
511 temp = temp|((0x05)<<10); 509 temp = temp|((0x05)<<10);
512 setITVCReg(dev, ITVC_WRITE_DIR, temp); 510 setITVCReg(dev, ITVC_WRITE_DIR, temp);
513 511
514 /* write address byte 2;*/ 512 /* write address byte 2;*/
515 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE | 513 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
516 ((address & 0x003F0000)>>8); 514 ((address & 0x003F0000)>>8);
517 temp = temp<<10; 515 temp = temp<<10;
518 setITVCReg(dev, ITVC_WRITE_DIR, temp); 516 setITVCReg(dev, ITVC_WRITE_DIR, temp);
519 temp = temp|((0x05)<<10); 517 temp = temp|((0x05)<<10);
520 setITVCReg(dev, ITVC_WRITE_DIR, temp); 518 setITVCReg(dev, ITVC_WRITE_DIR, temp);
521 519
522 /* write address byte 1;*/ 520 /* write address byte 1;*/
523 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); 521 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
524 temp = temp<<10; 522 temp = temp<<10;
525 setITVCReg(dev, ITVC_WRITE_DIR, temp); 523 setITVCReg(dev, ITVC_WRITE_DIR, temp);
526 temp = temp|((0x05)<<10); 524 temp = temp|((0x05)<<10);
527 setITVCReg(dev, ITVC_WRITE_DIR, temp); 525 setITVCReg(dev, ITVC_WRITE_DIR, temp);
528 526
529 /* write address byte 0;*/ 527 /* write address byte 0;*/
530 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8); 528 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8);
531 temp = temp<<10; 529 temp = temp<<10;
532 setITVCReg(dev, ITVC_WRITE_DIR, temp); 530 setITVCReg(dev, ITVC_WRITE_DIR, temp);
533 temp = temp|((0x05)<<10); 531 temp = temp|((0x05)<<10);
534 setITVCReg(dev, ITVC_WRITE_DIR, temp); 532 setITVCReg(dev, ITVC_WRITE_DIR, temp);
535 533
536 /*wait for MIRDY line;*/ 534 /*wait for MIRDY line;*/
537 waitForMciComplete(dev); 535 waitForMciComplete(dev);
538
539return 0;
540 536
537 return 0;
541} 538}
542 539
543int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value) 540int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value)
544{ 541{
545 542 u32 temp = 0;
546 u32 temp = 0; 543 u32 return_value = 0;
547 u32 return_value = 0;
548 int ret = 0; 544 int ret = 0;
549 545
550 /*write address byte 2;*/ 546 /*write address byte 2;*/
551 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ | 547 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ |
552 ((address & 0x003F0000)>>8); 548 ((address & 0x003F0000)>>8);
553 temp = temp<<10; 549 temp = temp<<10;
554 ret = setITVCReg(dev, ITVC_WRITE_DIR, temp); 550 ret = setITVCReg(dev, ITVC_WRITE_DIR, temp);
555 if (ret < 0) 551 if (ret < 0)
556 return ret; 552 return ret;
557 temp = temp|((0x05)<<10); 553 temp = temp|((0x05)<<10);
558 setITVCReg(dev, ITVC_WRITE_DIR, temp); 554 setITVCReg(dev, ITVC_WRITE_DIR, temp);
559 555
560 /*write address byte 1*/ 556 /*write address byte 1*/
561 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); 557 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
562 temp = temp<<10; 558 temp = temp<<10;
563 setITVCReg(dev, ITVC_WRITE_DIR, temp); 559 setITVCReg(dev, ITVC_WRITE_DIR, temp);
564 temp = temp|((0x05)<<10); 560 temp = temp|((0x05)<<10);
565 setITVCReg(dev, ITVC_WRITE_DIR, temp); 561 setITVCReg(dev, ITVC_WRITE_DIR, temp);
566 562
567 /*write address byte 0*/ 563 /*write address byte 0*/
568 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF)<<8); 564 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF)<<8);
569 temp = temp<<10; 565 temp = temp<<10;
570 setITVCReg(dev, ITVC_WRITE_DIR, temp); 566 setITVCReg(dev, ITVC_WRITE_DIR, temp);
571 temp = temp|((0x05)<<10); 567 temp = temp|((0x05)<<10);
572 setITVCReg(dev, ITVC_WRITE_DIR, temp); 568 setITVCReg(dev, ITVC_WRITE_DIR, temp);
573 569
574 /*Wait for MIRDY line*/ 570 /*Wait for MIRDY line*/
575 ret = waitForMciComplete(dev); 571 ret = waitForMciComplete(dev);
576 572
577 573
578 /*Read data byte 3;*/ 574 /*Read data byte 3;*/
579 temp = (0x82|MCI_MEMORY_DATA_BYTE3)<<10; 575 temp = (0x82|MCI_MEMORY_DATA_BYTE3)<<10;
580 setITVCReg(dev, ITVC_READ_DIR, temp); 576 setITVCReg(dev, ITVC_READ_DIR, temp);
581 temp = ((0x81|MCI_MEMORY_DATA_BYTE3)<<10); 577 temp = ((0x81|MCI_MEMORY_DATA_BYTE3)<<10);
582 setITVCReg(dev, ITVC_READ_DIR, temp); 578 setITVCReg(dev, ITVC_READ_DIR, temp);
583 getITVCReg(dev, ITVC_READ_DIR, &temp); 579 getITVCReg(dev, ITVC_READ_DIR, &temp);
584 return_value |= ((temp&0x03FC0000)<<6); 580 return_value |= ((temp&0x03FC0000)<<6);
585 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); 581 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
586 582
587 /*Read data byte 2;*/ 583 /*Read data byte 2;*/
588 temp = (0x82|MCI_MEMORY_DATA_BYTE2)<<10; 584 temp = (0x82|MCI_MEMORY_DATA_BYTE2)<<10;
589 setITVCReg(dev, ITVC_READ_DIR, temp); 585 setITVCReg(dev, ITVC_READ_DIR, temp);
590 temp = ((0x81|MCI_MEMORY_DATA_BYTE2)<<10); 586 temp = ((0x81|MCI_MEMORY_DATA_BYTE2)<<10);
591 setITVCReg(dev, ITVC_READ_DIR, temp); 587 setITVCReg(dev, ITVC_READ_DIR, temp);
592 getITVCReg(dev, ITVC_READ_DIR, &temp); 588 getITVCReg(dev, ITVC_READ_DIR, &temp);
593 return_value |= ((temp&0x03FC0000)>>2); 589 return_value |= ((temp&0x03FC0000)>>2);
594 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); 590 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
595 591
596 /* Read data byte 1;*/ 592 /* Read data byte 1;*/
597 temp = (0x82|MCI_MEMORY_DATA_BYTE1)<<10; 593 temp = (0x82|MCI_MEMORY_DATA_BYTE1)<<10;
598 setITVCReg(dev, ITVC_READ_DIR, temp); 594 setITVCReg(dev, ITVC_READ_DIR, temp);
599 temp = ((0x81|MCI_MEMORY_DATA_BYTE1)<<10); 595 temp = ((0x81|MCI_MEMORY_DATA_BYTE1)<<10);
600 setITVCReg(dev, ITVC_READ_DIR, temp); 596 setITVCReg(dev, ITVC_READ_DIR, temp);
601 getITVCReg(dev, ITVC_READ_DIR, &temp); 597 getITVCReg(dev, ITVC_READ_DIR, &temp);
602 return_value |= ((temp&0x03FC0000)>>10); 598 return_value |= ((temp&0x03FC0000)>>10);
603 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); 599 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
604 600
605 /*Read data byte 0;*/ 601 /*Read data byte 0;*/
606 temp = (0x82|MCI_MEMORY_DATA_BYTE0)<<10; 602 temp = (0x82|MCI_MEMORY_DATA_BYTE0)<<10;
607 setITVCReg(dev, ITVC_READ_DIR, temp); 603 setITVCReg(dev, ITVC_READ_DIR, temp);
608 temp = ((0x81|MCI_MEMORY_DATA_BYTE0)<<10); 604 temp = ((0x81|MCI_MEMORY_DATA_BYTE0)<<10);
609 setITVCReg(dev, ITVC_READ_DIR, temp); 605 setITVCReg(dev, ITVC_READ_DIR, temp);
610 getITVCReg(dev, ITVC_READ_DIR, &temp); 606 getITVCReg(dev, ITVC_READ_DIR, &temp);
611 return_value |= ((temp&0x03FC0000)>>18); 607 return_value |= ((temp&0x03FC0000)>>18);
612 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); 608 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
613 609
614 *value = return_value; 610 *value = return_value;
615 return ret; 611 return ret;
616} 612}
617 613
618void mc417_gpio_set(struct cx231xx *dev, u32 mask) 614void mc417_gpio_set(struct cx231xx *dev, u32 mask)
@@ -884,74 +880,73 @@ void mciWriteMemoryToGPIO(struct cx231xx *dev, u32 address, u32 value,
884 u32 temp = 0; 880 u32 temp = 0;
885 int i = 0; 881 int i = 0;
886 882
887 temp = 0x82|MCI_MEMORY_DATA_BYTE0|((value&0x000000FF)<<8); 883 temp = 0x82|MCI_MEMORY_DATA_BYTE0|((value&0x000000FF)<<8);
888 temp = temp<<10; 884 temp = temp<<10;
889 *p_fw_image = temp; 885 *p_fw_image = temp;
890 p_fw_image++; 886 p_fw_image++;
891 temp = temp|((0x05)<<10); 887 temp = temp|((0x05)<<10);
892 *p_fw_image = temp; 888 *p_fw_image = temp;
893 p_fw_image++;
894
895 /*write data byte 1;*/
896 temp = 0x82|MCI_MEMORY_DATA_BYTE1|(value&0x0000FF00);
897 temp = temp<<10;
898 *p_fw_image = temp;
899 p_fw_image++;
900 temp = temp|((0x05)<<10);
901 *p_fw_image = temp;
902 p_fw_image++;
903
904 /*write data byte 2;*/
905 temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8);
906 temp = temp<<10;
907 *p_fw_image = temp;
908 p_fw_image++;
909 temp = temp|((0x05)<<10);
910 *p_fw_image = temp;
911 p_fw_image++;
912
913 /*write data byte 3;*/
914 temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16);
915 temp = temp<<10;
916 *p_fw_image = temp;
917 p_fw_image++;
918 temp = temp|((0x05)<<10);
919 *p_fw_image = temp;
920 p_fw_image++;
921
922 /* write address byte 2;*/
923 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
924 ((address & 0x003F0000)>>8);
925 temp = temp<<10;
926 *p_fw_image = temp;
927 p_fw_image++;
928 temp = temp|((0x05)<<10);
929 *p_fw_image = temp;
930 p_fw_image++;
931
932 /* write address byte 1;*/
933 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
934 temp = temp<<10;
935 *p_fw_image = temp;
936 p_fw_image++;
937 temp = temp|((0x05)<<10);
938 *p_fw_image = temp;
939 p_fw_image++;
940
941 /* write address byte 0;*/
942 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8);
943 temp = temp<<10;
944 *p_fw_image = temp;
945 p_fw_image++;
946 temp = temp|((0x05)<<10);
947 *p_fw_image = temp;
948 p_fw_image++;
949
950 for (i = 0; i < 6; i++) {
951 *p_fw_image = 0xFFFFFFFF;
952 p_fw_image++; 889 p_fw_image++;
953 }
954 890
891 /*write data byte 1;*/
892 temp = 0x82|MCI_MEMORY_DATA_BYTE1|(value&0x0000FF00);
893 temp = temp<<10;
894 *p_fw_image = temp;
895 p_fw_image++;
896 temp = temp|((0x05)<<10);
897 *p_fw_image = temp;
898 p_fw_image++;
899
900 /*write data byte 2;*/
901 temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8);
902 temp = temp<<10;
903 *p_fw_image = temp;
904 p_fw_image++;
905 temp = temp|((0x05)<<10);
906 *p_fw_image = temp;
907 p_fw_image++;
908
909 /*write data byte 3;*/
910 temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16);
911 temp = temp<<10;
912 *p_fw_image = temp;
913 p_fw_image++;
914 temp = temp|((0x05)<<10);
915 *p_fw_image = temp;
916 p_fw_image++;
917
918 /* write address byte 2;*/
919 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
920 ((address & 0x003F0000)>>8);
921 temp = temp<<10;
922 *p_fw_image = temp;
923 p_fw_image++;
924 temp = temp|((0x05)<<10);
925 *p_fw_image = temp;
926 p_fw_image++;
927
928 /* write address byte 1;*/
929 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
930 temp = temp<<10;
931 *p_fw_image = temp;
932 p_fw_image++;
933 temp = temp|((0x05)<<10);
934 *p_fw_image = temp;
935 p_fw_image++;
936
937 /* write address byte 0;*/
938 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8);
939 temp = temp<<10;
940 *p_fw_image = temp;
941 p_fw_image++;
942 temp = temp|((0x05)<<10);
943 *p_fw_image = temp;
944 p_fw_image++;
945
946 for (i = 0; i < 6; i++) {
947 *p_fw_image = 0xFFFFFFFF;
948 p_fw_image++;
949 }
955} 950}
956 951
957 952
@@ -1055,7 +1050,7 @@ static int cx231xx_load_firmware(struct cx231xx *dev)
1055 p_fw_data += 1; 1050 p_fw_data += 1;
1056 } 1051 }
1057 1052
1058/*download the firmware by ep5-out*/ 1053 /*download the firmware by ep5-out*/
1059 1054
1060 for (frame = 0; frame < (int)(CX231xx_FIRM_IMAGE_SIZE*20/_buffer_size); 1055 for (frame = 0; frame < (int)(CX231xx_FIRM_IMAGE_SIZE*20/_buffer_size);
1061 frame++) { 1056 frame++) {
@@ -2112,7 +2107,7 @@ static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
2112 .vidioc_g_std = vidioc_g_std, 2107 .vidioc_g_std = vidioc_g_std,
2113 .vidioc_enum_input = vidioc_enum_input, 2108 .vidioc_enum_input = vidioc_enum_input,
2114 .vidioc_enumaudio = vidioc_enumaudio, 2109 .vidioc_enumaudio = vidioc_enumaudio,
2115 .vidioc_g_audio = vidioc_g_audio, 2110 .vidioc_g_audio = vidioc_g_audio,
2116 .vidioc_g_input = vidioc_g_input, 2111 .vidioc_g_input = vidioc_g_input,
2117 .vidioc_s_input = vidioc_s_input, 2112 .vidioc_s_input = vidioc_s_input,
2118 .vidioc_g_tuner = vidioc_g_tuner, 2113 .vidioc_g_tuner = vidioc_g_tuner,
diff --git a/drivers/media/video/cx231xx/cx231xx-avcore.c b/drivers/media/video/cx231xx/cx231xx-avcore.c
index 2d773b31da1e..4e082435a1b1 100644
--- a/drivers/media/video/cx231xx/cx231xx-avcore.c
+++ b/drivers/media/video/cx231xx/cx231xx-avcore.c
@@ -55,7 +55,7 @@
55*******************************************************************************/ 55*******************************************************************************/
56/****************************************************************************** 56/******************************************************************************
57 * VERVE REGISTER * 57 * VERVE REGISTER *
58 * * 58 * *
59 ******************************************************************************/ 59 ******************************************************************************/
60static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data) 60static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
61{ 61{
@@ -936,11 +936,11 @@ void cx231xx_enable656(struct cx231xx *dev)
936{ 936{
937 u8 temp = 0; 937 u8 temp = 0;
938 int status; 938 int status;
939 /*enable TS1 data[0:7] as output to export 656*/ 939 /*enable TS1 data[0:7] as output to export 656*/
940 940
941 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF); 941 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
942 942
943 /*enable TS1 clock as output to export 656*/ 943 /*enable TS1 clock as output to export 656*/
944 944
945 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 945 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
946 temp = temp|0x04; 946 temp = temp|0x04;
@@ -1344,13 +1344,13 @@ void cx231xx_dump_HH_reg(struct cx231xx *dev)
1344 i = i+3; 1344 i = i+3;
1345 } 1345 }
1346 1346
1347 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1347 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1348 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 1348 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1349 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 1349 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1350 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1350 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1351 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 1351 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1352
1353} 1352}
1353
1354void cx231xx_dump_SC_reg(struct cx231xx *dev) 1354void cx231xx_dump_SC_reg(struct cx231xx *dev)
1355{ 1355{
1356 u8 value[4] = { 0, 0, 0, 0 }; 1356 u8 value[4] = { 0, 0, 0, 0 };
@@ -1455,12 +1455,12 @@ void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
1455 1455
1456 1456
1457/* 1457/*
1458 config colibri to lo-if mode 1458 config colibri to lo-if mode
1459 1459
1460 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce 1460 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce
1461 the diff IF input by half, 1461 the diff IF input by half,
1462 1462
1463 for low-if agc defect 1463 for low-if agc defect
1464*/ 1464*/
1465 1465
1466 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value); 1466 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
@@ -1535,10 +1535,9 @@ void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
1535 1535
1536u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd) 1536u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
1537{ 1537{
1538 u32 colibri_carrier_offset = 0; 1538 u32 colibri_carrier_offset = 0;
1539
1540 1539
1541 if (mode == TUNER_MODE_FM_RADIO) { 1540 if (mode == TUNER_MODE_FM_RADIO) {
1542 colibri_carrier_offset = 1100000; 1541 colibri_carrier_offset = 1100000;
1543 } else if (standerd & (V4L2_STD_NTSC | V4L2_STD_NTSC_M_JP)) { 1542 } else if (standerd & (V4L2_STD_NTSC | V4L2_STD_NTSC_M_JP)) {
1544 colibri_carrier_offset = 4832000; /*4.83MHz */ 1543 colibri_carrier_offset = 4832000; /*4.83MHz */
@@ -1549,74 +1548,70 @@ u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
1549 colibri_carrier_offset = 2100000; /*2.10MHz */ 1548 colibri_carrier_offset = 2100000; /*2.10MHz */
1550 } 1549 }
1551 1550
1552 1551 return colibri_carrier_offset;
1553 return colibri_carrier_offset;
1554} 1552}
1555 1553
1556void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq, 1554void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
1557 u8 spectral_invert, u32 mode) 1555 u8 spectral_invert, u32 mode)
1558{ 1556{
1559 1557 unsigned long pll_freq_word;
1560 unsigned long pll_freq_word; 1558 int status = 0;
1561 int status = 0; 1559 u32 dif_misc_ctrl_value = 0;
1562 u32 dif_misc_ctrl_value = 0; 1560 u64 pll_freq_u64 = 0;
1563 u64 pll_freq_u64 = 0; 1561 u32 i = 0;
1564 u32 i = 0;
1565
1566 1562
1567 cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n", 1563 cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
1568 if_freq, spectral_invert, mode); 1564 if_freq, spectral_invert, mode);
1569 1565
1570 1566
1571 if (mode == TUNER_MODE_FM_RADIO) { 1567 if (mode == TUNER_MODE_FM_RADIO) {
1572 pll_freq_word = 0x905A1CAC; 1568 pll_freq_word = 0x905A1CAC;
1573 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 1569 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1574
1575 } else /*KSPROPERTY_TUNER_MODE_TV*/{
1576 /* Calculate the PLL frequency word based on the adjusted if_freq*/
1577 pll_freq_word = if_freq;
1578 pll_freq_u64 = (u64)pll_freq_word << 28L;
1579 do_div(pll_freq_u64, 50000000);
1580 pll_freq_word = (u32)pll_freq_u64;
1581 /*pll_freq_word = 0x3463497;*/
1582 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1583
1584 if (spectral_invert) {
1585 if_freq -= 400000;
1586 /* Enable Spectral Invert*/
1587 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1588 &dif_misc_ctrl_value);
1589 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
1590 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1591 dif_misc_ctrl_value);
1592 } else {
1593 if_freq += 400000;
1594 /* Disable Spectral Invert*/
1595 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1596 &dif_misc_ctrl_value);
1597 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
1598 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1599 dif_misc_ctrl_value);
1600 }
1601 1570
1602 if_freq = (if_freq/100000)*100000; 1571 } else /*KSPROPERTY_TUNER_MODE_TV*/{
1572 /* Calculate the PLL frequency word based on the adjusted if_freq*/
1573 pll_freq_word = if_freq;
1574 pll_freq_u64 = (u64)pll_freq_word << 28L;
1575 do_div(pll_freq_u64, 50000000);
1576 pll_freq_word = (u32)pll_freq_u64;
1577 /*pll_freq_word = 0x3463497;*/
1578 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1603 1579
1604 if (if_freq < 3000000) 1580 if (spectral_invert) {
1605 if_freq = 3000000; 1581 if_freq -= 400000;
1582 /* Enable Spectral Invert*/
1583 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1584 &dif_misc_ctrl_value);
1585 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
1586 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1587 dif_misc_ctrl_value);
1588 } else {
1589 if_freq += 400000;
1590 /* Disable Spectral Invert*/
1591 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1592 &dif_misc_ctrl_value);
1593 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
1594 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1595 dif_misc_ctrl_value);
1596 }
1597
1598 if_freq = (if_freq/100000)*100000;
1606 1599
1607 if (if_freq > 16000000) 1600 if (if_freq < 3000000)
1608 if_freq = 16000000; 1601 if_freq = 3000000;
1609 }
1610 1602
1611 cx231xx_info("Enter IF=%zd\n", 1603 if (if_freq > 16000000)
1612 sizeof(Dif_set_array)/sizeof(struct dif_settings)); 1604 if_freq = 16000000;
1613 for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) {
1614 if (Dif_set_array[i].if_freq == if_freq) {
1615 status = vid_blk_write_word(dev,
1616 Dif_set_array[i].register_address, Dif_set_array[i].value);
1617 } 1605 }
1618 }
1619 1606
1607 cx231xx_info("Enter IF=%zd\n",
1608 sizeof(Dif_set_array)/sizeof(struct dif_settings));
1609 for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) {
1610 if (Dif_set_array[i].if_freq == if_freq) {
1611 status = vid_blk_write_word(dev,
1612 Dif_set_array[i].register_address, Dif_set_array[i].value);
1613 }
1614 }
1620} 1615}
1621 1616
1622/****************************************************************************** 1617/******************************************************************************
@@ -2122,8 +2117,8 @@ int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
2122{ 2117{
2123 int status = 0; 2118 int status = 0;
2124 u32 dwval; 2119 u32 dwval;
2125 cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n", 2120 cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n",
2126 dev->tuner_type); 2121 dev->tuner_type);
2127 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for 2122 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
2128 * SECAM L/B/D standards */ 2123 * SECAM L/B/D standards */
2129 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 2124 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
diff --git a/drivers/media/video/cx231xx/cx231xx-dif.h b/drivers/media/video/cx231xx/cx231xx-dif.h
index 8187afcb0145..2b63c2f6d3b0 100644
--- a/drivers/media/video/cx231xx/cx231xx-dif.h
+++ b/drivers/media/video/cx231xx/cx231xx-dif.h
@@ -1,21 +1,21 @@
1/* 1/*
2 cx231xx-dif.h - driver for Conexant Cx23100/101/102 USB video capture devices 2 * cx231xx-dif.h - driver for Conexant Cx23100/101/102 USB video capture devices
3 3 *
4 Copyright {C} 2009 <Bill.Liu@conexant.com> 4 * Copyright {C} 2009 <Bill.Liu@conexant.com>
5 5 *
6 This program is free software, you can redistribute it and/or modify 6 * This program is free software, you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
8 the Free Software Foundation, either version 2 of the License, or 8 * the Free Software Foundation, either version 2 of the License, or
9 (at your option) any later version. 9 * (at your option) any later version.
10 10 *
11 This program is distributed in the hope that it will be useful, 11 * This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY, without even the implied warranty of 12 * but WITHOUT ANY WARRANTY, without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details. 14 * GNU General Public License for more details.
15 15 *
16 You should have received a copy of the GNU General Public License 16 * You should have received a copy of the GNU General Public License
17 along with this program, if not, write to the Free Software 17 * along with this program, if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */ 19 */
20 20
21#ifndef _CX231XX_DIF_H 21#ifndef _CX231XX_DIF_H
diff --git a/drivers/media/video/cx231xx/cx231xx.h b/drivers/media/video/cx231xx/cx231xx.h
index f9cdc01a7faa..7631135b6420 100644
--- a/drivers/media/video/cx231xx/cx231xx.h
+++ b/drivers/media/video/cx231xx/cx231xx.h
@@ -56,13 +56,13 @@
56 56
57/* Boards supported by driver */ 57/* Boards supported by driver */
58#define CX231XX_BOARD_UNKNOWN 0 58#define CX231XX_BOARD_UNKNOWN 0
59#define CX231XX_BOARD_CNXT_CARRAERA 1 59#define CX231XX_BOARD_CNXT_CARRAERA 1
60#define CX231XX_BOARD_CNXT_SHELBY 2 60#define CX231XX_BOARD_CNXT_SHELBY 2
61#define CX231XX_BOARD_CNXT_RDE_253S 3 61#define CX231XX_BOARD_CNXT_RDE_253S 3
62#define CX231XX_BOARD_CNXT_RDU_253S 4 62#define CX231XX_BOARD_CNXT_RDU_253S 4
63#define CX231XX_BOARD_CNXT_VIDEO_GRABBER 5 63#define CX231XX_BOARD_CNXT_VIDEO_GRABBER 5
64#define CX231XX_BOARD_CNXT_RDE_250 6 64#define CX231XX_BOARD_CNXT_RDE_250 6
65#define CX231XX_BOARD_CNXT_RDU_250 7 65#define CX231XX_BOARD_CNXT_RDU_250 7
66#define CX231XX_BOARD_HAUPPAUGE_EXETER 8 66#define CX231XX_BOARD_HAUPPAUGE_EXETER 8
67#define CX231XX_BOARD_HAUPPAUGE_USBLIVE2 9 67#define CX231XX_BOARD_HAUPPAUGE_USBLIVE2 9
68 68
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 11:40:28 -0500