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-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear.h63
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear300.h29
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear310.h14
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear320.h32
-rw-r--r--arch/arm/mach-spear6xx/include/mach/spear.h83
5 files changed, 2 insertions, 219 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 87458020421d..df60e3004aa5 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -19,118 +19,55 @@
19#include <mach/spear320.h> 19#include <mach/spear320.h>
20 20
21#define SPEAR3XX_ML_SDRAM_BASE 0x00000000 21#define SPEAR3XX_ML_SDRAM_BASE 0x00000000
22#define SPEAR3XX_ML_SDRAM_SIZE 0x40000000
23 22
24#define SPEAR3XX_ICM9_BASE 0xC0000000 23#define SPEAR3XX_ICM9_BASE 0xC0000000
25#define SPEAR3XX_ICM9_SIZE 0x10000000
26 24
27/* ICM1 - Low speed connection */ 25/* ICM1 - Low speed connection */
28#define SPEAR3XX_ICM1_2_BASE 0xD0000000 26#define SPEAR3XX_ICM1_2_BASE 0xD0000000
29#define SPEAR3XX_ICM1_2_SIZE 0x10000000
30
31#define SPEAR3XX_ICM1_UART_BASE 0xD0000000 27#define SPEAR3XX_ICM1_UART_BASE 0xD0000000
32#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE) 28#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
33#define SPEAR3XX_ICM1_UART_SIZE 0x00080000
34
35#define SPEAR3XX_ICM1_ADC_BASE 0xD0080000 29#define SPEAR3XX_ICM1_ADC_BASE 0xD0080000
36#define SPEAR3XX_ICM1_ADC_SIZE 0x00080000
37
38#define SPEAR3XX_ICM1_SSP_BASE 0xD0100000 30#define SPEAR3XX_ICM1_SSP_BASE 0xD0100000
39#define SPEAR3XX_ICM1_SSP_SIZE 0x00080000
40
41#define SPEAR3XX_ICM1_I2C_BASE 0xD0180000 31#define SPEAR3XX_ICM1_I2C_BASE 0xD0180000
42#define SPEAR3XX_ICM1_I2C_SIZE 0x00080000
43
44#define SPEAR3XX_ICM1_JPEG_BASE 0xD0800000 32#define SPEAR3XX_ICM1_JPEG_BASE 0xD0800000
45#define SPEAR3XX_ICM1_JPEG_SIZE 0x00800000
46
47#define SPEAR3XX_ICM1_IRDA_BASE 0xD1000000 33#define SPEAR3XX_ICM1_IRDA_BASE 0xD1000000
48#define SPEAR3XX_ICM1_IRDA_SIZE 0x00080000
49
50#define SPEAR3XX_ICM1_SRAM_BASE 0xD2800000 34#define SPEAR3XX_ICM1_SRAM_BASE 0xD2800000
51#define SPEAR3XX_ICM1_SRAM_SIZE 0x05800000
52 35
53/* ICM2 - Application Subsystem */ 36/* ICM2 - Application Subsystem */
54#define SPEAR3XX_ICM2_HWACCEL0_BASE 0xD8800000 37#define SPEAR3XX_ICM2_HWACCEL0_BASE 0xD8800000
55#define SPEAR3XX_ICM2_HWACCEL0_SIZE 0x00800000
56
57#define SPEAR3XX_ICM2_HWACCEL1_BASE 0xD9000000 38#define SPEAR3XX_ICM2_HWACCEL1_BASE 0xD9000000
58#define SPEAR3XX_ICM2_HWACCEL1_SIZE 0x00800000
59 39
60/* ICM4 - High Speed Connection */ 40/* ICM4 - High Speed Connection */
61#define SPEAR3XX_ICM4_BASE 0xE0000000 41#define SPEAR3XX_ICM4_BASE 0xE0000000
62#define SPEAR3XX_ICM4_SIZE 0x08000000
63
64#define SPEAR3XX_ICM4_MII_BASE 0xE0800000 42#define SPEAR3XX_ICM4_MII_BASE 0xE0800000
65#define SPEAR3XX_ICM4_MII_SIZE 0x00800000
66
67#define SPEAR3XX_ICM4_USBD_FIFO_BASE 0xE1000000 43#define SPEAR3XX_ICM4_USBD_FIFO_BASE 0xE1000000
68#define SPEAR3XX_ICM4_USBD_FIFO_SIZE 0x00100000
69
70#define SPEAR3XX_ICM4_USBD_CSR_BASE 0xE1100000 44#define SPEAR3XX_ICM4_USBD_CSR_BASE 0xE1100000
71#define SPEAR3XX_ICM4_USBD_CSR_SIZE 0x00100000
72
73#define SPEAR3XX_ICM4_USBD_PLDT_BASE 0xE1200000 45#define SPEAR3XX_ICM4_USBD_PLDT_BASE 0xE1200000
74#define SPEAR3XX_ICM4_USBD_PLDT_SIZE 0x00100000
75
76#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE 0xE1800000 46#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE 0xE1800000
77#define SPEAR3XX_ICM4_USB_EHCI0_1_SIZE 0x00100000
78
79#define SPEAR3XX_ICM4_USB_OHCI0_BASE 0xE1900000 47#define SPEAR3XX_ICM4_USB_OHCI0_BASE 0xE1900000
80#define SPEAR3XX_ICM4_USB_OHCI0_SIZE 0x00100000
81
82#define SPEAR3XX_ICM4_USB_OHCI1_BASE 0xE2100000 48#define SPEAR3XX_ICM4_USB_OHCI1_BASE 0xE2100000
83#define SPEAR3XX_ICM4_USB_OHCI1_SIZE 0x00100000
84
85#define SPEAR3XX_ICM4_USB_ARB_BASE 0xE2800000 49#define SPEAR3XX_ICM4_USB_ARB_BASE 0xE2800000
86#define SPEAR3XX_ICM4_USB_ARB_SIZE 0x00010000
87 50
88/* ML1 - Multi Layer CPU Subsystem */ 51/* ML1 - Multi Layer CPU Subsystem */
89#define SPEAR3XX_ICM3_ML1_2_BASE 0xF0000000 52#define SPEAR3XX_ICM3_ML1_2_BASE 0xF0000000
90#define SPEAR3XX_ICM3_ML1_2_SIZE 0x0F000000
91
92#define SPEAR3XX_ML1_TMR_BASE 0xF0000000 53#define SPEAR3XX_ML1_TMR_BASE 0xF0000000
93#define SPEAR3XX_ML1_TMR_SIZE 0x00100000
94
95#define SPEAR3XX_ML1_VIC_BASE 0xF1100000 54#define SPEAR3XX_ML1_VIC_BASE 0xF1100000
96#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE) 55#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
97#define SPEAR3XX_ML1_VIC_SIZE 0x00100000
98 56
99/* ICM3 - Basic Subsystem */ 57/* ICM3 - Basic Subsystem */
100#define SPEAR3XX_ICM3_SMEM_BASE 0xF8000000 58#define SPEAR3XX_ICM3_SMEM_BASE 0xF8000000
101#define SPEAR3XX_ICM3_SMEM_SIZE 0x04000000
102
103#define SPEAR3XX_ICM3_SMI_CTRL_BASE 0xFC000000 59#define SPEAR3XX_ICM3_SMI_CTRL_BASE 0xFC000000
104#define SPEAR3XX_ICM3_SMI_CTRL_SIZE 0x00200000
105
106#define SPEAR3XX_ICM3_DMA_BASE 0xFC400000 60#define SPEAR3XX_ICM3_DMA_BASE 0xFC400000
107#define SPEAR3XX_ICM3_DMA_SIZE 0x00200000
108
109#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE 0xFC600000 61#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE 0xFC600000
110#define SPEAR3XX_ICM3_SDRAM_CTRL_SIZE 0x00200000
111
112#define SPEAR3XX_ICM3_TMR0_BASE 0xFC800000 62#define SPEAR3XX_ICM3_TMR0_BASE 0xFC800000
113#define SPEAR3XX_ICM3_TMR0_SIZE 0x00080000
114
115#define SPEAR3XX_ICM3_WDT_BASE 0xFC880000 63#define SPEAR3XX_ICM3_WDT_BASE 0xFC880000
116#define SPEAR3XX_ICM3_WDT_SIZE 0x00080000
117
118#define SPEAR3XX_ICM3_RTC_BASE 0xFC900000 64#define SPEAR3XX_ICM3_RTC_BASE 0xFC900000
119#define SPEAR3XX_ICM3_RTC_SIZE 0x00080000
120
121#define SPEAR3XX_ICM3_GPIO_BASE 0xFC980000 65#define SPEAR3XX_ICM3_GPIO_BASE 0xFC980000
122#define SPEAR3XX_ICM3_GPIO_SIZE 0x00080000
123
124#define SPEAR3XX_ICM3_SYS_CTRL_BASE 0xFCA00000 66#define SPEAR3XX_ICM3_SYS_CTRL_BASE 0xFCA00000
125#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE) 67#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
126#define SPEAR3XX_ICM3_SYS_CTRL_SIZE 0x00080000
127
128#define SPEAR3XX_ICM3_MISC_REG_BASE 0xFCA80000 68#define SPEAR3XX_ICM3_MISC_REG_BASE 0xFCA80000
129#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE) 69#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
130#define SPEAR3XX_ICM3_MISC_REG_SIZE 0x00080000
131
132#define SPEAR3XX_ICM3_TMR1_BASE 0xFCB00000 70#define SPEAR3XX_ICM3_TMR1_BASE 0xFCB00000
133#define SPEAR3XX_ICM3_TMR1_SIZE 0x00080000
134 71
135/* Debug uart for linux, will be used for debug and uncompress messages */ 72/* Debug uart for linux, will be used for debug and uncompress messages */
136#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE 73#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
index 1059d5a11874..8f96cc569591 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -18,10 +18,8 @@
18 18
19/* Base address of various IPs */ 19/* Base address of various IPs */
20#define SPEAR300_TELECOM_BASE 0x50000000 20#define SPEAR300_TELECOM_BASE 0x50000000
21#define SPEAR300_TELECOM_SIZE 0x10000000
22 21
23/* Interrupt registers offsets and masks */ 22/* Interrupt registers offsets and masks */
24#define SPEAR300_TELECOM_REG_SIZE 0x00010000
25#define INT_ENB_MASK_REG 0x54 23#define INT_ENB_MASK_REG 0x54
26#define INT_STS_MASK_REG 0x58 24#define INT_STS_MASK_REG 0x58
27#define IT_PERS_S_IRQ_MASK (1 << 0) 25#define IT_PERS_S_IRQ_MASK (1 << 0)
@@ -37,46 +35,19 @@
37#define SHIRQ_RAS1_MASK 0x1FF 35#define SHIRQ_RAS1_MASK 0x1FF
38 36
39#define SPEAR300_CLCD_BASE 0x60000000 37#define SPEAR300_CLCD_BASE 0x60000000
40#define SPEAR300_CLCD_SIZE 0x10000000
41
42#define SPEAR300_SDHCI_BASE 0x70000000 38#define SPEAR300_SDHCI_BASE 0x70000000
43#define SPEAR300_SDHCI_SIZE 0x10000000
44
45#define SPEAR300_NAND_0_BASE 0x80000000 39#define SPEAR300_NAND_0_BASE 0x80000000
46#define SPEAR300_NAND_0_SIZE 0x04000000
47
48#define SPEAR300_NAND_1_BASE 0x84000000 40#define SPEAR300_NAND_1_BASE 0x84000000
49#define SPEAR300_NAND_1_SIZE 0x04000000
50
51#define SPEAR300_NAND_2_BASE 0x88000000 41#define SPEAR300_NAND_2_BASE 0x88000000
52#define SPEAR300_NAND_2_SIZE 0x04000000
53
54#define SPEAR300_NAND_3_BASE 0x8c000000 42#define SPEAR300_NAND_3_BASE 0x8c000000
55#define SPEAR300_NAND_3_SIZE 0x04000000
56
57#define SPEAR300_NOR_0_BASE 0x90000000 43#define SPEAR300_NOR_0_BASE 0x90000000
58#define SPEAR300_NOR_0_SIZE 0x01000000
59
60#define SPEAR300_NOR_1_BASE 0x91000000 44#define SPEAR300_NOR_1_BASE 0x91000000
61#define SPEAR300_NOR_1_SIZE 0x01000000
62
63#define SPEAR300_NOR_2_BASE 0x92000000 45#define SPEAR300_NOR_2_BASE 0x92000000
64#define SPEAR300_NOR_2_SIZE 0x01000000
65
66#define SPEAR300_NOR_3_BASE 0x93000000 46#define SPEAR300_NOR_3_BASE 0x93000000
67#define SPEAR300_NOR_3_SIZE 0x01000000
68
69#define SPEAR300_FSMC_BASE 0x94000000 47#define SPEAR300_FSMC_BASE 0x94000000
70#define SPEAR300_FSMC_SIZE 0x05000000
71
72#define SPEAR300_SOC_CONFIG_BASE 0x99000000 48#define SPEAR300_SOC_CONFIG_BASE 0x99000000
73#define SPEAR300_SOC_CONFIG_SIZE 0x00000008
74
75#define SPEAR300_KEYBOARD_BASE 0xA0000000 49#define SPEAR300_KEYBOARD_BASE 0xA0000000
76#define SPEAR300_KEYBOARD_SIZE 0x09000000
77
78#define SPEAR300_GPIO_BASE 0xA9000000 50#define SPEAR300_GPIO_BASE 0xA9000000
79#define SPEAR300_GPIO_SIZE 0x07000000
80 51
81#endif /* __MACH_SPEAR300_H */ 52#endif /* __MACH_SPEAR300_H */
82 53
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
index b27bb8af3309..4f58eb12cc58 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -17,29 +17,17 @@
17#define __MACH_SPEAR310_H 17#define __MACH_SPEAR310_H
18 18
19#define SPEAR310_NAND_BASE 0x40000000 19#define SPEAR310_NAND_BASE 0x40000000
20#define SPEAR310_NAND_SIZE 0x04000000
21
22#define SPEAR310_FSMC_BASE 0x44000000 20#define SPEAR310_FSMC_BASE 0x44000000
23#define SPEAR310_FSMC_SIZE 0x01000000
24
25#define SPEAR310_UART1_BASE 0xB2000000 21#define SPEAR310_UART1_BASE 0xB2000000
26#define SPEAR310_UART2_BASE 0xB2080000 22#define SPEAR310_UART2_BASE 0xB2080000
27#define SPEAR310_UART3_BASE 0xB2100000 23#define SPEAR310_UART3_BASE 0xB2100000
28#define SPEAR310_UART4_BASE 0xB2180000 24#define SPEAR310_UART4_BASE 0xB2180000
29#define SPEAR310_UART5_BASE 0xB2200000 25#define SPEAR310_UART5_BASE 0xB2200000
30#define SPEAR310_UART_SIZE 0x00080000
31
32#define SPEAR310_HDLC_BASE 0xB2800000 26#define SPEAR310_HDLC_BASE 0xB2800000
33#define SPEAR310_HDLC_SIZE 0x00800000
34
35#define SPEAR310_RS485_0_BASE 0xB3000000 27#define SPEAR310_RS485_0_BASE 0xB3000000
36#define SPEAR310_RS485_0_SIZE 0x00800000
37
38#define SPEAR310_RS485_1_BASE 0xB3800000 28#define SPEAR310_RS485_1_BASE 0xB3800000
39#define SPEAR310_RS485_1_SIZE 0x00800000
40
41#define SPEAR310_SOC_CONFIG_BASE 0xB4000000 29#define SPEAR310_SOC_CONFIG_BASE 0xB4000000
42#define SPEAR310_SOC_CONFIG_SIZE 0x00000070 30
43/* Interrupt registers offsets and masks */ 31/* Interrupt registers offsets and masks */
44#define INT_STS_MASK_REG 0x04 32#define INT_STS_MASK_REG 0x04
45#define SMII0_IRQ_MASK (1 << 0) 33#define SMII0_IRQ_MASK (1 << 0)
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index 1c9d310c8a95..95bdb2ea312a 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -17,53 +17,23 @@
17#define __MACH_SPEAR320_H 17#define __MACH_SPEAR320_H
18 18
19#define SPEAR320_EMI_CTRL_BASE 0x40000000 19#define SPEAR320_EMI_CTRL_BASE 0x40000000
20#define SPEAR320_EMI_CTRL_SIZE 0x08000000
21
22#define SPEAR320_FSMC_BASE 0x4C000000 20#define SPEAR320_FSMC_BASE 0x4C000000
23#define SPEAR320_FSMC_SIZE 0x01000000
24
25#define SPEAR320_I2S_BASE 0x60000000 21#define SPEAR320_I2S_BASE 0x60000000
26#define SPEAR320_I2S_SIZE 0x10000000
27
28#define SPEAR320_SDHCI_BASE 0x70000000 22#define SPEAR320_SDHCI_BASE 0x70000000
29#define SPEAR320_SDHCI_SIZE 0x10000000
30
31#define SPEAR320_CLCD_BASE 0x90000000 23#define SPEAR320_CLCD_BASE 0x90000000
32#define SPEAR320_CLCD_SIZE 0x10000000
33
34#define SPEAR320_PAR_PORT_BASE 0xA0000000 24#define SPEAR320_PAR_PORT_BASE 0xA0000000
35#define SPEAR320_PAR_PORT_SIZE 0x01000000
36
37#define SPEAR320_CAN0_BASE 0xA1000000 25#define SPEAR320_CAN0_BASE 0xA1000000
38#define SPEAR320_CAN0_SIZE 0x01000000
39
40#define SPEAR320_CAN1_BASE 0xA2000000 26#define SPEAR320_CAN1_BASE 0xA2000000
41#define SPEAR320_CAN1_SIZE 0x01000000
42
43#define SPEAR320_UART1_BASE 0xA3000000 27#define SPEAR320_UART1_BASE 0xA3000000
44#define SPEAR320_UART2_BASE 0xA4000000 28#define SPEAR320_UART2_BASE 0xA4000000
45#define SPEAR320_UART_SIZE 0x01000000
46
47#define SPEAR320_SSP0_BASE 0xA5000000 29#define SPEAR320_SSP0_BASE 0xA5000000
48#define SPEAR320_SSP0_SIZE 0x01000000
49
50#define SPEAR320_SSP1_BASE 0xA6000000 30#define SPEAR320_SSP1_BASE 0xA6000000
51#define SPEAR320_SSP1_SIZE 0x01000000
52
53#define SPEAR320_I2C_BASE 0xA7000000 31#define SPEAR320_I2C_BASE 0xA7000000
54#define SPEAR320_I2C_SIZE 0x01000000
55
56#define SPEAR320_PWM_BASE 0xA8000000 32#define SPEAR320_PWM_BASE 0xA8000000
57#define SPEAR320_PWM_SIZE 0x01000000
58
59#define SPEAR320_SMII0_BASE 0xAA000000 33#define SPEAR320_SMII0_BASE 0xAA000000
60#define SPEAR320_SMII0_SIZE 0x01000000
61
62#define SPEAR320_SMII1_BASE 0xAB000000 34#define SPEAR320_SMII1_BASE 0xAB000000
63#define SPEAR320_SMII1_SIZE 0x01000000
64
65#define SPEAR320_SOC_CONFIG_BASE 0xB3000000 35#define SPEAR320_SOC_CONFIG_BASE 0xB3000000
66#define SPEAR320_SOC_CONFIG_SIZE 0x00000070 36
67/* Interrupt registers offsets and masks */ 37/* Interrupt registers offsets and masks */
68#define INT_STS_MASK_REG 0x04 38#define INT_STS_MASK_REG 0x04
69#define INT_CLR_MASK_REG 0x04 39#define INT_CLR_MASK_REG 0x04
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index 17ab5aab6b5d..c9bba39dddce 100644
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -17,149 +17,66 @@
17#include <mach/spear600.h> 17#include <mach/spear600.h>
18 18
19#define SPEAR6XX_ML_SDRAM_BASE 0x00000000 19#define SPEAR6XX_ML_SDRAM_BASE 0x00000000
20#define SPEAR6XX_ML_SDRAM_SIZE 0x40000000
21
22/* ICM1 - Low speed connection */ 20/* ICM1 - Low speed connection */
23#define SPEAR6XX_ICM1_BASE 0xD0000000 21#define SPEAR6XX_ICM1_BASE 0xD0000000
24#define SPEAR6XX_ICM1_SIZE 0x08000000
25 22
26#define SPEAR6XX_ICM1_UART0_BASE 0xD0000000 23#define SPEAR6XX_ICM1_UART0_BASE 0xD0000000
27#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE) 24#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
28#define SPEAR6XX_ICM1_UART0_SIZE 0x00080000
29 25
30#define SPEAR6XX_ICM1_UART1_BASE 0xD0080000 26#define SPEAR6XX_ICM1_UART1_BASE 0xD0080000
31#define SPEAR6XX_ICM1_UART1_SIZE 0x00080000
32
33#define SPEAR6XX_ICM1_SSP0_BASE 0xD0100000 27#define SPEAR6XX_ICM1_SSP0_BASE 0xD0100000
34#define SPEAR6XX_ICM1_SSP0_SIZE 0x00080000
35
36#define SPEAR6XX_ICM1_SSP1_BASE 0xD0180000 28#define SPEAR6XX_ICM1_SSP1_BASE 0xD0180000
37#define SPEAR6XX_ICM1_SSP1_SIZE 0x00080000
38
39#define SPEAR6XX_ICM1_I2C_BASE 0xD0200000 29#define SPEAR6XX_ICM1_I2C_BASE 0xD0200000
40#define SPEAR6XX_ICM1_I2C_SIZE 0x00080000
41
42#define SPEAR6XX_ICM1_JPEG_BASE 0xD0800000 30#define SPEAR6XX_ICM1_JPEG_BASE 0xD0800000
43#define SPEAR6XX_ICM1_JPEG_SIZE 0x00800000
44
45#define SPEAR6XX_ICM1_IRDA_BASE 0xD1000000 31#define SPEAR6XX_ICM1_IRDA_BASE 0xD1000000
46#define SPEAR6XX_ICM1_IRDA_SIZE 0x00800000
47
48#define SPEAR6XX_ICM1_FSMC_BASE 0xD1800000 32#define SPEAR6XX_ICM1_FSMC_BASE 0xD1800000
49#define SPEAR6XX_ICM1_FSMC_SIZE 0x00800000
50
51#define SPEAR6XX_ICM1_NAND_BASE 0xD2000000 33#define SPEAR6XX_ICM1_NAND_BASE 0xD2000000
52#define SPEAR6XX_ICM1_NAND_SIZE 0x00800000
53
54#define SPEAR6XX_ICM1_SRAM_BASE 0xD2800000 34#define SPEAR6XX_ICM1_SRAM_BASE 0xD2800000
55#define SPEAR6XX_ICM1_SRAM_SIZE 0x00800000
56 35
57/* ICM2 - Application Subsystem */ 36/* ICM2 - Application Subsystem */
58#define SPEAR6XX_ICM2_BASE 0xD8000000 37#define SPEAR6XX_ICM2_BASE 0xD8000000
59#define SPEAR6XX_ICM2_SIZE 0x08000000
60
61#define SPEAR6XX_ICM2_TMR0_BASE 0xD8000000 38#define SPEAR6XX_ICM2_TMR0_BASE 0xD8000000
62#define SPEAR6XX_ICM2_TMR0_SIZE 0x00080000
63
64#define SPEAR6XX_ICM2_TMR1_BASE 0xD8080000 39#define SPEAR6XX_ICM2_TMR1_BASE 0xD8080000
65#define SPEAR6XX_ICM2_TMR1_SIZE 0x00080000
66
67#define SPEAR6XX_ICM2_GPIO_BASE 0xD8100000 40#define SPEAR6XX_ICM2_GPIO_BASE 0xD8100000
68#define SPEAR6XX_ICM2_GPIO_SIZE 0x00080000
69
70#define SPEAR6XX_ICM2_SPI2_BASE 0xD8180000 41#define SPEAR6XX_ICM2_SPI2_BASE 0xD8180000
71#define SPEAR6XX_ICM2_SPI2_SIZE 0x00080000
72
73#define SPEAR6XX_ICM2_ADC_BASE 0xD8200000 42#define SPEAR6XX_ICM2_ADC_BASE 0xD8200000
74#define SPEAR6XX_ICM2_ADC_SIZE 0x00080000
75 43
76/* ML-1, 2 - Multi Layer CPU Subsystem */ 44/* ML-1, 2 - Multi Layer CPU Subsystem */
77#define SPEAR6XX_ML_CPU_BASE 0xF0000000 45#define SPEAR6XX_ML_CPU_BASE 0xF0000000
78#define SPEAR6XX_ML_CPU_SIZE 0x08000000
79
80#define SPEAR6XX_CPU_TMR_BASE 0xF0000000 46#define SPEAR6XX_CPU_TMR_BASE 0xF0000000
81#define SPEAR6XX_CPU_TMR_SIZE 0x00100000
82
83#define SPEAR6XX_CPU_GPIO_BASE 0xF0100000 47#define SPEAR6XX_CPU_GPIO_BASE 0xF0100000
84#define SPEAR6XX_CPU_GPIO_SIZE 0x00100000
85
86#define SPEAR6XX_CPU_VIC_SEC_BASE 0xF1000000 48#define SPEAR6XX_CPU_VIC_SEC_BASE 0xF1000000
87#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE) 49#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
88#define SPEAR6XX_CPU_VIC_SEC_SIZE 0x00100000
89
90#define SPEAR6XX_CPU_VIC_PRI_BASE 0xF1100000 50#define SPEAR6XX_CPU_VIC_PRI_BASE 0xF1100000
91#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE) 51#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
92#define SPEAR6XX_CPU_VIC_PRI_SIZE 0x00100000
93 52
94/* ICM3 - Basic Subsystem */ 53/* ICM3 - Basic Subsystem */
95#define SPEAR6XX_ICM3_BASE 0xF8000000 54#define SPEAR6XX_ICM3_BASE 0xF8000000
96#define SPEAR6XX_ICM3_SIZE 0x08000000
97
98#define SPEAR6XX_ICM3_SMEM_BASE 0xF8000000 55#define SPEAR6XX_ICM3_SMEM_BASE 0xF8000000
99#define SPEAR6XX_ICM3_SMEM_SIZE 0x04000000
100
101#define SPEAR6XX_ICM3_SMI_CTRL_BASE 0xFC000000 56#define SPEAR6XX_ICM3_SMI_CTRL_BASE 0xFC000000
102#define SPEAR6XX_ICM3_SMI_CTRL_SIZE 0x00200000
103
104#define SPEAR6XX_ICM3_CLCD_BASE 0xFC200000 57#define SPEAR6XX_ICM3_CLCD_BASE 0xFC200000
105#define SPEAR6XX_ICM3_CLCD_SIZE 0x00200000
106
107#define SPEAR6XX_ICM3_DMA_BASE 0xFC400000 58#define SPEAR6XX_ICM3_DMA_BASE 0xFC400000
108#define SPEAR6XX_ICM3_DMA_SIZE 0x00200000
109
110#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE 0xFC600000 59#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE 0xFC600000
111#define SPEAR6XX_ICM3_SDRAM_CTRL_SIZE 0x00200000
112
113#define SPEAR6XX_ICM3_TMR_BASE 0xFC800000 60#define SPEAR6XX_ICM3_TMR_BASE 0xFC800000
114#define SPEAR6XX_ICM3_TMR_SIZE 0x00080000
115
116#define SPEAR6XX_ICM3_WDT_BASE 0xFC880000 61#define SPEAR6XX_ICM3_WDT_BASE 0xFC880000
117#define SPEAR6XX_ICM3_WDT_SIZE 0x00080000
118
119#define SPEAR6XX_ICM3_RTC_BASE 0xFC900000 62#define SPEAR6XX_ICM3_RTC_BASE 0xFC900000
120#define SPEAR6XX_ICM3_RTC_SIZE 0x00080000
121
122#define SPEAR6XX_ICM3_GPIO_BASE 0xFC980000 63#define SPEAR6XX_ICM3_GPIO_BASE 0xFC980000
123#define SPEAR6XX_ICM3_GPIO_SIZE 0x00080000
124
125#define SPEAR6XX_ICM3_SYS_CTRL_BASE 0xFCA00000 64#define SPEAR6XX_ICM3_SYS_CTRL_BASE 0xFCA00000
126#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE) 65#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
127#define SPEAR6XX_ICM3_SYS_CTRL_SIZE 0x00080000
128
129#define SPEAR6XX_ICM3_MISC_REG_BASE 0xFCA80000 66#define SPEAR6XX_ICM3_MISC_REG_BASE 0xFCA80000
130#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE) 67#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
131#define SPEAR6XX_ICM3_MISC_REG_SIZE 0x00080000
132 68
133/* ICM4 - High Speed Connection */ 69/* ICM4 - High Speed Connection */
134#define SPEAR6XX_ICM4_BASE 0xE0000000 70#define SPEAR6XX_ICM4_BASE 0xE0000000
135#define SPEAR6XX_ICM4_SIZE 0x08000000
136
137#define SPEAR6XX_ICM4_GMAC_BASE 0xE0800000 71#define SPEAR6XX_ICM4_GMAC_BASE 0xE0800000
138#define SPEAR6XX_ICM4_GMAC_SIZE 0x00800000
139
140#define SPEAR6XX_ICM4_USBD_FIFO_BASE 0xE1000000 72#define SPEAR6XX_ICM4_USBD_FIFO_BASE 0xE1000000
141#define SPEAR6XX_ICM4_USBD_FIFO_SIZE 0x00100000
142
143#define SPEAR6XX_ICM4_USBD_CSR_BASE 0xE1100000 73#define SPEAR6XX_ICM4_USBD_CSR_BASE 0xE1100000
144#define SPEAR6XX_ICM4_USBD_CSR_SIZE 0x00100000
145
146#define SPEAR6XX_ICM4_USBD_PLDT_BASE 0xE1200000 74#define SPEAR6XX_ICM4_USBD_PLDT_BASE 0xE1200000
147#define SPEAR6XX_ICM4_USBD_PLDT_SIZE 0x00100000
148
149#define SPEAR6XX_ICM4_USB_EHCI0_BASE 0xE1800000 75#define SPEAR6XX_ICM4_USB_EHCI0_BASE 0xE1800000
150#define SPEAR6XX_ICM4_USB_EHCI0_SIZE 0x00100000
151
152#define SPEAR6XX_ICM4_USB_OHCI0_BASE 0xE1900000 76#define SPEAR6XX_ICM4_USB_OHCI0_BASE 0xE1900000
153#define SPEAR6XX_ICM4_USB_OHCI0_SIZE 0x00100000
154
155#define SPEAR6XX_ICM4_USB_EHCI1_BASE 0xE2000000 77#define SPEAR6XX_ICM4_USB_EHCI1_BASE 0xE2000000
156#define SPEAR6XX_ICM4_USB_EHCI1_SIZE 0x00100000
157
158#define SPEAR6XX_ICM4_USB_OHCI1_BASE 0xE2100000 78#define SPEAR6XX_ICM4_USB_OHCI1_BASE 0xE2100000
159#define SPEAR6XX_ICM4_USB_OHCI1_SIZE 0x00100000
160
161#define SPEAR6XX_ICM4_USB_ARB_BASE 0xE2800000 79#define SPEAR6XX_ICM4_USB_ARB_BASE 0xE2800000
162#define SPEAR6XX_ICM4_USB_ARB_SIZE 0x00010000
163 80
164/* Debug uart for linux, will be used for debug and uncompress messages */ 81/* Debug uart for linux, will be used for debug and uncompress messages */
165#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE 82#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 22:05:33 -0500