aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--Documentation/kernel-parameters.txt6
-rw-r--r--arch/ia64/Kconfig13
-rw-r--r--arch/ia64/Makefile2
-rw-r--r--arch/ia64/ia32/ia32_support.c10
-rw-r--r--arch/ia64/kernel/acpi.c10
-rw-r--r--arch/ia64/kernel/entry.S26
-rw-r--r--arch/ia64/kernel/palinfo.c6
-rw-r--r--arch/ia64/kernel/perfmon.c16
-rw-r--r--arch/ia64/kernel/process.c25
-rw-r--r--arch/ia64/kernel/sal.c11
-rw-r--r--arch/ia64/kernel/setup.c29
-rw-r--r--arch/ia64/mm/init.c25
-rw-r--r--arch/ia64/uv/Makefile12
-rw-r--r--arch/ia64/uv/kernel/Makefile13
-rw-r--r--arch/ia64/uv/kernel/machvec.c11
-rw-r--r--arch/ia64/uv/kernel/setup.c98
-rw-r--r--include/asm-ia64/machvec.h2
-rw-r--r--include/asm-ia64/machvec_uv.h26
-rw-r--r--include/asm-ia64/uv/uv_hub.h309
-rw-r--r--include/asm-ia64/uv/uv_mmrs.h266
20 files changed, 878 insertions, 38 deletions
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 7038a6da3c12..e07c432c731f 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -686,6 +686,12 @@ and is between 256 and 4096 characters. It is defined in the file
686 floppy= [HW] 686 floppy= [HW]
687 See Documentation/floppy.txt. 687 See Documentation/floppy.txt.
688 688
689 force_pal_cache_flush
690 [IA-64] Avoid check_sal_cache_flush which may hang on
691 buggy SAL_CACHE_FLUSH implementations. Using this
692 parameter will force ia64_sal_cache_flush to call
693 ia64_pal_cache_flush instead of SAL_CACHE_FLUSH.
694
689 gamecon.map[2|3]= 695 gamecon.map[2|3]=
690 [HW,JOY] Multisystem joystick and NES/SNES/PSX pad 696 [HW,JOY] Multisystem joystick and NES/SNES/PSX pad
691 support via parallel port (up to 5 devices per port) 697 support via parallel port (up to 5 devices per port)
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 0df5f6f75edf..16be41446b5b 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -135,6 +135,7 @@ config IA64_GENERIC
135 HP-zx1/sx1000 For HP systems 135 HP-zx1/sx1000 For HP systems
136 HP-zx1/sx1000+swiotlb For HP systems with (broken) DMA-constrained devices. 136 HP-zx1/sx1000+swiotlb For HP systems with (broken) DMA-constrained devices.
137 SGI-SN2 For SGI Altix systems 137 SGI-SN2 For SGI Altix systems
138 SGI-UV For SGI UV systems
138 Ski-simulator For the HP simulator <http://www.hpl.hp.com/research/linux/ski/> 139 Ski-simulator For the HP simulator <http://www.hpl.hp.com/research/linux/ski/>
139 140
140 If you don't know what to do, choose "generic". 141 If you don't know what to do, choose "generic".
@@ -170,6 +171,18 @@ config IA64_SGI_SN2
170 to select this option. If in doubt, select ia64 generic support 171 to select this option. If in doubt, select ia64 generic support
171 instead. 172 instead.
172 173
174config IA64_SGI_UV`
175 bool "SGI-UV`"
176 select NUMA
177 select ACPI_NUMA
178 select SWIOTLB
179 help
180 Selecting this option will optimize the kernel for use on UV based
181 systems, but the resulting kernel binary will not run on other
182 types of ia64 systems. If you have an SGI UV system, it's safe
183 to select this option. If in doubt, select ia64 generic support
184 instead.
185
173config IA64_HP_SIM 186config IA64_HP_SIM
174 bool "Ski-simulator" 187 bool "Ski-simulator"
175 select SWIOTLB 188 select SWIOTLB
diff --git a/arch/ia64/Makefile b/arch/ia64/Makefile
index ec4cca477f49..88f1a55c6c94 100644
--- a/arch/ia64/Makefile
+++ b/arch/ia64/Makefile
@@ -63,7 +63,7 @@ drivers-$(CONFIG_PCI) += arch/ia64/pci/
63drivers-$(CONFIG_IA64_HP_SIM) += arch/ia64/hp/sim/ 63drivers-$(CONFIG_IA64_HP_SIM) += arch/ia64/hp/sim/
64drivers-$(CONFIG_IA64_HP_ZX1) += arch/ia64/hp/common/ arch/ia64/hp/zx1/ 64drivers-$(CONFIG_IA64_HP_ZX1) += arch/ia64/hp/common/ arch/ia64/hp/zx1/
65drivers-$(CONFIG_IA64_HP_ZX1_SWIOTLB) += arch/ia64/hp/common/ arch/ia64/hp/zx1/ 65drivers-$(CONFIG_IA64_HP_ZX1_SWIOTLB) += arch/ia64/hp/common/ arch/ia64/hp/zx1/
66drivers-$(CONFIG_IA64_GENERIC) += arch/ia64/hp/common/ arch/ia64/hp/zx1/ arch/ia64/hp/sim/ arch/ia64/sn/ 66drivers-$(CONFIG_IA64_GENERIC) += arch/ia64/hp/common/ arch/ia64/hp/zx1/ arch/ia64/hp/sim/ arch/ia64/sn/ arch/ia64/uv/
67drivers-$(CONFIG_OPROFILE) += arch/ia64/oprofile/ 67drivers-$(CONFIG_OPROFILE) += arch/ia64/oprofile/
68 68
69boot := arch/ia64/hp/sim/boot 69boot := arch/ia64/hp/sim/boot
diff --git a/arch/ia64/ia32/ia32_support.c b/arch/ia64/ia32/ia32_support.c
index 896b1ebbfb26..a6965ddafc46 100644
--- a/arch/ia64/ia32/ia32_support.c
+++ b/arch/ia64/ia32/ia32_support.c
@@ -15,7 +15,6 @@
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/mm.h> 17#include <linux/mm.h>
18#include <linux/personality.h>
19#include <linux/sched.h> 18#include <linux/sched.h>
20 19
21#include <asm/intrinsics.h> 20#include <asm/intrinsics.h>
@@ -29,7 +28,6 @@
29 28
30extern int die_if_kernel (char *str, struct pt_regs *regs, long err); 29extern int die_if_kernel (char *str, struct pt_regs *regs, long err);
31 30
32struct exec_domain ia32_exec_domain;
33struct page *ia32_shared_page[NR_CPUS]; 31struct page *ia32_shared_page[NR_CPUS];
34unsigned long *ia32_boot_gdt; 32unsigned long *ia32_boot_gdt;
35unsigned long *cpu_gdt_table[NR_CPUS]; 33unsigned long *cpu_gdt_table[NR_CPUS];
@@ -240,14 +238,6 @@ ia32_cpu_init (void)
240static int __init 238static int __init
241ia32_init (void) 239ia32_init (void)
242{ 240{
243 ia32_exec_domain.name = "Linux/x86";
244 ia32_exec_domain.handler = NULL;
245 ia32_exec_domain.pers_low = PER_LINUX32;
246 ia32_exec_domain.pers_high = PER_LINUX32;
247 ia32_exec_domain.signal_map = default_exec_domain.signal_map;
248 ia32_exec_domain.signal_invmap = default_exec_domain.signal_invmap;
249 register_exec_domain(&ia32_exec_domain);
250
251#if PAGE_SHIFT > IA32_PAGE_SHIFT 241#if PAGE_SHIFT > IA32_PAGE_SHIFT
252 { 242 {
253 extern struct kmem_cache *ia64_partial_page_cachep; 243 extern struct kmem_cache *ia64_partial_page_cachep;
diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c
index 19709a079635..853d1f11be00 100644
--- a/arch/ia64/kernel/acpi.c
+++ b/arch/ia64/kernel/acpi.c
@@ -117,7 +117,10 @@ acpi_get_sysname(void)
117 if (!strcmp(hdr->oem_id, "HP")) { 117 if (!strcmp(hdr->oem_id, "HP")) {
118 return "hpzx1"; 118 return "hpzx1";
119 } else if (!strcmp(hdr->oem_id, "SGI")) { 119 } else if (!strcmp(hdr->oem_id, "SGI")) {
120 return "sn2"; 120 if (!strcmp(hdr->oem_table_id + 4, "UV"))
121 return "uv";
122 else
123 return "sn2";
121 } 124 }
122 125
123 return "dig"; 126 return "dig";
@@ -130,6 +133,8 @@ acpi_get_sysname(void)
130 return "hpzx1_swiotlb"; 133 return "hpzx1_swiotlb";
131# elif defined (CONFIG_IA64_SGI_SN2) 134# elif defined (CONFIG_IA64_SGI_SN2)
132 return "sn2"; 135 return "sn2";
136# elif defined (CONFIG_IA64_SGI_UV)
137 return "uv";
133# elif defined (CONFIG_IA64_DIG) 138# elif defined (CONFIG_IA64_DIG)
134 return "dig"; 139 return "dig";
135# else 140# else
@@ -622,6 +627,9 @@ void acpi_unregister_gsi(u32 gsi)
622 if (acpi_irq_model == ACPI_IRQ_MODEL_PLATFORM) 627 if (acpi_irq_model == ACPI_IRQ_MODEL_PLATFORM)
623 return; 628 return;
624 629
630 if (has_8259 && gsi < 16)
631 return;
632
625 iosapic_unregister_intr(gsi); 633 iosapic_unregister_intr(gsi);
626} 634}
627 635
diff --git a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S
index e49ad8c5dc69..ca2bb95726de 100644
--- a/arch/ia64/kernel/entry.S
+++ b/arch/ia64/kernel/entry.S
@@ -1156,6 +1156,9 @@ skip_rbs_switch:
1156 * r31 = current->thread_info->flags 1156 * r31 = current->thread_info->flags
1157 * On exit: 1157 * On exit:
1158 * p6 = TRUE if work-pending-check needs to be redone 1158 * p6 = TRUE if work-pending-check needs to be redone
1159 *
1160 * Interrupts are disabled on entry, reenabled depend on work, and
1161 * disabled on exit.
1159 */ 1162 */
1160.work_pending_syscall: 1163.work_pending_syscall:
1161 add r2=-8,r2 1164 add r2=-8,r2
@@ -1164,16 +1167,16 @@ skip_rbs_switch:
1164 st8 [r2]=r8 1167 st8 [r2]=r8
1165 st8 [r3]=r10 1168 st8 [r3]=r10
1166.work_pending: 1169.work_pending:
1167 tbit.z p6,p0=r31,TIF_NEED_RESCHED // current_thread_info()->need_resched==0? 1170 tbit.z p6,p0=r31,TIF_NEED_RESCHED // is resched not needed?
1168(p6) br.cond.sptk.few .notify 1171(p6) br.cond.sptk.few .notify
1169#ifdef CONFIG_PREEMPT 1172#ifdef CONFIG_PREEMPT
1170(pKStk) dep r21=-1,r0,PREEMPT_ACTIVE_BIT,1 1173(pKStk) dep r21=-1,r0,PREEMPT_ACTIVE_BIT,1
1171 ;; 1174 ;;
1172(pKStk) st4 [r20]=r21 1175(pKStk) st4 [r20]=r21
1173 ssm psr.i // enable interrupts
1174#endif 1176#endif
1177 ssm psr.i // enable interrupts
1175 br.call.spnt.many rp=schedule 1178 br.call.spnt.many rp=schedule
1176.ret9: cmp.eq p6,p0=r0,r0 // p6 <- 1 1179.ret9: cmp.eq p6,p0=r0,r0 // p6 <- 1 (re-check)
1177 rsm psr.i // disable interrupts 1180 rsm psr.i // disable interrupts
1178 ;; 1181 ;;
1179#ifdef CONFIG_PREEMPT 1182#ifdef CONFIG_PREEMPT
@@ -1182,13 +1185,13 @@ skip_rbs_switch:
1182(pKStk) st4 [r20]=r0 // preempt_count() <- 0 1185(pKStk) st4 [r20]=r0 // preempt_count() <- 0
1183#endif 1186#endif
1184(pLvSys)br.cond.sptk.few .work_pending_syscall_end 1187(pLvSys)br.cond.sptk.few .work_pending_syscall_end
1185 br.cond.sptk.many .work_processed_kernel // re-check 1188 br.cond.sptk.many .work_processed_kernel
1186 1189
1187.notify: 1190.notify:
1188(pUStk) br.call.spnt.many rp=notify_resume_user 1191(pUStk) br.call.spnt.many rp=notify_resume_user
1189.ret10: cmp.ne p6,p0=r0,r0 // p6 <- 0 1192.ret10: cmp.ne p6,p0=r0,r0 // p6 <- 0 (don't re-check)
1190(pLvSys)br.cond.sptk.few .work_pending_syscall_end 1193(pLvSys)br.cond.sptk.few .work_pending_syscall_end
1191 br.cond.sptk.many .work_processed_kernel // don't re-check 1194 br.cond.sptk.many .work_processed_kernel
1192 1195
1193.work_pending_syscall_end: 1196.work_pending_syscall_end:
1194 adds r2=PT(R8)+16,r12 1197 adds r2=PT(R8)+16,r12
@@ -1196,7 +1199,7 @@ skip_rbs_switch:
1196 ;; 1199 ;;
1197 ld8 r8=[r2] 1200 ld8 r8=[r2]
1198 ld8 r10=[r3] 1201 ld8 r10=[r3]
1199 br.cond.sptk.many .work_processed_syscall // re-check 1202 br.cond.sptk.many .work_processed_syscall
1200 1203
1201END(ia64_leave_kernel) 1204END(ia64_leave_kernel)
1202 1205
@@ -1234,9 +1237,12 @@ GLOBAL_ENTRY(ia64_invoke_schedule_tail)
1234END(ia64_invoke_schedule_tail) 1237END(ia64_invoke_schedule_tail)
1235 1238
1236 /* 1239 /*
1237 * Setup stack and call do_notify_resume_user(). Note that pSys and pNonSys need to 1240 * Setup stack and call do_notify_resume_user(), keeping interrupts
1238 * be set up by the caller. We declare 8 input registers so the system call 1241 * disabled.
1239 * args get preserved, in case we need to restart a system call. 1242 *
1243 * Note that pSys and pNonSys need to be set up by the caller.
1244 * We declare 8 input registers so the system call args get preserved,
1245 * in case we need to restart a system call.
1240 */ 1246 */
1241ENTRY(notify_resume_user) 1247ENTRY(notify_resume_user)
1242 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8) 1248 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
diff --git a/arch/ia64/kernel/palinfo.c b/arch/ia64/kernel/palinfo.c
index 4547a2092af9..9dc00f7fe10e 100644
--- a/arch/ia64/kernel/palinfo.c
+++ b/arch/ia64/kernel/palinfo.c
@@ -900,12 +900,6 @@ static void
900palinfo_smp_call(void *info) 900palinfo_smp_call(void *info)
901{ 901{
902 palinfo_smp_data_t *data = (palinfo_smp_data_t *)info; 902 palinfo_smp_data_t *data = (palinfo_smp_data_t *)info;
903 if (data == NULL) {
904 printk(KERN_ERR "palinfo: data pointer is NULL\n");
905 data->ret = 0; /* no output */
906 return;
907 }
908 /* does this actual call */
909 data->ret = (*data->func)(data->page); 903 data->ret = (*data->func)(data->page);
910} 904}
911 905
diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
index c1ad27de2dd2..71d05133f556 100644
--- a/arch/ia64/kernel/perfmon.c
+++ b/arch/ia64/kernel/perfmon.c
@@ -5013,12 +5013,13 @@ pfm_context_force_terminate(pfm_context_t *ctx, struct pt_regs *regs)
5013} 5013}
5014 5014
5015static int pfm_ovfl_notify_user(pfm_context_t *ctx, unsigned long ovfl_pmds); 5015static int pfm_ovfl_notify_user(pfm_context_t *ctx, unsigned long ovfl_pmds);
5016
5016 /* 5017 /*
5017 * pfm_handle_work() can be called with interrupts enabled 5018 * pfm_handle_work() can be called with interrupts enabled
5018 * (TIF_NEED_RESCHED) or disabled. The down_interruptible 5019 * (TIF_NEED_RESCHED) or disabled. The down_interruptible
5019 * call may sleep, therefore we must re-enable interrupts 5020 * call may sleep, therefore we must re-enable interrupts
5020 * to avoid deadlocks. It is safe to do so because this function 5021 * to avoid deadlocks. It is safe to do so because this function
5021 * is called ONLY when returning to user level (PUStk=1), in which case 5022 * is called ONLY when returning to user level (pUStk=1), in which case
5022 * there is no risk of kernel stack overflow due to deep 5023 * there is no risk of kernel stack overflow due to deep
5023 * interrupt nesting. 5024 * interrupt nesting.
5024 */ 5025 */
@@ -5034,7 +5035,8 @@ pfm_handle_work(void)
5034 5035
5035 ctx = PFM_GET_CTX(current); 5036 ctx = PFM_GET_CTX(current);
5036 if (ctx == NULL) { 5037 if (ctx == NULL) {
5037 printk(KERN_ERR "perfmon: [%d] has no PFM context\n", task_pid_nr(current)); 5038 printk(KERN_ERR "perfmon: [%d] has no PFM context\n",
5039 task_pid_nr(current));
5038 return; 5040 return;
5039 } 5041 }
5040 5042
@@ -5058,11 +5060,12 @@ pfm_handle_work(void)
5058 /* 5060 /*
5059 * must be done before we check for simple-reset mode 5061 * must be done before we check for simple-reset mode
5060 */ 5062 */
5061 if (ctx->ctx_fl_going_zombie || ctx->ctx_state == PFM_CTX_ZOMBIE) goto do_zombie; 5063 if (ctx->ctx_fl_going_zombie || ctx->ctx_state == PFM_CTX_ZOMBIE)
5062 5064 goto do_zombie;
5063 5065
5064 //if (CTX_OVFL_NOBLOCK(ctx)) goto skip_blocking; 5066 //if (CTX_OVFL_NOBLOCK(ctx)) goto skip_blocking;
5065 if (reason == PFM_TRAP_REASON_RESET) goto skip_blocking; 5067 if (reason == PFM_TRAP_REASON_RESET)
5068 goto skip_blocking;
5066 5069
5067 /* 5070 /*
5068 * restore interrupt mask to what it was on entry. 5071 * restore interrupt mask to what it was on entry.
@@ -5110,7 +5113,8 @@ do_zombie:
5110 /* 5113 /*
5111 * in case of interruption of down() we don't restart anything 5114 * in case of interruption of down() we don't restart anything
5112 */ 5115 */
5113 if (ret < 0) goto nothing_to_do; 5116 if (ret < 0)
5117 goto nothing_to_do;
5114 5118
5115skip_blocking: 5119skip_blocking:
5116 pfm_resume_after_ovfl(ctx, ovfl_regs, regs); 5120 pfm_resume_after_ovfl(ctx, ovfl_regs, regs);
diff --git a/arch/ia64/kernel/process.c b/arch/ia64/kernel/process.c
index 58dcfac5ea88..a3a34b4eb038 100644
--- a/arch/ia64/kernel/process.c
+++ b/arch/ia64/kernel/process.c
@@ -167,11 +167,18 @@ void tsk_clear_notify_resume(struct task_struct *tsk)
167 clear_ti_thread_flag(task_thread_info(tsk), TIF_NOTIFY_RESUME); 167 clear_ti_thread_flag(task_thread_info(tsk), TIF_NOTIFY_RESUME);
168} 168}
169 169
170/*
171 * do_notify_resume_user():
172 * Called from notify_resume_user at entry.S, with interrupts disabled.
173 */
170void 174void
171do_notify_resume_user (sigset_t *unused, struct sigscratch *scr, long in_syscall) 175do_notify_resume_user(sigset_t *unused, struct sigscratch *scr, long in_syscall)
172{ 176{
173 if (fsys_mode(current, &scr->pt)) { 177 if (fsys_mode(current, &scr->pt)) {
174 /* defer signal-handling etc. until we return to privilege-level 0. */ 178 /*
179 * defer signal-handling etc. until we return to
180 * privilege-level 0.
181 */
175 if (!ia64_psr(&scr->pt)->lp) 182 if (!ia64_psr(&scr->pt)->lp)
176 ia64_psr(&scr->pt)->lp = 1; 183 ia64_psr(&scr->pt)->lp = 1;
177 return; 184 return;
@@ -179,16 +186,26 @@ do_notify_resume_user (sigset_t *unused, struct sigscratch *scr, long in_syscall
179 186
180#ifdef CONFIG_PERFMON 187#ifdef CONFIG_PERFMON
181 if (current->thread.pfm_needs_checking) 188 if (current->thread.pfm_needs_checking)
189 /*
190 * Note: pfm_handle_work() allow us to call it with interrupts
191 * disabled, and may enable interrupts within the function.
192 */
182 pfm_handle_work(); 193 pfm_handle_work();
183#endif 194#endif
184 195
185 /* deal with pending signal delivery */ 196 /* deal with pending signal delivery */
186 if (test_thread_flag(TIF_SIGPENDING)) 197 if (test_thread_flag(TIF_SIGPENDING)) {
198 local_irq_enable(); /* force interrupt enable */
187 ia64_do_signal(scr, in_syscall); 199 ia64_do_signal(scr, in_syscall);
200 }
188 201
189 /* copy user rbs to kernel rbs */ 202 /* copy user rbs to kernel rbs */
190 if (unlikely(test_thread_flag(TIF_RESTORE_RSE))) 203 if (unlikely(test_thread_flag(TIF_RESTORE_RSE))) {
204 local_irq_enable(); /* force interrupt enable */
191 ia64_sync_krbs(); 205 ia64_sync_krbs();
206 }
207
208 local_irq_disable(); /* force interrupt disable */
192} 209}
193 210
194static int pal_halt = 1; 211static int pal_halt = 1;
diff --git a/arch/ia64/kernel/sal.c b/arch/ia64/kernel/sal.c
index a3022dc48ef8..7e0259709c04 100644
--- a/arch/ia64/kernel/sal.c
+++ b/arch/ia64/kernel/sal.c
@@ -229,6 +229,14 @@ static void __init sal_desc_ap_wakeup(void *p) { }
229 */ 229 */
230static int sal_cache_flush_drops_interrupts; 230static int sal_cache_flush_drops_interrupts;
231 231
232static int __init
233force_pal_cache_flush(char *str)
234{
235 sal_cache_flush_drops_interrupts = 1;
236 return 0;
237}
238early_param("force_pal_cache_flush", force_pal_cache_flush);
239
232void __init 240void __init
233check_sal_cache_flush (void) 241check_sal_cache_flush (void)
234{ 242{
@@ -237,6 +245,9 @@ check_sal_cache_flush (void)
237 u64 vector, cache_type = 3; 245 u64 vector, cache_type = 3;
238 struct ia64_sal_retval isrv; 246 struct ia64_sal_retval isrv;
239 247
248 if (sal_cache_flush_drops_interrupts)
249 return;
250
240 cpu = get_cpu(); 251 cpu = get_cpu();
241 local_irq_save(flags); 252 local_irq_save(flags);
242 253
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
index 5015ca1275ca..e9596cd0cdab 100644
--- a/arch/ia64/kernel/setup.c
+++ b/arch/ia64/kernel/setup.c
@@ -239,6 +239,25 @@ __initcall(register_memory);
239 239
240 240
241#ifdef CONFIG_KEXEC 241#ifdef CONFIG_KEXEC
242
243/*
244 * This function checks if the reserved crashkernel is allowed on the specific
245 * IA64 machine flavour. Machines without an IO TLB use swiotlb and require
246 * some memory below 4 GB (i.e. in 32 bit area), see the implementation of
247 * lib/swiotlb.c. The hpzx1 architecture has an IO TLB but cannot use that
248 * in kdump case. See the comment in sba_init() in sba_iommu.c.
249 *
250 * So, the only machvec that really supports loading the kdump kernel
251 * over 4 GB is "sn2".
252 */
253static int __init check_crashkernel_memory(unsigned long pbase, size_t size)
254{
255 if (ia64_platform_is("sn2") || ia64_platform_is("uv"))
256 return 1;
257 else
258 return pbase < (1UL << 32);
259}
260
242static void __init setup_crashkernel(unsigned long total, int *n) 261static void __init setup_crashkernel(unsigned long total, int *n)
243{ 262{
244 unsigned long long base = 0, size = 0; 263 unsigned long long base = 0, size = 0;
@@ -252,6 +271,16 @@ static void __init setup_crashkernel(unsigned long total, int *n)
252 base = kdump_find_rsvd_region(size, 271 base = kdump_find_rsvd_region(size,
253 rsvd_region, *n); 272 rsvd_region, *n);
254 } 273 }
274
275 if (!check_crashkernel_memory(base, size)) {
276 pr_warning("crashkernel: There would be kdump memory "
277 "at %ld GB but this is unusable because it "
278 "must\nbe below 4 GB. Change the memory "
279 "configuration of the machine.\n",
280 (unsigned long)(base >> 30));
281 return;
282 }
283
255 if (base != ~0UL) { 284 if (base != ~0UL) {
256 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " 285 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
257 "for crashkernel (System RAM: %ldMB)\n", 286 "for crashkernel (System RAM: %ldMB)\n",
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
index fc6c6636ffda..200100ea7610 100644
--- a/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@ -719,3 +719,28 @@ out:
719EXPORT_SYMBOL_GPL(remove_memory); 719EXPORT_SYMBOL_GPL(remove_memory);
720#endif /* CONFIG_MEMORY_HOTREMOVE */ 720#endif /* CONFIG_MEMORY_HOTREMOVE */
721#endif 721#endif
722
723/*
724 * Even when CONFIG_IA32_SUPPORT is not enabled it is
725 * useful to have the Linux/x86 domain registered to
726 * avoid an attempted module load when emulators call
727 * personality(PER_LINUX32). This saves several milliseconds
728 * on each such call.
729 */
730static struct exec_domain ia32_exec_domain;
731
732static int __init
733per_linux32_init(void)
734{
735 ia32_exec_domain.name = "Linux/x86";
736 ia32_exec_domain.handler = NULL;
737 ia32_exec_domain.pers_low = PER_LINUX32;
738 ia32_exec_domain.pers_high = PER_LINUX32;
739 ia32_exec_domain.signal_map = default_exec_domain.signal_map;
740 ia32_exec_domain.signal_invmap = default_exec_domain.signal_invmap;
741 register_exec_domain(&ia32_exec_domain);
742
743 return 0;
744}
745
746__initcall(per_linux32_init);
diff --git a/arch/ia64/uv/Makefile b/arch/ia64/uv/Makefile
new file mode 100644
index 000000000000..aa9f91947c49
--- /dev/null
+++ b/arch/ia64/uv/Makefile
@@ -0,0 +1,12 @@
1# arch/ia64/uv/Makefile
2#
3# This file is subject to the terms and conditions of the GNU General Public
4# License. See the file "COPYING" in the main directory of this archive
5# for more details.
6#
7# Copyright (C) 2008 Silicon Graphics, Inc. All Rights Reserved.
8#
9# Makefile for the sn uv subplatform
10#
11
12obj-y += kernel/
diff --git a/arch/ia64/uv/kernel/Makefile b/arch/ia64/uv/kernel/Makefile
new file mode 100644
index 000000000000..8d92b4684d8e
--- /dev/null
+++ b/arch/ia64/uv/kernel/Makefile
@@ -0,0 +1,13 @@
1# arch/ia64/uv/kernel/Makefile
2#
3# This file is subject to the terms and conditions of the GNU General Public
4# License. See the file "COPYING" in the main directory of this archive
5# for more details.
6#
7# Copyright (C) 2008 Silicon Graphics, Inc. All Rights Reserved.
8#
9
10EXTRA_CFLAGS += -Iarch/ia64/sn/include
11
12obj-y += setup.o
13obj-$(CONFIG_IA64_GENERIC) += machvec.o
diff --git a/arch/ia64/uv/kernel/machvec.c b/arch/ia64/uv/kernel/machvec.c
new file mode 100644
index 000000000000..50737a9dca74
--- /dev/null
+++ b/arch/ia64/uv/kernel/machvec.c
@@ -0,0 +1,11 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
7 */
8
9#define MACHVEC_PLATFORM_NAME uv
10#define MACHVEC_PLATFORM_HEADER <asm/machvec_uv.h>
11#include <asm/machvec_init.h>
diff --git a/arch/ia64/uv/kernel/setup.c b/arch/ia64/uv/kernel/setup.c
new file mode 100644
index 000000000000..9aa743203c3c
--- /dev/null
+++ b/arch/ia64/uv/kernel/setup.c
@@ -0,0 +1,98 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV Core Functions
7 *
8 * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#include <linux/module.h>
12#include <linux/percpu.h>
13#include <asm/sn/simulator.h>
14#include <asm/uv/uv_mmrs.h>
15#include <asm/uv/uv_hub.h>
16
17DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
18EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
19
20
21struct redir_addr {
22 unsigned long redirect;
23 unsigned long alias;
24};
25
26#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
27
28static __initdata struct redir_addr redir_addrs[] = {
29 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
30 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
31 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
32};
33
34static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
35{
36 union uvh_si_alias0_overlay_config_u alias;
37 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
38 int i;
39
40 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
41 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
42 if (alias.s.base == 0) {
43 *size = (1UL << alias.s.m_alias);
44 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
45 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
46 return;
47 }
48 }
49 BUG();
50}
51
52void __init uv_setup(char **cmdline_p)
53{
54 union uvh_si_addr_map_config_u m_n_config;
55 union uvh_node_id_u node_id;
56 unsigned long gnode_upper;
57 int nid, cpu, m_val, n_val;
58 unsigned long mmr_base, lowmem_redir_base, lowmem_redir_size;
59
60 if (IS_MEDUSA()) {
61 lowmem_redir_base = 0;
62 lowmem_redir_size = 0;
63 node_id.v = 0;
64 m_n_config.s.m_skt = 37;
65 m_n_config.s.n_skt = 0;
66 mmr_base = 0;
67 } else {
68 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
69 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
70 m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
71 mmr_base =
72 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
73 ~UV_MMR_ENABLE;
74 }
75
76 m_val = m_n_config.s.m_skt;
77 n_val = m_n_config.s.n_skt;
78 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
79
80 gnode_upper = (((unsigned long)node_id.s.node_id) &
81 ~((1 << n_val) - 1)) << m_val;
82
83 for_each_present_cpu(cpu) {
84 nid = cpu_to_node(cpu);
85 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
86 uv_cpu_hub_info(cpu)->lowmem_remap_top =
87 lowmem_redir_base + lowmem_redir_size;
88 uv_cpu_hub_info(cpu)->m_val = m_val;
89 uv_cpu_hub_info(cpu)->n_val = m_val;
90 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) -1;
91 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
92 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
93 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
94 uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
95 printk(KERN_DEBUG "UV cpu %d, nid %d\n", cpu, nid);
96 }
97}
98
diff --git a/include/asm-ia64/machvec.h b/include/asm-ia64/machvec.h
index 9f020eb825c5..0721a5e8271e 100644
--- a/include/asm-ia64/machvec.h
+++ b/include/asm-ia64/machvec.h
@@ -126,6 +126,8 @@ extern void machvec_tlb_migrate_finish (struct mm_struct *);
126# include <asm/machvec_hpzx1_swiotlb.h> 126# include <asm/machvec_hpzx1_swiotlb.h>
127# elif defined (CONFIG_IA64_SGI_SN2) 127# elif defined (CONFIG_IA64_SGI_SN2)
128# include <asm/machvec_sn2.h> 128# include <asm/machvec_sn2.h>
129# elif defined (CONFIG_IA64_SGI_UV)
130# include <asm/machvec_uv.h>
129# elif defined (CONFIG_IA64_GENERIC) 131# elif defined (CONFIG_IA64_GENERIC)
130 132
131# ifdef MACHVEC_PLATFORM_HEADER 133# ifdef MACHVEC_PLATFORM_HEADER
diff --git a/include/asm-ia64/machvec_uv.h b/include/asm-ia64/machvec_uv.h
new file mode 100644
index 000000000000..2931447f3813
--- /dev/null
+++ b/include/asm-ia64/machvec_uv.h
@@ -0,0 +1,26 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV Core Functions
7 *
8 * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef _ASM_IA64_MACHVEC_UV_H
12#define _ASM_IA64_MACHVEC_UV_H
13
14extern ia64_mv_setup_t uv_setup;
15
16/*
17 * This stuff has dual use!
18 *
19 * For a generic kernel, the macros are used to initialize the
20 * platform's machvec structure. When compiling a non-generic kernel,
21 * the macros are used directly.
22 */
23#define platform_name "uv"
24#define platform_setup uv_setup
25
26#endif /* _ASM_IA64_MACHVEC_UV_H */
diff --git a/include/asm-ia64/uv/uv_hub.h b/include/asm-ia64/uv/uv_hub.h
new file mode 100644
index 000000000000..f607018af4a1
--- /dev/null
+++ b/include/asm-ia64/uv/uv_hub.h
@@ -0,0 +1,309 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV architectural definitions
7 *
8 * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef __ASM_IA64_UV_HUB_H__
12#define __ASM_IA64_UV_HUB_H__
13
14#include <linux/numa.h>
15#include <linux/percpu.h>
16#include <asm/types.h>
17#include <asm/percpu.h>
18
19
20/*
21 * Addressing Terminology
22 *
23 * M - The low M bits of a physical address represent the offset
24 * into the blade local memory. RAM memory on a blade is physically
25 * contiguous (although various IO spaces may punch holes in
26 * it)..
27 *
28 * N - Number of bits in the node portion of a socket physical
29 * address.
30 *
31 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
32 * routers always have low bit of 1, C/MBricks have low bit
33 * equal to 0. Most addressing macros that target UV hub chips
34 * right shift the NASID by 1 to exclude the always-zero bit.
35 * NASIDs contain up to 15 bits.
36 *
37 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
38 * of nasids.
39 *
40 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
41 * of the nasid for socket usage.
42 *
43 *
44 * NumaLink Global Physical Address Format:
45 * +--------------------------------+---------------------+
46 * |00..000| GNODE | NodeOffset |
47 * +--------------------------------+---------------------+
48 * |<-------53 - M bits --->|<--------M bits ----->
49 *
50 * M - number of node offset bits (35 .. 40)
51 *
52 *
53 * Memory/UV-HUB Processor Socket Address Format:
54 * +----------------+---------------+---------------------+
55 * |00..000000000000| PNODE | NodeOffset |
56 * +----------------+---------------+---------------------+
57 * <--- N bits --->|<--------M bits ----->
58 *
59 * M - number of node offset bits (35 .. 40)
60 * N - number of PNODE bits (0 .. 10)
61 *
62 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
63 * The actual values are configuration dependent and are set at
64 * boot time. M & N values are set by the hardware/BIOS at boot.
65 */
66
67
68/*
69 * Maximum number of bricks in all partitions and in all coherency domains.
70 * This is the total number of bricks accessible in the numalink fabric. It
71 * includes all C & M bricks. Routers are NOT included.
72 *
73 * This value is also the value of the maximum number of non-router NASIDs
74 * in the numalink fabric.
75 *
76 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
77 */
78#define UV_MAX_NUMALINK_BLADES 16384
79
80/*
81 * Maximum number of C/Mbricks within a software SSI (hardware may support
82 * more).
83 */
84#define UV_MAX_SSI_BLADES 1
85
86/*
87 * The largest possible NASID of a C or M brick (+ 2)
88 */
89#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2)
90
91/*
92 * The following defines attributes of the HUB chip. These attributes are
93 * frequently referenced and are kept in the per-cpu data areas of each cpu.
94 * They are kept together in a struct to minimize cache misses.
95 */
96struct uv_hub_info_s {
97 unsigned long global_mmr_base;
98 unsigned long gpa_mask;
99 unsigned long gnode_upper;
100 unsigned long lowmem_remap_top;
101 unsigned long lowmem_remap_base;
102 unsigned short pnode;
103 unsigned short pnode_mask;
104 unsigned short coherency_domain_number;
105 unsigned short numa_blade_id;
106 unsigned char blade_processor_id;
107 unsigned char m_val;
108 unsigned char n_val;
109};
110DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
111#define uv_hub_info (&__get_cpu_var(__uv_hub_info))
112#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
113
114/*
115 * Local & Global MMR space macros.
116 * Note: macros are intended to be used ONLY by inline functions
117 * in this file - not by other kernel code.
118 * n - NASID (full 15-bit global nasid)
119 * g - GNODE (full 15-bit global nasid, right shifted 1)
120 * p - PNODE (local part of nsids, right shifted 1)
121 */
122#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
123#define UV_PNODE_TO_NASID(p) (((p) << 1) | uv_hub_info->gnode_upper)
124
125#define UV_LOCAL_MMR_BASE 0xf4000000UL
126#define UV_GLOBAL_MMR32_BASE 0xf8000000UL
127#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
128
129#define UV_GLOBAL_MMR32_PNODE_SHIFT 15
130#define UV_GLOBAL_MMR64_PNODE_SHIFT 26
131
132#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
133
134#define UV_GLOBAL_MMR64_PNODE_BITS(p) \
135 ((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)
136
137/*
138 * Macros for converting between kernel virtual addresses, socket local physical
139 * addresses, and UV global physical addresses.
140 * Note: use the standard __pa() & __va() macros for converting
141 * between socket virtual and socket physical addresses.
142 */
143
144/* socket phys RAM --> UV global physical address */
145static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
146{
147 if (paddr < uv_hub_info->lowmem_remap_top)
148 paddr += uv_hub_info->lowmem_remap_base;
149 return paddr | uv_hub_info->gnode_upper;
150}
151
152
153/* socket virtual --> UV global physical address */
154static inline unsigned long uv_gpa(void *v)
155{
156 return __pa(v) | uv_hub_info->gnode_upper;
157}
158
159/* socket virtual --> UV global physical address */
160static inline void *uv_vgpa(void *v)
161{
162 return (void *)uv_gpa(v);
163}
164
165/* UV global physical address --> socket virtual */
166static inline void *uv_va(unsigned long gpa)
167{
168 return __va(gpa & uv_hub_info->gpa_mask);
169}
170
171/* pnode, offset --> socket virtual */
172static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
173{
174 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
175}
176
177
178/*
179 * Access global MMRs using the low memory MMR32 space. This region supports
180 * faster MMR access but not all MMRs are accessible in this space.
181 */
182static inline unsigned long *uv_global_mmr32_address(int pnode,
183 unsigned long offset)
184{
185 return __va(UV_GLOBAL_MMR32_BASE |
186 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
187}
188
189static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
190 unsigned long val)
191{
192 *uv_global_mmr32_address(pnode, offset) = val;
193}
194
195static inline unsigned long uv_read_global_mmr32(int pnode,
196 unsigned long offset)
197{
198 return *uv_global_mmr32_address(pnode, offset);
199}
200
201/*
202 * Access Global MMR space using the MMR space located at the top of physical
203 * memory.
204 */
205static inline unsigned long *uv_global_mmr64_address(int pnode,
206 unsigned long offset)
207{
208 return __va(UV_GLOBAL_MMR64_BASE |
209 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
210}
211
212static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
213 unsigned long val)
214{
215 *uv_global_mmr64_address(pnode, offset) = val;
216}
217
218static inline unsigned long uv_read_global_mmr64(int pnode,
219 unsigned long offset)
220{
221 return *uv_global_mmr64_address(pnode, offset);
222}
223
224/*
225 * Access hub local MMRs. Faster than using global space but only local MMRs
226 * are accessible.
227 */
228static inline unsigned long *uv_local_mmr_address(unsigned long offset)
229{
230 return __va(UV_LOCAL_MMR_BASE | offset);
231}
232
233static inline unsigned long uv_read_local_mmr(unsigned long offset)
234{
235 return *uv_local_mmr_address(offset);
236}
237
238static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
239{
240 *uv_local_mmr_address(offset) = val;
241}
242
243/*
244 * Structures and definitions for converting between cpu, node, pnode, and blade
245 * numbers.
246 */
247
248/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
249static inline int uv_blade_processor_id(void)
250{
251 return smp_processor_id();
252}
253
254/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
255static inline int uv_numa_blade_id(void)
256{
257 return 0;
258}
259
260/* Convert a cpu number to the the UV blade number */
261static inline int uv_cpu_to_blade_id(int cpu)
262{
263 return 0;
264}
265
266/* Convert linux node number to the UV blade number */
267static inline int uv_node_to_blade_id(int nid)
268{
269 return 0;
270}
271
272/* Convert a blade id to the PNODE of the blade */
273static inline int uv_blade_to_pnode(int bid)
274{
275 return 0;
276}
277
278/* Determine the number of possible cpus on a blade */
279static inline int uv_blade_nr_possible_cpus(int bid)
280{
281 return num_possible_cpus();
282}
283
284/* Determine the number of online cpus on a blade */
285static inline int uv_blade_nr_online_cpus(int bid)
286{
287 return num_online_cpus();
288}
289
290/* Convert a cpu id to the PNODE of the blade containing the cpu */
291static inline int uv_cpu_to_pnode(int cpu)
292{
293 return 0;
294}
295
296/* Convert a linux node number to the PNODE of the blade */
297static inline int uv_node_to_pnode(int nid)
298{
299 return 0;
300}
301
302/* Maximum possible number of blades */
303static inline int uv_num_possible_blades(void)
304{
305 return 1;
306}
307
308#endif /* __ASM_IA64_UV_HUB__ */
309
diff --git a/include/asm-ia64/uv/uv_mmrs.h b/include/asm-ia64/uv/uv_mmrs.h
new file mode 100644
index 000000000000..1cc1dbb0182f
--- /dev/null
+++ b/include/asm-ia64/uv/uv_mmrs.h
@@ -0,0 +1,266 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV MMR definitions
7 *
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef __ASM_IA64_UV_MMRS__
12#define __ASM_IA64_UV_MMRS__
13
14/*
15 * AUTO GENERATED - Do not edit
16 */
17
18 #define UV_MMR_ENABLE (1UL << 63)
19
20/* ========================================================================= */
21/* UVH_NODE_ID */
22/* ========================================================================= */
23#define UVH_NODE_ID 0x0UL
24
25#define UVH_NODE_ID_FORCE1_SHFT 0
26#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
27#define UVH_NODE_ID_MANUFACTURER_SHFT 1
28#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
29#define UVH_NODE_ID_PART_NUMBER_SHFT 12
30#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
31#define UVH_NODE_ID_REVISION_SHFT 28
32#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
33#define UVH_NODE_ID_NODE_ID_SHFT 32
34#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
35#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
36#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
37#define UVH_NODE_ID_NI_PORT_SHFT 56
38#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
39
40union uvh_node_id_u {
41 unsigned long v;
42 struct uvh_node_id_s {
43 unsigned long force1 : 1; /* RO */
44 unsigned long manufacturer : 11; /* RO */
45 unsigned long part_number : 16; /* RO */
46 unsigned long revision : 4; /* RO */
47 unsigned long node_id : 15; /* RW */
48 unsigned long rsvd_47 : 1; /* */
49 unsigned long nodes_per_bit : 7; /* RW */
50 unsigned long rsvd_55 : 1; /* */
51 unsigned long ni_port : 4; /* RO */
52 unsigned long rsvd_60_63 : 4; /* */
53 } s;
54};
55
56/* ========================================================================= */
57/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
58/* ========================================================================= */
59#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
60
61#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
62#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
63
64union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
65 unsigned long v;
66 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
67 unsigned long rsvd_0_23 : 24; /* */
68 unsigned long dest_base : 22; /* RW */
69 unsigned long rsvd_46_63: 18; /* */
70 } s;
71};
72
73/* ========================================================================= */
74/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */
75/* ========================================================================= */
76#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
77
78#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
79#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
80
81union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
82 unsigned long v;
83 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
84 unsigned long rsvd_0_23 : 24; /* */
85 unsigned long dest_base : 22; /* RW */
86 unsigned long rsvd_46_63: 18; /* */
87 } s;
88};
89
90/* ========================================================================= */
91/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */
92/* ========================================================================= */
93#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
94
95#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
96#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
97
98union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
99 unsigned long v;
100 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
101 unsigned long rsvd_0_23 : 24; /* */
102 unsigned long dest_base : 22; /* RW */
103 unsigned long rsvd_46_63: 18; /* */
104 } s;
105};
106
107/* ========================================================================= */
108/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
109/* ========================================================================= */
110#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
111
112#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
113#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
114#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 46
115#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0000400000000000UL
116#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
117#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
118#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
119#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
120
121union uvh_rh_gam_gru_overlay_config_mmr_u {
122 unsigned long v;
123 struct uvh_rh_gam_gru_overlay_config_mmr_s {
124 unsigned long rsvd_0_27: 28; /* */
125 unsigned long base : 18; /* RW */
126 unsigned long gr4 : 1; /* RW */
127 unsigned long rsvd_47_51: 5; /* */
128 unsigned long n_gru : 4; /* RW */
129 unsigned long rsvd_56_62: 7; /* */
130 unsigned long enable : 1; /* RW */
131 } s;
132};
133
134/* ========================================================================= */
135/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
136/* ========================================================================= */
137#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
138
139#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
140#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
141#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
142#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
143#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
144#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
145
146union uvh_rh_gam_mmr_overlay_config_mmr_u {
147 unsigned long v;
148 struct uvh_rh_gam_mmr_overlay_config_mmr_s {
149 unsigned long rsvd_0_25: 26; /* */
150 unsigned long base : 20; /* RW */
151 unsigned long dual_hub : 1; /* RW */
152 unsigned long rsvd_47_62: 16; /* */
153 unsigned long enable : 1; /* RW */
154 } s;
155};
156
157/* ========================================================================= */
158/* UVH_RTC */
159/* ========================================================================= */
160#define UVH_RTC 0x28000UL
161
162#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
163#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
164
165union uvh_rtc_u {
166 unsigned long v;
167 struct uvh_rtc_s {
168 unsigned long real_time_clock : 56; /* RW */
169 unsigned long rsvd_56_63 : 8; /* */
170 } s;
171};
172
173/* ========================================================================= */
174/* UVH_SI_ADDR_MAP_CONFIG */
175/* ========================================================================= */
176#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
177
178#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
179#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
180#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
181#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
182
183union uvh_si_addr_map_config_u {
184 unsigned long v;
185 struct uvh_si_addr_map_config_s {
186 unsigned long m_skt : 6; /* RW */
187 unsigned long rsvd_6_7: 2; /* */
188 unsigned long n_skt : 4; /* RW */
189 unsigned long rsvd_12_63: 52; /* */
190 } s;
191};
192
193/* ========================================================================= */
194/* UVH_SI_ALIAS0_OVERLAY_CONFIG */
195/* ========================================================================= */
196#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
197
198#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
199#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
200#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
201#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
202#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
203#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
204
205union uvh_si_alias0_overlay_config_u {
206 unsigned long v;
207 struct uvh_si_alias0_overlay_config_s {
208 unsigned long rsvd_0_23: 24; /* */
209 unsigned long base : 8; /* RW */
210 unsigned long rsvd_32_47: 16; /* */
211 unsigned long m_alias : 5; /* RW */
212 unsigned long rsvd_53_62: 10; /* */
213 unsigned long enable : 1; /* RW */
214 } s;
215};
216
217/* ========================================================================= */
218/* UVH_SI_ALIAS1_OVERLAY_CONFIG */
219/* ========================================================================= */
220#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
221
222#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
223#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
224#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
225#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
226#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
227#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
228
229union uvh_si_alias1_overlay_config_u {
230 unsigned long v;
231 struct uvh_si_alias1_overlay_config_s {
232 unsigned long rsvd_0_23: 24; /* */
233 unsigned long base : 8; /* RW */
234 unsigned long rsvd_32_47: 16; /* */
235 unsigned long m_alias : 5; /* RW */
236 unsigned long rsvd_53_62: 10; /* */
237 unsigned long enable : 1; /* RW */
238 } s;
239};
240
241/* ========================================================================= */
242/* UVH_SI_ALIAS2_OVERLAY_CONFIG */
243/* ========================================================================= */
244#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
245
246#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
247#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
248#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
249#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
250#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
251#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
252
253union uvh_si_alias2_overlay_config_u {
254 unsigned long v;
255 struct uvh_si_alias2_overlay_config_s {
256 unsigned long rsvd_0_23: 24; /* */
257 unsigned long base : 8; /* RW */
258 unsigned long rsvd_32_47: 16; /* */
259 unsigned long m_alias : 5; /* RW */
260 unsigned long rsvd_53_62: 10; /* */
261 unsigned long enable : 1; /* RW */
262 } s;
263};
264
265
266#endif /* __ASM_IA64_UV_MMRS__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-25 08:43:15 -0500