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-rw-r--r--drivers/net/mv643xx_eth.c92
1 files changed, 34 insertions, 58 deletions
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index fea99b7fb6a4..bcc891dd84f4 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -169,42 +169,6 @@ static char mv643xx_driver_version[] = "1.0";
169#define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800 169#define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
170#define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400 170#define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
171 171
172/* Gigabit Ethernet Unit Global Registers */
173
174/* MIB Counters register definitions */
175#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
176#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
177#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
178#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
179#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
180#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
181#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
182#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
183#define ETH_MIB_FRAMES_64_OCTETS 0x20
184#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
185#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
186#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
187#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
188#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
189#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
190#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
191#define ETH_MIB_GOOD_FRAMES_SENT 0x40
192#define ETH_MIB_EXCESSIVE_COLLISION 0x44
193#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
194#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
195#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
196#define ETH_MIB_FC_SENT 0x54
197#define ETH_MIB_GOOD_FC_RECEIVED 0x58
198#define ETH_MIB_BAD_FC_RECEIVED 0x5c
199#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
200#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
201#define ETH_MIB_OVERSIZE_RECEIVED 0x68
202#define ETH_MIB_JABBER_RECEIVED 0x6c
203#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
204#define ETH_MIB_BAD_CRC_EVENT 0x74
205#define ETH_MIB_COLLISION 0x78
206#define ETH_MIB_LATE_COLLISION 0x7c
207
208/* Port serial status reg (PSR) */ 172/* Port serial status reg (PSR) */
209#define ETH_INTERFACE_PCM 0x00000001 173#define ETH_INTERFACE_PCM 0x00000001
210#define ETH_LINK_IS_UP 0x00000002 174#define ETH_LINK_IS_UP 0x00000002
@@ -1156,8 +1120,7 @@ static void eth_clear_mib_counters(struct mv643xx_private *mp)
1156 int i; 1120 int i;
1157 1121
1158 /* Perform dummy reads from MIB counters */ 1122 /* Perform dummy reads from MIB counters */
1159 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; 1123 for (i = 0; i < 0x80; i += 4)
1160 i += 4)
1161 rdl(mp, MIB_COUNTERS(port_num) + i); 1124 rdl(mp, MIB_COUNTERS(port_num) + i);
1162} 1125}
1163 1126
@@ -1169,26 +1132,39 @@ static inline u32 read_mib(struct mv643xx_private *mp, int offset)
1169static void eth_update_mib_counters(struct mv643xx_private *mp) 1132static void eth_update_mib_counters(struct mv643xx_private *mp)
1170{ 1133{
1171 struct mv643xx_mib_counters *p = &mp->mib_counters; 1134 struct mv643xx_mib_counters *p = &mp->mib_counters;
1172 int offset; 1135
1173 1136 p->good_octets_received += read_mib(mp, 0x00);
1174 p->good_octets_received += 1137 p->good_octets_received += (u64)read_mib(mp, 0x04) << 32;
1175 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); 1138 p->bad_octets_received += read_mib(mp, 0x08);
1176 p->good_octets_received += 1139 p->internal_mac_transmit_err += read_mib(mp, 0x0c);
1177 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32; 1140 p->good_frames_received += read_mib(mp, 0x10);
1178 1141 p->bad_frames_received += read_mib(mp, 0x14);
1179 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED; 1142 p->broadcast_frames_received += read_mib(mp, 0x18);
1180 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS; 1143 p->multicast_frames_received += read_mib(mp, 0x1c);
1181 offset += 4) 1144 p->frames_64_octets += read_mib(mp, 0x20);
1182 *(u32 *)((char *)p + offset) += read_mib(mp, offset); 1145 p->frames_65_to_127_octets += read_mib(mp, 0x24);
1183 1146 p->frames_128_to_255_octets += read_mib(mp, 0x28);
1184 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW); 1147 p->frames_256_to_511_octets += read_mib(mp, 0x2c);
1185 p->good_octets_sent += 1148 p->frames_512_to_1023_octets += read_mib(mp, 0x30);
1186 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32; 1149 p->frames_1024_to_max_octets += read_mib(mp, 0x34);
1187 1150 p->good_octets_sent += read_mib(mp, 0x38);
1188 for (offset = ETH_MIB_GOOD_FRAMES_SENT; 1151 p->good_octets_sent += (u64)read_mib(mp, 0x3c) << 32;
1189 offset <= ETH_MIB_LATE_COLLISION; 1152 p->good_frames_sent += read_mib(mp, 0x40);
1190 offset += 4) 1153 p->excessive_collision += read_mib(mp, 0x44);
1191 *(u32 *)((char *)p + offset) += read_mib(mp, offset); 1154 p->multicast_frames_sent += read_mib(mp, 0x48);
1155 p->broadcast_frames_sent += read_mib(mp, 0x4c);
1156 p->unrec_mac_control_received += read_mib(mp, 0x50);
1157 p->fc_sent += read_mib(mp, 0x54);
1158 p->good_fc_received += read_mib(mp, 0x58);
1159 p->bad_fc_received += read_mib(mp, 0x5c);
1160 p->undersize_received += read_mib(mp, 0x60);
1161 p->fragments_received += read_mib(mp, 0x64);
1162 p->oversize_received += read_mib(mp, 0x68);
1163 p->jabber_received += read_mib(mp, 0x6c);
1164 p->mac_receive_error += read_mib(mp, 0x70);
1165 p->bad_crc_event += read_mib(mp, 0x74);
1166 p->collision += read_mib(mp, 0x78);
1167 p->late_collision += read_mib(mp, 0x7c);
1192} 1168}
1193 1169
1194 1170