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-rw-r--r--drivers/tty/serial/8250.c14
-rw-r--r--drivers/tty/serial/8250.h1
-rw-r--r--include/linux/serial_core.h3
-rw-r--r--include/linux/serial_reg.h1
4 files changed, 16 insertions, 3 deletions
diff --git a/drivers/tty/serial/8250.c b/drivers/tty/serial/8250.c
index 54482d724fee..a5e290de8c93 100644
--- a/drivers/tty/serial/8250.c
+++ b/drivers/tty/serial/8250.c
@@ -271,7 +271,7 @@ static const struct serial8250_config uart_config[] = {
271 .fifo_size = 32, 271 .fifo_size = 32,
272 .tx_loadsz = 32, 272 .tx_loadsz = 32,
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
274 .flags = UART_CAP_FIFO | UART_CAP_UUE, 274 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
275 }, 275 },
276 [PORT_RM9000] = { 276 [PORT_RM9000] = {
277 .name = "RM9000", 277 .name = "RM9000",
@@ -301,6 +301,14 @@ static const struct serial8250_config uart_config[] = {
301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
302 .flags = UART_CAP_FIFO | UART_CAP_AFE, 302 .flags = UART_CAP_FIFO | UART_CAP_AFE,
303 }, 303 },
304 [PORT_TEGRA] = {
305 .name = "Tegra",
306 .fifo_size = 32,
307 .tx_loadsz = 8,
308 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
309 UART_FCR_T_TRIG_01,
310 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
311 },
304}; 312};
305 313
306#if defined(CONFIG_MIPS_ALCHEMY) 314#if defined(CONFIG_MIPS_ALCHEMY)
@@ -2403,7 +2411,9 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2403 UART_ENABLE_MS(&up->port, termios->c_cflag)) 2411 UART_ENABLE_MS(&up->port, termios->c_cflag))
2404 up->ier |= UART_IER_MSI; 2412 up->ier |= UART_IER_MSI;
2405 if (up->capabilities & UART_CAP_UUE) 2413 if (up->capabilities & UART_CAP_UUE)
2406 up->ier |= UART_IER_UUE | UART_IER_RTOIE; 2414 up->ier |= UART_IER_UUE;
2415 if (up->capabilities & UART_CAP_RTOIE)
2416 up->ier |= UART_IER_RTOIE;
2407 2417
2408 serial_out(up, UART_IER, up->ier); 2418 serial_out(up, UART_IER, up->ier);
2409 2419
diff --git a/drivers/tty/serial/8250.h b/drivers/tty/serial/8250.h
index d13b586c0f72..6edf4a6a22d4 100644
--- a/drivers/tty/serial/8250.h
+++ b/drivers/tty/serial/8250.h
@@ -42,6 +42,7 @@ struct serial8250_config {
42#define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */ 42#define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */
43#define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */ 43#define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */
44#define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */ 44#define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */
45#define UART_CAP_RTOIE (1 << 13) /* UART needs IER bit 4 set (Xscale, Tegra) */
45 46
46#define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */ 47#define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */
47#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */ 48#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 95d479ba514e..a5c31146a337 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -45,7 +45,8 @@
45#define PORT_OCTEON 17 /* Cavium OCTEON internal UART */ 45#define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
46#define PORT_AR7 18 /* Texas Instruments AR7 internal UART */ 46#define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
47#define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */ 47#define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
48#define PORT_MAX_8250 19 /* max port ID */ 48#define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
49#define PORT_MAX_8250 20 /* max port ID */
49 50
50/* 51/*
51 * ARM specific type numbers. These are not currently guaranteed 52 * ARM specific type numbers. These are not currently guaranteed
diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h
index 3ecb71a9e505..5f66e8499fb9 100644
--- a/include/linux/serial_reg.h
+++ b/include/linux/serial_reg.h
@@ -57,6 +57,7 @@
57 * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 57 * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654
58 * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 58 * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
59 * TI16C752: 8 16 56 60 8 16 32 56 59 * TI16C752: 8 16 56 60 8 16 32 56
60 * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA
60 */ 61 */
61#define UART_FCR_R_TRIG_00 0x00 62#define UART_FCR_R_TRIG_00 0x00
62#define UART_FCR_R_TRIG_01 0x40 63#define UART_FCR_R_TRIG_01 0x40