aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/mm/proc-arm1020.S16
-rw-r--r--arch/arm/mm/proc-arm1020e.S15
-rw-r--r--arch/arm/mm/proc-arm1022.S15
-rw-r--r--arch/arm/mm/proc-arm1026.S15
-rw-r--r--arch/arm/mm/proc-arm720.S15
-rw-r--r--arch/arm/mm/proc-arm920.S15
-rw-r--r--arch/arm/mm/proc-arm922.S15
-rw-r--r--arch/arm/mm/proc-arm925.S14
-rw-r--r--arch/arm/mm/proc-arm926.S15
-rw-r--r--arch/arm/mm/proc-macros.S10
-rw-r--r--arch/arm/mm/proc-sa110.S16
-rw-r--r--arch/arm/mm/proc-sa1100.S15
-rw-r--r--arch/arm/mm/proc-v6.S15
-rw-r--r--arch/arm/mm/proc-xsc3.S19
-rw-r--r--arch/arm/mm/proc-xscale.S16
15 files changed, 101 insertions, 125 deletions
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index efeebe77891f..6c731a4f70c9 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -440,11 +440,12 @@ __arm1020_setup:
440#ifdef CONFIG_MMU 440#ifdef CONFIG_MMU
441 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 441 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
442#endif 442#endif
443
444 adr r5, arm1020_crval
445 ldmia r5, {r5, r6}
443 mrc p15, 0, r0, c1, c0 @ get control register v4 446 mrc p15, 0, r0, c1, c0 @ get control register v4
444 ldr r5, arm1020_cr1_clear
445 bic r0, r0, r5 447 bic r0, r0, r5
446 ldr r5, arm1020_cr1_set 448 orr r0, r0, r6
447 orr r0, r0, r5
448#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 449#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
449 orr r0, r0, #0x4000 @ .R.. .... .... .... 450 orr r0, r0, #0x4000 @ .R.. .... .... ....
450#endif 451#endif
@@ -456,12 +457,9 @@ __arm1020_setup:
456 * .RVI ZFRS BLDP WCAM 457 * .RVI ZFRS BLDP WCAM
457 * .011 1001 ..11 0101 458 * .011 1001 ..11 0101
458 */ 459 */
459 .type arm1020_cr1_clear, #object 460 .type arm1020_crval, #object
460 .type arm1020_cr1_set, #object 461arm1020_crval:
461arm1020_cr1_clear: 462 crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
462 .word 0x593f
463arm1020_cr1_set:
464 .word 0x3935
465 463
466 __INITDATA 464 __INITDATA
467 465
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 78622ac1e732..269f485d092d 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -422,11 +422,11 @@ __arm1020e_setup:
422#ifdef CONFIG_MMU 422#ifdef CONFIG_MMU
423 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 423 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
424#endif 424#endif
425 adr r5, arm1020e_crval
426 ldmia r5, {r5, r6}
425 mrc p15, 0, r0, c1, c0 @ get control register v4 427 mrc p15, 0, r0, c1, c0 @ get control register v4
426 ldr r5, arm1020e_cr1_clear
427 bic r0, r0, r5 428 bic r0, r0, r5
428 ldr r5, arm1020e_cr1_set 429 orr r0, r0, r6
429 orr r0, r0, r5
430#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 430#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
431 orr r0, r0, #0x4000 @ .R.. .... .... .... 431 orr r0, r0, #0x4000 @ .R.. .... .... ....
432#endif 432#endif
@@ -438,12 +438,9 @@ __arm1020e_setup:
438 * .RVI ZFRS BLDP WCAM 438 * .RVI ZFRS BLDP WCAM
439 * .011 1001 ..11 0101 439 * .011 1001 ..11 0101
440 */ 440 */
441 .type arm1020e_cr1_clear, #object 441 .type arm1020e_crval, #object
442 .type arm1020e_cr1_set, #object 442arm1020e_crval:
443arm1020e_cr1_clear: 443 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
444 .word 0x5f3f
445arm1020e_cr1_set:
446 .word 0x3935
447 444
448 __INITDATA 445 __INITDATA
449 446
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 840dfc85ba6d..0643bd464969 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -404,11 +404,11 @@ __arm1022_setup:
404#ifdef CONFIG_MMU 404#ifdef CONFIG_MMU
405 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 405 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
406#endif 406#endif
407 adr r5, arm1022_crval
408 ldmia r5, {r5, r6}
407 mrc p15, 0, r0, c1, c0 @ get control register v4 409 mrc p15, 0, r0, c1, c0 @ get control register v4
408 ldr r5, arm1022_cr1_clear
409 bic r0, r0, r5 410 bic r0, r0, r5
410 ldr r5, arm1022_cr1_set 411 orr r0, r0, r6
411 orr r0, r0, r5
412#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 412#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
413 orr r0, r0, #0x4000 @ .R.............. 413 orr r0, r0, #0x4000 @ .R..............
414#endif 414#endif
@@ -421,12 +421,9 @@ __arm1022_setup:
421 * .011 1001 ..11 0101 421 * .011 1001 ..11 0101
422 * 422 *
423 */ 423 */
424 .type arm1022_cr1_clear, #object 424 .type arm1022_crval, #object
425 .type arm1022_cr1_set, #object 425arm1022_crval:
426arm1022_cr1_clear: 426 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
427 .word 0x7f3f
428arm1022_cr1_set:
429 .word 0x3935
430 427
431 __INITDATA 428 __INITDATA
432 429
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 72b75d9c712a..0668bfbac67b 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -399,11 +399,11 @@ __arm1026_setup:
399 mov r0, #4 @ explicitly disable writeback 399 mov r0, #4 @ explicitly disable writeback
400 mcr p15, 7, r0, c15, c0, 0 400 mcr p15, 7, r0, c15, c0, 0
401#endif 401#endif
402 adr r5, arm1026_crval
403 ldmia r5, {r5, r6}
402 mrc p15, 0, r0, c1, c0 @ get control register v4 404 mrc p15, 0, r0, c1, c0 @ get control register v4
403 ldr r5, arm1026_cr1_clear
404 bic r0, r0, r5 405 bic r0, r0, r5
405 ldr r5, arm1026_cr1_set 406 orr r0, r0, r6
406 orr r0, r0, r5
407#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 407#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
408 orr r0, r0, #0x4000 @ .R.. .... .... .... 408 orr r0, r0, #0x4000 @ .R.. .... .... ....
409#endif 409#endif
@@ -416,12 +416,9 @@ __arm1026_setup:
416 * .011 1001 ..11 0101 416 * .011 1001 ..11 0101
417 * 417 *
418 */ 418 */
419 .type arm1026_cr1_clear, #object 419 .type arm1026_crval, #object
420 .type arm1026_cr1_set, #object 420arm1026_crval:
421arm1026_cr1_clear: 421 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
422 .word 0x7f3f
423arm1026_cr1_set:
424 .word 0x3935
425 422
426 __INITDATA 423 __INITDATA
427 424
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index fb4110a9db6f..0e6946ab6e5b 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -169,11 +169,11 @@ __arm720_setup:
169#ifdef CONFIG_MMU 169#ifdef CONFIG_MMU
170 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) 170 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
171#endif 171#endif
172 adr r5, arm720_crval
173 ldmia r5, {r5, r6}
172 mrc p15, 0, r0, c1, c0 @ get control register 174 mrc p15, 0, r0, c1, c0 @ get control register
173 ldr r5, arm720_cr1_clear
174 bic r0, r0, r5 175 bic r0, r0, r5
175 ldr r5, arm720_cr1_set 176 orr r0, r0, r6
176 orr r0, r0, r5
177 mov pc, lr @ __ret (head.S) 177 mov pc, lr @ __ret (head.S)
178 .size __arm720_setup, . - __arm720_setup 178 .size __arm720_setup, . - __arm720_setup
179 179
@@ -183,12 +183,9 @@ __arm720_setup:
183 * ..1. 1001 ..11 1101 183 * ..1. 1001 ..11 1101
184 * 184 *
185 */ 185 */
186 .type arm720_cr1_clear, #object 186 .type arm720_crval, #object
187 .type arm720_cr1_set, #object 187arm720_crval:
188arm720_cr1_clear: 188 crval clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
189 .word 0x2f3f
190arm720_cr1_set:
191 .word 0x213d
192 189
193 __INITDATA 190 __INITDATA
194 191
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index b9f1bd11bc62..45292f46c3b2 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -391,11 +391,11 @@ __arm920_setup:
391#ifdef CONFIG_MMU 391#ifdef CONFIG_MMU
392 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 392 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
393#endif 393#endif
394 adr r5, arm920_crval
395 ldmia r5, {r5, r6}
394 mrc p15, 0, r0, c1, c0 @ get control register v4 396 mrc p15, 0, r0, c1, c0 @ get control register v4
395 ldr r5, arm920_cr1_clear
396 bic r0, r0, r5 397 bic r0, r0, r5
397 ldr r5, arm920_cr1_set 398 orr r0, r0, r6
398 orr r0, r0, r5
399 mov pc, lr 399 mov pc, lr
400 .size __arm920_setup, . - __arm920_setup 400 .size __arm920_setup, . - __arm920_setup
401 401
@@ -405,12 +405,9 @@ __arm920_setup:
405 * ..11 0001 ..11 0101 405 * ..11 0001 ..11 0101
406 * 406 *
407 */ 407 */
408 .type arm920_cr1_clear, #object 408 .type arm920_crval, #object
409 .type arm920_cr1_set, #object 409arm920_crval:
410arm920_cr1_clear: 410 crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
411 .word 0x3f3f
412arm920_cr1_set:
413 .word 0x3135
414 411
415 __INITDATA 412 __INITDATA
416 413
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index bda0aea4ce82..3c57519494d7 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -395,11 +395,11 @@ __arm922_setup:
395#ifdef CONFIG_MMU 395#ifdef CONFIG_MMU
396 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 396 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
397#endif 397#endif
398 adr r5, arm922_crval
399 ldmia r5, {r5, r6}
398 mrc p15, 0, r0, c1, c0 @ get control register v4 400 mrc p15, 0, r0, c1, c0 @ get control register v4
399 ldr r5, arm922_cr1_clear
400 bic r0, r0, r5 401 bic r0, r0, r5
401 ldr r5, arm922_cr1_set 402 orr r0, r0, r6
402 orr r0, r0, r5
403 mov pc, lr 403 mov pc, lr
404 .size __arm922_setup, . - __arm922_setup 404 .size __arm922_setup, . - __arm922_setup
405 405
@@ -409,12 +409,9 @@ __arm922_setup:
409 * ..11 0001 ..11 0101 409 * ..11 0001 ..11 0101
410 * 410 *
411 */ 411 */
412 .type arm922_cr1_clear, #object 412 .type arm922_crval, #object
413 .type arm922_cr1_set, #object 413arm922_crval:
414arm922_cr1_clear: 414 crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
415 .word 0x3f3f
416arm922_cr1_set:
417 .word 0x3135
418 415
419 __INITDATA 416 __INITDATA
420 417
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index a28da8f0578f..66d5a32ba0f5 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -455,11 +455,10 @@ __arm925_setup:
455 mcr p15, 7, r0, c15, c0, 0 455 mcr p15, 7, r0, c15, c0, 0
456#endif 456#endif
457 457
458 adr r5, {r5, r6}
458 mrc p15, 0, r0, c1, c0 @ get control register v4 459 mrc p15, 0, r0, c1, c0 @ get control register v4
459 ldr r5, arm925_cr1_clear
460 bic r0, r0, r5 460 bic r0, r0, r5
461 ldr r5, arm925_cr1_set 461 orr r0, r0, r6
462 orr r0, r0, r5
463#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 462#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
464 orr r0, r0, #0x4000 @ .1.. .... .... .... 463 orr r0, r0, #0x4000 @ .1.. .... .... ....
465#endif 464#endif
@@ -472,12 +471,9 @@ __arm925_setup:
472 * .011 0001 ..11 1101 471 * .011 0001 ..11 1101
473 * 472 *
474 */ 473 */
475 .type arm925_cr1_clear, #object 474 .type arm925_crval, #object
476 .type arm925_cr1_set, #object 475arm925_crval:
477arm925_cr1_clear: 476 crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
478 .word 0x7f3f
479arm925_cr1_set:
480 .word 0x313d
481 477
482 __INITDATA 478 __INITDATA
483 479
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 496a2335d69e..189820e25184 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -404,11 +404,11 @@ __arm926_setup:
404 mcr p15, 7, r0, c15, c0, 0 404 mcr p15, 7, r0, c15, c0, 0
405#endif 405#endif
406 406
407 adr r5, arm926_crval
408 ldmia r5, {r5, r6}
407 mrc p15, 0, r0, c1, c0 @ get control register v4 409 mrc p15, 0, r0, c1, c0 @ get control register v4
408 ldr r5, arm926_cr1_clear
409 bic r0, r0, r5 410 bic r0, r0, r5
410 ldr r5, arm926_cr1_set 411 orr r0, r0, r6
411 orr r0, r0, r5
412#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 412#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
413 orr r0, r0, #0x4000 @ .1.. .... .... .... 413 orr r0, r0, #0x4000 @ .1.. .... .... ....
414#endif 414#endif
@@ -421,12 +421,9 @@ __arm926_setup:
421 * .011 0001 ..11 0101 421 * .011 0001 ..11 0101
422 * 422 *
423 */ 423 */
424 .type arm926_cr1_clear, #object 424 .type arm926_crval, #object
425 .type arm926_cr1_set, #object 425arm926_crval:
426arm926_cr1_clear: 426 crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
427 .word 0x7f3f
428arm926_cr1_set:
429 .word 0x3135
430 427
431 __INITDATA 428 __INITDATA
432 429
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 7cfc2604a1ee..9e2c89eb2115 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -49,3 +49,13 @@
49 .macro asid, rd, rn 49 .macro asid, rd, rn
50 and \rd, \rn, #255 50 and \rd, \rn, #255
51 .endm 51 .endm
52
53 .macro crval, clear, mmuset, ucset
54#ifdef CONFIG_MMU
55 .word \clear
56 .word \mmuset
57#else
58 .word \clear
59 .word \ucset
60#endif
61 .endm
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 31a09087865d..e812246277cf 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -185,11 +185,12 @@ __sa110_setup:
185#ifdef CONFIG_MMU 185#ifdef CONFIG_MMU
186 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4 186 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
187#endif 187#endif
188
189 adr r5, sa110_crval
190 ldmia r5, {r5, r6}
188 mrc p15, 0, r0, c1, c0 @ get control register v4 191 mrc p15, 0, r0, c1, c0 @ get control register v4
189 ldr r5, sa110_cr1_clear
190 bic r0, r0, r5 192 bic r0, r0, r5
191 ldr r5, sa110_cr1_set 193 orr r0, r0, r6
192 orr r0, r0, r5
193 mov pc, lr 194 mov pc, lr
194 .size __sa110_setup, . - __sa110_setup 195 .size __sa110_setup, . - __sa110_setup
195 196
@@ -199,12 +200,9 @@ __sa110_setup:
199 * ..01 0001 ..11 1101 200 * ..01 0001 ..11 1101
200 * 201 *
201 */ 202 */
202 .type sa110_cr1_clear, #object 203 .type sa110_crval, #object
203 .type sa110_cr1_set, #object 204sa110_crval:
204sa110_cr1_clear: 205 crval clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
205 .word 0x3f3f
206sa110_cr1_set:
207 .word 0x113d
208 206
209 __INITDATA 207 __INITDATA
210 208
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 4e2489c3e1cc..ba32cc6296a0 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -198,11 +198,11 @@ __sa1100_setup:
198#ifdef CONFIG_MMU 198#ifdef CONFIG_MMU
199 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 199 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
200#endif 200#endif
201 adr r5, sa1100_crval
202 ldmia r5, {r5, r6}
201 mrc p15, 0, r0, c1, c0 @ get control register v4 203 mrc p15, 0, r0, c1, c0 @ get control register v4
202 ldr r5, sa1100_cr1_clear
203 bic r0, r0, r5 204 bic r0, r0, r5
204 ldr r5, sa1100_cr1_set 205 orr r0, r0, r6
205 orr r0, r0, r5
206 mov pc, lr 206 mov pc, lr
207 .size __sa1100_setup, . - __sa1100_setup 207 .size __sa1100_setup, . - __sa1100_setup
208 208
@@ -212,12 +212,9 @@ __sa1100_setup:
212 * ..11 0001 ..11 1101 212 * ..11 0001 ..11 1101
213 * 213 *
214 */ 214 */
215 .type sa1100_cr1_clear, #object 215 .type sa1100_crval, #object
216 .type sa1100_cr1_set, #object 216sa1100_crval:
217sa1100_cr1_clear: 217 crval clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
218 .word 0x3f3f
219sa1100_cr1_set:
220 .word 0x313d
221 218
222 __INITDATA 219 __INITDATA
223 220
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index ff778967a005..6f72549f8843 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -212,11 +212,11 @@ __v6_setup:
212 orr r0, r0, #(0xf << 20) 212 orr r0, r0, #(0xf << 20)
213 mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP 213 mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP
214#endif 214#endif
215 adr r5, v6_crval
216 ldmia r5, {r5, r6}
215 mrc p15, 0, r0, c1, c0, 0 @ read control register 217 mrc p15, 0, r0, c1, c0, 0 @ read control register
216 ldr r5, v6_cr1_clear @ get mask for bits to clear
217 bic r0, r0, r5 @ clear bits them 218 bic r0, r0, r5 @ clear bits them
218 ldr r5, v6_cr1_set @ get mask for bits to set 219 orr r0, r0, r6 @ set them
219 orr r0, r0, r5 @ set them
220 mov pc, lr @ return to head.S:__ret 220 mov pc, lr @ return to head.S:__ret
221 221
222 /* 222 /*
@@ -225,12 +225,9 @@ __v6_setup:
225 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced 225 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
226 * 0 110 0011 1.00 .111 1101 < we want 226 * 0 110 0011 1.00 .111 1101 < we want
227 */ 227 */
228 .type v6_cr1_clear, #object 228 .type v6_crval, #object
229 .type v6_cr1_set, #object 229v6_crval:
230v6_cr1_clear: 230 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
231 .word 0x01e0fb7f
232v6_cr1_set:
233 .word 0x00c0387d
234 231
235 .type v6_processor_functions, #object 232 .type v6_processor_functions, #object
236ENTRY(v6_processor_functions) 233ENTRY(v6_processor_functions)
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 9aea506d3e65..4ace2d8090c7 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -426,23 +426,26 @@ __xsc3_setup:
426 orr r0, r0, #(1 << 10) @ enable L2 for LLR cache 426 orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
427#endif 427#endif
428 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg 428 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
429
430 adr r5, xsc3_crval
431 ldmia r5, {r5, r6}
429 mrc p15, 0, r0, c1, c0, 0 @ get control register 432 mrc p15, 0, r0, c1, c0, 0 @ get control register
430 bic r0, r0, #0x0002 @ .... .... .... ..A. 433 bic r0, r0, r5 @ .... .... .... ..A.
431 orr r0, r0, #0x0005 @ .... .... .... .C.M 434 orr r0, r0, r6 @ .... .... .... .C.M
432#if BTB_ENABLE 435#if BTB_ENABLE
433 bic r0, r0, #0x0200 @ .... ..R. .... .... 436 orr r0, r0, #0x00000800 @ ..VI Z..S .... ....
434 orr r0, r0, #0x3900 @ ..VI Z..S .... ....
435#else
436 bic r0, r0, #0x0a00 @ .... Z.R. .... ....
437 orr r0, r0, #0x3100 @ ..VI ...S .... ....
438#endif 437#endif
439#if L2_CACHE_ENABLE 438#if L2_CACHE_ENABLE
440 orr r0, r0, #0x4000000 @ L2 enable 439 orr r0, r0, #0x04000000 @ L2 enable
441#endif 440#endif
442 mov pc, lr 441 mov pc, lr
443 442
444 .size __xsc3_setup, . - __xsc3_setup 443 .size __xsc3_setup, . - __xsc3_setup
445 444
445 .type xsc3_crval, #object
446xsc3_crval:
447 crval clear=0x04003b02, mmuset=0x00003105, ucset=0x00001100
448
446 __INITDATA 449 __INITDATA
447 450
448/* 451/*
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index f4aeb7b06911..535395e25a8a 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -475,11 +475,12 @@ __xscale_setup:
475 orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde 475 orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
476 orr r0, r0, #1 << 13 @ Its undefined whether this 476 orr r0, r0, #1 << 13 @ Its undefined whether this
477 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes 477 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
478
479 adr r5, xscale_crval
480 ldmia r5, {r5, r6}
478 mrc p15, 0, r0, c1, c0, 0 @ get control register 481 mrc p15, 0, r0, c1, c0, 0 @ get control register
479 ldr r5, xscale_cr1_clear
480 bic r0, r0, r5 482 bic r0, r0, r5
481 ldr r5, xscale_cr1_set 483 orr r0, r0, r6
482 orr r0, r0, r5
483 mov pc, lr 484 mov pc, lr
484 .size __xscale_setup, . - __xscale_setup 485 .size __xscale_setup, . - __xscale_setup
485 486
@@ -489,12 +490,9 @@ __xscale_setup:
489 * ..11 1.01 .... .101 490 * ..11 1.01 .... .101
490 * 491 *
491 */ 492 */
492 .type xscale_cr1_clear, #object 493 .type xscale_crval, #object
493 .type xscale_cr1_set, #object 494xscale_crval:
494xscale_cr1_clear: 495 crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
495 .word 0x3b07
496xscale_cr1_set:
497 .word 0x3905
498 496
499 __INITDATA 497 __INITDATA
500 498
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 23:51:37 -0500