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-rw-r--r--arch/sh/Kconfig11
-rw-r--r--arch/sh/boards/mach-dreamcast/setup.c6
-rw-r--r--arch/sh/boards/mach-se/7751/Makefile2
-rw-r--r--arch/sh/boards/mach-se/7751/io.c16
-rw-r--r--arch/sh/boards/mach-se/7751/pci.c147
-rw-r--r--arch/sh/boards/mach-se/7780/irq.c27
-rw-r--r--arch/sh/boards/mach-snapgear/io.c16
-rw-r--r--arch/sh/boards/mach-systemh/io.c16
-rw-r--r--arch/sh/boards/mach-titan/io.c20
-rw-r--r--arch/sh/configs/sh7724_generic_defconfig707
-rw-r--r--arch/sh/drivers/pci/Kconfig18
-rw-r--r--arch/sh/drivers/pci/Makefile28
-rw-r--r--arch/sh/drivers/pci/fixups-cayman.c (renamed from arch/sh/drivers/pci/ops-cayman.c)12
-rw-r--r--arch/sh/drivers/pci/fixups-dreamcast.c9
-rw-r--r--arch/sh/drivers/pci/fixups-landisk.c (renamed from arch/sh/drivers/pci/ops-landisk.c)33
-rw-r--r--arch/sh/drivers/pci/fixups-lboxre2.c41
-rw-r--r--arch/sh/drivers/pci/fixups-r7780rp.c41
-rw-r--r--arch/sh/drivers/pci/fixups-rts7751r2d.c48
-rw-r--r--arch/sh/drivers/pci/fixups-sdk7780.c63
-rw-r--r--arch/sh/drivers/pci/fixups-se7751.c111
-rw-r--r--arch/sh/drivers/pci/fixups-se7780.c60
-rw-r--r--arch/sh/drivers/pci/fixups-sh7785lcr.c46
-rw-r--r--arch/sh/drivers/pci/fixups-snapgear.c38
-rw-r--r--arch/sh/drivers/pci/fixups-titan.c (renamed from arch/sh/drivers/pci/ops-titan.c)39
-rw-r--r--arch/sh/drivers/pci/ops-dreamcast.c107
-rw-r--r--arch/sh/drivers/pci/ops-lboxre2.c63
-rw-r--r--arch/sh/drivers/pci/ops-r7780rp.c68
-rw-r--r--arch/sh/drivers/pci/ops-rts7751r2d.c74
-rw-r--r--arch/sh/drivers/pci/ops-sdk7780.c73
-rw-r--r--arch/sh/drivers/pci/ops-se7780.c96
-rw-r--r--arch/sh/drivers/pci/ops-sh03.c45
-rw-r--r--arch/sh/drivers/pci/ops-sh4.c79
-rw-r--r--arch/sh/drivers/pci/ops-sh5.c25
-rw-r--r--arch/sh/drivers/pci/ops-sh7785lcr.c66
-rw-r--r--arch/sh/drivers/pci/ops-snapgear.c94
-rw-r--r--arch/sh/drivers/pci/pci-auto.c545
-rw-r--r--arch/sh/drivers/pci/pci-dreamcast.c102
-rw-r--r--arch/sh/drivers/pci/pci-sh4.h19
-rw-r--r--arch/sh/drivers/pci/pci-sh5.c51
-rw-r--r--arch/sh/drivers/pci/pci-sh5.h3
-rw-r--r--arch/sh/drivers/pci/pci-sh7751.c216
-rw-r--r--arch/sh/drivers/pci/pci-sh7751.h12
-rw-r--r--arch/sh/drivers/pci/pci-sh7780.c227
-rw-r--r--arch/sh/drivers/pci/pci-sh7780.h16
-rw-r--r--arch/sh/drivers/pci/pci.c279
-rw-r--r--arch/sh/include/asm/device.h2
-rw-r--r--arch/sh/include/asm/pci.h98
-rw-r--r--arch/sh/include/asm/processor.h2
-rw-r--r--arch/sh/include/cpu-sh4/cpu/freq.h18
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7724.h255
-rw-r--r--arch/sh/include/mach-dreamcast/mach/pci.h2
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile3
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c112
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c2230
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c10
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c10
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c10
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c10
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c556
-rw-r--r--arch/sh/kernel/io.c1
-rw-r--r--arch/sh/kernel/setup.c10
-rw-r--r--arch/sh/kernel/time_32.c9
-rw-r--r--arch/sh/mm/ioremap_32.c14
-rw-r--r--arch/sh/oprofile/common.c1
-rw-r--r--drivers/clocksource/sh_cmt.c84
-rw-r--r--drivers/serial/sh-sci.h23
67 files changed, 5004 insertions, 2277 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index e7390dd0283d..4c68fdedfa10 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -347,6 +347,16 @@ config CPU_SUBTYPE_SH7723
347 help 347 help
348 Select SH7723 if you have an SH-MobileR2 CPU. 348 Select SH7723 if you have an SH-MobileR2 CPU.
349 349
350config CPU_SUBTYPE_SH7724
351 bool "Support SH7724 processor"
352 select CPU_SH4A
353 select CPU_SHX2
354 select ARCH_SHMOBILE
355 select ARCH_SPARSEMEM_ENABLE
356 select SYS_SUPPORTS_CMT
357 help
358 Select SH7724 if you have an SH-MobileR2R CPU.
359
350config CPU_SUBTYPE_SH7763 360config CPU_SUBTYPE_SH7763
351 bool "Support SH7763 processor" 361 bool "Support SH7763 processor"
352 select CPU_SH4A 362 select CPU_SH4A
@@ -495,6 +505,7 @@ config SH_PCLK_FREQ
495 CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \ 505 CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \
496 CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG || \ 506 CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG || \
497 CPU_SUBTYPE_SH7786 507 CPU_SUBTYPE_SH7786
508 default "41666666" if CPU_SUBTYPE_SH7724
498 default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R 509 default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
499 default "66000000" if CPU_SUBTYPE_SH4_202 510 default "66000000" if CPU_SUBTYPE_SH4_202
500 default "50000000" 511 default "50000000"
diff --git a/arch/sh/boards/mach-dreamcast/setup.c b/arch/sh/boards/mach-dreamcast/setup.c
index d1bee4884cd6..ebe99227d4e6 100644
--- a/arch/sh/boards/mach-dreamcast/setup.c
+++ b/arch/sh/boards/mach-dreamcast/setup.c
@@ -30,7 +30,6 @@
30 30
31extern struct irq_chip systemasic_int; 31extern struct irq_chip systemasic_int;
32extern void aica_time_init(void); 32extern void aica_time_init(void);
33extern int gapspci_init(void);
34extern int systemasic_irq_demux(int); 33extern int systemasic_irq_demux(int);
35 34
36static void __init dreamcast_setup(char **cmdline_p) 35static void __init dreamcast_setup(char **cmdline_p)
@@ -51,11 +50,6 @@ static void __init dreamcast_setup(char **cmdline_p)
51 handle_level_irq); 50 handle_level_irq);
52 51
53 board_time_init = aica_time_init; 52 board_time_init = aica_time_init;
54
55#ifdef CONFIG_PCI
56 if (gapspci_init() < 0)
57 printk(KERN_WARNING "GAPSPCI was not detected.\n");
58#endif
59} 53}
60 54
61static struct sh_machine_vector mv_dreamcast __initmv = { 55static struct sh_machine_vector mv_dreamcast __initmv = {
diff --git a/arch/sh/boards/mach-se/7751/Makefile b/arch/sh/boards/mach-se/7751/Makefile
index dbc29f3a9de5..e6f4341bfe6e 100644
--- a/arch/sh/boards/mach-se/7751/Makefile
+++ b/arch/sh/boards/mach-se/7751/Makefile
@@ -3,5 +3,3 @@
3# 3#
4 4
5obj-y := setup.o io.o irq.o 5obj-y := setup.o io.o irq.o
6
7obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/sh/boards/mach-se/7751/io.c b/arch/sh/boards/mach-se/7751/io.c
index 6287ae570319..6e75bd4459e5 100644
--- a/arch/sh/boards/mach-se/7751/io.c
+++ b/arch/sh/boards/mach-se/7751/io.c
@@ -34,8 +34,6 @@ unsigned char sh7751se_inb(unsigned long port)
34{ 34{
35 if (PXSEG(port)) 35 if (PXSEG(port))
36 return *(volatile unsigned char *)port; 36 return *(volatile unsigned char *)port;
37 else if (is_pci_ioaddr(port))
38 return *(volatile unsigned char *)pci_ioaddr(port);
39 else 37 else
40 return (*port2adr(port)) & 0xff; 38 return (*port2adr(port)) & 0xff;
41} 39}
@@ -46,8 +44,6 @@ unsigned char sh7751se_inb_p(unsigned long port)
46 44
47 if (PXSEG(port)) 45 if (PXSEG(port))
48 v = *(volatile unsigned char *)port; 46 v = *(volatile unsigned char *)port;
49 else if (is_pci_ioaddr(port))
50 v = *(volatile unsigned char *)pci_ioaddr(port);
51 else 47 else
52 v = (*port2adr(port)) & 0xff; 48 v = (*port2adr(port)) & 0xff;
53 ctrl_delay(); 49 ctrl_delay();
@@ -58,8 +54,6 @@ unsigned short sh7751se_inw(unsigned long port)
58{ 54{
59 if (PXSEG(port)) 55 if (PXSEG(port))
60 return *(volatile unsigned short *)port; 56 return *(volatile unsigned short *)port;
61 else if (is_pci_ioaddr(port))
62 return *(volatile unsigned short *)pci_ioaddr(port);
63 else if (port >= 0x2000) 57 else if (port >= 0x2000)
64 return *port2adr(port); 58 return *port2adr(port);
65 else 59 else
@@ -71,8 +65,6 @@ unsigned int sh7751se_inl(unsigned long port)
71{ 65{
72 if (PXSEG(port)) 66 if (PXSEG(port))
73 return *(volatile unsigned long *)port; 67 return *(volatile unsigned long *)port;
74 else if (is_pci_ioaddr(port))
75 return *(volatile unsigned int *)pci_ioaddr(port);
76 else if (port >= 0x2000) 68 else if (port >= 0x2000)
77 return *port2adr(port); 69 return *port2adr(port);
78 else 70 else
@@ -85,8 +77,6 @@ void sh7751se_outb(unsigned char value, unsigned long port)
85 77
86 if (PXSEG(port)) 78 if (PXSEG(port))
87 *(volatile unsigned char *)port = value; 79 *(volatile unsigned char *)port = value;
88 else if (is_pci_ioaddr(port))
89 *((unsigned char*)pci_ioaddr(port)) = value;
90 else 80 else
91 *(port2adr(port)) = value; 81 *(port2adr(port)) = value;
92} 82}
@@ -95,8 +85,6 @@ void sh7751se_outb_p(unsigned char value, unsigned long port)
95{ 85{
96 if (PXSEG(port)) 86 if (PXSEG(port))
97 *(volatile unsigned char *)port = value; 87 *(volatile unsigned char *)port = value;
98 else if (is_pci_ioaddr(port))
99 *((unsigned char*)pci_ioaddr(port)) = value;
100 else 88 else
101 *(port2adr(port)) = value; 89 *(port2adr(port)) = value;
102 ctrl_delay(); 90 ctrl_delay();
@@ -106,8 +94,6 @@ void sh7751se_outw(unsigned short value, unsigned long port)
106{ 94{
107 if (PXSEG(port)) 95 if (PXSEG(port))
108 *(volatile unsigned short *)port = value; 96 *(volatile unsigned short *)port = value;
109 else if (is_pci_ioaddr(port))
110 *((unsigned short *)pci_ioaddr(port)) = value;
111 else if (port >= 0x2000) 97 else if (port >= 0x2000)
112 *port2adr(port) = value; 98 *port2adr(port) = value;
113 else 99 else
@@ -118,8 +104,6 @@ void sh7751se_outl(unsigned int value, unsigned long port)
118{ 104{
119 if (PXSEG(port)) 105 if (PXSEG(port))
120 *(volatile unsigned long *)port = value; 106 *(volatile unsigned long *)port = value;
121 else if (is_pci_ioaddr(port))
122 *((unsigned long*)pci_ioaddr(port)) = value;
123 else 107 else
124 maybebadio(port); 108 maybebadio(port);
125} 109}
diff --git a/arch/sh/boards/mach-se/7751/pci.c b/arch/sh/boards/mach-se/7751/pci.c
deleted file mode 100644
index 203b2923fe7f..000000000000
--- a/arch/sh/boards/mach-se/7751/pci.c
+++ /dev/null
@@ -1,147 +0,0 @@
1/*
2 * linux/arch/sh/boards/se/7751/pci.c
3 *
4 * Author: Ian DaSilva (idasilva@mvista.com)
5 *
6 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 *
11 * PCI initialization for the Hitachi SH7751 Solution Engine board (MS7751SE01)
12 */
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pci.h>
19
20#include <asm/io.h>
21#include "../../../drivers/pci/pci-sh7751.h"
22
23#define PCIMCR_MRSET_OFF 0xBFFFFFFF
24#define PCIMCR_RFSH_OFF 0xFFFFFFFB
25
26/*
27 * Only long word accesses of the PCIC's internal local registers and the
28 * configuration registers from the CPU is supported.
29 */
30#define PCIC_WRITE(x,v) writel((v), PCI_REG(x))
31#define PCIC_READ(x) readl(PCI_REG(x))
32
33/*
34 * Description: This function sets up and initializes the pcic, sets
35 * up the BARS, maps the DRAM into the address space etc, etc.
36 */
37int __init pcibios_init_platform(void)
38{
39 unsigned long bcr1, wcr1, wcr2, wcr3, mcr;
40 unsigned short bcr2;
41
42 /*
43 * Initialize the slave bus controller on the pcic. The values used
44 * here should not be hardcoded, but they should be taken from the bsc
45 * on the processor, to make this function as generic as possible.
46 * (i.e. Another sbc may usr different SDRAM timing settings -- in order
47 * for the pcic to work, its settings need to be exactly the same.)
48 */
49 bcr1 = (*(volatile unsigned long*)(SH7751_BCR1));
50 bcr2 = (*(volatile unsigned short*)(SH7751_BCR2));
51 wcr1 = (*(volatile unsigned long*)(SH7751_WCR1));
52 wcr2 = (*(volatile unsigned long*)(SH7751_WCR2));
53 wcr3 = (*(volatile unsigned long*)(SH7751_WCR3));
54 mcr = (*(volatile unsigned long*)(SH7751_MCR));
55
56 bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */
57 (*(volatile unsigned long*)(SH7751_BCR1)) = bcr1;
58
59 bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
60 PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */
61 PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */
62 PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */
63 PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */
64 PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */
65 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
66 PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */
67
68
69 /* Enable all interrupts, so we know what to fix */
70 PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff);
71 PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f);
72
73 /* Set up standard PCI config registers */
74 PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */
75 PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */
76 PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */
77 PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */
78 PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */
79 PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */
80 PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */
81 PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */
82 PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */
83 PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */
84
85 /* Now turn it on... */
86 PCIC_WRITE(SH7751_PCICR, 0xa5000001);
87
88 /*
89 * Set PCIMBR and PCIIOBR here, assuming a single window
90 * (16M MEM, 256K IO) is enough. If a larger space is
91 * needed, the readx/writex and inx/outx functions will
92 * have to do more (e.g. setting registers for each call).
93 */
94
95 /*
96 * Set the MBR so PCI address is one-to-one with window,
97 * meaning all calls go straight through... use BUG_ON to
98 * catch erroneous assumption.
99 */
100 BUG_ON(PCIBIOS_MIN_MEM != SH7751_PCI_MEMORY_BASE);
101
102 PCIC_WRITE(SH7751_PCIMBR, PCIBIOS_MIN_MEM);
103
104 /* Set IOBR for window containing area specified in pci.h */
105 PCIC_WRITE(SH7751_PCIIOBR, (PCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK));
106
107 /* All done, may as well say so... */
108 printk("SH7751 PCI: Finished initialization of the PCI controller\n");
109
110 return 1;
111}
112
113int __init pcibios_map_platform_irq(u8 slot, u8 pin)
114{
115 switch (slot) {
116 case 0: return 13;
117 case 1: return 13; /* AMD Ethernet controller */
118 case 2: return -1;
119 case 3: return -1;
120 case 4: return -1;
121 default:
122 printk("PCI: Bad IRQ mapping request for slot %d\n", slot);
123 return -1;
124 }
125}
126
127static struct resource sh7751_io_resource = {
128 .name = "SH7751 IO",
129 .start = SH7751_PCI_IO_BASE,
130 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
131 .flags = IORESOURCE_IO
132};
133
134static struct resource sh7751_mem_resource = {
135 .name = "SH7751 mem",
136 .start = SH7751_PCI_MEMORY_BASE,
137 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
138 .flags = IORESOURCE_MEM
139};
140
141extern struct pci_ops sh7751_pci_ops;
142
143struct pci_channel board_pci_channels[] = {
144 { &sh7751_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
145 { NULL, NULL, NULL, 0, 0 },
146};
147
diff --git a/arch/sh/boards/mach-se/7780/irq.c b/arch/sh/boards/mach-se/7780/irq.c
index 66ad292c9fc3..b8d43b638fcf 100644
--- a/arch/sh/boards/mach-se/7780/irq.c
+++ b/arch/sh/boards/mach-se/7780/irq.c
@@ -12,10 +12,13 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <asm/irq.h> 15#include <linux/irq.h>
16#include <asm/io.h> 16#include <linux/io.h>
17#include <mach-se/mach/se7780.h> 17#include <mach-se/mach/se7780.h>
18 18
19#define INTC_BASE 0xffd00000
20#define INTC_ICR1 (INTC_BASE+0x1c)
21
19/* 22/*
20 * Initialize IRQ setting 23 * Initialize IRQ setting
21 */ 24 */
@@ -43,4 +46,24 @@ void __init init_se7780_IRQ(void)
43 ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3); 46 ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
44 47
45 plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */ 48 plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */
49
50 /* ICR1: detect low level(for 2ndcut) */
51 ctrl_outl(0xAAAA0000, INTC_ICR1);
52
53 /*
54 * FPGA PCISEL register initialize
55 *
56 * CPU || SLOT1 | SLOT2 | S-ATA | USB
57 * -------------------------------------
58 * INTA || INTA | INTD | -- | INTB
59 * -------------------------------------
60 * INTB || INTB | INTA | -- | INTC
61 * -------------------------------------
62 * INTC || INTC | INTB | INTA | --
63 * -------------------------------------
64 * INTD || INTD | INTC | -- | INTA
65 * -------------------------------------
66 */
67 ctrl_outw(0x0013, FPGA_PCI_INTSEL1);
68 ctrl_outw(0xE402, FPGA_PCI_INTSEL2);
46} 69}
diff --git a/arch/sh/boards/mach-snapgear/io.c b/arch/sh/boards/mach-snapgear/io.c
index 0f4824264557..476650e42dbc 100644
--- a/arch/sh/boards/mach-snapgear/io.c
+++ b/arch/sh/boards/mach-snapgear/io.c
@@ -36,8 +36,6 @@ unsigned char snapgear_inb(unsigned long port)
36{ 36{
37 if (PXSEG(port)) 37 if (PXSEG(port))
38 return *(volatile unsigned char *)port; 38 return *(volatile unsigned char *)port;
39 else if (is_pci_ioaddr(port))
40 return *(volatile unsigned char *)pci_ioaddr(port);
41 else 39 else
42 return (*port2adr(port)) & 0xff; 40 return (*port2adr(port)) & 0xff;
43} 41}
@@ -48,8 +46,6 @@ unsigned char snapgear_inb_p(unsigned long port)
48 46
49 if (PXSEG(port)) 47 if (PXSEG(port))
50 v = *(volatile unsigned char *)port; 48 v = *(volatile unsigned char *)port;
51 else if (is_pci_ioaddr(port))
52 v = *(volatile unsigned char *)pci_ioaddr(port);
53 else 49 else
54 v = (*port2adr(port))&0xff; 50 v = (*port2adr(port))&0xff;
55 ctrl_delay(); 51 ctrl_delay();
@@ -60,8 +56,6 @@ unsigned short snapgear_inw(unsigned long port)
60{ 56{
61 if (PXSEG(port)) 57 if (PXSEG(port))
62 return *(volatile unsigned short *)port; 58 return *(volatile unsigned short *)port;
63 else if (is_pci_ioaddr(port))
64 return *(volatile unsigned short *)pci_ioaddr(port);
65 else if (port >= 0x2000) 59 else if (port >= 0x2000)
66 return *port2adr(port); 60 return *port2adr(port);
67 else 61 else
@@ -73,8 +67,6 @@ unsigned int snapgear_inl(unsigned long port)
73{ 67{
74 if (PXSEG(port)) 68 if (PXSEG(port))
75 return *(volatile unsigned long *)port; 69 return *(volatile unsigned long *)port;
76 else if (is_pci_ioaddr(port))
77 return *(volatile unsigned int *)pci_ioaddr(port);
78 else if (port >= 0x2000) 70 else if (port >= 0x2000)
79 return *port2adr(port); 71 return *port2adr(port);
80 else 72 else
@@ -87,8 +79,6 @@ void snapgear_outb(unsigned char value, unsigned long port)
87 79
88 if (PXSEG(port)) 80 if (PXSEG(port))
89 *(volatile unsigned char *)port = value; 81 *(volatile unsigned char *)port = value;
90 else if (is_pci_ioaddr(port))
91 *((unsigned char*)pci_ioaddr(port)) = value;
92 else 82 else
93 *(port2adr(port)) = value; 83 *(port2adr(port)) = value;
94} 84}
@@ -97,8 +87,6 @@ void snapgear_outb_p(unsigned char value, unsigned long port)
97{ 87{
98 if (PXSEG(port)) 88 if (PXSEG(port))
99 *(volatile unsigned char *)port = value; 89 *(volatile unsigned char *)port = value;
100 else if (is_pci_ioaddr(port))
101 *((unsigned char*)pci_ioaddr(port)) = value;
102 else 90 else
103 *(port2adr(port)) = value; 91 *(port2adr(port)) = value;
104 ctrl_delay(); 92 ctrl_delay();
@@ -108,8 +96,6 @@ void snapgear_outw(unsigned short value, unsigned long port)
108{ 96{
109 if (PXSEG(port)) 97 if (PXSEG(port))
110 *(volatile unsigned short *)port = value; 98 *(volatile unsigned short *)port = value;
111 else if (is_pci_ioaddr(port))
112 *((unsigned short *)pci_ioaddr(port)) = value;
113 else if (port >= 0x2000) 99 else if (port >= 0x2000)
114 *port2adr(port) = value; 100 *port2adr(port) = value;
115 else 101 else
@@ -120,8 +106,6 @@ void snapgear_outl(unsigned int value, unsigned long port)
120{ 106{
121 if (PXSEG(port)) 107 if (PXSEG(port))
122 *(volatile unsigned long *)port = value; 108 *(volatile unsigned long *)port = value;
123 else if (is_pci_ioaddr(port))
124 *((unsigned long*)pci_ioaddr(port)) = value;
125 else 109 else
126 maybebadio(port); 110 maybebadio(port);
127} 111}
diff --git a/arch/sh/boards/mach-systemh/io.c b/arch/sh/boards/mach-systemh/io.c
index dec3db0ee933..15577ff1f715 100644
--- a/arch/sh/boards/mach-systemh/io.c
+++ b/arch/sh/boards/mach-systemh/io.c
@@ -35,8 +35,6 @@ unsigned char sh7751systemh_inb(unsigned long port)
35{ 35{
36 if (PXSEG(port)) 36 if (PXSEG(port))
37 return *(volatile unsigned char *)port; 37 return *(volatile unsigned char *)port;
38 else if (is_pci_ioaddr(port))
39 return *(volatile unsigned char *)pci_ioaddr(port);
40 else if (port <= 0x3F1) 38 else if (port <= 0x3F1)
41 return *(volatile unsigned char *)ETHER_IOMAP(port); 39 return *(volatile unsigned char *)ETHER_IOMAP(port);
42 else 40 else
@@ -49,8 +47,6 @@ unsigned char sh7751systemh_inb_p(unsigned long port)
49 47
50 if (PXSEG(port)) 48 if (PXSEG(port))
51 v = *(volatile unsigned char *)port; 49 v = *(volatile unsigned char *)port;
52 else if (is_pci_ioaddr(port))
53 v = *(volatile unsigned char *)pci_ioaddr(port);
54 else if (port <= 0x3F1) 50 else if (port <= 0x3F1)
55 v = *(volatile unsigned char *)ETHER_IOMAP(port); 51 v = *(volatile unsigned char *)ETHER_IOMAP(port);
56 else 52 else
@@ -63,8 +59,6 @@ unsigned short sh7751systemh_inw(unsigned long port)
63{ 59{
64 if (PXSEG(port)) 60 if (PXSEG(port))
65 return *(volatile unsigned short *)port; 61 return *(volatile unsigned short *)port;
66 else if (is_pci_ioaddr(port))
67 return *(volatile unsigned short *)pci_ioaddr(port);
68 else if (port >= 0x2000) 62 else if (port >= 0x2000)
69 return *port2adr(port); 63 return *port2adr(port);
70 else if (port <= 0x3F1) 64 else if (port <= 0x3F1)
@@ -78,8 +72,6 @@ unsigned int sh7751systemh_inl(unsigned long port)
78{ 72{
79 if (PXSEG(port)) 73 if (PXSEG(port))
80 return *(volatile unsigned long *)port; 74 return *(volatile unsigned long *)port;
81 else if (is_pci_ioaddr(port))
82 return *(volatile unsigned int *)pci_ioaddr(port);
83 else if (port >= 0x2000) 75 else if (port >= 0x2000)
84 return *port2adr(port); 76 return *port2adr(port);
85 else if (port <= 0x3F1) 77 else if (port <= 0x3F1)
@@ -94,8 +86,6 @@ void sh7751systemh_outb(unsigned char value, unsigned long port)
94 86
95 if (PXSEG(port)) 87 if (PXSEG(port))
96 *(volatile unsigned char *)port = value; 88 *(volatile unsigned char *)port = value;
97 else if (is_pci_ioaddr(port))
98 *((unsigned char*)pci_ioaddr(port)) = value;
99 else if (port <= 0x3F1) 89 else if (port <= 0x3F1)
100 *(volatile unsigned char *)ETHER_IOMAP(port) = value; 90 *(volatile unsigned char *)ETHER_IOMAP(port) = value;
101 else 91 else
@@ -106,8 +96,6 @@ void sh7751systemh_outb_p(unsigned char value, unsigned long port)
106{ 96{
107 if (PXSEG(port)) 97 if (PXSEG(port))
108 *(volatile unsigned char *)port = value; 98 *(volatile unsigned char *)port = value;
109 else if (is_pci_ioaddr(port))
110 *((unsigned char*)pci_ioaddr(port)) = value;
111 else if (port <= 0x3F1) 99 else if (port <= 0x3F1)
112 *(volatile unsigned char *)ETHER_IOMAP(port) = value; 100 *(volatile unsigned char *)ETHER_IOMAP(port) = value;
113 else 101 else
@@ -119,8 +107,6 @@ void sh7751systemh_outw(unsigned short value, unsigned long port)
119{ 107{
120 if (PXSEG(port)) 108 if (PXSEG(port))
121 *(volatile unsigned short *)port = value; 109 *(volatile unsigned short *)port = value;
122 else if (is_pci_ioaddr(port))
123 *((unsigned short *)pci_ioaddr(port)) = value;
124 else if (port >= 0x2000) 110 else if (port >= 0x2000)
125 *port2adr(port) = value; 111 *port2adr(port) = value;
126 else if (port <= 0x3F1) 112 else if (port <= 0x3F1)
@@ -133,8 +119,6 @@ void sh7751systemh_outl(unsigned int value, unsigned long port)
133{ 119{
134 if (PXSEG(port)) 120 if (PXSEG(port))
135 *(volatile unsigned long *)port = value; 121 *(volatile unsigned long *)port = value;
136 else if (is_pci_ioaddr(port))
137 *((unsigned long*)pci_ioaddr(port)) = value;
138 else 122 else
139 maybebadio(port); 123 maybebadio(port);
140} 124}
diff --git a/arch/sh/boards/mach-titan/io.c b/arch/sh/boards/mach-titan/io.c
index 4badad4c6f30..0130e9826aca 100644
--- a/arch/sh/boards/mach-titan/io.c
+++ b/arch/sh/boards/mach-titan/io.c
@@ -17,8 +17,6 @@ u8 titan_inb(unsigned long port)
17{ 17{
18 if (PXSEG(port)) 18 if (PXSEG(port))
19 return ctrl_inb(port); 19 return ctrl_inb(port);
20 else if (is_pci_ioaddr(port))
21 return ctrl_inb(pci_ioaddr(port));
22 return ctrl_inw(port2adr(port)) & 0xff; 20 return ctrl_inw(port2adr(port)) & 0xff;
23} 21}
24 22
@@ -28,8 +26,6 @@ u8 titan_inb_p(unsigned long port)
28 26
29 if (PXSEG(port)) 27 if (PXSEG(port))
30 v = ctrl_inb(port); 28 v = ctrl_inb(port);
31 else if (is_pci_ioaddr(port))
32 v = ctrl_inb(pci_ioaddr(port));
33 else 29 else
34 v = ctrl_inw(port2adr(port)) & 0xff; 30 v = ctrl_inw(port2adr(port)) & 0xff;
35 ctrl_delay(); 31 ctrl_delay();
@@ -40,8 +36,6 @@ u16 titan_inw(unsigned long port)
40{ 36{
41 if (PXSEG(port)) 37 if (PXSEG(port))
42 return ctrl_inw(port); 38 return ctrl_inw(port);
43 else if (is_pci_ioaddr(port))
44 return ctrl_inw(pci_ioaddr(port));
45 else if (port >= 0x2000) 39 else if (port >= 0x2000)
46 return ctrl_inw(port2adr(port)); 40 return ctrl_inw(port2adr(port));
47 else 41 else
@@ -53,8 +47,6 @@ u32 titan_inl(unsigned long port)
53{ 47{
54 if (PXSEG(port)) 48 if (PXSEG(port))
55 return ctrl_inl(port); 49 return ctrl_inl(port);
56 else if (is_pci_ioaddr(port))
57 return ctrl_inl(pci_ioaddr(port));
58 else if (port >= 0x2000) 50 else if (port >= 0x2000)
59 return ctrl_inw(port2adr(port)); 51 return ctrl_inw(port2adr(port));
60 else 52 else
@@ -66,8 +58,6 @@ void titan_outb(u8 value, unsigned long port)
66{ 58{
67 if (PXSEG(port)) 59 if (PXSEG(port))
68 ctrl_outb(value, port); 60 ctrl_outb(value, port);
69 else if (is_pci_ioaddr(port))
70 ctrl_outb(value, pci_ioaddr(port));
71 else 61 else
72 ctrl_outw(value, port2adr(port)); 62 ctrl_outw(value, port2adr(port));
73} 63}
@@ -76,8 +66,6 @@ void titan_outb_p(u8 value, unsigned long port)
76{ 66{
77 if (PXSEG(port)) 67 if (PXSEG(port))
78 ctrl_outb(value, port); 68 ctrl_outb(value, port);
79 else if (is_pci_ioaddr(port))
80 ctrl_outb(value, pci_ioaddr(port));
81 else 69 else
82 ctrl_outw(value, port2adr(port)); 70 ctrl_outw(value, port2adr(port));
83 ctrl_delay(); 71 ctrl_delay();
@@ -87,8 +75,6 @@ void titan_outw(u16 value, unsigned long port)
87{ 75{
88 if (PXSEG(port)) 76 if (PXSEG(port))
89 ctrl_outw(value, port); 77 ctrl_outw(value, port);
90 else if (is_pci_ioaddr(port))
91 ctrl_outw(value, pci_ioaddr(port));
92 else if (port >= 0x2000) 78 else if (port >= 0x2000)
93 ctrl_outw(value, port2adr(port)); 79 ctrl_outw(value, port2adr(port));
94 else 80 else
@@ -99,8 +85,6 @@ void titan_outl(u32 value, unsigned long port)
99{ 85{
100 if (PXSEG(port)) 86 if (PXSEG(port))
101 ctrl_outl(value, port); 87 ctrl_outl(value, port);
102 else if (is_pci_ioaddr(port))
103 ctrl_outl(value, pci_ioaddr(port));
104 else 88 else
105 maybebadio(port); 89 maybebadio(port);
106} 90}
@@ -117,10 +101,8 @@ void titan_outsl(unsigned long port, const void *src, unsigned long count)
117 101
118void __iomem *titan_ioport_map(unsigned long port, unsigned int size) 102void __iomem *titan_ioport_map(unsigned long port, unsigned int size)
119{ 103{
120 if (PXSEG(port) || is_pci_memaddr(port)) 104 if (PXSEG(port))
121 return (void __iomem *)port; 105 return (void __iomem *)port;
122 else if (is_pci_ioaddr(port))
123 return (void __iomem *)pci_ioaddr(port);
124 106
125 return (void __iomem *)port2adr(port); 107 return (void __iomem *)port2adr(port);
126} 108}
diff --git a/arch/sh/configs/sh7724_generic_defconfig b/arch/sh/configs/sh7724_generic_defconfig
new file mode 100644
index 000000000000..268d04ed8cdd
--- /dev/null
+++ b/arch/sh/configs/sh7724_generic_defconfig
@@ -0,0 +1,707 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.30-rc2
4# Thu Apr 16 15:42:20 2009
5#
6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
10CONFIG_RWSEM_GENERIC_SPINLOCK=y
11CONFIG_GENERIC_BUG=y
12CONFIG_GENERIC_FIND_NEXT_BIT=y
13CONFIG_GENERIC_HWEIGHT=y
14CONFIG_GENERIC_HARDIRQS=y
15CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
16CONFIG_GENERIC_IRQ_PROBE=y
17# CONFIG_GENERIC_GPIO is not set
18CONFIG_GENERIC_TIME=y
19CONFIG_GENERIC_CLOCKEVENTS=y
20CONFIG_ARCH_SUSPEND_POSSIBLE=y
21CONFIG_ARCH_HIBERNATION_POSSIBLE=y
22CONFIG_SYS_SUPPORTS_CMT=y
23CONFIG_STACKTRACE_SUPPORT=y
24CONFIG_LOCKDEP_SUPPORT=y
25CONFIG_HAVE_LATENCYTOP_SUPPORT=y
26# CONFIG_ARCH_HAS_ILOG2_U32 is not set
27# CONFIG_ARCH_HAS_ILOG2_U64 is not set
28CONFIG_ARCH_NO_VIRT_TO_BUS=y
29CONFIG_ARCH_HAS_DEFAULT_IDLE=y
30CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
31
32#
33# General setup
34#
35CONFIG_EXPERIMENTAL=y
36CONFIG_BROKEN_ON_SMP=y
37CONFIG_INIT_ENV_ARG_LIMIT=32
38CONFIG_LOCALVERSION=""
39# CONFIG_LOCALVERSION_AUTO is not set
40CONFIG_SWAP=y
41CONFIG_SYSVIPC=y
42CONFIG_SYSVIPC_SYSCTL=y
43# CONFIG_BSD_PROCESS_ACCT is not set
44
45#
46# RCU Subsystem
47#
48# CONFIG_CLASSIC_RCU is not set
49CONFIG_TREE_RCU=y
50# CONFIG_PREEMPT_RCU is not set
51# CONFIG_RCU_TRACE is not set
52CONFIG_RCU_FANOUT=32
53# CONFIG_RCU_FANOUT_EXACT is not set
54# CONFIG_TREE_RCU_TRACE is not set
55# CONFIG_PREEMPT_RCU_TRACE is not set
56# CONFIG_IKCONFIG is not set
57CONFIG_LOG_BUF_SHIFT=17
58CONFIG_GROUP_SCHED=y
59CONFIG_FAIR_GROUP_SCHED=y
60CONFIG_RT_GROUP_SCHED=y
61CONFIG_USER_SCHED=y
62# CONFIG_CGROUP_SCHED is not set
63CONFIG_CGROUPS=y
64# CONFIG_CGROUP_DEBUG is not set
65# CONFIG_CGROUP_NS is not set
66# CONFIG_CGROUP_FREEZER is not set
67# CONFIG_CGROUP_DEVICE is not set
68# CONFIG_CPUSETS is not set
69# CONFIG_CGROUP_CPUACCT is not set
70# CONFIG_RESOURCE_COUNTERS is not set
71# CONFIG_RELAY is not set
72# CONFIG_NAMESPACES is not set
73# CONFIG_BLK_DEV_INITRD is not set
74CONFIG_CC_OPTIMIZE_FOR_SIZE=y
75CONFIG_SYSCTL=y
76CONFIG_ANON_INODES=y
77CONFIG_EMBEDDED=y
78# CONFIG_UID16 is not set
79CONFIG_SYSCTL_SYSCALL=y
80CONFIG_KALLSYMS=y
81# CONFIG_KALLSYMS_EXTRA_PASS is not set
82# CONFIG_STRIP_ASM_SYMS is not set
83CONFIG_HOTPLUG=y
84CONFIG_PRINTK=y
85CONFIG_BUG=y
86CONFIG_ELF_CORE=y
87CONFIG_BASE_FULL=y
88CONFIG_FUTEX=y
89CONFIG_EPOLL=y
90CONFIG_SIGNALFD=y
91CONFIG_TIMERFD=y
92CONFIG_EVENTFD=y
93CONFIG_SHMEM=y
94CONFIG_AIO=y
95CONFIG_VM_EVENT_COUNTERS=y
96# CONFIG_COMPAT_BRK is not set
97# CONFIG_SLAB is not set
98CONFIG_SLUB=y
99# CONFIG_SLOB is not set
100CONFIG_PROFILING=y
101CONFIG_TRACEPOINTS=y
102# CONFIG_MARKERS is not set
103CONFIG_OPROFILE=y
104CONFIG_HAVE_OPROFILE=y
105CONFIG_HAVE_IOREMAP_PROT=y
106CONFIG_HAVE_KPROBES=y
107CONFIG_HAVE_KRETPROBES=y
108CONFIG_HAVE_ARCH_TRACEHOOK=y
109CONFIG_HAVE_CLK=y
110CONFIG_HAVE_DMA_API_DEBUG=y
111# CONFIG_SLOW_WORK is not set
112CONFIG_HAVE_GENERIC_DMA_COHERENT=y
113CONFIG_RT_MUTEXES=y
114CONFIG_BASE_SMALL=0
115# CONFIG_MODULES is not set
116CONFIG_BLOCK=y
117# CONFIG_LBD is not set
118# CONFIG_BLK_DEV_BSG is not set
119# CONFIG_BLK_DEV_INTEGRITY is not set
120
121#
122# IO Schedulers
123#
124CONFIG_IOSCHED_NOOP=y
125CONFIG_IOSCHED_AS=y
126CONFIG_IOSCHED_DEADLINE=y
127CONFIG_IOSCHED_CFQ=y
128CONFIG_DEFAULT_AS=y
129# CONFIG_DEFAULT_DEADLINE is not set
130# CONFIG_DEFAULT_CFQ is not set
131# CONFIG_DEFAULT_NOOP is not set
132CONFIG_DEFAULT_IOSCHED="anticipatory"
133CONFIG_FREEZER=y
134
135#
136# System type
137#
138CONFIG_CPU_SH4=y
139CONFIG_CPU_SH4A=y
140CONFIG_CPU_SHX2=y
141CONFIG_ARCH_SHMOBILE=y
142# CONFIG_CPU_SUBTYPE_SH7619 is not set
143# CONFIG_CPU_SUBTYPE_SH7201 is not set
144# CONFIG_CPU_SUBTYPE_SH7203 is not set
145# CONFIG_CPU_SUBTYPE_SH7206 is not set
146# CONFIG_CPU_SUBTYPE_SH7263 is not set
147# CONFIG_CPU_SUBTYPE_MXG is not set
148# CONFIG_CPU_SUBTYPE_SH7705 is not set
149# CONFIG_CPU_SUBTYPE_SH7706 is not set
150# CONFIG_CPU_SUBTYPE_SH7707 is not set
151# CONFIG_CPU_SUBTYPE_SH7708 is not set
152# CONFIG_CPU_SUBTYPE_SH7709 is not set
153# CONFIG_CPU_SUBTYPE_SH7710 is not set
154# CONFIG_CPU_SUBTYPE_SH7712 is not set
155# CONFIG_CPU_SUBTYPE_SH7720 is not set
156# CONFIG_CPU_SUBTYPE_SH7721 is not set
157# CONFIG_CPU_SUBTYPE_SH7750 is not set
158# CONFIG_CPU_SUBTYPE_SH7091 is not set
159# CONFIG_CPU_SUBTYPE_SH7750R is not set
160# CONFIG_CPU_SUBTYPE_SH7750S is not set
161# CONFIG_CPU_SUBTYPE_SH7751 is not set
162# CONFIG_CPU_SUBTYPE_SH7751R is not set
163# CONFIG_CPU_SUBTYPE_SH7760 is not set
164# CONFIG_CPU_SUBTYPE_SH4_202 is not set
165# CONFIG_CPU_SUBTYPE_SH7723 is not set
166CONFIG_CPU_SUBTYPE_SH7724=y
167# CONFIG_CPU_SUBTYPE_SH7763 is not set
168# CONFIG_CPU_SUBTYPE_SH7770 is not set
169# CONFIG_CPU_SUBTYPE_SH7780 is not set
170# CONFIG_CPU_SUBTYPE_SH7785 is not set
171# CONFIG_CPU_SUBTYPE_SH7786 is not set
172# CONFIG_CPU_SUBTYPE_SHX3 is not set
173# CONFIG_CPU_SUBTYPE_SH7343 is not set
174# CONFIG_CPU_SUBTYPE_SH7722 is not set
175# CONFIG_CPU_SUBTYPE_SH7366 is not set
176
177#
178# Memory management options
179#
180CONFIG_QUICKLIST=y
181CONFIG_MMU=y
182CONFIG_PAGE_OFFSET=0x80000000
183CONFIG_MEMORY_START=0x08000000
184CONFIG_MEMORY_SIZE=0x04000000
185CONFIG_29BIT=y
186# CONFIG_X2TLB is not set
187CONFIG_VSYSCALL=y
188CONFIG_ARCH_FLATMEM_ENABLE=y
189CONFIG_ARCH_SPARSEMEM_ENABLE=y
190CONFIG_ARCH_SPARSEMEM_DEFAULT=y
191CONFIG_MAX_ACTIVE_REGIONS=1
192CONFIG_ARCH_POPULATES_NODE_MAP=y
193CONFIG_ARCH_SELECT_MEMORY_MODEL=y
194CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
195CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
196CONFIG_PAGE_SIZE_4KB=y
197# CONFIG_PAGE_SIZE_8KB is not set
198# CONFIG_PAGE_SIZE_16KB is not set
199# CONFIG_PAGE_SIZE_64KB is not set
200CONFIG_ENTRY_OFFSET=0x00001000
201CONFIG_SELECT_MEMORY_MODEL=y
202# CONFIG_FLATMEM_MANUAL is not set
203# CONFIG_DISCONTIGMEM_MANUAL is not set
204CONFIG_SPARSEMEM_MANUAL=y
205CONFIG_SPARSEMEM=y
206CONFIG_HAVE_MEMORY_PRESENT=y
207CONFIG_SPARSEMEM_STATIC=y
208
209#
210# Memory hotplug is currently incompatible with Software Suspend
211#
212CONFIG_PAGEFLAGS_EXTENDED=y
213CONFIG_SPLIT_PTLOCK_CPUS=4
214CONFIG_MIGRATION=y
215# CONFIG_PHYS_ADDR_T_64BIT is not set
216CONFIG_ZONE_DMA_FLAG=0
217CONFIG_NR_QUICK=2
218CONFIG_UNEVICTABLE_LRU=y
219CONFIG_HAVE_MLOCK=y
220CONFIG_HAVE_MLOCKED_PAGE_BIT=y
221
222#
223# Cache configuration
224#
225CONFIG_CACHE_WRITEBACK=y
226# CONFIG_CACHE_WRITETHROUGH is not set
227# CONFIG_CACHE_OFF is not set
228
229#
230# Processor features
231#
232CONFIG_CPU_LITTLE_ENDIAN=y
233# CONFIG_CPU_BIG_ENDIAN is not set
234CONFIG_SH_FPU=y
235# CONFIG_SH_STORE_QUEUES is not set
236CONFIG_CPU_HAS_INTEVT=y
237CONFIG_CPU_HAS_SR_RB=y
238CONFIG_CPU_HAS_PTEA=y
239CONFIG_CPU_HAS_FPU=y
240
241#
242# Board support
243#
244
245#
246# Timer and clock configuration
247#
248CONFIG_SH_TMU=y
249CONFIG_SH_TIMER_CMT=y
250CONFIG_SH_TIMER_IRQ=16
251CONFIG_SH_PCLK_FREQ=41666666
252CONFIG_TICK_ONESHOT=y
253CONFIG_NO_HZ=y
254CONFIG_HIGH_RES_TIMERS=y
255CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
256
257#
258# CPU Frequency scaling
259#
260CONFIG_CPU_FREQ=y
261CONFIG_CPU_FREQ_TABLE=y
262# CONFIG_CPU_FREQ_DEBUG is not set
263CONFIG_CPU_FREQ_STAT=y
264# CONFIG_CPU_FREQ_STAT_DETAILS is not set
265CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
266# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
267# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
268# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
269# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
270CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
271# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
272# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
273# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
274# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
275CONFIG_SH_CPU_FREQ=y
276
277#
278# DMA support
279#
280# CONFIG_SH_DMA is not set
281
282#
283# Companion Chips
284#
285
286#
287# Additional SuperH Device Drivers
288#
289# CONFIG_HEARTBEAT is not set
290# CONFIG_PUSH_SWITCH is not set
291
292#
293# Kernel features
294#
295# CONFIG_HZ_100 is not set
296CONFIG_HZ_250=y
297# CONFIG_HZ_300 is not set
298# CONFIG_HZ_1000 is not set
299CONFIG_HZ=250
300CONFIG_SCHED_HRTICK=y
301CONFIG_KEXEC=y
302# CONFIG_CRASH_DUMP is not set
303CONFIG_KEXEC_JUMP=y
304CONFIG_PREEMPT_NONE=y
305# CONFIG_PREEMPT_VOLUNTARY is not set
306# CONFIG_PREEMPT is not set
307CONFIG_GUSA=y
308
309#
310# Boot options
311#
312CONFIG_ZERO_PAGE_OFFSET=0x00001000
313CONFIG_BOOT_LINK_OFFSET=0x00800000
314# CONFIG_CMDLINE_BOOL is not set
315
316#
317# Bus options
318#
319# CONFIG_ARCH_SUPPORTS_MSI is not set
320# CONFIG_PCCARD is not set
321
322#
323# Executable file formats
324#
325CONFIG_BINFMT_ELF=y
326# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
327# CONFIG_HAVE_AOUT is not set
328# CONFIG_BINFMT_MISC is not set
329
330#
331# Power management options (EXPERIMENTAL)
332#
333CONFIG_PM=y
334# CONFIG_PM_DEBUG is not set
335CONFIG_PM_SLEEP=y
336CONFIG_SUSPEND=y
337CONFIG_SUSPEND_FREEZER=y
338CONFIG_HIBERNATION=y
339CONFIG_PM_STD_PARTITION=""
340CONFIG_CPU_IDLE=y
341CONFIG_CPU_IDLE_GOV_LADDER=y
342CONFIG_CPU_IDLE_GOV_MENU=y
343# CONFIG_NET is not set
344
345#
346# Device Drivers
347#
348
349#
350# Generic Driver Options
351#
352CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
353CONFIG_STANDALONE=y
354# CONFIG_PREVENT_FIRMWARE_BUILD is not set
355CONFIG_FW_LOADER=y
356CONFIG_FIRMWARE_IN_KERNEL=y
357CONFIG_EXTRA_FIRMWARE=""
358# CONFIG_SYS_HYPERVISOR is not set
359# CONFIG_MTD is not set
360# CONFIG_PARPORT is not set
361CONFIG_BLK_DEV=y
362# CONFIG_BLK_DEV_COW_COMMON is not set
363# CONFIG_BLK_DEV_LOOP is not set
364# CONFIG_BLK_DEV_RAM is not set
365# CONFIG_CDROM_PKTCDVD is not set
366# CONFIG_BLK_DEV_HD is not set
367# CONFIG_MISC_DEVICES is not set
368CONFIG_HAVE_IDE=y
369# CONFIG_IDE is not set
370
371#
372# SCSI device support
373#
374# CONFIG_RAID_ATTRS is not set
375# CONFIG_SCSI is not set
376# CONFIG_SCSI_DMA is not set
377# CONFIG_SCSI_NETLINK is not set
378# CONFIG_ATA is not set
379# CONFIG_MD is not set
380# CONFIG_PHONE is not set
381
382#
383# Input device support
384#
385# CONFIG_INPUT is not set
386
387#
388# Hardware I/O ports
389#
390# CONFIG_SERIO is not set
391# CONFIG_GAMEPORT is not set
392
393#
394# Character devices
395#
396# CONFIG_VT is not set
397# CONFIG_DEVKMEM is not set
398# CONFIG_SERIAL_NONSTANDARD is not set
399
400#
401# Serial drivers
402#
403# CONFIG_SERIAL_8250 is not set
404
405#
406# Non-8250 serial port support
407#
408CONFIG_SERIAL_SH_SCI=y
409CONFIG_SERIAL_SH_SCI_NR_UARTS=6
410CONFIG_SERIAL_SH_SCI_CONSOLE=y
411CONFIG_SERIAL_CORE=y
412CONFIG_SERIAL_CORE_CONSOLE=y
413# CONFIG_UNIX98_PTYS is not set
414# CONFIG_LEGACY_PTYS is not set
415# CONFIG_IPMI_HANDLER is not set
416# CONFIG_HW_RANDOM is not set
417# CONFIG_R3964 is not set
418# CONFIG_RAW_DRIVER is not set
419# CONFIG_TCG_TPM is not set
420CONFIG_I2C=y
421CONFIG_I2C_BOARDINFO=y
422CONFIG_I2C_CHARDEV=y
423CONFIG_I2C_HELPER_AUTO=y
424
425#
426# I2C Hardware Bus support
427#
428
429#
430# I2C system bus drivers (mostly embedded / system-on-chip)
431#
432# CONFIG_I2C_OCORES is not set
433CONFIG_I2C_SH_MOBILE=y
434# CONFIG_I2C_SIMTEC is not set
435
436#
437# External I2C/SMBus adapter drivers
438#
439# CONFIG_I2C_PARPORT_LIGHT is not set
440# CONFIG_I2C_TAOS_EVM is not set
441
442#
443# Other I2C/SMBus bus drivers
444#
445# CONFIG_I2C_PCA_PLATFORM is not set
446
447#
448# Miscellaneous I2C Chip support
449#
450# CONFIG_DS1682 is not set
451# CONFIG_SENSORS_PCF8574 is not set
452# CONFIG_PCF8575 is not set
453# CONFIG_SENSORS_PCA9539 is not set
454# CONFIG_SENSORS_MAX6875 is not set
455# CONFIG_SENSORS_TSL2550 is not set
456# CONFIG_I2C_DEBUG_CORE is not set
457# CONFIG_I2C_DEBUG_ALGO is not set
458# CONFIG_I2C_DEBUG_BUS is not set
459# CONFIG_I2C_DEBUG_CHIP is not set
460# CONFIG_SPI is not set
461# CONFIG_W1 is not set
462# CONFIG_POWER_SUPPLY is not set
463# CONFIG_HWMON is not set
464# CONFIG_THERMAL is not set
465# CONFIG_THERMAL_HWMON is not set
466# CONFIG_WATCHDOG is not set
467CONFIG_SSB_POSSIBLE=y
468
469#
470# Sonics Silicon Backplane
471#
472# CONFIG_SSB is not set
473
474#
475# Multifunction device drivers
476#
477# CONFIG_MFD_CORE is not set
478# CONFIG_MFD_SM501 is not set
479# CONFIG_HTC_PASIC3 is not set
480# CONFIG_TWL4030_CORE is not set
481# CONFIG_MFD_TMIO is not set
482# CONFIG_PMIC_DA903X is not set
483# CONFIG_MFD_WM8400 is not set
484# CONFIG_MFD_WM8350_I2C is not set
485# CONFIG_MFD_PCF50633 is not set
486# CONFIG_REGULATOR is not set
487
488#
489# Multimedia devices
490#
491
492#
493# Multimedia core support
494#
495# CONFIG_VIDEO_DEV is not set
496# CONFIG_VIDEO_MEDIA is not set
497
498#
499# Multimedia drivers
500#
501# CONFIG_DAB is not set
502
503#
504# Graphics support
505#
506# CONFIG_VGASTATE is not set
507# CONFIG_VIDEO_OUTPUT_CONTROL is not set
508# CONFIG_FB is not set
509# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
510
511#
512# Display device support
513#
514# CONFIG_DISPLAY_SUPPORT is not set
515# CONFIG_SOUND is not set
516# CONFIG_USB_SUPPORT is not set
517# CONFIG_MMC is not set
518# CONFIG_MEMSTICK is not set
519# CONFIG_NEW_LEDS is not set
520# CONFIG_ACCESSIBILITY is not set
521CONFIG_RTC_LIB=y
522CONFIG_RTC_CLASS=y
523CONFIG_RTC_HCTOSYS=y
524CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
525# CONFIG_RTC_DEBUG is not set
526
527#
528# RTC interfaces
529#
530CONFIG_RTC_INTF_DEV=y
531# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
532# CONFIG_RTC_DRV_TEST is not set
533
534#
535# I2C RTC drivers
536#
537# CONFIG_RTC_DRV_DS1307 is not set
538# CONFIG_RTC_DRV_DS1374 is not set
539# CONFIG_RTC_DRV_DS1672 is not set
540# CONFIG_RTC_DRV_MAX6900 is not set
541# CONFIG_RTC_DRV_RS5C372 is not set
542# CONFIG_RTC_DRV_ISL1208 is not set
543# CONFIG_RTC_DRV_X1205 is not set
544# CONFIG_RTC_DRV_PCF8563 is not set
545# CONFIG_RTC_DRV_PCF8583 is not set
546# CONFIG_RTC_DRV_M41T80 is not set
547# CONFIG_RTC_DRV_S35390A is not set
548# CONFIG_RTC_DRV_FM3130 is not set
549# CONFIG_RTC_DRV_RX8581 is not set
550
551#
552# SPI RTC drivers
553#
554
555#
556# Platform RTC drivers
557#
558# CONFIG_RTC_DRV_DS1286 is not set
559# CONFIG_RTC_DRV_DS1511 is not set
560# CONFIG_RTC_DRV_DS1553 is not set
561# CONFIG_RTC_DRV_DS1742 is not set
562# CONFIG_RTC_DRV_STK17TA8 is not set
563# CONFIG_RTC_DRV_M48T86 is not set
564# CONFIG_RTC_DRV_M48T35 is not set
565# CONFIG_RTC_DRV_M48T59 is not set
566# CONFIG_RTC_DRV_BQ4802 is not set
567# CONFIG_RTC_DRV_V3020 is not set
568
569#
570# on-CPU RTC drivers
571#
572CONFIG_RTC_DRV_SH=y
573# CONFIG_DMADEVICES is not set
574# CONFIG_AUXDISPLAY is not set
575CONFIG_UIO=y
576# CONFIG_UIO_PDRV is not set
577CONFIG_UIO_PDRV_GENIRQ=y
578# CONFIG_UIO_SMX is not set
579# CONFIG_UIO_SERCOS3 is not set
580# CONFIG_STAGING is not set
581
582#
583# File systems
584#
585# CONFIG_EXT2_FS is not set
586# CONFIG_EXT3_FS is not set
587# CONFIG_EXT4_FS is not set
588# CONFIG_REISERFS_FS is not set
589# CONFIG_JFS_FS is not set
590# CONFIG_FS_POSIX_ACL is not set
591CONFIG_FILE_LOCKING=y
592# CONFIG_XFS_FS is not set
593# CONFIG_BTRFS_FS is not set
594# CONFIG_DNOTIFY is not set
595# CONFIG_INOTIFY is not set
596# CONFIG_QUOTA is not set
597# CONFIG_AUTOFS_FS is not set
598# CONFIG_AUTOFS4_FS is not set
599# CONFIG_FUSE_FS is not set
600
601#
602# Caches
603#
604# CONFIG_FSCACHE is not set
605
606#
607# CD-ROM/DVD Filesystems
608#
609# CONFIG_ISO9660_FS is not set
610# CONFIG_UDF_FS is not set
611
612#
613# DOS/FAT/NT Filesystems
614#
615# CONFIG_MSDOS_FS is not set
616# CONFIG_VFAT_FS is not set
617# CONFIG_NTFS_FS is not set
618
619#
620# Pseudo filesystems
621#
622# CONFIG_PROC_FS is not set
623# CONFIG_SYSFS is not set
624# CONFIG_TMPFS is not set
625# CONFIG_HUGETLBFS is not set
626# CONFIG_HUGETLB_PAGE is not set
627# CONFIG_MISC_FILESYSTEMS is not set
628
629#
630# Partition Types
631#
632# CONFIG_PARTITION_ADVANCED is not set
633CONFIG_MSDOS_PARTITION=y
634# CONFIG_NLS is not set
635
636#
637# Kernel hacking
638#
639CONFIG_TRACE_IRQFLAGS_SUPPORT=y
640# CONFIG_PRINTK_TIME is not set
641# CONFIG_ENABLE_WARN_DEPRECATED is not set
642# CONFIG_ENABLE_MUST_CHECK is not set
643CONFIG_FRAME_WARN=1024
644# CONFIG_MAGIC_SYSRQ is not set
645# CONFIG_UNUSED_SYMBOLS is not set
646CONFIG_DEBUG_FS=y
647# CONFIG_HEADERS_CHECK is not set
648# CONFIG_DEBUG_KERNEL is not set
649CONFIG_STACKTRACE=y
650# CONFIG_DEBUG_BUGVERBOSE is not set
651# CONFIG_DEBUG_MEMORY_INIT is not set
652# CONFIG_RCU_CPU_STALL_DETECTOR is not set
653# CONFIG_LATENCYTOP is not set
654# CONFIG_SYSCTL_SYSCALL_CHECK is not set
655CONFIG_NOP_TRACER=y
656CONFIG_HAVE_FUNCTION_TRACER=y
657CONFIG_HAVE_DYNAMIC_FTRACE=y
658CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
659CONFIG_RING_BUFFER=y
660CONFIG_TRACING=y
661CONFIG_TRACING_SUPPORT=y
662
663#
664# Tracers
665#
666# CONFIG_FUNCTION_TRACER is not set
667# CONFIG_IRQSOFF_TRACER is not set
668# CONFIG_SCHED_TRACER is not set
669# CONFIG_CONTEXT_SWITCH_TRACER is not set
670# CONFIG_EVENT_TRACER is not set
671# CONFIG_BOOT_TRACER is not set
672# CONFIG_TRACE_BRANCH_PROFILING is not set
673# CONFIG_STACK_TRACER is not set
674# CONFIG_KMEMTRACE is not set
675# CONFIG_WORKQUEUE_TRACER is not set
676# CONFIG_FTRACE_STARTUP_TEST is not set
677# CONFIG_DYNAMIC_DEBUG is not set
678# CONFIG_DMA_API_DEBUG is not set
679# CONFIG_SAMPLES is not set
680CONFIG_HAVE_ARCH_KGDB=y
681# CONFIG_SH_STANDARD_BIOS is not set
682# CONFIG_EARLY_SCIF_CONSOLE is not set
683# CONFIG_MORE_COMPILE_OPTIONS is not set
684
685#
686# Security options
687#
688# CONFIG_KEYS is not set
689# CONFIG_SECURITYFS is not set
690# CONFIG_SECURITY_FILE_CAPABILITIES is not set
691# CONFIG_CRYPTO is not set
692CONFIG_BINARY_PRINTF=y
693
694#
695# Library routines
696#
697CONFIG_GENERIC_FIND_LAST_BIT=y
698# CONFIG_CRC_CCITT is not set
699# CONFIG_CRC16 is not set
700# CONFIG_CRC_T10DIF is not set
701# CONFIG_CRC_ITU_T is not set
702# CONFIG_CRC32 is not set
703# CONFIG_CRC7 is not set
704# CONFIG_LIBCRC32C is not set
705CONFIG_HAS_IOMEM=y
706CONFIG_HAS_IOPORT=y
707CONFIG_HAS_DMA=y
diff --git a/arch/sh/drivers/pci/Kconfig b/arch/sh/drivers/pci/Kconfig
index 7e816ededed7..e8db585a6638 100644
--- a/arch/sh/drivers/pci/Kconfig
+++ b/arch/sh/drivers/pci/Kconfig
@@ -17,21 +17,3 @@ config SH_PCIDMA_NONCOHERENT
17 code will not have to flush the CPU's caches. If you have a PCI host 17 code will not have to flush the CPU's caches. If you have a PCI host
18 bridge integrated with your SH CPU, refer carefully to the chip specs 18 bridge integrated with your SH CPU, refer carefully to the chip specs
19 to see if you can say 'N' here. Otherwise, leave it as 'Y'. 19 to see if you can say 'N' here. Otherwise, leave it as 'Y'.
20
21# This is also board-specific
22config PCI_AUTO
23 bool
24 depends on PCI
25 default y
26
27config PCI_AUTO_UPDATE_RESOURCES
28 bool
29 depends on PCI_AUTO
30 default y if !SH_DREAMCAST
31 help
32 Selecting this option will cause the PCI auto code to leave your
33 BAR values alone. Otherwise they will be updated automatically. If
34 for some reason, you have a board that simply refuses to work
35 with its resources updated beyond what they are when the device
36 is powered up, set this to N. Everyone else will want this as Y.
37
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index 847e90894d1b..d2ffc477549a 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -1,9 +1,7 @@
1# 1#
2# Makefile for the PCI specific kernel interface routines under Linux. 2# Makefile for the PCI specific kernel interface routines under Linux.
3# 3#
4
5obj-y += pci.o 4obj-y += pci.o
6obj-$(CONFIG_PCI_AUTO) += pci-auto.o
7 5
8obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o 6obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o 7obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o
@@ -12,15 +10,17 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o 10obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o
13obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o 11obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o
14 12
15obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o 13obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \
16obj-$(CONFIG_SH_SECUREEDGE5410) += ops-snapgear.o 14 pci-dreamcast.o
17obj-$(CONFIG_SH_RTS7751R2D) += ops-rts7751r2d.o fixups-rts7751r2d.o 15obj-$(CONFIG_SH_SECUREEDGE5410) += fixups-snapgear.o
18obj-$(CONFIG_SH_SH03) += ops-sh03.o fixups-sh03.o 16obj-$(CONFIG_SH_7751_SOLUTION_ENGINE) += fixups-se7751.o
19obj-$(CONFIG_SH_HIGHLANDER) += ops-r7780rp.o fixups-r7780rp.o 17obj-$(CONFIG_SH_RTS7751R2D) += fixups-rts7751r2d.o
20obj-$(CONFIG_SH_SDK7780) += ops-sdk7780.o fixups-sdk7780.o 18obj-$(CONFIG_SH_SH03) += fixups-sh03.o
21obj-$(CONFIG_SH_TITAN) += ops-titan.o 19obj-$(CONFIG_SH_HIGHLANDER) += fixups-r7780rp.o
22obj-$(CONFIG_SH_LANDISK) += ops-landisk.o 20obj-$(CONFIG_SH_SH7785LCR) += fixups-r7780rp.o
23obj-$(CONFIG_SH_LBOX_RE2) += ops-lboxre2.o fixups-lboxre2.o 21obj-$(CONFIG_SH_SDK7780) += fixups-sdk7780.o
24obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += ops-se7780.o fixups-se7780.o 22obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += fixups-sdk7780.o
25obj-$(CONFIG_SH_CAYMAN) += ops-cayman.o 23obj-$(CONFIG_SH_TITAN) += fixups-titan.o
26obj-$(CONFIG_SH_SH7785LCR) += ops-sh7785lcr.o fixups-sh7785lcr.o 24obj-$(CONFIG_SH_LANDISK) += fixups-landisk.o
25obj-$(CONFIG_SH_LBOX_RE2) += fixups-rts7751r2d.o
26obj-$(CONFIG_SH_CAYMAN) += fixups-cayman.o
diff --git a/arch/sh/drivers/pci/ops-cayman.c b/arch/sh/drivers/pci/fixups-cayman.c
index 38ef76207af6..b68b61d22c6c 100644
--- a/arch/sh/drivers/pci/ops-cayman.c
+++ b/arch/sh/drivers/pci/fixups-cayman.c
@@ -75,15 +75,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin)
75 75
76 return result; 76 return result;
77} 77}
78
79struct pci_channel board_pci_channels[] = {
80 { &sh5_pci_ops, NULL, NULL, 0, 0xff },
81 { NULL, NULL, NULL, 0, 0 },
82};
83EXPORT_SYMBOL(board_pci_channels);
84
85int __init pcibios_init_platform(void)
86{
87 return sh5pci_init(__pa(memory_start),
88 __pa(memory_end) - __pa(memory_start));
89}
diff --git a/arch/sh/drivers/pci/fixups-dreamcast.c b/arch/sh/drivers/pci/fixups-dreamcast.c
index 2bf85cf091e1..ed7f489936f1 100644
--- a/arch/sh/drivers/pci/fixups-dreamcast.c
+++ b/arch/sh/drivers/pci/fixups-dreamcast.c
@@ -30,7 +30,7 @@
30 30
31static void __init gapspci_fixup_resources(struct pci_dev *dev) 31static void __init gapspci_fixup_resources(struct pci_dev *dev)
32{ 32{
33 struct pci_channel *p = board_pci_channels; 33 struct pci_channel *p = dev->sysdata;
34 34
35 printk(KERN_NOTICE "PCI: Fixing up device %s\n", pci_name(dev)); 35 printk(KERN_NOTICE "PCI: Fixing up device %s\n", pci_name(dev));
36 36
@@ -41,6 +41,13 @@ static void __init gapspci_fixup_resources(struct pci_dev *dev)
41 */ 41 */
42 dev->resource[1].start = p->io_resource->start + 0x100; 42 dev->resource[1].start = p->io_resource->start + 0x100;
43 dev->resource[1].end = dev->resource[1].start + 0x200 - 1; 43 dev->resource[1].end = dev->resource[1].start + 0x200 - 1;
44
45 /*
46 * This is not a normal BAR, prevent any attempts to move
47 * the BAR, as this will result in a bus lock.
48 */
49 dev->resource[1].flags |= IORESOURCE_PCI_FIXED;
50
44 /* 51 /*
45 * Redirect dma memory allocations to special memory window. 52 * Redirect dma memory allocations to special memory window.
46 */ 53 */
diff --git a/arch/sh/drivers/pci/ops-landisk.c b/arch/sh/drivers/pci/fixups-landisk.c
index bff09ecf3419..bb1a6bb5149e 100644
--- a/arch/sh/drivers/pci/ops-landisk.c
+++ b/arch/sh/drivers/pci/fixups-landisk.c
@@ -15,39 +15,6 @@
15#include <linux/pci.h> 15#include <linux/pci.h>
16#include "pci-sh4.h" 16#include "pci-sh4.h"
17 17
18static struct resource sh7751_io_resource = {
19 .name = "SH7751 IO",
20 .start = SH7751_PCI_IO_BASE,
21 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
22 .flags = IORESOURCE_IO
23};
24
25static struct resource sh7751_mem_resource = {
26 .name = "SH7751 mem",
27 .start = SH7751_PCI_MEMORY_BASE,
28 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
29 .flags = IORESOURCE_MEM
30};
31
32struct pci_channel board_pci_channels[] = {
33 {&sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0x3ff},
34 {NULL, NULL, NULL, 0, 0},
35};
36
37static struct sh4_pci_address_map sh7751_pci_map = {
38 .window0 = {
39 .base = SH7751_CS3_BASE_ADDR,
40 .size = (64 << 20), /* 64MB */
41 },
42
43 .flags = SH4_PCIC_NO_RESET,
44};
45
46int __init pcibios_init_platform(void)
47{
48 return sh7751_pcic_init(&sh7751_pci_map);
49}
50
51int pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) 18int pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
52{ 19{
53 /* 20 /*
diff --git a/arch/sh/drivers/pci/fixups-lboxre2.c b/arch/sh/drivers/pci/fixups-lboxre2.c
deleted file mode 100644
index 1c1d41255ec0..000000000000
--- a/arch/sh/drivers/pci/fixups-lboxre2.c
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * arch/sh/drivers/pci/fixups-lboxre2.c
3 *
4 * L-BOX RE2 PCI fixups
5 *
6 * Copyright (C) 2007 Nobuhiro Iwamatsu
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include "pci-sh4.h"
13
14#define PCIMCR_MRSET_OFF 0xBFFFFFFF
15#define PCIMCR_RFSH_OFF 0xFFFFFFFB
16
17int pci_fixup_pcic(void)
18{
19 unsigned long bcr1, mcr;
20
21 bcr1 = ctrl_inl(SH7751_BCR1);
22 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
23 pci_write_reg(bcr1, SH4_PCIBCR1);
24
25 /* Enable all interrupts, so we known what to fix */
26 pci_write_reg(0x0000c3ff, SH4_PCIINTM);
27 pci_write_reg(0x0000380f, SH4_PCIAINTM);
28 pci_write_reg(0xfb900047, SH7751_PCICONF1);
29 pci_write_reg(0xab000001, SH7751_PCICONF4);
30
31 mcr = ctrl_inl(SH7751_MCR);
32 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
33 pci_write_reg(mcr, SH4_PCIMCR);
34
35 pci_write_reg(0x0c000000, SH7751_PCICONF5);
36 pci_write_reg(0xd0000000, SH7751_PCICONF6);
37 pci_write_reg(0x0c000000, SH4_PCILAR0);
38 pci_write_reg(0x00000000, SH4_PCILAR1);
39
40 return 0;
41}
diff --git a/arch/sh/drivers/pci/fixups-r7780rp.c b/arch/sh/drivers/pci/fixups-r7780rp.c
index 3e321df65d22..15ca65cb667e 100644
--- a/arch/sh/drivers/pci/fixups-r7780rp.c
+++ b/arch/sh/drivers/pci/fixups-r7780rp.c
@@ -11,35 +11,26 @@
11 * for more details. 11 * for more details.
12 */ 12 */
13#include <linux/pci.h> 13#include <linux/pci.h>
14#include <linux/io.h>
14#include "pci-sh4.h" 15#include "pci-sh4.h"
15#include <asm/io.h>
16 16
17int pci_fixup_pcic(void) 17static char irq_tab[] __initdata = {
18{ 18 65, 66, 67, 68,
19 pci_write_reg(0x000043ff, SH4_PCIINTM); 19};
20 pci_write_reg(0x0000380f, SH4_PCIAINTM);
21
22 pci_write_reg(0xfbb00047, SH7780_PCICMD);
23 pci_write_reg(0x00000000, SH7780_PCIIBAR);
24
25 pci_write_reg(0x00011912, SH7780_PCISVID);
26 pci_write_reg(0x08000000, SH7780_PCICSCR0);
27 pci_write_reg(0x0000001b, SH7780_PCICSAR0);
28 pci_write_reg(0xfd000000, SH7780_PCICSCR1);
29 pci_write_reg(0x0000000f, SH7780_PCICSAR1);
30
31 pci_write_reg(0xfd000000, SH7780_PCIMBR0);
32 pci_write_reg(0x00fc0000, SH7780_PCIMBMR0);
33 20
34#ifdef CONFIG_32BIT 21int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
35 pci_write_reg(0xc0000000, SH7780_PCIMBR2); 22{
36 pci_write_reg(0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2); 23 return irq_tab[slot];
37#endif 24}
38 25
39 /* Set IOBR for windows containing area specified in pci.h */ 26int pci_fixup_pcic(struct pci_channel *chan)
40 pci_write_reg((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)), 27{
41 SH7780_PCIIOBR); 28 pci_write_reg(chan, 0x000043ff, SH4_PCIINTM);
42 pci_write_reg(((SH7780_PCI_IO_SIZE-1) & (7<<18)), SH7780_PCIIOBMR); 29 pci_write_reg(chan, 0x00000000, SH7780_PCIIBAR);
30 pci_write_reg(chan, 0x08000000, SH7780_PCICSCR0);
31 pci_write_reg(chan, 0x0000001b, SH7780_PCICSAR0);
32 pci_write_reg(chan, 0xfd000000, SH7780_PCICSCR1);
33 pci_write_reg(chan, 0x0000000f, SH7780_PCICSAR1);
43 34
44 return 0; 35 return 0;
45} 36}
diff --git a/arch/sh/drivers/pci/fixups-rts7751r2d.c b/arch/sh/drivers/pci/fixups-rts7751r2d.c
index 904bce8768d3..052b354236dc 100644
--- a/arch/sh/drivers/pci/fixups-rts7751r2d.c
+++ b/arch/sh/drivers/pci/fixups-rts7751r2d.c
@@ -1,43 +1,67 @@
1/* 1/*
2 * arch/sh/drivers/pci/fixups-rts7751r2d.c 2 * arch/sh/drivers/pci/fixups-rts7751r2d.c
3 * 3 *
4 * RTS7751R2D PCI fixups 4 * RTS7751R2D / LBOXRE2 PCI fixups
5 * 5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc. 6 * Copyright (C) 2003 Lineo uSolutions, Inc.
7 * Copyright (C) 2004 Paul Mundt 7 * Copyright (C) 2004 Paul Mundt
8 * Copyright (C) 2007 Nobuhiro Iwamatsu
8 * 9 *
9 * This file is subject to the terms and conditions of the GNU General Public 10 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive 11 * License. See the file "COPYING" in the main directory of this archive
11 * for more details. 12 * for more details.
12 */ 13 */
14#include <linux/pci.h>
15#include <mach/lboxre2.h>
16#include <mach/r2d.h>
13#include "pci-sh4.h" 17#include "pci-sh4.h"
18#include <asm/machtypes.h>
14 19
15#define PCIMCR_MRSET_OFF 0xBFFFFFFF 20#define PCIMCR_MRSET_OFF 0xBFFFFFFF
16#define PCIMCR_RFSH_OFF 0xFFFFFFFB 21#define PCIMCR_RFSH_OFF 0xFFFFFFFB
17 22
18int pci_fixup_pcic(void) 23static u8 rts7751r2d_irq_tab[] __initdata = {
24 IRQ_PCI_INTA,
25 IRQ_PCI_INTB,
26 IRQ_PCI_INTC,
27 IRQ_PCI_INTD,
28};
29
30static char lboxre2_irq_tab[] __initdata = {
31 IRQ_ETH0, IRQ_ETH1, IRQ_INTA, IRQ_INTD,
32};
33
34int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
35{
36 if (mach_is_lboxre2())
37 return lboxre2_irq_tab[slot];
38 else
39 return rts7751r2d_irq_tab[slot];
40}
41
42int pci_fixup_pcic(struct pci_channel *chan)
19{ 43{
20 unsigned long bcr1, mcr; 44 unsigned long bcr1, mcr;
21 45
22 bcr1 = ctrl_inl(SH7751_BCR1); 46 bcr1 = ctrl_inl(SH7751_BCR1);
23 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ 47 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
24 pci_write_reg(bcr1, SH4_PCIBCR1); 48 pci_write_reg(chan, bcr1, SH4_PCIBCR1);
25 49
26 /* Enable all interrupts, so we known what to fix */ 50 /* Enable all interrupts, so we known what to fix */
27 pci_write_reg(0x0000c3ff, SH4_PCIINTM); 51 pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM);
28 pci_write_reg(0x0000380f, SH4_PCIAINTM); 52 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
29 53
30 pci_write_reg(0xfb900047, SH7751_PCICONF1); 54 pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
31 pci_write_reg(0xab000001, SH7751_PCICONF4); 55 pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
32 56
33 mcr = ctrl_inl(SH7751_MCR); 57 mcr = ctrl_inl(SH7751_MCR);
34 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; 58 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
35 pci_write_reg(mcr, SH4_PCIMCR); 59 pci_write_reg(chan, mcr, SH4_PCIMCR);
36 60
37 pci_write_reg(0x0c000000, SH7751_PCICONF5); 61 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
38 pci_write_reg(0xd0000000, SH7751_PCICONF6); 62 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
39 pci_write_reg(0x0c000000, SH4_PCILAR0); 63 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
40 pci_write_reg(0x00000000, SH4_PCILAR1); 64 pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
41 65
42 return 0; 66 return 0;
43} 67}
diff --git a/arch/sh/drivers/pci/fixups-sdk7780.c b/arch/sh/drivers/pci/fixups-sdk7780.c
index 2f8863099dd1..250b0edd7365 100644
--- a/arch/sh/drivers/pci/fixups-sdk7780.c
+++ b/arch/sh/drivers/pci/fixups-sdk7780.c
@@ -5,55 +5,48 @@
5 * 5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc. 6 * Copyright (C) 2003 Lineo uSolutions, Inc.
7 * Copyright (C) 2004 - 2006 Paul Mundt 7 * Copyright (C) 2004 - 2006 Paul Mundt
8 * Copyright (C) 2006 Nobuhiro Iwamatsu
8 * 9 *
9 * This file is subject to the terms and conditions of the GNU General Public 10 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive 11 * License. See the file "COPYING" in the main directory of this archive
11 * for more details. 12 * for more details.
12 */ 13 */
13#include <linux/pci.h> 14#include <linux/pci.h>
15#include <linux/io.h>
14#include "pci-sh4.h" 16#include "pci-sh4.h"
15#include <asm/io.h>
16 17
17int pci_fixup_pcic(void) 18/* IDSEL [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] */
19static char sdk7780_irq_tab[4][16] __initdata = {
20 /* INTA */
21 { 65, 68, 67, 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
22 /* INTB */
23 { 66, 65, -1, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
24 /* INTC */
25 { 67, 66, -1, 66, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
26 /* INTD */
27 { 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
28};
29
30int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
31{
32 return sdk7780_irq_tab[pin-1][slot];
33}
34int pci_fixup_pcic(struct pci_channel *chan)
18{ 35{
19 ctrl_outl(0x00000001, SH7780_PCI_VCR2);
20
21 /* Enable all interrupts, so we know what to fix */ 36 /* Enable all interrupts, so we know what to fix */
22 pci_write_reg(0x0000C3FF, SH7780_PCIIMR); 37 pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);
23 pci_write_reg(0x0000380F, SH7780_PCIAINTM);
24 38
25 /* Set up standard PCI config registers */ 39 /* Set up standard PCI config registers */
26 pci_write_reg(0xFB00, SH7780_PCISTATUS); 40 pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0); /* PCI */
27 pci_write_reg(0x0047, SH7780_PCICMD); 41 pci_write_reg(chan, 0x08000000, SH4_PCILAR0); /* SHwy */
28 pci_write_reg(0x00, SH7780_PCIPIF); 42 pci_write_reg(chan, 0x07F00001, SH4_PCILSR0); /* size 128M w/ MBAR */
29 pci_write_reg(0x00, SH7780_PCISUB);
30 pci_write_reg(0x06, SH7780_PCIBCC);
31 pci_write_reg(0x1912, SH7780_PCISVID);
32 pci_write_reg(0x0001, SH7780_PCISID);
33
34 pci_write_reg(0x08000000, SH7780_PCIMBAR0); /* PCI */
35 pci_write_reg(0x08000000, SH7780_PCILAR0); /* SHwy */
36 pci_write_reg(0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */
37
38 pci_write_reg(0x00000000, SH7780_PCIMBAR1);
39 pci_write_reg(0x00000000, SH7780_PCILAR1);
40 pci_write_reg(0x00000000, SH7780_PCILSR1);
41
42 pci_write_reg(0xAB000801, SH7780_PCIIBAR);
43
44 /*
45 * Set the MBR so PCI address is one-to-one with window,
46 * meaning all calls go straight through... use ifdef to
47 * catch erroneous assumption.
48 */
49 pci_write_reg(0xFD000000 , SH7780_PCIMBR0);
50 pci_write_reg(0x00FC0000 , SH7780_PCIMBMR0); /* 16M */
51 43
52 /* Set IOBR for window containing area specified in pci.h */ 44 pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);
53 pci_write_reg(PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), SH7780_PCIIOBR); 45 pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
54 pci_write_reg((SH7780_PCI_IO_SIZE-1) & (7 << 18), SH7780_PCIIOBMR); 46 pci_write_reg(chan, 0x00000000, SH4_PCILSR1);
55 47
56 pci_write_reg(0xA5000C01, SH7780_PCICR); 48 pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);
49 pci_write_reg(chan, 0xA5000C01, SH4_PCICR);
57 50
58 return 0; 51 return 0;
59} 52}
diff --git a/arch/sh/drivers/pci/fixups-se7751.c b/arch/sh/drivers/pci/fixups-se7751.c
new file mode 100644
index 000000000000..475fa9f0fe2c
--- /dev/null
+++ b/arch/sh/drivers/pci/fixups-se7751.c
@@ -0,0 +1,111 @@
1#include <linux/kernel.h>
2#include <linux/types.h>
3#include <linux/init.h>
4#include <linux/delay.h>
5#include <linux/pci.h>
6#include <linux/io.h>
7#include "pci-sh4.h"
8
9int __init pcibios_map_platform_irq(u8 slot, u8 pin)
10{
11 switch (slot) {
12 case 0: return 13;
13 case 1: return 13; /* AMD Ethernet controller */
14 case 2: return -1;
15 case 3: return -1;
16 case 4: return -1;
17 default:
18 printk("PCI: Bad IRQ mapping request for slot %d\n", slot);
19 return -1;
20 }
21}
22
23#define PCIMCR_MRSET_OFF 0xBFFFFFFF
24#define PCIMCR_RFSH_OFF 0xFFFFFFFB
25
26/*
27 * Only long word accesses of the PCIC's internal local registers and the
28 * configuration registers from the CPU is supported.
29 */
30#define PCIC_WRITE(x,v) writel((v), PCI_REG(x))
31#define PCIC_READ(x) readl(PCI_REG(x))
32
33/*
34 * Description: This function sets up and initializes the pcic, sets
35 * up the BARS, maps the DRAM into the address space etc, etc.
36 */
37int pci_fixup_pcic(struct pci_channel *chan)
38{
39 unsigned long bcr1, wcr1, wcr2, wcr3, mcr;
40 unsigned short bcr2;
41
42 /*
43 * Initialize the slave bus controller on the pcic. The values used
44 * here should not be hardcoded, but they should be taken from the bsc
45 * on the processor, to make this function as generic as possible.
46 * (i.e. Another sbc may usr different SDRAM timing settings -- in order
47 * for the pcic to work, its settings need to be exactly the same.)
48 */
49 bcr1 = (*(volatile unsigned long*)(SH7751_BCR1));
50 bcr2 = (*(volatile unsigned short*)(SH7751_BCR2));
51 wcr1 = (*(volatile unsigned long*)(SH7751_WCR1));
52 wcr2 = (*(volatile unsigned long*)(SH7751_WCR2));
53 wcr3 = (*(volatile unsigned long*)(SH7751_WCR3));
54 mcr = (*(volatile unsigned long*)(SH7751_MCR));
55
56 bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */
57 (*(volatile unsigned long*)(SH7751_BCR1)) = bcr1;
58
59 bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
60 PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */
61 PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */
62 PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */
63 PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */
64 PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */
65 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
66 PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */
67
68
69 /* Enable all interrupts, so we know what to fix */
70 PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff);
71 PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f);
72
73 /* Set up standard PCI config registers */
74 PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */
75 PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */
76 PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */
77 PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */
78 PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */
79 PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */
80 PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */
81 PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */
82 PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */
83 PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */
84
85 /* Now turn it on... */
86 PCIC_WRITE(SH7751_PCICR, 0xa5000001);
87
88 /*
89 * Set PCIMBR and PCIIOBR here, assuming a single window
90 * (16M MEM, 256K IO) is enough. If a larger space is
91 * needed, the readx/writex and inx/outx functions will
92 * have to do more (e.g. setting registers for each call).
93 */
94
95 /*
96 * Set the MBR so PCI address is one-to-one with window,
97 * meaning all calls go straight through... use BUG_ON to
98 * catch erroneous assumption.
99 */
100 BUG_ON(chan->mem_resource->start != SH7751_PCI_MEMORY_BASE);
101
102 PCIC_WRITE(SH7751_PCIMBR, chan->mem_resource->start);
103
104 /* Set IOBR for window containing area specified in pci.h */
105 PCIC_WRITE(SH7751_PCIIOBR, (chan->io_resource->start & SH7751_PCIIOBR_MASK));
106
107 /* All done, may as well say so... */
108 printk("SH7751 PCI: Finished initialization of the PCI controller\n");
109
110 return 1;
111}
diff --git a/arch/sh/drivers/pci/fixups-se7780.c b/arch/sh/drivers/pci/fixups-se7780.c
deleted file mode 100644
index 880cea1c0d89..000000000000
--- a/arch/sh/drivers/pci/fixups-se7780.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * arch/sh/drivers/pci/fixups-se7780.c
3 *
4 * HITACHI UL Solution Engine 7780 PCI fixups
5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc.
7 * Copyright (C) 2004 - 2006 Paul Mundt
8 * Copyright (C) 2006 Nobuhiro Iwamatsu
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14#include <linux/pci.h>
15#include "pci-sh4.h"
16#include <asm/io.h>
17
18int pci_fixup_pcic(void)
19{
20 ctrl_outl(0x00000001, SH7780_PCI_VCR2);
21
22 /* Enable all interrupts, so we know what to fix */
23 pci_write_reg(0x0000C3FF, SH7780_PCIIMR);
24 pci_write_reg(0x0000380F, SH7780_PCIAINTM);
25
26 /* Set up standard PCI config registers */
27 ctrl_outw(0xFB00, PCI_REG(SH7780_PCISTATUS));
28 ctrl_outw(0x0047, PCI_REG(SH7780_PCICMD));
29 ctrl_outb( 0x00, PCI_REG(SH7780_PCIPIF));
30 ctrl_outb( 0x00, PCI_REG(SH7780_PCISUB));
31 ctrl_outb( 0x06, PCI_REG(SH7780_PCIBCC));
32 ctrl_outw(0x1912, PCI_REG(SH7780_PCISVID));
33 ctrl_outw(0x0001, PCI_REG(SH7780_PCISID));
34
35 pci_write_reg(0x08000000, SH7780_PCIMBAR0); /* PCI */
36 pci_write_reg(0x08000000, SH7780_PCILAR0); /* SHwy */
37 pci_write_reg(0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */
38
39 pci_write_reg(0x00000000, SH7780_PCIMBAR1);
40 pci_write_reg(0x00000000, SH7780_PCILAR1);
41 pci_write_reg(0x00000000, SH7780_PCILSR1);
42
43 pci_write_reg(0xAB000801, SH7780_PCIIBAR);
44
45 /*
46 * Set the MBR so PCI address is one-to-one with window,
47 * meaning all calls go straight through... use ifdef to
48 * catch erroneous assumption.
49 */
50 pci_write_reg(0xFD000000 , SH7780_PCIMBR0);
51 pci_write_reg(0x00FC0000 , SH7780_PCIMBMR0); /* 16M */
52
53 /* Set IOBR for window containing area specified in pci.h */
54 pci_write_reg(PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), SH7780_PCIIOBR);
55 pci_write_reg((SH7780_PCI_IO_SIZE-1) & (7 << 18), SH7780_PCIIOBMR);
56
57 pci_write_reg(0xA5000C01, SH7780_PCICR);
58
59 return 0;
60}
diff --git a/arch/sh/drivers/pci/fixups-sh7785lcr.c b/arch/sh/drivers/pci/fixups-sh7785lcr.c
deleted file mode 100644
index 4949e601387a..000000000000
--- a/arch/sh/drivers/pci/fixups-sh7785lcr.c
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * arch/sh/drivers/pci/fixups-sh7785lcr.c
3 *
4 * R0P7785LC0011RL PCI fixups
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * Based on arch/sh/drivers/pci/fixups-r7780rp.c
8 * Copyright (C) 2003 Lineo uSolutions, Inc.
9 * Copyright (C) 2004 - 2006 Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/pci.h>
16#include "pci-sh4.h"
17
18int pci_fixup_pcic(void)
19{
20 pci_write_reg(0x000043ff, SH4_PCIINTM);
21 pci_write_reg(0x0000380f, SH4_PCIAINTM);
22
23 pci_write_reg(0xfbb00047, SH7780_PCICMD);
24 pci_write_reg(0x00000000, SH7780_PCIIBAR);
25
26 pci_write_reg(0x00011912, SH7780_PCISVID);
27 pci_write_reg(0x08000000, SH7780_PCICSCR0);
28 pci_write_reg(0x0000001b, SH7780_PCICSAR0);
29 pci_write_reg(0xfd000000, SH7780_PCICSCR1);
30 pci_write_reg(0x0000000f, SH7780_PCICSAR1);
31
32 pci_write_reg(0xfd000000, SH7780_PCIMBR0);
33 pci_write_reg(0x00fc0000, SH7780_PCIMBMR0);
34
35#ifdef CONFIG_32BIT
36 pci_write_reg(0xc0000000, SH7780_PCIMBR2);
37 pci_write_reg(0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
38#endif
39
40 /* Set IOBR for windows containing area specified in pci.h */
41 pci_write_reg((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)),
42 SH7780_PCIIOBR);
43 pci_write_reg(((SH7780_PCI_IO_SIZE - 1) & (7 << 18)), SH7780_PCIIOBMR);
44
45 return 0;
46}
diff --git a/arch/sh/drivers/pci/fixups-snapgear.c b/arch/sh/drivers/pci/fixups-snapgear.c
new file mode 100644
index 000000000000..5a39ecc1adb8
--- /dev/null
+++ b/arch/sh/drivers/pci/fixups-snapgear.c
@@ -0,0 +1,38 @@
1/*
2 * arch/sh/drivers/pci/ops-snapgear.c
3 *
4 * Author: David McCullough <davidm@snapgear.com>
5 *
6 * Ported to new API by Paul Mundt <lethal@linux-sh.org>
7 *
8 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
9 *
10 * May be copied or modified under the terms of the GNU General Public
11 * License. See linux/COPYING for more information.
12 *
13 * PCI initialization for the SnapGear boards
14 */
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/init.h>
18#include <linux/pci.h>
19#include "pci-sh4.h"
20
21int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
22{
23 int irq = -1;
24
25 switch (slot) {
26 case 8: /* the PCI bridge */ break;
27 case 11: irq = 8; break; /* USB */
28 case 12: irq = 11; break; /* PCMCIA */
29 case 13: irq = 5; break; /* eth0 */
30 case 14: irq = 8; break; /* eth1 */
31 case 15: irq = 11; break; /* safenet (unused) */
32 }
33
34 printk("PCI: Mapping SnapGear IRQ for slot %d, pin %c to irq %d\n",
35 slot, pin - 1 + 'A', irq);
36
37 return irq;
38}
diff --git a/arch/sh/drivers/pci/ops-titan.c b/arch/sh/drivers/pci/fixups-titan.c
index a8f7801a34af..3a79fa8254a6 100644
--- a/arch/sh/drivers/pci/ops-titan.c
+++ b/arch/sh/drivers/pci/fixups-titan.c
@@ -36,42 +36,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
36 36
37 return irq; 37 return irq;
38} 38}
39
40static struct resource sh7751_io_resource = {
41 .name = "SH7751_IO",
42 .start = SH7751_PCI_IO_BASE,
43 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
44 .flags = IORESOURCE_IO
45};
46
47static struct resource sh7751_mem_resource = {
48 .name = "SH7751_mem",
49 .start = SH7751_PCI_MEMORY_BASE,
50 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
51 .flags = IORESOURCE_MEM
52};
53
54struct pci_channel board_pci_channels[] = {
55 { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
56 { NULL, NULL, NULL, 0, 0 },
57};
58EXPORT_SYMBOL(board_pci_channels);
59
60static struct sh4_pci_address_map sh7751_pci_map = {
61 .window0 = {
62 .base = SH7751_CS2_BASE_ADDR,
63 .size = SH7751_MEM_REGION_SIZE*2, /* cs2 and cs3 */
64 },
65
66 .window1 = {
67 .base = SH7751_CS2_BASE_ADDR,
68 .size = SH7751_MEM_REGION_SIZE*2,
69 },
70
71 .flags = SH4_PCIC_NO_RESET,
72};
73
74int __init pcibios_init_platform(void)
75{
76 return sh7751_pcic_init(&sh7751_pci_map);
77}
diff --git a/arch/sh/drivers/pci/ops-dreamcast.c b/arch/sh/drivers/pci/ops-dreamcast.c
index f5d2a2aa6f3f..e83d0d3aabe2 100644
--- a/arch/sh/drivers/pci/ops-dreamcast.c
+++ b/arch/sh/drivers/pci/ops-dreamcast.c
@@ -1,15 +1,9 @@
1/* 1/*
2 * arch/sh/drivers/pci/ops-dreamcast.c
3 *
4 * PCI operations for the Sega Dreamcast 2 * PCI operations for the Sega Dreamcast
5 * 3 *
6 * Copyright (C) 2001, 2002 M. R. Brown 4 * Copyright (C) 2001, 2002 M. R. Brown
7 * Copyright (C) 2002, 2003 Paul Mundt 5 * Copyright (C) 2002, 2003 Paul Mundt
8 * 6 *
9 * This file originally bore the message (with enclosed-$):
10 * Id: pci.c,v 1.3 2003/05/04 19:29:46 lethal Exp
11 * Dreamcast PCI: Supports SEGA Broadband Adaptor only.
12 *
13 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
15 * for more details. 9 * for more details.
@@ -23,34 +17,10 @@
23#include <linux/irq.h> 17#include <linux/irq.h>
24#include <linux/pci.h> 18#include <linux/pci.h>
25#include <linux/module.h> 19#include <linux/module.h>
26 20#include <linux/io.h>
27#include <asm/io.h> 21#include <linux/irq.h>
28#include <asm/irq.h>
29#include <mach/pci.h> 22#include <mach/pci.h>
30 23
31static struct resource gapspci_io_resource = {
32 .name = "GAPSPCI IO",
33 .start = GAPSPCI_BBA_CONFIG,
34 .end = GAPSPCI_BBA_CONFIG + GAPSPCI_BBA_CONFIG_SIZE - 1,
35 .flags = IORESOURCE_IO,
36};
37
38static struct resource gapspci_mem_resource = {
39 .name = "GAPSPCI mem",
40 .start = GAPSPCI_DMA_BASE,
41 .end = GAPSPCI_DMA_BASE + GAPSPCI_DMA_SIZE - 1,
42 .flags = IORESOURCE_MEM,
43};
44
45static struct pci_ops gapspci_pci_ops;
46
47struct pci_channel board_pci_channels[] = {
48 { &gapspci_pci_ops, &gapspci_io_resource,
49 &gapspci_mem_resource, 0, 1 },
50 { 0, }
51};
52EXPORT_SYMBOL(board_pci_channels);
53
54/* 24/*
55 * The !gapspci_config_access case really shouldn't happen, ever, unless 25 * The !gapspci_config_access case really shouldn't happen, ever, unless
56 * someone implicitly messes around with the last devfn value.. otherwise we 26 * someone implicitly messes around with the last devfn value.. otherwise we
@@ -85,10 +55,10 @@ static int gapspci_read(struct pci_bus *bus, unsigned int devfn, int where, int
85 return PCIBIOS_DEVICE_NOT_FOUND; 55 return PCIBIOS_DEVICE_NOT_FOUND;
86 56
87 switch (size) { 57 switch (size) {
88 case 1: *val = inb(GAPSPCI_BBA_CONFIG+where); break; 58 case 1: *val = inb(GAPSPCI_BBA_CONFIG+where); break;
89 case 2: *val = inw(GAPSPCI_BBA_CONFIG+where); break; 59 case 2: *val = inw(GAPSPCI_BBA_CONFIG+where); break;
90 case 4: *val = inl(GAPSPCI_BBA_CONFIG+where); break; 60 case 4: *val = inl(GAPSPCI_BBA_CONFIG+where); break;
91 } 61 }
92 62
93 return PCIBIOS_SUCCESSFUL; 63 return PCIBIOS_SUCCESSFUL;
94} 64}
@@ -99,72 +69,15 @@ static int gapspci_write(struct pci_bus *bus, unsigned int devfn, int where, int
99 return PCIBIOS_DEVICE_NOT_FOUND; 69 return PCIBIOS_DEVICE_NOT_FOUND;
100 70
101 switch (size) { 71 switch (size) {
102 case 1: outb(( u8)val, GAPSPCI_BBA_CONFIG+where); break; 72 case 1: outb(( u8)val, GAPSPCI_BBA_CONFIG+where); break;
103 case 2: outw((u16)val, GAPSPCI_BBA_CONFIG+where); break; 73 case 2: outw((u16)val, GAPSPCI_BBA_CONFIG+where); break;
104 case 4: outl((u32)val, GAPSPCI_BBA_CONFIG+where); break; 74 case 4: outl((u32)val, GAPSPCI_BBA_CONFIG+where); break;
105 } 75 }
106 76
107 return PCIBIOS_SUCCESSFUL; 77 return PCIBIOS_SUCCESSFUL;
108} 78}
109 79
110static struct pci_ops gapspci_pci_ops = { 80struct pci_ops gapspci_pci_ops = {
111 .read = gapspci_read, 81 .read = gapspci_read,
112 .write = gapspci_write, 82 .write = gapspci_write,
113}; 83};
114
115/*
116 * gapspci init
117 */
118
119int __init gapspci_init(void)
120{
121 char idbuf[16];
122 int i;
123
124 /*
125 * FIXME: All of this wants documenting to some degree,
126 * even some basic register definitions would be nice.
127 *
128 * I haven't seen anything this ugly since.. maple.
129 */
130
131 for (i=0; i<16; i++)
132 idbuf[i] = inb(GAPSPCI_REGS+i);
133
134 if (strncmp(idbuf, "GAPSPCI_BRIDGE_2", 16))
135 return -ENODEV;
136
137 outl(0x5a14a501, GAPSPCI_REGS+0x18);
138
139 for (i=0; i<1000000; i++)
140 ;
141
142 if (inl(GAPSPCI_REGS+0x18) != 1)
143 return -EINVAL;
144
145 outl(0x01000000, GAPSPCI_REGS+0x20);
146 outl(0x01000000, GAPSPCI_REGS+0x24);
147
148 outl(GAPSPCI_DMA_BASE, GAPSPCI_REGS+0x28);
149 outl(GAPSPCI_DMA_BASE+GAPSPCI_DMA_SIZE, GAPSPCI_REGS+0x2c);
150
151 outl(1, GAPSPCI_REGS+0x14);
152 outl(1, GAPSPCI_REGS+0x34);
153
154 /* Setting Broadband Adapter */
155 outw(0xf900, GAPSPCI_BBA_CONFIG+0x06);
156 outl(0x00000000, GAPSPCI_BBA_CONFIG+0x30);
157 outb(0x00, GAPSPCI_BBA_CONFIG+0x3c);
158 outb(0xf0, GAPSPCI_BBA_CONFIG+0x0d);
159 outw(0x0006, GAPSPCI_BBA_CONFIG+0x04);
160 outl(0x00002001, GAPSPCI_BBA_CONFIG+0x10);
161 outl(0x01000000, GAPSPCI_BBA_CONFIG+0x14);
162
163 return 0;
164}
165
166/* Haven't done anything here as yet */
167char * __devinit pcibios_setup(char *str)
168{
169 return str;
170}
diff --git a/arch/sh/drivers/pci/ops-lboxre2.c b/arch/sh/drivers/pci/ops-lboxre2.c
deleted file mode 100644
index 86c0b6fb7375..000000000000
--- a/arch/sh/drivers/pci/ops-lboxre2.c
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * linux/arch/sh/drivers/pci/ops-lboxre2.c
3 *
4 * Copyright (C) 2007 Nobuhiro Iwamatsu
5 *
6 * PCI initialization for the NTT COMWARE L-BOX RE2
7 */
8#include <linux/kernel.h>
9#include <linux/types.h>
10#include <linux/init.h>
11#include <linux/pci.h>
12#include <linux/io.h>
13#include <mach/lboxre2.h>
14#include "pci-sh4.h"
15
16static char lboxre2_irq_tab[] __initdata = {
17 IRQ_ETH0, IRQ_ETH1, IRQ_INTA, IRQ_INTD,
18};
19
20int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
21{
22 return lboxre2_irq_tab[slot];
23}
24
25static struct resource sh7751_io_resource = {
26 .name = "SH7751_IO",
27 .start = SH7751_PCI_IO_BASE ,
28 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
29 .flags = IORESOURCE_IO
30};
31
32static struct resource sh7751_mem_resource = {
33 .name = "SH7751_mem",
34 .start = SH7751_PCI_MEMORY_BASE,
35 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
36 .flags = IORESOURCE_MEM
37};
38
39extern struct pci_ops sh7751_pci_ops;
40
41struct pci_channel board_pci_channels[] = {
42 { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
43 { NULL, NULL, NULL, 0, 0 },
44};
45
46EXPORT_SYMBOL(board_pci_channels);
47
48static struct sh4_pci_address_map sh7751_pci_map = {
49 .window0 = {
50 .base = SH7751_CS3_BASE_ADDR,
51 .size = 0x04000000,
52 },
53 .window1 = {
54 .base = 0x00000000, /* Unused */
55 .size = 0x00000000, /* Unused */
56 },
57 .flags = SH4_PCIC_NO_RESET,
58};
59
60int __init pcibios_init_platform(void)
61{
62 return sh7751_pcic_init(&sh7751_pci_map);
63}
diff --git a/arch/sh/drivers/pci/ops-r7780rp.c b/arch/sh/drivers/pci/ops-r7780rp.c
deleted file mode 100644
index 8555238e63eb..000000000000
--- a/arch/sh/drivers/pci/ops-r7780rp.c
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * Author: Ian DaSilva (idasilva@mvista.com)
3 *
4 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * PCI initialization for the Renesas SH7780 Highlander R7780RP-1 board
10 */
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/pci.h>
16#include <mach/highlander.h>
17#include <asm/io.h>
18#include "pci-sh4.h"
19
20static char irq_tab[] __initdata = {
21 65, 66, 67, 68,
22};
23
24int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
25{
26 return irq_tab[slot];
27}
28
29static struct resource sh7780_io_resource = {
30 .name = "SH7780_IO",
31 .start = SH7780_PCI_IO_BASE,
32 .end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
33 .flags = IORESOURCE_IO
34};
35
36static struct resource sh7780_mem_resource = {
37 .name = "SH7780_mem",
38 .start = SH7780_PCI_MEMORY_BASE,
39 .end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
40 .flags = IORESOURCE_MEM
41};
42
43extern struct pci_ops sh7780_pci_ops;
44
45struct pci_channel board_pci_channels[] = {
46 { &sh4_pci_ops, &sh7780_io_resource, &sh7780_mem_resource, 0, 0xff },
47 { NULL, NULL, NULL, 0, 0 },
48};
49EXPORT_SYMBOL(board_pci_channels);
50
51static struct sh4_pci_address_map sh7780_pci_map = {
52 .window0 = {
53 .base = SH7780_CS2_BASE_ADDR,
54 .size = 0x04000000,
55 },
56
57 .window1 = {
58 .base = SH7780_CS3_BASE_ADDR,
59 .size = 0x04000000,
60 },
61
62 .flags = SH4_PCIC_NO_RESET,
63};
64
65int __init pcibios_init_platform(void)
66{
67 return sh7780_pcic_init(&sh7780_pci_map);
68}
diff --git a/arch/sh/drivers/pci/ops-rts7751r2d.c b/arch/sh/drivers/pci/ops-rts7751r2d.c
deleted file mode 100644
index d6ca74b25d5f..000000000000
--- a/arch/sh/drivers/pci/ops-rts7751r2d.c
+++ /dev/null
@@ -1,74 +0,0 @@
1/*
2 * linux/arch/sh/drivers/pci/ops-rts7751r2d.c
3 *
4 * Author: Ian DaSilva (idasilva@mvista.com)
5 *
6 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 *
11 * PCI initialization for the Renesas SH7751R RTS7751R2D board
12 */
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <linux/io.h>
18#include <mach/r2d.h>
19#include "pci-sh4.h"
20
21static u8 rts7751r2d_irq_tab[] __initdata = {
22 IRQ_PCI_INTA,
23 IRQ_PCI_INTB,
24 IRQ_PCI_INTC,
25 IRQ_PCI_INTD,
26};
27
28int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
29{
30 return rts7751r2d_irq_tab[slot];
31}
32
33static struct resource sh7751_io_resource = {
34 .name = "SH7751_IO",
35 .start = 0x4000,
36 .end = SH7751_PCI_IO_SIZE - 1,
37 .flags = IORESOURCE_IO
38};
39
40static struct resource sh7751_mem_resource = {
41 .name = "SH7751_mem",
42 .start = SH7751_PCI_MEMORY_BASE,
43 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
44 .flags = IORESOURCE_MEM
45};
46
47extern struct pci_ops sh7751_pci_ops;
48
49struct pci_channel board_pci_channels[] = {
50 { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
51 { NULL, NULL, NULL, 0, 0 },
52};
53EXPORT_SYMBOL(board_pci_channels);
54
55static struct sh4_pci_address_map sh7751_pci_map = {
56 .window0 = {
57 .base = SH7751_CS3_BASE_ADDR,
58 .size = 0x04000000,
59 },
60
61 .window1 = {
62 .base = 0x00000000, /* Unused */
63 .size = 0x00000000, /* Unused */
64 },
65
66 .flags = SH4_PCIC_NO_RESET,
67};
68
69int __init pcibios_init_platform(void)
70{
71 __set_io_port_base(SH7751_PCI_IO_BASE);
72 return sh7751_pcic_init(&sh7751_pci_map);
73}
74
diff --git a/arch/sh/drivers/pci/ops-sdk7780.c b/arch/sh/drivers/pci/ops-sdk7780.c
deleted file mode 100644
index 4dcc64184b23..000000000000
--- a/arch/sh/drivers/pci/ops-sdk7780.c
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * linux/arch/sh/drivers/pci/ops-sdk7780.c
3 *
4 * Copyright (C) 2006 Nobuhiro Iwamatsu
5 *
6 * PCI initialization for the SDK7780SE03
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 */
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/pci.h>
16#include <mach/sdk7780.h>
17#include <asm/io.h>
18#include "pci-sh4.h"
19
20/* IDSEL [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] */
21static char sdk7780_irq_tab[4][16] __initdata = {
22 /* INTA */
23 { 65, 68, 67, 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
24 /* INTB */
25 { 66, 65, -1, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
26 /* INTC */
27 { 67, 66, -1, 66, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
28 /* INTD */
29 { 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
30};
31
32int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
33{
34 return sdk7780_irq_tab[pin-1][slot];
35}
36
37static struct resource sdk7780_io_resource = {
38 .name = "SH7780_IO",
39 .start = SH7780_PCI_IO_BASE,
40 .end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
41 .flags = IORESOURCE_IO
42};
43
44static struct resource sdk7780_mem_resource = {
45 .name = "SH7780_mem",
46 .start = SH7780_PCI_MEMORY_BASE,
47 .end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
48 .flags = IORESOURCE_MEM
49};
50
51struct pci_channel board_pci_channels[] = {
52 { &sh4_pci_ops, &sdk7780_io_resource, &sdk7780_mem_resource, 0, 0xff },
53 { NULL, NULL, NULL, 0, 0 },
54};
55EXPORT_SYMBOL(board_pci_channels);
56
57static struct sh4_pci_address_map sdk7780_pci_map = {
58 .window0 = {
59 .base = SH7780_CS2_BASE_ADDR,
60 .size = 0x04000000,
61 },
62 .window1 = {
63 .base = SH7780_CS3_BASE_ADDR,
64 .size = 0x04000000,
65 },
66 .flags = SH4_PCIC_NO_RESET,
67};
68
69int __init pcibios_init_platform(void)
70{
71 printk(KERN_INFO "SH7780 PCI: Finished initializing PCI controller\n");
72 return sh7780_pcic_init(&sdk7780_pci_map);
73}
diff --git a/arch/sh/drivers/pci/ops-se7780.c b/arch/sh/drivers/pci/ops-se7780.c
deleted file mode 100644
index 3145c62484d6..000000000000
--- a/arch/sh/drivers/pci/ops-se7780.c
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * linux/arch/sh/drivers/pci/ops-se7780.c
3 *
4 * Copyright (C) 2006 Nobuhiro Iwamatsu
5 *
6 * PCI initialization for the Hitachi UL Solution Engine 7780SE03
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 */
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/pci.h>
16#include <mach-se/mach/se7780.h>
17#include <asm/io.h>
18#include "pci-sh4.h"
19
20/*
21 * IDSEL = AD16 PCI slot
22 * IDSEL = AD17 PCI slot
23 * IDSEL = AD18 Serial ATA Controller (Silicon Image SiL3512A)
24 * IDSEL = AD19 USB Host Controller (NEC uPD7210100A)
25 */
26
27/* IDSEL [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] */
28static char se7780_irq_tab[4][16] __initdata = {
29 /* INTA */
30 { 65, 68, 67, 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
31 /* INTB */
32 { 66, 65, -1, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
33 /* INTC */
34 { 67, 66, -1, 66, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
35 /* INTD */
36 { 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
37};
38
39int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
40{
41 return se7780_irq_tab[pin-1][slot];
42}
43
44static struct resource se7780_io_resource = {
45 .name = "SH7780_IO",
46 .start = SH7780_PCI_IO_BASE,
47 .end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
48 .flags = IORESOURCE_IO
49};
50
51static struct resource se7780_mem_resource = {
52 .name = "SH7780_mem",
53 .start = SH7780_PCI_MEMORY_BASE,
54 .end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
55 .flags = IORESOURCE_MEM
56};
57
58extern struct pci_ops se7780_pci_ops;
59
60struct pci_channel board_pci_channels[] = {
61 { &sh4_pci_ops, &se7780_io_resource, &se7780_mem_resource, 0, 0xff },
62 { NULL, NULL, NULL, 0, 0 },
63};
64EXPORT_SYMBOL(board_pci_channels);
65
66static struct sh4_pci_address_map se7780_pci_map = {
67 .window0 = {
68 .base = SH7780_CS2_BASE_ADDR,
69 .size = 0x04000000,
70 },
71 .flags = SH4_PCIC_NO_RESET,
72};
73
74int __init pcibios_init_platform(void)
75{
76 printk("SH7780 PCI: Finished initialization of the PCI controller\n");
77
78 /*
79 * FPGA PCISEL register initialize
80 *
81 * CPU || SLOT1 | SLOT2 | S-ATA | USB
82 * -------------------------------------
83 * INTA || INTA | INTD | -- | INTB
84 * -------------------------------------
85 * INTB || INTB | INTA | -- | INTC
86 * -------------------------------------
87 * INTC || INTC | INTB | INTA | --
88 * -------------------------------------
89 * INTD || INTD | INTC | -- | INTA
90 * -------------------------------------
91 */
92 ctrl_outw(0x0013, FPGA_PCI_INTSEL1);
93 ctrl_outw(0xE402, FPGA_PCI_INTSEL2);
94
95 return sh7780_pcic_init(&se7780_pci_map);
96}
diff --git a/arch/sh/drivers/pci/ops-sh03.c b/arch/sh/drivers/pci/ops-sh03.c
deleted file mode 100644
index e1703ff5a4d2..000000000000
--- a/arch/sh/drivers/pci/ops-sh03.c
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * linux/arch/sh/drivers/pci/ops-sh03.c
3 *
4 * PCI initialization for the Interface CTP/PCI-SH03 board
5 */
6
7#include <linux/kernel.h>
8#include <linux/types.h>
9#include <linux/init.h>
10#include <linux/delay.h>
11#include <linux/pci.h>
12#include <asm/io.h>
13#include "pci-sh7751.h"
14
15/*
16 * Description: This function sets up and initializes the pcic, sets
17 * up the BARS, maps the DRAM into the address space etc, etc.
18 */
19int __init pcibios_init_platform(void)
20{
21 __set_io_port_base(SH7751_PCI_IO_BASE);
22 return 1;
23}
24
25static struct resource sh7751_io_resource = {
26 .name = "SH03 IO",
27 .start = SH7751_PCI_IO_BASE,
28 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
29 .flags = IORESOURCE_IO
30};
31
32static struct resource sh7751_mem_resource = {
33 .name = "SH03 mem",
34 .start = SH7751_PCI_MEMORY_BASE,
35 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
36 .flags = IORESOURCE_MEM
37};
38
39extern struct pci_ops sh4_pci_ops;
40
41struct pci_channel board_pci_channels[] = {
42 { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
43 { NULL, NULL, NULL, 0, 0 },
44};
45
diff --git a/arch/sh/drivers/pci/ops-sh4.c b/arch/sh/drivers/pci/ops-sh4.c
index 710a3b0306e5..78bebebdc99c 100644
--- a/arch/sh/drivers/pci/ops-sh4.c
+++ b/arch/sh/drivers/pci/ops-sh4.c
@@ -1,22 +1,22 @@
1/* 1/*
2 * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780). 2 * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780).
3 * 3 *
4 * Copyright (C) 2002 - 2006 Paul Mundt 4 * Copyright (C) 2002 - 2009 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License v2. See the file "COPYING" in the main directory of this archive 7 * License v2. See the file "COPYING" in the main directory of this archive
8 * for more details. 8 * for more details.
9 */ 9 */
10#include <linux/pci.h> 10#include <linux/pci.h>
11#include <linux/io.h>
11#include <asm/addrspace.h> 12#include <asm/addrspace.h>
12#include <asm/io.h>
13#include "pci-sh4.h" 13#include "pci-sh4.h"
14 14
15/* 15/*
16 * Direct access to PCI hardware... 16 * Direct access to PCI hardware...
17 */ 17 */
18#define CONFIG_CMD(bus, devfn, where) \ 18#define CONFIG_CMD(bus, devfn, where) \
19 P1SEGADDR((bus->number << 16) | (devfn << 8) | (where & ~3)) 19 (P1SEG | (bus->number << 16) | (devfn << 8) | (where & ~3))
20 20
21static DEFINE_SPINLOCK(sh4_pci_lock); 21static DEFINE_SPINLOCK(sh4_pci_lock);
22 22
@@ -26,6 +26,7 @@ static DEFINE_SPINLOCK(sh4_pci_lock);
26static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn, 26static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
27 int where, int size, u32 *val) 27 int where, int size, u32 *val)
28{ 28{
29 struct pci_channel *chan = bus->sysdata;
29 unsigned long flags; 30 unsigned long flags;
30 u32 data; 31 u32 data;
31 32
@@ -34,8 +35,8 @@ static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
34 * so we must do byte alignment by hand 35 * so we must do byte alignment by hand
35 */ 36 */
36 spin_lock_irqsave(&sh4_pci_lock, flags); 37 spin_lock_irqsave(&sh4_pci_lock, flags);
37 pci_write_reg(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR); 38 pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
38 data = pci_read_reg(SH4_PCIPDR); 39 data = pci_read_reg(chan, SH4_PCIPDR);
39 spin_unlock_irqrestore(&sh4_pci_lock, flags); 40 spin_unlock_irqrestore(&sh4_pci_lock, flags);
40 41
41 switch (size) { 42 switch (size) {
@@ -63,13 +64,14 @@ static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
63static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn, 64static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
64 int where, int size, u32 val) 65 int where, int size, u32 val)
65{ 66{
67 struct pci_channel *chan = bus->sysdata;
66 unsigned long flags; 68 unsigned long flags;
67 int shift; 69 int shift;
68 u32 data; 70 u32 data;
69 71
70 spin_lock_irqsave(&sh4_pci_lock, flags); 72 spin_lock_irqsave(&sh4_pci_lock, flags);
71 pci_write_reg(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR); 73 pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
72 data = pci_read_reg(SH4_PCIPDR); 74 data = pci_read_reg(chan, SH4_PCIPDR);
73 spin_unlock_irqrestore(&sh4_pci_lock, flags); 75 spin_unlock_irqrestore(&sh4_pci_lock, flags);
74 76
75 switch (size) { 77 switch (size) {
@@ -90,7 +92,7 @@ static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
90 return PCIBIOS_FUNC_NOT_SUPPORTED; 92 return PCIBIOS_FUNC_NOT_SUPPORTED;
91 } 93 }
92 94
93 pci_write_reg(data, SH4_PCIPDR); 95 pci_write_reg(chan, data, SH4_PCIPDR);
94 96
95 return PCIBIOS_SUCCESSFUL; 97 return PCIBIOS_SUCCESSFUL;
96} 98}
@@ -104,66 +106,31 @@ struct pci_ops sh4_pci_ops = {
104 * Not really related to pci_ops, but it's common and not worth shoving 106 * Not really related to pci_ops, but it's common and not worth shoving
105 * somewhere else for now.. 107 * somewhere else for now..
106 */ 108 */
107static unsigned int pci_probe = PCI_PROBE_CONF1; 109int __init sh4_pci_check_direct(struct pci_channel *chan)
108
109int __init sh4_pci_check_direct(void)
110{ 110{
111 /* 111 /*
112 * Check if configuration works. 112 * Check if configuration works.
113 */ 113 */
114 if (pci_probe & PCI_PROBE_CONF1) { 114 unsigned int tmp = pci_read_reg(chan, SH4_PCIPAR);
115 unsigned int tmp = pci_read_reg(SH4_PCIPAR);
116
117 pci_write_reg(P1SEG, SH4_PCIPAR);
118 115
119 if (pci_read_reg(SH4_PCIPAR) == P1SEG) { 116 pci_write_reg(chan, P1SEG, SH4_PCIPAR);
120 pci_write_reg(tmp, SH4_PCIPAR);
121 printk(KERN_INFO "PCI: Using configuration type 1\n");
122 request_region(PCI_REG(SH4_PCIPAR), 8, "PCI conf1");
123 117
124 return 0; 118 if (pci_read_reg(chan, SH4_PCIPAR) == P1SEG) {
125 } 119 pci_write_reg(chan, tmp, SH4_PCIPAR);
126 120 printk(KERN_INFO "PCI: Using configuration type 1\n");
127 pci_write_reg(tmp, SH4_PCIPAR); 121 request_region(chan->reg_base + SH4_PCIPAR, 8,
122 "PCI conf1");
123 return 0;
128 } 124 }
129 125
130 pr_debug("PCI: pci_check_direct failed\n"); 126 pci_write_reg(chan, tmp, SH4_PCIPAR);
131 return -EINVAL;
132}
133 127
134/* Handle generic fixups */ 128 printk(KERN_ERR "PCI: %s failed\n", __func__);
135static void __init pci_fixup_ide_bases(struct pci_dev *d)
136{
137 int i;
138 129
139 /* 130 return -EINVAL;
140 * PCI IDE controllers use non-standard I/O port decoding, respect it.
141 */
142 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
143 return;
144 pr_debug("PCI: IDE base address fixup for %s\n", pci_name(d));
145 for(i = 0; i < 4; i++) {
146 struct resource *r = &d->resource[i];
147
148 if ((r->start & ~0x80) == 0x374) {
149 r->start |= 2;
150 r->end = r->start;
151 }
152 }
153}
154DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
155
156char * __devinit pcibios_setup(char *str)
157{
158 if (!strcmp(str, "off")) {
159 pci_probe = 0;
160 return NULL;
161 }
162
163 return str;
164} 131}
165 132
166int __attribute__((weak)) pci_fixup_pcic(void) 133int __attribute__((weak)) pci_fixup_pcic(struct pci_channel *chan)
167{ 134{
168 /* Nothing to do. */ 135 /* Nothing to do. */
169 return 0; 136 return 0;
diff --git a/arch/sh/drivers/pci/ops-sh5.c b/arch/sh/drivers/pci/ops-sh5.c
index 729e38a6fe07..4ce95a001b80 100644
--- a/arch/sh/drivers/pci/ops-sh5.c
+++ b/arch/sh/drivers/pci/ops-sh5.c
@@ -22,31 +22,6 @@
22#include <asm/io.h> 22#include <asm/io.h>
23#include "pci-sh5.h" 23#include "pci-sh5.h"
24 24
25static void __init pci_fixup_ide_bases(struct pci_dev *d)
26{
27 int i;
28
29 /*
30 * PCI IDE controllers use non-standard I/O port decoding, respect it.
31 */
32 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
33 return;
34 printk("PCI: IDE base address fixup for %s\n", pci_name(d));
35 for(i=0; i<4; i++) {
36 struct resource *r = &d->resource[i];
37 if ((r->start & ~0x80) == 0x374) {
38 r->start |= 2;
39 r->end = r->start;
40 }
41 }
42}
43DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
44
45char * __devinit pcibios_setup(char *str)
46{
47 return str;
48}
49
50static int sh5pci_read(struct pci_bus *bus, unsigned int devfn, int where, 25static int sh5pci_read(struct pci_bus *bus, unsigned int devfn, int where,
51 int size, u32 *val) 26 int size, u32 *val)
52{ 27{
diff --git a/arch/sh/drivers/pci/ops-sh7785lcr.c b/arch/sh/drivers/pci/ops-sh7785lcr.c
deleted file mode 100644
index fb0869f0bef8..000000000000
--- a/arch/sh/drivers/pci/ops-sh7785lcr.c
+++ /dev/null
@@ -1,66 +0,0 @@
1/*
2 * Author: Ian DaSilva (idasilva@mvista.com)
3 *
4 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * PCI initialization for the Renesas R0P7785LC0011RL board
10 * Based on arch/sh/drivers/pci/ops-r7780rp.c
11 *
12 */
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pci.h>
18#include "pci-sh4.h"
19
20static char irq_tab[] __initdata = {
21 65, 66, 67, 68,
22};
23
24int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
25{
26 return irq_tab[slot];
27}
28
29static struct resource sh7785_io_resource = {
30 .name = "SH7785_IO",
31 .start = SH7780_PCI_IO_BASE,
32 .end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
33 .flags = IORESOURCE_IO
34};
35
36static struct resource sh7785_mem_resource = {
37 .name = "SH7785_mem",
38 .start = SH7780_PCI_MEMORY_BASE,
39 .end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
40 .flags = IORESOURCE_MEM
41};
42
43struct pci_channel board_pci_channels[] = {
44 { &sh4_pci_ops, &sh7785_io_resource, &sh7785_mem_resource, 0, 0xff },
45 { NULL, NULL, NULL, 0, 0 },
46};
47EXPORT_SYMBOL(board_pci_channels);
48
49static struct sh4_pci_address_map sh7785_pci_map = {
50 .window0 = {
51#if defined(CONFIG_32BIT)
52 .base = SH7780_32BIT_DDR_BASE_ADDR,
53 .size = 0x40000000,
54#else
55 .base = SH7780_CS0_BASE_ADDR,
56 .size = 0x20000000,
57#endif
58 },
59
60 .flags = SH4_PCIC_NO_RESET,
61};
62
63int __init pcibios_init_platform(void)
64{
65 return sh7780_pcic_init(&sh7785_pci_map);
66}
diff --git a/arch/sh/drivers/pci/ops-snapgear.c b/arch/sh/drivers/pci/ops-snapgear.c
deleted file mode 100644
index 53dd893d4e54..000000000000
--- a/arch/sh/drivers/pci/ops-snapgear.c
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * arch/sh/drivers/pci/ops-snapgear.c
3 *
4 * Author: David McCullough <davidm@snapgear.com>
5 *
6 * Ported to new API by Paul Mundt <lethal@linux-sh.org>
7 *
8 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
9 *
10 * May be copied or modified under the terms of the GNU General Public
11 * License. See linux/COPYING for more information.
12 *
13 * PCI initialization for the SnapGear boards
14 */
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/init.h>
18#include <linux/pci.h>
19#include "pci-sh4.h"
20
21#define SNAPGEAR_PCI_IO 0x4000
22#define SNAPGEAR_PCI_MEM 0xfd000000
23
24/* PCI: default LOCAL memory window sizes (seen from PCI bus) */
25#define SNAPGEAR_LSR0_SIZE (64*(1<<20)) //64MB
26#define SNAPGEAR_LSR1_SIZE (64*(1<<20)) //64MB
27
28static struct resource sh7751_io_resource = {
29 .name = "SH7751 IO",
30 .start = SNAPGEAR_PCI_IO,
31 .end = SNAPGEAR_PCI_IO + (64*1024) - 1, /* 64KiB I/O */
32 .flags = IORESOURCE_IO,
33};
34
35static struct resource sh7751_mem_resource = {
36 .name = "SH7751 mem",
37 .start = SNAPGEAR_PCI_MEM,
38 .end = SNAPGEAR_PCI_MEM + (64*1024*1024) - 1, /* 64MiB mem */
39 .flags = IORESOURCE_MEM,
40};
41
42struct pci_channel board_pci_channels[] = {
43 { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
44 { 0, }
45};
46
47static struct sh4_pci_address_map sh7751_pci_map = {
48 .window0 = {
49 .base = SH7751_CS2_BASE_ADDR,
50 .size = SNAPGEAR_LSR0_SIZE,
51 },
52
53 .window1 = {
54 .base = SH7751_CS2_BASE_ADDR,
55 .size = SNAPGEAR_LSR1_SIZE,
56 },
57
58 .flags = SH4_PCIC_NO_RESET,
59};
60
61/*
62 * Initialize the SnapGear PCI interface
63 * Setup hardware to be Central Funtion
64 * Copy the BSR regs to the PCI interface
65 * Setup PCI windows into local RAM
66 */
67int __init pcibios_init_platform(void)
68{
69 return sh7751_pcic_init(&sh7751_pci_map);
70}
71
72int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
73{
74 int irq = -1;
75
76 switch (slot) {
77 case 8: /* the PCI bridge */ break;
78 case 11: irq = 8; break; /* USB */
79 case 12: irq = 11; break; /* PCMCIA */
80 case 13: irq = 5; break; /* eth0 */
81 case 14: irq = 8; break; /* eth1 */
82 case 15: irq = 11; break; /* safenet (unused) */
83 }
84
85 printk("PCI: Mapping SnapGear IRQ for slot %d, pin %c to irq %d\n",
86 slot, pin - 1 + 'A', irq);
87
88 return irq;
89}
90
91void __init pcibios_fixup(void)
92{
93 /* Nothing to fixup .. */
94}
diff --git a/arch/sh/drivers/pci/pci-auto.c b/arch/sh/drivers/pci/pci-auto.c
deleted file mode 100644
index cf48b12ee58c..000000000000
--- a/arch/sh/drivers/pci/pci-auto.c
+++ /dev/null
@@ -1,545 +0,0 @@
1/*
2 * PCI autoconfiguration library
3 *
4 * Author: Matt Porter <mporter@mvista.com>
5 *
6 * Copyright 2000, 2001 MontaVista Software Inc.
7 * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
8 * Copyright 2003 Paul Mundt <lethal@linux-sh.org>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16/*
17 * Modified for MIPS by Jun Sun, jsun@mvista.com
18 *
19 * . Simplify the interface between pci_auto and the rest: a single function.
20 * . Assign resources from low address to upper address.
21 * . change most int to u32.
22 *
23 * Further modified to include it as mips generic code, ppopov@mvista.com.
24 *
25 * 2001-10-26 Bradley D. LaRonde <brad@ltc.com>
26 * - Add a top_bus argument to the "early config" functions so that
27 * they can set a fake parent bus pointer to convince the underlying
28 * pci ops to use type 1 configuration for sub busses.
29 * - Set bridge base and limit registers correctly.
30 * - Align io and memory base properly before and after bridge setup.
31 * - Don't fall through to pci_setup_bars for bridge.
32 * - Reformat the debug output to look more like lspci's output.
33 *
34 * Cloned for SuperH by M. R. Brown, mrbrown@0xd6.org
35 *
36 * 2003-08-05 Paul Mundt <lethal@linux-sh.org>
37 * - Don't update the BAR values on systems that already have valid addresses
38 * and don't want these updated for whatever reason, by way of a new config
39 * option check. However, we still read in the old BAR values so that they
40 * can still be reported through the debug output.
41 */
42
43#include <linux/kernel.h>
44#include <linux/init.h>
45#include <linux/types.h>
46#include <linux/pci.h>
47
48#define DEBUG
49#ifdef DEBUG
50#define DBG(x...) printk(x)
51#else
52#define DBG(x...)
53#endif
54
55/*
56 * These functions are used early on before PCI scanning is done
57 * and all of the pci_dev and pci_bus structures have been created.
58 */
59static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
60 int top_bus, int busnr, int devfn)
61{
62 static struct pci_dev dev;
63 static struct pci_bus bus;
64
65 dev.bus = &bus;
66 dev.sysdata = hose;
67 dev.devfn = devfn;
68 bus.number = busnr;
69 bus.ops = hose->pci_ops;
70
71 if(busnr != top_bus)
72 /* Fake a parent bus structure. */
73 bus.parent = &bus;
74 else
75 bus.parent = NULL;
76
77 return &dev;
78}
79
80#define EARLY_PCI_OP(rw, size, type) \
81static int early_##rw##_config_##size(struct pci_channel *hose, \
82 int top_bus, int bus, int devfn, int offset, type value) \
83{ \
84 return pci_##rw##_config_##size( \
85 fake_pci_dev(hose, top_bus, bus, devfn), \
86 offset, value); \
87}
88
89EARLY_PCI_OP(read, byte, u8 *)
90EARLY_PCI_OP(read, word, u16 *)
91EARLY_PCI_OP(read, dword, u32 *)
92EARLY_PCI_OP(write, byte, u8)
93EARLY_PCI_OP(write, word, u16)
94EARLY_PCI_OP(write, dword, u32)
95
96static struct resource *io_resource_inuse;
97static struct resource *mem_resource_inuse;
98
99static u32 pciauto_lower_iospc;
100static u32 pciauto_upper_iospc;
101
102static u32 pciauto_lower_memspc;
103static u32 pciauto_upper_memspc;
104
105static void __init
106pciauto_setup_bars(struct pci_channel *hose,
107 int top_bus,
108 int current_bus,
109 int pci_devfn,
110 int bar_limit)
111{
112 u32 bar_response, bar_size, bar_value;
113 u32 bar, addr_mask, bar_nr = 0;
114 u32 * upper_limit;
115 u32 * lower_limit;
116 int found_mem64 = 0;
117
118 for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
119 u32 bar_addr;
120
121 /* Read the old BAR value */
122 early_read_config_dword(hose, top_bus,
123 current_bus,
124 pci_devfn,
125 bar,
126 &bar_addr);
127
128 /* Tickle the BAR and get the response */
129 early_write_config_dword(hose, top_bus,
130 current_bus,
131 pci_devfn,
132 bar,
133 0xffffffff);
134
135 early_read_config_dword(hose, top_bus,
136 current_bus,
137 pci_devfn,
138 bar,
139 &bar_response);
140
141 /*
142 * Write the old BAR value back out, only update the BAR
143 * if we implicitly want resources to be updated, which
144 * is done by the generic code further down. -- PFM.
145 */
146 early_write_config_dword(hose, top_bus,
147 current_bus,
148 pci_devfn,
149 bar,
150 bar_addr);
151
152 /* If BAR is not implemented go to the next BAR */
153 if (!bar_response)
154 continue;
155
156 /*
157 * Workaround for a BAR that doesn't use its upper word,
158 * like the ALi 1535D+ PCI DC-97 Controller Modem (M5457).
159 * bdl <brad@ltc.com>
160 */
161 if (!(bar_response & 0xffff0000))
162 bar_response |= 0xffff0000;
163
164retry:
165 /* Check the BAR type and set our address mask */
166 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
167 addr_mask = PCI_BASE_ADDRESS_IO_MASK;
168 upper_limit = &pciauto_upper_iospc;
169 lower_limit = &pciauto_lower_iospc;
170 DBG(" I/O");
171 } else {
172 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
173 PCI_BASE_ADDRESS_MEM_TYPE_64)
174 found_mem64 = 1;
175
176 addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
177 upper_limit = &pciauto_upper_memspc;
178 lower_limit = &pciauto_lower_memspc;
179 DBG(" Mem");
180 }
181
182
183 /* Calculate requested size */
184 bar_size = ~(bar_response & addr_mask) + 1;
185
186 /* Allocate a base address */
187 bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
188
189 if ((bar_value + bar_size) > *upper_limit) {
190 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
191 if (io_resource_inuse->child) {
192 io_resource_inuse =
193 io_resource_inuse->child;
194 pciauto_lower_iospc =
195 io_resource_inuse->start;
196 pciauto_upper_iospc =
197 io_resource_inuse->end + 1;
198 goto retry;
199 }
200
201 } else {
202 if (mem_resource_inuse->child) {
203 mem_resource_inuse =
204 mem_resource_inuse->child;
205 pciauto_lower_memspc =
206 mem_resource_inuse->start;
207 pciauto_upper_memspc =
208 mem_resource_inuse->end + 1;
209 goto retry;
210 }
211 }
212 DBG(" unavailable -- skipping, value %x size %x\n",
213 bar_value, bar_size);
214 continue;
215 }
216
217 if (bar_value < *lower_limit || (bar_value + bar_size) >= *upper_limit) {
218 DBG(" unavailable -- skipping, value %x size %x\n",
219 bar_value, bar_size);
220 continue;
221 }
222
223#ifdef CONFIG_PCI_AUTO_UPDATE_RESOURCES
224 /* Write it out and update our limit */
225 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
226 bar, bar_value);
227#endif
228
229 *lower_limit = bar_value + bar_size;
230
231 /*
232 * If we are a 64-bit decoder then increment to the
233 * upper 32 bits of the bar and force it to locate
234 * in the lower 4GB of memory.
235 */
236 if (found_mem64) {
237 bar += 4;
238 early_write_config_dword(hose, top_bus,
239 current_bus,
240 pci_devfn,
241 bar,
242 0x00000000);
243 }
244
245 DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size);
246
247 bar_nr++;
248 }
249
250}
251
252static void __init
253pciauto_prescan_setup_bridge(struct pci_channel *hose,
254 int top_bus,
255 int current_bus,
256 int pci_devfn,
257 int sub_bus)
258{
259 /* Configure bus number registers */
260 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
261 PCI_PRIMARY_BUS, current_bus);
262 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
263 PCI_SECONDARY_BUS, sub_bus + 1);
264 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
265 PCI_SUBORDINATE_BUS, 0xff);
266
267 /* Align memory and I/O to 1MB and 4KB boundaries. */
268 pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
269 & ~(0x100000 - 1);
270 pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
271 & ~(0x1000 - 1);
272
273 /* Set base (lower limit) of address range behind bridge. */
274 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
275 PCI_MEMORY_BASE, pciauto_lower_memspc >> 16);
276 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
277 PCI_IO_BASE, (pciauto_lower_iospc & 0x0000f000) >> 8);
278 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
279 PCI_IO_BASE_UPPER16, pciauto_lower_iospc >> 16);
280
281 /* We don't support prefetchable memory for now, so disable */
282 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
283 PCI_PREF_MEMORY_BASE, 0);
284 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
285 PCI_PREF_MEMORY_LIMIT, 0);
286}
287
288static void __init
289pciauto_postscan_setup_bridge(struct pci_channel *hose,
290 int top_bus,
291 int current_bus,
292 int pci_devfn,
293 int sub_bus)
294{
295 u32 temp;
296
297 /*
298 * [jsun] we always bump up baselines a little, so that if there
299 * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
300 * spaces.
301 */
302 pciauto_lower_memspc += 1;
303 pciauto_lower_iospc += 1;
304
305 /* Configure bus number registers */
306 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
307 PCI_SUBORDINATE_BUS, sub_bus);
308
309 /* Set upper limit of address range behind bridge. */
310 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
311 PCI_MEMORY_LIMIT, pciauto_lower_memspc >> 16);
312 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
313 PCI_IO_LIMIT, (pciauto_lower_iospc & 0x0000f000) >> 8);
314 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
315 PCI_IO_LIMIT_UPPER16, pciauto_lower_iospc >> 16);
316
317 /* Align memory and I/O to 1MB and 4KB boundaries. */
318 pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
319 & ~(0x100000 - 1);
320 pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
321 & ~(0x1000 - 1);
322
323 /* Enable memory and I/O accesses, enable bus master */
324 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
325 PCI_COMMAND, &temp);
326 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
327 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
328 | PCI_COMMAND_MASTER);
329}
330
331static void __init
332pciauto_prescan_setup_cardbus_bridge(struct pci_channel *hose,
333 int top_bus,
334 int current_bus,
335 int pci_devfn,
336 int sub_bus)
337{
338 /* Configure bus number registers */
339 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
340 PCI_PRIMARY_BUS, current_bus);
341 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
342 PCI_SECONDARY_BUS, sub_bus + 1);
343 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
344 PCI_SUBORDINATE_BUS, 0xff);
345
346 /* Align memory and I/O to 4KB and 4 byte boundaries. */
347 pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
348 & ~(0x1000 - 1);
349 pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
350 & ~(0x4 - 1);
351
352 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
353 PCI_CB_MEMORY_BASE_0, pciauto_lower_memspc);
354 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
355 PCI_CB_IO_BASE_0, pciauto_lower_iospc);
356}
357
358static void __init
359pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
360 int top_bus,
361 int current_bus,
362 int pci_devfn,
363 int sub_bus)
364{
365 u32 temp;
366
367 /*
368 * [jsun] we always bump up baselines a little, so that if there
369 * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
370 * spaces.
371 */
372 pciauto_lower_memspc += 1;
373 pciauto_lower_iospc += 1;
374
375 /*
376 * Configure subordinate bus number. The PCI subsystem
377 * bus scan will renumber buses (reserving three additional
378 * for this PCI<->CardBus bridge for the case where a CardBus
379 * adapter contains a P2P or CB2CB bridge.
380 */
381
382 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
383 PCI_SUBORDINATE_BUS, sub_bus);
384
385 /*
386 * Reserve an additional 4MB for mem space and 16KB for
387 * I/O space. This should cover any additional space
388 * requirement of unusual CardBus devices with
389 * additional bridges that can consume more address space.
390 *
391 * Although pcmcia-cs currently will reprogram bridge
392 * windows, the goal is to add an option to leave them
393 * alone and use the bridge window ranges as the regions
394 * that are searched for free resources upon hot-insertion
395 * of a device. This will allow a PCI<->CardBus bridge
396 * configured by this routine to happily live behind a
397 * P2P bridge in a system.
398 */
399 /* Align memory and I/O to 4KB and 4 byte boundaries. */
400 pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
401 & ~(0x1000 - 1);
402 pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
403 & ~(0x4 - 1);
404 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
405 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
406 PCI_CB_MEMORY_LIMIT_0, pciauto_lower_memspc - 1);
407 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
408 PCI_CB_IO_LIMIT_0, pciauto_lower_iospc - 1);
409
410 /* Enable memory and I/O accesses, enable bus master */
411 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
412 PCI_COMMAND, &temp);
413 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
414 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
415 PCI_COMMAND_MASTER);
416}
417
418#define PCIAUTO_IDE_MODE_MASK 0x05
419
420static int __init
421pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
422{
423 int sub_bus;
424 u32 pci_devfn, pci_class, cmdstat, found_multi=0;
425 unsigned short vid, did;
426 unsigned char header_type;
427 int devfn_start = 0;
428 int devfn_stop = 0xff;
429
430 sub_bus = current_bus;
431
432 if (hose->first_devfn)
433 devfn_start = hose->first_devfn;
434 if (hose->last_devfn)
435 devfn_stop = hose->last_devfn;
436
437 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
438
439 if (PCI_FUNC(pci_devfn) && !found_multi)
440 continue;
441
442 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
443 PCI_VENDOR_ID, &vid);
444
445 if (vid == 0xffff) continue;
446
447 early_read_config_byte(hose, top_bus, current_bus, pci_devfn,
448 PCI_HEADER_TYPE, &header_type);
449
450 if (!PCI_FUNC(pci_devfn))
451 found_multi = header_type & 0x80;
452
453 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
454 PCI_DEVICE_ID, &did);
455
456 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
457 PCI_CLASS_REVISION, &pci_class);
458
459 DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x",
460 current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn),
461 pci_class >> 16, vid, did);
462 if (pci_class & 0xff)
463 DBG(" (rev %.2x)", pci_class & 0xff);
464 DBG("\n");
465
466 if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
467 DBG(" Bridge: primary=%.2x, secondary=%.2x\n",
468 current_bus, sub_bus + 1);
469 pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
470 pci_devfn, sub_bus);
471 DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
472 sub_bus + 1,
473 pciauto_lower_iospc, pciauto_lower_memspc);
474 sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
475 DBG("Back to bus %.2x\n", current_bus);
476 pciauto_postscan_setup_bridge(hose, top_bus, current_bus,
477 pci_devfn, sub_bus);
478 continue;
479 } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
480 DBG(" CARDBUS Bridge: primary=%.2x, secondary=%.2x\n",
481 current_bus, sub_bus + 1);
482 DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
483 /* Place CardBus Socket/ExCA registers */
484 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_0);
485
486 pciauto_prescan_setup_cardbus_bridge(hose, top_bus,
487 current_bus, pci_devfn, sub_bus);
488
489 DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
490 sub_bus + 1,
491 pciauto_lower_iospc, pciauto_lower_memspc);
492 sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
493 DBG("Back to bus %.2x, sub_bus is %x\n", current_bus, sub_bus);
494 pciauto_postscan_setup_cardbus_bridge(hose, top_bus,
495 current_bus, pci_devfn, sub_bus);
496 continue;
497 } else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
498
499 unsigned char prg_iface;
500
501 early_read_config_byte(hose, top_bus, current_bus,
502 pci_devfn, PCI_CLASS_PROG, &prg_iface);
503 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
504 DBG("Skipping legacy mode IDE controller\n");
505 continue;
506 }
507 }
508
509 /*
510 * Found a peripheral, enable some standard
511 * settings
512 */
513 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
514 PCI_COMMAND, &cmdstat);
515 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
516 PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
517 PCI_COMMAND_MEMORY |
518 PCI_COMMAND_MASTER);
519 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
520 PCI_LATENCY_TIMER, 0x80);
521
522 /* Allocate PCI I/O and/or memory space */
523 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_5);
524 }
525 return sub_bus;
526}
527
528int __init
529pciauto_assign_resources(int busno, struct pci_channel *hose)
530{
531 /* setup resource limits */
532 io_resource_inuse = hose->io_resource;
533 mem_resource_inuse = hose->mem_resource;
534
535 pciauto_lower_iospc = io_resource_inuse->start;
536 pciauto_upper_iospc = io_resource_inuse->end + 1;
537 pciauto_lower_memspc = mem_resource_inuse->start;
538 pciauto_upper_memspc = mem_resource_inuse->end + 1;
539 DBG("Autoconfig PCI channel 0x%p\n", hose);
540 DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n",
541 busno, pciauto_lower_iospc, pciauto_upper_iospc,
542 pciauto_lower_memspc, pciauto_upper_memspc);
543
544 return pciauto_bus_scan(hose, busno, busno);
545}
diff --git a/arch/sh/drivers/pci/pci-dreamcast.c b/arch/sh/drivers/pci/pci-dreamcast.c
new file mode 100644
index 000000000000..210f9d4af141
--- /dev/null
+++ b/arch/sh/drivers/pci/pci-dreamcast.c
@@ -0,0 +1,102 @@
1/*
2 * PCI support for the Sega Dreamcast
3 *
4 * Copyright (C) 2001, 2002 M. R. Brown
5 * Copyright (C) 2002, 2003 Paul Mundt
6 *
7 * This file originally bore the message (with enclosed-$):
8 * Id: pci.c,v 1.3 2003/05/04 19:29:46 lethal Exp
9 * Dreamcast PCI: Supports SEGA Broadband Adaptor only.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15
16#include <linux/sched.h>
17#include <linux/kernel.h>
18#include <linux/param.h>
19#include <linux/interrupt.h>
20#include <linux/init.h>
21#include <linux/irq.h>
22#include <linux/pci.h>
23#include <linux/module.h>
24#include <asm/io.h>
25#include <asm/irq.h>
26#include <mach/pci.h>
27
28static struct resource gapspci_io_resource = {
29 .name = "GAPSPCI IO",
30 .start = GAPSPCI_BBA_CONFIG,
31 .end = GAPSPCI_BBA_CONFIG + GAPSPCI_BBA_CONFIG_SIZE - 1,
32 .flags = IORESOURCE_IO,
33};
34
35static struct resource gapspci_mem_resource = {
36 .name = "GAPSPCI mem",
37 .start = GAPSPCI_DMA_BASE,
38 .end = GAPSPCI_DMA_BASE + GAPSPCI_DMA_SIZE - 1,
39 .flags = IORESOURCE_MEM,
40};
41
42static struct pci_channel dreamcast_pci_controller = {
43 .pci_ops = &gapspci_pci_ops,
44 .io_resource = &gapspci_io_resource,
45 .io_offset = 0x00000000,
46 .mem_resource = &gapspci_mem_resource,
47 .mem_offset = 0x00000000,
48};
49
50/*
51 * gapspci init
52 */
53
54static int __init gapspci_init(void)
55{
56 char idbuf[16];
57 int i;
58
59 /*
60 * FIXME: All of this wants documenting to some degree,
61 * even some basic register definitions would be nice.
62 *
63 * I haven't seen anything this ugly since.. maple.
64 */
65
66 for (i=0; i<16; i++)
67 idbuf[i] = inb(GAPSPCI_REGS+i);
68
69 if (strncmp(idbuf, "GAPSPCI_BRIDGE_2", 16))
70 return -ENODEV;
71
72 outl(0x5a14a501, GAPSPCI_REGS+0x18);
73
74 for (i=0; i<1000000; i++)
75 cpu_relax();
76
77 if (inl(GAPSPCI_REGS+0x18) != 1)
78 return -EINVAL;
79
80 outl(0x01000000, GAPSPCI_REGS+0x20);
81 outl(0x01000000, GAPSPCI_REGS+0x24);
82
83 outl(GAPSPCI_DMA_BASE, GAPSPCI_REGS+0x28);
84 outl(GAPSPCI_DMA_BASE+GAPSPCI_DMA_SIZE, GAPSPCI_REGS+0x2c);
85
86 outl(1, GAPSPCI_REGS+0x14);
87 outl(1, GAPSPCI_REGS+0x34);
88
89 /* Setting Broadband Adapter */
90 outw(0xf900, GAPSPCI_BBA_CONFIG+0x06);
91 outl(0x00000000, GAPSPCI_BBA_CONFIG+0x30);
92 outb(0x00, GAPSPCI_BBA_CONFIG+0x3c);
93 outb(0xf0, GAPSPCI_BBA_CONFIG+0x0d);
94 outw(0x0006, GAPSPCI_BBA_CONFIG+0x04);
95 outl(0x00002001, GAPSPCI_BBA_CONFIG+0x10);
96 outl(0x01000000, GAPSPCI_BBA_CONFIG+0x14);
97
98 register_pci_controller(&dreamcast_pci_controller);
99
100 return 0;
101}
102arch_initcall(gapspci_init);
diff --git a/arch/sh/drivers/pci/pci-sh4.h b/arch/sh/drivers/pci/pci-sh4.h
index a83dcf70c13b..3d5296cde622 100644
--- a/arch/sh/drivers/pci/pci-sh4.h
+++ b/arch/sh/drivers/pci/pci-sh4.h
@@ -149,13 +149,10 @@
149 #define SH4_PCIPDTR_PB0 0x000000001 /* Port 0 Enable */ 149 #define SH4_PCIPDTR_PB0 0x000000001 /* Port 0 Enable */
150#define SH4_PCIPDR 0x220 /* Port IO Data Register */ 150#define SH4_PCIPDR 0x220 /* Port IO Data Register */
151 151
152/* Flags */
153#define SH4_PCIC_NO_RESET 0x0001
154
155/* arch/sh/kernel/drivers/pci/ops-sh4.c */ 152/* arch/sh/kernel/drivers/pci/ops-sh4.c */
156extern struct pci_ops sh4_pci_ops; 153extern struct pci_ops sh4_pci_ops;
157int sh4_pci_check_direct(void); 154int sh4_pci_check_direct(struct pci_channel *chan);
158int pci_fixup_pcic(void); 155int pci_fixup_pcic(struct pci_channel *chan);
159 156
160struct sh4_pci_address_space { 157struct sh4_pci_address_space {
161 unsigned long base; 158 unsigned long base;
@@ -165,16 +162,18 @@ struct sh4_pci_address_space {
165struct sh4_pci_address_map { 162struct sh4_pci_address_map {
166 struct sh4_pci_address_space window0; 163 struct sh4_pci_address_space window0;
167 struct sh4_pci_address_space window1; 164 struct sh4_pci_address_space window1;
168 unsigned long flags;
169}; 165};
170 166
171static inline void pci_write_reg(unsigned long val, unsigned long reg) 167static inline void pci_write_reg(struct pci_channel *chan,
168 unsigned long val, unsigned long reg)
172{ 169{
173 ctrl_outl(val, PCI_REG(reg)); 170 ctrl_outl(val, chan->reg_base + reg);
174} 171}
175 172
176static inline unsigned long pci_read_reg(unsigned long reg) 173static inline unsigned long pci_read_reg(struct pci_channel *chan,
174 unsigned long reg)
177{ 175{
178 return ctrl_inl(PCI_REG(reg)); 176 return ctrl_inl(chan->reg_base + reg);
179} 177}
178
180#endif /* __PCI_SH4_H */ 179#endif /* __PCI_SH4_H */
diff --git a/arch/sh/drivers/pci/pci-sh5.c b/arch/sh/drivers/pci/pci-sh5.c
index 7a97438762c8..cf431852213c 100644
--- a/arch/sh/drivers/pci/pci-sh5.c
+++ b/arch/sh/drivers/pci/pci-sh5.c
@@ -89,8 +89,21 @@ static irqreturn_t pcish5_serr_irq(int irq, void *dev_id)
89 return IRQ_NONE; 89 return IRQ_NONE;
90} 90}
91 91
92int __init sh5pci_init(unsigned long memStart, unsigned long memSize) 92static struct resource sh5_io_resource = { /* place holder */ };
93static struct resource sh5_mem_resource = { /* place holder */ };
94
95static struct pci_channel sh5pci_controller = {
96 .pci_ops = &sh5_pci_ops,
97 .mem_resource = &sh5_mem_resource,
98 .mem_offset = 0x00000000,
99 .io_resource = &sh5_io_resource,
100 .io_offset = 0x00000000,
101};
102
103static int __init sh5pci_init(void)
93{ 104{
105 unsigned long memStart = __pa(memory_start);
106 unsigned long memSize = __pa(memory_end) - memStart;
94 u32 lsr0; 107 u32 lsr0;
95 u32 uval; 108 u32 uval;
96 109
@@ -197,32 +210,14 @@ int __init sh5pci_init(unsigned long memStart, unsigned long memSize)
197 SH5PCI_WRITE(AINTM, ~0); 210 SH5PCI_WRITE(AINTM, ~0);
198 SH5PCI_WRITE(PINTM, ~0); 211 SH5PCI_WRITE(PINTM, ~0);
199 212
200 return 0; 213 sh5_io_resource.start = PCI_IO_AREA;
201} 214 sh5_io_resource.end = PCI_IO_AREA + 0x10000;
202 215
203void __devinit pcibios_fixup_bus(struct pci_bus *bus) 216 sh5_mem_resource.start = memStart;
204{ 217 sh5_mem_resource.end = memStart + memSize;
205 struct pci_dev *dev = bus->self; 218
206 int i; 219 register_pci_controller(&sh5pci_controller);
207 220
208 if (dev) { 221 return 0;
209 for (i= 0; i < 3; i++) {
210 bus->resource[i] =
211 &dev->resource[PCI_BRIDGE_RESOURCES+i];
212 bus->resource[i]->name = bus->name;
213 }
214 bus->resource[0]->flags |= IORESOURCE_IO;
215 bus->resource[1]->flags |= IORESOURCE_MEM;
216
217 /* For now, propagate host limits to the bus;
218 * we'll adjust them later. */
219 bus->resource[0]->end = 64*1024 - 1 ;
220 bus->resource[1]->end = PCIBIOS_MIN_MEM+(256*1024*1024)-1;
221 bus->resource[0]->start = PCIBIOS_MIN_IO;
222 bus->resource[1]->start = PCIBIOS_MIN_MEM;
223
224 /* Turn off downstream PF memory address range by default */
225 bus->resource[2]->start = 1024*1024;
226 bus->resource[2]->end = bus->resource[2]->start - 1;
227 }
228} 222}
223arch_initcall(sh5pci_init);
diff --git a/arch/sh/drivers/pci/pci-sh5.h b/arch/sh/drivers/pci/pci-sh5.h
index 7cff3fc04d30..f277628221f3 100644
--- a/arch/sh/drivers/pci/pci-sh5.h
+++ b/arch/sh/drivers/pci/pci-sh5.h
@@ -107,7 +107,4 @@ extern unsigned long pcicr_virt;
107 107
108extern struct pci_ops sh5_pci_ops; 108extern struct pci_ops sh5_pci_ops;
109 109
110/* arch/sh/drivers/pci/pci-sh5.c */
111int sh5pci_init(unsigned long memStart, unsigned long memSize);
112
113#endif /* __PCI_SH5_H */ 110#endif /* __PCI_SH5_H */
diff --git a/arch/sh/drivers/pci/pci-sh7751.c b/arch/sh/drivers/pci/pci-sh7751.c
index 3065eb184f01..c4fa0bb13976 100644
--- a/arch/sh/drivers/pci/pci-sh7751.c
+++ b/arch/sh/drivers/pci/pci-sh7751.c
@@ -1,88 +1,99 @@
1/* 1/*
2 * Low-Level PCI Support for the SH7751 2 * Low-Level PCI Support for the SH7751
3 * 3 *
4 * Dustin McIntire (dustin@sensoria.com) 4 * Copyright (C) 2003 - 2009 Paul Mundt
5 * Derived from arch/i386/kernel/pci-*.c which bore the message: 5 * Copyright (C) 2001 Dustin McIntire
6 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
7 * 6 *
8 * Ported to the new API by Paul Mundt <lethal@linux-sh.org> 7 * With cleanup by Paul van Gool <pvangool@mimotech.com>, 2003.
9 * With cleanup by Paul van Gool <pvangool@mimotech.com>
10 *
11 * May be copied or modified under the terms of the GNU General Public
12 * License. See linux/COPYING for more information.
13 * 8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
14 */ 12 */
15#undef DEBUG
16
17#include <linux/init.h> 13#include <linux/init.h>
18#include <linux/pci.h> 14#include <linux/pci.h>
19#include <linux/types.h> 15#include <linux/types.h>
20#include <linux/errno.h> 16#include <linux/errno.h>
21#include <linux/delay.h> 17#include <linux/io.h>
22#include "pci-sh4.h" 18#include "pci-sh4.h"
23#include <asm/addrspace.h> 19#include <asm/addrspace.h>
24#include <asm/io.h>
25 20
26/* 21static int __init __area_sdram_check(struct pci_channel *chan,
27 * Initialization. Try all known PCI access methods. Note that we support 22 unsigned int area)
28 * using both PCI BIOS and direct access: in such cases, we use I/O ports
29 * to access config space.
30 *
31 * Note that the platform specific initialization (BSC registers, and memory
32 * space mapping) will be called via the platform defined function
33 * pcibios_init_platform().
34 */
35static int __init sh7751_pci_init(void)
36{ 23{
37 unsigned int id; 24 unsigned long word;
38 int ret;
39
40 pr_debug("PCI: Starting intialization.\n");
41 25
42 /* check for SH7751/SH7751R hardware */ 26 word = __raw_readl(SH7751_BCR1);
43 id = pci_read_reg(SH7751_PCICONF0);
44 if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
45 id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
46 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
47 return -ENODEV;
48 }
49
50 if ((ret = sh4_pci_check_direct()) != 0)
51 return ret;
52
53 return pcibios_init_platform();
54}
55subsys_initcall(sh7751_pci_init);
56
57static int __init __area_sdram_check(unsigned int area)
58{
59 u32 word;
60
61 word = ctrl_inl(SH7751_BCR1);
62 /* check BCR for SDRAM in area */ 27 /* check BCR for SDRAM in area */
63 if (((word >> area) & 1) == 0) { 28 if (((word >> area) & 1) == 0) {
64 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n", 29 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n",
65 area, word); 30 area, word);
66 return 0; 31 return 0;
67 } 32 }
68 pci_write_reg(word, SH4_PCIBCR1); 33 pci_write_reg(chan, word, SH4_PCIBCR1);
69 34
70 word = (u16)ctrl_inw(SH7751_BCR2); 35 word = __raw_readw(SH7751_BCR2);
71 /* check BCR2 for 32bit SDRAM interface*/ 36 /* check BCR2 for 32bit SDRAM interface*/
72 if (((word >> (area << 1)) & 0x3) != 0x3) { 37 if (((word >> (area << 1)) & 0x3) != 0x3) {
73 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n", 38 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n",
74 area, word); 39 area, word);
75 return 0; 40 return 0;
76 } 41 }
77 pci_write_reg(word, SH4_PCIBCR2); 42 pci_write_reg(chan, word, SH4_PCIBCR2);
78 43
79 return 1; 44 return 1;
80} 45}
81 46
82int __init sh7751_pcic_init(struct sh4_pci_address_map *map) 47static struct resource sh7751_io_resource = {
48 .name = "SH7751_IO",
49 .start = SH7751_PCI_IO_BASE,
50 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
51 .flags = IORESOURCE_IO
52};
53
54static struct resource sh7751_mem_resource = {
55 .name = "SH7785_mem",
56 .start = SH7751_PCI_MEMORY_BASE,
57 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
58 .flags = IORESOURCE_MEM
59};
60
61static struct pci_channel sh7751_pci_controller = {
62 .pci_ops = &sh4_pci_ops,
63 .mem_resource = &sh7751_mem_resource,
64 .mem_offset = 0x00000000,
65 .io_resource = &sh7751_io_resource,
66 .io_offset = 0x00000000,
67};
68
69static struct sh4_pci_address_map sh7751_pci_map = {
70 .window0 = {
71 .base = SH7751_CS3_BASE_ADDR,
72 .size = 0x04000000,
73 },
74};
75
76static int __init sh7751_pci_init(void)
83{ 77{
84 u32 reg; 78 struct pci_channel *chan = &sh7751_pci_controller;
85 u32 word; 79 unsigned int id;
80 u32 word, reg;
81 int ret;
82
83 printk(KERN_NOTICE "PCI: Starting intialization.\n");
84
85 chan->reg_base = 0xfe200000;
86
87 /* check for SH7751/SH7751R hardware */
88 id = pci_read_reg(chan, SH7751_PCICONF0);
89 if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
90 id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
91 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
92 return -ENODEV;
93 }
94
95 if ((ret = sh4_pci_check_direct(chan)) != 0)
96 return ret;
86 97
87 /* Set the BCR's to enable PCI access */ 98 /* Set the BCR's to enable PCI access */
88 reg = ctrl_inl(SH7751_BCR1); 99 reg = ctrl_inl(SH7751_BCR1);
@@ -90,25 +101,10 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
90 ctrl_outl(reg, SH7751_BCR1); 101 ctrl_outl(reg, SH7751_BCR1);
91 102
92 /* Turn the clocks back on (not done in reset)*/ 103 /* Turn the clocks back on (not done in reset)*/
93 pci_write_reg(0, SH4_PCICLKR); 104 pci_write_reg(chan, 0, SH4_PCICLKR);
94 /* Clear Powerdown IRQ's (not done in reset) */ 105 /* Clear Powerdown IRQ's (not done in reset) */
95 word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0; 106 word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0;
96 pci_write_reg(word, SH4_PCIPINT); 107 pci_write_reg(chan, word, SH4_PCIPINT);
97
98 /*
99 * This code is unused for some boards as it is done in the
100 * bootloader and doing it here means the MAC addresses loaded
101 * by the bootloader get lost.
102 */
103 if (!(map->flags & SH4_PCIC_NO_RESET)) {
104 /* toggle PCI reset pin */
105 word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
106 pci_write_reg(word, SH4_PCICR);
107 /* Wait for a long time... not 1 sec. but long enough */
108 mdelay(100);
109 word = SH4_PCICR_PREFIX;
110 pci_write_reg(word, SH4_PCICR);
111 }
112 108
113 /* set the command/status bits to: 109 /* set the command/status bits to:
114 * Wait Cycle Control + Parity Enable + Bus Master + 110 * Wait Cycle Control + Parity Enable + Bus Master +
@@ -116,89 +112,77 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
116 */ 112 */
117 word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER | 113 word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
118 SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES; 114 SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
119 pci_write_reg(word, SH7751_PCICONF1); 115 pci_write_reg(chan, word, SH7751_PCICONF1);
120 116
121 /* define this host as the host bridge */ 117 /* define this host as the host bridge */
122 word = PCI_BASE_CLASS_BRIDGE << 24; 118 word = PCI_BASE_CLASS_BRIDGE << 24;
123 pci_write_reg(word, SH7751_PCICONF2); 119 pci_write_reg(chan, word, SH7751_PCICONF2);
124 120
125 /* Set IO and Mem windows to local address 121 /* Set IO and Mem windows to local address
126 * Make PCI and local address the same for easy 1 to 1 mapping 122 * Make PCI and local address the same for easy 1 to 1 mapping
127 * Window0 = map->window0.size @ non-cached area base = SDRAM
128 * Window1 = map->window1.size @ cached area base = SDRAM
129 */ 123 */
130 word = map->window0.size - 1; 124 word = sh7751_pci_map.window0.size - 1;
131 pci_write_reg(word, SH4_PCILSR0); 125 pci_write_reg(chan, word, SH4_PCILSR0);
132 word = map->window1.size - 1;
133 pci_write_reg(word, SH4_PCILSR1);
134 /* Set the values on window 0 PCI config registers */ 126 /* Set the values on window 0 PCI config registers */
135 word = P2SEGADDR(map->window0.base); 127 word = P2SEGADDR(sh7751_pci_map.window0.base);
136 pci_write_reg(word, SH4_PCILAR0); 128 pci_write_reg(chan, word, SH4_PCILAR0);
137 pci_write_reg(word, SH7751_PCICONF5); 129 pci_write_reg(chan, word, SH7751_PCICONF5);
138 /* Set the values on window 1 PCI config registers */
139 word = PHYSADDR(map->window1.base);
140 pci_write_reg(word, SH4_PCILAR1);
141 pci_write_reg(word, SH7751_PCICONF6);
142 130
143 /* Set the local 16MB PCI memory space window to 131 /* Set the local 16MB PCI memory space window to
144 * the lowest PCI mapped address 132 * the lowest PCI mapped address
145 */ 133 */
146 word = PCIBIOS_MIN_MEM & SH4_PCIMBR_MASK; 134 word = chan->mem_resource->start & SH4_PCIMBR_MASK;
147 pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word); 135 pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);
148 pci_write_reg(word , SH4_PCIMBR); 136 pci_write_reg(chan, word , SH4_PCIMBR);
149
150 /* Map IO space into PCI IO window
151 * The IO window is 64K-PCIBIOS_MIN_IO in size
152 * IO addresses will be translated to the
153 * PCI IO window base address
154 */
155 pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
156 PCIBIOS_MIN_IO, (64 << 10),
157 SH7751_PCI_IO_BASE + PCIBIOS_MIN_IO);
158 137
159 /* Make sure the MSB's of IO window are set to access PCI space 138 /* Make sure the MSB's of IO window are set to access PCI space
160 * correctly */ 139 * correctly */
161 word = PCIBIOS_MIN_IO & SH4_PCIIOBR_MASK; 140 word = chan->io_resource->start & SH4_PCIIOBR_MASK;
162 pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word); 141 pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);
163 pci_write_reg(word, SH4_PCIIOBR); 142 pci_write_reg(chan, word, SH4_PCIIOBR);
164 143
165 /* Set PCI WCRx, BCRx's, copy from BSC locations */ 144 /* Set PCI WCRx, BCRx's, copy from BSC locations */
166 145
167 /* check BCR for SDRAM in specified area */ 146 /* check BCR for SDRAM in specified area */
168 switch (map->window0.base) { 147 switch (sh7751_pci_map.window0.base) {
169 case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(0); break; 148 case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(chan, 0); break;
170 case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(1); break; 149 case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(chan, 1); break;
171 case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(2); break; 150 case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(chan, 2); break;
172 case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(3); break; 151 case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(chan, 3); break;
173 case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(4); break; 152 case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(chan, 4); break;
174 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(5); break; 153 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(chan, 5); break;
175 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(6); break; 154 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(chan, 6); break;
176 } 155 }
177 156
178 if (!word) 157 if (!word)
179 return 0; 158 return -1;
180 159
181 /* configure the wait control registers */ 160 /* configure the wait control registers */
182 word = ctrl_inl(SH7751_WCR1); 161 word = ctrl_inl(SH7751_WCR1);
183 pci_write_reg(word, SH4_PCIWCR1); 162 pci_write_reg(chan, word, SH4_PCIWCR1);
184 word = ctrl_inl(SH7751_WCR2); 163 word = ctrl_inl(SH7751_WCR2);
185 pci_write_reg(word, SH4_PCIWCR2); 164 pci_write_reg(chan, word, SH4_PCIWCR2);
186 word = ctrl_inl(SH7751_WCR3); 165 word = ctrl_inl(SH7751_WCR3);
187 pci_write_reg(word, SH4_PCIWCR3); 166 pci_write_reg(chan, word, SH4_PCIWCR3);
188 word = ctrl_inl(SH7751_MCR); 167 word = ctrl_inl(SH7751_MCR);
189 pci_write_reg(word, SH4_PCIMCR); 168 pci_write_reg(chan, word, SH4_PCIMCR);
190 169
191 /* NOTE: I'm ignoring the PCI error IRQs for now.. 170 /* NOTE: I'm ignoring the PCI error IRQs for now..
192 * TODO: add support for the internal error interrupts and 171 * TODO: add support for the internal error interrupts and
193 * DMA interrupts... 172 * DMA interrupts...
194 */ 173 */
195 174
196 pci_fixup_pcic(); 175 pci_fixup_pcic(chan);
197 176
198 /* SH7751 init done, set central function init complete */ 177 /* SH7751 init done, set central function init complete */
199 /* use round robin mode to stop a device starving/overruning */ 178 /* use round robin mode to stop a device starving/overruning */
200 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM; 179 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
201 pci_write_reg(word, SH4_PCICR); 180 pci_write_reg(chan, word, SH4_PCICR);
202 181
203 return 1; 182 __set_io_port_base(SH7751_PCI_IO_BASE);
183
184 register_pci_controller(chan);
185
186 return 0;
204} 187}
188arch_initcall(sh7751_pci_init);
diff --git a/arch/sh/drivers/pci/pci-sh7751.h b/arch/sh/drivers/pci/pci-sh7751.h
index 68e3cb5e6bec..4983a4d20355 100644
--- a/arch/sh/drivers/pci/pci-sh7751.h
+++ b/arch/sh/drivers/pci/pci-sh7751.h
@@ -26,7 +26,6 @@
26#define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */ 26#define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
27 27
28#define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */ 28#define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
29#define PCI_REG(n) (SH7751_PCIREG_BASE+ n)
30 29
31#define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */ 30#define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */
32 #define SH7751_PCICONF0_DEVID 0xFFFF0000 /* Device ID */ 31 #define SH7751_PCICONF0_DEVID 0xFFFF0000 /* Device ID */
@@ -58,7 +57,7 @@
58 #define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */ 57 #define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */
59 #define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */ 58 #define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */
60 #define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */ 59 #define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */
61#define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */ 60#define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */
62 #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */ 61 #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */
63 #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */ 62 #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */
64 #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */ 63 #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */
@@ -73,12 +72,12 @@
73 #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */ 72 #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
74 #define SH7751_PCICONF5_LAP 0x00000008 /* Prefetch Enabled */ 73 #define SH7751_PCICONF5_LAP 0x00000008 /* Prefetch Enabled */
75 #define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */ 74 #define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */
76 #define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */ 75 #define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */
77#define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */ 76#define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */
78 #define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */ 77 #define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
79 #define SH7751_PCICONF6_LAP 0x00000008 /* Prefetch Enabled */ 78 #define SH7751_PCICONF6_LAP 0x00000008 /* Prefetch Enabled */
80 #define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */ 79 #define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */
81 #define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */ 80 #define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */
82/* PCICONF7 - PCICONF10 are undefined */ 81/* PCICONF7 - PCICONF10 are undefined */
83#define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */ 82#define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */
84 #define SH7751_PCICONF11_SSID 0xFFFF0000 /* Subsystem ID */ 83 #define SH7751_PCICONF11_SSID 0xFFFF0000 /* Subsystem ID */
@@ -127,9 +126,4 @@
127#define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE) 126#define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE)
128#define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE) 127#define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE)
129 128
130struct sh4_pci_address_map;
131
132/* arch/sh/drivers/pci/pci-sh7751.c */
133int sh7751_pcic_init(struct sh4_pci_address_map *map);
134
135#endif /* _PCI_SH7751_H_ */ 129#endif /* _PCI_SH7751_H_ */
diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c
index bae6a2cf047d..ae13ff925c61 100644
--- a/arch/sh/drivers/pci/pci-sh7780.c
+++ b/arch/sh/drivers/pci/pci-sh7780.c
@@ -1,19 +1,12 @@
1/* 1/*
2 * Low-Level PCI Support for the SH7780 2 * Low-Level PCI Support for the SH7780
3 * 3 *
4 * Dustin McIntire (dustin@sensoria.com) 4 * Copyright (C) 2005 - 2009 Paul Mundt
5 * Derived from arch/i386/kernel/pci-*.c which bore the message:
6 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
7 *
8 * Ported to the new API by Paul Mundt <lethal@linux-sh.org>
9 * With cleanup by Paul van Gool <pvangool@mimotech.com>
10 *
11 * May be copied or modified under the terms of the GNU General Public
12 * License. See linux/COPYING for more information.
13 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
14 */ 9 */
15#undef DEBUG
16
17#include <linux/types.h> 10#include <linux/types.h>
18#include <linux/kernel.h> 11#include <linux/kernel.h>
19#include <linux/init.h> 12#include <linux/init.h>
@@ -22,135 +15,137 @@
22#include <linux/delay.h> 15#include <linux/delay.h>
23#include "pci-sh4.h" 16#include "pci-sh4.h"
24 17
25#define INTC_BASE 0xffd00000 18extern u8 pci_cache_line_size;
26#define INTC_ICR0 (INTC_BASE+0x0) 19
27#define INTC_ICR1 (INTC_BASE+0x1c) 20static struct resource sh7785_io_resource = {
28#define INTC_INTPRI (INTC_BASE+0x10) 21 .name = "SH7785_IO",
29#define INTC_INTREQ (INTC_BASE+0x24) 22 .start = SH7780_PCI_IO_BASE,
30#define INTC_INTMSK0 (INTC_BASE+0x44) 23 .end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
31#define INTC_INTMSK1 (INTC_BASE+0x48) 24 .flags = IORESOURCE_IO
32#define INTC_INTMSK2 (INTC_BASE+0x40080) 25};
33#define INTC_INTMSKCLR0 (INTC_BASE+0x64) 26
34#define INTC_INTMSKCLR1 (INTC_BASE+0x68) 27static struct resource sh7785_mem_resource = {
35#define INTC_INTMSKCLR2 (INTC_BASE+0x40084) 28 .name = "SH7785_mem",
36#define INTC_INT2MSKR (INTC_BASE+0x40038) 29 .start = SH7780_PCI_MEMORY_BASE,
37#define INTC_INT2MSKCR (INTC_BASE+0x4003c) 30 .end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
31 .flags = IORESOURCE_MEM
32};
33
34static struct pci_channel sh7780_pci_controller = {
35 .pci_ops = &sh4_pci_ops,
36 .mem_resource = &sh7785_mem_resource,
37 .mem_offset = 0x00000000,
38 .io_resource = &sh7785_io_resource,
39 .io_offset = 0x00000000,
40};
41
42static struct sh4_pci_address_map sh7780_pci_map = {
43 .window0 = {
44#if defined(CONFIG_32BIT)
45 .base = SH7780_32BIT_DDR_BASE_ADDR,
46 .size = 0x40000000,
47#else
48 .base = SH7780_CS0_BASE_ADDR,
49 .size = 0x20000000,
50#endif
51 },
52};
38 53
39/*
40 * Initialization. Try all known PCI access methods. Note that we support
41 * using both PCI BIOS and direct access: in such cases, we use I/O ports
42 * to access config space.
43 *
44 * Note that the platform specific initialization (BSC registers, and memory
45 * space mapping) will be called via the platform defined function
46 * pcibios_init_platform().
47 */
48static int __init sh7780_pci_init(void) 54static int __init sh7780_pci_init(void)
49{ 55{
56 struct pci_channel *chan = &sh7780_pci_controller;
50 unsigned int id; 57 unsigned int id;
51 int ret, match = 0; 58 const char *type = NULL;
52 59 int ret;
53 pr_debug("PCI: Starting intialization.\n"); 60 u32 word;
54
55 ctrl_outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
56
57 /* check for SH7780/SH7780R hardware */
58 id = pci_read_reg(SH7780_PCIVID);
59 if ((id & 0xffff) == SH7780_VENDOR_ID) {
60 switch ((id >> 16) & 0xffff) {
61 case SH7763_DEVICE_ID:
62 case SH7780_DEVICE_ID:
63 case SH7781_DEVICE_ID:
64 case SH7785_DEVICE_ID:
65 match = 1;
66 break;
67 }
68 }
69 61
70 if (unlikely(!match)) { 62 printk(KERN_NOTICE "PCI: Starting intialization.\n");
71 printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id); 63
64 chan->reg_base = 0xfe040000;
65
66 /* Enable CPU access to the PCIC registers. */
67 __raw_writel(PCIECR_ENBL, PCIECR);
68
69 id = __raw_readw(chan->reg_base + SH7780_PCIVID);
70 if (id != SH7780_VENDOR_ID) {
71 printk(KERN_ERR "PCI: Unknown vendor ID 0x%04x.\n", id);
72 return -ENODEV; 72 return -ENODEV;
73 } 73 }
74 74
75 /* Setup the INTC */ 75 id = __raw_readw(chan->reg_base + SH7780_PCIDID);
76 if (mach_is_7780se()) { 76 type = (id == SH7763_DEVICE_ID) ? "SH7763" :
77 /* ICR0: IRL=use separately */ 77 (id == SH7780_DEVICE_ID) ? "SH7780" :
78 ctrl_outl(0x00C00020, INTC_ICR0); 78 (id == SH7781_DEVICE_ID) ? "SH7781" :
79 /* ICR1: detect low level(for 2ndcut) */ 79 (id == SH7785_DEVICE_ID) ? "SH7785" :
80 ctrl_outl(0xAAAA0000, INTC_ICR1); 80 NULL;
81 /* INTPRI: priority=3(all) */ 81 if (unlikely(!type)) {
82 ctrl_outl(0x33333333, INTC_INTPRI); 82 printk(KERN_ERR "PCI: Found an unsupported Renesas host "
83 "controller, device id 0x%04x.\n", id);
84 return -EINVAL;
83 } 85 }
84 86
85 if ((ret = sh4_pci_check_direct()) != 0) 87 printk(KERN_NOTICE "PCI: Found a Renesas %s host "
86 return ret; 88 "controller, revision %d.\n", type,
89 __raw_readb(chan->reg_base + SH7780_PCIRID));
87 90
88 return pcibios_init_platform(); 91 if ((ret = sh4_pci_check_direct(chan)) != 0)
89} 92 return ret;
90core_initcall(sh7780_pci_init);
91
92int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
93{
94 u32 word;
95 93
96 /* 94 /*
97 * This code is unused for some boards as it is done in the 95 * Set the class and sub-class codes.
98 * bootloader and doing it here means the MAC addresses loaded
99 * by the bootloader get lost.
100 */
101 if (!(map->flags & SH4_PCIC_NO_RESET)) {
102 /* toggle PCI reset pin */
103 word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
104 pci_write_reg(word, SH4_PCICR);
105 /* Wait for a long time... not 1 sec. but long enough */
106 mdelay(100);
107 word = SH4_PCICR_PREFIX;
108 pci_write_reg(word, SH4_PCICR);
109 }
110
111 /* set the command/status bits to:
112 * Wait Cycle Control + Parity Enable + Bus Master +
113 * Mem space enable
114 */ 96 */
115 pci_write_reg(0x00000046, SH7780_PCICMD); 97 __raw_writeb(PCI_CLASS_BRIDGE_HOST >> 8,
98 chan->reg_base + SH7780_PCIBCC);
99 __raw_writeb(PCI_CLASS_BRIDGE_HOST & 0xff,
100 chan->reg_base + SH7780_PCISUB);
116 101
117 /* define this host as the host bridge */ 102 pci_cache_line_size = pci_read_reg(chan, SH7780_PCICLS) / 4;
118 word = PCI_BASE_CLASS_BRIDGE << 24;
119 pci_write_reg(word, SH7780_PCIRID);
120 103
121 /* Set IO and Mem windows to local address 104 /*
105 * Set IO and Mem windows to local address
122 * Make PCI and local address the same for easy 1 to 1 mapping 106 * Make PCI and local address the same for easy 1 to 1 mapping
123 */ 107 */
124 pci_write_reg(map->window0.size - 0xfffff, SH4_PCILSR0); 108 pci_write_reg(chan, sh7780_pci_map.window0.size - 0xfffff, SH4_PCILSR0);
125 pci_write_reg(map->window1.size - 0xfffff, SH4_PCILSR1);
126 /* Set the values on window 0 PCI config registers */ 109 /* Set the values on window 0 PCI config registers */
127 pci_write_reg(map->window0.base, SH4_PCILAR0); 110 pci_write_reg(chan, sh7780_pci_map.window0.base, SH4_PCILAR0);
128 pci_write_reg(map->window0.base, SH7780_PCIMBAR0); 111 pci_write_reg(chan, sh7780_pci_map.window0.base, SH7780_PCIMBAR0);
129 /* Set the values on window 1 PCI config registers */
130 pci_write_reg(map->window1.base, SH4_PCILAR1);
131 pci_write_reg(map->window1.base, SH7780_PCIMBAR1);
132
133 /* Map IO space into PCI IO window
134 * The IO window is 64K-PCIBIOS_MIN_IO in size
135 * IO addresses will be translated to the
136 * PCI IO window base address
137 */
138 pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
139 PCIBIOS_MIN_IO, (64 << 10),
140 SH7780_PCI_IO_BASE + PCIBIOS_MIN_IO);
141 112
142 /* NOTE: I'm ignoring the PCI error IRQs for now.. 113 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
143 * TODO: add support for the internal error interrupts and 114
144 * DMA interrupts... 115 /* Set up standard PCI config registers */
145 */ 116 __raw_writew(0xFB00, chan->reg_base + SH7780_PCISTATUS);
117 __raw_writew(0x0047, chan->reg_base + SH7780_PCICMD);
118 __raw_writew(0x1912, chan->reg_base + SH7780_PCISVID);
119 __raw_writew(0x0001, chan->reg_base + SH7780_PCISID);
120
121 __raw_writeb(0x00, chan->reg_base + SH7780_PCIPIF);
146 122
147 /* Apply any last-minute PCIC fixups */ 123 /* Apply any last-minute PCIC fixups */
148 pci_fixup_pcic(); 124 pci_fixup_pcic(chan);
125
126 pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0);
127 pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0);
128
129#ifdef CONFIG_32BIT
130 pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2);
131 pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
132#endif
133
134 /* Set IOBR for windows containing area specified in pci.h */
135 pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),
136 SH7780_PCIIOBR);
137 pci_write_reg(chan, ((SH7780_PCI_IO_SIZE-1) & (7<<18)),
138 SH7780_PCIIOBMR);
149 139
150 /* SH7780 init done, set central function init complete */ 140 /* SH7780 init done, set central function init complete */
151 /* use round robin mode to stop a device starving/overruning */ 141 /* use round robin mode to stop a device starving/overruning */
152 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO; 142 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
153 pci_write_reg(word, SH4_PCICR); 143 pci_write_reg(chan, word, SH4_PCICR);
144
145 __set_io_port_base(SH7780_PCI_IO_BASE);
146
147 register_pci_controller(chan);
154 148
155 return 1; 149 return 0;
156} 150}
151arch_initcall(sh7780_pci_init);
diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h
index 93adc7119b79..4a52478c97cf 100644
--- a/arch/sh/drivers/pci/pci-sh7780.h
+++ b/arch/sh/drivers/pci/pci-sh7780.h
@@ -20,9 +20,8 @@
20#define SH7785_DEVICE_ID 0x0007 20#define SH7785_DEVICE_ID 0x0007
21 21
22/* SH7780 Control Registers */ 22/* SH7780 Control Registers */
23#define SH7780_PCI_VCR0 0xFE000000 23#define PCIECR 0xFE000008
24#define SH7780_PCI_VCR1 0xFE000004 24#define PCIECR_ENBL 0x01
25#define SH7780_PCI_VCR2 0xFE000008
26 25
27/* SH7780 Specific Values */ 26/* SH7780 Specific Values */
28#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */ 27#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
@@ -35,7 +34,6 @@
35#define SH7780_PCI_IO_SIZE 0x00400000 /* Size of IO window */ 34#define SH7780_PCI_IO_SIZE 0x00400000 /* Size of IO window */
36 35
37#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */ 36#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
38#define PCI_REG(n) (SH7780_PCIREG_BASE+n)
39 37
40/* SH7780 PCI Config Registers */ 38/* SH7780 PCI Config Registers */
41#define SH7780_PCIVID 0x000 /* Vendor ID */ 39#define SH7780_PCIVID 0x000 /* Vendor ID */
@@ -67,11 +65,6 @@
67#define SH7780_PCIPMCSR_BSE 0x046 65#define SH7780_PCIPMCSR_BSE 0x046
68#define SH7780_PCICDD 0x047 66#define SH7780_PCICDD 0x047
69 67
70#define SH7780_PCICR 0x100 /* PCI Control Register */
71#define SH7780_PCILSR 0x104 /* PCI Local Space Register0 */
72#define SH7780_PCILSR1 0x108 /* PCI Local Space Register1 */
73#define SH7780_PCILAR0 0x10C /* PCI Local Address Register1 */
74#define SH7780_PCILAR1 0x110 /* PCI Local Address Register1 */
75#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */ 68#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
76#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */ 69#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
77#define SH7780_PCIAIR 0x11C /* Error Address Register */ 70#define SH7780_PCIAIR 0x11C /* Error Address Register */
@@ -106,9 +99,4 @@
106 99
107#define SH7780_32BIT_DDR_BASE_ADDR 0x40000000 100#define SH7780_32BIT_DDR_BASE_ADDR 0x40000000
108 101
109struct sh4_pci_address_map;
110
111/* arch/sh/drivers/pci/pci-sh7780.c */
112int sh7780_pcic_init(struct sh4_pci_address_map *map);
113
114#endif /* _PCI_SH7780_H_ */ 102#endif /* _PCI_SH7780_H_ */
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index 0d6ac7a1db49..54d77cbb8b39 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -1,67 +1,156 @@
1/* 1/*
2 * arch/sh/drivers/pci/pci.c 2 * New-style PCI core.
3 * 3 *
4 * Copyright (c) 2002 M. R. Brown <mrbrown@linux-sh.org> 4 * Copyright (c) 2004 - 2009 Paul Mundt
5 * Copyright (c) 2004 - 2006 Paul Mundt <lethal@linux-sh.org> 5 * Copyright (c) 2002 M. R. Brown
6 * 6 *
7 * These functions are collected here to reduce duplication of common 7 * Modelled after arch/mips/pci/pci.c:
8 * code amongst the many platform-specific PCI support code files. 8 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
9 *
10 * These routines require the following board-specific routines:
11 * void pcibios_fixup_irqs();
12 *
13 * See include/asm-sh/pci.h for more information.
14 * 9 *
15 * This file is subject to the terms and conditions of the GNU General Public 10 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive 11 * License. See the file "COPYING" in the main directory of this archive
17 * for more details. 12 * for more details.
18 */ 13 */
19#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/mm.h>
20#include <linux/pci.h> 16#include <linux/pci.h>
21#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/types.h>
22#include <linux/dma-debug.h> 19#include <linux/dma-debug.h>
23#include <asm/io.h> 20#include <linux/io.h>
21#include <linux/mutex.h>
24 22
25static int __init pcibios_init(void) 23unsigned long PCIBIOS_MIN_IO = 0x0000;
24unsigned long PCIBIOS_MIN_MEM = 0;
25
26/*
27 * The PCI controller list.
28 */
29static struct pci_channel *hose_head, **hose_tail = &hose_head;
30
31static int pci_initialized;
32
33static void __devinit pcibios_scanbus(struct pci_channel *hose)
26{ 34{
27 struct pci_channel *p; 35 static int next_busno;
28 struct pci_bus *bus; 36 struct pci_bus *bus;
29 int busno;
30 37
31#ifdef CONFIG_PCI_AUTO 38 bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
32 /* assign resources */ 39 if (bus) {
33 busno = 0; 40 next_busno = bus->subordinate + 1;
34 for (p = board_pci_channels; p->pci_ops != NULL; p++) 41 /* Don't allow 8-bit bus number overflow inside the hose -
35 busno = pciauto_assign_resources(busno, p) + 1; 42 reserve some space for bridges. */
36#endif 43 if (next_busno > 224)
44 next_busno = 0;
45
46 pci_bus_size_bridges(bus);
47 pci_bus_assign_resources(bus);
48 pci_enable_bridges(bus);
49 }
50}
51
52static DEFINE_MUTEX(pci_scan_mutex);
37 53
38 /* scan the buses */ 54void __devinit register_pci_controller(struct pci_channel *hose)
39 busno = 0; 55{
40 for (p = board_pci_channels; p->pci_ops != NULL; p++) { 56 if (request_resource(&iomem_resource, hose->mem_resource) < 0)
41 bus = pci_scan_bus(busno, p->pci_ops, p); 57 goto out;
42 busno = bus->subordinate + 1; 58 if (request_resource(&ioport_resource, hose->io_resource) < 0) {
59 release_resource(hose->mem_resource);
60 goto out;
43 } 61 }
44 62
63 *hose_tail = hose;
64 hose_tail = &hose->next;
65
66 /*
67 * Do not panic here but later - this might hapen before console init.
68 */
69 if (!hose->io_map_base) {
70 printk(KERN_WARNING
71 "registering PCI controller with io_map_base unset\n");
72 }
73
74 /*
75 * Scan the bus if it is register after the PCI subsystem
76 * initialization.
77 */
78 if (pci_initialized) {
79 mutex_lock(&pci_scan_mutex);
80 pcibios_scanbus(hose);
81 mutex_unlock(&pci_scan_mutex);
82 }
83
84 return;
85
86out:
87 printk(KERN_WARNING
88 "Skipping PCI bus scan due to resource conflict\n");
89}
90
91static int __init pcibios_init(void)
92{
93 struct pci_channel *hose;
94
95 /* Scan all of the recorded PCI controllers. */
96 for (hose = hose_head; hose; hose = hose->next)
97 pcibios_scanbus(hose);
98
45 pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq); 99 pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq);
46 100
47 dma_debug_add_bus(&pci_bus_type); 101 dma_debug_add_bus(&pci_bus_type);
48 102
103 pci_initialized = 1;
104
49 return 0; 105 return 0;
50} 106}
51subsys_initcall(pcibios_init); 107subsys_initcall(pcibios_init);
52 108
109static void pcibios_fixup_device_resources(struct pci_dev *dev,
110 struct pci_bus *bus)
111{
112 /* Update device resources. */
113 struct pci_channel *hose = bus->sysdata;
114 unsigned long offset = 0;
115 int i;
116
117 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
118 if (!dev->resource[i].start)
119 continue;
120 if (dev->resource[i].flags & IORESOURCE_PCI_FIXED)
121 continue;
122 if (dev->resource[i].flags & IORESOURCE_IO)
123 offset = hose->io_offset;
124 else if (dev->resource[i].flags & IORESOURCE_MEM)
125 offset = hose->mem_offset;
126
127 dev->resource[i].start += offset;
128 dev->resource[i].end += offset;
129 }
130}
131
53/* 132/*
54 * Called after each bus is probed, but before its children 133 * Called after each bus is probed, but before its children
55 * are examined. 134 * are examined.
56 */ 135 */
57void __devinit __weak pcibios_fixup_bus(struct pci_bus *bus) 136void __devinit pcibios_fixup_bus(struct pci_bus *bus)
58{ 137{
59 pci_read_bridge_bases(bus); 138 struct pci_dev *dev = bus->self;
60} 139 struct list_head *ln;
140 struct pci_channel *chan = bus->sysdata;
61 141
62void pcibios_align_resource(void *data, struct resource *res, 142 if (!dev) {
63 resource_size_t size, resource_size_t align) 143 bus->resource[0] = chan->io_resource;
64 __attribute__ ((weak)); 144 bus->resource[1] = chan->mem_resource;
145 }
146
147 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
148 dev = pci_dev_b(ln);
149
150 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
151 pcibios_fixup_device_resources(dev, bus);
152 }
153}
65 154
66/* 155/*
67 * We need to avoid collisions with `mirrored' VGA ports 156 * We need to avoid collisions with `mirrored' VGA ports
@@ -72,14 +161,58 @@ void pcibios_align_resource(void *data, struct resource *res,
72void pcibios_align_resource(void *data, struct resource *res, 161void pcibios_align_resource(void *data, struct resource *res,
73 resource_size_t size, resource_size_t align) 162 resource_size_t size, resource_size_t align)
74{ 163{
164 struct pci_dev *dev = data;
165 struct pci_channel *chan = dev->sysdata;
166 resource_size_t start = res->start;
167
75 if (res->flags & IORESOURCE_IO) { 168 if (res->flags & IORESOURCE_IO) {
76 resource_size_t start = res->start; 169 if (start < PCIBIOS_MIN_IO + chan->io_resource->start)
170 start = PCIBIOS_MIN_IO + chan->io_resource->start;
77 171
172 /*
173 * Put everything into 0x00-0xff region modulo 0x400.
174 */
78 if (start & 0x300) { 175 if (start & 0x300) {
79 start = (start + 0x3ff) & ~0x3ff; 176 start = (start + 0x3ff) & ~0x3ff;
80 res->start = start; 177 res->start = start;
81 } 178 }
179 } else if (res->flags & IORESOURCE_MEM) {
180 if (start < PCIBIOS_MIN_MEM + chan->mem_resource->start)
181 start = PCIBIOS_MIN_MEM + chan->mem_resource->start;
82 } 182 }
183
184 res->start = start;
185}
186
187void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
188 struct resource *res)
189{
190 struct pci_channel *hose = dev->sysdata;
191 unsigned long offset = 0;
192
193 if (res->flags & IORESOURCE_IO)
194 offset = hose->io_offset;
195 else if (res->flags & IORESOURCE_MEM)
196 offset = hose->mem_offset;
197
198 region->start = res->start - offset;
199 region->end = res->end - offset;
200}
201
202void __devinit
203pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
204 struct pci_bus_region *region)
205{
206 struct pci_channel *hose = dev->sysdata;
207 unsigned long offset = 0;
208
209 if (res->flags & IORESOURCE_IO)
210 offset = hose->io_offset;
211 else if (res->flags & IORESOURCE_MEM)
212 offset = hose->mem_offset;
213
214 res->start = region->start + offset;
215 res->end = region->end + offset;
83} 216}
84 217
85int pcibios_enable_device(struct pci_dev *dev, int mask) 218int pcibios_enable_device(struct pci_dev *dev, int mask)
@@ -90,13 +223,21 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
90 223
91 pci_read_config_word(dev, PCI_COMMAND, &cmd); 224 pci_read_config_word(dev, PCI_COMMAND, &cmd);
92 old_cmd = cmd; 225 old_cmd = cmd;
93 for(idx=0; idx<6; idx++) { 226 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
94 if (!(mask & (1 << idx))) 227 /* Only set up the requested stuff */
228 if (!(mask & (1<<idx)))
95 continue; 229 continue;
230
96 r = &dev->resource[idx]; 231 r = &dev->resource[idx];
232 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
233 continue;
234 if ((idx == PCI_ROM_RESOURCE) &&
235 (!(r->flags & IORESOURCE_ROM_ENABLE)))
236 continue;
97 if (!r->start && r->end) { 237 if (!r->start && r->end) {
98 printk(KERN_ERR "PCI: Device %s not available because " 238 printk(KERN_ERR "PCI: Device %s not available "
99 "of resource collisions\n", pci_name(dev)); 239 "because of resource collisions\n",
240 pci_name(dev));
100 return -EINVAL; 241 return -EINVAL;
101 } 242 }
102 if (r->flags & IORESOURCE_IO) 243 if (r->flags & IORESOURCE_IO)
@@ -104,10 +245,8 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
104 if (r->flags & IORESOURCE_MEM) 245 if (r->flags & IORESOURCE_MEM)
105 cmd |= PCI_COMMAND_MEMORY; 246 cmd |= PCI_COMMAND_MEMORY;
106 } 247 }
107 if (dev->resource[PCI_ROM_RESOURCE].start)
108 cmd |= PCI_COMMAND_MEMORY;
109 if (cmd != old_cmd) { 248 if (cmd != old_cmd) {
110 printk(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n", 249 printk("PCI: Enabling device %s (%04x -> %04x)\n",
111 pci_name(dev), old_cmd, cmd); 250 pci_name(dev), old_cmd, cmd);
112 pci_write_config_word(dev, PCI_COMMAND, cmd); 251 pci_write_config_word(dev, PCI_COMMAND, cmd);
113 } 252 }
@@ -140,6 +279,43 @@ void __init pcibios_update_irq(struct pci_dev *dev, int irq)
140 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 279 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
141} 280}
142 281
282char * __devinit pcibios_setup(char *str)
283{
284 return str;
285}
286
287int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
288 enum pci_mmap_state mmap_state, int write_combine)
289{
290 /*
291 * I/O space can be accessed via normal processor loads and stores on
292 * this platform but for now we elect not to do this and portable
293 * drivers should not do this anyway.
294 */
295 if (mmap_state == pci_mmap_io)
296 return -EINVAL;
297
298 /*
299 * Ignore write-combine; for now only return uncached mappings.
300 */
301 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
302
303 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
304 vma->vm_end - vma->vm_start,
305 vma->vm_page_prot);
306}
307
308static void __iomem *ioport_map_pci(struct pci_dev *dev,
309 unsigned long port, unsigned int nr)
310{
311 struct pci_channel *chan = dev->sysdata;
312
313 if (!chan->io_map_base)
314 chan->io_map_base = generic_io_base;
315
316 return (void __iomem *)(chan->io_map_base + port);
317}
318
143void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) 319void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
144{ 320{
145 resource_size_t start = pci_resource_start(dev, bar); 321 resource_size_t start = pci_resource_start(dev, bar);
@@ -151,20 +327,24 @@ void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
151 if (maxlen && len > maxlen) 327 if (maxlen && len > maxlen)
152 len = maxlen; 328 len = maxlen;
153 329
330 if (flags & IORESOURCE_IO)
331 return ioport_map_pci(dev, start, len);
332
154 /* 333 /*
155 * Presently the IORESOURCE_MEM case is a bit special, most 334 * Presently the IORESOURCE_MEM case is a bit special, most
156 * SH7751 style PCI controllers have PCI memory at a fixed 335 * SH7751 style PCI controllers have PCI memory at a fixed
157 * location in the address space where no remapping is desired 336 * location in the address space where no remapping is desired.
158 * (typically at 0xfd000000, but is_pci_memaddr() will know 337 * With the IORESOURCE_MEM case more care has to be taken
159 * best). With the IORESOURCE_MEM case more care has to be taken
160 * to inhibit page table mapping for legacy cores, but this is 338 * to inhibit page table mapping for legacy cores, but this is
161 * punted off to __ioremap(). 339 * punted off to __ioremap().
162 * -- PFM. 340 * -- PFM.
163 */ 341 */
164 if (flags & IORESOURCE_IO) 342 if (flags & IORESOURCE_MEM) {
165 return ioport_map(start, len); 343 if (flags & IORESOURCE_CACHEABLE)
166 if (flags & IORESOURCE_MEM) 344 return ioremap(start, len);
167 return ioremap(start, len); 345
346 return ioremap_nocache(start, len);
347 }
168 348
169 return NULL; 349 return NULL;
170} 350}
@@ -175,3 +355,10 @@ void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
175 iounmap(addr); 355 iounmap(addr);
176} 356}
177EXPORT_SYMBOL(pci_iounmap); 357EXPORT_SYMBOL(pci_iounmap);
358
359#ifdef CONFIG_HOTPLUG
360EXPORT_SYMBOL(pcibios_resource_to_bus);
361EXPORT_SYMBOL(pcibios_bus_to_resource);
362EXPORT_SYMBOL(PCIBIOS_MIN_IO);
363EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
364#endif
diff --git a/arch/sh/include/asm/device.h b/arch/sh/include/asm/device.h
index efd511d0803a..8688a88303ee 100644
--- a/arch/sh/include/asm/device.h
+++ b/arch/sh/include/asm/device.h
@@ -10,3 +10,5 @@ struct platform_device;
10int platform_resource_setup_memory(struct platform_device *pdev, 10int platform_resource_setup_memory(struct platform_device *pdev,
11 char *name, unsigned long memsize); 11 char *name, unsigned long memsize);
12 12
13void plat_early_device_setup(void);
14
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index df1d383e18a5..5b2e0fcdfc22 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -17,54 +17,29 @@
17 * external) PCI controllers. 17 * external) PCI controllers.
18 */ 18 */
19struct pci_channel { 19struct pci_channel {
20 struct pci_ops *pci_ops; 20 struct pci_channel *next;
21 struct resource *io_resource;
22 struct resource *mem_resource;
23 int first_devfn;
24 int last_devfn;
25};
26 21
27/* 22 struct pci_ops *pci_ops;
28 * Each board initializes this array and terminates it with a NULL entry. 23 struct resource *io_resource;
29 */ 24 struct resource *mem_resource;
30extern struct pci_channel board_pci_channels[];
31 25
32#define PCIBIOS_MIN_IO board_pci_channels->io_resource->start 26 unsigned long io_offset;
33#define PCIBIOS_MIN_MEM board_pci_channels->mem_resource->start 27 unsigned long mem_offset;
34 28
35/* 29 unsigned long reg_base;
36 * I/O routine helpers
37 */
38#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
39#define PCI_IO_AREA 0xFE400000
40#define PCI_IO_SIZE 0x00400000
41#elif defined(CONFIG_CPU_SH5)
42extern unsigned long PCI_IO_AREA;
43#define PCI_IO_SIZE 0x00010000
44#else
45#define PCI_IO_AREA 0xFE240000
46#define PCI_IO_SIZE 0x00040000
47#endif
48 30
49#define PCI_MEM_SIZE 0x01000000 31 unsigned long io_map_base;
32};
50 33
51#define SH4_PCIIOBR_MASK 0xFFFC0000 34extern void register_pci_controller(struct pci_channel *hose);
52#define pci_ioaddr(addr) (PCI_IO_AREA + (addr & ~SH4_PCIIOBR_MASK))
53 35
54#if defined(CONFIG_PCI) 36extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
55#define is_pci_ioaddr(port) \
56 (((port) >= PCIBIOS_MIN_IO) && \
57 ((port) < (PCIBIOS_MIN_IO + PCI_IO_SIZE)))
58#define is_pci_memaddr(port) \
59 (((port) >= PCIBIOS_MIN_MEM) && \
60 ((port) < (PCIBIOS_MIN_MEM + PCI_MEM_SIZE)))
61#else
62#define is_pci_ioaddr(port) (0)
63#define is_pci_memaddr(port) (0)
64#endif
65 37
66struct pci_dev; 38struct pci_dev;
67 39
40#define HAVE_PCI_MMAP
41extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
42 enum pci_mmap_state mmap_state, int write_combine);
68extern void pcibios_set_master(struct pci_dev *dev); 43extern void pcibios_set_master(struct pci_dev *dev);
69 44
70static inline void pcibios_penalize_isa_irq(int irq, int active) 45static inline void pcibios_penalize_isa_irq(int irq, int active)
@@ -123,22 +98,51 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
123} 98}
124#endif 99#endif
125 100
101#ifdef CONFIG_SUPERH32
102/*
103 * If we're on an SH7751 or SH7780 PCI controller, PCI memory is mapped
104 * at the end of the address space in a special non-translatable area.
105 */
106#define PCI_MEM_FIXED_START 0xfd000000
107#define PCI_MEM_FIXED_END (PCI_MEM_FIXED_START + 0x01000000)
108
109#define is_pci_memory_fixed_range(s, e) \
110 ((s) >= PCI_MEM_FIXED_START && (e) < PCI_MEM_FIXED_END)
111#else
112#define is_pci_memory_fixed_range(s, e) (0)
113#endif
114
126/* Board-specific fixup routines. */ 115/* Board-specific fixup routines. */
127void pcibios_fixup(void);
128int pcibios_init_platform(void);
129int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin); 116int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
130 117
131#ifdef CONFIG_PCI_AUTO 118extern void pcibios_resource_to_bus(struct pci_dev *dev,
132int pciauto_assign_resources(int busno, struct pci_channel *hose); 119 struct pci_bus_region *region, struct resource *res);
133#endif
134 120
135#endif /* __KERNEL__ */ 121extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
122 struct pci_bus_region *region);
123
124static inline struct resource *
125pcibios_select_root(struct pci_dev *pdev, struct resource *res)
126{
127 struct resource *root = NULL;
136 128
137/* generic pci stuff */ 129 if (res->flags & IORESOURCE_IO)
138#include <asm-generic/pci.h> 130 root = &ioport_resource;
131 if (res->flags & IORESOURCE_MEM)
132 root = &iomem_resource;
133
134 return root;
135}
136
137/* Chances are this interrupt is wired PC-style ... */
138static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
139{
140 return channel ? 15 : 14;
141}
139 142
140/* generic DMA-mapping stuff */ 143/* generic DMA-mapping stuff */
141#include <asm-generic/pci-dma-compat.h> 144#include <asm-generic/pci-dma-compat.h>
142 145
146#endif /* __KERNEL__ */
143#endif /* __ASM_SH_PCI_H */ 147#endif /* __ASM_SH_PCI_H */
144 148
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 1fd58b421438..005c962c8b1c 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -32,7 +32,7 @@ enum cpu_type {
32 32
33 /* SH-4A types */ 33 /* SH-4A types */
34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, 34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
35 CPU_SH7723, CPU_SHX3, 35 CPU_SH7723, CPU_SH7724, CPU_SHX3,
36 36
37 /* SH4AL-DSP types */ 37 /* SH4AL-DSP types */
38 CPU_SH7343, CPU_SH7722, CPU_SH7366, 38 CPU_SH7343, CPU_SH7722, CPU_SH7366,
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
index 749d1c434337..ccf1d999db6d 100644
--- a/arch/sh/include/cpu-sh4/cpu/freq.h
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -25,6 +25,24 @@
25#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 25#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
26 defined(CONFIG_CPU_SUBTYPE_SH7780) 26 defined(CONFIG_CPU_SUBTYPE_SH7780)
27#define FRQCR 0xffc80000 27#define FRQCR 0xffc80000
28#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
29#define FRQCRA 0xa4150000
30#define FRQCRB 0xa4150004
31#define VCLKCR 0xa4150048
32
33#define FCLKACR 0xa4150008
34#define FCLKBCR 0xa415000c
35#define FRQCR FRQCRA
36#define SCLKACR FCLKACR
37#define SCLKBCR FCLKBCR
38#define FCLKACR 0xa4150008
39#define FCLKBCR 0xa415000c
40#define IrDACLKCR 0xa4150018
41
42#define MSTPCR0 0xa4150030
43#define MSTPCR1 0xa4150034
44#define MSTPCR2 0xa4150038
45
28#elif defined(CONFIG_CPU_SUBTYPE_SH7785) 46#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
29#define FRQCR0 0xffc80000 47#define FRQCR0 0xffc80000
30#define FRQCR1 0xffc80004 48#define FRQCR1 0xffc80004
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7724.h b/arch/sh/include/cpu-sh4/cpu/sh7724.h
new file mode 100644
index 000000000000..34605c9e354d
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sh7724.h
@@ -0,0 +1,255 @@
1#ifndef __ASM_SH7724_H__
2#define __ASM_SH7724_H__
3
4enum {
5 /* PTA */
6 GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
7 GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0,
8
9 /* PTB */
10 GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4,
11 GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0,
12
13 /* PTC */
14 GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4,
15 GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0,
16
17 /* PTD */
18 GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4,
19 GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0,
20
21 /* PTE */
22 GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4,
23 GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0,
24
25 /* PTF */
26 GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4,
27 GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0,
28
29 /* PTG */
30 GPIO_PTG5, GPIO_PTG4,
31 GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0,
32
33 /* PTH */
34 GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4,
35 GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0,
36
37 /* PTJ */
38 GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5,
39 GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0,
40
41 /* PTK */
42 GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4,
43 GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0,
44
45 /* PTL */
46 GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4,
47 GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0,
48
49 /* PTM */
50 GPIO_PTM7, GPIO_PTM6, GPIO_PTM5, GPIO_PTM4,
51 GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0,
52
53 /* PTN */
54 GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4,
55 GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,
56
57 /* PTQ */
58 GPIO_PTQ7, GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,
59 GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,
60
61 /* PTR */
62 GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4,
63 GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0,
64
65 /* PTS */
66 GPIO_PTS6, GPIO_PTS5, GPIO_PTS4,
67 GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0,
68
69 /* PTT */
70 GPIO_PTT7, GPIO_PTT6, GPIO_PTT5, GPIO_PTT4,
71 GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0,
72
73 /* PTU */
74 GPIO_PTU7, GPIO_PTU6, GPIO_PTU5, GPIO_PTU4,
75 GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0,
76
77 /* PTV */
78 GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4,
79 GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0,
80
81 /* PTW */
82 GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4,
83 GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0,
84
85 /* PTX */
86 GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4,
87 GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0,
88
89 /* PTY */
90 GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4,
91 GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0,
92
93 /* PTZ */
94 GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4,
95 GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0,
96
97 /* BSC (PTA/PTB/PTJ/PTQ/PTR/PTT) */
98 GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28,
99 GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24,
100 GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20,
101 GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16,
102 GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
103 GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
104 GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
105 GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
106 GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22,
107 GPIO_FN_CS6B_CE1B, GPIO_FN_CS6A_CE2B,
108 GPIO_FN_CS5B_CE1A, GPIO_FN_CS5A_CE2A,
109 GPIO_FN_WE3_ICIOWR, GPIO_FN_WE2_ICIORD,
110 GPIO_FN_IOIS16, GPIO_FN_WAIT,
111 GPIO_FN_BS,
112
113 /* KEYSC (PTA/PTB)*/
114 GPIO_FN_KEYOUT5_IN5, GPIO_FN_KEYOUT4_IN6, GPIO_FN_KEYIN4,
115 GPIO_FN_KEYIN3, GPIO_FN_KEYIN2, GPIO_FN_KEYIN1, GPIO_FN_KEYIN0,
116 GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT2, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT0,
117
118 /* ATAPI (PTA/PTB/PTK/PTR/PTS/PTW) */
119 GPIO_FN_IDED15, GPIO_FN_IDED14, GPIO_FN_IDED13, GPIO_FN_IDED12,
120 GPIO_FN_IDED11, GPIO_FN_IDED10, GPIO_FN_IDED9, GPIO_FN_IDED8,
121 GPIO_FN_IDED7, GPIO_FN_IDED6, GPIO_FN_IDED5, GPIO_FN_IDED4,
122 GPIO_FN_IDED3, GPIO_FN_IDED2, GPIO_FN_IDED1, GPIO_FN_IDED0,
123 GPIO_FN_IDEA2, GPIO_FN_IDEA1, GPIO_FN_IDEA0, GPIO_FN_IDEIOWR,
124 GPIO_FN_IODREQ, GPIO_FN_IDECS0, GPIO_FN_IDECS1, GPIO_FN_IDEIORD,
125 GPIO_FN_DIRECTION, GPIO_FN_EXBUF_ENB, GPIO_FN_IDERST, GPIO_FN_IODACK,
126 GPIO_FN_IDEINT, GPIO_FN_IDEIORDY,
127
128 /* TPU (PTB/PTR/PTS) */
129 GPIO_FN_TPUTO3, GPIO_FN_TPUTO2, GPIO_FN_TPUTO1, GPIO_FN_TPUTO0,
130 GPIO_FN_TPUTI3, GPIO_FN_TPUTI2,
131
132 /* LCDC (PTC/PTD/PTE/PTF/PTM/PTR) */
133 GPIO_FN_LCDD23, GPIO_FN_LCDD22, GPIO_FN_LCDD21, GPIO_FN_LCDD20,
134 GPIO_FN_LCDD19, GPIO_FN_LCDD18, GPIO_FN_LCDD17, GPIO_FN_LCDD16,
135 GPIO_FN_LCDD15, GPIO_FN_LCDD14, GPIO_FN_LCDD13, GPIO_FN_LCDD12,
136 GPIO_FN_LCDD11, GPIO_FN_LCDD10, GPIO_FN_LCDD9, GPIO_FN_LCDD8,
137 GPIO_FN_LCDD7, GPIO_FN_LCDD6, GPIO_FN_LCDD5, GPIO_FN_LCDD4,
138 GPIO_FN_LCDD3, GPIO_FN_LCDD2, GPIO_FN_LCDD1, GPIO_FN_LCDD0,
139 GPIO_FN_LCDVSYN, GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_LCDHSYN,
140 GPIO_FN_LCDCS, GPIO_FN_LCDDON, GPIO_FN_LCDDCK, GPIO_FN_LCDWR,
141 GPIO_FN_LCDVEPWC, GPIO_FN_LCDVCPWC, GPIO_FN_LCDRD, GPIO_FN_LCDLCLK,
142
143 /* SCIF0 (PTF/PTM) */
144 GPIO_FN_SCIF0_TXD, GPIO_FN_SCIF0_RXD, GPIO_FN_SCIF0_SCK,
145
146 /* SCIF1 (PTL) */
147 GPIO_FN_SCIF1_SCK, GPIO_FN_SCIF1_RXD, GPIO_FN_SCIF1_TXD,
148
149 /* SCIF2 (PTE/PTF/PTN) with LCDC, VOU */
150 GPIO_FN_SCIF2_L_TXD, GPIO_FN_SCIF2_L_SCK, GPIO_FN_SCIF2_L_RXD,
151 GPIO_FN_SCIF2_V_TXD, GPIO_FN_SCIF2_V_SCK, GPIO_FN_SCIF2_V_RXD,
152
153 /* SCIF3 (PTL/PTN/PTZ) with VOU, IRQ */
154 GPIO_FN_SCIF3_V_SCK, GPIO_FN_SCIF3_V_RXD, GPIO_FN_SCIF3_V_TXD,
155 GPIO_FN_SCIF3_V_CTS, GPIO_FN_SCIF3_V_RTS,
156 GPIO_FN_SCIF3_I_SCK, GPIO_FN_SCIF3_I_RXD, GPIO_FN_SCIF3_I_TXD,
157 GPIO_FN_SCIF3_I_CTS, GPIO_FN_SCIF3_I_RTS,
158
159 /* SCIF4 (PTE) */
160 GPIO_FN_SCIF4_SCK, GPIO_FN_SCIF4_RXD, GPIO_FN_SCIF4_TXD,
161
162 /* SCIF5 (PTS) */
163 GPIO_FN_SCIF5_SCK, GPIO_FN_SCIF5_RXD, GPIO_FN_SCIF5_TXD,
164
165 /* FSI (PTE/PTU/PTV) */
166 GPIO_FN_FSIMCKB, GPIO_FN_FSIMCKA, GPIO_FN_FSIOASD,
167 GPIO_FN_FSIIABCK, GPIO_FN_FSIIALRCK, GPIO_FN_FSIOABCK,
168 GPIO_FN_FSIOALRCK, GPIO_FN_CLKAUDIOAO, GPIO_FN_FSIIBSD,
169 GPIO_FN_FSIOBSD, GPIO_FN_FSIIBBCK, GPIO_FN_FSIIBLRCK,
170 GPIO_FN_FSIOBBCK, GPIO_FN_FSIOBLRCK, GPIO_FN_CLKAUDIOBO,
171 GPIO_FN_FSIIASD,
172
173 /* AUD (PTG) */
174 GPIO_FN_AUDCK, GPIO_FN_AUDSYNC, GPIO_FN_AUDATA3,
175 GPIO_FN_AUDATA2, GPIO_FN_AUDATA1, GPIO_FN_AUDATA0,
176
177 /* VIO (PTS) (common?) */
178 GPIO_FN_VIO_CKO,
179
180 /* VIO0 (PTH/PTK) */
181 GPIO_FN_VIO0_D15, GPIO_FN_VIO0_D14, GPIO_FN_VIO0_D13, GPIO_FN_VIO0_D12,
182 GPIO_FN_VIO0_D11, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D8,
183 GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D5, GPIO_FN_VIO0_D4,
184 GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D2, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D0,
185 GPIO_FN_VIO0_VD, GPIO_FN_VIO0_CLK,
186 GPIO_FN_VIO0_FLD, GPIO_FN_VIO0_HD,
187
188 /* VIO1 (PTK/PTS) */
189 GPIO_FN_VIO1_D7, GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D5, GPIO_FN_VIO1_D4,
190 GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D2, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D0,
191 GPIO_FN_VIO1_FLD, GPIO_FN_VIO1_HD, GPIO_FN_VIO1_VD, GPIO_FN_VIO1_CLK,
192
193 /* Eth (PTL/PTN/PTX) */
194 GPIO_FN_RMII_RXD0, GPIO_FN_RMII_RXD1,
195 GPIO_FN_RMII_TXD0, GPIO_FN_RMII_TXD1,
196 GPIO_FN_RMII_REF_CLK, GPIO_FN_RMII_TX_EN,
197 GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_CRS_DV,
198 GPIO_FN_LNKSTA, GPIO_FN_MDIO,
199 GPIO_FN_MDC,
200
201 /* System (PTJ) */
202 GPIO_FN_PDSTATUS, GPIO_FN_STATUS2, GPIO_FN_STATUS0,
203
204 /* VOU (PTL/PTM/PTN*/
205 GPIO_FN_DV_D15, GPIO_FN_DV_D14, GPIO_FN_DV_D13, GPIO_FN_DV_D12,
206 GPIO_FN_DV_D11, GPIO_FN_DV_D10, GPIO_FN_DV_D9, GPIO_FN_DV_D8,
207 GPIO_FN_DV_D7, GPIO_FN_DV_D6, GPIO_FN_DV_D5, GPIO_FN_DV_D4,
208 GPIO_FN_DV_D3, GPIO_FN_DV_D2, GPIO_FN_DV_D1, GPIO_FN_DV_D0,
209 GPIO_FN_DV_CLKI, GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC,
210
211 /* MSIOF0 (PTL/PTM) */
212 GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
213 GPIO_FN_MSIOF0_MCK, GPIO_FN_MSIOF0_TSCK,
214 GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
215 GPIO_FN_MSIOF0_TSYNC, GPIO_FN_MSIOF0_RSCK,
216 GPIO_FN_MSIOF0_RSYNC,
217
218 /* MSIOF1 (PTV) */
219 GPIO_FN_MSIOF1_RXD, GPIO_FN_MSIOF1_TXD,
220 GPIO_FN_MSIOF1_MCK, GPIO_FN_MSIOF1_TSCK,
221 GPIO_FN_MSIOF1_SS1, GPIO_FN_MSIOF1_SS2,
222 GPIO_FN_MSIOF1_TSYNC, GPIO_FN_MSIOF1_RSCK,
223 GPIO_FN_MSIOF1_RSYNC,
224
225 /* DMAC (PTU/PTX) */
226 GPIO_FN_DMAC_DACK0, GPIO_FN_DMAC_DREQ0,
227 GPIO_FN_DMAC_DACK1, GPIO_FN_DMAC_DREQ1,
228
229 /* SDHI0 (PTY) */
230 GPIO_FN_SDHI0CD, GPIO_FN_SDHI0WP, GPIO_FN_SDHI0CMD, GPIO_FN_SDHI0CLK,
231 GPIO_FN_SDHI0D3, GPIO_FN_SDHI0D2, GPIO_FN_SDHI0D1, GPIO_FN_SDHI0D0,
232
233 /* SDHI1 (PTW) */
234 GPIO_FN_SDHI1CD, GPIO_FN_SDHI1WP, GPIO_FN_SDHI1CMD, GPIO_FN_SDHI1CLK,
235 GPIO_FN_SDHI1D3, GPIO_FN_SDHI1D2, GPIO_FN_SDHI1D1, GPIO_FN_SDHI1D0,
236
237 /* MMC (PTW/PTX)*/
238 GPIO_FN_MMC_D7, GPIO_FN_MMC_D6, GPIO_FN_MMC_D5, GPIO_FN_MMC_D4,
239 GPIO_FN_MMC_D3, GPIO_FN_MMC_D2, GPIO_FN_MMC_D1, GPIO_FN_MMC_D0,
240 GPIO_FN_MMC_CLK, GPIO_FN_MMC_CMD,
241
242 /* IrDA (PTX) */
243 GPIO_FN_IRDA_OUT, GPIO_FN_IRDA_IN,
244
245 /* TSIF (PTX) */
246 GPIO_FN_TSIF_TS0_SDAT, GPIO_FN_TSIF_TS0_SCK,
247 GPIO_FN_TSIF_TS0_SDEN, GPIO_FN_TSIF_TS0_SPSYNC,
248
249 /* IRQ (PTZ) */
250 GPIO_FN_INTC_IRQ7, GPIO_FN_INTC_IRQ6, GPIO_FN_INTC_IRQ5,
251 GPIO_FN_INTC_IRQ4, GPIO_FN_INTC_IRQ3, GPIO_FN_INTC_IRQ2,
252 GPIO_FN_INTC_IRQ1, GPIO_FN_INTC_IRQ0,
253};
254
255#endif /* __ASM_SH7724_H__ */
diff --git a/arch/sh/include/mach-dreamcast/mach/pci.h b/arch/sh/include/mach-dreamcast/mach/pci.h
index 75fc9009e092..0314d975e626 100644
--- a/arch/sh/include/mach-dreamcast/mach/pci.h
+++ b/arch/sh/include/mach-dreamcast/mach/pci.h
@@ -21,5 +21,7 @@
21 21
22#define GAPSPCI_IRQ HW_EVENT_EXTERNAL 22#define GAPSPCI_IRQ HW_EVENT_EXTERNAL
23 23
24extern struct pci_ops gapspci_pci_ops;
25
24#endif /* __ASM_SH_DREAMCAST_PCI_H */ 26#endif /* __ASM_SH_DREAMCAST_PCI_H */
25 27
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 91e3677ae09d..973ff831c8a8 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -156,6 +156,12 @@ int __init detect_cpu_and_cache_system(void)
156 break; 156 break;
157 } 157 }
158 break; 158 break;
159 case 0x300b:
160 boot_cpu_data.type = CPU_SH7724;
161 boot_cpu_data.icache.ways = 4;
162 boot_cpu_data.dcache.ways = 4;
163 boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_FPU;
164 break;
159 case 0x4000: /* 1st cut */ 165 case 0x4000: /* 1st cut */
160 case 0x4001: /* 2nd cut */ 166 case 0x4001: /* 2nd cut */
161 boot_cpu_data.type = CPU_SHX3; 167 boot_cpu_data.type = CPU_SHX3;
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 1a92361feeb9..afd6fba47849 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o 15obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o
15obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o 16obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o
16 17
@@ -26,12 +27,14 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
26clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o 27clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o
27clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o 28clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
28clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o 29clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o
30clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7722.o
29clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o 31clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o
30clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o 32clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
31 33
32# Pinmux setup 34# Pinmux setup
33pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o 35pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o
34pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o 36pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o
37pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o
35pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o 38pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
36pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o 39pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
37 40
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 0e174af21874..1ccdfc561fef 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -130,6 +130,12 @@ static void adjust_clocks(int originate, int *l, unsigned long v[],
130 * is quite simple.. 130 * is quite simple..
131 */ 131 */
132 132
133#if defined(CONFIG_CPU_SUBTYPE_SH7724)
134#define STCPLL(frqcr) ((((frqcr >> 24) & 0x3f) + 1) * 2)
135#else
136#define STCPLL(frqcr) (((frqcr >> 24) & 0x1f) + 1)
137#endif
138
133/* 139/*
134 * Instead of having two separate multipliers/divisors set, like this: 140 * Instead of having two separate multipliers/divisors set, like this:
135 * 141 *
@@ -139,13 +145,17 @@ static void adjust_clocks(int originate, int *l, unsigned long v[],
139 * I created the divisors2 array, which is used to calculate rate like 145 * I created the divisors2 array, which is used to calculate rate like
140 * rate = parent * 2 / divisors2[ divisor ]; 146 * rate = parent * 2 / divisors2[ divisor ];
141*/ 147*/
148#if defined(CONFIG_CPU_SUBTYPE_SH7724)
149static int divisors2[] = { 4, 1, 8, 12, 16, 24, 32, 1, 48, 64, 72, 96, 1, 144 };
150#else
142static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 }; 151static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
152#endif
143 153
144static void master_clk_recalc(struct clk *clk) 154static void master_clk_recalc(struct clk *clk)
145{ 155{
146 unsigned frqcr = ctrl_inl(FRQCR); 156 unsigned frqcr = ctrl_inl(FRQCR);
147 157
148 clk->rate = CONFIG_SH_PCLK_FREQ * (((frqcr >> 24) & 0x1f) + 1); 158 clk->rate = CONFIG_SH_PCLK_FREQ * STCPLL(frqcr);
149} 159}
150 160
151static void master_clk_init(struct clk *clk) 161static void master_clk_init(struct clk *clk)
@@ -161,13 +171,30 @@ static void module_clk_recalc(struct clk *clk)
161{ 171{
162 unsigned long frqcr = ctrl_inl(FRQCR); 172 unsigned long frqcr = ctrl_inl(FRQCR);
163 173
164 clk->rate = clk->parent->rate / (((frqcr >> 24) & 0x1f) + 1); 174 clk->rate = clk->parent->rate / STCPLL(frqcr);
165} 175}
166 176
177#if defined(CONFIG_CPU_SUBTYPE_SH7724)
178#define MASTERDIVS { 12, 16, 24, 30, 32, 36, 48 }
179#define STCMASK 0x3f
180#define DIVCALC(div) (div/2-1)
181#define FRQCRKICK 0x80000000
182#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
183#define MASTERDIVS { 6, 8, 12, 16 }
184#define STCMASK 0x1f
185#define DIVCALC(div) (div-1)
186#define FRQCRKICK 0x00000000
187#else
188#define MASTERDIVS { 2, 3, 4, 6, 8, 16 }
189#define STCMASK 0x1f
190#define DIVCALC(div) (div-1)
191#define FRQCRKICK 0x00000000
192#endif
193
167static int master_clk_setrate(struct clk *clk, unsigned long rate, int id) 194static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
168{ 195{
169 int div = rate / clk->rate; 196 int div = rate / clk->rate;
170 int master_divs[] = { 2, 3, 4, 6, 8, 16 }; 197 int master_divs[] = MASTERDIVS;
171 int index; 198 int index;
172 unsigned long frqcr; 199 unsigned long frqcr;
173 200
@@ -180,8 +207,9 @@ static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
180 div = master_divs[index - 1]; 207 div = master_divs[index - 1];
181 208
182 frqcr = ctrl_inl(FRQCR); 209 frqcr = ctrl_inl(FRQCR);
183 frqcr &= ~(0xF << 24); 210 frqcr &= ~(STCMASK << 24);
184 frqcr |= ( (div-1) << 24); 211 frqcr |= (DIVCALC(div) << 24);
212 frqcr |= FRQCRKICK;
185 ctrl_outl(frqcr, FRQCR); 213 ctrl_outl(frqcr, FRQCR);
186 214
187 return 0; 215 return 0;
@@ -377,6 +405,7 @@ static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate,
377 /* clear FRQCR bits */ 405 /* clear FRQCR bits */
378 frqcr &= ~(ctx.mask << ctx.shift); 406 frqcr &= ~(ctx.mask << ctx.shift);
379 frqcr |= div << ctx.shift; 407 frqcr |= div << ctx.shift;
408 frqcr |= FRQCRKICK;
380 409
381 /* ...and perform actual change */ 410 /* ...and perform actual change */
382 ctrl_outl(frqcr, FRQCR); 411 ctrl_outl(frqcr, FRQCR);
@@ -542,8 +571,8 @@ static struct clk sh7722_r_clock = {
542 .flags = CLK_RATE_PROPAGATES, 571 .flags = CLK_RATE_PROPAGATES,
543}; 572};
544 573
545#ifndef CONFIG_CPU_SUBTYPE_SH7343 574#if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\
546 575 !defined(CONFIG_CPU_SUBTYPE_SH7724)
547/* 576/*
548 * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops 577 * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops
549 * methods of clk_ops determine which register they should access by 578 * methods of clk_ops determine which register they should access by
@@ -560,15 +589,16 @@ static struct clk sh7722_siu_b_clock = {
560 .arch_flags = SCLKBCR, 589 .arch_flags = SCLKBCR,
561 .ops = &sh7722_siu_clk_ops, 590 .ops = &sh7722_siu_clk_ops,
562}; 591};
592#endif /* CONFIG_CPU_SUBTYPE_SH7343, SH7724 */
563 593
564#if defined(CONFIG_CPU_SUBTYPE_SH7722) 594#if defined(CONFIG_CPU_SUBTYPE_SH7722) ||\
595 defined(CONFIG_CPU_SUBTYPE_SH7724)
565static struct clk sh7722_irda_clock = { 596static struct clk sh7722_irda_clock = {
566 .name = "irda_clk", 597 .name = "irda_clk",
567 .arch_flags = IrDACLKCR, 598 .arch_flags = IrDACLKCR,
568 .ops = &sh7722_siu_clk_ops, 599 .ops = &sh7722_siu_clk_ops,
569}; 600};
570#endif 601#endif
571#endif /* CONFIG_CPU_SUBTYPE_SH7343 */
572 602
573static struct clk sh7722_video_clock = { 603static struct clk sh7722_video_clock = {
574 .name = "video_clk", 604 .name = "video_clk",
@@ -715,6 +745,61 @@ static struct clk sh7722_mstpcr_clocks[] = {
715 MSTPCR("vpu0", "bus_clk", 2, 1), 745 MSTPCR("vpu0", "bus_clk", 2, 1),
716 MSTPCR("lcdc0", "bus_clk", 2, 0), 746 MSTPCR("lcdc0", "bus_clk", 2, 0),
717#endif 747#endif
748#if defined(CONFIG_CPU_SUBTYPE_SH7724)
749 /* See Datasheet : Overview -> Block Diagram */
750 MSTPCR("tlb0", "cpu_clk", 0, 31),
751 MSTPCR("ic0", "cpu_clk", 0, 30),
752 MSTPCR("oc0", "cpu_clk", 0, 29),
753 MSTPCR("rs0", "bus_clk", 0, 28),
754 MSTPCR("ilmem0", "cpu_clk", 0, 27),
755 MSTPCR("l2c0", "sh_clk", 0, 26),
756 MSTPCR("fpu0", "cpu_clk", 0, 24),
757 MSTPCR("intc0", "peripheral_clk", 0, 22),
758 MSTPCR("dmac0", "bus_clk", 0, 21),
759 MSTPCR("sh0", "sh_clk", 0, 20),
760 MSTPCR("hudi0", "peripheral_clk", 0, 19),
761 MSTPCR("ubc0", "cpu_clk", 0, 17),
762 MSTPCR("tmu0", "peripheral_clk", 0, 15),
763 MSTPCR("cmt0", "r_clk", 0, 14),
764 MSTPCR("rwdt0", "r_clk", 0, 13),
765 MSTPCR("dmac1", "bus_clk", 0, 12),
766 MSTPCR("tmu1", "peripheral_clk", 0, 10),
767 MSTPCR("scif0", "peripheral_clk", 0, 9),
768 MSTPCR("scif1", "peripheral_clk", 0, 8),
769 MSTPCR("scif2", "peripheral_clk", 0, 7),
770 MSTPCR("scif3", "bus_clk", 0, 6),
771 MSTPCR("scif4", "bus_clk", 0, 5),
772 MSTPCR("scif5", "bus_clk", 0, 4),
773 MSTPCR("msiof0", "bus_clk", 0, 2),
774 MSTPCR("msiof1", "bus_clk", 0, 1),
775 MSTPCR("keysc0", "r_clk", 1, 12),
776 MSTPCR("rtc0", "r_clk", 1, 11),
777 MSTPCR("i2c0", "peripheral_clk", 1, 9),
778 MSTPCR("i2c1", "peripheral_clk", 1, 8),
779 MSTPCR("mmc0", "bus_clk", 2, 29),
780 MSTPCR("eth0", "bus_clk", 2, 28),
781 MSTPCR("atapi0", "bus_clk", 2, 26),
782 MSTPCR("tpu0", "bus_clk", 2, 25),
783 MSTPCR("irda0", "peripheral_clk", 2, 24),
784 MSTPCR("tsif0", "bus_clk", 2, 22),
785 MSTPCR("usb1", "bus_clk", 2, 21),
786 MSTPCR("usb0", "bus_clk", 2, 20),
787 MSTPCR("2dg0", "bus_clk", 2, 19),
788 MSTPCR("sdhi0", "bus_clk", 2, 18),
789 MSTPCR("sdhi1", "bus_clk", 2, 17),
790 MSTPCR("veu1", "bus_clk", 2, 15),
791 MSTPCR("ceu1", "bus_clk", 2, 13),
792 MSTPCR("beu1", "bus_clk", 2, 12),
793 MSTPCR("2ddmac0", "sh_clk", 2, 10),
794 MSTPCR("spu0", "bus_clk", 2, 9),
795 MSTPCR("jpu0", "bus_clk", 2, 6),
796 MSTPCR("vou0", "bus_clk", 2, 5),
797 MSTPCR("beu0", "bus_clk", 2, 4),
798 MSTPCR("ceu0", "bus_clk", 2, 3),
799 MSTPCR("veu0", "bus_clk", 2, 2),
800 MSTPCR("vpu0", "bus_clk", 2, 1),
801 MSTPCR("lcdc0", "bus_clk", 2, 0),
802#endif
718#if defined(CONFIG_CPU_SUBTYPE_SH7343) 803#if defined(CONFIG_CPU_SUBTYPE_SH7343)
719 MSTPCR("uram0", "umem_clk", 0, 28), 804 MSTPCR("uram0", "umem_clk", 0, 28),
720 MSTPCR("xymem0", "bus_clk", 0, 26), 805 MSTPCR("xymem0", "bus_clk", 0, 26),
@@ -786,12 +871,15 @@ static struct clk *sh7722_clocks[] = {
786 &sh7722_sh_clock, 871 &sh7722_sh_clock,
787 &sh7722_peripheral_clock, 872 &sh7722_peripheral_clock,
788 &sh7722_sdram_clock, 873 &sh7722_sdram_clock,
789#ifndef CONFIG_CPU_SUBTYPE_SH7343 874#if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\
875 !defined(CONFIG_CPU_SUBTYPE_SH7724)
790 &sh7722_siu_a_clock, 876 &sh7722_siu_a_clock,
791 &sh7722_siu_b_clock, 877 &sh7722_siu_b_clock,
792#if defined(CONFIG_CPU_SUBTYPE_SH7722)
793 &sh7722_irda_clock,
794#endif 878#endif
879/* 7724 should support FSI clock */
880#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
881 defined(CONFIG_CPU_SUBTYPE_SH7724)
882 &sh7722_irda_clock,
795#endif 883#endif
796 &sh7722_video_clock, 884 &sh7722_video_clock,
797}; 885};
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
new file mode 100644
index 000000000000..1af0f9586379
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
@@ -0,0 +1,2230 @@
1/*
2 * SH7724 Pinmux
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 *
8 * Based on SH7723 Pinmux
9 * Copyright (C) 2008 Magnus Damm
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/gpio.h>
19#include <cpu/sh7724.h>
20
21enum {
22 PINMUX_RESERVED = 0,
23
24 PINMUX_DATA_BEGIN,
25 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
26 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
27 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
28 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
29 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
30 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
31 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
32 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
33 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
34 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
35 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
36 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
37 PTG5_DATA, PTG4_DATA,
38 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
39 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
40 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
41 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA,
42 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
43 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
44 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
45 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
46 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
47 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
48 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
49 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
50 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
51 PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
52 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
53 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
54 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
55 PTS6_DATA, PTS5_DATA, PTS4_DATA,
56 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
57 PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
58 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
59 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
60 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
61 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
62 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
63 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
64 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
65 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
66 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
67 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
68 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
69 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
70 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
71 PINMUX_DATA_END,
72
73 PINMUX_INPUT_BEGIN,
74 PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
75 PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
76 PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
77 PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
78 PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
79 PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
80 PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
81 PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
82 PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN,
83 PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
84 PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN,
85 PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
86 PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN,
87 PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
88 PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
89 PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
90 PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
91 PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN,
92 PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
93 PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
94 PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
95 PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN,
96 PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
97 PTQ7_IN, PTQ6_IN, PTQ5_IN, PTQ4_IN,
98 PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
99 PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
100 PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
101 PTS6_IN, PTS5_IN, PTS4_IN,
102 PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
103 PTT7_IN, PTT6_IN, PTT5_IN, PTT4_IN,
104 PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
105 PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN,
106 PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
107 PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN,
108 PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
109 PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN,
110 PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
111 PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN,
112 PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
113 PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN,
114 PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN,
115 PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN,
116 PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN,
117 PINMUX_INPUT_END,
118
119 PINMUX_INPUT_PULLUP_BEGIN,
120 PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU,
121 PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU,
122 PTB7_IN_PU, PTB6_IN_PU, PTB5_IN_PU, PTB4_IN_PU,
123 PTB3_IN_PU, PTB2_IN_PU, PTB1_IN_PU, PTB0_IN_PU,
124 PTC7_IN_PU, PTC6_IN_PU, PTC5_IN_PU, PTC4_IN_PU,
125 PTC3_IN_PU, PTC2_IN_PU, PTC1_IN_PU, PTC0_IN_PU,
126 PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
127 PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU,
128 PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU,
129 PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU,
130 PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU,
131 PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU,
132 PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU,
133 PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU,
134 PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU,
135 PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU,
136 PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU,
137 PTL7_IN_PU, PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU,
138 PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU,
139 PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU,
140 PTM3_IN_PU, PTM2_IN_PU, PTM1_IN_PU, PTM0_IN_PU,
141 PTN7_IN_PU, PTN6_IN_PU, PTN5_IN_PU, PTN4_IN_PU,
142 PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU,
143 PTQ7_IN_PU, PTQ6_IN_PU, PTQ5_IN_PU, PTQ4_IN_PU,
144 PTQ3_IN_PU, PTQ2_IN_PU, PTQ1_IN_PU, PTQ0_IN_PU,
145 PTR7_IN_PU, PTR6_IN_PU, PTR5_IN_PU, PTR4_IN_PU,
146 PTR3_IN_PU, PTR2_IN_PU, PTR1_IN_PU, PTR0_IN_PU,
147 PTS6_IN_PU, PTS5_IN_PU, PTS4_IN_PU,
148 PTS3_IN_PU, PTS2_IN_PU, PTS1_IN_PU, PTS0_IN_PU,
149 PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU,
150 PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU,
151 PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU,
152 PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU,
153 PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU,
154 PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU,
155 PTW7_IN_PU, PTW6_IN_PU, PTW5_IN_PU, PTW4_IN_PU,
156 PTW3_IN_PU, PTW2_IN_PU, PTW1_IN_PU, PTW0_IN_PU,
157 PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU,
158 PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU,
159 PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU,
160 PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU,
161 PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU,
162 PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU,
163 PINMUX_INPUT_PULLUP_END,
164
165 PINMUX_OUTPUT_BEGIN,
166 PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
167 PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
168 PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
169 PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
170 PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
171 PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
172 PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
173 PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
174 PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT,
175 PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
176 PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT,
177 PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT,
178 PTG5_OUT, PTG4_OUT,
179 PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
180 PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
181 PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
182 PTJ7_OUT, PTJ6_OUT, PTJ5_OUT,
183 PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
184 PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
185 PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
186 PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT,
187 PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
188 PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
189 PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
190 PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT,
191 PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
192 PTQ7_OUT, PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
193 PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
194 PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
195 PTR1_OUT, PTR0_OUT,
196 PTS6_OUT, PTS5_OUT, PTS4_OUT,
197 PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
198 PTT7_OUT, PTT6_OUT, PTT5_OUT, PTT4_OUT,
199 PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
200 PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT,
201 PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
202 PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT,
203 PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
204 PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT,
205 PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
206 PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT,
207 PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
208 PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT,
209 PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
210 PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT,
211 PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT,
212 PINMUX_OUTPUT_END,
213
214 PINMUX_FUNCTION_BEGIN,
215 PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
216 PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
217 PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
218 PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
219 PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
220 PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
221 PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
222 PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
223 PTE7_FN, PTE6_FN, PTE5_FN, PTE4_FN,
224 PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
225 PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN,
226 PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
227 PTG5_FN, PTG4_FN,
228 PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
229 PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN,
230 PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
231 PTJ7_FN, PTJ6_FN, PTJ5_FN,
232 PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
233 PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
234 PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
235 PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN,
236 PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
237 PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
238 PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
239 PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN,
240 PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
241 PTQ7_FN, PTQ6_FN, PTQ5_FN, PTQ4_FN,
242 PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
243 PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
244 PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
245 PTS6_FN, PTS5_FN, PTS4_FN,
246 PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
247 PTT7_FN, PTT6_FN, PTT5_FN, PTT4_FN,
248 PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
249 PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN,
250 PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
251 PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN,
252 PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
253 PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN,
254 PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN,
255 PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN,
256 PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN,
257 PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN,
258 PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN,
259 PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
260 PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
261
262
263 PSA15_0, PSA15_1,
264 PSA14_0, PSA14_1,
265 PSA13_0, PSA13_1,
266 PSA12_0, PSA12_1,
267 PSA10_0, PSA10_1,
268 PSA9_0, PSA9_1,
269 PSA8_0, PSA8_1,
270 PSA7_0, PSA7_1,
271 PSA6_0, PSA6_1,
272 PSA5_0, PSA5_1,
273 PSA3_0, PSA3_1,
274 PSA2_0, PSA2_1,
275 PSA1_0, PSA1_1,
276 PSA0_0, PSA0_1,
277
278 PSB14_0, PSB14_1,
279 PSB13_0, PSB13_1,
280 PSB12_0, PSB12_1,
281 PSB11_0, PSB11_1,
282 PSB10_0, PSB10_1,
283 PSB9_0, PSB9_1,
284 PSB8_0, PSB8_1,
285 PSB7_0, PSB7_1,
286 PSB6_0, PSB6_1,
287 PSB5_0, PSB5_1,
288 PSB4_0, PSB4_1,
289 PSB3_0, PSB3_1,
290 PSB2_0, PSB2_1,
291 PSB1_0, PSB1_1,
292 PSB0_0, PSB0_1,
293
294 PSC15_0, PSC15_1,
295 PSC14_0, PSC14_1,
296 PSC13_0, PSC13_1,
297 PSC12_0, PSC12_1,
298 PSC11_0, PSC11_1,
299 PSC10_0, PSC10_1,
300 PSC9_0, PSC9_1,
301 PSC8_0, PSC8_1,
302 PSC7_0, PSC7_1,
303 PSC6_0, PSC6_1,
304 PSC5_0, PSC5_1,
305 PSC4_0, PSC4_1,
306 PSC2_0, PSC2_1,
307 PSC1_0, PSC1_1,
308 PSC0_0, PSC0_1,
309
310 PSD15_0, PSD15_1,
311 PSD14_0, PSD14_1,
312 PSD13_0, PSD13_1,
313 PSD12_0, PSD12_1,
314 PSD11_0, PSD11_1,
315 PSD10_0, PSD10_1,
316 PSD9_0, PSD9_1,
317 PSD8_0, PSD8_1,
318 PSD7_0, PSD7_1,
319 PSD6_0, PSD6_1,
320 PSD5_0, PSD5_1,
321 PSD4_0, PSD4_1,
322 PSD3_0, PSD3_1,
323 PSD2_0, PSD2_1,
324 PSD1_0, PSD1_1,
325 PSD0_0, PSD0_1,
326
327 PSE15_0, PSE15_1,
328 PSE14_0, PSE14_1,
329 PSE13_0, PSE13_1,
330 PSE12_0, PSE12_1,
331 PSE11_0, PSE11_1,
332 PSE10_0, PSE10_1,
333 PSE9_0, PSE9_1,
334 PSE8_0, PSE8_1,
335 PSE7_0, PSE7_1,
336 PSE6_0, PSE6_1,
337 PSE5_0, PSE5_1,
338 PSE4_0, PSE4_1,
339 PSE3_0, PSE3_1,
340 PSE2_0, PSE2_1,
341 PSE1_0, PSE1_1,
342 PSE0_0, PSE0_1,
343 PINMUX_FUNCTION_END,
344
345 PINMUX_MARK_BEGIN,
346 /*PTA*/
347 D23_MARK, KEYOUT2_MARK, IDED15_MARK,
348 D22_MARK, KEYOUT1_MARK, IDED14_MARK,
349 D21_MARK, KEYOUT0_MARK, IDED13_MARK,
350 D20_MARK, KEYIN4_MARK, IDED12_MARK,
351 D19_MARK, KEYIN3_MARK, IDED11_MARK,
352 D18_MARK, KEYIN2_MARK, IDED10_MARK,
353 D17_MARK, KEYIN1_MARK, IDED9_MARK,
354 D16_MARK, KEYIN0_MARK, IDED8_MARK,
355
356 /*PTB*/
357 D31_MARK, TPUTO1_MARK, IDEA1_MARK,
358 D30_MARK, TPUTO0_MARK, IDEA0_MARK,
359 D29_MARK, IODREQ_MARK,
360 D28_MARK, IDECS0_MARK,
361 D27_MARK, IDECS1_MARK,
362 D26_MARK, KEYOUT5_IN5_MARK, IDEIORD_MARK,
363 D25_MARK, KEYOUT4_IN6_MARK, IDEIOWR_MARK,
364 D24_MARK, KEYOUT3_MARK, IDEINT_MARK,
365
366 /*PTC*/
367 LCDD7_MARK,
368 LCDD6_MARK,
369 LCDD5_MARK,
370 LCDD4_MARK,
371 LCDD3_MARK,
372 LCDD2_MARK,
373 LCDD1_MARK,
374 LCDD0_MARK,
375
376 /*PTD*/
377 LCDD15_MARK,
378 LCDD14_MARK,
379 LCDD13_MARK,
380 LCDD12_MARK,
381 LCDD11_MARK,
382 LCDD10_MARK,
383 LCDD9_MARK,
384 LCDD8_MARK,
385
386 /*PTE*/
387 FSIMCKB_MARK,
388 FSIMCKA_MARK,
389 LCDD21_MARK, SCIF2_L_TXD_MARK,
390 LCDD20_MARK, SCIF4_SCK_MARK,
391 LCDD19_MARK, SCIF4_RXD_MARK,
392 LCDD18_MARK, SCIF4_TXD_MARK,
393 LCDD17_MARK,
394 LCDD16_MARK,
395
396 /*PTF*/
397 LCDVSYN_MARK,
398 LCDDISP_MARK, LCDRS_MARK,
399 LCDHSYN_MARK, LCDCS_MARK,
400 LCDDON_MARK,
401 LCDDCK_MARK, LCDWR_MARK,
402 LCDVEPWC_MARK, SCIF0_TXD_MARK,
403 LCDD23_MARK, SCIF2_L_SCK_MARK,
404 LCDD22_MARK, SCIF2_L_RXD_MARK,
405
406 /*PTG*/
407 AUDCK_MARK,
408 AUDSYNC_MARK,
409 AUDATA3_MARK,
410 AUDATA2_MARK,
411 AUDATA1_MARK,
412 AUDATA0_MARK,
413
414 /*PTH*/
415 VIO0_VD_MARK,
416 VIO0_CLK_MARK,
417 VIO0_D7_MARK,
418 VIO0_D6_MARK,
419 VIO0_D5_MARK,
420 VIO0_D4_MARK,
421 VIO0_D3_MARK,
422 VIO0_D2_MARK,
423
424 /*PTJ*/
425 PDSTATUS_MARK,
426 STATUS2_MARK,
427 STATUS0_MARK,
428 A25_MARK, BS_MARK,
429 A24_MARK,
430 A23_MARK,
431 A22_MARK,
432
433 /*PTK*/
434 VIO1_D5_MARK, VIO0_D13_MARK, IDED5_MARK,
435 VIO1_D4_MARK, VIO0_D12_MARK, IDED4_MARK,
436 VIO1_D3_MARK, VIO0_D11_MARK, IDED3_MARK,
437 VIO1_D2_MARK, VIO0_D10_MARK, IDED2_MARK,
438 VIO1_D1_MARK, VIO0_D9_MARK, IDED1_MARK,
439 VIO1_D0_MARK, VIO0_D8_MARK, IDED0_MARK,
440 VIO0_FLD_MARK,
441 VIO0_HD_MARK,
442
443 /*PTL*/
444 DV_D5_MARK, SCIF3_V_SCK_MARK, RMII_RXD0_MARK,
445 DV_D4_MARK, SCIF3_V_RXD_MARK, RMII_RXD1_MARK,
446 DV_D3_MARK, SCIF3_V_TXD_MARK, RMII_REF_CLK_MARK,
447 DV_D2_MARK, SCIF1_SCK_MARK, RMII_TX_EN_MARK,
448 DV_D1_MARK, SCIF1_RXD_MARK, RMII_TXD0_MARK,
449 DV_D0_MARK, SCIF1_TXD_MARK, RMII_TXD1_MARK,
450 DV_D15_MARK,
451 DV_D14_MARK, MSIOF0_MCK_MARK,
452
453 /*PTM*/
454 DV_D13_MARK, MSIOF0_TSCK_MARK,
455 DV_D12_MARK, MSIOF0_RXD_MARK,
456 DV_D11_MARK, MSIOF0_TXD_MARK,
457 DV_D10_MARK, MSIOF0_TSYNC_MARK,
458 DV_D9_MARK, MSIOF0_SS1_MARK, MSIOF0_RSCK_MARK,
459 DV_D8_MARK, MSIOF0_SS2_MARK, MSIOF0_RSYNC_MARK,
460 LCDVCPWC_MARK, SCIF0_RXD_MARK,
461 LCDRD_MARK, SCIF0_SCK_MARK,
462
463 /*PTN*/
464 VIO0_D1_MARK,
465 VIO0_D0_MARK,
466 DV_CLKI_MARK,
467 DV_CLK_MARK, SCIF2_V_SCK_MARK,
468 DV_VSYNC_MARK, SCIF2_V_RXD_MARK,
469 DV_HSYNC_MARK, SCIF2_V_TXD_MARK,
470 DV_D7_MARK, SCIF3_V_CTS_MARK, RMII_RX_ER_MARK,
471 DV_D6_MARK, SCIF3_V_RTS_MARK, RMII_CRS_DV_MARK,
472
473 /*PTQ*/
474 D7_MARK,
475 D6_MARK,
476 D5_MARK,
477 D4_MARK,
478 D3_MARK,
479 D2_MARK,
480 D1_MARK,
481 D0_MARK,
482
483 /*PTR*/
484 CS6B_CE1B_MARK,
485 CS6A_CE2B_MARK,
486 CS5B_CE1A_MARK,
487 CS5A_CE2A_MARK,
488 IOIS16_MARK, LCDLCLK_MARK,
489 WAIT_MARK,
490 WE3_ICIOWR_MARK, TPUTO3_MARK, TPUTI3_MARK,
491 WE2_ICIORD_MARK, TPUTO2_MARK, IDEA2_MARK,
492
493 /*PTS*/
494 VIO_CKO_MARK,
495 VIO1_FLD_MARK, TPUTI2_MARK, IDEIORDY_MARK,
496 VIO1_HD_MARK, SCIF5_SCK_MARK,
497 VIO1_VD_MARK, SCIF5_RXD_MARK,
498 VIO1_CLK_MARK, SCIF5_TXD_MARK,
499 VIO1_D7_MARK, VIO0_D15_MARK, IDED7_MARK,
500 VIO1_D6_MARK, VIO0_D14_MARK, IDED6_MARK,
501
502 /*PTT*/
503 D15_MARK,
504 D14_MARK,
505 D13_MARK,
506 D12_MARK,
507 D11_MARK,
508 D10_MARK,
509 D9_MARK,
510 D8_MARK,
511
512 /*PTU*/
513 DMAC_DACK0_MARK,
514 DMAC_DREQ0_MARK,
515 FSIOASD_MARK,
516 FSIIABCK_MARK,
517 FSIIALRCK_MARK,
518 FSIOABCK_MARK,
519 FSIOALRCK_MARK,
520 CLKAUDIOAO_MARK,
521
522 /*PTV*/
523 FSIIBSD_MARK, MSIOF1_SS2_MARK, MSIOF1_RSYNC_MARK,
524 FSIOBSD_MARK, MSIOF1_SS1_MARK, MSIOF1_RSCK_MARK,
525 FSIIBBCK_MARK, MSIOF1_RXD_MARK,
526 FSIIBLRCK_MARK, MSIOF1_TSYNC_MARK,
527 FSIOBBCK_MARK, MSIOF1_TSCK_MARK,
528 FSIOBLRCK_MARK, MSIOF1_TXD_MARK,
529 CLKAUDIOBO_MARK, MSIOF1_MCK_MARK,
530 FSIIASD_MARK,
531
532 /*PTW*/
533 MMC_D7_MARK, SDHI1CD_MARK, IODACK_MARK,
534 MMC_D6_MARK, SDHI1WP_MARK, IDERST_MARK,
535 MMC_D5_MARK, SDHI1D3_MARK, EXBUF_ENB_MARK,
536 MMC_D4_MARK, SDHI1D2_MARK, DIRECTION_MARK,
537 MMC_D3_MARK, SDHI1D1_MARK,
538 MMC_D2_MARK, SDHI1D0_MARK,
539 MMC_D1_MARK, SDHI1CMD_MARK,
540 MMC_D0_MARK, SDHI1CLK_MARK,
541
542 /*PTX*/
543 DMAC_DACK1_MARK, IRDA_OUT_MARK,
544 DMAC_DREQ1_MARK, IRDA_IN_MARK,
545 TSIF_TS0_SDAT_MARK, LNKSTA_MARK,
546 TSIF_TS0_SCK_MARK, MDIO_MARK,
547 TSIF_TS0_SDEN_MARK, MDC_MARK,
548 TSIF_TS0_SPSYNC_MARK,
549 MMC_CLK_MARK,
550 MMC_CMD_MARK,
551
552 /*PTY*/
553 SDHI0CD_MARK,
554 SDHI0WP_MARK,
555 SDHI0D3_MARK,
556 SDHI0D2_MARK,
557 SDHI0D1_MARK,
558 SDHI0D0_MARK,
559 SDHI0CMD_MARK,
560 SDHI0CLK_MARK,
561
562 /*PTZ*/
563 INTC_IRQ7_MARK, SCIF3_I_CTS_MARK,
564 INTC_IRQ6_MARK, SCIF3_I_RTS_MARK,
565 INTC_IRQ5_MARK, SCIF3_I_SCK_MARK,
566 INTC_IRQ4_MARK, SCIF3_I_RXD_MARK,
567 INTC_IRQ3_MARK, SCIF3_I_TXD_MARK,
568 INTC_IRQ2_MARK,
569 INTC_IRQ1_MARK,
570 INTC_IRQ0_MARK,
571 PINMUX_MARK_END,
572};
573
574static pinmux_enum_t pinmux_data[] = {
575 /* PTA GPIO */
576 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
577 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
578 PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT, PTA5_IN_PU),
579 PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU),
580 PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU),
581 PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU),
582 PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU),
583 PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU),
584
585 /* PTB GPIO */
586 PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT, PTB7_IN_PU),
587 PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT, PTB6_IN_PU),
588 PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT, PTB5_IN_PU),
589 PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT, PTB4_IN_PU),
590 PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT, PTB3_IN_PU),
591 PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU),
592 PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU),
593 PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT, PTB0_IN_PU),
594
595 /* PTC GPIO */
596 PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT, PTC7_IN_PU),
597 PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT, PTC6_IN_PU),
598 PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT, PTC5_IN_PU),
599 PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT, PTC4_IN_PU),
600 PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT, PTC3_IN_PU),
601 PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT, PTC2_IN_PU),
602 PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT, PTC1_IN_PU),
603 PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT, PTC0_IN_PU),
604
605 /* PTD GPIO */
606 PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT, PTD7_IN_PU),
607 PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT, PTD6_IN_PU),
608 PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT, PTD5_IN_PU),
609 PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT, PTD4_IN_PU),
610 PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT, PTD3_IN_PU),
611 PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT, PTD2_IN_PU),
612 PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT, PTD1_IN_PU),
613 PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT, PTD0_IN_PU),
614
615 /* PTE GPIO */
616 PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT, PTE7_IN_PU),
617 PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT, PTE6_IN_PU),
618 PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT, PTE5_IN_PU),
619 PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT, PTE4_IN_PU),
620 PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT, PTE3_IN_PU),
621 PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT, PTE2_IN_PU),
622 PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT, PTE1_IN_PU),
623 PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT, PTE0_IN_PU),
624
625 /* PTF GPIO */
626 PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT, PTF7_IN_PU),
627 PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT, PTF6_IN_PU),
628 PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT, PTF5_IN_PU),
629 PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT, PTF4_IN_PU),
630 PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT, PTF3_IN_PU),
631 PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT, PTF2_IN_PU),
632 PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT, PTF1_IN_PU),
633 PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT, PTF0_IN_PU),
634
635 /* PTG GPIO */
636 PINMUX_DATA(PTG5_DATA, PTG5_OUT),
637 PINMUX_DATA(PTG4_DATA, PTG4_OUT),
638 PINMUX_DATA(PTG3_DATA, PTG3_OUT),
639 PINMUX_DATA(PTG2_DATA, PTG2_OUT),
640 PINMUX_DATA(PTG1_DATA, PTG1_OUT),
641 PINMUX_DATA(PTG0_DATA, PTG0_OUT),
642
643 /* PTH GPIO */
644 PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT, PTH7_IN_PU),
645 PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT, PTH6_IN_PU),
646 PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT, PTH5_IN_PU),
647 PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT, PTH4_IN_PU),
648 PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT, PTH3_IN_PU),
649 PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT, PTH2_IN_PU),
650 PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT, PTH1_IN_PU),
651 PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT, PTH0_IN_PU),
652
653 /* PTJ GPIO */
654 PINMUX_DATA(PTJ7_DATA, PTJ7_OUT),
655 PINMUX_DATA(PTJ6_DATA, PTJ6_OUT),
656 PINMUX_DATA(PTJ5_DATA, PTJ5_OUT),
657 PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT, PTJ3_IN_PU),
658 PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT, PTJ2_IN_PU),
659 PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT, PTJ1_IN_PU),
660 PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT, PTJ0_IN_PU),
661
662 /* PTK GPIO */
663 PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT, PTK7_IN_PU),
664 PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT, PTK6_IN_PU),
665 PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT, PTK5_IN_PU),
666 PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT, PTK4_IN_PU),
667 PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT, PTK3_IN_PU),
668 PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT, PTK2_IN_PU),
669 PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT, PTK1_IN_PU),
670 PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT, PTK0_IN_PU),
671
672 /* PTL GPIO */
673 PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT, PTL7_IN_PU),
674 PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT, PTL6_IN_PU),
675 PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT, PTL5_IN_PU),
676 PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT, PTL4_IN_PU),
677 PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT, PTL3_IN_PU),
678 PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT, PTL2_IN_PU),
679 PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT, PTL1_IN_PU),
680 PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT, PTL0_IN_PU),
681
682 /* PTM GPIO */
683 PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT, PTM7_IN_PU),
684 PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT, PTM6_IN_PU),
685 PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT, PTM5_IN_PU),
686 PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT, PTM4_IN_PU),
687 PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT, PTM3_IN_PU),
688 PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT, PTM2_IN_PU),
689 PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT, PTM1_IN_PU),
690 PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT, PTM0_IN_PU),
691
692 /* PTN GPIO */
693 PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT, PTN7_IN_PU),
694 PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT, PTN6_IN_PU),
695 PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT, PTN5_IN_PU),
696 PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT, PTN4_IN_PU),
697 PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT, PTN3_IN_PU),
698 PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT, PTN2_IN_PU),
699 PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT, PTN1_IN_PU),
700 PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT, PTN0_IN_PU),
701
702 /* PTQ GPIO */
703 PINMUX_DATA(PTQ7_DATA, PTQ7_IN, PTQ7_OUT, PTQ7_IN_PU),
704 PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT, PTQ6_IN_PU),
705 PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT, PTQ5_IN_PU),
706 PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT, PTQ4_IN_PU),
707 PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT, PTQ3_IN_PU),
708 PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT, PTQ2_IN_PU),
709 PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT, PTQ1_IN_PU),
710 PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT, PTQ0_IN_PU),
711
712 /* PTR GPIO */
713 PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT, PTR7_IN_PU),
714 PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT, PTR6_IN_PU),
715 PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT, PTR5_IN_PU),
716 PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT, PTR4_IN_PU),
717 PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_IN_PU),
718 PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU),
719 PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT, PTR1_IN_PU),
720 PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT, PTR0_IN_PU),
721
722 /* PTS GPIO */
723 PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT, PTS6_IN_PU),
724 PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT, PTS5_IN_PU),
725 PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT, PTS4_IN_PU),
726 PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT, PTS3_IN_PU),
727 PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT, PTS2_IN_PU),
728 PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT, PTS1_IN_PU),
729 PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT, PTS0_IN_PU),
730
731 /* PTT GPIO */
732 PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT, PTT7_IN_PU),
733 PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT, PTT6_IN_PU),
734 PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT, PTT5_IN_PU),
735 PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT, PTT4_IN_PU),
736 PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT, PTT3_IN_PU),
737 PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT, PTT2_IN_PU),
738 PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT, PTT1_IN_PU),
739 PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT, PTT0_IN_PU),
740
741 /* PTU GPIO */
742 PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT, PTU7_IN_PU),
743 PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT, PTU6_IN_PU),
744 PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT, PTU5_IN_PU),
745 PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT, PTU4_IN_PU),
746 PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT, PTU3_IN_PU),
747 PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT, PTU2_IN_PU),
748 PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT, PTU1_IN_PU),
749 PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT, PTU0_IN_PU),
750
751 /* PTV GPIO */
752 PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT, PTV7_IN_PU),
753 PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT, PTV6_IN_PU),
754 PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT, PTV5_IN_PU),
755 PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT, PTV4_IN_PU),
756 PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT, PTV3_IN_PU),
757 PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT, PTV2_IN_PU),
758 PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT, PTV1_IN_PU),
759 PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT, PTV0_IN_PU),
760
761 /* PTW GPIO */
762 PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT, PTW7_IN_PU),
763 PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT, PTW6_IN_PU),
764 PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT, PTW5_IN_PU),
765 PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT, PTW4_IN_PU),
766 PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT, PTW3_IN_PU),
767 PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT, PTW2_IN_PU),
768 PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT, PTW1_IN_PU),
769 PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT, PTW0_IN_PU),
770
771 /* PTX GPIO */
772 PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT, PTX7_IN_PU),
773 PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT, PTX6_IN_PU),
774 PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT, PTX5_IN_PU),
775 PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT, PTX4_IN_PU),
776 PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT, PTX3_IN_PU),
777 PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT, PTX2_IN_PU),
778 PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT, PTX1_IN_PU),
779 PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT, PTX0_IN_PU),
780
781 /* PTY GPIO */
782 PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT, PTY7_IN_PU),
783 PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT, PTY6_IN_PU),
784 PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT, PTY5_IN_PU),
785 PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT, PTY4_IN_PU),
786 PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT, PTY3_IN_PU),
787 PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT, PTY2_IN_PU),
788 PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT, PTY1_IN_PU),
789 PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT, PTY0_IN_PU),
790
791 /* PTZ GPIO */
792 PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT, PTZ7_IN_PU),
793 PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT, PTZ6_IN_PU),
794 PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT, PTZ5_IN_PU),
795 PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT, PTZ4_IN_PU),
796 PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT, PTZ3_IN_PU),
797 PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT, PTZ2_IN_PU),
798 PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT, PTZ1_IN_PU),
799 PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT, PTZ0_IN_PU),
800
801 /* PTA FN */
802 PINMUX_DATA(D23_MARK, PSA15_0, PSA14_0, PTA7_FN),
803 PINMUX_DATA(D22_MARK, PSA15_0, PSA14_0, PTA6_FN),
804 PINMUX_DATA(D21_MARK, PSA15_0, PSA14_0, PTA5_FN),
805 PINMUX_DATA(D20_MARK, PSA15_0, PSA14_0, PTA4_FN),
806 PINMUX_DATA(D19_MARK, PSA15_0, PSA14_0, PTA3_FN),
807 PINMUX_DATA(D18_MARK, PSA15_0, PSA14_0, PTA2_FN),
808 PINMUX_DATA(D17_MARK, PSA15_0, PSA14_0, PTA1_FN),
809 PINMUX_DATA(D16_MARK, PSA15_0, PSA14_0, PTA0_FN),
810
811 PINMUX_DATA(KEYOUT2_MARK, PSA15_0, PSA14_1, PTA7_FN),
812 PINMUX_DATA(KEYOUT1_MARK, PSA15_0, PSA14_1, PTA6_FN),
813 PINMUX_DATA(KEYOUT0_MARK, PSA15_0, PSA14_1, PTA5_FN),
814 PINMUX_DATA(KEYIN4_MARK, PSA15_0, PSA14_1, PTA4_FN),
815 PINMUX_DATA(KEYIN3_MARK, PSA15_0, PSA14_1, PTA3_FN),
816 PINMUX_DATA(KEYIN2_MARK, PSA15_0, PSA14_1, PTA2_FN),
817 PINMUX_DATA(KEYIN1_MARK, PSA15_0, PSA14_1, PTA1_FN),
818 PINMUX_DATA(KEYIN0_MARK, PSA15_0, PSA14_1, PTA0_FN),
819
820 PINMUX_DATA(IDED15_MARK, PSA15_1, PSA14_0, PTA7_FN),
821 PINMUX_DATA(IDED14_MARK, PSA15_1, PSA14_0, PTA6_FN),
822 PINMUX_DATA(IDED13_MARK, PSA15_1, PSA14_0, PTA5_FN),
823 PINMUX_DATA(IDED12_MARK, PSA15_1, PSA14_0, PTA4_FN),
824 PINMUX_DATA(IDED11_MARK, PSA15_1, PSA14_0, PTA3_FN),
825 PINMUX_DATA(IDED10_MARK, PSA15_1, PSA14_0, PTA2_FN),
826 PINMUX_DATA(IDED9_MARK, PSA15_1, PSA14_0, PTA1_FN),
827 PINMUX_DATA(IDED8_MARK, PSA15_1, PSA14_0, PTA0_FN),
828
829 /* PTB FN */
830 PINMUX_DATA(D31_MARK, PSE15_0, PSE14_0, PTB7_FN),
831 PINMUX_DATA(D30_MARK, PSE15_0, PSE14_0, PTB6_FN),
832 PINMUX_DATA(D29_MARK, PSE11_0, PTB5_FN),
833 PINMUX_DATA(D28_MARK, PSE11_0, PTB4_FN),
834 PINMUX_DATA(D27_MARK, PSE11_0, PTB3_FN),
835 PINMUX_DATA(D26_MARK, PSA15_0, PSA14_0, PTB2_FN),
836 PINMUX_DATA(D25_MARK, PSA15_0, PSA14_0, PTB1_FN),
837 PINMUX_DATA(D24_MARK, PSA15_0, PSA14_0, PTB0_FN),
838
839 PINMUX_DATA(IDEA1_MARK, PSE15_1, PSE14_0, PTB7_FN),
840 PINMUX_DATA(IDEA0_MARK, PSE15_1, PSE14_0, PTB6_FN),
841 PINMUX_DATA(IODREQ_MARK, PSE11_1, PTB5_FN),
842 PINMUX_DATA(IDECS0_MARK, PSE11_1, PTB4_FN),
843 PINMUX_DATA(IDECS1_MARK, PSE11_1, PTB3_FN),
844 PINMUX_DATA(IDEIORD_MARK, PSA15_1, PSA14_0, PTB2_FN),
845 PINMUX_DATA(IDEIOWR_MARK, PSA15_1, PSA14_0, PTB1_FN),
846 PINMUX_DATA(IDEINT_MARK, PSA15_1, PSA14_0, PTB0_FN),
847
848 PINMUX_DATA(TPUTO1_MARK, PSE15_0, PSE14_1, PTB7_FN),
849 PINMUX_DATA(TPUTO0_MARK, PSE15_0, PSE14_1, PTB6_FN),
850
851 PINMUX_DATA(KEYOUT5_IN5_MARK, PSA15_0, PSA14_1, PTB2_FN),
852 PINMUX_DATA(KEYOUT4_IN6_MARK, PSA15_0, PSA14_1, PTB1_FN),
853 PINMUX_DATA(KEYOUT3_MARK, PSA15_0, PSA14_1, PTB0_FN),
854
855 /* PTC FN */
856 PINMUX_DATA(LCDD7_MARK, PSD5_0, PTC7_FN),
857 PINMUX_DATA(LCDD6_MARK, PSD5_0, PTC6_FN),
858 PINMUX_DATA(LCDD5_MARK, PSD5_0, PTC5_FN),
859 PINMUX_DATA(LCDD4_MARK, PSD5_0, PTC4_FN),
860 PINMUX_DATA(LCDD3_MARK, PSD5_0, PTC3_FN),
861 PINMUX_DATA(LCDD2_MARK, PSD5_0, PTC2_FN),
862 PINMUX_DATA(LCDD1_MARK, PSD5_0, PTC1_FN),
863 PINMUX_DATA(LCDD0_MARK, PSD5_0, PTC0_FN),
864
865 /* PTD FN */
866 PINMUX_DATA(LCDD15_MARK, PSD5_0, PTD7_FN),
867 PINMUX_DATA(LCDD14_MARK, PSD5_0, PTD6_FN),
868 PINMUX_DATA(LCDD13_MARK, PSD5_0, PTD5_FN),
869 PINMUX_DATA(LCDD12_MARK, PSD5_0, PTD4_FN),
870 PINMUX_DATA(LCDD11_MARK, PSD5_0, PTD3_FN),
871 PINMUX_DATA(LCDD10_MARK, PSD5_0, PTD2_FN),
872 PINMUX_DATA(LCDD9_MARK, PSD5_0, PTD1_FN),
873 PINMUX_DATA(LCDD8_MARK, PSD5_0, PTD0_FN),
874
875 /* PTE FN */
876 PINMUX_DATA(FSIMCKB_MARK, PTE7_FN),
877 PINMUX_DATA(FSIMCKA_MARK, PTE6_FN),
878
879 PINMUX_DATA(LCDD21_MARK, PSC5_0, PSC4_0, PTE5_FN),
880 PINMUX_DATA(LCDD20_MARK, PSD3_0, PSD2_0, PTE4_FN),
881 PINMUX_DATA(LCDD19_MARK, PSA3_0, PSA2_0, PTE3_FN),
882 PINMUX_DATA(LCDD18_MARK, PSA3_0, PSA2_0, PTE2_FN),
883 PINMUX_DATA(LCDD17_MARK, PSD5_0, PTE1_FN),
884 PINMUX_DATA(LCDD16_MARK, PSD5_0, PTE0_FN),
885
886 PINMUX_DATA(SCIF2_L_TXD_MARK, PSC5_0, PSC4_1, PTE5_FN),
887 PINMUX_DATA(SCIF4_SCK_MARK, PSD3_0, PSD2_1, PTE4_FN),
888 PINMUX_DATA(SCIF4_RXD_MARK, PSA3_0, PSA2_1, PTE3_FN),
889 PINMUX_DATA(SCIF4_TXD_MARK, PSA3_0, PSA2_1, PTE2_FN),
890
891 /* PTF FN */
892 PINMUX_DATA(LCDVSYN_MARK, PSD8_0, PTF7_FN),
893 PINMUX_DATA(LCDDISP_MARK, PSD10_0, PSD9_0, PTF6_FN),
894 PINMUX_DATA(LCDHSYN_MARK, PSD10_0, PSD9_0, PTF5_FN),
895 PINMUX_DATA(LCDDON_MARK, PSD8_0, PTF4_FN),
896 PINMUX_DATA(LCDDCK_MARK, PSD10_0, PSD9_0, PTF3_FN),
897 PINMUX_DATA(LCDVEPWC_MARK, PSA6_0, PTF2_FN),
898 PINMUX_DATA(LCDD23_MARK, PSC7_0, PSC6_0, PTF1_FN),
899 PINMUX_DATA(LCDD22_MARK, PSC5_0, PSC4_0, PTF0_FN),
900
901 PINMUX_DATA(LCDRS_MARK, PSD10_0, PSD9_1, PTF6_FN),
902 PINMUX_DATA(LCDCS_MARK, PSD10_0, PSD9_1, PTF5_FN),
903 PINMUX_DATA(LCDWR_MARK, PSD10_0, PSD9_1, PTF3_FN),
904
905 PINMUX_DATA(SCIF0_TXD_MARK, PSA6_1, PTF2_FN),
906 PINMUX_DATA(SCIF2_L_SCK_MARK, PSC7_0, PSC6_1, PTF1_FN),
907 PINMUX_DATA(SCIF2_L_RXD_MARK, PSC5_0, PSC4_1, PTF0_FN),
908
909 /* PTG FN */
910 PINMUX_DATA(AUDCK_MARK, PTG5_FN),
911 PINMUX_DATA(AUDSYNC_MARK, PTG4_FN),
912 PINMUX_DATA(AUDATA3_MARK, PTG3_FN),
913 PINMUX_DATA(AUDATA2_MARK, PTG2_FN),
914 PINMUX_DATA(AUDATA1_MARK, PTG1_FN),
915 PINMUX_DATA(AUDATA0_MARK, PTG0_FN),
916
917 /* PTH FN */
918 PINMUX_DATA(VIO0_VD_MARK, PTH7_FN),
919 PINMUX_DATA(VIO0_CLK_MARK, PTH6_FN),
920 PINMUX_DATA(VIO0_D7_MARK, PTH5_FN),
921 PINMUX_DATA(VIO0_D6_MARK, PTH4_FN),
922 PINMUX_DATA(VIO0_D5_MARK, PTH3_FN),
923 PINMUX_DATA(VIO0_D4_MARK, PTH2_FN),
924 PINMUX_DATA(VIO0_D3_MARK, PTH1_FN),
925 PINMUX_DATA(VIO0_D2_MARK, PTH0_FN),
926
927 /* PTJ FN */
928 PINMUX_DATA(PDSTATUS_MARK, PTJ7_FN),
929 PINMUX_DATA(STATUS2_MARK, PTJ6_FN),
930 PINMUX_DATA(STATUS0_MARK, PTJ5_FN),
931 PINMUX_DATA(A25_MARK, PSA8_0, PTJ3_FN),
932 PINMUX_DATA(BS_MARK, PSA8_1, PTJ3_FN),
933 PINMUX_DATA(A24_MARK, PTJ2_FN),
934 PINMUX_DATA(A23_MARK, PTJ1_FN),
935 PINMUX_DATA(A22_MARK, PTJ0_FN),
936
937 /* PTK FN */
938 PINMUX_DATA(VIO1_D5_MARK, PSB7_0, PSB6_0, PTK7_FN),
939 PINMUX_DATA(VIO1_D4_MARK, PSB7_0, PSB6_0, PTK6_FN),
940 PINMUX_DATA(VIO1_D3_MARK, PSB7_0, PSB6_0, PTK5_FN),
941 PINMUX_DATA(VIO1_D2_MARK, PSB7_0, PSB6_0, PTK4_FN),
942 PINMUX_DATA(VIO1_D1_MARK, PSB7_0, PSB6_0, PTK3_FN),
943 PINMUX_DATA(VIO1_D0_MARK, PSB7_0, PSB6_0, PTK2_FN),
944
945 PINMUX_DATA(VIO0_D13_MARK, PSB7_0, PSB6_1, PTK7_FN),
946 PINMUX_DATA(VIO0_D12_MARK, PSB7_0, PSB6_1, PTK6_FN),
947 PINMUX_DATA(VIO0_D11_MARK, PSB7_0, PSB6_1, PTK5_FN),
948 PINMUX_DATA(VIO0_D10_MARK, PSB7_0, PSB6_1, PTK4_FN),
949 PINMUX_DATA(VIO0_D9_MARK, PSB7_0, PSB6_1, PTK3_FN),
950 PINMUX_DATA(VIO0_D8_MARK, PSB7_0, PSB6_1, PTK2_FN),
951
952 PINMUX_DATA(IDED5_MARK, PSB7_1, PSB6_0, PTK7_FN),
953 PINMUX_DATA(IDED4_MARK, PSB7_1, PSB6_0, PTK6_FN),
954 PINMUX_DATA(IDED3_MARK, PSB7_1, PSB6_0, PTK5_FN),
955 PINMUX_DATA(IDED2_MARK, PSB7_1, PSB6_0, PTK4_FN),
956 PINMUX_DATA(IDED1_MARK, PSB7_1, PSB6_0, PTK3_FN),
957 PINMUX_DATA(IDED0_MARK, PSB7_1, PSB6_0, PTK2_FN),
958
959 PINMUX_DATA(VIO0_FLD_MARK, PTK1_FN),
960 PINMUX_DATA(VIO0_HD_MARK, PTK0_FN),
961
962 /* PTL FN */
963 PINMUX_DATA(DV_D5_MARK, PSB9_0, PSB8_0, PTL7_FN),
964 PINMUX_DATA(DV_D4_MARK, PSB9_0, PSB8_0, PTL6_FN),
965 PINMUX_DATA(DV_D3_MARK, PSE7_0, PSE6_0, PTL5_FN),
966 PINMUX_DATA(DV_D2_MARK, PSC9_0, PSC8_0, PTL4_FN),
967 PINMUX_DATA(DV_D1_MARK, PSC9_0, PSC8_0, PTL3_FN),
968 PINMUX_DATA(DV_D0_MARK, PSC9_0, PSC8_0, PTL2_FN),
969 PINMUX_DATA(DV_D15_MARK, PSD4_0, PTL1_FN),
970 PINMUX_DATA(DV_D14_MARK, PSE5_0, PSE4_0, PTL0_FN),
971
972 PINMUX_DATA(SCIF3_V_SCK_MARK, PSB9_0, PSB8_1, PTL7_FN),
973 PINMUX_DATA(SCIF3_V_RXD_MARK, PSB9_0, PSB8_1, PTL6_FN),
974 PINMUX_DATA(SCIF3_V_TXD_MARK, PSE7_0, PSE6_1, PTL5_FN),
975 PINMUX_DATA(SCIF1_SCK_MARK, PSC9_0, PSC8_1, PTL4_FN),
976 PINMUX_DATA(SCIF1_RXD_MARK, PSC9_0, PSC8_1, PTL3_FN),
977 PINMUX_DATA(SCIF1_TXD_MARK, PSC9_0, PSC8_1, PTL2_FN),
978
979 PINMUX_DATA(RMII_RXD0_MARK, PSB9_1, PSB8_0, PTL7_FN),
980 PINMUX_DATA(RMII_RXD1_MARK, PSB9_1, PSB8_0, PTL6_FN),
981 PINMUX_DATA(RMII_REF_CLK_MARK, PSE7_1, PSE6_0, PTL5_FN),
982 PINMUX_DATA(RMII_TX_EN_MARK, PSC9_1, PSC8_0, PTL4_FN),
983 PINMUX_DATA(RMII_TXD0_MARK, PSC9_1, PSC8_0, PTL3_FN),
984 PINMUX_DATA(RMII_TXD1_MARK, PSC9_1, PSC8_0, PTL2_FN),
985
986 PINMUX_DATA(MSIOF0_MCK_MARK, PSE5_0, PSE4_1, PTL0_FN),
987
988 /* PTM FN */
989 PINMUX_DATA(DV_D13_MARK, PSC13_0, PSC12_0, PTM7_FN),
990 PINMUX_DATA(DV_D12_MARK, PSC13_0, PSC12_0, PTM6_FN),
991 PINMUX_DATA(DV_D11_MARK, PSC13_0, PSC12_0, PTM5_FN),
992 PINMUX_DATA(DV_D10_MARK, PSC13_0, PSC12_0, PTM4_FN),
993 PINMUX_DATA(DV_D9_MARK, PSC11_0, PSC10_0, PTM3_FN),
994 PINMUX_DATA(DV_D8_MARK, PSC11_0, PSC10_0, PTM2_FN),
995
996 PINMUX_DATA(MSIOF0_TSCK_MARK, PSC13_0, PSC12_1, PTM7_FN),
997 PINMUX_DATA(MSIOF0_RXD_MARK, PSC13_0, PSC12_1, PTM6_FN),
998 PINMUX_DATA(MSIOF0_TXD_MARK, PSC13_0, PSC12_1, PTM5_FN),
999 PINMUX_DATA(MSIOF0_TSYNC_MARK, PSC13_0, PSC12_1, PTM4_FN),
1000 PINMUX_DATA(MSIOF0_SS1_MARK, PSC11_0, PSC10_1, PTM3_FN),
1001 PINMUX_DATA(MSIOF0_RSCK_MARK, PSC11_1, PSC10_0, PTM3_FN),
1002 PINMUX_DATA(MSIOF0_SS2_MARK, PSC11_0, PSC10_1, PTM2_FN),
1003 PINMUX_DATA(MSIOF0_RSYNC_MARK, PSC11_1, PSC10_0, PTM2_FN),
1004
1005 PINMUX_DATA(LCDVCPWC_MARK, PSA6_0, PTM1_FN),
1006 PINMUX_DATA(LCDRD_MARK, PSA7_0, PTM0_FN),
1007
1008 PINMUX_DATA(SCIF0_RXD_MARK, PSA6_1, PTM1_FN),
1009 PINMUX_DATA(SCIF0_SCK_MARK, PSA7_1, PTM0_FN),
1010
1011 /* PTN FN */
1012 PINMUX_DATA(VIO0_D1_MARK, PTN7_FN),
1013 PINMUX_DATA(VIO0_D0_MARK, PTN6_FN),
1014
1015 PINMUX_DATA(DV_CLKI_MARK, PSD11_0, PTN5_FN),
1016 PINMUX_DATA(DV_CLK_MARK, PSD13_0, PSD12_0, PTN4_FN),
1017 PINMUX_DATA(DV_VSYNC_MARK, PSD15_0, PSD14_0, PTN3_FN),
1018 PINMUX_DATA(DV_HSYNC_MARK, PSB5_0, PSB4_0, PTN2_FN),
1019 PINMUX_DATA(DV_D7_MARK, PSB3_0, PSB2_0, PTN1_FN),
1020 PINMUX_DATA(DV_D6_MARK, PSB1_0, PSB0_0, PTN0_FN),
1021
1022 PINMUX_DATA(SCIF2_V_SCK_MARK, PSD13_0, PSD12_1, PTN4_FN),
1023 PINMUX_DATA(SCIF2_V_RXD_MARK, PSD15_0, PSD14_1, PTN3_FN),
1024 PINMUX_DATA(SCIF2_V_TXD_MARK, PSB5_0, PSB4_1, PTN2_FN),
1025 PINMUX_DATA(SCIF3_V_CTS_MARK, PSB3_0, PSB2_1, PTN1_FN),
1026 PINMUX_DATA(SCIF3_V_RTS_MARK, PSB1_0, PSB0_1, PTN0_FN),
1027
1028 PINMUX_DATA(RMII_RX_ER_MARK, PSB3_1, PSB2_0, PTN1_FN),
1029 PINMUX_DATA(RMII_CRS_DV_MARK, PSB1_1, PSB0_0, PTN0_FN),
1030
1031 /* PTQ FN */
1032 PINMUX_DATA(D7_MARK, PTQ7_FN),
1033 PINMUX_DATA(D6_MARK, PTQ6_FN),
1034 PINMUX_DATA(D5_MARK, PTQ5_FN),
1035 PINMUX_DATA(D4_MARK, PTQ4_FN),
1036 PINMUX_DATA(D3_MARK, PTQ3_FN),
1037 PINMUX_DATA(D2_MARK, PTQ2_FN),
1038 PINMUX_DATA(D1_MARK, PTQ1_FN),
1039 PINMUX_DATA(D0_MARK, PTQ0_FN),
1040
1041 /* PTR FN */
1042 PINMUX_DATA(CS6B_CE1B_MARK, PTR7_FN),
1043 PINMUX_DATA(CS6A_CE2B_MARK, PTR6_FN),
1044 PINMUX_DATA(CS5B_CE1A_MARK, PTR5_FN),
1045 PINMUX_DATA(CS5A_CE2A_MARK, PTR4_FN),
1046 PINMUX_DATA(IOIS16_MARK, PSA5_0, PTR3_FN),
1047 PINMUX_DATA(WAIT_MARK, PTR2_FN),
1048 PINMUX_DATA(WE3_ICIOWR_MARK, PSA1_0, PSA0_0, PTR1_FN),
1049 PINMUX_DATA(WE2_ICIORD_MARK, PSD1_0, PSD0_0, PTR0_FN),
1050
1051 PINMUX_DATA(LCDLCLK_MARK, PSA5_1, PTR3_FN),
1052
1053 PINMUX_DATA(IDEA2_MARK, PSD1_1, PSD0_0, PTR0_FN),
1054
1055 PINMUX_DATA(TPUTO3_MARK, PSA1_0, PSA0_1, PTR1_FN),
1056 PINMUX_DATA(TPUTI3_MARK, PSA1_1, PSA0_0, PTR1_FN),
1057 PINMUX_DATA(TPUTO2_MARK, PSD1_0, PSD0_1, PTR0_FN),
1058
1059 /* PTS FN */
1060 PINMUX_DATA(VIO_CKO_MARK, PTS6_FN),
1061
1062 PINMUX_DATA(TPUTI2_MARK, PSE9_0, PSE8_1, PTS5_FN),
1063
1064 PINMUX_DATA(IDEIORDY_MARK, PSE9_1, PSE8_0, PTS5_FN),
1065
1066 PINMUX_DATA(VIO1_FLD_MARK, PSE9_0, PSE8_0, PTS5_FN),
1067 PINMUX_DATA(VIO1_HD_MARK, PSA10_0, PTS4_FN),
1068 PINMUX_DATA(VIO1_VD_MARK, PSA9_0, PTS3_FN),
1069 PINMUX_DATA(VIO1_CLK_MARK, PSA9_0, PTS2_FN),
1070 PINMUX_DATA(VIO1_D7_MARK, PSB7_0, PSB6_0, PTS1_FN),
1071 PINMUX_DATA(VIO1_D6_MARK, PSB7_0, PSB6_0, PTS0_FN),
1072
1073 PINMUX_DATA(SCIF5_SCK_MARK, PSA10_1, PTS4_FN),
1074 PINMUX_DATA(SCIF5_RXD_MARK, PSA9_1, PTS3_FN),
1075 PINMUX_DATA(SCIF5_TXD_MARK, PSA9_1, PTS2_FN),
1076
1077 PINMUX_DATA(VIO0_D15_MARK, PSB7_0, PSB6_1, PTS1_FN),
1078 PINMUX_DATA(VIO0_D14_MARK, PSB7_0, PSB6_1, PTS0_FN),
1079
1080 PINMUX_DATA(IDED7_MARK, PSB7_1, PSB6_0, PTS1_FN),
1081 PINMUX_DATA(IDED6_MARK, PSB7_1, PSB6_0, PTS0_FN),
1082
1083 /* PTT FN */
1084 PINMUX_DATA(D15_MARK, PTT7_FN),
1085 PINMUX_DATA(D14_MARK, PTT6_FN),
1086 PINMUX_DATA(D13_MARK, PTT5_FN),
1087 PINMUX_DATA(D12_MARK, PTT4_FN),
1088 PINMUX_DATA(D11_MARK, PTT3_FN),
1089 PINMUX_DATA(D10_MARK, PTT2_FN),
1090 PINMUX_DATA(D9_MARK, PTT1_FN),
1091 PINMUX_DATA(D8_MARK, PTT0_FN),
1092
1093 /* PTU FN */
1094 PINMUX_DATA(DMAC_DACK0_MARK, PTU7_FN),
1095 PINMUX_DATA(DMAC_DREQ0_MARK, PTU6_FN),
1096
1097 PINMUX_DATA(FSIOASD_MARK, PSE1_0, PTU5_FN),
1098 PINMUX_DATA(FSIIABCK_MARK, PSE1_0, PTU4_FN),
1099 PINMUX_DATA(FSIIALRCK_MARK, PSE1_0, PTU3_FN),
1100 PINMUX_DATA(FSIOABCK_MARK, PSE1_0, PTU2_FN),
1101 PINMUX_DATA(FSIOALRCK_MARK, PSE1_0, PTU1_FN),
1102 PINMUX_DATA(CLKAUDIOAO_MARK, PSE0_0, PTU0_FN),
1103
1104 /* PTV FN */
1105 PINMUX_DATA(FSIIBSD_MARK, PSD7_0, PSD6_0, PTV7_FN),
1106 PINMUX_DATA(FSIOBSD_MARK, PSD7_0, PSD6_0, PTV6_FN),
1107 PINMUX_DATA(FSIIBBCK_MARK, PSC15_0, PSC14_0, PTV5_FN),
1108 PINMUX_DATA(FSIIBLRCK_MARK, PSC15_0, PSC14_0, PTV4_FN),
1109 PINMUX_DATA(FSIOBBCK_MARK, PSC15_0, PSC14_0, PTV3_FN),
1110 PINMUX_DATA(FSIOBLRCK_MARK, PSC15_0, PSC14_0, PTV2_FN),
1111 PINMUX_DATA(CLKAUDIOBO_MARK, PSE3_0, PSE2_0, PTV1_FN),
1112 PINMUX_DATA(FSIIASD_MARK, PSE10_0, PTV0_FN),
1113
1114 PINMUX_DATA(MSIOF1_SS2_MARK, PSD7_0, PSD6_1, PTV7_FN),
1115 PINMUX_DATA(MSIOF1_RSYNC_MARK, PSD7_1, PSD6_0, PTV7_FN),
1116 PINMUX_DATA(MSIOF1_SS1_MARK, PSD7_0, PSD6_1, PTV6_FN),
1117 PINMUX_DATA(MSIOF1_RSCK_MARK, PSD7_1, PSD6_0, PTV6_FN),
1118 PINMUX_DATA(MSIOF1_RXD_MARK, PSC15_0, PSC14_1, PTV5_FN),
1119 PINMUX_DATA(MSIOF1_TSYNC_MARK, PSC15_0, PSC14_1, PTV4_FN),
1120 PINMUX_DATA(MSIOF1_TSCK_MARK, PSC15_0, PSC14_1, PTV3_FN),
1121 PINMUX_DATA(MSIOF1_TXD_MARK, PSC15_0, PSC14_1, PTV2_FN),
1122 PINMUX_DATA(MSIOF1_MCK_MARK, PSE3_0, PSE2_1, PTV1_FN),
1123
1124 /* PTW FN */
1125 PINMUX_DATA(MMC_D7_MARK, PSE13_0, PSE12_0, PTW7_FN),
1126 PINMUX_DATA(MMC_D6_MARK, PSE13_0, PSE12_0, PTW6_FN),
1127 PINMUX_DATA(MMC_D5_MARK, PSE13_0, PSE12_0, PTW5_FN),
1128 PINMUX_DATA(MMC_D4_MARK, PSE13_0, PSE12_0, PTW4_FN),
1129 PINMUX_DATA(MMC_D3_MARK, PSA13_0, PTW3_FN),
1130 PINMUX_DATA(MMC_D2_MARK, PSA13_0, PTW2_FN),
1131 PINMUX_DATA(MMC_D1_MARK, PSA13_0, PTW1_FN),
1132 PINMUX_DATA(MMC_D0_MARK, PSA13_0, PTW0_FN),
1133
1134 PINMUX_DATA(SDHI1CD_MARK, PSE13_0, PSE12_1, PTW7_FN),
1135 PINMUX_DATA(SDHI1WP_MARK, PSE13_0, PSE12_1, PTW6_FN),
1136 PINMUX_DATA(SDHI1D3_MARK, PSE13_0, PSE12_1, PTW5_FN),
1137 PINMUX_DATA(SDHI1D2_MARK, PSE13_0, PSE12_1, PTW4_FN),
1138 PINMUX_DATA(SDHI1D1_MARK, PSA13_1, PTW3_FN),
1139 PINMUX_DATA(SDHI1D0_MARK, PSA13_1, PTW2_FN),
1140 PINMUX_DATA(SDHI1CMD_MARK, PSA13_1, PTW1_FN),
1141 PINMUX_DATA(SDHI1CLK_MARK, PSA13_1, PTW0_FN),
1142
1143 PINMUX_DATA(IODACK_MARK, PSE13_1, PSE12_0, PTW7_FN),
1144 PINMUX_DATA(IDERST_MARK, PSE13_1, PSE12_0, PTW6_FN),
1145 PINMUX_DATA(EXBUF_ENB_MARK, PSE13_1, PSE12_0, PTW5_FN),
1146 PINMUX_DATA(DIRECTION_MARK, PSE13_1, PSE12_0, PTW4_FN),
1147
1148 /* PTX FN */
1149 PINMUX_DATA(DMAC_DACK1_MARK, PSA12_0, PTX7_FN),
1150 PINMUX_DATA(DMAC_DREQ1_MARK, PSA12_0, PTX6_FN),
1151
1152 PINMUX_DATA(IRDA_OUT_MARK, PSA12_1, PTX7_FN),
1153 PINMUX_DATA(IRDA_IN_MARK, PSA12_1, PTX6_FN),
1154
1155 PINMUX_DATA(TSIF_TS0_SDAT_MARK, PSC0_0, PTX5_FN),
1156 PINMUX_DATA(TSIF_TS0_SCK_MARK, PSC1_0, PTX4_FN),
1157 PINMUX_DATA(TSIF_TS0_SDEN_MARK, PSC2_0, PTX3_FN),
1158 PINMUX_DATA(TSIF_TS0_SPSYNC_MARK, PTX2_FN),
1159
1160 PINMUX_DATA(LNKSTA_MARK, PSC0_1, PTX5_FN),
1161 PINMUX_DATA(MDIO_MARK, PSC1_1, PTX4_FN),
1162 PINMUX_DATA(MDC_MARK, PSC2_1, PTX3_FN),
1163
1164 PINMUX_DATA(MMC_CLK_MARK, PTX1_FN),
1165 PINMUX_DATA(MMC_CMD_MARK, PTX0_FN),
1166
1167 /* PTY FN */
1168 PINMUX_DATA(SDHI0CD_MARK, PTY7_FN),
1169 PINMUX_DATA(SDHI0WP_MARK, PTY6_FN),
1170 PINMUX_DATA(SDHI0D3_MARK, PTY5_FN),
1171 PINMUX_DATA(SDHI0D2_MARK, PTY4_FN),
1172 PINMUX_DATA(SDHI0D1_MARK, PTY3_FN),
1173 PINMUX_DATA(SDHI0D0_MARK, PTY2_FN),
1174 PINMUX_DATA(SDHI0CMD_MARK, PTY1_FN),
1175 PINMUX_DATA(SDHI0CLK_MARK, PTY0_FN),
1176
1177 /* PTZ FN */
1178 PINMUX_DATA(INTC_IRQ7_MARK, PSB10_0, PTZ7_FN),
1179 PINMUX_DATA(INTC_IRQ6_MARK, PSB11_0, PTZ6_FN),
1180 PINMUX_DATA(INTC_IRQ5_MARK, PSB12_0, PTZ5_FN),
1181 PINMUX_DATA(INTC_IRQ4_MARK, PSB13_0, PTZ4_FN),
1182 PINMUX_DATA(INTC_IRQ3_MARK, PSB14_0, PTZ3_FN),
1183 PINMUX_DATA(INTC_IRQ2_MARK, PTZ2_FN),
1184 PINMUX_DATA(INTC_IRQ1_MARK, PTZ1_FN),
1185 PINMUX_DATA(INTC_IRQ0_MARK, PTZ0_FN),
1186
1187 PINMUX_DATA(SCIF3_I_CTS_MARK, PSB10_1, PTZ7_FN),
1188 PINMUX_DATA(SCIF3_I_RTS_MARK, PSB11_1, PTZ6_FN),
1189 PINMUX_DATA(SCIF3_I_SCK_MARK, PSB12_1, PTZ5_FN),
1190 PINMUX_DATA(SCIF3_I_RXD_MARK, PSB13_1, PTZ4_FN),
1191 PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN),
1192};
1193
1194static struct pinmux_gpio pinmux_gpios[] = {
1195 /* PTA */
1196 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
1197 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
1198 PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
1199 PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
1200 PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
1201 PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
1202 PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
1203 PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
1204
1205 /* PTB */
1206 PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
1207 PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
1208 PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
1209 PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
1210 PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
1211 PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
1212 PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
1213 PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
1214
1215 /* PTC */
1216 PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
1217 PINMUX_GPIO(GPIO_PTC6, PTC6_DATA),
1218 PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
1219 PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
1220 PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
1221 PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
1222 PINMUX_GPIO(GPIO_PTC1, PTC1_DATA),
1223 PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
1224
1225 /* PTD */
1226 PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
1227 PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
1228 PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
1229 PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
1230 PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
1231 PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
1232 PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
1233 PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
1234
1235 /* PTE */
1236 PINMUX_GPIO(GPIO_PTE7, PTE7_DATA),
1237 PINMUX_GPIO(GPIO_PTE6, PTE6_DATA),
1238 PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
1239 PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
1240 PINMUX_GPIO(GPIO_PTE3, PTE3_DATA),
1241 PINMUX_GPIO(GPIO_PTE2, PTE2_DATA),
1242 PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
1243 PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
1244
1245 /* PTF */
1246 PINMUX_GPIO(GPIO_PTF7, PTF7_DATA),
1247 PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
1248 PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
1249 PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
1250 PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
1251 PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
1252 PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
1253 PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
1254
1255 /* PTG */
1256 PINMUX_GPIO(GPIO_PTG5, PTG5_DATA),
1257 PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
1258 PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
1259 PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
1260 PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
1261 PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
1262
1263 /* PTH */
1264 PINMUX_GPIO(GPIO_PTH7, PTH7_DATA),
1265 PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
1266 PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
1267 PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
1268 PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
1269 PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
1270 PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
1271 PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
1272
1273 /* PTJ */
1274 PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA),
1275 PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
1276 PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
1277 PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA),
1278 PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA),
1279 PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
1280 PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
1281
1282 /* PTK */
1283 PINMUX_GPIO(GPIO_PTK7, PTK7_DATA),
1284 PINMUX_GPIO(GPIO_PTK6, PTK6_DATA),
1285 PINMUX_GPIO(GPIO_PTK5, PTK5_DATA),
1286 PINMUX_GPIO(GPIO_PTK4, PTK4_DATA),
1287 PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
1288 PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
1289 PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
1290 PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
1291
1292 /* PTL */
1293 PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
1294 PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
1295 PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
1296 PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
1297 PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
1298 PINMUX_GPIO(GPIO_PTL2, PTL2_DATA),
1299 PINMUX_GPIO(GPIO_PTL1, PTL1_DATA),
1300 PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
1301
1302 /* PTM */
1303 PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
1304 PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
1305 PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
1306 PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
1307 PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
1308 PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
1309 PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
1310 PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
1311
1312 /* PTN */
1313 PINMUX_GPIO(GPIO_PTN7, PTN7_DATA),
1314 PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
1315 PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
1316 PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
1317 PINMUX_GPIO(GPIO_PTN3, PTN3_DATA),
1318 PINMUX_GPIO(GPIO_PTN2, PTN2_DATA),
1319 PINMUX_GPIO(GPIO_PTN1, PTN1_DATA),
1320 PINMUX_GPIO(GPIO_PTN0, PTN0_DATA),
1321
1322 /* PTQ */
1323 PINMUX_GPIO(GPIO_PTQ7, PTQ7_DATA),
1324 PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA),
1325 PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA),
1326 PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA),
1327 PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA),
1328 PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA),
1329 PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA),
1330 PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA),
1331
1332 /* PTR */
1333 PINMUX_GPIO(GPIO_PTR7, PTR7_DATA),
1334 PINMUX_GPIO(GPIO_PTR6, PTR6_DATA),
1335 PINMUX_GPIO(GPIO_PTR5, PTR5_DATA),
1336 PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
1337 PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
1338 PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
1339 PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
1340 PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
1341
1342 /* PTS */
1343 PINMUX_GPIO(GPIO_PTS6, PTS6_DATA),
1344 PINMUX_GPIO(GPIO_PTS5, PTS5_DATA),
1345 PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
1346 PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
1347 PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
1348 PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
1349 PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
1350
1351 /* PTT */
1352 PINMUX_GPIO(GPIO_PTT7, PTT7_DATA),
1353 PINMUX_GPIO(GPIO_PTT6, PTT6_DATA),
1354 PINMUX_GPIO(GPIO_PTT5, PTT5_DATA),
1355 PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
1356 PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
1357 PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
1358 PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
1359 PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
1360
1361 /* PTU */
1362 PINMUX_GPIO(GPIO_PTU7, PTU7_DATA),
1363 PINMUX_GPIO(GPIO_PTU6, PTU6_DATA),
1364 PINMUX_GPIO(GPIO_PTU5, PTU5_DATA),
1365 PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
1366 PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
1367 PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
1368 PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
1369 PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
1370
1371 /* PTV */
1372 PINMUX_GPIO(GPIO_PTV7, PTV7_DATA),
1373 PINMUX_GPIO(GPIO_PTV6, PTV6_DATA),
1374 PINMUX_GPIO(GPIO_PTV5, PTV5_DATA),
1375 PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
1376 PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
1377 PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
1378 PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
1379 PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
1380
1381 /* PTW */
1382 PINMUX_GPIO(GPIO_PTW7, PTW7_DATA),
1383 PINMUX_GPIO(GPIO_PTW6, PTW6_DATA),
1384 PINMUX_GPIO(GPIO_PTW5, PTW5_DATA),
1385 PINMUX_GPIO(GPIO_PTW4, PTW4_DATA),
1386 PINMUX_GPIO(GPIO_PTW3, PTW3_DATA),
1387 PINMUX_GPIO(GPIO_PTW2, PTW2_DATA),
1388 PINMUX_GPIO(GPIO_PTW1, PTW1_DATA),
1389 PINMUX_GPIO(GPIO_PTW0, PTW0_DATA),
1390
1391 /* PTX */
1392 PINMUX_GPIO(GPIO_PTX7, PTX7_DATA),
1393 PINMUX_GPIO(GPIO_PTX6, PTX6_DATA),
1394 PINMUX_GPIO(GPIO_PTX5, PTX5_DATA),
1395 PINMUX_GPIO(GPIO_PTX4, PTX4_DATA),
1396 PINMUX_GPIO(GPIO_PTX3, PTX3_DATA),
1397 PINMUX_GPIO(GPIO_PTX2, PTX2_DATA),
1398 PINMUX_GPIO(GPIO_PTX1, PTX1_DATA),
1399 PINMUX_GPIO(GPIO_PTX0, PTX0_DATA),
1400
1401 /* PTY */
1402 PINMUX_GPIO(GPIO_PTY7, PTY7_DATA),
1403 PINMUX_GPIO(GPIO_PTY6, PTY6_DATA),
1404 PINMUX_GPIO(GPIO_PTY5, PTY5_DATA),
1405 PINMUX_GPIO(GPIO_PTY4, PTY4_DATA),
1406 PINMUX_GPIO(GPIO_PTY3, PTY3_DATA),
1407 PINMUX_GPIO(GPIO_PTY2, PTY2_DATA),
1408 PINMUX_GPIO(GPIO_PTY1, PTY1_DATA),
1409 PINMUX_GPIO(GPIO_PTY0, PTY0_DATA),
1410
1411 /* PTZ */
1412 PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA),
1413 PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA),
1414 PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA),
1415 PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA),
1416 PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
1417 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
1418 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
1419 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
1420
1421 /* BSC */
1422 PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
1423 PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
1424 PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
1425 PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
1426 PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
1427 PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
1428 PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
1429 PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
1430 PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
1431 PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
1432 PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
1433 PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
1434 PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
1435 PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
1436 PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
1437 PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
1438 PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
1439 PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
1440 PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
1441 PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
1442 PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
1443 PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
1444 PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
1445 PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
1446 PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
1447 PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
1448 PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
1449 PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
1450 PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
1451 PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
1452 PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
1453 PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
1454 PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
1455 PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
1456 PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
1457 PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
1458 PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK),
1459 PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK),
1460 PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK),
1461 PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK),
1462 PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK),
1463 PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK),
1464 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
1465 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
1466 PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
1467
1468 /* KEYSC */
1469 PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK),
1470 PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK),
1471 PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK),
1472 PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK),
1473 PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK),
1474 PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK),
1475 PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK),
1476 PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK),
1477 PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK),
1478 PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK),
1479 PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK),
1480
1481 /* ATAPI */
1482 PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK),
1483 PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK),
1484 PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK),
1485 PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK),
1486 PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK),
1487 PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK),
1488 PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK),
1489 PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK),
1490 PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK),
1491 PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK),
1492 PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK),
1493 PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK),
1494 PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK),
1495 PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK),
1496 PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK),
1497 PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK),
1498 PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK),
1499 PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK),
1500 PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK),
1501 PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK),
1502 PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK),
1503 PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK),
1504 PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK),
1505 PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK),
1506 PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK),
1507 PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK),
1508 PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK),
1509 PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK),
1510 PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK),
1511 PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK),
1512
1513 /* TPU */
1514 PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK),
1515 PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK),
1516 PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK),
1517 PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK),
1518 PINMUX_GPIO(GPIO_FN_TPUTI3, TPUTI3_MARK),
1519 PINMUX_GPIO(GPIO_FN_TPUTI2, TPUTI2_MARK),
1520
1521 /* LCDC */
1522 PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK),
1523 PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK),
1524 PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK),
1525 PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK),
1526 PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK),
1527 PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK),
1528 PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK),
1529 PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK),
1530 PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK),
1531 PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK),
1532 PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK),
1533 PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK),
1534 PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK),
1535 PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK),
1536 PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK),
1537 PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK),
1538 PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK),
1539 PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK),
1540 PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK),
1541 PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK),
1542 PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK),
1543 PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK),
1544 PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK),
1545 PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK),
1546 PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK),
1547 PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK),
1548 PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK),
1549 PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK),
1550 PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK),
1551 PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK),
1552 PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK),
1553 PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK),
1554 PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK),
1555 PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK),
1556 PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK),
1557 PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK),
1558
1559 /* SCIF0 */
1560 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
1561 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
1562 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
1563
1564 /* SCIF1 */
1565 PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK),
1566 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
1567 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
1568
1569 /* SCIF2 */
1570 PINMUX_GPIO(GPIO_FN_SCIF2_L_TXD, SCIF2_L_TXD_MARK),
1571 PINMUX_GPIO(GPIO_FN_SCIF2_L_SCK, SCIF2_L_SCK_MARK),
1572 PINMUX_GPIO(GPIO_FN_SCIF2_L_RXD, SCIF2_L_RXD_MARK),
1573 PINMUX_GPIO(GPIO_FN_SCIF2_V_TXD, SCIF2_V_TXD_MARK),
1574 PINMUX_GPIO(GPIO_FN_SCIF2_V_SCK, SCIF2_V_SCK_MARK),
1575 PINMUX_GPIO(GPIO_FN_SCIF2_V_RXD, SCIF2_V_RXD_MARK),
1576
1577 /* SCIF3 */
1578 PINMUX_GPIO(GPIO_FN_SCIF3_V_SCK, SCIF3_V_SCK_MARK),
1579 PINMUX_GPIO(GPIO_FN_SCIF3_V_RXD, SCIF3_V_RXD_MARK),
1580 PINMUX_GPIO(GPIO_FN_SCIF3_V_TXD, SCIF3_V_TXD_MARK),
1581 PINMUX_GPIO(GPIO_FN_SCIF3_V_CTS, SCIF3_V_CTS_MARK),
1582 PINMUX_GPIO(GPIO_FN_SCIF3_V_RTS, SCIF3_V_RTS_MARK),
1583 PINMUX_GPIO(GPIO_FN_SCIF3_I_SCK, SCIF3_I_SCK_MARK),
1584 PINMUX_GPIO(GPIO_FN_SCIF3_I_RXD, SCIF3_I_RXD_MARK),
1585 PINMUX_GPIO(GPIO_FN_SCIF3_I_TXD, SCIF3_I_TXD_MARK),
1586 PINMUX_GPIO(GPIO_FN_SCIF3_I_CTS, SCIF3_I_CTS_MARK),
1587 PINMUX_GPIO(GPIO_FN_SCIF3_I_RTS, SCIF3_I_RTS_MARK),
1588
1589 /* SCIF4 */
1590 PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK),
1591 PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK),
1592 PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK),
1593
1594 /* SCIF5 */
1595 PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK),
1596 PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK),
1597 PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK),
1598
1599 /* FSI */
1600 PINMUX_GPIO(GPIO_FN_FSIMCKB, FSIMCKB_MARK),
1601 PINMUX_GPIO(GPIO_FN_FSIMCKA, FSIMCKA_MARK),
1602 PINMUX_GPIO(GPIO_FN_FSIOASD, FSIOASD_MARK),
1603 PINMUX_GPIO(GPIO_FN_FSIIABCK, FSIIABCK_MARK),
1604 PINMUX_GPIO(GPIO_FN_FSIIALRCK, FSIIALRCK_MARK),
1605 PINMUX_GPIO(GPIO_FN_FSIOABCK, FSIOABCK_MARK),
1606 PINMUX_GPIO(GPIO_FN_FSIOALRCK, FSIOALRCK_MARK),
1607 PINMUX_GPIO(GPIO_FN_CLKAUDIOAO, CLKAUDIOAO_MARK),
1608 PINMUX_GPIO(GPIO_FN_FSIIBSD, FSIIBSD_MARK),
1609 PINMUX_GPIO(GPIO_FN_FSIOBSD, FSIOBSD_MARK),
1610 PINMUX_GPIO(GPIO_FN_FSIIBBCK, FSIIBBCK_MARK),
1611 PINMUX_GPIO(GPIO_FN_FSIIBLRCK, FSIIBLRCK_MARK),
1612 PINMUX_GPIO(GPIO_FN_FSIOBBCK, FSIOBBCK_MARK),
1613 PINMUX_GPIO(GPIO_FN_FSIOBLRCK, FSIOBLRCK_MARK),
1614 PINMUX_GPIO(GPIO_FN_CLKAUDIOBO, CLKAUDIOBO_MARK),
1615 PINMUX_GPIO(GPIO_FN_FSIIASD, FSIIASD_MARK),
1616
1617 /* AUD */
1618 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
1619 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
1620 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
1621 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
1622 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
1623 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
1624
1625 /* VIO */
1626 PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK),
1627
1628 /* VIO0 */
1629 PINMUX_GPIO(GPIO_FN_VIO0_D15, VIO0_D15_MARK),
1630 PINMUX_GPIO(GPIO_FN_VIO0_D14, VIO0_D14_MARK),
1631 PINMUX_GPIO(GPIO_FN_VIO0_D13, VIO0_D13_MARK),
1632 PINMUX_GPIO(GPIO_FN_VIO0_D12, VIO0_D12_MARK),
1633 PINMUX_GPIO(GPIO_FN_VIO0_D11, VIO0_D11_MARK),
1634 PINMUX_GPIO(GPIO_FN_VIO0_D10, VIO0_D10_MARK),
1635 PINMUX_GPIO(GPIO_FN_VIO0_D9, VIO0_D9_MARK),
1636 PINMUX_GPIO(GPIO_FN_VIO0_D8, VIO0_D8_MARK),
1637 PINMUX_GPIO(GPIO_FN_VIO0_D7, VIO0_D7_MARK),
1638 PINMUX_GPIO(GPIO_FN_VIO0_D6, VIO0_D6_MARK),
1639 PINMUX_GPIO(GPIO_FN_VIO0_D5, VIO0_D5_MARK),
1640 PINMUX_GPIO(GPIO_FN_VIO0_D4, VIO0_D4_MARK),
1641 PINMUX_GPIO(GPIO_FN_VIO0_D3, VIO0_D3_MARK),
1642 PINMUX_GPIO(GPIO_FN_VIO0_D2, VIO0_D2_MARK),
1643 PINMUX_GPIO(GPIO_FN_VIO0_D1, VIO0_D1_MARK),
1644 PINMUX_GPIO(GPIO_FN_VIO0_D0, VIO0_D0_MARK),
1645 PINMUX_GPIO(GPIO_FN_VIO0_VD, VIO0_VD_MARK),
1646 PINMUX_GPIO(GPIO_FN_VIO0_CLK, VIO0_CLK_MARK),
1647 PINMUX_GPIO(GPIO_FN_VIO0_FLD, VIO0_FLD_MARK),
1648 PINMUX_GPIO(GPIO_FN_VIO0_HD, VIO0_HD_MARK),
1649
1650 /* VIO1 */
1651 PINMUX_GPIO(GPIO_FN_VIO1_D7, VIO1_D7_MARK),
1652 PINMUX_GPIO(GPIO_FN_VIO1_D6, VIO1_D6_MARK),
1653 PINMUX_GPIO(GPIO_FN_VIO1_D5, VIO1_D5_MARK),
1654 PINMUX_GPIO(GPIO_FN_VIO1_D4, VIO1_D4_MARK),
1655 PINMUX_GPIO(GPIO_FN_VIO1_D3, VIO1_D3_MARK),
1656 PINMUX_GPIO(GPIO_FN_VIO1_D2, VIO1_D2_MARK),
1657 PINMUX_GPIO(GPIO_FN_VIO1_D1, VIO1_D1_MARK),
1658 PINMUX_GPIO(GPIO_FN_VIO1_D0, VIO1_D0_MARK),
1659 PINMUX_GPIO(GPIO_FN_VIO1_FLD, VIO1_FLD_MARK),
1660 PINMUX_GPIO(GPIO_FN_VIO1_HD, VIO1_HD_MARK),
1661 PINMUX_GPIO(GPIO_FN_VIO1_VD, VIO1_VD_MARK),
1662 PINMUX_GPIO(GPIO_FN_VIO1_CLK, VIO1_CLK_MARK),
1663
1664 /* Eth */
1665 PINMUX_GPIO(GPIO_FN_RMII_RXD0, RMII_RXD0_MARK),
1666 PINMUX_GPIO(GPIO_FN_RMII_RXD1, RMII_RXD1_MARK),
1667 PINMUX_GPIO(GPIO_FN_RMII_TXD0, RMII_TXD0_MARK),
1668 PINMUX_GPIO(GPIO_FN_RMII_TXD1, RMII_TXD1_MARK),
1669 PINMUX_GPIO(GPIO_FN_RMII_REF_CLK, RMII_REF_CLK_MARK),
1670 PINMUX_GPIO(GPIO_FN_RMII_TX_EN, RMII_TX_EN_MARK),
1671 PINMUX_GPIO(GPIO_FN_RMII_RX_ER, RMII_RX_ER_MARK),
1672 PINMUX_GPIO(GPIO_FN_RMII_CRS_DV, RMII_CRS_DV_MARK),
1673 PINMUX_GPIO(GPIO_FN_LNKSTA, LNKSTA_MARK),
1674 PINMUX_GPIO(GPIO_FN_MDIO, MDIO_MARK),
1675 PINMUX_GPIO(GPIO_FN_MDC, MDC_MARK),
1676
1677 /* System */
1678 PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK),
1679 PINMUX_GPIO(GPIO_FN_STATUS2, STATUS2_MARK),
1680 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
1681
1682 /* VOU */
1683 PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK),
1684 PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK),
1685 PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK),
1686 PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK),
1687 PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK),
1688 PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK),
1689 PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK),
1690 PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK),
1691 PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK),
1692 PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK),
1693 PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK),
1694 PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK),
1695 PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK),
1696 PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK),
1697 PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK),
1698 PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK),
1699 PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK),
1700 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
1701 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
1702 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
1703
1704 /* MSIOF0 */
1705 PINMUX_GPIO(GPIO_FN_MSIOF0_RXD, MSIOF0_RXD_MARK),
1706 PINMUX_GPIO(GPIO_FN_MSIOF0_TXD, MSIOF0_TXD_MARK),
1707 PINMUX_GPIO(GPIO_FN_MSIOF0_MCK, MSIOF0_MCK_MARK),
1708 PINMUX_GPIO(GPIO_FN_MSIOF0_TSCK, MSIOF0_TSCK_MARK),
1709 PINMUX_GPIO(GPIO_FN_MSIOF0_SS1, MSIOF0_SS1_MARK),
1710 PINMUX_GPIO(GPIO_FN_MSIOF0_SS2, MSIOF0_SS2_MARK),
1711 PINMUX_GPIO(GPIO_FN_MSIOF0_TSYNC, MSIOF0_TSYNC_MARK),
1712 PINMUX_GPIO(GPIO_FN_MSIOF0_RSCK, MSIOF0_RSCK_MARK),
1713 PINMUX_GPIO(GPIO_FN_MSIOF0_RSYNC, MSIOF0_RSYNC_MARK),
1714
1715 /* MSIOF1 */
1716 PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK),
1717 PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK),
1718 PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK),
1719 PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK),
1720 PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK),
1721 PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK),
1722 PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK),
1723 PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK),
1724 PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK),
1725
1726 /* DMAC */
1727 PINMUX_GPIO(GPIO_FN_DMAC_DACK0, DMAC_DACK0_MARK),
1728 PINMUX_GPIO(GPIO_FN_DMAC_DREQ0, DMAC_DREQ0_MARK),
1729 PINMUX_GPIO(GPIO_FN_DMAC_DACK1, DMAC_DACK1_MARK),
1730 PINMUX_GPIO(GPIO_FN_DMAC_DREQ1, DMAC_DREQ1_MARK),
1731
1732 /* SDHI0 */
1733 PINMUX_GPIO(GPIO_FN_SDHI0CD, SDHI0CD_MARK),
1734 PINMUX_GPIO(GPIO_FN_SDHI0WP, SDHI0WP_MARK),
1735 PINMUX_GPIO(GPIO_FN_SDHI0CMD, SDHI0CMD_MARK),
1736 PINMUX_GPIO(GPIO_FN_SDHI0CLK, SDHI0CLK_MARK),
1737 PINMUX_GPIO(GPIO_FN_SDHI0D3, SDHI0D3_MARK),
1738 PINMUX_GPIO(GPIO_FN_SDHI0D2, SDHI0D2_MARK),
1739 PINMUX_GPIO(GPIO_FN_SDHI0D1, SDHI0D1_MARK),
1740 PINMUX_GPIO(GPIO_FN_SDHI0D0, SDHI0D0_MARK),
1741
1742 /* SDHI1 */
1743 PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK),
1744 PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK),
1745 PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK),
1746 PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK),
1747 PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK),
1748 PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK),
1749 PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK),
1750 PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK),
1751
1752 /* MMC */
1753 PINMUX_GPIO(GPIO_FN_MMC_D7, MMC_D7_MARK),
1754 PINMUX_GPIO(GPIO_FN_MMC_D6, MMC_D6_MARK),
1755 PINMUX_GPIO(GPIO_FN_MMC_D5, MMC_D5_MARK),
1756 PINMUX_GPIO(GPIO_FN_MMC_D4, MMC_D4_MARK),
1757 PINMUX_GPIO(GPIO_FN_MMC_D3, MMC_D3_MARK),
1758 PINMUX_GPIO(GPIO_FN_MMC_D2, MMC_D2_MARK),
1759 PINMUX_GPIO(GPIO_FN_MMC_D1, MMC_D1_MARK),
1760 PINMUX_GPIO(GPIO_FN_MMC_D0, MMC_D0_MARK),
1761 PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK),
1762 PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK),
1763
1764 /* IrDA */
1765 PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK),
1766 PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK),
1767
1768 /* TSIF */
1769 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDAT, TSIF_TS0_SDAT_MARK),
1770 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SCK, TSIF_TS0_SCK_MARK),
1771 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDEN, TSIF_TS0_SDEN_MARK),
1772 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SPSYNC, TSIF_TS0_SPSYNC_MARK),
1773
1774 /* IRQ */
1775 PINMUX_GPIO(GPIO_FN_INTC_IRQ7, INTC_IRQ7_MARK),
1776 PINMUX_GPIO(GPIO_FN_INTC_IRQ6, INTC_IRQ6_MARK),
1777 PINMUX_GPIO(GPIO_FN_INTC_IRQ5, INTC_IRQ5_MARK),
1778 PINMUX_GPIO(GPIO_FN_INTC_IRQ4, INTC_IRQ4_MARK),
1779 PINMUX_GPIO(GPIO_FN_INTC_IRQ3, INTC_IRQ3_MARK),
1780 PINMUX_GPIO(GPIO_FN_INTC_IRQ2, INTC_IRQ2_MARK),
1781 PINMUX_GPIO(GPIO_FN_INTC_IRQ1, INTC_IRQ1_MARK),
1782 PINMUX_GPIO(GPIO_FN_INTC_IRQ0, INTC_IRQ0_MARK),
1783 };
1784
1785static struct pinmux_cfg_reg pinmux_config_regs[] = {
1786 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
1787 PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
1788 PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
1789 PTA5_FN, PTA5_OUT, PTA5_IN_PU, PTA5_IN,
1790 PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN,
1791 PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN,
1792 PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN,
1793 PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN,
1794 PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN }
1795 },
1796 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
1797 PTB7_FN, PTB7_OUT, PTB7_IN_PU, PTB7_IN,
1798 PTB6_FN, PTB6_OUT, PTB6_IN_PU, PTB6_IN,
1799 PTB5_FN, PTB5_OUT, PTB5_IN_PU, PTB5_IN,
1800 PTB4_FN, PTB4_OUT, PTB4_IN_PU, PTB4_IN,
1801 PTB3_FN, PTB3_OUT, PTB3_IN_PU, PTB3_IN,
1802 PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN,
1803 PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN,
1804 PTB0_FN, PTB0_OUT, PTB0_IN_PU, PTB0_IN }
1805 },
1806 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
1807 PTC7_FN, PTC7_OUT, PTC7_IN_PU, PTC7_IN,
1808 PTC6_FN, PTC6_OUT, PTC6_IN_PU, PTC6_IN,
1809 PTC5_FN, PTC5_OUT, PTC5_IN_PU, PTC5_IN,
1810 PTC4_FN, PTC4_OUT, PTC4_IN_PU, PTC4_IN,
1811 PTC3_FN, PTC3_OUT, PTC3_IN_PU, PTC3_IN,
1812 PTC2_FN, PTC2_OUT, PTC2_IN_PU, PTC2_IN,
1813 PTC1_FN, PTC1_OUT, PTC1_IN_PU, PTC1_IN,
1814 PTC0_FN, PTC0_OUT, PTC0_IN_PU, PTC0_IN }
1815 },
1816 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
1817 PTD7_FN, PTD7_OUT, PTD7_IN_PU, PTD7_IN,
1818 PTD6_FN, PTD6_OUT, PTD6_IN_PU, PTD6_IN,
1819 PTD5_FN, PTD5_OUT, PTD5_IN_PU, PTD5_IN,
1820 PTD4_FN, PTD4_OUT, PTD4_IN_PU, PTD4_IN,
1821 PTD3_FN, PTD3_OUT, PTD3_IN_PU, PTD3_IN,
1822 PTD2_FN, PTD2_OUT, PTD2_IN_PU, PTD2_IN,
1823 PTD1_FN, PTD1_OUT, PTD1_IN_PU, PTD1_IN,
1824 PTD0_FN, PTD0_OUT, PTD0_IN_PU, PTD0_IN }
1825 },
1826 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
1827 PTE7_FN, PTE7_OUT, PTE7_IN_PU, PTE7_IN,
1828 PTE6_FN, PTE6_OUT, PTE6_IN_PU, PTE6_IN,
1829 PTE5_FN, PTE5_OUT, PTE5_IN_PU, PTE5_IN,
1830 PTE4_FN, PTE4_OUT, PTE4_IN_PU, PTE4_IN,
1831 PTE3_FN, PTE3_OUT, PTE3_IN_PU, PTE3_IN,
1832 PTE2_FN, PTE2_OUT, PTE2_IN_PU, PTE2_IN,
1833 PTE1_FN, PTE1_OUT, PTE1_IN_PU, PTE1_IN,
1834 PTE0_FN, PTE0_OUT, PTE0_IN_PU, PTE0_IN }
1835 },
1836 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
1837 PTF7_FN, PTF7_OUT, PTF7_IN_PU, PTF7_IN,
1838 PTF6_FN, PTF6_OUT, PTF6_IN_PU, PTF6_IN,
1839 PTF5_FN, PTF5_OUT, PTF5_IN_PU, PTF5_IN,
1840 PTF4_FN, PTF4_OUT, PTF4_IN_PU, PTF4_IN,
1841 PTF3_FN, PTF3_OUT, PTF3_IN_PU, PTF3_IN,
1842 PTF2_FN, PTF2_OUT, PTF2_IN_PU, PTF2_IN,
1843 PTF1_FN, PTF1_OUT, PTF1_IN_PU, PTF1_IN,
1844 PTF0_FN, PTF0_OUT, PTF0_IN_PU, PTF0_IN }
1845 },
1846 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
1847 0, 0, 0, 0,
1848 0, 0, 0, 0,
1849 PTG5_FN, PTG5_OUT, 0, 0,
1850 PTG4_FN, PTG4_OUT, 0, 0,
1851 PTG3_FN, PTG3_OUT, 0, 0,
1852 PTG2_FN, PTG2_OUT, 0, 0,
1853 PTG1_FN, PTG1_OUT, 0, 0,
1854 PTG0_FN, PTG0_OUT, 0, 0 }
1855 },
1856 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
1857 PTH7_FN, PTH7_OUT, PTH7_IN_PU, PTH7_IN,
1858 PTH6_FN, PTH6_OUT, PTH6_IN_PU, PTH6_IN,
1859 PTH5_FN, PTH5_OUT, PTH5_IN_PU, PTH5_IN,
1860 PTH4_FN, PTH4_OUT, PTH4_IN_PU, PTH4_IN,
1861 PTH3_FN, PTH3_OUT, PTH3_IN_PU, PTH3_IN,
1862 PTH2_FN, PTH2_OUT, PTH2_IN_PU, PTH2_IN,
1863 PTH1_FN, PTH1_OUT, PTH1_IN_PU, PTH1_IN,
1864 PTH0_FN, PTH0_OUT, PTH0_IN_PU, PTH0_IN }
1865 },
1866 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
1867 PTJ7_FN, PTJ7_OUT, 0, 0,
1868 PTJ6_FN, PTJ6_OUT, 0, 0,
1869 PTJ5_FN, PTJ5_OUT, 0, 0,
1870 0, 0, 0, 0,
1871 PTJ3_FN, PTJ3_OUT, PTJ3_IN_PU, PTJ3_IN,
1872 PTJ2_FN, PTJ2_OUT, PTJ2_IN_PU, PTJ2_IN,
1873 PTJ1_FN, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN,
1874 PTJ0_FN, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN }
1875 },
1876 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
1877 PTK7_FN, PTK7_OUT, PTK7_IN_PU, PTK7_IN,
1878 PTK6_FN, PTK6_OUT, PTK6_IN_PU, PTK6_IN,
1879 PTK5_FN, PTK5_OUT, PTK5_IN_PU, PTK5_IN,
1880 PTK4_FN, PTK4_OUT, PTK4_IN_PU, PTK4_IN,
1881 PTK3_FN, PTK3_OUT, PTK3_IN_PU, PTK3_IN,
1882 PTK2_FN, PTK2_OUT, PTK2_IN_PU, PTK2_IN,
1883 PTK1_FN, PTK1_OUT, PTK1_IN_PU, PTK1_IN,
1884 PTK0_FN, PTK0_OUT, PTK0_IN_PU, PTK0_IN }
1885 },
1886 { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
1887 PTL7_FN, PTL7_OUT, PTL7_IN_PU, PTL7_IN,
1888 PTL6_FN, PTL6_OUT, PTL6_IN_PU, PTL6_IN,
1889 PTL5_FN, PTL5_OUT, PTL5_IN_PU, PTL5_IN,
1890 PTL4_FN, PTL4_OUT, PTL4_IN_PU, PTL4_IN,
1891 PTL3_FN, PTL3_OUT, PTL3_IN_PU, PTL3_IN,
1892 PTL2_FN, PTL2_OUT, PTL2_IN_PU, PTL2_IN,
1893 PTL1_FN, PTL1_OUT, PTL1_IN_PU, PTL1_IN,
1894 PTL0_FN, PTL0_OUT, PTL0_IN_PU, PTL0_IN }
1895 },
1896 { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
1897 PTM7_FN, PTM7_OUT, PTM7_IN_PU, PTM7_IN,
1898 PTM6_FN, PTM6_OUT, PTM6_IN_PU, PTM6_IN,
1899 PTM5_FN, PTM5_OUT, PTM5_IN_PU, PTM5_IN,
1900 PTM4_FN, PTM4_OUT, PTM4_IN_PU, PTM4_IN,
1901 PTM3_FN, PTM3_OUT, PTM3_IN_PU, PTM3_IN,
1902 PTM2_FN, PTM2_OUT, PTM2_IN_PU, PTM2_IN,
1903 PTM1_FN, PTM1_OUT, PTM1_IN_PU, PTM1_IN,
1904 PTM0_FN, PTM0_OUT, PTM0_IN_PU, PTM0_IN }
1905 },
1906 { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) {
1907 PTN7_FN, PTN7_OUT, PTN7_IN_PU, PTN7_IN,
1908 PTN6_FN, PTN6_OUT, PTN6_IN_PU, PTN6_IN,
1909 PTN5_FN, PTN5_OUT, PTN5_IN_PU, PTN5_IN,
1910 PTN4_FN, PTN4_OUT, PTN4_IN_PU, PTN4_IN,
1911 PTN3_FN, PTN3_OUT, PTN3_IN_PU, PTN3_IN,
1912 PTN2_FN, PTN2_OUT, PTN2_IN_PU, PTN2_IN,
1913 PTN1_FN, PTN1_OUT, PTN1_IN_PU, PTN1_IN,
1914 PTN0_FN, PTN0_OUT, PTN0_IN_PU, PTN0_IN }
1915 },
1916 { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) {
1917 PTQ7_FN, PTQ7_OUT, PTQ7_IN_PU, PTQ7_IN,
1918 PTQ6_FN, PTQ6_OUT, PTQ6_IN_PU, PTQ6_IN,
1919 PTQ5_FN, PTQ5_OUT, PTQ5_IN_PU, PTQ5_IN,
1920 PTQ4_FN, PTQ4_OUT, PTQ4_IN_PU, PTQ4_IN,
1921 PTQ3_FN, PTQ3_OUT, PTQ3_IN_PU, PTQ3_IN,
1922 PTQ2_FN, PTQ2_OUT, PTQ2_IN_PU, PTQ2_IN,
1923 PTQ1_FN, PTQ1_OUT, PTQ1_IN_PU, PTQ1_IN,
1924 PTQ0_FN, PTQ0_OUT, PTQ0_IN_PU, PTQ0_IN }
1925 },
1926 { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) {
1927 PTR7_FN, PTR7_OUT, PTR7_IN_PU, PTR7_IN,
1928 PTR6_FN, PTR6_OUT, PTR6_IN_PU, PTR6_IN,
1929 PTR5_FN, PTR5_OUT, PTR5_IN_PU, PTR5_IN,
1930 PTR4_FN, PTR4_OUT, PTR4_IN_PU, PTR4_IN,
1931 PTR3_FN, 0, PTR3_IN_PU, PTR3_IN,
1932 PTR2_FN, 0, PTR2_IN_PU, PTR2_IN,
1933 PTR1_FN, PTR1_OUT, PTR1_IN_PU, PTR1_IN,
1934 PTR0_FN, PTR0_OUT, PTR0_IN_PU, PTR0_IN }
1935 },
1936 { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) {
1937 0, 0, 0, 0,
1938 PTS6_FN, PTS6_OUT, PTS6_IN_PU, PTS6_IN,
1939 PTS5_FN, PTS5_OUT, PTS5_IN_PU, PTS5_IN,
1940 PTS4_FN, PTS4_OUT, PTS4_IN_PU, PTS4_IN,
1941 PTS3_FN, PTS3_OUT, PTS3_IN_PU, PTS3_IN,
1942 PTS2_FN, PTS2_OUT, PTS2_IN_PU, PTS2_IN,
1943 PTS1_FN, PTS1_OUT, PTS1_IN_PU, PTS1_IN,
1944 PTS0_FN, PTS0_OUT, PTS0_IN_PU, PTS0_IN }
1945 },
1946 { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) {
1947 PTT7_FN, PTT7_OUT, PTT7_IN_PU, PTT7_IN,
1948 PTT6_FN, PTT6_OUT, PTT6_IN_PU, PTT6_IN,
1949 PTT5_FN, PTT5_OUT, PTT5_IN_PU, PTT5_IN,
1950 PTT4_FN, PTT4_OUT, PTT4_IN_PU, PTT4_IN,
1951 PTT3_FN, PTT3_OUT, PTT3_IN_PU, PTT3_IN,
1952 PTT2_FN, PTT2_OUT, PTT2_IN_PU, PTT2_IN,
1953 PTT1_FN, PTT1_OUT, PTT1_IN_PU, PTT1_IN,
1954 PTT0_FN, PTT0_OUT, PTT0_IN_PU, PTT0_IN }
1955 },
1956 { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) {
1957 PTU7_FN, PTU7_OUT, PTU7_IN_PU, PTU7_IN,
1958 PTU6_FN, PTU6_OUT, PTU6_IN_PU, PTU6_IN,
1959 PTU5_FN, PTU5_OUT, PTU5_IN_PU, PTU5_IN,
1960 PTU4_FN, PTU4_OUT, PTU4_IN_PU, PTU4_IN,
1961 PTU3_FN, PTU3_OUT, PTU3_IN_PU, PTU3_IN,
1962 PTU2_FN, PTU2_OUT, PTU2_IN_PU, PTU2_IN,
1963 PTU1_FN, PTU1_OUT, PTU1_IN_PU, PTU1_IN,
1964 PTU0_FN, PTU0_OUT, PTU0_IN_PU, PTU0_IN }
1965 },
1966 { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) {
1967 PTV7_FN, PTV7_OUT, PTV7_IN_PU, PTV7_IN,
1968 PTV6_FN, PTV6_OUT, PTV6_IN_PU, PTV6_IN,
1969 PTV5_FN, PTV5_OUT, PTV5_IN_PU, PTV5_IN,
1970 PTV4_FN, PTV4_OUT, PTV4_IN_PU, PTV4_IN,
1971 PTV3_FN, PTV3_OUT, PTV3_IN_PU, PTV3_IN,
1972 PTV2_FN, PTV2_OUT, PTV2_IN_PU, PTV2_IN,
1973 PTV1_FN, PTV1_OUT, PTV1_IN_PU, PTV1_IN,
1974 PTV0_FN, PTV0_OUT, PTV0_IN_PU, PTV0_IN }
1975 },
1976 { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) {
1977 PTW7_FN, PTW7_OUT, PTW7_IN_PU, PTW7_IN,
1978 PTW6_FN, PTW6_OUT, PTW6_IN_PU, PTW6_IN,
1979 PTW5_FN, PTW5_OUT, PTW5_IN_PU, PTW5_IN,
1980 PTW4_FN, PTW4_OUT, PTW4_IN_PU, PTW4_IN,
1981 PTW3_FN, PTW3_OUT, PTW3_IN_PU, PTW3_IN,
1982 PTW2_FN, PTW2_OUT, PTW2_IN_PU, PTW2_IN,
1983 PTW1_FN, PTW1_OUT, PTW1_IN_PU, PTW1_IN,
1984 PTW0_FN, PTW0_OUT, PTW0_IN_PU, PTW0_IN }
1985 },
1986 { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) {
1987 PTX7_FN, PTX7_OUT, PTX7_IN_PU, PTX7_IN,
1988 PTX6_FN, PTX6_OUT, PTX6_IN_PU, PTX6_IN,
1989 PTX5_FN, PTX5_OUT, PTX5_IN_PU, PTX5_IN,
1990 PTX4_FN, PTX4_OUT, PTX4_IN_PU, PTX4_IN,
1991 PTX3_FN, PTX3_OUT, PTX3_IN_PU, PTX3_IN,
1992 PTX2_FN, PTX2_OUT, PTX2_IN_PU, PTX2_IN,
1993 PTX1_FN, PTX1_OUT, PTX1_IN_PU, PTX1_IN,
1994 PTX0_FN, PTX0_OUT, PTX0_IN_PU, PTX0_IN }
1995 },
1996 { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) {
1997 PTY7_FN, PTY7_OUT, PTY7_IN_PU, PTY7_IN,
1998 PTY6_FN, PTY6_OUT, PTY6_IN_PU, PTY6_IN,
1999 PTY5_FN, PTY5_OUT, PTY5_IN_PU, PTY5_IN,
2000 PTY4_FN, PTY4_OUT, PTY4_IN_PU, PTY4_IN,
2001 PTY3_FN, PTY3_OUT, PTY3_IN_PU, PTY3_IN,
2002 PTY2_FN, PTY2_OUT, PTY2_IN_PU, PTY2_IN,
2003 PTY1_FN, PTY1_OUT, PTY1_IN_PU, PTY1_IN,
2004 PTY0_FN, PTY0_OUT, PTY0_IN_PU, PTY0_IN }
2005 },
2006 { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) {
2007 PTZ7_FN, PTZ7_OUT, PTZ7_IN_PU, PTZ7_IN,
2008 PTZ6_FN, PTZ6_OUT, PTZ6_IN_PU, PTZ6_IN,
2009 PTZ5_FN, PTZ5_OUT, PTZ5_IN_PU, PTZ5_IN,
2010 PTZ4_FN, PTZ4_OUT, PTZ4_IN_PU, PTZ4_IN,
2011 PTZ3_FN, PTZ3_OUT, PTZ3_IN_PU, PTZ3_IN,
2012 PTZ2_FN, PTZ2_OUT, PTZ2_IN_PU, PTZ2_IN,
2013 PTZ1_FN, PTZ1_OUT, PTZ1_IN_PU, PTZ1_IN,
2014 PTZ0_FN, PTZ0_OUT, PTZ0_IN_PU, PTZ0_IN }
2015 },
2016 { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) {
2017 PSA15_0, PSA15_1,
2018 PSA14_0, PSA14_1,
2019 PSA13_0, PSA13_1,
2020 PSA12_0, PSA12_1,
2021 0, 0,
2022 PSA10_0, PSA10_1,
2023 PSA9_0, PSA9_1,
2024 PSA8_0, PSA8_1,
2025 PSA7_0, PSA7_1,
2026 PSA6_0, PSA6_1,
2027 PSA5_0, PSA5_1,
2028 0, 0,
2029 PSA3_0, PSA3_1,
2030 PSA2_0, PSA2_1,
2031 PSA1_0, PSA1_1,
2032 PSA0_0, PSA0_1}
2033 },
2034 { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1) {
2035 0, 0,
2036 PSB14_0, PSB14_1,
2037 PSB13_0, PSB13_1,
2038 PSB12_0, PSB12_1,
2039 PSB11_0, PSB11_1,
2040 PSB10_0, PSB10_1,
2041 PSB9_0, PSB9_1,
2042 PSB8_0, PSB8_1,
2043 PSB7_0, PSB7_1,
2044 PSB6_0, PSB6_1,
2045 PSB5_0, PSB5_1,
2046 PSB4_0, PSB4_1,
2047 PSB3_0, PSB3_1,
2048 PSB2_0, PSB2_1,
2049 PSB1_0, PSB1_1,
2050 PSB0_0, PSB0_1}
2051 },
2052 { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1) {
2053 PSC15_0, PSC15_1,
2054 PSC14_0, PSC14_1,
2055 PSC13_0, PSC13_1,
2056 PSC12_0, PSC12_1,
2057 PSC11_0, PSC11_1,
2058 PSC10_0, PSC10_1,
2059 PSC9_0, PSC9_1,
2060 PSC8_0, PSC8_1,
2061 PSC7_0, PSC7_1,
2062 PSC6_0, PSC6_1,
2063 PSC5_0, PSC5_1,
2064 PSC4_0, PSC4_1,
2065 0, 0,
2066 PSC2_0, PSC2_1,
2067 PSC1_0, PSC1_1,
2068 PSC0_0, PSC0_1}
2069 },
2070 { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1) {
2071 PSD15_0, PSD15_1,
2072 PSD14_0, PSD14_1,
2073 PSD13_0, PSD13_1,
2074 PSD12_0, PSD12_1,
2075 PSD11_0, PSD11_1,
2076 PSD10_0, PSD10_1,
2077 PSD9_0, PSD9_1,
2078 PSD8_0, PSD8_1,
2079 PSD7_0, PSD7_1,
2080 PSD6_0, PSD6_1,
2081 PSD5_0, PSD5_1,
2082 PSD4_0, PSD4_1,
2083 PSD3_0, PSD3_1,
2084 PSD2_0, PSD2_1,
2085 PSD1_0, PSD1_1,
2086 PSD0_0, PSD0_1}
2087 },
2088 { PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1) {
2089 PSE15_0, PSE15_1,
2090 PSE14_0, PSE14_1,
2091 PSE13_0, PSE13_1,
2092 PSE12_0, PSE12_1,
2093 PSE11_0, PSE11_1,
2094 PSE10_0, PSE10_1,
2095 PSE9_0, PSE9_1,
2096 PSE8_0, PSE8_1,
2097 PSE7_0, PSE7_1,
2098 PSE6_0, PSE6_1,
2099 PSE5_0, PSE5_1,
2100 PSE4_0, PSE4_1,
2101 PSE3_0, PSE3_1,
2102 PSE2_0, PSE2_1,
2103 PSE1_0, PSE1_1,
2104 PSE0_0, PSE0_1}
2105 },
2106 {}
2107};
2108
2109static struct pinmux_data_reg pinmux_data_regs[] = {
2110 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
2111 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
2112 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
2113 },
2114 { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) {
2115 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
2116 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
2117 },
2118 { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) {
2119 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
2120 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
2121 },
2122 { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
2123 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
2124 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
2125 },
2126 { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) {
2127 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
2128 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
2129 },
2130 { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) {
2131 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
2132 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
2133 },
2134 { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) {
2135 0, 0, PTG5_DATA, PTG4_DATA,
2136 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
2137 },
2138 { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) {
2139 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
2140 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
2141 },
2142 { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) {
2143 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0,
2144 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
2145 },
2146 { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) {
2147 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
2148 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
2149 },
2150 { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) {
2151 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
2152 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
2153 },
2154 { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) {
2155 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
2156 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
2157 },
2158 { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) {
2159 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
2160 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
2161 },
2162 { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) {
2163 PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
2164 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
2165 },
2166 { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) {
2167 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
2168 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
2169 },
2170 { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) {
2171 0, PTS6_DATA, PTS5_DATA, PTS4_DATA,
2172 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
2173 },
2174 { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) {
2175 PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
2176 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
2177 },
2178 { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) {
2179 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
2180 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
2181 },
2182 { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) {
2183 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
2184 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
2185 },
2186 { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) {
2187 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
2188 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
2189 },
2190 { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) {
2191 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
2192 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
2193 },
2194 { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) {
2195 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
2196 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
2197 },
2198 { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) {
2199 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
2200 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
2201 },
2202 { },
2203};
2204
2205static struct pinmux_info sh7724_pinmux_info = {
2206 .name = "sh7724_pfc",
2207 .reserved_id = PINMUX_RESERVED,
2208 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2209 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2210 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
2211 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2212 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2213 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2214
2215 .first_gpio = GPIO_PTA7,
2216 .last_gpio = GPIO_FN_INTC_IRQ0,
2217
2218 .gpios = pinmux_gpios,
2219 .cfg_regs = pinmux_config_regs,
2220 .data_regs = pinmux_data_regs,
2221
2222 .gpio_data = pinmux_data,
2223 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2224};
2225
2226static int __init plat_pinmux_setup(void)
2227{
2228 return register_pinmux(&sh7724_pinmux_info);
2229}
2230arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index c1549382c87c..cb5b4db1ca25 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -234,6 +234,16 @@ static int __init sh7343_devices_setup(void)
234} 234}
235__initcall(sh7343_devices_setup); 235__initcall(sh7343_devices_setup);
236 236
237static struct platform_device *sh7343_early_devices[] __initdata = {
238 &cmt_device,
239};
240
241void __init plat_early_device_setup(void)
242{
243 early_platform_add_devices(sh7343_early_devices,
244 ARRAY_SIZE(sh7343_early_devices));
245}
246
237enum { 247enum {
238 UNUSED = 0, 248 UNUSED = 0,
239 249
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 93ecf8ed5c6c..2a771f48e9e0 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -226,6 +226,16 @@ static int __init sh7366_devices_setup(void)
226} 226}
227__initcall(sh7366_devices_setup); 227__initcall(sh7366_devices_setup);
228 228
229static struct platform_device *sh7366_early_devices[] __initdata = {
230 &cmt_device,
231};
232
233void __init plat_early_device_setup(void)
234{
235 early_platform_add_devices(sh7366_early_devices,
236 ARRAY_SIZE(sh7366_early_devices));
237}
238
229enum { 239enum {
230 UNUSED=0, 240 UNUSED=0,
231 241
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 406747f07dc0..793c50da6a84 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -269,6 +269,16 @@ static int __init sh7722_devices_setup(void)
269} 269}
270__initcall(sh7722_devices_setup); 270__initcall(sh7722_devices_setup);
271 271
272static struct platform_device *sh7722_early_devices[] __initdata = {
273 &cmt_device,
274};
275
276void __init plat_early_device_setup(void)
277{
278 early_platform_add_devices(sh7722_early_devices,
279 ARRAY_SIZE(sh7722_early_devices));
280}
281
272enum { 282enum {
273 UNUSED=0, 283 UNUSED=0,
274 284
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index a800466b938c..dbb44949ed19 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -280,6 +280,16 @@ static int __init sh7723_devices_setup(void)
280} 280}
281__initcall(sh7723_devices_setup); 281__initcall(sh7723_devices_setup);
282 282
283static struct platform_device *sh7723_early_devices[] __initdata = {
284 &cmt_device,
285};
286
287void __init plat_early_device_setup(void)
288{
289 early_platform_add_devices(sh7723_early_devices,
290 ARRAY_SIZE(sh7723_early_devices));
291}
292
283enum { 293enum {
284 UNUSED=0, 294 UNUSED=0,
285 295
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
new file mode 100644
index 000000000000..8429396acb59
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -0,0 +1,556 @@
1/*
2 * SH7724 Setup
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 *
8 * Based on SH7723 Setup
9 * Copyright (C) 2008 Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/platform_device.h>
16#include <linux/init.h>
17#include <linux/serial.h>
18#include <linux/mm.h>
19#include <linux/serial_sci.h>
20#include <linux/uio_driver.h>
21#include <linux/sh_cmt.h>
22#include <linux/io.h>
23#include <asm/clock.h>
24#include <asm/mmzone.h>
25
26/* Serial */
27static struct plat_sci_port sci_platform_data[] = {
28 {
29 .mapbase = 0xffe00000,
30 .flags = UPF_BOOT_AUTOCONF,
31 .type = PORT_SCIF,
32 .irqs = { 80, 80, 80, 80 },
33 }, {
34 .mapbase = 0xffe10000,
35 .flags = UPF_BOOT_AUTOCONF,
36 .type = PORT_SCIF,
37 .irqs = { 81, 81, 81, 81 },
38 }, {
39 .mapbase = 0xffe20000,
40 .flags = UPF_BOOT_AUTOCONF,
41 .type = PORT_SCIF,
42 .irqs = { 82, 82, 82, 82 },
43 }, {
44 .mapbase = 0xa4e30000,
45 .flags = UPF_BOOT_AUTOCONF,
46 .type = PORT_SCIFA,
47 .irqs = { 56, 56, 56, 56 },
48 }, {
49 .mapbase = 0xa4e40000,
50 .flags = UPF_BOOT_AUTOCONF,
51 .type = PORT_SCIFA,
52 .irqs = { 88, 88, 88, 88 },
53 }, {
54 .mapbase = 0xa4e50000,
55 .flags = UPF_BOOT_AUTOCONF,
56 .type = PORT_SCIFA,
57 .irqs = { 109, 109, 109, 109 },
58 }, {
59 .flags = 0,
60 }
61};
62
63static struct platform_device sci_device = {
64 .name = "sh-sci",
65 .id = -1,
66 .dev = {
67 .platform_data = sci_platform_data,
68 },
69};
70
71/* RTC */
72static struct resource rtc_resources[] = {
73 [0] = {
74 .start = 0xa465fec0,
75 .end = 0xa465fec0 + 0x58 - 1,
76 .flags = IORESOURCE_IO,
77 },
78 [1] = {
79 /* Period IRQ */
80 .start = 69,
81 .flags = IORESOURCE_IRQ,
82 },
83 [2] = {
84 /* Carry IRQ */
85 .start = 70,
86 .flags = IORESOURCE_IRQ,
87 },
88 [3] = {
89 /* Alarm IRQ */
90 .start = 68,
91 .flags = IORESOURCE_IRQ,
92 },
93};
94
95static struct platform_device rtc_device = {
96 .name = "sh-rtc",
97 .id = -1,
98 .num_resources = ARRAY_SIZE(rtc_resources),
99 .resource = rtc_resources,
100};
101
102/* I2C0 */
103static struct resource iic0_resources[] = {
104 [0] = {
105 .name = "IIC0",
106 .start = 0x04470000,
107 .end = 0x04470018 - 1,
108 .flags = IORESOURCE_MEM,
109 },
110 [1] = {
111 .start = 96,
112 .end = 99,
113 .flags = IORESOURCE_IRQ,
114 },
115};
116
117static struct platform_device iic0_device = {
118 .name = "i2c-sh_mobile",
119 .id = 0, /* "i2c0" clock */
120 .num_resources = ARRAY_SIZE(iic0_resources),
121 .resource = iic0_resources,
122};
123
124/* I2C1 */
125static struct resource iic1_resources[] = {
126 [0] = {
127 .name = "IIC1",
128 .start = 0x04750000,
129 .end = 0x04750018 - 1,
130 .flags = IORESOURCE_MEM,
131 },
132 [1] = {
133 .start = 92,
134 .end = 95,
135 .flags = IORESOURCE_IRQ,
136 },
137};
138
139static struct platform_device iic1_device = {
140 .name = "i2c-sh_mobile",
141 .id = 1, /* "i2c1" clock */
142 .num_resources = ARRAY_SIZE(iic1_resources),
143 .resource = iic1_resources,
144};
145
146/* VPU */
147static struct uio_info vpu_platform_data = {
148 .name = "VPU5F",
149 .version = "0",
150 .irq = 60,
151};
152
153static struct resource vpu_resources[] = {
154 [0] = {
155 .name = "VPU",
156 .start = 0xfe900000,
157 .end = 0xfe902807,
158 .flags = IORESOURCE_MEM,
159 },
160 [1] = {
161 /* place holder for contiguous memory */
162 },
163};
164
165static struct platform_device vpu_device = {
166 .name = "uio_pdrv_genirq",
167 .id = 0,
168 .dev = {
169 .platform_data = &vpu_platform_data,
170 },
171 .resource = vpu_resources,
172 .num_resources = ARRAY_SIZE(vpu_resources),
173};
174
175/* VEU0 */
176static struct uio_info veu0_platform_data = {
177 .name = "VEU3F0",
178 .version = "0",
179 .irq = 83,
180};
181
182static struct resource veu0_resources[] = {
183 [0] = {
184 .name = "VEU3F0",
185 .start = 0xfe920000,
186 .end = 0xfe9200cb - 1,
187 .flags = IORESOURCE_MEM,
188 },
189 [1] = {
190 /* place holder for contiguous memory */
191 },
192};
193
194static struct platform_device veu0_device = {
195 .name = "uio_pdrv_genirq",
196 .id = 1,
197 .dev = {
198 .platform_data = &veu0_platform_data,
199 },
200 .resource = veu0_resources,
201 .num_resources = ARRAY_SIZE(veu0_resources),
202};
203
204/* VEU1 */
205static struct uio_info veu1_platform_data = {
206 .name = "VEU3F1",
207 .version = "0",
208 .irq = 54,
209};
210
211static struct resource veu1_resources[] = {
212 [0] = {
213 .name = "VEU3F1",
214 .start = 0xfe924000,
215 .end = 0xfe9240cb - 1,
216 .flags = IORESOURCE_MEM,
217 },
218 [1] = {
219 /* place holder for contiguous memory */
220 },
221};
222
223static struct platform_device veu1_device = {
224 .name = "uio_pdrv_genirq",
225 .id = 2,
226 .dev = {
227 .platform_data = &veu1_platform_data,
228 },
229 .resource = veu1_resources,
230 .num_resources = ARRAY_SIZE(veu1_resources),
231};
232
233static struct sh_cmt_config cmt_platform_data = {
234 .name = "CMT",
235 .channel_offset = 0x60,
236 .timer_bit = 5,
237 .clk = "cmt0",
238 .clockevent_rating = 125,
239 .clocksource_rating = 200,
240};
241
242static struct resource cmt_resources[] = {
243 [0] = {
244 .name = "CMT",
245 .start = 0x044a0060,
246 .end = 0x044a006b,
247 .flags = IORESOURCE_MEM,
248 },
249 [1] = {
250 .start = 104,
251 .flags = IORESOURCE_IRQ,
252 },
253};
254
255static struct platform_device cmt_device = {
256 .name = "sh_cmt",
257 .id = 0,
258 .dev = {
259 .platform_data = &cmt_platform_data,
260 },
261 .resource = cmt_resources,
262 .num_resources = ARRAY_SIZE(cmt_resources),
263};
264
265static struct platform_device *sh7724_devices[] __initdata = {
266 &cmt_device,
267 &sci_device,
268 &rtc_device,
269 &iic0_device,
270 &iic1_device,
271 &vpu_device,
272 &veu0_device,
273 &veu1_device,
274};
275
276static int __init sh7724_devices_setup(void)
277{
278 clk_always_enable("vpu0"); /* VPU */
279 clk_always_enable("veu1"); /* VEU3F1 */
280 clk_always_enable("veu0"); /* VEU3F0 */
281
282 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
283 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
284 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
285
286 return platform_add_devices(sh7724_devices,
287 ARRAY_SIZE(sh7724_devices));
288}
289device_initcall(sh7724_devices_setup);
290
291static struct platform_device *sh7724_early_devices[] __initdata = {
292 &cmt_device,
293};
294
295void __init plat_early_device_setup(void)
296{
297 early_platform_add_devices(sh7724_early_devices,
298 ARRAY_SIZE(sh7724_early_devices));
299}
300
301enum {
302 UNUSED = 0,
303
304 /* interrupt sources */
305 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
306 HUDI,
307 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
308 _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK,
309 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
310 VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI,
311 SCIFA_SCIFA0,
312 VPU_VPUI,
313 TPU_TPUI,
314 CEU21I,
315 BEU21I,
316 USB_USI0,
317 ATAPI,
318 RTC_ATI, RTC_PRI, RTC_CUI,
319 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
320 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
321 KEYSC_KEYI,
322 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
323 VEU3F0I,
324 MSIOF_MSIOFI0, MSIOF_MSIOFI1,
325 SPU_SPUI0, SPU_SPUI1,
326 SCIFA_SCIFA1,
327/* ICB_ICBI, */
328 ETHI,
329 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
330 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
331 SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2,
332 CMT_CMTI,
333 TSIF_TSIFI,
334/* ICB_LMBI, */
335 FSI_FSI,
336 SCIFA_SCIFA2,
337 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
338 IRDA_IRDAI,
339 SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
340 JPU_JPUI,
341 MMC_MMCI0, MMC_MMCI1, MMC_MMCI2,
342 LCDC_LCDCI,
343 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
344
345 /* interrupt groups */
346 DMAC1A, _2DG, DMAC0A, VIO, RTC,
347 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMC,
348};
349
350static struct intc_vect vectors[] __initdata = {
351 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
352 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
353 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
354 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
355
356 INTC_VECT(DMAC1A_DEI0, 0x700),
357 INTC_VECT(DMAC1A_DEI1, 0x720),
358 INTC_VECT(DMAC1A_DEI2, 0x740),
359 INTC_VECT(DMAC1A_DEI3, 0x760),
360
361 INTC_VECT(_2DG_TRI, 0x780),
362 INTC_VECT(_2DG_INI, 0x7A0),
363 INTC_VECT(_2DG_CEI, 0x7C0),
364 INTC_VECT(_2DG_BRK, 0x7E0),
365
366 INTC_VECT(DMAC0A_DEI0, 0x800),
367 INTC_VECT(DMAC0A_DEI1, 0x820),
368 INTC_VECT(DMAC0A_DEI2, 0x840),
369 INTC_VECT(DMAC0A_DEI3, 0x860),
370
371 INTC_VECT(VIO_CEU20I, 0x880),
372 INTC_VECT(VIO_BEU20I, 0x8A0),
373 INTC_VECT(VIO_VEU3F1, 0x8C0),
374 INTC_VECT(VIO_VOUI, 0x8E0),
375
376 INTC_VECT(SCIFA_SCIFA0, 0x900),
377 INTC_VECT(VPU_VPUI, 0x980),
378 INTC_VECT(TPU_TPUI, 0x9A0),
379 INTC_VECT(CEU21I, 0x9E0),
380 INTC_VECT(BEU21I, 0xA00),
381 INTC_VECT(USB_USI0, 0xA20),
382 INTC_VECT(ATAPI, 0xA60),
383
384 INTC_VECT(RTC_ATI, 0xA80),
385 INTC_VECT(RTC_PRI, 0xAA0),
386 INTC_VECT(RTC_CUI, 0xAC0),
387
388 INTC_VECT(DMAC1B_DEI4, 0xB00),
389 INTC_VECT(DMAC1B_DEI5, 0xB20),
390 INTC_VECT(DMAC1B_DADERR, 0xB40),
391
392 INTC_VECT(DMAC0B_DEI4, 0xB80),
393 INTC_VECT(DMAC0B_DEI5, 0xBA0),
394 INTC_VECT(DMAC0B_DADERR, 0xBC0),
395
396 INTC_VECT(KEYSC_KEYI, 0xBE0),
397 INTC_VECT(SCIF_SCIF0, 0xC00),
398 INTC_VECT(SCIF_SCIF1, 0xC20),
399 INTC_VECT(SCIF_SCIF2, 0xC40),
400 INTC_VECT(VEU3F0I, 0xC60),
401 INTC_VECT(MSIOF_MSIOFI0, 0xC80),
402 INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
403 INTC_VECT(SPU_SPUI0, 0xCC0),
404 INTC_VECT(SPU_SPUI1, 0xCE0),
405 INTC_VECT(SCIFA_SCIFA1, 0xD00),
406
407/* INTC_VECT(ICB_ICBI, 0xD20), */
408 INTC_VECT(ETHI, 0xD60),
409
410 INTC_VECT(I2C1_ALI, 0xD80),
411 INTC_VECT(I2C1_TACKI, 0xDA0),
412 INTC_VECT(I2C1_WAITI, 0xDC0),
413 INTC_VECT(I2C1_DTEI, 0xDE0),
414
415 INTC_VECT(I2C0_ALI, 0xE00),
416 INTC_VECT(I2C0_TACKI, 0xE20),
417 INTC_VECT(I2C0_WAITI, 0xE40),
418 INTC_VECT(I2C0_DTEI, 0xE60),
419
420 INTC_VECT(SDHI0_SDHII0, 0xE80),
421 INTC_VECT(SDHI0_SDHII1, 0xEA0),
422 INTC_VECT(SDHI0_SDHII2, 0xEC0),
423
424 INTC_VECT(CMT_CMTI, 0xF00),
425 INTC_VECT(TSIF_TSIFI, 0xF20),
426/* INTC_VECT(ICB_LMBI, 0xF60), */
427 INTC_VECT(FSI_FSI, 0xF80),
428 INTC_VECT(SCIFA_SCIFA2, 0xFA0),
429
430 INTC_VECT(TMU0_TUNI0, 0x400),
431 INTC_VECT(TMU0_TUNI1, 0x420),
432 INTC_VECT(TMU0_TUNI2, 0x440),
433
434 INTC_VECT(IRDA_IRDAI, 0x480),
435
436 INTC_VECT(SDHI1_SDHII0, 0x4E0),
437 INTC_VECT(SDHI1_SDHII1, 0x500),
438 INTC_VECT(SDHI1_SDHII2, 0x520),
439
440 INTC_VECT(JPU_JPUI, 0x560),
441
442 INTC_VECT(MMC_MMCI0, 0x580),
443 INTC_VECT(MMC_MMCI1, 0x5A0),
444 INTC_VECT(MMC_MMCI2, 0x5C0),
445
446 INTC_VECT(LCDC_LCDCI, 0xF40),
447
448 INTC_VECT(TMU1_TUNI0, 0x920),
449 INTC_VECT(TMU1_TUNI1, 0x940),
450 INTC_VECT(TMU1_TUNI2, 0x960),
451};
452
453static struct intc_group groups[] __initdata = {
454 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
455 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK),
456 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
457 INTC_GROUP(VIO, VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI),
458 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
459 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
460 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
461 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
462 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
463 INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2),
464 INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
465 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
466 INTC_GROUP(MMC, MMC_MMCI0, MMC_MMCI1, MMC_MMCI2),
467};
468
469/* FIXMEEEEEEEEEEEEEEEEEEE !!!!! */
470/* very bad manual !! */
471static struct intc_mask_reg mask_registers[] __initdata = {
472 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
473 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
474 /*SDHII3?*/0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } },
475 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
476 { VIO_VOUI, VIO_VEU3F1, VIO_BEU20I, VIO_CEU20I,
477 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
478 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
479 { 0, 0, 0, VPU_VPUI, ATAPI, ETHI, 0, /*SCIFA3*/SCIFA_SCIFA0 } },
480 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
481 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
482 SPU_SPUI1, SPU_SPUI0, BEU21I, IRDA_IRDAI } },
483 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
484 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
485 JPU_JPUI, 0, 0, LCDC_LCDCI } },
486 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
487 { KEYSC_KEYI, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
488 VEU3F0I, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
489 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
490 { 0, 0, /*ICB_ICBI*/0, /*SCIFA4*/SCIFA_SCIFA1,
491 CEU21I, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
492 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
493 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
494 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
495 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
496 { /*SDHII3*/0, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0,
497 0, 0, /*SCIFA5*/SCIFA_SCIFA2, FSI_FSI } },
498 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
499 { 0, 0, 0, CMT_CMTI, 0, /*USB1*/0, USB_USI0, 0 } },
500 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
501 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
502 0, RTC_ATI, RTC_PRI, RTC_CUI } },
503 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
504 { _2DG_BRK, _2DG_CEI, _2DG_INI, _2DG_TRI,
505 0, TPU_TPUI, /*ICB_LMBI*/0, TSIF_TSIFI } },
506 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
507 { 0, 0, 0, 0, 0, 0, 0, 0/*2DDMAC*/ } },
508 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
509 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
510};
511
512static struct intc_prio_reg prio_registers[] __initdata = {
513 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
514 TMU0_TUNI2, IRDA_IRDAI } },
515 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU_JPUI, LCDC_LCDCI,
516 DMAC1A, BEU21I } },
517 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
518 TMU1_TUNI2, SPU } },
519 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMC, 0, ATAPI } },
520 { 0xa4080010, 0, 16, 4, /* IPRE */
521 { DMAC0A, /*BEU?VEU?*/VIO, /*SCIFA3*/SCIFA_SCIFA0, /*VPU5F*/
522 VPU_VPUI } },
523 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B,
524 USB_USI0, CMT_CMTI } },
525 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
526 SCIF_SCIF2, VEU3F0I } },
527 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
528 I2C1, I2C0 } },
529 { 0xa4080020, 0, 16, 4, /* IPRI */ { /*SCIFA4*/SCIFA_SCIFA1, /*ICB*/0,
530 TSIF_TSIFI, _2DG/*ICB?*/ } },
531 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU21I, ETHI, FSI_FSI, SDHI1 } },
532 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, /*ICB?*/0, SDHI0 } },
533 { 0xa408002c, 0, 16, 4, /* IPRL */ { /*SCIFA5*/SCIFA_SCIFA2, 0,
534 TPU_TPUI, /*2DDMAC*/0 } },
535 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
536 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
537};
538
539static struct intc_sense_reg sense_registers[] __initdata = {
540 { 0xa414001c, 16, 2, /* ICR1 */
541 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
542};
543
544static struct intc_mask_reg ack_registers[] __initdata = {
545 { 0xa4140024, 0, 8, /* INTREQ00 */
546 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
547};
548
549static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups,
550 mask_registers, prio_registers, sense_registers,
551 ack_registers);
552
553void __init plat_irq_setup(void)
554{
555 register_intc_controller(&intc_desc);
556}
diff --git a/arch/sh/kernel/io.c b/arch/sh/kernel/io.c
index 29cf4588fc05..4f85fffaa557 100644
--- a/arch/sh/kernel/io.c
+++ b/arch/sh/kernel/io.c
@@ -12,6 +12,7 @@
12 * for more details. 12 * for more details.
13 */ 13 */
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/pci.h>
15#include <asm/machvec.h> 16#include <asm/machvec.h>
16#include <asm/io.h> 17#include <asm/io.h>
17 18
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 04a6004fccc4..38515a795920 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -29,6 +29,7 @@
29#include <linux/mmzone.h> 29#include <linux/mmzone.h>
30#include <linux/clk.h> 30#include <linux/clk.h>
31#include <linux/delay.h> 31#include <linux/delay.h>
32#include <linux/platform_device.h>
32#include <asm/uaccess.h> 33#include <asm/uaccess.h>
33#include <asm/io.h> 34#include <asm/io.h>
34#include <asm/page.h> 35#include <asm/page.h>
@@ -328,6 +329,10 @@ static int __init parse_elfcorehdr(char *arg)
328early_param("elfcorehdr", parse_elfcorehdr); 329early_param("elfcorehdr", parse_elfcorehdr);
329#endif 330#endif
330 331
332void __init __attribute__ ((weak)) plat_early_device_setup(void)
333{
334}
335
331void __init setup_arch(char **cmdline_p) 336void __init setup_arch(char **cmdline_p)
332{ 337{
333 enable_mmu(); 338 enable_mmu();
@@ -381,6 +386,8 @@ void __init setup_arch(char **cmdline_p)
381 386
382 parse_early_param(); 387 parse_early_param();
383 388
389 plat_early_device_setup();
390
384 sh_mv_setup(); 391 sh_mv_setup();
385 392
386 /* 393 /*
@@ -435,7 +442,8 @@ static const char *cpu_name[] = {
435 [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3", 442 [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
436 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103", 443 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
437 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723", 444 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
438 [CPU_SH7366] = "SH7366", [CPU_SH_NONE] = "Unknown" 445 [CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724",
446 [CPU_SH_NONE] = "Unknown"
439}; 447};
440 448
441const char *get_cpu_subtype(struct sh_cpuinfo *c) 449const char *get_cpu_subtype(struct sh_cpuinfo *c)
diff --git a/arch/sh/kernel/time_32.c b/arch/sh/kernel/time_32.c
index 1700d2465f6c..c770413c3213 100644
--- a/arch/sh/kernel/time_32.c
+++ b/arch/sh/kernel/time_32.c
@@ -17,6 +17,7 @@
17#include <linux/sched.h> 17#include <linux/sched.h>
18#include <linux/clockchips.h> 18#include <linux/clockchips.h>
19#include <linux/mc146818rtc.h> /* for rtc_lock */ 19#include <linux/mc146818rtc.h> /* for rtc_lock */
20#include <linux/platform_device.h>
20#include <linux/smp.h> 21#include <linux/smp.h>
21#include <asm/clock.h> 22#include <asm/clock.h>
22#include <asm/rtc.h> 23#include <asm/rtc.h>
@@ -229,6 +230,14 @@ void __init time_init(void)
229#endif 230#endif
230 231
231 /* 232 /*
233 * Make sure all compiled-in early timers register themselves.
234 * Run probe() for one "earlytimer" device.
235 */
236 early_platform_driver_register_all("earlytimer");
237 if (early_platform_driver_probe("earlytimer", 1, 0))
238 return;
239
240 /*
232 * Find the timer to use as the system timer, it will be 241 * Find the timer to use as the system timer, it will be
233 * initialized for us. 242 * initialized for us.
234 */ 243 */
diff --git a/arch/sh/mm/ioremap_32.c b/arch/sh/mm/ioremap_32.c
index 60cc486d2c2c..da2f4186f2cd 100644
--- a/arch/sh/mm/ioremap_32.c
+++ b/arch/sh/mm/ioremap_32.c
@@ -46,17 +46,15 @@ void __iomem *__ioremap(unsigned long phys_addr, unsigned long size,
46 return NULL; 46 return NULL;
47 47
48 /* 48 /*
49 * If we're on an SH7751 or SH7780 PCI controller, PCI memory is 49 * If we're in the fixed PCI memory range, mapping through page
50 * mapped at the end of the address space (typically 0xfd000000) 50 * tables is not only pointless, but also fundamentally broken.
51 * in a non-translatable area, so mapping through page tables for 51 * Just return the physical address instead.
52 * this area is not only pointless, but also fundamentally
53 * broken. Just return the physical address instead.
54 * 52 *
55 * For boards that map a small PCI memory aperture somewhere in 53 * For boards that map a small PCI memory aperture somewhere in
56 * P1/P2 space, ioremap() will already do the right thing, 54 * P1/P2 space, ioremap() will already do the right thing,
57 * and we'll never get this far. 55 * and we'll never get this far.
58 */ 56 */
59 if (is_pci_memaddr(phys_addr) && is_pci_memaddr(last_addr)) 57 if (is_pci_memory_fixed_range(phys_addr, size))
60 return (void __iomem *)phys_addr; 58 return (void __iomem *)phys_addr;
61 59
62#if !defined(CONFIG_PMB_FIXED) 60#if !defined(CONFIG_PMB_FIXED)
@@ -121,7 +119,9 @@ void __iounmap(void __iomem *addr)
121 unsigned long seg = PXSEG(vaddr); 119 unsigned long seg = PXSEG(vaddr);
122 struct vm_struct *p; 120 struct vm_struct *p;
123 121
124 if (seg < P3SEG || vaddr >= P3_ADDR_MAX || is_pci_memaddr(vaddr)) 122 if (seg < P3SEG || vaddr >= P3_ADDR_MAX)
123 return;
124 if (is_pci_memory_fixed_range(vaddr, 0))
125 return; 125 return;
126 126
127#ifdef CONFIG_PMB 127#ifdef CONFIG_PMB
diff --git a/arch/sh/oprofile/common.c b/arch/sh/oprofile/common.c
index 1b9d4304b3bf..44f4e31c6d63 100644
--- a/arch/sh/oprofile/common.c
+++ b/arch/sh/oprofile/common.c
@@ -109,6 +109,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
109 case CPU_SH7785: 109 case CPU_SH7785:
110 case CPU_SH7786: 110 case CPU_SH7786:
111 case CPU_SH7723: 111 case CPU_SH7723:
112 case CPU_SH7724:
112 case CPU_SHX3: 113 case CPU_SHX3:
113 lmodel = &op_model_sh4a_ops; 114 lmodel = &op_model_sh4a_ops;
114 break; 115 break;
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index 1c92c39a53aa..c24756489612 100644
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -47,6 +47,7 @@ struct sh_cmt_priv {
47 unsigned long rate; 47 unsigned long rate;
48 spinlock_t lock; 48 spinlock_t lock;
49 struct clock_event_device ced; 49 struct clock_event_device ced;
50 struct clocksource cs;
50 unsigned long total_cycles; 51 unsigned long total_cycles;
51}; 52};
52 53
@@ -376,6 +377,68 @@ static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
376 spin_unlock_irqrestore(&p->lock, flags); 377 spin_unlock_irqrestore(&p->lock, flags);
377} 378}
378 379
380static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs)
381{
382 return container_of(cs, struct sh_cmt_priv, cs);
383}
384
385static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
386{
387 struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
388 unsigned long flags, raw;
389 unsigned long value;
390 int has_wrapped;
391
392 spin_lock_irqsave(&p->lock, flags);
393 value = p->total_cycles;
394 raw = sh_cmt_get_counter(p, &has_wrapped);
395
396 if (unlikely(has_wrapped))
397 raw = p->match_value;
398 spin_unlock_irqrestore(&p->lock, flags);
399
400 return value + raw;
401}
402
403static int sh_cmt_clocksource_enable(struct clocksource *cs)
404{
405 struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
406 int ret;
407
408 p->total_cycles = 0;
409
410 ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
411 if (ret)
412 return ret;
413
414 /* TODO: calculate good shift from rate and counter bit width */
415 cs->shift = 0;
416 cs->mult = clocksource_hz2mult(p->rate, cs->shift);
417 return 0;
418}
419
420static void sh_cmt_clocksource_disable(struct clocksource *cs)
421{
422 sh_cmt_stop(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
423}
424
425static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
426 char *name, unsigned long rating)
427{
428 struct clocksource *cs = &p->cs;
429
430 cs->name = name;
431 cs->rating = rating;
432 cs->read = sh_cmt_clocksource_read;
433 cs->enable = sh_cmt_clocksource_enable;
434 cs->disable = sh_cmt_clocksource_disable;
435 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
436 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
437 pr_info("sh_cmt: %s used as clock source\n", cs->name);
438 clocksource_register(cs);
439 return 0;
440}
441
379static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced) 442static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced)
380{ 443{
381 return container_of(ced, struct sh_cmt_priv, ced); 444 return container_of(ced, struct sh_cmt_priv, ced);
@@ -483,6 +546,9 @@ int sh_cmt_register(struct sh_cmt_priv *p, char *name,
483 if (clockevent_rating) 546 if (clockevent_rating)
484 sh_cmt_register_clockevent(p, name, clockevent_rating); 547 sh_cmt_register_clockevent(p, name, clockevent_rating);
485 548
549 if (clocksource_rating)
550 sh_cmt_register_clocksource(p, name, clocksource_rating);
551
486 return 0; 552 return 0;
487} 553}
488 554
@@ -566,9 +632,19 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
566static int __devinit sh_cmt_probe(struct platform_device *pdev) 632static int __devinit sh_cmt_probe(struct platform_device *pdev)
567{ 633{
568 struct sh_cmt_priv *p = platform_get_drvdata(pdev); 634 struct sh_cmt_priv *p = platform_get_drvdata(pdev);
635 struct sh_cmt_config *cfg = pdev->dev.platform_data;
569 int ret; 636 int ret;
570 637
571 p = kmalloc(sizeof(*p), GFP_KERNEL); 638 if (p) {
639 pr_info("sh_cmt: %s kept as earlytimer\n", cfg->name);
640 return 0;
641 }
642
643 if (is_early_platform_device(pdev))
644 p = alloc_bootmem(sizeof(*p));
645 else
646 p = kmalloc(sizeof(*p), GFP_KERNEL);
647
572 if (p == NULL) { 648 if (p == NULL) {
573 dev_err(&pdev->dev, "failed to allocate driver data\n"); 649 dev_err(&pdev->dev, "failed to allocate driver data\n");
574 return -ENOMEM; 650 return -ENOMEM;
@@ -576,7 +652,10 @@ static int __devinit sh_cmt_probe(struct platform_device *pdev)
576 652
577 ret = sh_cmt_setup(p, pdev); 653 ret = sh_cmt_setup(p, pdev);
578 if (ret) { 654 if (ret) {
579 kfree(p); 655 if (is_early_platform_device(pdev))
656 free_bootmem(__pa(p), sizeof(*p));
657 else
658 kfree(p);
580 659
581 platform_set_drvdata(pdev, NULL); 660 platform_set_drvdata(pdev, NULL);
582 } 661 }
@@ -606,6 +685,7 @@ static void __exit sh_cmt_exit(void)
606 platform_driver_unregister(&sh_cmt_device_driver); 685 platform_driver_unregister(&sh_cmt_device_driver);
607} 686}
608 687
688early_platform_init("earlytimer", &sh_cmt_device_driver);
609module_init(sh_cmt_init); 689module_init(sh_cmt_init);
610module_exit(sh_cmt_exit); 690module_exit(sh_cmt_exit);
611 691
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index d0aa82d7fce0..84cc6512f081 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -91,6 +91,9 @@
91# define SCSPTR5 0xa4050128 91# define SCSPTR5 0xa4050128
92# define SCIF_ORER 0x0001 /* overrun error bit */ 92# define SCIF_ORER 0x0001 /* overrun error bit */
93# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 93# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
94#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
95# define SCIF_ORER 0x0001 /* overrun error bit */
96# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
94#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 97#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
95# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 98# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
96# define SCIF_ORER 0x0001 /* overrun error bit */ 99# define SCIF_ORER 0x0001 /* overrun error bit */
@@ -361,7 +364,8 @@
361 h8_sci_offset, h8_sci_size) \ 364 h8_sci_offset, h8_sci_size) \
362 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) 365 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
363#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) 366#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
364#elif defined(CONFIG_CPU_SUBTYPE_SH7723) 367#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
368 defined(CONFIG_CPU_SUBTYPE_SH7724)
365 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \ 369 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
366 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) 370 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
367 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ 371 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
@@ -390,7 +394,8 @@ SCIF_FNS(SCFDR, 0x1c, 16)
390SCIF_FNS(SCxTDR, 0x20, 8) 394SCIF_FNS(SCxTDR, 0x20, 8)
391SCIF_FNS(SCxRDR, 0x24, 8) 395SCIF_FNS(SCxRDR, 0x24, 8)
392SCIF_FNS(SCLSR, 0x24, 16) 396SCIF_FNS(SCLSR, 0x24, 16)
393#elif defined(CONFIG_CPU_SUBTYPE_SH7723) 397#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
398 defined(CONFIG_CPU_SUBTYPE_SH7724)
394SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) 399SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
395SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) 400SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
396SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) 401SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
@@ -604,6 +609,17 @@ static inline int sci_rxd_in(struct uart_port *port)
604 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */ 609 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
605 return 1; 610 return 1;
606} 611}
612#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
613# define SCFSR 0x0010
614# define SCASSR 0x0014
615static inline int sci_rxd_in(struct uart_port *port)
616{
617 if (port->type == PORT_SCIF)
618 return ctrl_inw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0;
619 if (port->type == PORT_SCIFA)
620 return ctrl_inw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0;
621 return 1;
622}
607#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 623#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
608static inline int sci_rxd_in(struct uart_port *port) 624static inline int sci_rxd_in(struct uart_port *port)
609{ 625{
@@ -757,7 +773,8 @@ static inline int sci_rxd_in(struct uart_port *port)
757 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 773 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
758 defined(CONFIG_CPU_SUBTYPE_SH7721) 774 defined(CONFIG_CPU_SUBTYPE_SH7721)
759#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 775#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
760#elif defined(CONFIG_CPU_SUBTYPE_SH7723) 776#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
777 defined(CONFIG_CPU_SUBTYPE_SH7724)
761static inline int scbrr_calc(struct uart_port *port, int bps, int clk) 778static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
762{ 779{
763 if (port->type == PORT_SCIF) 780 if (port->type == PORT_SCIF)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 22:33:09 -0500