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-rw-r--r--drivers/media/dvb-frontends/rtl2832.c314
-rw-r--r--drivers/media/dvb-frontends/rtl2832_priv.h3
2 files changed, 144 insertions, 173 deletions
diff --git a/drivers/media/dvb-frontends/rtl2832.c b/drivers/media/dvb-frontends/rtl2832.c
index db0178717f2d..f86e9ab8b901 100644
--- a/drivers/media/dvb-frontends/rtl2832.c
+++ b/drivers/media/dvb-frontends/rtl2832.c
@@ -25,133 +25,133 @@
25#define REG_MASK(b) (BIT(b + 1) - 1) 25#define REG_MASK(b) (BIT(b + 1) - 1)
26 26
27static const struct rtl2832_reg_entry registers[] = { 27static const struct rtl2832_reg_entry registers[] = {
28 [DVBT_SOFT_RST] = {0x1, 0x1, 2, 2}, 28 [DVBT_SOFT_RST] = {0x101, 2, 2},
29 [DVBT_IIC_REPEAT] = {0x1, 0x1, 3, 3}, 29 [DVBT_IIC_REPEAT] = {0x101, 3, 3},
30 [DVBT_TR_WAIT_MIN_8K] = {0x1, 0x88, 11, 2}, 30 [DVBT_TR_WAIT_MIN_8K] = {0x188, 11, 2},
31 [DVBT_RSD_BER_FAIL_VAL] = {0x1, 0x8f, 15, 0}, 31 [DVBT_RSD_BER_FAIL_VAL] = {0x18f, 15, 0},
32 [DVBT_EN_BK_TRK] = {0x1, 0xa6, 7, 7}, 32 [DVBT_EN_BK_TRK] = {0x1a6, 7, 7},
33 [DVBT_AD_EN_REG] = {0x0, 0x8, 7, 7}, 33 [DVBT_AD_EN_REG] = {0x008, 7, 7},
34 [DVBT_AD_EN_REG1] = {0x0, 0x8, 6, 6}, 34 [DVBT_AD_EN_REG1] = {0x008, 6, 6},
35 [DVBT_EN_BBIN] = {0x1, 0xb1, 0, 0}, 35 [DVBT_EN_BBIN] = {0x1b1, 0, 0},
36 [DVBT_MGD_THD0] = {0x1, 0x95, 7, 0}, 36 [DVBT_MGD_THD0] = {0x195, 7, 0},
37 [DVBT_MGD_THD1] = {0x1, 0x96, 7, 0}, 37 [DVBT_MGD_THD1] = {0x196, 7, 0},
38 [DVBT_MGD_THD2] = {0x1, 0x97, 7, 0}, 38 [DVBT_MGD_THD2] = {0x197, 7, 0},
39 [DVBT_MGD_THD3] = {0x1, 0x98, 7, 0}, 39 [DVBT_MGD_THD3] = {0x198, 7, 0},
40 [DVBT_MGD_THD4] = {0x1, 0x99, 7, 0}, 40 [DVBT_MGD_THD4] = {0x199, 7, 0},
41 [DVBT_MGD_THD5] = {0x1, 0x9a, 7, 0}, 41 [DVBT_MGD_THD5] = {0x19a, 7, 0},
42 [DVBT_MGD_THD6] = {0x1, 0x9b, 7, 0}, 42 [DVBT_MGD_THD6] = {0x19b, 7, 0},
43 [DVBT_MGD_THD7] = {0x1, 0x9c, 7, 0}, 43 [DVBT_MGD_THD7] = {0x19c, 7, 0},
44 [DVBT_EN_CACQ_NOTCH] = {0x1, 0x61, 4, 4}, 44 [DVBT_EN_CACQ_NOTCH] = {0x161, 4, 4},
45 [DVBT_AD_AV_REF] = {0x0, 0x9, 6, 0}, 45 [DVBT_AD_AV_REF] = {0x009, 6, 0},
46 [DVBT_REG_PI] = {0x0, 0xa, 2, 0}, 46 [DVBT_REG_PI] = {0x00a, 2, 0},
47 [DVBT_PIP_ON] = {0x0, 0x21, 3, 3}, 47 [DVBT_PIP_ON] = {0x021, 3, 3},
48 [DVBT_SCALE1_B92] = {0x2, 0x92, 7, 0}, 48 [DVBT_SCALE1_B92] = {0x292, 7, 0},
49 [DVBT_SCALE1_B93] = {0x2, 0x93, 7, 0}, 49 [DVBT_SCALE1_B93] = {0x293, 7, 0},
50 [DVBT_SCALE1_BA7] = {0x2, 0xa7, 7, 0}, 50 [DVBT_SCALE1_BA7] = {0x2a7, 7, 0},
51 [DVBT_SCALE1_BA9] = {0x2, 0xa9, 7, 0}, 51 [DVBT_SCALE1_BA9] = {0x2a9, 7, 0},
52 [DVBT_SCALE1_BAA] = {0x2, 0xaa, 7, 0}, 52 [DVBT_SCALE1_BAA] = {0x2aa, 7, 0},
53 [DVBT_SCALE1_BAB] = {0x2, 0xab, 7, 0}, 53 [DVBT_SCALE1_BAB] = {0x2ab, 7, 0},
54 [DVBT_SCALE1_BAC] = {0x2, 0xac, 7, 0}, 54 [DVBT_SCALE1_BAC] = {0x2ac, 7, 0},
55 [DVBT_SCALE1_BB0] = {0x2, 0xb0, 7, 0}, 55 [DVBT_SCALE1_BB0] = {0x2b0, 7, 0},
56 [DVBT_SCALE1_BB1] = {0x2, 0xb1, 7, 0}, 56 [DVBT_SCALE1_BB1] = {0x2b1, 7, 0},
57 [DVBT_KB_P1] = {0x1, 0x64, 3, 1}, 57 [DVBT_KB_P1] = {0x164, 3, 1},
58 [DVBT_KB_P2] = {0x1, 0x64, 6, 4}, 58 [DVBT_KB_P2] = {0x164, 6, 4},
59 [DVBT_KB_P3] = {0x1, 0x65, 2, 0}, 59 [DVBT_KB_P3] = {0x165, 2, 0},
60 [DVBT_OPT_ADC_IQ] = {0x0, 0x6, 5, 4}, 60 [DVBT_OPT_ADC_IQ] = {0x006, 5, 4},
61 [DVBT_AD_AVI] = {0x0, 0x9, 1, 0}, 61 [DVBT_AD_AVI] = {0x009, 1, 0},
62 [DVBT_AD_AVQ] = {0x0, 0x9, 3, 2}, 62 [DVBT_AD_AVQ] = {0x009, 3, 2},
63 [DVBT_K1_CR_STEP12] = {0x2, 0xad, 9, 4}, 63 [DVBT_K1_CR_STEP12] = {0x2ad, 9, 4},
64 [DVBT_TRK_KS_P2] = {0x1, 0x6f, 2, 0}, 64 [DVBT_TRK_KS_P2] = {0x16f, 2, 0},
65 [DVBT_TRK_KS_I2] = {0x1, 0x70, 5, 3}, 65 [DVBT_TRK_KS_I2] = {0x170, 5, 3},
66 [DVBT_TR_THD_SET2] = {0x1, 0x72, 3, 0}, 66 [DVBT_TR_THD_SET2] = {0x172, 3, 0},
67 [DVBT_TRK_KC_P2] = {0x1, 0x73, 5, 3}, 67 [DVBT_TRK_KC_P2] = {0x173, 5, 3},
68 [DVBT_TRK_KC_I2] = {0x1, 0x75, 2, 0}, 68 [DVBT_TRK_KC_I2] = {0x175, 2, 0},
69 [DVBT_CR_THD_SET2] = {0x1, 0x76, 7, 6}, 69 [DVBT_CR_THD_SET2] = {0x176, 7, 6},
70 [DVBT_PSET_IFFREQ] = {0x1, 0x19, 21, 0}, 70 [DVBT_PSET_IFFREQ] = {0x119, 21, 0},
71 [DVBT_SPEC_INV] = {0x1, 0x15, 0, 0}, 71 [DVBT_SPEC_INV] = {0x115, 0, 0},
72 [DVBT_RSAMP_RATIO] = {0x1, 0x9f, 27, 2}, 72 [DVBT_RSAMP_RATIO] = {0x19f, 27, 2},
73 [DVBT_CFREQ_OFF_RATIO] = {0x1, 0x9d, 23, 4}, 73 [DVBT_CFREQ_OFF_RATIO] = {0x19d, 23, 4},
74 [DVBT_FSM_STAGE] = {0x3, 0x51, 6, 3}, 74 [DVBT_FSM_STAGE] = {0x351, 6, 3},
75 [DVBT_RX_CONSTEL] = {0x3, 0x3c, 3, 2}, 75 [DVBT_RX_CONSTEL] = {0x33c, 3, 2},
76 [DVBT_RX_HIER] = {0x3, 0x3c, 6, 4}, 76 [DVBT_RX_HIER] = {0x33c, 6, 4},
77 [DVBT_RX_C_RATE_LP] = {0x3, 0x3d, 2, 0}, 77 [DVBT_RX_C_RATE_LP] = {0x33d, 2, 0},
78 [DVBT_RX_C_RATE_HP] = {0x3, 0x3d, 5, 3}, 78 [DVBT_RX_C_RATE_HP] = {0x33d, 5, 3},
79 [DVBT_GI_IDX] = {0x3, 0x51, 1, 0}, 79 [DVBT_GI_IDX] = {0x351, 1, 0},
80 [DVBT_FFT_MODE_IDX] = {0x3, 0x51, 2, 2}, 80 [DVBT_FFT_MODE_IDX] = {0x351, 2, 2},
81 [DVBT_RSD_BER_EST] = {0x3, 0x4e, 15, 0}, 81 [DVBT_RSD_BER_EST] = {0x34e, 15, 0},
82 [DVBT_CE_EST_EVM] = {0x4, 0xc, 15, 0}, 82 [DVBT_CE_EST_EVM] = {0x40c, 15, 0},
83 [DVBT_RF_AGC_VAL] = {0x3, 0x5b, 13, 0}, 83 [DVBT_RF_AGC_VAL] = {0x35b, 13, 0},
84 [DVBT_IF_AGC_VAL] = {0x3, 0x59, 13, 0}, 84 [DVBT_IF_AGC_VAL] = {0x359, 13, 0},
85 [DVBT_DAGC_VAL] = {0x3, 0x5, 7, 0}, 85 [DVBT_DAGC_VAL] = {0x305, 7, 0},
86 [DVBT_SFREQ_OFF] = {0x3, 0x18, 13, 0}, 86 [DVBT_SFREQ_OFF] = {0x318, 13, 0},
87 [DVBT_CFREQ_OFF] = {0x3, 0x5f, 17, 0}, 87 [DVBT_CFREQ_OFF] = {0x35f, 17, 0},
88 [DVBT_POLAR_RF_AGC] = {0x0, 0xe, 1, 1}, 88 [DVBT_POLAR_RF_AGC] = {0x00e, 1, 1},
89 [DVBT_POLAR_IF_AGC] = {0x0, 0xe, 0, 0}, 89 [DVBT_POLAR_IF_AGC] = {0x00e, 0, 0},
90 [DVBT_AAGC_HOLD] = {0x1, 0x4, 5, 5}, 90 [DVBT_AAGC_HOLD] = {0x104, 5, 5},
91 [DVBT_EN_RF_AGC] = {0x1, 0x4, 6, 6}, 91 [DVBT_EN_RF_AGC] = {0x104, 6, 6},
92 [DVBT_EN_IF_AGC] = {0x1, 0x4, 7, 7}, 92 [DVBT_EN_IF_AGC] = {0x104, 7, 7},
93 [DVBT_IF_AGC_MIN] = {0x1, 0x8, 7, 0}, 93 [DVBT_IF_AGC_MIN] = {0x108, 7, 0},
94 [DVBT_IF_AGC_MAX] = {0x1, 0x9, 7, 0}, 94 [DVBT_IF_AGC_MAX] = {0x109, 7, 0},
95 [DVBT_RF_AGC_MIN] = {0x1, 0xa, 7, 0}, 95 [DVBT_RF_AGC_MIN] = {0x10a, 7, 0},
96 [DVBT_RF_AGC_MAX] = {0x1, 0xb, 7, 0}, 96 [DVBT_RF_AGC_MAX] = {0x10b, 7, 0},
97 [DVBT_IF_AGC_MAN] = {0x1, 0xc, 6, 6}, 97 [DVBT_IF_AGC_MAN] = {0x10c, 6, 6},
98 [DVBT_IF_AGC_MAN_VAL] = {0x1, 0xc, 13, 0}, 98 [DVBT_IF_AGC_MAN_VAL] = {0x10c, 13, 0},
99 [DVBT_RF_AGC_MAN] = {0x1, 0xe, 6, 6}, 99 [DVBT_RF_AGC_MAN] = {0x10e, 6, 6},
100 [DVBT_RF_AGC_MAN_VAL] = {0x1, 0xe, 13, 0}, 100 [DVBT_RF_AGC_MAN_VAL] = {0x10e, 13, 0},
101 [DVBT_DAGC_TRG_VAL] = {0x1, 0x12, 7, 0}, 101 [DVBT_DAGC_TRG_VAL] = {0x112, 7, 0},
102 [DVBT_AGC_TARG_VAL_0] = {0x1, 0x2, 0, 0}, 102 [DVBT_AGC_TARG_VAL_0] = {0x102, 0, 0},
103 [DVBT_AGC_TARG_VAL_8_1] = {0x1, 0x3, 7, 0}, 103 [DVBT_AGC_TARG_VAL_8_1] = {0x103, 7, 0},
104 [DVBT_AAGC_LOOP_GAIN] = {0x1, 0xc7, 5, 1}, 104 [DVBT_AAGC_LOOP_GAIN] = {0x1c7, 5, 1},
105 [DVBT_LOOP_GAIN2_3_0] = {0x1, 0x4, 4, 1}, 105 [DVBT_LOOP_GAIN2_3_0] = {0x104, 4, 1},
106 [DVBT_LOOP_GAIN2_4] = {0x1, 0x5, 7, 7}, 106 [DVBT_LOOP_GAIN2_4] = {0x105, 7, 7},
107 [DVBT_LOOP_GAIN3] = {0x1, 0xc8, 4, 0}, 107 [DVBT_LOOP_GAIN3] = {0x1c8, 4, 0},
108 [DVBT_VTOP1] = {0x1, 0x6, 5, 0}, 108 [DVBT_VTOP1] = {0x106, 5, 0},
109 [DVBT_VTOP2] = {0x1, 0xc9, 5, 0}, 109 [DVBT_VTOP2] = {0x1c9, 5, 0},
110 [DVBT_VTOP3] = {0x1, 0xca, 5, 0}, 110 [DVBT_VTOP3] = {0x1ca, 5, 0},
111 [DVBT_KRF1] = {0x1, 0xcb, 7, 0}, 111 [DVBT_KRF1] = {0x1cb, 7, 0},
112 [DVBT_KRF2] = {0x1, 0x7, 7, 0}, 112 [DVBT_KRF2] = {0x107, 7, 0},
113 [DVBT_KRF3] = {0x1, 0xcd, 7, 0}, 113 [DVBT_KRF3] = {0x1cd, 7, 0},
114 [DVBT_KRF4] = {0x1, 0xce, 7, 0}, 114 [DVBT_KRF4] = {0x1ce, 7, 0},
115 [DVBT_EN_GI_PGA] = {0x1, 0xe5, 0, 0}, 115 [DVBT_EN_GI_PGA] = {0x1e5, 0, 0},
116 [DVBT_THD_LOCK_UP] = {0x1, 0xd9, 8, 0}, 116 [DVBT_THD_LOCK_UP] = {0x1d9, 8, 0},
117 [DVBT_THD_LOCK_DW] = {0x1, 0xdb, 8, 0}, 117 [DVBT_THD_LOCK_DW] = {0x1db, 8, 0},
118 [DVBT_THD_UP1] = {0x1, 0xdd, 7, 0}, 118 [DVBT_THD_UP1] = {0x1dd, 7, 0},
119 [DVBT_THD_DW1] = {0x1, 0xde, 7, 0}, 119 [DVBT_THD_DW1] = {0x1de, 7, 0},
120 [DVBT_INTER_CNT_LEN] = {0x1, 0xd8, 3, 0}, 120 [DVBT_INTER_CNT_LEN] = {0x1d8, 3, 0},
121 [DVBT_GI_PGA_STATE] = {0x1, 0xe6, 3, 3}, 121 [DVBT_GI_PGA_STATE] = {0x1e6, 3, 3},
122 [DVBT_EN_AGC_PGA] = {0x1, 0xd7, 0, 0}, 122 [DVBT_EN_AGC_PGA] = {0x1d7, 0, 0},
123 [DVBT_CKOUTPAR] = {0x1, 0x7b, 5, 5}, 123 [DVBT_CKOUTPAR] = {0x17b, 5, 5},
124 [DVBT_CKOUT_PWR] = {0x1, 0x7b, 6, 6}, 124 [DVBT_CKOUT_PWR] = {0x17b, 6, 6},
125 [DVBT_SYNC_DUR] = {0x1, 0x7b, 7, 7}, 125 [DVBT_SYNC_DUR] = {0x17b, 7, 7},
126 [DVBT_ERR_DUR] = {0x1, 0x7c, 0, 0}, 126 [DVBT_ERR_DUR] = {0x17c, 0, 0},
127 [DVBT_SYNC_LVL] = {0x1, 0x7c, 1, 1}, 127 [DVBT_SYNC_LVL] = {0x17c, 1, 1},
128 [DVBT_ERR_LVL] = {0x1, 0x7c, 2, 2}, 128 [DVBT_ERR_LVL] = {0x17c, 2, 2},
129 [DVBT_VAL_LVL] = {0x1, 0x7c, 3, 3}, 129 [DVBT_VAL_LVL] = {0x17c, 3, 3},
130 [DVBT_SERIAL] = {0x1, 0x7c, 4, 4}, 130 [DVBT_SERIAL] = {0x17c, 4, 4},
131 [DVBT_SER_LSB] = {0x1, 0x7c, 5, 5}, 131 [DVBT_SER_LSB] = {0x17c, 5, 5},
132 [DVBT_CDIV_PH0] = {0x1, 0x7d, 3, 0}, 132 [DVBT_CDIV_PH0] = {0x17d, 3, 0},
133 [DVBT_CDIV_PH1] = {0x1, 0x7d, 7, 4}, 133 [DVBT_CDIV_PH1] = {0x17d, 7, 4},
134 [DVBT_MPEG_IO_OPT_2_2] = {0x0, 0x6, 7, 7}, 134 [DVBT_MPEG_IO_OPT_2_2] = {0x006, 7, 7},
135 [DVBT_MPEG_IO_OPT_1_0] = {0x0, 0x7, 7, 6}, 135 [DVBT_MPEG_IO_OPT_1_0] = {0x007, 7, 6},
136 [DVBT_CKOUTPAR_PIP] = {0x0, 0xb7, 4, 4}, 136 [DVBT_CKOUTPAR_PIP] = {0x0b7, 4, 4},
137 [DVBT_CKOUT_PWR_PIP] = {0x0, 0xb7, 3, 3}, 137 [DVBT_CKOUT_PWR_PIP] = {0x0b7, 3, 3},
138 [DVBT_SYNC_LVL_PIP] = {0x0, 0xb7, 2, 2}, 138 [DVBT_SYNC_LVL_PIP] = {0x0b7, 2, 2},
139 [DVBT_ERR_LVL_PIP] = {0x0, 0xb7, 1, 1}, 139 [DVBT_ERR_LVL_PIP] = {0x0b7, 1, 1},
140 [DVBT_VAL_LVL_PIP] = {0x0, 0xb7, 0, 0}, 140 [DVBT_VAL_LVL_PIP] = {0x0b7, 0, 0},
141 [DVBT_CKOUTPAR_PID] = {0x0, 0xb9, 4, 4}, 141 [DVBT_CKOUTPAR_PID] = {0x0b9, 4, 4},
142 [DVBT_CKOUT_PWR_PID] = {0x0, 0xb9, 3, 3}, 142 [DVBT_CKOUT_PWR_PID] = {0x0b9, 3, 3},
143 [DVBT_SYNC_LVL_PID] = {0x0, 0xb9, 2, 2}, 143 [DVBT_SYNC_LVL_PID] = {0x0b9, 2, 2},
144 [DVBT_ERR_LVL_PID] = {0x0, 0xb9, 1, 1}, 144 [DVBT_ERR_LVL_PID] = {0x0b9, 1, 1},
145 [DVBT_VAL_LVL_PID] = {0x0, 0xb9, 0, 0}, 145 [DVBT_VAL_LVL_PID] = {0x0b9, 0, 0},
146 [DVBT_SM_PASS] = {0x1, 0x93, 11, 0}, 146 [DVBT_SM_PASS] = {0x193, 11, 0},
147 [DVBT_AD7_SETTING] = {0x0, 0x11, 15, 0}, 147 [DVBT_AD7_SETTING] = {0x011, 15, 0},
148 [DVBT_RSSI_R] = {0x3, 0x1, 6, 0}, 148 [DVBT_RSSI_R] = {0x301, 6, 0},
149 [DVBT_ACI_DET_IND] = {0x3, 0x12, 0, 0}, 149 [DVBT_ACI_DET_IND] = {0x312, 0, 0},
150 [DVBT_REG_MON] = {0x0, 0xd, 1, 0}, 150 [DVBT_REG_MON] = {0x00d, 1, 0},
151 [DVBT_REG_MONSEL] = {0x0, 0xd, 2, 2}, 151 [DVBT_REG_MONSEL] = {0x00d, 2, 2},
152 [DVBT_REG_GPE] = {0x0, 0xd, 7, 7}, 152 [DVBT_REG_GPE] = {0x00d, 7, 7},
153 [DVBT_REG_GPO] = {0x0, 0x10, 0, 0}, 153 [DVBT_REG_GPO] = {0x010, 0, 0},
154 [DVBT_REG_4MSEL] = {0x0, 0x13, 0, 0}, 154 [DVBT_REG_4MSEL] = {0x013, 0, 0},
155}; 155};
156 156
157/* Our regmap is bypassing I2C adapter lock, thus we do it! */ 157/* Our regmap is bypassing I2C adapter lock, thus we do it! */
@@ -191,38 +191,13 @@ int rtl2832_bulk_read(struct i2c_client *client, unsigned int reg, void *val,
191 return ret; 191 return ret;
192} 192}
193 193
194/* write multiple registers */
195static int rtl2832_wr_regs(struct rtl2832_dev *dev, u8 reg, u8 page, u8 *val, int len)
196{
197 return rtl2832_bulk_write(dev->client, page << 8 | reg, val, len);
198}
199
200/* read multiple registers */
201static int rtl2832_rd_regs(struct rtl2832_dev *dev, u8 reg, u8 page, u8 *val, int len)
202{
203 return rtl2832_bulk_read(dev->client, page << 8 | reg, val, len);
204}
205
206/* write single register */
207static int rtl2832_wr_reg(struct rtl2832_dev *dev, u8 reg, u8 page, u8 val)
208{
209 return rtl2832_wr_regs(dev, reg, page, &val, 1);
210}
211
212/* read single register */
213static int rtl2832_rd_reg(struct rtl2832_dev *dev, u8 reg, u8 page, u8 *val)
214{
215 return rtl2832_rd_regs(dev, reg, page, val, 1);
216}
217
218static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val) 194static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val)
219{ 195{
220 struct i2c_client *client = dev->client; 196 struct i2c_client *client = dev->client;
221 int ret; 197 int ret;
222 198
223 u8 reg_start_addr; 199 u16 reg_start_addr;
224 u8 msb, lsb; 200 u8 msb, lsb;
225 u8 page;
226 u8 reading[4]; 201 u8 reading[4];
227 u32 reading_tmp; 202 u32 reading_tmp;
228 int i; 203 int i;
@@ -233,12 +208,11 @@ static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val)
233 reg_start_addr = registers[reg].start_address; 208 reg_start_addr = registers[reg].start_address;
234 msb = registers[reg].msb; 209 msb = registers[reg].msb;
235 lsb = registers[reg].lsb; 210 lsb = registers[reg].lsb;
236 page = registers[reg].page;
237 211
238 len = (msb >> 3) + 1; 212 len = (msb >> 3) + 1;
239 mask = REG_MASK(msb - lsb); 213 mask = REG_MASK(msb - lsb);
240 214
241 ret = rtl2832_rd_regs(dev, reg_start_addr, page, &reading[0], len); 215 ret = rtl2832_bulk_read(client, reg_start_addr, reading, len);
242 if (ret) 216 if (ret)
243 goto err; 217 goto err;
244 218
@@ -261,9 +235,8 @@ static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val)
261 struct i2c_client *client = dev->client; 235 struct i2c_client *client = dev->client;
262 int ret, i; 236 int ret, i;
263 u8 len; 237 u8 len;
264 u8 reg_start_addr; 238 u16 reg_start_addr;
265 u8 msb, lsb; 239 u8 msb, lsb;
266 u8 page;
267 u32 mask; 240 u32 mask;
268 241
269 242
@@ -276,13 +249,12 @@ static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val)
276 reg_start_addr = registers[reg].start_address; 249 reg_start_addr = registers[reg].start_address;
277 msb = registers[reg].msb; 250 msb = registers[reg].msb;
278 lsb = registers[reg].lsb; 251 lsb = registers[reg].lsb;
279 page = registers[reg].page;
280 252
281 len = (msb >> 3) + 1; 253 len = (msb >> 3) + 1;
282 mask = REG_MASK(msb - lsb); 254 mask = REG_MASK(msb - lsb);
283 255
284 256
285 ret = rtl2832_rd_regs(dev, reg_start_addr, page, &reading[0], len); 257 ret = rtl2832_bulk_read(client, reg_start_addr, reading, len);
286 if (ret) 258 if (ret)
287 goto err; 259 goto err;
288 260
@@ -297,7 +269,7 @@ static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val)
297 for (i = 0; i < len; i++) 269 for (i = 0; i < len; i++)
298 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff; 270 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
299 271
300 ret = rtl2832_wr_regs(dev, reg_start_addr, page, &writing[0], len); 272 ret = rtl2832_bulk_write(client, reg_start_addr, writing, len);
301 if (ret) 273 if (ret)
302 goto err; 274 goto err;
303 275
@@ -522,7 +494,7 @@ static int rtl2832_set_frontend(struct dvb_frontend *fe)
522 fe->ops.tuner_ops.set_params(fe); 494 fe->ops.tuner_ops.set_params(fe);
523 495
524 /* PIP mode related */ 496 /* PIP mode related */
525 ret = rtl2832_wr_regs(dev, 0x92, 1, "\x00\x0f\xff", 3); 497 ret = rtl2832_bulk_write(client, 0x192, "\x00\x0f\xff", 3);
526 if (ret) 498 if (ret)
527 goto err; 499 goto err;
528 500
@@ -560,7 +532,7 @@ static int rtl2832_set_frontend(struct dvb_frontend *fe)
560 } 532 }
561 533
562 for (j = 0; j < sizeof(bw_params[0]); j++) { 534 for (j = 0; j < sizeof(bw_params[0]); j++) {
563 ret = rtl2832_wr_regs(dev, 0x1c+j, 1, &bw_params[i][j], 1); 535 ret = rtl2832_bulk_write(client, 0x11c + j, &bw_params[i][j], 1);
564 if (ret) 536 if (ret)
565 goto err; 537 goto err;
566 } 538 }
@@ -616,11 +588,11 @@ static int rtl2832_get_frontend(struct dvb_frontend *fe)
616 if (dev->sleeping) 588 if (dev->sleeping)
617 return 0; 589 return 0;
618 590
619 ret = rtl2832_rd_regs(dev, 0x3c, 3, buf, 2); 591 ret = rtl2832_bulk_read(client, 0x33c, buf, 2);
620 if (ret) 592 if (ret)
621 goto err; 593 goto err;
622 594
623 ret = rtl2832_rd_reg(dev, 0x51, 3, &buf[2]); 595 ret = rtl2832_bulk_read(client, 0x351, &buf[2], 1);
624 if (ret) 596 if (ret)
625 goto err; 597 goto err;
626 598
@@ -1103,7 +1075,7 @@ static int rtl2832_enable_slave_ts(struct i2c_client *client)
1103 1075
1104 dev_dbg(&client->dev, "\n"); 1076 dev_dbg(&client->dev, "\n");
1105 1077
1106 ret = rtl2832_wr_regs(dev, 0x0c, 1, "\x5f\xff", 2); 1078 ret = rtl2832_bulk_write(client, 0x10c, "\x5f\xff", 2);
1107 if (ret) 1079 if (ret)
1108 goto err; 1080 goto err;
1109 1081
@@ -1111,23 +1083,23 @@ static int rtl2832_enable_slave_ts(struct i2c_client *client)
1111 if (ret) 1083 if (ret)
1112 goto err; 1084 goto err;
1113 1085
1114 ret = rtl2832_wr_reg(dev, 0xbc, 0, 0x18); 1086 ret = rtl2832_bulk_write(client, 0x0bc, "\x18", 1);
1115 if (ret) 1087 if (ret)
1116 goto err; 1088 goto err;
1117 1089
1118 ret = rtl2832_wr_reg(dev, 0x22, 0, 0x01); 1090 ret = rtl2832_bulk_write(client, 0x022, "\x01", 1);
1119 if (ret) 1091 if (ret)
1120 goto err; 1092 goto err;
1121 1093
1122 ret = rtl2832_wr_reg(dev, 0x26, 0, 0x1f); 1094 ret = rtl2832_bulk_write(client, 0x026, "\x1f", 1);
1123 if (ret) 1095 if (ret)
1124 goto err; 1096 goto err;
1125 1097
1126 ret = rtl2832_wr_reg(dev, 0x27, 0, 0xff); 1098 ret = rtl2832_bulk_write(client, 0x027, "\xff", 1);
1127 if (ret) 1099 if (ret)
1128 goto err; 1100 goto err;
1129 1101
1130 ret = rtl2832_wr_regs(dev, 0x92, 1, "\x7f\xf7\xff", 3); 1102 ret = rtl2832_bulk_write(client, 0x192, "\x7f\xf7\xff", 3);
1131 if (ret) 1103 if (ret)
1132 goto err; 1104 goto err;
1133 1105
@@ -1284,7 +1256,7 @@ static int rtl2832_probe(struct i2c_client *client,
1284 } 1256 }
1285 1257
1286 /* check if the demod is there */ 1258 /* check if the demod is there */
1287 ret = rtl2832_rd_reg(dev, 0x00, 0x0, &tmp); 1259 ret = rtl2832_bulk_read(client, 0x000, &tmp, 1);
1288 if (ret) 1260 if (ret)
1289 goto err_i2c_del_mux_adapter; 1261 goto err_i2c_del_mux_adapter;
1290 1262
diff --git a/drivers/media/dvb-frontends/rtl2832_priv.h b/drivers/media/dvb-frontends/rtl2832_priv.h
index 216e905763d4..973892afb916 100644
--- a/drivers/media/dvb-frontends/rtl2832_priv.h
+++ b/drivers/media/dvb-frontends/rtl2832_priv.h
@@ -45,8 +45,7 @@ struct rtl2832_dev {
45}; 45};
46 46
47struct rtl2832_reg_entry { 47struct rtl2832_reg_entry {
48 u8 page; 48 u16 start_address;
49 u8 start_address;
50 u8 msb; 49 u8 msb;
51 u8 lsb; 50 u8 lsb;
52}; 51};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 17:57:13 -0500