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-rw-r--r--Documentation/devicetree/bindings/arm/omap/l3-noc.txt1
-rw-r--r--arch/arm/boot/dts/omap5.dtsi2
-rw-r--r--drivers/bus/omap_l3_noc.c5
-rw-r--r--drivers/bus/omap_l3_noc.h52
4 files changed, 44 insertions, 16 deletions
diff --git a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt
index 974624ea68f6..161448da959d 100644
--- a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt
+++ b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt
@@ -6,6 +6,7 @@ provided by Arteris.
6Required properties: 6Required properties:
7- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family 7- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
8 Should be "ti,omap4-l3-noc" for OMAP4 family 8 Should be "ti,omap4-l3-noc" for OMAP4 family
9 Should be "ti,omap5-l3-noc" for OMAP5 family
9 Should be "ti,dra7-l3-noc" for DRA7 family 10 Should be "ti,dra7-l3-noc" for DRA7 family
10 Should be "ti,am4372-l3-noc" for AM43 family 11 Should be "ti,am4372-l3-noc" for AM43 family
11- reg: Contains L3 register address range for each noc domain. 12- reg: Contains L3 register address range for each noc domain.
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index efe5f737f39b..7d24ae0306b5 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -128,7 +128,7 @@
128 * hierarchy. 128 * hierarchy.
129 */ 129 */
130 ocp { 130 ocp {
131 compatible = "ti,omap4-l3-noc", "simple-bus"; 131 compatible = "ti,omap5-l3-noc", "simple-bus";
132 #address-cells = <1>; 132 #address-cells = <1>;
133 #size-cells = <1>; 133 #size-cells = <1>;
134 ranges; 134 ranges;
diff --git a/drivers/bus/omap_l3_noc.c b/drivers/bus/omap_l3_noc.c
index 11f7982cbdb3..ebee57d715d2 100644
--- a/drivers/bus/omap_l3_noc.c
+++ b/drivers/bus/omap_l3_noc.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP L3 Interconnect error handling driver 2 * OMAP L3 Interconnect error handling driver
3 * 3 *
4 * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
5 * Santosh Shilimkar <santosh.shilimkar@ti.com> 5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Sricharan <r.sricharan@ti.com> 6 * Sricharan <r.sricharan@ti.com>
7 * 7 *
@@ -233,7 +233,8 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
233} 233}
234 234
235static const struct of_device_id l3_noc_match[] = { 235static const struct of_device_id l3_noc_match[] = {
236 {.compatible = "ti,omap4-l3-noc", .data = &omap_l3_data}, 236 {.compatible = "ti,omap4-l3-noc", .data = &omap4_l3_data},
237 {.compatible = "ti,omap5-l3-noc", .data = &omap5_l3_data},
237 {.compatible = "ti,dra7-l3-noc", .data = &dra_l3_data}, 238 {.compatible = "ti,dra7-l3-noc", .data = &dra_l3_data},
238 {.compatible = "ti,am4372-l3-noc", .data = &am4372_l3_data}, 239 {.compatible = "ti,am4372-l3-noc", .data = &am4372_l3_data},
239 {}, 240 {},
diff --git a/drivers/bus/omap_l3_noc.h b/drivers/bus/omap_l3_noc.h
index a314d800f394..73431f81da28 100644
--- a/drivers/bus/omap_l3_noc.h
+++ b/drivers/bus/omap_l3_noc.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP L3 Interconnect error handling driver header 2 * OMAP L3 Interconnect error handling driver header
3 * 3 *
4 * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
5 * Santosh Shilimkar <santosh.shilimkar@ti.com> 5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * sricharan <r.sricharan@ti.com> 6 * sricharan <r.sricharan@ti.com>
7 * 7 *
@@ -175,16 +175,14 @@ static struct l3_flagmux_data omap_l3_flagmux_clk2 = {
175}; 175};
176 176
177 177
178static struct l3_target_data omap_l3_target_data_clk3[] = { 178static struct l3_target_data omap4_l3_target_data_clk3[] = {
179 {0x0100, "EMUSS",}, 179 {0x0100, "DEBUGSS",},
180 {0x0300, "DEBUG SOURCE",},
181 {0x0, "HOST CLK3",},
182}; 180};
183 181
184static struct l3_flagmux_data omap_l3_flagmux_clk3 = { 182static struct l3_flagmux_data omap4_l3_flagmux_clk3 = {
185 .offset = 0x0200, 183 .offset = 0x0200,
186 .l3_targ = omap_l3_target_data_clk3, 184 .l3_targ = omap4_l3_target_data_clk3,
187 .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk3), 185 .num_targ_data = ARRAY_SIZE(omap4_l3_target_data_clk3),
188}; 186};
189 187
190static struct l3_masters_data omap_l3_masters[] = { 188static struct l3_masters_data omap_l3_masters[] = {
@@ -215,21 +213,49 @@ static struct l3_masters_data omap_l3_masters[] = {
215 { 0x32, "USBHOSTFS"} 213 { 0x32, "USBHOSTFS"}
216}; 214};
217 215
218static struct l3_flagmux_data *omap_l3_flagmux[] = { 216static struct l3_flagmux_data *omap4_l3_flagmux[] = {
219 &omap_l3_flagmux_clk1, 217 &omap_l3_flagmux_clk1,
220 &omap_l3_flagmux_clk2, 218 &omap_l3_flagmux_clk2,
221 &omap_l3_flagmux_clk3, 219 &omap4_l3_flagmux_clk3,
222}; 220};
223 221
224static const struct omap_l3 omap_l3_data = { 222static const struct omap_l3 omap4_l3_data = {
225 .l3_flagmux = omap_l3_flagmux, 223 .l3_flagmux = omap4_l3_flagmux,
226 .num_modules = ARRAY_SIZE(omap_l3_flagmux), 224 .num_modules = ARRAY_SIZE(omap4_l3_flagmux),
227 .l3_masters = omap_l3_masters, 225 .l3_masters = omap_l3_masters,
228 .num_masters = ARRAY_SIZE(omap_l3_masters), 226 .num_masters = ARRAY_SIZE(omap_l3_masters),
229 /* The 6 MSBs of register field used to distinguish initiator */ 227 /* The 6 MSBs of register field used to distinguish initiator */
230 .mst_addr_mask = 0xFC, 228 .mst_addr_mask = 0xFC,
231}; 229};
232 230
231/* OMAP5 data */
232static struct l3_target_data omap5_l3_target_data_clk3[] = {
233 {0x0100, "L3INSTR",},
234 {0x0300, "DEBUGSS",},
235 {0x0, "HOSTCLK3",},
236};
237
238static struct l3_flagmux_data omap5_l3_flagmux_clk3 = {
239 .offset = 0x0200,
240 .l3_targ = omap5_l3_target_data_clk3,
241 .num_targ_data = ARRAY_SIZE(omap5_l3_target_data_clk3),
242};
243
244static struct l3_flagmux_data *omap5_l3_flagmux[] = {
245 &omap_l3_flagmux_clk1,
246 &omap_l3_flagmux_clk2,
247 &omap5_l3_flagmux_clk3,
248};
249
250static const struct omap_l3 omap5_l3_data = {
251 .l3_flagmux = omap5_l3_flagmux,
252 .num_modules = ARRAY_SIZE(omap5_l3_flagmux),
253 .l3_masters = omap_l3_masters,
254 .num_masters = ARRAY_SIZE(omap_l3_masters),
255 /* The 6 MSBs of register field used to distinguish initiator */
256 .mst_addr_mask = 0x7E0,
257};
258
233/* DRA7 data */ 259/* DRA7 data */
234static struct l3_target_data dra_l3_target_data_clk1[] = { 260static struct l3_target_data dra_l3_target_data_clk1[] = {
235 {0x2a00, "AES1",}, 261 {0x2a00, "AES1",},