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-rw-r--r--arch/arm/mach-omap2/Makefile22
-rw-r--r--arch/arm/mach-omap2/omap_opp_data.h24
-rw-r--r--arch/arm/mach-omap2/opp3xxx_data.c66
-rw-r--r--arch/arm/mach-omap2/opp4xxx_data.c43
-rw-r--r--arch/arm/mach-omap2/vc.h83
-rw-r--r--arch/arm/mach-omap2/vc3xxx_data.c63
-rw-r--r--arch/arm/mach-omap2/vc44xx_data.c75
-rw-r--r--arch/arm/mach-omap2/voltage.c1017
-rw-r--r--arch/arm/mach-omap2/voltage.h89
-rw-r--r--arch/arm/mach-omap2/voltagedomains3xxx_data.c95
-rw-r--r--arch/arm/mach-omap2/voltagedomains44xx_data.c102
-rw-r--r--arch/arm/mach-omap2/vp.h143
-rw-r--r--arch/arm/mach-omap2/vp3xxx_data.c82
-rw-r--r--arch/arm/mach-omap2/vp44xx_data.c100
14 files changed, 1226 insertions, 778 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index c5b1be9b7328..ea1e26f58b91 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -59,10 +59,10 @@ endif
59# Power Management 59# Power Management
60ifeq ($(CONFIG_PM),y) 60ifeq ($(CONFIG_PM),y)
61obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o 61obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
62obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o voltage.o 62obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o
63obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o voltage.o \ 63obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o \
64 cpuidle34xx.o pm_bus.o 64 cpuidle34xx.o pm_bus.o
65obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o voltage.o pm_bus.o 65obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o
66obj-$(CONFIG_PM_DEBUG) += pm-debug.o 66obj-$(CONFIG_PM_DEBUG) += pm-debug.o
67obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o 67obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
68obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o 68obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o
@@ -78,13 +78,25 @@ endif
78 78
79# PRCM 79# PRCM
80obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o 80obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
81obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o 81obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
82 vc3xxx_data.o vp3xxx_data.o
82# XXX The presence of cm2xxx_3xxx.o on the line below is temporary and 83# XXX The presence of cm2xxx_3xxx.o on the line below is temporary and
83# will be removed once the OMAP4 part of the codebase is converted to 84# will be removed once the OMAP4 part of the codebase is converted to
84# use OMAP4-specific PRCM functions. 85# use OMAP4-specific PRCM functions.
85obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \ 86obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \
86 cm44xx.o prcm_mpu44xx.o \ 87 cm44xx.o prcm_mpu44xx.o \
87 prminst44xx.o 88 prminst44xx.o vc44xx_data.o \
89 vp44xx_data.o
90
91# OMAP voltage domains
92ifeq ($(CONFIG_PM),y)
93voltagedomain-common := voltage.o
94obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common)
95obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) \
96 voltagedomains3xxx_data.o
97obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) \
98 voltagedomains44xx_data.o
99endif
88 100
89# OMAP powerdomain framework 101# OMAP powerdomain framework
90powerdomain-common += powerdomain.o powerdomain-common.o 102powerdomain-common += powerdomain.o powerdomain-common.o
diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h
index 46ac27dd6c84..c784c12f98a1 100644
--- a/arch/arm/mach-omap2/omap_opp_data.h
+++ b/arch/arm/mach-omap2/omap_opp_data.h
@@ -21,6 +21,8 @@
21 21
22#include <plat/omap_hwmod.h> 22#include <plat/omap_hwmod.h>
23 23
24#include "voltage.h"
25
24/* 26/*
25 * *BIG FAT WARNING*: 27 * *BIG FAT WARNING*:
26 * USE the following ONLY in opp data initialization common to an SoC. 28 * USE the following ONLY in opp data initialization common to an SoC.
@@ -65,8 +67,30 @@ struct omap_opp_def {
65 .u_volt = _uv, \ 67 .u_volt = _uv, \
66} 68}
67 69
70/*
71 * Initialization wrapper used to define SmartReflex process data
72 * XXX Is this needed? Just use C99 initializers in data files?
73 */
74#define VOLT_DATA_DEFINE(_v_nom, _efuse_offs, _errminlimit, _errgain) \
75{ \
76 .volt_nominal = _v_nom, \
77 .sr_efuse_offs = _efuse_offs, \
78 .sr_errminlimit = _errminlimit, \
79 .vp_errgain = _errgain \
80}
81
68/* Use this to initialize the default table */ 82/* Use this to initialize the default table */
69extern int __init omap_init_opp_table(struct omap_opp_def *opp_def, 83extern int __init omap_init_opp_table(struct omap_opp_def *opp_def,
70 u32 opp_def_size); 84 u32 opp_def_size);
71 85
86
87extern struct omap_volt_data omap34xx_vddmpu_volt_data[];
88extern struct omap_volt_data omap34xx_vddcore_volt_data[];
89extern struct omap_volt_data omap36xx_vddmpu_volt_data[];
90extern struct omap_volt_data omap36xx_vddcore_volt_data[];
91
92extern struct omap_volt_data omap44xx_vdd_mpu_volt_data[];
93extern struct omap_volt_data omap44xx_vdd_iva_volt_data[];
94extern struct omap_volt_data omap44xx_vdd_core_volt_data[];
95
72#endif /* __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H */ 96#endif /* __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H */
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index 0486fce8a92c..3bba9204a174 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -4,8 +4,9 @@
4 * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Nishanth Menon 5 * Nishanth Menon
6 * Kevin Hilman 6 * Kevin Hilman
7 * Copyright (C) 2010 Nokia Corporation. 7 * Copyright (C) 2010-2011 Nokia Corporation.
8 * Eduardo Valentin 8 * Eduardo Valentin
9 * Paul Walmsley
9 * 10 *
10 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
@@ -20,8 +21,71 @@
20 21
21#include <plat/cpu.h> 22#include <plat/cpu.h>
22 23
24#include "control.h"
23#include "omap_opp_data.h" 25#include "omap_opp_data.h"
24 26
27/* 34xx */
28
29/* VDD1 */
30
31#define OMAP3430_VDD_MPU_OPP1_UV 975000
32#define OMAP3430_VDD_MPU_OPP2_UV 1075000
33#define OMAP3430_VDD_MPU_OPP3_UV 1200000
34#define OMAP3430_VDD_MPU_OPP4_UV 1270000
35#define OMAP3430_VDD_MPU_OPP5_UV 1350000
36
37struct omap_volt_data omap34xx_vddmpu_volt_data[] = {
38 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c),
39 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c),
40 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18),
41 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18),
42 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18),
43 VOLT_DATA_DEFINE(0, 0, 0, 0),
44};
45
46/* VDD2 */
47
48#define OMAP3430_VDD_CORE_OPP1_UV 975000
49#define OMAP3430_VDD_CORE_OPP2_UV 1050000
50#define OMAP3430_VDD_CORE_OPP3_UV 1150000
51
52struct omap_volt_data omap34xx_vddcore_volt_data[] = {
53 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c),
54 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c),
55 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18),
56 VOLT_DATA_DEFINE(0, 0, 0, 0),
57};
58
59/* 36xx */
60
61/* VDD1 */
62
63#define OMAP3630_VDD_MPU_OPP50_UV 1012500
64#define OMAP3630_VDD_MPU_OPP100_UV 1200000
65#define OMAP3630_VDD_MPU_OPP120_UV 1325000
66#define OMAP3630_VDD_MPU_OPP1G_UV 1375000
67
68struct omap_volt_data omap36xx_vddmpu_volt_data[] = {
69 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c),
70 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16),
71 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23),
72 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27),
73 VOLT_DATA_DEFINE(0, 0, 0, 0),
74};
75
76/* VDD2 */
77
78#define OMAP3630_VDD_CORE_OPP50_UV 1000000
79#define OMAP3630_VDD_CORE_OPP100_UV 1200000
80
81struct omap_volt_data omap36xx_vddcore_volt_data[] = {
82 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c),
83 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16),
84 VOLT_DATA_DEFINE(0, 0, 0, 0),
85};
86
87/* OPP data */
88
25static struct omap_opp_def __initdata omap34xx_opp_def_list[] = { 89static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
26 /* MPU OPP1 */ 90 /* MPU OPP1 */
27 OPP_INITIALIZER("mpu", true, 125000000, 975000), 91 OPP_INITIALIZER("mpu", true, 125000000, 975000),
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index a11fa566d8ee..fdee8d4186ab 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -5,8 +5,9 @@
5 * Nishanth Menon 5 * Nishanth Menon
6 * Kevin Hilman 6 * Kevin Hilman
7 * Thara Gopinath 7 * Thara Gopinath
8 * Copyright (C) 2010 Nokia Corporation. 8 * Copyright (C) 2010-2011 Nokia Corporation.
9 * Eduardo Valentin 9 * Eduardo Valentin
10 * Paul Walmsley
10 * 11 *
11 * This program is free software; you can redistribute it and/or modify 12 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as 13 * it under the terms of the GNU General Public License version 2 as
@@ -21,8 +22,48 @@
21 22
22#include <plat/cpu.h> 23#include <plat/cpu.h>
23 24
25#include "control.h"
24#include "omap_opp_data.h" 26#include "omap_opp_data.h"
25 27
28/*
29 * Structures containing OMAP4430 voltage supported and various
30 * voltage dependent data for each VDD.
31 */
32
33#define OMAP4430_VDD_MPU_OPP50_UV 930000
34#define OMAP4430_VDD_MPU_OPP100_UV 1100000
35#define OMAP4430_VDD_MPU_OPPTURBO_UV 1260000
36#define OMAP4430_VDD_MPU_OPPNITRO_UV 1350000
37
38struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
39 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
40 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
41 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
42 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
43 VOLT_DATA_DEFINE(0, 0, 0, 0),
44};
45
46#define OMAP4430_VDD_IVA_OPP50_UV 930000
47#define OMAP4430_VDD_IVA_OPP100_UV 1100000
48#define OMAP4430_VDD_IVA_OPPTURBO_UV 1260000
49
50struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
51 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
52 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
53 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
54 VOLT_DATA_DEFINE(0, 0, 0, 0),
55};
56
57#define OMAP4430_VDD_CORE_OPP50_UV 930000
58#define OMAP4430_VDD_CORE_OPP100_UV 1100000
59
60struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
61 VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
62 VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
63 VOLT_DATA_DEFINE(0, 0, 0, 0),
64};
65
66
26static struct omap_opp_def __initdata omap44xx_opp_def_list[] = { 67static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
27 /* MPU OPP1 - OPP50 */ 68 /* MPU OPP1 - OPP50 */
28 OPP_INITIALIZER("mpu", true, 300000000, 1100000), 69 OPP_INITIALIZER("mpu", true, 300000000, 1100000),
diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
new file mode 100644
index 000000000000..e7767771de49
--- /dev/null
+++ b/arch/arm/mach-omap2/vc.h
@@ -0,0 +1,83 @@
1/*
2 * OMAP3/4 Voltage Controller (VC) structure and macro definitions
3 *
4 * Copyright (C) 2007, 2010 Texas Instruments, Inc.
5 * Rajendra Nayak <rnayak@ti.com>
6 * Lesly A M <x0080970@ti.com>
7 * Thara Gopinath <thara@ti.com>
8 *
9 * Copyright (C) 2008, 2011 Nokia Corporation
10 * Kalle Jokiniemi
11 * Paul Walmsley
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License version
15 * 2 as published by the Free Software Foundation.
16 */
17#ifndef __ARCH_ARM_MACH_OMAP2_VC_H
18#define __ARCH_ARM_MACH_OMAP2_VC_H
19
20#include <linux/kernel.h>
21
22/**
23 * struct omap_vc_common_data - per-VC register/bitfield data
24 * @cmd_on_mask: ON bitmask in PRM_VC_CMD_VAL* register
25 * @valid: VALID bitmask in PRM_VC_BYPASS_VAL register
26 * @smps_sa_reg: Offset of PRM_VC_SMPS_SA reg from PRM start
27 * @smps_volra_reg: Offset of PRM_VC_SMPS_VOL_RA reg from PRM start
28 * @bypass_val_reg: Offset of PRM_VC_BYPASS_VAL reg from PRM start
29 * @data_shift: DATA field shift in PRM_VC_BYPASS_VAL register
30 * @slaveaddr_shift: SLAVEADDR field shift in PRM_VC_BYPASS_VAL register
31 * @regaddr_shift: REGADDR field shift in PRM_VC_BYPASS_VAL register
32 * @cmd_on_shift: ON field shift in PRM_VC_CMD_VAL_* register
33 * @cmd_onlp_shift: ONLP field shift in PRM_VC_CMD_VAL_* register
34 * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
35 * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
36 *
37 * XXX One of cmd_on_mask and cmd_on_shift are not needed
38 * XXX VALID should probably be a shift, not a mask
39 */
40struct omap_vc_common_data {
41 u32 cmd_on_mask;
42 u32 valid;
43 u8 smps_sa_reg;
44 u8 smps_volra_reg;
45 u8 bypass_val_reg;
46 u8 data_shift;
47 u8 slaveaddr_shift;
48 u8 regaddr_shift;
49 u8 cmd_on_shift;
50 u8 cmd_onlp_shift;
51 u8 cmd_ret_shift;
52 u8 cmd_off_shift;
53};
54
55/**
56 * struct omap_vc_instance_data - VC per-instance data
57 * @vc_common: pointer to VC common data for this platform
58 * @smps_sa_mask: SA* bitmask in the PRM_VC_SMPS_SA register
59 * @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register
60 * @smps_sa_shift: SA* field shift in the PRM_VC_SMPS_SA register
61 * @smps_volra_shift: VOLRA* field shift in the PRM_VC_VOL_RA register
62 *
63 * XXX It is not necessary to have both a *_mask and a *_shift -
64 * remove one
65 */
66struct omap_vc_instance_data {
67 const struct omap_vc_common_data *vc_common;
68 u32 smps_sa_mask;
69 u32 smps_volra_mask;
70 u8 cmdval_reg;
71 u8 smps_sa_shift;
72 u8 smps_volra_shift;
73};
74
75extern struct omap_vc_instance_data omap3_vc1_data;
76extern struct omap_vc_instance_data omap3_vc2_data;
77
78extern struct omap_vc_instance_data omap4_vc_mpu_data;
79extern struct omap_vc_instance_data omap4_vc_iva_data;
80extern struct omap_vc_instance_data omap4_vc_core_data;
81
82#endif
83
diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
new file mode 100644
index 000000000000..f37dc4bc379a
--- /dev/null
+++ b/arch/arm/mach-omap2/vc3xxx_data.c
@@ -0,0 +1,63 @@
1/*
2 * OMAP3 Voltage Controller (VC) data
3 *
4 * Copyright (C) 2007, 2010 Texas Instruments, Inc.
5 * Rajendra Nayak <rnayak@ti.com>
6 * Lesly A M <x0080970@ti.com>
7 * Thara Gopinath <thara@ti.com>
8 *
9 * Copyright (C) 2008, 2011 Nokia Corporation
10 * Kalle Jokiniemi
11 * Paul Walmsley
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#include <linux/io.h>
18#include <linux/err.h>
19#include <linux/init.h>
20
21#include <plat/common.h>
22
23#include "prm-regbits-34xx.h"
24#include "voltage.h"
25
26#include "vc.h"
27
28/*
29 * VC data common to 34xx/36xx chips
30 * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
31 */
32static struct omap_vc_common_data omap3_vc_common = {
33 .smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET,
34 .smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
35 .bypass_val_reg = OMAP3_PRM_VC_BYPASS_VAL_OFFSET,
36 .data_shift = OMAP3430_DATA_SHIFT,
37 .slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT,
38 .regaddr_shift = OMAP3430_REGADDR_SHIFT,
39 .valid = OMAP3430_VALID_MASK,
40 .cmd_on_shift = OMAP3430_VC_CMD_ON_SHIFT,
41 .cmd_on_mask = OMAP3430_VC_CMD_ON_MASK,
42 .cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT,
43 .cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT,
44 .cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT,
45};
46
47struct omap_vc_instance_data omap3_vc1_data = {
48 .vc_common = &omap3_vc_common,
49 .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET,
50 .smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT,
51 .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK,
52 .smps_volra_shift = OMAP3430_VOLRA0_SHIFT,
53 .smps_volra_mask = OMAP3430_VOLRA0_MASK,
54};
55
56struct omap_vc_instance_data omap3_vc2_data = {
57 .vc_common = &omap3_vc_common,
58 .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET,
59 .smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
60 .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK,
61 .smps_volra_shift = OMAP3430_VOLRA1_SHIFT,
62 .smps_volra_mask = OMAP3430_VOLRA1_MASK,
63};
diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
new file mode 100644
index 000000000000..a98da8ddec52
--- /dev/null
+++ b/arch/arm/mach-omap2/vc44xx_data.c
@@ -0,0 +1,75 @@
1/*
2 * OMAP4 Voltage Controller (VC) data
3 *
4 * Copyright (C) 2007, 2010 Texas Instruments, Inc.
5 * Rajendra Nayak <rnayak@ti.com>
6 * Lesly A M <x0080970@ti.com>
7 * Thara Gopinath <thara@ti.com>
8 *
9 * Copyright (C) 2008, 2011 Nokia Corporation
10 * Kalle Jokiniemi
11 * Paul Walmsley
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#include <linux/io.h>
18#include <linux/err.h>
19#include <linux/init.h>
20
21#include <plat/common.h>
22
23#include "prm44xx.h"
24#include "prm-regbits-44xx.h"
25#include "voltage.h"
26
27#include "vc.h"
28
29/*
30 * VC data common to 44xx chips
31 * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
32 */
33static const struct omap_vc_common_data omap4_vc_common = {
34 .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
35 .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
36 .bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET,
37 .data_shift = OMAP4430_DATA_SHIFT,
38 .slaveaddr_shift = OMAP4430_SLAVEADDR_SHIFT,
39 .regaddr_shift = OMAP4430_REGADDR_SHIFT,
40 .valid = OMAP4430_VALID_MASK,
41 .cmd_on_shift = OMAP4430_ON_SHIFT,
42 .cmd_on_mask = OMAP4430_ON_MASK,
43 .cmd_onlp_shift = OMAP4430_ONLP_SHIFT,
44 .cmd_ret_shift = OMAP4430_RET_SHIFT,
45 .cmd_off_shift = OMAP4430_OFF_SHIFT,
46};
47
48/* VC instance data for each controllable voltage line */
49struct omap_vc_instance_data omap4_vc_mpu_data = {
50 .vc_common = &omap4_vc_common,
51 .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET,
52 .smps_sa_shift = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT,
53 .smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK,
54 .smps_volra_shift = OMAP4430_VOLRA_VDD_MPU_L_SHIFT,
55 .smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK,
56};
57
58struct omap_vc_instance_data omap4_vc_iva_data = {
59 .vc_common = &omap4_vc_common,
60 .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET,
61 .smps_sa_shift = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT,
62 .smps_sa_mask = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK,
63 .smps_volra_shift = OMAP4430_VOLRA_VDD_IVA_L_SHIFT,
64 .smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK,
65};
66
67struct omap_vc_instance_data omap4_vc_core_data = {
68 .vc_common = &omap4_vc_common,
69 .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET,
70 .smps_sa_shift = OMAP4430_SA_VDD_CORE_L_0_6_SHIFT,
71 .smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK,
72 .smps_volra_shift = OMAP4430_VOLRA_VDD_CORE_L_SHIFT,
73 .smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK,
74};
75
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 3c9bcdce612b..c6facf7becf8 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -7,8 +7,9 @@
7 * Rajendra Nayak <rnayak@ti.com> 7 * Rajendra Nayak <rnayak@ti.com>
8 * Lesly A M <x0080970@ti.com> 8 * Lesly A M <x0080970@ti.com>
9 * 9 *
10 * Copyright (C) 2008 Nokia Corporation 10 * Copyright (C) 2008, 2011 Nokia Corporation
11 * Kalle Jokiniemi 11 * Kalle Jokiniemi
12 * Paul Walmsley
12 * 13 *
13 * Copyright (C) 2010 Texas Instruments, Inc. 14 * Copyright (C) 2010 Texas Instruments, Inc.
14 * Thara Gopinath <thara@ti.com> 15 * Thara Gopinath <thara@ti.com>
@@ -36,284 +37,28 @@
36 37
37#include "voltage.h" 38#include "voltage.h"
38 39
39#define VP_IDLE_TIMEOUT 200 40#include "vc.h"
40#define VP_TRANXDONE_TIMEOUT 300 41#include "vp.h"
42
41#define VOLTAGE_DIR_SIZE 16 43#define VOLTAGE_DIR_SIZE 16
42 44
43/* Voltage processor register offsets */
44struct vp_reg_offs {
45 u8 vpconfig;
46 u8 vstepmin;
47 u8 vstepmax;
48 u8 vlimitto;
49 u8 vstatus;
50 u8 voltage;
51};
52
53/* Voltage Processor bit field values, shifts and masks */
54struct vp_reg_val {
55 /* PRM module */
56 u16 prm_mod;
57 /* VPx_VPCONFIG */
58 u32 vpconfig_erroroffset;
59 u16 vpconfig_errorgain;
60 u32 vpconfig_errorgain_mask;
61 u8 vpconfig_errorgain_shift;
62 u32 vpconfig_initvoltage_mask;
63 u8 vpconfig_initvoltage_shift;
64 u32 vpconfig_timeouten;
65 u32 vpconfig_initvdd;
66 u32 vpconfig_forceupdate;
67 u32 vpconfig_vpenable;
68 /* VPx_VSTEPMIN */
69 u8 vstepmin_stepmin;
70 u16 vstepmin_smpswaittimemin;
71 u8 vstepmin_stepmin_shift;
72 u8 vstepmin_smpswaittimemin_shift;
73 /* VPx_VSTEPMAX */
74 u8 vstepmax_stepmax;
75 u16 vstepmax_smpswaittimemax;
76 u8 vstepmax_stepmax_shift;
77 u8 vstepmax_smpswaittimemax_shift;
78 /* VPx_VLIMITTO */
79 u8 vlimitto_vddmin;
80 u8 vlimitto_vddmax;
81 u16 vlimitto_timeout;
82 u8 vlimitto_vddmin_shift;
83 u8 vlimitto_vddmax_shift;
84 u8 vlimitto_timeout_shift;
85 /* PRM_IRQSTATUS*/
86 u32 tranxdone_status;
87};
88
89/* Voltage controller registers and offsets */
90struct vc_reg_info {
91 /* PRM module */
92 u16 prm_mod;
93 /* VC register offsets */
94 u8 smps_sa_reg;
95 u8 smps_volra_reg;
96 u8 bypass_val_reg;
97 u8 cmdval_reg;
98 u8 voltsetup_reg;
99 /*VC_SMPS_SA*/
100 u8 smps_sa_shift;
101 u32 smps_sa_mask;
102 /* VC_SMPS_VOL_RA */
103 u8 smps_volra_shift;
104 u32 smps_volra_mask;
105 /* VC_BYPASS_VAL */
106 u8 data_shift;
107 u8 slaveaddr_shift;
108 u8 regaddr_shift;
109 u32 valid;
110 /* VC_CMD_VAL */
111 u8 cmd_on_shift;
112 u8 cmd_onlp_shift;
113 u8 cmd_ret_shift;
114 u8 cmd_off_shift;
115 u32 cmd_on_mask;
116 /* PRM_VOLTSETUP */
117 u8 voltsetup_shift;
118 u32 voltsetup_mask;
119};
120 45
121/** 46static struct omap_vdd_info **vdd_info;
122 * omap_vdd_info - Per Voltage Domain info 47
123 *
124 * @volt_data : voltage table having the distinct voltages supported
125 * by the domain and other associated per voltage data.
126 * @pmic_info : pmic specific parameters which should be populted by
127 * the pmic drivers.
128 * @vp_offs : structure containing the offsets for various
129 * vp registers
130 * @vp_reg : the register values, shifts, masks for various
131 * vp registers
132 * @vc_reg : structure containing various various vc registers,
133 * shifts, masks etc.
134 * @voltdm : pointer to the voltage domain structure
135 * @debug_dir : debug directory for this voltage domain.
136 * @curr_volt : current voltage for this vdd.
137 * @ocp_mod : The prm module for accessing the prm irqstatus reg.
138 * @prm_irqst_reg : prm irqstatus register.
139 * @vp_enabled : flag to keep track of whether vp is enabled or not
140 * @volt_scale : API to scale the voltage of the vdd.
141 */
142struct omap_vdd_info {
143 struct omap_volt_data *volt_data;
144 struct omap_volt_pmic_info *pmic_info;
145 struct vp_reg_offs vp_offs;
146 struct vp_reg_val vp_reg;
147 struct vc_reg_info vc_reg;
148 struct voltagedomain voltdm;
149 struct dentry *debug_dir;
150 u32 curr_volt;
151 u16 ocp_mod;
152 u8 prm_irqst_reg;
153 bool vp_enabled;
154 u32 (*read_reg) (u16 mod, u8 offset);
155 void (*write_reg) (u32 val, u16 mod, u8 offset);
156 int (*volt_scale) (struct omap_vdd_info *vdd,
157 unsigned long target_volt);
158};
159
160static struct omap_vdd_info *vdd_info;
161/* 48/*
162 * Number of scalable voltage domains. 49 * Number of scalable voltage domains.
163 */ 50 */
164static int nr_scalable_vdd; 51static int nr_scalable_vdd;
165 52
166/* OMAP3 VDD sturctures */ 53/* XXX document */
167static struct omap_vdd_info omap3_vdd_info[] = { 54static s16 prm_mod_offs;
168 { 55static s16 prm_irqst_ocp_mod_offs;
169 .vp_offs = {
170 .vpconfig = OMAP3_PRM_VP1_CONFIG_OFFSET,
171 .vstepmin = OMAP3_PRM_VP1_VSTEPMIN_OFFSET,
172 .vstepmax = OMAP3_PRM_VP1_VSTEPMAX_OFFSET,
173 .vlimitto = OMAP3_PRM_VP1_VLIMITTO_OFFSET,
174 .vstatus = OMAP3_PRM_VP1_STATUS_OFFSET,
175 .voltage = OMAP3_PRM_VP1_VOLTAGE_OFFSET,
176 },
177 .voltdm = {
178 .name = "mpu",
179 },
180 },
181 {
182 .vp_offs = {
183 .vpconfig = OMAP3_PRM_VP2_CONFIG_OFFSET,
184 .vstepmin = OMAP3_PRM_VP2_VSTEPMIN_OFFSET,
185 .vstepmax = OMAP3_PRM_VP2_VSTEPMAX_OFFSET,
186 .vlimitto = OMAP3_PRM_VP2_VLIMITTO_OFFSET,
187 .vstatus = OMAP3_PRM_VP2_STATUS_OFFSET,
188 .voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET,
189 },
190 .voltdm = {
191 .name = "core",
192 },
193 },
194};
195
196#define OMAP3_NR_SCALABLE_VDD ARRAY_SIZE(omap3_vdd_info)
197
198/* OMAP4 VDD sturctures */
199static struct omap_vdd_info omap4_vdd_info[] = {
200 {
201 .vp_offs = {
202 .vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET,
203 .vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET,
204 .vstepmax = OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET,
205 .vlimitto = OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET,
206 .vstatus = OMAP4_PRM_VP_MPU_STATUS_OFFSET,
207 .voltage = OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET,
208 },
209 .voltdm = {
210 .name = "mpu",
211 },
212 },
213 {
214 .vp_offs = {
215 .vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET,
216 .vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET,
217 .vstepmax = OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET,
218 .vlimitto = OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET,
219 .vstatus = OMAP4_PRM_VP_IVA_STATUS_OFFSET,
220 .voltage = OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET,
221 },
222 .voltdm = {
223 .name = "iva",
224 },
225 },
226 {
227 .vp_offs = {
228 .vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET,
229 .vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET,
230 .vstepmax = OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET,
231 .vlimitto = OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET,
232 .vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET,
233 .voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET,
234 },
235 .voltdm = {
236 .name = "core",
237 },
238 },
239};
240
241#define OMAP4_NR_SCALABLE_VDD ARRAY_SIZE(omap4_vdd_info)
242
243/*
244 * Structures containing OMAP3430/OMAP3630 voltage supported and various
245 * voltage dependent data for each VDD.
246 */
247#define VOLT_DATA_DEFINE(_v_nom, _efuse_offs, _errminlimit, _errgain) \
248{ \
249 .volt_nominal = _v_nom, \
250 .sr_efuse_offs = _efuse_offs, \
251 .sr_errminlimit = _errminlimit, \
252 .vp_errgain = _errgain \
253}
254
255/* VDD1 */
256static struct omap_volt_data omap34xx_vddmpu_volt_data[] = {
257 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c),
258 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c),
259 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18),
260 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18),
261 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18),
262 VOLT_DATA_DEFINE(0, 0, 0, 0),
263};
264
265static struct omap_volt_data omap36xx_vddmpu_volt_data[] = {
266 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c),
267 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16),
268 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23),
269 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27),
270 VOLT_DATA_DEFINE(0, 0, 0, 0),
271};
272
273/* VDD2 */
274static struct omap_volt_data omap34xx_vddcore_volt_data[] = {
275 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c),
276 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c),
277 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18),
278 VOLT_DATA_DEFINE(0, 0, 0, 0),
279};
280
281static struct omap_volt_data omap36xx_vddcore_volt_data[] = {
282 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c),
283 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16),
284 VOLT_DATA_DEFINE(0, 0, 0, 0),
285};
286
287/*
288 * Structures containing OMAP4430 voltage supported and various
289 * voltage dependent data for each VDD.
290 */
291static struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
292 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
293 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
294 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
295 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
296 VOLT_DATA_DEFINE(0, 0, 0, 0),
297};
298
299static struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
300 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
301 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
302 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
303 VOLT_DATA_DEFINE(0, 0, 0, 0),
304};
305
306static struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
307 VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
308 VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
309 VOLT_DATA_DEFINE(0, 0, 0, 0),
310};
311 56
312static struct dentry *voltage_dir; 57static struct dentry *voltage_dir;
313 58
314/* Init function pointers */ 59/* Init function pointers */
315static void (*vc_init) (struct omap_vdd_info *vdd); 60static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
316static int (*vdd_data_configure) (struct omap_vdd_info *vdd); 61 unsigned long target_volt);
317 62
318static u32 omap3_voltage_read_reg(u16 mod, u8 offset) 63static u32 omap3_voltage_read_reg(u16 mod, u8 offset)
319{ 64{
@@ -336,6 +81,62 @@ static void omap4_voltage_write_reg(u32 val, u16 mod, u8 offset)
336 omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, mod, offset); 81 omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, mod, offset);
337} 82}
338 83
84static int __init _config_common_vdd_data(struct omap_vdd_info *vdd)
85{
86 char *sys_ck_name;
87 struct clk *sys_ck;
88 u32 sys_clk_speed, timeout_val, waittime;
89
90 /*
91 * XXX Clockfw should handle this, or this should be in a
92 * struct record
93 */
94 if (cpu_is_omap24xx() || cpu_is_omap34xx())
95 sys_ck_name = "sys_ck";
96 else if (cpu_is_omap44xx())
97 sys_ck_name = "sys_clkin_ck";
98 else
99 return -EINVAL;
100
101 /*
102 * Sys clk rate is require to calculate vp timeout value and
103 * smpswaittimemin and smpswaittimemax.
104 */
105 sys_ck = clk_get(NULL, sys_ck_name);
106 if (IS_ERR(sys_ck)) {
107 pr_warning("%s: Could not get the sys clk to calculate"
108 "various vdd_%s params\n", __func__, vdd->voltdm.name);
109 return -EINVAL;
110 }
111 sys_clk_speed = clk_get_rate(sys_ck);
112 clk_put(sys_ck);
113 /* Divide to avoid overflow */
114 sys_clk_speed /= 1000;
115
116 /* Generic voltage parameters */
117 vdd->curr_volt = 1200000;
118 vdd->volt_scale = vp_forceupdate_scale_voltage;
119 vdd->vp_enabled = false;
120
121 vdd->vp_rt_data.vpconfig_erroroffset =
122 (vdd->pmic_info->vp_erroroffset <<
123 vdd->vp_data->vp_common->vpconfig_erroroffset_shift);
124
125 timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000;
126 vdd->vp_rt_data.vlimitto_timeout = timeout_val;
127 vdd->vp_rt_data.vlimitto_vddmin = vdd->pmic_info->vp_vddmin;
128 vdd->vp_rt_data.vlimitto_vddmax = vdd->pmic_info->vp_vddmax;
129
130 waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) *
131 sys_clk_speed) / 1000;
132 vdd->vp_rt_data.vstepmin_smpswaittimemin = waittime;
133 vdd->vp_rt_data.vstepmax_smpswaittimemax = waittime;
134 vdd->vp_rt_data.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin;
135 vdd->vp_rt_data.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax;
136
137 return 0;
138}
139
339/* Voltage debugfs support */ 140/* Voltage debugfs support */
340static int vp_volt_debug_get(void *data, u64 *val) 141static int vp_volt_debug_get(void *data, u64 *val)
341{ 142{
@@ -347,7 +148,7 @@ static int vp_volt_debug_get(void *data, u64 *val)
347 return -EINVAL; 148 return -EINVAL;
348 } 149 }
349 150
350 vsel = vdd->read_reg(vdd->vp_reg.prm_mod, vdd->vp_offs.voltage); 151 vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
351 pr_notice("curr_vsel = %x\n", vsel); 152 pr_notice("curr_vsel = %x\n", vsel);
352 153
353 if (!vdd->pmic_info->vsel_to_uv) { 154 if (!vdd->pmic_info->vsel_to_uv) {
@@ -380,7 +181,6 @@ DEFINE_SIMPLE_ATTRIBUTE(nom_volt_debug_fops, nom_volt_debug_get, NULL,
380static void vp_latch_vsel(struct omap_vdd_info *vdd) 181static void vp_latch_vsel(struct omap_vdd_info *vdd)
381{ 182{
382 u32 vpconfig; 183 u32 vpconfig;
383 u16 mod;
384 unsigned long uvdc; 184 unsigned long uvdc;
385 char vsel; 185 char vsel;
386 186
@@ -397,30 +197,27 @@ static void vp_latch_vsel(struct omap_vdd_info *vdd)
397 return; 197 return;
398 } 198 }
399 199
400 mod = vdd->vp_reg.prm_mod;
401
402 vsel = vdd->pmic_info->uv_to_vsel(uvdc); 200 vsel = vdd->pmic_info->uv_to_vsel(uvdc);
403 201
404 vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); 202 vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
405 vpconfig &= ~(vdd->vp_reg.vpconfig_initvoltage_mask | 203 vpconfig &= ~(vdd->vp_data->vp_common->vpconfig_initvoltage_mask |
406 vdd->vp_reg.vpconfig_initvdd); 204 vdd->vp_data->vp_common->vpconfig_initvdd);
407 vpconfig |= vsel << vdd->vp_reg.vpconfig_initvoltage_shift; 205 vpconfig |= vsel << vdd->vp_data->vp_common->vpconfig_initvoltage_shift;
408 206
409 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 207 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
410 208
411 /* Trigger initVDD value copy to voltage processor */ 209 /* Trigger initVDD value copy to voltage processor */
412 vdd->write_reg((vpconfig | vdd->vp_reg.vpconfig_initvdd), mod, 210 vdd->write_reg((vpconfig | vdd->vp_data->vp_common->vpconfig_initvdd),
413 vdd->vp_offs.vpconfig); 211 prm_mod_offs, vdd->vp_data->vpconfig);
414 212
415 /* Clear initVDD copy trigger bit */ 213 /* Clear initVDD copy trigger bit */
416 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 214 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
417} 215}
418 216
419/* Generic voltage init functions */ 217/* Generic voltage init functions */
420static void __init vp_init(struct omap_vdd_info *vdd) 218static void __init vp_init(struct omap_vdd_info *vdd)
421{ 219{
422 u32 vp_val; 220 u32 vp_val;
423 u16 mod;
424 221
425 if (!vdd->read_reg || !vdd->write_reg) { 222 if (!vdd->read_reg || !vdd->write_reg) {
426 pr_err("%s: No read/write API for accessing vdd_%s regs\n", 223 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
@@ -428,33 +225,31 @@ static void __init vp_init(struct omap_vdd_info *vdd)
428 return; 225 return;
429 } 226 }
430 227
431 mod = vdd->vp_reg.prm_mod; 228 vp_val = vdd->vp_rt_data.vpconfig_erroroffset |
432 229 (vdd->vp_rt_data.vpconfig_errorgain <<
433 vp_val = vdd->vp_reg.vpconfig_erroroffset | 230 vdd->vp_data->vp_common->vpconfig_errorgain_shift) |
434 (vdd->vp_reg.vpconfig_errorgain << 231 vdd->vp_data->vp_common->vpconfig_timeouten;
435 vdd->vp_reg.vpconfig_errorgain_shift) | 232 vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vpconfig);
436 vdd->vp_reg.vpconfig_timeouten; 233
437 vdd->write_reg(vp_val, mod, vdd->vp_offs.vpconfig); 234 vp_val = ((vdd->vp_rt_data.vstepmin_smpswaittimemin <<
438 235 vdd->vp_data->vp_common->vstepmin_smpswaittimemin_shift) |
439 vp_val = ((vdd->vp_reg.vstepmin_smpswaittimemin << 236 (vdd->vp_rt_data.vstepmin_stepmin <<
440 vdd->vp_reg.vstepmin_smpswaittimemin_shift) | 237 vdd->vp_data->vp_common->vstepmin_stepmin_shift));
441 (vdd->vp_reg.vstepmin_stepmin << 238 vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vstepmin);
442 vdd->vp_reg.vstepmin_stepmin_shift)); 239
443 vdd->write_reg(vp_val, mod, vdd->vp_offs.vstepmin); 240 vp_val = ((vdd->vp_rt_data.vstepmax_smpswaittimemax <<
444 241 vdd->vp_data->vp_common->vstepmax_smpswaittimemax_shift) |
445 vp_val = ((vdd->vp_reg.vstepmax_smpswaittimemax << 242 (vdd->vp_rt_data.vstepmax_stepmax <<
446 vdd->vp_reg.vstepmax_smpswaittimemax_shift) | 243 vdd->vp_data->vp_common->vstepmax_stepmax_shift));
447 (vdd->vp_reg.vstepmax_stepmax << 244 vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vstepmax);
448 vdd->vp_reg.vstepmax_stepmax_shift)); 245
449 vdd->write_reg(vp_val, mod, vdd->vp_offs.vstepmax); 246 vp_val = ((vdd->vp_rt_data.vlimitto_vddmax <<
450 247 vdd->vp_data->vp_common->vlimitto_vddmax_shift) |
451 vp_val = ((vdd->vp_reg.vlimitto_vddmax << 248 (vdd->vp_rt_data.vlimitto_vddmin <<
452 vdd->vp_reg.vlimitto_vddmax_shift) | 249 vdd->vp_data->vp_common->vlimitto_vddmin_shift) |
453 (vdd->vp_reg.vlimitto_vddmin << 250 (vdd->vp_rt_data.vlimitto_timeout <<
454 vdd->vp_reg.vlimitto_vddmin_shift) | 251 vdd->vp_data->vp_common->vlimitto_timeout_shift));
455 (vdd->vp_reg.vlimitto_timeout << 252 vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vlimitto);
456 vdd->vp_reg.vlimitto_timeout_shift));
457 vdd->write_reg(vp_val, mod, vdd->vp_offs.vlimitto);
458} 253}
459 254
460static void __init vdd_debugfs_init(struct omap_vdd_info *vdd) 255static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
@@ -481,23 +276,23 @@ static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
481 } 276 }
482 277
483 (void) debugfs_create_x16("vp_errorgain", S_IRUGO, vdd->debug_dir, 278 (void) debugfs_create_x16("vp_errorgain", S_IRUGO, vdd->debug_dir,
484 &(vdd->vp_reg.vpconfig_errorgain)); 279 &(vdd->vp_rt_data.vpconfig_errorgain));
485 (void) debugfs_create_x16("vp_smpswaittimemin", S_IRUGO, 280 (void) debugfs_create_x16("vp_smpswaittimemin", S_IRUGO,
486 vdd->debug_dir, 281 vdd->debug_dir,
487 &(vdd->vp_reg.vstepmin_smpswaittimemin)); 282 &(vdd->vp_rt_data.vstepmin_smpswaittimemin));
488 (void) debugfs_create_x8("vp_stepmin", S_IRUGO, vdd->debug_dir, 283 (void) debugfs_create_x8("vp_stepmin", S_IRUGO, vdd->debug_dir,
489 &(vdd->vp_reg.vstepmin_stepmin)); 284 &(vdd->vp_rt_data.vstepmin_stepmin));
490 (void) debugfs_create_x16("vp_smpswaittimemax", S_IRUGO, 285 (void) debugfs_create_x16("vp_smpswaittimemax", S_IRUGO,
491 vdd->debug_dir, 286 vdd->debug_dir,
492 &(vdd->vp_reg.vstepmax_smpswaittimemax)); 287 &(vdd->vp_rt_data.vstepmax_smpswaittimemax));
493 (void) debugfs_create_x8("vp_stepmax", S_IRUGO, vdd->debug_dir, 288 (void) debugfs_create_x8("vp_stepmax", S_IRUGO, vdd->debug_dir,
494 &(vdd->vp_reg.vstepmax_stepmax)); 289 &(vdd->vp_rt_data.vstepmax_stepmax));
495 (void) debugfs_create_x8("vp_vddmax", S_IRUGO, vdd->debug_dir, 290 (void) debugfs_create_x8("vp_vddmax", S_IRUGO, vdd->debug_dir,
496 &(vdd->vp_reg.vlimitto_vddmax)); 291 &(vdd->vp_rt_data.vlimitto_vddmax));
497 (void) debugfs_create_x8("vp_vddmin", S_IRUGO, vdd->debug_dir, 292 (void) debugfs_create_x8("vp_vddmin", S_IRUGO, vdd->debug_dir,
498 &(vdd->vp_reg.vlimitto_vddmin)); 293 &(vdd->vp_rt_data.vlimitto_vddmin));
499 (void) debugfs_create_x16("vp_timeout", S_IRUGO, vdd->debug_dir, 294 (void) debugfs_create_x16("vp_timeout", S_IRUGO, vdd->debug_dir,
500 &(vdd->vp_reg.vlimitto_timeout)); 295 &(vdd->vp_rt_data.vlimitto_timeout));
501 (void) debugfs_create_file("curr_vp_volt", S_IRUGO, vdd->debug_dir, 296 (void) debugfs_create_file("curr_vp_volt", S_IRUGO, vdd->debug_dir,
502 (void *) vdd, &vp_volt_debug_fops); 297 (void *) vdd, &vp_volt_debug_fops);
503 (void) debugfs_create_file("curr_nominal_volt", S_IRUGO, 298 (void) debugfs_create_file("curr_nominal_volt", S_IRUGO,
@@ -510,8 +305,12 @@ static int _pre_volt_scale(struct omap_vdd_info *vdd,
510 unsigned long target_volt, u8 *target_vsel, u8 *current_vsel) 305 unsigned long target_volt, u8 *target_vsel, u8 *current_vsel)
511{ 306{
512 struct omap_volt_data *volt_data; 307 struct omap_volt_data *volt_data;
308 const struct omap_vc_common_data *vc_common;
309 const struct omap_vp_common_data *vp_common;
513 u32 vc_cmdval, vp_errgain_val; 310 u32 vc_cmdval, vp_errgain_val;
514 u16 vp_mod, vc_mod; 311
312 vc_common = vdd->vc_data->vc_common;
313 vp_common = vdd->vp_data->vp_common;
515 314
516 /* Check if suffiecient pmic info is available for this vdd */ 315 /* Check if suffiecient pmic info is available for this vdd */
517 if (!vdd->pmic_info) { 316 if (!vdd->pmic_info) {
@@ -533,33 +332,30 @@ static int _pre_volt_scale(struct omap_vdd_info *vdd,
533 return -EINVAL; 332 return -EINVAL;
534 } 333 }
535 334
536 vp_mod = vdd->vp_reg.prm_mod;
537 vc_mod = vdd->vc_reg.prm_mod;
538
539 /* Get volt_data corresponding to target_volt */ 335 /* Get volt_data corresponding to target_volt */
540 volt_data = omap_voltage_get_voltdata(&vdd->voltdm, target_volt); 336 volt_data = omap_voltage_get_voltdata(&vdd->voltdm, target_volt);
541 if (IS_ERR(volt_data)) 337 if (IS_ERR(volt_data))
542 volt_data = NULL; 338 volt_data = NULL;
543 339
544 *target_vsel = vdd->pmic_info->uv_to_vsel(target_volt); 340 *target_vsel = vdd->pmic_info->uv_to_vsel(target_volt);
545 *current_vsel = vdd->read_reg(vp_mod, vdd->vp_offs.voltage); 341 *current_vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
546 342
547 /* Setting the ON voltage to the new target voltage */ 343 /* Setting the ON voltage to the new target voltage */
548 vc_cmdval = vdd->read_reg(vc_mod, vdd->vc_reg.cmdval_reg); 344 vc_cmdval = vdd->read_reg(prm_mod_offs, vdd->vc_data->cmdval_reg);
549 vc_cmdval &= ~vdd->vc_reg.cmd_on_mask; 345 vc_cmdval &= ~vc_common->cmd_on_mask;
550 vc_cmdval |= (*target_vsel << vdd->vc_reg.cmd_on_shift); 346 vc_cmdval |= (*target_vsel << vc_common->cmd_on_shift);
551 vdd->write_reg(vc_cmdval, vc_mod, vdd->vc_reg.cmdval_reg); 347 vdd->write_reg(vc_cmdval, prm_mod_offs, vdd->vc_data->cmdval_reg);
552 348
553 /* Setting vp errorgain based on the voltage */ 349 /* Setting vp errorgain based on the voltage */
554 if (volt_data) { 350 if (volt_data) {
555 vp_errgain_val = vdd->read_reg(vp_mod, 351 vp_errgain_val = vdd->read_reg(prm_mod_offs,
556 vdd->vp_offs.vpconfig); 352 vdd->vp_data->vpconfig);
557 vdd->vp_reg.vpconfig_errorgain = volt_data->vp_errgain; 353 vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
558 vp_errgain_val &= ~vdd->vp_reg.vpconfig_errorgain_mask; 354 vp_errgain_val &= ~vp_common->vpconfig_errorgain_mask;
559 vp_errgain_val |= vdd->vp_reg.vpconfig_errorgain << 355 vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain <<
560 vdd->vp_reg.vpconfig_errorgain_shift; 356 vp_common->vpconfig_errorgain_shift;
561 vdd->write_reg(vp_errgain_val, vp_mod, 357 vdd->write_reg(vp_errgain_val, prm_mod_offs,
562 vdd->vp_offs.vpconfig); 358 vdd->vp_data->vpconfig);
563 } 359 }
564 360
565 return 0; 361 return 0;
@@ -585,7 +381,6 @@ static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
585{ 381{
586 u32 loop_cnt = 0, retries_cnt = 0; 382 u32 loop_cnt = 0, retries_cnt = 0;
587 u32 vc_valid, vc_bypass_val_reg, vc_bypass_value; 383 u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
588 u16 mod;
589 u8 target_vsel, current_vsel; 384 u8 target_vsel, current_vsel;
590 int ret; 385 int ret;
591 386
@@ -593,20 +388,19 @@ static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
593 if (ret) 388 if (ret)
594 return ret; 389 return ret;
595 390
596 mod = vdd->vc_reg.prm_mod; 391 vc_valid = vdd->vc_data->vc_common->valid;
597 392 vc_bypass_val_reg = vdd->vc_data->vc_common->bypass_val_reg;
598 vc_valid = vdd->vc_reg.valid; 393 vc_bypass_value = (target_vsel << vdd->vc_data->vc_common->data_shift) |
599 vc_bypass_val_reg = vdd->vc_reg.bypass_val_reg;
600 vc_bypass_value = (target_vsel << vdd->vc_reg.data_shift) |
601 (vdd->pmic_info->pmic_reg << 394 (vdd->pmic_info->pmic_reg <<
602 vdd->vc_reg.regaddr_shift) | 395 vdd->vc_data->vc_common->regaddr_shift) |
603 (vdd->pmic_info->i2c_slave_addr << 396 (vdd->pmic_info->i2c_slave_addr <<
604 vdd->vc_reg.slaveaddr_shift); 397 vdd->vc_data->vc_common->slaveaddr_shift);
605 398
606 vdd->write_reg(vc_bypass_value, mod, vc_bypass_val_reg); 399 vdd->write_reg(vc_bypass_value, prm_mod_offs, vc_bypass_val_reg);
607 vdd->write_reg(vc_bypass_value | vc_valid, mod, vc_bypass_val_reg); 400 vdd->write_reg(vc_bypass_value | vc_valid, prm_mod_offs,
401 vc_bypass_val_reg);
608 402
609 vc_bypass_value = vdd->read_reg(mod, vc_bypass_val_reg); 403 vc_bypass_value = vdd->read_reg(prm_mod_offs, vc_bypass_val_reg);
610 /* 404 /*
611 * Loop till the bypass command is acknowledged from the SMPS. 405 * Loop till the bypass command is acknowledged from the SMPS.
612 * NOTE: This is legacy code. The loop count and retry count needs 406 * NOTE: This is legacy code. The loop count and retry count needs
@@ -625,7 +419,8 @@ static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
625 loop_cnt = 0; 419 loop_cnt = 0;
626 udelay(10); 420 udelay(10);
627 } 421 }
628 vc_bypass_value = vdd->read_reg(mod, vc_bypass_val_reg); 422 vc_bypass_value = vdd->read_reg(prm_mod_offs,
423 vc_bypass_val_reg);
629 } 424 }
630 425
631 _post_volt_scale(vdd, target_volt, target_vsel, current_vsel); 426 _post_volt_scale(vdd, target_volt, target_vsel, current_vsel);
@@ -637,7 +432,6 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
637 unsigned long target_volt) 432 unsigned long target_volt)
638{ 433{
639 u32 vpconfig; 434 u32 vpconfig;
640 u16 mod, ocp_mod;
641 u8 target_vsel, current_vsel, prm_irqst_reg; 435 u8 target_vsel, current_vsel, prm_irqst_reg;
642 int ret, timeout = 0; 436 int ret, timeout = 0;
643 437
@@ -645,20 +439,18 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
645 if (ret) 439 if (ret)
646 return ret; 440 return ret;
647 441
648 mod = vdd->vp_reg.prm_mod; 442 prm_irqst_reg = vdd->vp_data->prm_irqst_data->prm_irqst_reg;
649 ocp_mod = vdd->ocp_mod;
650 prm_irqst_reg = vdd->prm_irqst_reg;
651 443
652 /* 444 /*
653 * Clear all pending TransactionDone interrupt/status. Typical latency 445 * Clear all pending TransactionDone interrupt/status. Typical latency
654 * is <3us 446 * is <3us
655 */ 447 */
656 while (timeout++ < VP_TRANXDONE_TIMEOUT) { 448 while (timeout++ < VP_TRANXDONE_TIMEOUT) {
657 vdd->write_reg(vdd->vp_reg.tranxdone_status, 449 vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
658 ocp_mod, prm_irqst_reg); 450 prm_irqst_ocp_mod_offs, prm_irqst_reg);
659 if (!(vdd->read_reg(ocp_mod, prm_irqst_reg) & 451 if (!(vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
660 vdd->vp_reg.tranxdone_status)) 452 vdd->vp_data->prm_irqst_data->tranxdone_status))
661 break; 453 break;
662 udelay(1); 454 udelay(1);
663 } 455 }
664 if (timeout >= VP_TRANXDONE_TIMEOUT) { 456 if (timeout >= VP_TRANXDONE_TIMEOUT) {
@@ -668,30 +460,30 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
668 } 460 }
669 461
670 /* Configure for VP-Force Update */ 462 /* Configure for VP-Force Update */
671 vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); 463 vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
672 vpconfig &= ~(vdd->vp_reg.vpconfig_initvdd | 464 vpconfig &= ~(vdd->vp_data->vp_common->vpconfig_initvdd |
673 vdd->vp_reg.vpconfig_forceupdate | 465 vdd->vp_data->vp_common->vpconfig_forceupdate |
674 vdd->vp_reg.vpconfig_initvoltage_mask); 466 vdd->vp_data->vp_common->vpconfig_initvoltage_mask);
675 vpconfig |= ((target_vsel << 467 vpconfig |= ((target_vsel <<
676 vdd->vp_reg.vpconfig_initvoltage_shift)); 468 vdd->vp_data->vp_common->vpconfig_initvoltage_shift));
677 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 469 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
678 470
679 /* Trigger initVDD value copy to voltage processor */ 471 /* Trigger initVDD value copy to voltage processor */
680 vpconfig |= vdd->vp_reg.vpconfig_initvdd; 472 vpconfig |= vdd->vp_data->vp_common->vpconfig_initvdd;
681 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 473 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
682 474
683 /* Force update of voltage */ 475 /* Force update of voltage */
684 vpconfig |= vdd->vp_reg.vpconfig_forceupdate; 476 vpconfig |= vdd->vp_data->vp_common->vpconfig_forceupdate;
685 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 477 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
686 478
687 /* 479 /*
688 * Wait for TransactionDone. Typical latency is <200us. 480 * Wait for TransactionDone. Typical latency is <200us.
689 * Depends on SMPSWAITTIMEMIN/MAX and voltage change 481 * Depends on SMPSWAITTIMEMIN/MAX and voltage change
690 */ 482 */
691 timeout = 0; 483 timeout = 0;
692 omap_test_timeout((vdd->read_reg(ocp_mod, prm_irqst_reg) & 484 omap_test_timeout((vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
693 vdd->vp_reg.tranxdone_status), 485 vdd->vp_data->prm_irqst_data->tranxdone_status),
694 VP_TRANXDONE_TIMEOUT, timeout); 486 VP_TRANXDONE_TIMEOUT, timeout);
695 if (timeout >= VP_TRANXDONE_TIMEOUT) 487 if (timeout >= VP_TRANXDONE_TIMEOUT)
696 pr_err("%s: vdd_%s TRANXDONE timeout exceeded." 488 pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
697 "TRANXDONE never got set after the voltage update\n", 489 "TRANXDONE never got set after the voltage update\n",
@@ -705,11 +497,11 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
705 */ 497 */
706 timeout = 0; 498 timeout = 0;
707 while (timeout++ < VP_TRANXDONE_TIMEOUT) { 499 while (timeout++ < VP_TRANXDONE_TIMEOUT) {
708 vdd->write_reg(vdd->vp_reg.tranxdone_status, 500 vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
709 ocp_mod, prm_irqst_reg); 501 prm_irqst_ocp_mod_offs, prm_irqst_reg);
710 if (!(vdd->read_reg(ocp_mod, prm_irqst_reg) & 502 if (!(vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
711 vdd->vp_reg.tranxdone_status)) 503 vdd->vp_data->prm_irqst_data->tranxdone_status))
712 break; 504 break;
713 udelay(1); 505 udelay(1);
714 } 506 }
715 507
@@ -718,222 +510,95 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
718 "to clear the TRANXDONE status\n", 510 "to clear the TRANXDONE status\n",
719 __func__, vdd->voltdm.name); 511 __func__, vdd->voltdm.name);
720 512
721 vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); 513 vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
722 /* Clear initVDD copy trigger bit */ 514 /* Clear initVDD copy trigger bit */
723 vpconfig &= ~vdd->vp_reg.vpconfig_initvdd;; 515 vpconfig &= ~vdd->vp_data->vp_common->vpconfig_initvdd;
724 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 516 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
725 /* Clear force bit */ 517 /* Clear force bit */
726 vpconfig &= ~vdd->vp_reg.vpconfig_forceupdate; 518 vpconfig &= ~vdd->vp_data->vp_common->vpconfig_forceupdate;
727 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 519 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
728 520
729 return 0; 521 return 0;
730} 522}
731 523
732/* OMAP3 specific voltage init functions */ 524static void __init omap3_vfsm_init(struct omap_vdd_info *vdd)
525{
526 /*
527 * Voltage Manager FSM parameters init
528 * XXX This data should be passed in from the board file
529 */
530 vdd->write_reg(OMAP3_CLKSETUP, prm_mod_offs, OMAP3_PRM_CLKSETUP_OFFSET);
531 vdd->write_reg(OMAP3_VOLTOFFSET, prm_mod_offs,
532 OMAP3_PRM_VOLTOFFSET_OFFSET);
533 vdd->write_reg(OMAP3_VOLTSETUP2, prm_mod_offs,
534 OMAP3_PRM_VOLTSETUP2_OFFSET);
535}
733 536
734/*
735 * Intializes the voltage controller registers with the PMIC and board
736 * specific parameters and voltage setup times for OMAP3.
737 */
738static void __init omap3_vc_init(struct omap_vdd_info *vdd) 537static void __init omap3_vc_init(struct omap_vdd_info *vdd)
739{ 538{
740 u32 vc_val;
741 u16 mod;
742 u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
743 static bool is_initialized; 539 static bool is_initialized;
540 u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
541 u32 vc_val;
744 542
745 if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) { 543 if (is_initialized)
746 pr_err("%s: PMIC info requried to configure vc for"
747 "vdd_%s not populated.Hence cannot initialize vc\n",
748 __func__, vdd->voltdm.name);
749 return;
750 }
751
752 if (!vdd->read_reg || !vdd->write_reg) {
753 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
754 __func__, vdd->voltdm.name);
755 return; 544 return;
756 }
757
758 mod = vdd->vc_reg.prm_mod;
759
760 /* Set up the SMPS_SA(i2c slave address in VC */
761 vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_sa_reg);
762 vc_val &= ~vdd->vc_reg.smps_sa_mask;
763 vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_reg.smps_sa_shift;
764 vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg);
765
766 /* Setup the VOLRA(pmic reg addr) in VC */
767 vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_volra_reg);
768 vc_val &= ~vdd->vc_reg.smps_volra_mask;
769 vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_reg.smps_volra_shift;
770 vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_volra_reg);
771
772 /*Configure the setup times */
773 vc_val = vdd->read_reg(mod, vdd->vc_reg.voltsetup_reg);
774 vc_val &= ~vdd->vc_reg.voltsetup_mask;
775 vc_val |= vdd->pmic_info->volt_setup_time <<
776 vdd->vc_reg.voltsetup_shift;
777 vdd->write_reg(vc_val, mod, vdd->vc_reg.voltsetup_reg);
778 545
779 /* Set up the on, inactive, retention and off voltage */ 546 /* Set up the on, inactive, retention and off voltage */
780 on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt); 547 on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
781 onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt); 548 onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
782 ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt); 549 ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
783 off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt); 550 off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
784 vc_val = ((on_vsel << vdd->vc_reg.cmd_on_shift) | 551 vc_val = ((on_vsel << vdd->vc_data->vc_common->cmd_on_shift) |
785 (onlp_vsel << vdd->vc_reg.cmd_onlp_shift) | 552 (onlp_vsel << vdd->vc_data->vc_common->cmd_onlp_shift) |
786 (ret_vsel << vdd->vc_reg.cmd_ret_shift) | 553 (ret_vsel << vdd->vc_data->vc_common->cmd_ret_shift) |
787 (off_vsel << vdd->vc_reg.cmd_off_shift)); 554 (off_vsel << vdd->vc_data->vc_common->cmd_off_shift));
788 vdd->write_reg(vc_val, mod, vdd->vc_reg.cmdval_reg); 555 vdd->write_reg(vc_val, prm_mod_offs, vdd->vc_data->cmdval_reg);
789
790 if (is_initialized)
791 return;
792 556
793 /* Generic VC parameters init */ 557 /*
794 vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, mod, 558 * Generic VC parameters init
559 * XXX This data should be abstracted out
560 */
561 vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, prm_mod_offs,
795 OMAP3_PRM_VC_CH_CONF_OFFSET); 562 OMAP3_PRM_VC_CH_CONF_OFFSET);
796 vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, mod, 563 vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, prm_mod_offs,
797 OMAP3_PRM_VC_I2C_CFG_OFFSET); 564 OMAP3_PRM_VC_I2C_CFG_OFFSET);
798 vdd->write_reg(OMAP3_CLKSETUP, mod, OMAP3_PRM_CLKSETUP_OFFSET); 565
799 vdd->write_reg(OMAP3_VOLTOFFSET, mod, OMAP3_PRM_VOLTOFFSET_OFFSET); 566 omap3_vfsm_init(vdd);
800 vdd->write_reg(OMAP3_VOLTSETUP2, mod, OMAP3_PRM_VOLTSETUP2_OFFSET); 567
801 is_initialized = true; 568 is_initialized = true;
802} 569}
803 570
804/* Sets up all the VDD related info for OMAP3 */ 571
805static int __init omap3_vdd_data_configure(struct omap_vdd_info *vdd) 572/* OMAP4 specific voltage init functions */
573static void __init omap4_vc_init(struct omap_vdd_info *vdd)
806{ 574{
807 struct clk *sys_ck; 575 static bool is_initialized;
808 u32 sys_clk_speed, timeout_val, waittime; 576 u32 vc_val;
809 577
810 if (!vdd->pmic_info) { 578 if (is_initialized)
811 pr_err("%s: PMIC info requried to configure vdd_%s not" 579 return;
812 "populated.Hence cannot initialize vdd_%s\n",
813 __func__, vdd->voltdm.name, vdd->voltdm.name);
814 return -EINVAL;
815 }
816 580
817 if (!strcmp(vdd->voltdm.name, "mpu")) { 581 /* TODO: Configure setup times and CMD_VAL values*/
818 if (cpu_is_omap3630())
819 vdd->volt_data = omap36xx_vddmpu_volt_data;
820 else
821 vdd->volt_data = omap34xx_vddmpu_volt_data;
822
823 vdd->vp_reg.tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK;
824 vdd->vc_reg.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET;
825 vdd->vc_reg.smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT;
826 vdd->vc_reg.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK;
827 vdd->vc_reg.smps_volra_shift = OMAP3430_VOLRA0_SHIFT;
828 vdd->vc_reg.smps_volra_mask = OMAP3430_VOLRA0_MASK;
829 vdd->vc_reg.voltsetup_shift = OMAP3430_SETUP_TIME1_SHIFT;
830 vdd->vc_reg.voltsetup_mask = OMAP3430_SETUP_TIME1_MASK;
831 } else if (!strcmp(vdd->voltdm.name, "core")) {
832 if (cpu_is_omap3630())
833 vdd->volt_data = omap36xx_vddcore_volt_data;
834 else
835 vdd->volt_data = omap34xx_vddcore_volt_data;
836
837 vdd->vp_reg.tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK;
838 vdd->vc_reg.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET;
839 vdd->vc_reg.smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT;
840 vdd->vc_reg.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK;
841 vdd->vc_reg.smps_volra_shift = OMAP3430_VOLRA1_SHIFT;
842 vdd->vc_reg.smps_volra_mask = OMAP3430_VOLRA1_MASK;
843 vdd->vc_reg.voltsetup_shift = OMAP3430_SETUP_TIME2_SHIFT;
844 vdd->vc_reg.voltsetup_mask = OMAP3430_SETUP_TIME2_MASK;
845 } else {
846 pr_warning("%s: vdd_%s does not exisit in OMAP3\n",
847 __func__, vdd->voltdm.name);
848 return -EINVAL;
849 }
850 582
851 /* 583 /*
852 * Sys clk rate is require to calculate vp timeout value and 584 * Generic VC parameters init
853 * smpswaittimemin and smpswaittimemax. 585 * XXX This data should be abstracted out
854 */ 586 */
855 sys_ck = clk_get(NULL, "sys_ck"); 587 vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
856 if (IS_ERR(sys_ck)) { 588 OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
857 pr_warning("%s: Could not get the sys clk to calculate" 589 OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
858 "various vdd_%s params\n", __func__, vdd->voltdm.name); 590 vdd->write_reg(vc_val, prm_mod_offs, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
859 return -EINVAL;
860 }
861 sys_clk_speed = clk_get_rate(sys_ck);
862 clk_put(sys_ck);
863 /* Divide to avoid overflow */
864 sys_clk_speed /= 1000;
865
866 /* Generic voltage parameters */
867 vdd->curr_volt = 1200000;
868 vdd->ocp_mod = OCP_MOD;
869 vdd->prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET;
870 vdd->read_reg = omap3_voltage_read_reg;
871 vdd->write_reg = omap3_voltage_write_reg;
872 vdd->volt_scale = vp_forceupdate_scale_voltage;
873 vdd->vp_enabled = false;
874 591
875 /* VC parameters */ 592 /* XXX These are magic numbers and do not belong! */
876 vdd->vc_reg.prm_mod = OMAP3430_GR_MOD; 593 vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
877 vdd->vc_reg.smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET; 594 vdd->write_reg(vc_val, prm_mod_offs, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
878 vdd->vc_reg.smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET;
879 vdd->vc_reg.bypass_val_reg = OMAP3_PRM_VC_BYPASS_VAL_OFFSET;
880 vdd->vc_reg.voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET;
881 vdd->vc_reg.data_shift = OMAP3430_DATA_SHIFT;
882 vdd->vc_reg.slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT;
883 vdd->vc_reg.regaddr_shift = OMAP3430_REGADDR_SHIFT;
884 vdd->vc_reg.valid = OMAP3430_VALID_MASK;
885 vdd->vc_reg.cmd_on_shift = OMAP3430_VC_CMD_ON_SHIFT;
886 vdd->vc_reg.cmd_on_mask = OMAP3430_VC_CMD_ON_MASK;
887 vdd->vc_reg.cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT;
888 vdd->vc_reg.cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT;
889 vdd->vc_reg.cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT;
890
891 vdd->vp_reg.prm_mod = OMAP3430_GR_MOD;
892
893 /* VPCONFIG bit fields */
894 vdd->vp_reg.vpconfig_erroroffset = (vdd->pmic_info->vp_erroroffset <<
895 OMAP3430_ERROROFFSET_SHIFT);
896 vdd->vp_reg.vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK;
897 vdd->vp_reg.vpconfig_errorgain_shift = OMAP3430_ERRORGAIN_SHIFT;
898 vdd->vp_reg.vpconfig_initvoltage_shift = OMAP3430_INITVOLTAGE_SHIFT;
899 vdd->vp_reg.vpconfig_initvoltage_mask = OMAP3430_INITVOLTAGE_MASK;
900 vdd->vp_reg.vpconfig_timeouten = OMAP3430_TIMEOUTEN_MASK;
901 vdd->vp_reg.vpconfig_initvdd = OMAP3430_INITVDD_MASK;
902 vdd->vp_reg.vpconfig_forceupdate = OMAP3430_FORCEUPDATE_MASK;
903 vdd->vp_reg.vpconfig_vpenable = OMAP3430_VPENABLE_MASK;
904
905 /* VSTEPMIN VSTEPMAX bit fields */
906 waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) *
907 sys_clk_speed) / 1000;
908 vdd->vp_reg.vstepmin_smpswaittimemin = waittime;
909 vdd->vp_reg.vstepmax_smpswaittimemax = waittime;
910 vdd->vp_reg.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin;
911 vdd->vp_reg.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax;
912 vdd->vp_reg.vstepmin_smpswaittimemin_shift =
913 OMAP3430_SMPSWAITTIMEMIN_SHIFT;
914 vdd->vp_reg.vstepmax_smpswaittimemax_shift =
915 OMAP3430_SMPSWAITTIMEMAX_SHIFT;
916 vdd->vp_reg.vstepmin_stepmin_shift = OMAP3430_VSTEPMIN_SHIFT;
917 vdd->vp_reg.vstepmax_stepmax_shift = OMAP3430_VSTEPMAX_SHIFT;
918
919 /* VLIMITTO bit fields */
920 timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000;
921 vdd->vp_reg.vlimitto_timeout = timeout_val;
922 vdd->vp_reg.vlimitto_vddmin = vdd->pmic_info->vp_vddmin;
923 vdd->vp_reg.vlimitto_vddmax = vdd->pmic_info->vp_vddmax;
924 vdd->vp_reg.vlimitto_vddmin_shift = OMAP3430_VDDMIN_SHIFT;
925 vdd->vp_reg.vlimitto_vddmax_shift = OMAP3430_VDDMAX_SHIFT;
926 vdd->vp_reg.vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT;
927 595
928 return 0; 596 is_initialized = true;
929} 597}
930 598
931/* OMAP4 specific voltage init functions */ 599static void __init omap_vc_init(struct omap_vdd_info *vdd)
932static void __init omap4_vc_init(struct omap_vdd_info *vdd)
933{ 600{
934 u32 vc_val; 601 u32 vc_val;
935 u16 mod;
936 static bool is_initialized;
937 602
938 if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) { 603 if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
939 pr_err("%s: PMIC info requried to configure vc for" 604 pr_err("%s: PMIC info requried to configure vc for"
@@ -948,173 +613,61 @@ static void __init omap4_vc_init(struct omap_vdd_info *vdd)
948 return; 613 return;
949 } 614 }
950 615
951 mod = vdd->vc_reg.prm_mod;
952
953 /* Set up the SMPS_SA(i2c slave address in VC */ 616 /* Set up the SMPS_SA(i2c slave address in VC */
954 vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_sa_reg); 617 vc_val = vdd->read_reg(prm_mod_offs,
955 vc_val &= ~vdd->vc_reg.smps_sa_mask; 618 vdd->vc_data->vc_common->smps_sa_reg);
956 vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_reg.smps_sa_shift; 619 vc_val &= ~vdd->vc_data->smps_sa_mask;
957 vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg); 620 vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_data->smps_sa_shift;
621 vdd->write_reg(vc_val, prm_mod_offs,
622 vdd->vc_data->vc_common->smps_sa_reg);
958 623
959 /* Setup the VOLRA(pmic reg addr) in VC */ 624 /* Setup the VOLRA(pmic reg addr) in VC */
960 vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_volra_reg); 625 vc_val = vdd->read_reg(prm_mod_offs,
961 vc_val &= ~vdd->vc_reg.smps_volra_mask; 626 vdd->vc_data->vc_common->smps_volra_reg);
962 vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_reg.smps_volra_shift; 627 vc_val &= ~vdd->vc_data->smps_volra_mask;
963 vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_volra_reg); 628 vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_data->smps_volra_shift;
964 629 vdd->write_reg(vc_val, prm_mod_offs,
965 /* TODO: Configure setup times and CMD_VAL values*/ 630 vdd->vc_data->vc_common->smps_volra_reg);
966 631
967 if (is_initialized) 632 /* Configure the setup times */
968 return; 633 vc_val = vdd->read_reg(prm_mod_offs, vdd->vfsm->voltsetup_reg);
969 634 vc_val &= ~vdd->vfsm->voltsetup_mask;
970 /* Generic VC parameters init */ 635 vc_val |= vdd->pmic_info->volt_setup_time <<
971 vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK | 636 vdd->vfsm->voltsetup_shift;
972 OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK | 637 vdd->write_reg(vc_val, prm_mod_offs, vdd->vfsm->voltsetup_reg);
973 OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
974 vdd->write_reg(vc_val, mod, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
975
976 vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
977 vdd->write_reg(vc_val, mod, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
978 638
979 is_initialized = true; 639 if (cpu_is_omap34xx())
640 omap3_vc_init(vdd);
641 else if (cpu_is_omap44xx())
642 omap4_vc_init(vdd);
980} 643}
981 644
982/* Sets up all the VDD related info for OMAP4 */ 645static int __init omap_vdd_data_configure(struct omap_vdd_info *vdd)
983static int __init omap4_vdd_data_configure(struct omap_vdd_info *vdd)
984{ 646{
985 struct clk *sys_ck; 647 int ret = -EINVAL;
986 u32 sys_clk_speed, timeout_val, waittime;
987 648
988 if (!vdd->pmic_info) { 649 if (!vdd->pmic_info) {
989 pr_err("%s: PMIC info requried to configure vdd_%s not" 650 pr_err("%s: PMIC info requried to configure vdd_%s not"
990 "populated.Hence cannot initialize vdd_%s\n", 651 "populated.Hence cannot initialize vdd_%s\n",
991 __func__, vdd->voltdm.name, vdd->voltdm.name); 652 __func__, vdd->voltdm.name, vdd->voltdm.name);
992 return -EINVAL; 653 goto ovdc_out;
993 } 654 }
994 655
995 if (!strcmp(vdd->voltdm.name, "mpu")) { 656 if (IS_ERR_VALUE(_config_common_vdd_data(vdd)))
996 vdd->volt_data = omap44xx_vdd_mpu_volt_data; 657 goto ovdc_out;
997 vdd->vp_reg.tranxdone_status =
998 OMAP4430_VP_MPU_TRANXDONE_ST_MASK;
999 vdd->vc_reg.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET;
1000 vdd->vc_reg.smps_sa_shift =
1001 OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT;
1002 vdd->vc_reg.smps_sa_mask =
1003 OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK;
1004 vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_MPU_L_SHIFT;
1005 vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK;
1006 vdd->vc_reg.voltsetup_reg =
1007 OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET;
1008 vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET;
1009 } else if (!strcmp(vdd->voltdm.name, "core")) {
1010 vdd->volt_data = omap44xx_vdd_core_volt_data;
1011 vdd->vp_reg.tranxdone_status =
1012 OMAP4430_VP_CORE_TRANXDONE_ST_MASK;
1013 vdd->vc_reg.cmdval_reg =
1014 OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET;
1015 vdd->vc_reg.smps_sa_shift = OMAP4430_SA_VDD_CORE_L_0_6_SHIFT;
1016 vdd->vc_reg.smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK;
1017 vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_CORE_L_SHIFT;
1018 vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK;
1019 vdd->vc_reg.voltsetup_reg =
1020 OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET;
1021 vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET;
1022 } else if (!strcmp(vdd->voltdm.name, "iva")) {
1023 vdd->volt_data = omap44xx_vdd_iva_volt_data;
1024 vdd->vp_reg.tranxdone_status =
1025 OMAP4430_VP_IVA_TRANXDONE_ST_MASK;
1026 vdd->vc_reg.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET;
1027 vdd->vc_reg.smps_sa_shift =
1028 OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT;
1029 vdd->vc_reg.smps_sa_mask =
1030 OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK;
1031 vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_IVA_L_SHIFT;
1032 vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK;
1033 vdd->vc_reg.voltsetup_reg =
1034 OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET;
1035 vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET;
1036 } else {
1037 pr_warning("%s: vdd_%s does not exisit in OMAP4\n",
1038 __func__, vdd->voltdm.name);
1039 return -EINVAL;
1040 }
1041 658
1042 /* 659 if (cpu_is_omap34xx()) {
1043 * Sys clk rate is require to calculate vp timeout value and 660 vdd->read_reg = omap3_voltage_read_reg;
1044 * smpswaittimemin and smpswaittimemax. 661 vdd->write_reg = omap3_voltage_write_reg;
1045 */ 662 ret = 0;
1046 sys_ck = clk_get(NULL, "sys_clkin_ck"); 663 } else if (cpu_is_omap44xx()) {
1047 if (IS_ERR(sys_ck)) { 664 vdd->read_reg = omap4_voltage_read_reg;
1048 pr_warning("%s: Could not get the sys clk to calculate" 665 vdd->write_reg = omap4_voltage_write_reg;
1049 "various vdd_%s params\n", __func__, vdd->voltdm.name); 666 ret = 0;
1050 return -EINVAL;
1051 } 667 }
1052 sys_clk_speed = clk_get_rate(sys_ck);
1053 clk_put(sys_ck);
1054 /* Divide to avoid overflow */
1055 sys_clk_speed /= 1000;
1056
1057 /* Generic voltage parameters */
1058 vdd->curr_volt = 1200000;
1059 vdd->ocp_mod = OMAP4430_PRM_OCP_SOCKET_INST;
1060 vdd->read_reg = omap4_voltage_read_reg;
1061 vdd->write_reg = omap4_voltage_write_reg;
1062 vdd->volt_scale = vp_forceupdate_scale_voltage;
1063 vdd->vp_enabled = false;
1064 668
1065 /* VC parameters */ 669ovdc_out:
1066 vdd->vc_reg.prm_mod = OMAP4430_PRM_DEVICE_INST; 670 return ret;
1067 vdd->vc_reg.smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET;
1068 vdd->vc_reg.smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET;
1069 vdd->vc_reg.bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET;
1070 vdd->vc_reg.data_shift = OMAP4430_DATA_SHIFT;
1071 vdd->vc_reg.slaveaddr_shift = OMAP4430_SLAVEADDR_SHIFT;
1072 vdd->vc_reg.regaddr_shift = OMAP4430_REGADDR_SHIFT;
1073 vdd->vc_reg.valid = OMAP4430_VALID_MASK;
1074 vdd->vc_reg.cmd_on_shift = OMAP4430_ON_SHIFT;
1075 vdd->vc_reg.cmd_on_mask = OMAP4430_ON_MASK;
1076 vdd->vc_reg.cmd_onlp_shift = OMAP4430_ONLP_SHIFT;
1077 vdd->vc_reg.cmd_ret_shift = OMAP4430_RET_SHIFT;
1078 vdd->vc_reg.cmd_off_shift = OMAP4430_OFF_SHIFT;
1079
1080 vdd->vp_reg.prm_mod = OMAP4430_PRM_DEVICE_INST;
1081
1082 /* VPCONFIG bit fields */
1083 vdd->vp_reg.vpconfig_erroroffset = (vdd->pmic_info->vp_erroroffset <<
1084 OMAP4430_ERROROFFSET_SHIFT);
1085 vdd->vp_reg.vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK;
1086 vdd->vp_reg.vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT;
1087 vdd->vp_reg.vpconfig_initvoltage_shift = OMAP4430_INITVOLTAGE_SHIFT;
1088 vdd->vp_reg.vpconfig_initvoltage_mask = OMAP4430_INITVOLTAGE_MASK;
1089 vdd->vp_reg.vpconfig_timeouten = OMAP4430_TIMEOUTEN_MASK;
1090 vdd->vp_reg.vpconfig_initvdd = OMAP4430_INITVDD_MASK;
1091 vdd->vp_reg.vpconfig_forceupdate = OMAP4430_FORCEUPDATE_MASK;
1092 vdd->vp_reg.vpconfig_vpenable = OMAP4430_VPENABLE_MASK;
1093
1094 /* VSTEPMIN VSTEPMAX bit fields */
1095 waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) *
1096 sys_clk_speed) / 1000;
1097 vdd->vp_reg.vstepmin_smpswaittimemin = waittime;
1098 vdd->vp_reg.vstepmax_smpswaittimemax = waittime;
1099 vdd->vp_reg.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin;
1100 vdd->vp_reg.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax;
1101 vdd->vp_reg.vstepmin_smpswaittimemin_shift =
1102 OMAP4430_SMPSWAITTIMEMIN_SHIFT;
1103 vdd->vp_reg.vstepmax_smpswaittimemax_shift =
1104 OMAP4430_SMPSWAITTIMEMAX_SHIFT;
1105 vdd->vp_reg.vstepmin_stepmin_shift = OMAP4430_VSTEPMIN_SHIFT;
1106 vdd->vp_reg.vstepmax_stepmax_shift = OMAP4430_VSTEPMAX_SHIFT;
1107
1108 /* VLIMITTO bit fields */
1109 timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000;
1110 vdd->vp_reg.vlimitto_timeout = timeout_val;
1111 vdd->vp_reg.vlimitto_vddmin = vdd->pmic_info->vp_vddmin;
1112 vdd->vp_reg.vlimitto_vddmax = vdd->pmic_info->vp_vddmax;
1113 vdd->vp_reg.vlimitto_vddmin_shift = OMAP4430_VDDMIN_SHIFT;
1114 vdd->vp_reg.vlimitto_vddmax_shift = OMAP4430_VDDMAX_SHIFT;
1115 vdd->vp_reg.vlimitto_timeout_shift = OMAP4430_TIMEOUT_SHIFT;
1116
1117 return 0;
1118} 671}
1119 672
1120/* Public functions */ 673/* Public functions */
@@ -1162,8 +715,7 @@ unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
1162 return 0; 715 return 0;
1163 } 716 }
1164 717
1165 curr_vsel = vdd->read_reg(vdd->vp_reg.prm_mod, 718 curr_vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
1166 vdd->vp_offs.voltage);
1167 719
1168 if (!vdd->pmic_info || !vdd->pmic_info->vsel_to_uv) { 720 if (!vdd->pmic_info || !vdd->pmic_info->vsel_to_uv) {
1169 pr_warning("%s: PMIC function to convert vsel to voltage" 721 pr_warning("%s: PMIC function to convert vsel to voltage"
@@ -1185,7 +737,6 @@ void omap_vp_enable(struct voltagedomain *voltdm)
1185{ 737{
1186 struct omap_vdd_info *vdd; 738 struct omap_vdd_info *vdd;
1187 u32 vpconfig; 739 u32 vpconfig;
1188 u16 mod;
1189 740
1190 if (!voltdm || IS_ERR(voltdm)) { 741 if (!voltdm || IS_ERR(voltdm)) {
1191 pr_warning("%s: VDD specified does not exist!\n", __func__); 742 pr_warning("%s: VDD specified does not exist!\n", __func__);
@@ -1199,8 +750,6 @@ void omap_vp_enable(struct voltagedomain *voltdm)
1199 return; 750 return;
1200 } 751 }
1201 752
1202 mod = vdd->vp_reg.prm_mod;
1203
1204 /* If VP is already enabled, do nothing. Return */ 753 /* If VP is already enabled, do nothing. Return */
1205 if (vdd->vp_enabled) 754 if (vdd->vp_enabled)
1206 return; 755 return;
@@ -1208,9 +757,9 @@ void omap_vp_enable(struct voltagedomain *voltdm)
1208 vp_latch_vsel(vdd); 757 vp_latch_vsel(vdd);
1209 758
1210 /* Enable VP */ 759 /* Enable VP */
1211 vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); 760 vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
1212 vpconfig |= vdd->vp_reg.vpconfig_vpenable; 761 vpconfig |= vdd->vp_data->vp_common->vpconfig_vpenable;
1213 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 762 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
1214 vdd->vp_enabled = true; 763 vdd->vp_enabled = true;
1215} 764}
1216 765
@@ -1225,7 +774,6 @@ void omap_vp_disable(struct voltagedomain *voltdm)
1225{ 774{
1226 struct omap_vdd_info *vdd; 775 struct omap_vdd_info *vdd;
1227 u32 vpconfig; 776 u32 vpconfig;
1228 u16 mod;
1229 int timeout; 777 int timeout;
1230 778
1231 if (!voltdm || IS_ERR(voltdm)) { 779 if (!voltdm || IS_ERR(voltdm)) {
@@ -1240,8 +788,6 @@ void omap_vp_disable(struct voltagedomain *voltdm)
1240 return; 788 return;
1241 } 789 }
1242 790
1243 mod = vdd->vp_reg.prm_mod;
1244
1245 /* If VP is already disabled, do nothing. Return */ 791 /* If VP is already disabled, do nothing. Return */
1246 if (!vdd->vp_enabled) { 792 if (!vdd->vp_enabled) {
1247 pr_warning("%s: Trying to disable VP for vdd_%s when" 793 pr_warning("%s: Trying to disable VP for vdd_%s when"
@@ -1250,14 +796,14 @@ void omap_vp_disable(struct voltagedomain *voltdm)
1250 } 796 }
1251 797
1252 /* Disable VP */ 798 /* Disable VP */
1253 vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); 799 vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
1254 vpconfig &= ~vdd->vp_reg.vpconfig_vpenable; 800 vpconfig &= ~vdd->vp_data->vp_common->vpconfig_vpenable;
1255 vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); 801 vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
1256 802
1257 /* 803 /*
1258 * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us 804 * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us
1259 */ 805 */
1260 omap_test_timeout((vdd->read_reg(mod, vdd->vp_offs.vstatus)), 806 omap_test_timeout((vdd->read_reg(prm_mod_offs, vdd->vp_data->vstatus)),
1261 VP_IDLE_TIMEOUT, timeout); 807 VP_IDLE_TIMEOUT, timeout);
1262 808
1263 if (timeout >= VP_IDLE_TIMEOUT) 809 if (timeout >= VP_IDLE_TIMEOUT)
@@ -1510,8 +1056,8 @@ struct voltagedomain *omap_voltage_domain_lookup(char *name)
1510 } 1056 }
1511 1057
1512 for (i = 0; i < nr_scalable_vdd; i++) { 1058 for (i = 0; i < nr_scalable_vdd; i++) {
1513 if (!(strcmp(name, vdd_info[i].voltdm.name))) 1059 if (!(strcmp(name, vdd_info[i]->voltdm.name)))
1514 return &vdd_info[i].voltdm; 1060 return &vdd_info[i]->voltdm;
1515 } 1061 }
1516 1062
1517 return ERR_PTR(-EINVAL); 1063 return ERR_PTR(-EINVAL);
@@ -1539,35 +1085,24 @@ int __init omap_voltage_late_init(void)
1539 pr_err("%s: Unable to create voltage debugfs main dir\n", 1085 pr_err("%s: Unable to create voltage debugfs main dir\n",
1540 __func__); 1086 __func__);
1541 for (i = 0; i < nr_scalable_vdd; i++) { 1087 for (i = 0; i < nr_scalable_vdd; i++) {
1542 if (vdd_data_configure(&vdd_info[i])) 1088 if (omap_vdd_data_configure(vdd_info[i]))
1543 continue; 1089 continue;
1544 vc_init(&vdd_info[i]); 1090 omap_vc_init(vdd_info[i]);
1545 vp_init(&vdd_info[i]); 1091 vp_init(vdd_info[i]);
1546 vdd_debugfs_init(&vdd_info[i]); 1092 vdd_debugfs_init(vdd_info[i]);
1547 } 1093 }
1548 1094
1549 return 0; 1095 return 0;
1550} 1096}
1551 1097
1552/** 1098/* XXX document */
1553 * omap_voltage_early_init()- Volatage driver early init 1099int __init omap_voltage_early_init(s16 prm_mod, s16 prm_irqst_ocp_mod,
1554 */ 1100 struct omap_vdd_info *omap_vdd_array[],
1555static int __init omap_voltage_early_init(void) 1101 u8 omap_vdd_count)
1556{ 1102{
1557 if (cpu_is_omap34xx()) { 1103 prm_mod_offs = prm_mod;
1558 vdd_info = omap3_vdd_info; 1104 prm_irqst_ocp_mod_offs = prm_irqst_ocp_mod;
1559 nr_scalable_vdd = OMAP3_NR_SCALABLE_VDD; 1105 vdd_info = omap_vdd_array;
1560 vc_init = omap3_vc_init; 1106 nr_scalable_vdd = omap_vdd_count;
1561 vdd_data_configure = omap3_vdd_data_configure;
1562 } else if (cpu_is_omap44xx()) {
1563 vdd_info = omap4_vdd_info;
1564 nr_scalable_vdd = OMAP4_NR_SCALABLE_VDD;
1565 vc_init = omap4_vc_init;
1566 vdd_data_configure = omap4_vdd_data_configure;
1567 } else {
1568 pr_warning("%s: voltage driver support not added\n", __func__);
1569 }
1570
1571 return 0; 1107 return 0;
1572} 1108}
1573core_initcall(omap_voltage_early_init);
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 5bd204e55c32..e9f5408244e0 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -16,6 +16,10 @@
16 16
17#include <linux/err.h> 17#include <linux/err.h>
18 18
19#include "vc.h"
20#include "vp.h"
21
22/* XXX document */
19#define VOLTSCALE_VPFORCEUPDATE 1 23#define VOLTSCALE_VPFORCEUPDATE 1
20#define VOLTSCALE_VCBYPASS 2 24#define VOLTSCALE_VCBYPASS 2
21 25
@@ -27,36 +31,22 @@
27#define OMAP3_VOLTOFFSET 0xff 31#define OMAP3_VOLTOFFSET 0xff
28#define OMAP3_VOLTSETUP2 0xff 32#define OMAP3_VOLTSETUP2 0xff
29 33
30/* Voltage value defines */ 34/**
31#define OMAP3430_VDD_MPU_OPP1_UV 975000 35 * struct omap_vfsm_instance_data - per-voltage manager FSM register/bitfield
32#define OMAP3430_VDD_MPU_OPP2_UV 1075000 36 * data
33#define OMAP3430_VDD_MPU_OPP3_UV 1200000 37 * @voltsetup_mask: SETUP_TIME* bitmask in the PRM_VOLTSETUP* register
34#define OMAP3430_VDD_MPU_OPP4_UV 1270000 38 * @voltsetup_reg: register offset of PRM_VOLTSETUP from PRM base
35#define OMAP3430_VDD_MPU_OPP5_UV 1350000 39 * @voltsetup_shift: SETUP_TIME* field shift in the PRM_VOLTSETUP* register
36 40 *
37#define OMAP3430_VDD_CORE_OPP1_UV 975000 41 * XXX What about VOLTOFFSET/VOLTCTRL?
38#define OMAP3430_VDD_CORE_OPP2_UV 1050000 42 * XXX It is not necessary to have both a _mask and a _shift for the same
39#define OMAP3430_VDD_CORE_OPP3_UV 1150000 43 * bitfield - remove one!
40 44 */
41#define OMAP3630_VDD_MPU_OPP50_UV 1012500 45struct omap_vfsm_instance_data {
42#define OMAP3630_VDD_MPU_OPP100_UV 1200000 46 u32 voltsetup_mask;
43#define OMAP3630_VDD_MPU_OPP120_UV 1325000 47 u8 voltsetup_reg;
44#define OMAP3630_VDD_MPU_OPP1G_UV 1375000 48 u8 voltsetup_shift;
45 49};
46#define OMAP3630_VDD_CORE_OPP50_UV 1000000
47#define OMAP3630_VDD_CORE_OPP100_UV 1200000
48
49#define OMAP4430_VDD_MPU_OPP50_UV 930000
50#define OMAP4430_VDD_MPU_OPP100_UV 1100000
51#define OMAP4430_VDD_MPU_OPPTURBO_UV 1260000
52#define OMAP4430_VDD_MPU_OPPNITRO_UV 1350000
53
54#define OMAP4430_VDD_IVA_OPP50_UV 930000
55#define OMAP4430_VDD_IVA_OPP100_UV 1100000
56#define OMAP4430_VDD_IVA_OPPTURBO_UV 1260000
57
58#define OMAP4430_VDD_CORE_OPP50_UV 930000
59#define OMAP4430_VDD_CORE_OPP100_UV 1100000
60 50
61/** 51/**
62 * struct voltagedomain - omap voltage domain global structure. 52 * struct voltagedomain - omap voltage domain global structure.
@@ -113,6 +103,42 @@ struct omap_volt_pmic_info {
113 u8 (*uv_to_vsel) (unsigned long uV); 103 u8 (*uv_to_vsel) (unsigned long uV);
114}; 104};
115 105
106/**
107 * omap_vdd_info - Per Voltage Domain info
108 *
109 * @volt_data : voltage table having the distinct voltages supported
110 * by the domain and other associated per voltage data.
111 * @pmic_info : pmic specific parameters which should be populted by
112 * the pmic drivers.
113 * @vp_data : the register values, shifts, masks for various
114 * vp registers
115 * @vp_rt_data : VP data derived at runtime, not predefined
116 * @vc_data : structure containing various various vc registers,
117 * shifts, masks etc.
118 * @vfsm : voltage manager FSM data
119 * @voltdm : pointer to the voltage domain structure
120 * @debug_dir : debug directory for this voltage domain.
121 * @curr_volt : current voltage for this vdd.
122 * @vp_enabled : flag to keep track of whether vp is enabled or not
123 * @volt_scale : API to scale the voltage of the vdd.
124 */
125struct omap_vdd_info {
126 struct omap_volt_data *volt_data;
127 struct omap_volt_pmic_info *pmic_info;
128 struct omap_vp_instance_data *vp_data;
129 struct omap_vp_runtime_data vp_rt_data;
130 struct omap_vc_instance_data *vc_data;
131 const struct omap_vfsm_instance_data *vfsm;
132 struct voltagedomain voltdm;
133 struct dentry *debug_dir;
134 u32 curr_volt;
135 bool vp_enabled;
136 u32 (*read_reg) (u16 mod, u8 offset);
137 void (*write_reg) (u32 val, u16 mod, u8 offset);
138 int (*volt_scale) (struct omap_vdd_info *vdd,
139 unsigned long target_volt);
140};
141
116unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm); 142unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm);
117void omap_vp_enable(struct voltagedomain *voltdm); 143void omap_vp_enable(struct voltagedomain *voltdm);
118void omap_vp_disable(struct voltagedomain *voltdm); 144void omap_vp_disable(struct voltagedomain *voltdm);
@@ -125,6 +151,9 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
125 unsigned long volt); 151 unsigned long volt);
126unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm); 152unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm);
127struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm); 153struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm);
154int __init omap_voltage_early_init(s16 prm_mod, s16 prm_irqst_mod,
155 struct omap_vdd_info *omap_vdd_array[],
156 u8 omap_vdd_count);
128#ifdef CONFIG_PM 157#ifdef CONFIG_PM
129int omap_voltage_register_pmic(struct voltagedomain *voltdm, 158int omap_voltage_register_pmic(struct voltagedomain *voltdm,
130 struct omap_volt_pmic_info *pmic_info); 159 struct omap_volt_pmic_info *pmic_info);
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
new file mode 100644
index 000000000000..def230fd2fde
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
@@ -0,0 +1,95 @@
1/*
2 * OMAP3 voltage domain data
3 *
4 * Copyright (C) 2007, 2010 Texas Instruments, Inc.
5 * Rajendra Nayak <rnayak@ti.com>
6 * Lesly A M <x0080970@ti.com>
7 * Thara Gopinath <thara@ti.com>
8 *
9 * Copyright (C) 2008, 2011 Nokia Corporation
10 * Kalle Jokiniemi
11 * Paul Walmsley
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#include <linux/kernel.h>
18#include <linux/err.h>
19#include <linux/init.h>
20
21#include <plat/common.h>
22#include <plat/cpu.h>
23
24#include "prm-regbits-34xx.h"
25#include "omap_opp_data.h"
26#include "voltage.h"
27#include "vc.h"
28#include "vp.h"
29
30/*
31 * VDD data
32 */
33
34static const struct omap_vfsm_instance_data omap3_vdd1_vfsm_data = {
35 .voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,
36 .voltsetup_shift = OMAP3430_SETUP_TIME1_SHIFT,
37 .voltsetup_mask = OMAP3430_SETUP_TIME1_MASK,
38};
39
40static struct omap_vdd_info omap3_vdd1_info = {
41 .vp_data = &omap3_vp1_data,
42 .vc_data = &omap3_vc1_data,
43 .vfsm = &omap3_vdd1_vfsm_data,
44 .voltdm = {
45 .name = "mpu",
46 },
47};
48
49static const struct omap_vfsm_instance_data omap3_vdd2_vfsm_data = {
50 .voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,
51 .voltsetup_shift = OMAP3430_SETUP_TIME2_SHIFT,
52 .voltsetup_mask = OMAP3430_SETUP_TIME2_MASK,
53};
54
55static struct omap_vdd_info omap3_vdd2_info = {
56 .vp_data = &omap3_vp2_data,
57 .vc_data = &omap3_vc2_data,
58 .vfsm = &omap3_vdd2_vfsm_data,
59 .voltdm = {
60 .name = "core",
61 },
62};
63
64/* OMAP3 VDD structures */
65static struct omap_vdd_info *omap3_vdd_info[] = {
66 &omap3_vdd1_info,
67 &omap3_vdd2_info,
68};
69
70/* OMAP3 specific voltage init functions */
71static int __init omap3xxx_voltage_early_init(void)
72{
73 s16 prm_mod = OMAP3430_GR_MOD;
74 s16 prm_irqst_ocp_mod = OCP_MOD;
75
76 if (!cpu_is_omap34xx())
77 return 0;
78
79 /*
80 * XXX Will depend on the process, validation, and binning
81 * for the currently-running IC
82 */
83 if (cpu_is_omap3630()) {
84 omap3_vdd1_info.volt_data = omap36xx_vddmpu_volt_data;
85 omap3_vdd2_info.volt_data = omap36xx_vddcore_volt_data;
86 } else {
87 omap3_vdd1_info.volt_data = omap34xx_vddmpu_volt_data;
88 omap3_vdd2_info.volt_data = omap34xx_vddcore_volt_data;
89 }
90
91 return omap_voltage_early_init(prm_mod, prm_irqst_ocp_mod,
92 omap3_vdd_info,
93 ARRAY_SIZE(omap3_vdd_info));
94};
95core_initcall(omap3xxx_voltage_early_init);
diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
new file mode 100644
index 000000000000..cb64996de0e1
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
@@ -0,0 +1,102 @@
1/*
2 * OMAP3/OMAP4 Voltage Management Routines
3 *
4 * Author: Thara Gopinath <thara@ti.com>
5 *
6 * Copyright (C) 2007 Texas Instruments, Inc.
7 * Rajendra Nayak <rnayak@ti.com>
8 * Lesly A M <x0080970@ti.com>
9 *
10 * Copyright (C) 2008 Nokia Corporation
11 * Kalle Jokiniemi
12 *
13 * Copyright (C) 2010 Texas Instruments, Inc.
14 * Thara Gopinath <thara@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20#include <linux/kernel.h>
21#include <linux/err.h>
22#include <linux/init.h>
23
24#include <plat/common.h>
25
26#include "prm-regbits-44xx.h"
27#include "prm44xx.h"
28#include "prcm44xx.h"
29#include "prminst44xx.h"
30#include "voltage.h"
31#include "omap_opp_data.h"
32#include "vc.h"
33#include "vp.h"
34
35static const struct omap_vfsm_instance_data omap4_vdd_mpu_vfsm_data = {
36 .voltsetup_reg = OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
37};
38
39static struct omap_vdd_info omap4_vdd_mpu_info = {
40 .vp_data = &omap4_vp_mpu_data,
41 .vc_data = &omap4_vc_mpu_data,
42 .vfsm = &omap4_vdd_mpu_vfsm_data,
43 .voltdm = {
44 .name = "mpu",
45 },
46};
47
48static const struct omap_vfsm_instance_data omap4_vdd_iva_vfsm_data = {
49 .voltsetup_reg = OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET,
50};
51
52static struct omap_vdd_info omap4_vdd_iva_info = {
53 .vp_data = &omap4_vp_iva_data,
54 .vc_data = &omap4_vc_iva_data,
55 .vfsm = &omap4_vdd_iva_vfsm_data,
56 .voltdm = {
57 .name = "iva",
58 },
59};
60
61static const struct omap_vfsm_instance_data omap4_vdd_core_vfsm_data = {
62 .voltsetup_reg = OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
63};
64
65static struct omap_vdd_info omap4_vdd_core_info = {
66 .vp_data = &omap4_vp_core_data,
67 .vc_data = &omap4_vc_core_data,
68 .vfsm = &omap4_vdd_core_vfsm_data,
69 .voltdm = {
70 .name = "core",
71 },
72};
73
74/* OMAP4 VDD structures */
75static struct omap_vdd_info *omap4_vdd_info[] = {
76 &omap4_vdd_mpu_info,
77 &omap4_vdd_iva_info,
78 &omap4_vdd_core_info,
79};
80
81/* OMAP4 specific voltage init functions */
82static int __init omap44xx_voltage_early_init(void)
83{
84 s16 prm_mod = OMAP4430_PRM_DEVICE_INST;
85 s16 prm_irqst_ocp_mod = OMAP4430_PRM_OCP_SOCKET_INST;
86
87 if (!cpu_is_omap44xx())
88 return 0;
89
90 /*
91 * XXX Will depend on the process, validation, and binning
92 * for the currently-running IC
93 */
94 omap4_vdd_mpu_info.volt_data = omap44xx_vdd_mpu_volt_data;
95 omap4_vdd_iva_info.volt_data = omap44xx_vdd_iva_volt_data;
96 omap4_vdd_core_info.volt_data = omap44xx_vdd_core_volt_data;
97
98 return omap_voltage_early_init(prm_mod, prm_irqst_ocp_mod,
99 omap4_vdd_info,
100 ARRAY_SIZE(omap4_vdd_info));
101};
102core_initcall(omap44xx_voltage_early_init);
diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
new file mode 100644
index 000000000000..7ce134f7de79
--- /dev/null
+++ b/arch/arm/mach-omap2/vp.h
@@ -0,0 +1,143 @@
1/*
2 * OMAP3/4 Voltage Processor (VP) structure and macro definitions
3 *
4 * Copyright (C) 2007, 2010 Texas Instruments, Inc.
5 * Rajendra Nayak <rnayak@ti.com>
6 * Lesly A M <x0080970@ti.com>
7 * Thara Gopinath <thara@ti.com>
8 *
9 * Copyright (C) 2008, 2011 Nokia Corporation
10 * Kalle Jokiniemi
11 * Paul Walmsley
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License version
15 * 2 as published by the Free Software Foundation.
16 */
17#ifndef __ARCH_ARM_MACH_OMAP2_VP_H
18#define __ARCH_ARM_MACH_OMAP2_VP_H
19
20#include <linux/kernel.h>
21
22/* XXX document */
23#define VP_IDLE_TIMEOUT 200
24#define VP_TRANXDONE_TIMEOUT 300
25
26
27/**
28 * struct omap_vp_common_data - register data common to all VDDs
29 * @vpconfig_errorgain_mask: ERRORGAIN bitmask in the PRM_VP*_CONFIG reg
30 * @vpconfig_initvoltage_mask: INITVOLTAGE bitmask in the PRM_VP*_CONFIG reg
31 * @vpconfig_timeouten_mask: TIMEOUT bitmask in the PRM_VP*_CONFIG reg
32 * @vpconfig_initvdd: INITVDD bitmask in the PRM_VP*_CONFIG reg
33 * @vpconfig_forceupdate: FORCEUPDATE bitmask in the PRM_VP*_CONFIG reg
34 * @vpconfig_vpenable: VPENABLE bitmask in the PRM_VP*_CONFIG reg
35 * @vpconfig_erroroffset_shift: ERROROFFSET field shift in PRM_VP*_CONFIG reg
36 * @vpconfig_errorgain_shift: ERRORGAIN field shift in PRM_VP*_CONFIG reg
37 * @vpconfig_initvoltage_shift: INITVOLTAGE field shift in PRM_VP*_CONFIG reg
38 * @vpconfig_stepmin_shift: VSTEPMIN field shift in the PRM_VP*_VSTEPMIN reg
39 * @vpconfig_smpswaittimemin_shift: SMPSWAITTIMEMIN field shift in PRM_VP*_VSTEPMIN reg
40 * @vpconfig_stepmax_shift: VSTEPMAX field shift in the PRM_VP*_VSTEPMAX reg
41 * @vpconfig_smpswaittimemax_shift: SMPSWAITTIMEMAX field shift in PRM_VP*_VSTEPMAX reg
42 * @vpconfig_vlimitto_vddmin_shift: VDDMIN field shift in PRM_VP*_VLIMITTO reg
43 * @vpconfig_vlimitto_vddmax_shift: VDDMAX field shift in PRM_VP*_VLIMITTO reg
44 * @vpconfig_vlimitto_timeout_shift: TIMEOUT field shift in PRM_VP*_VLIMITTO reg
45 *
46 * XXX It it not necessary to have both a mask and a shift for the same
47 * bitfield - remove one
48 * XXX Many of these fields are wrongly named -- e.g., vpconfig_smps* -- fix!
49 */
50struct omap_vp_common_data {
51 u32 vpconfig_errorgain_mask;
52 u32 vpconfig_initvoltage_mask;
53 u32 vpconfig_timeouten;
54 u32 vpconfig_initvdd;
55 u32 vpconfig_forceupdate;
56 u32 vpconfig_vpenable;
57 u8 vpconfig_erroroffset_shift;
58 u8 vpconfig_errorgain_shift;
59 u8 vpconfig_initvoltage_shift;
60 u8 vstepmin_stepmin_shift;
61 u8 vstepmin_smpswaittimemin_shift;
62 u8 vstepmax_stepmax_shift;
63 u8 vstepmax_smpswaittimemax_shift;
64 u8 vlimitto_vddmin_shift;
65 u8 vlimitto_vddmax_shift;
66 u8 vlimitto_timeout_shift;
67};
68
69/**
70 * struct omap_vp_prm_irqst_data - PRM_IRQSTATUS_MPU.VP_TRANXDONE_ST data
71 * @prm_irqst_reg: reg offset for PRM_IRQSTATUS_MPU from top of PRM
72 * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
73 *
74 * XXX prm_irqst_reg does not belong here
75 * XXX Note that on OMAP3, VP_TRANXDONE interrupt may not work due to a
76 * hardware bug
77 * XXX This structure is probably not needed
78 */
79struct omap_vp_prm_irqst_data {
80 u8 prm_irqst_reg;
81 u32 tranxdone_status;
82};
83
84/**
85 * struct omap_vp_instance_data - VP register offsets (per-VDD)
86 * @vp_common: pointer to struct omap_vp_common_data * for this SoC
87 * @prm_irqst_data: pointer to struct omap_vp_prm_irqst_data for this VDD
88 * @vpconfig: PRM_VP*_CONFIG reg offset from PRM start
89 * @vstepmin: PRM_VP*_VSTEPMIN reg offset from PRM start
90 * @vlimitto: PRM_VP*_VLIMITTO reg offset from PRM start
91 * @vstatus: PRM_VP*_VSTATUS reg offset from PRM start
92 * @voltage: PRM_VP*_VOLTAGE reg offset from PRM start
93 *
94 * XXX vp_common is probably not needed since it is per-SoC
95 */
96struct omap_vp_instance_data {
97 const struct omap_vp_common_data *vp_common;
98 const struct omap_vp_prm_irqst_data *prm_irqst_data;
99 u8 vpconfig;
100 u8 vstepmin;
101 u8 vstepmax;
102 u8 vlimitto;
103 u8 vstatus;
104 u8 voltage;
105};
106
107/**
108 * struct omap_vp_runtime_data - VP data populated at runtime by code
109 * @vpconfig_erroroffset: value of ERROROFFSET bitfield in PRM_VP*_CONFIG
110 * @vpconfig_errorgain: value of ERRORGAIN bitfield in PRM_VP*_CONFIG
111 * @vstepmin_smpswaittimemin: value of SMPSWAITTIMEMIN bitfield in PRM_VP*_VSTEPMIN
112 * @vstepmax_smpswaittimemax: value of SMPSWAITTIMEMAX bitfield in PRM_VP*_VSTEPMAX
113 * @vlimitto_timeout: value of TIMEOUT bitfield in PRM_VP*_VLIMITTO
114 * @vstepmin_stepmin: value of VSTEPMIN bitfield in PRM_VP*_VSTEPMIN
115 * @vstepmax_stepmax: value of VSTEPMAX bitfield in PRM_VP*_VSTEPMAX
116 * @vlimitto_vddmin: value of VDDMIN bitfield in PRM_VP*_VLIMITTO
117 * @vlimitto_vddmax: value of VDDMAX bitfield in PRM_VP*_VLIMITTO
118 *
119 * XXX Is this structure really needed? Why not just program the
120 * device directly? They are in PRM space, therefore in the WKUP
121 * powerdomain, so register contents should not be lost in off-mode.
122 * XXX Some of these fields are incorrectly named, e.g., vstep*
123 */
124struct omap_vp_runtime_data {
125 u32 vpconfig_erroroffset;
126 u16 vpconfig_errorgain;
127 u16 vstepmin_smpswaittimemin;
128 u16 vstepmax_smpswaittimemax;
129 u16 vlimitto_timeout;
130 u8 vstepmin_stepmin;
131 u8 vstepmax_stepmax;
132 u8 vlimitto_vddmin;
133 u8 vlimitto_vddmax;
134};
135
136extern struct omap_vp_instance_data omap3_vp1_data;
137extern struct omap_vp_instance_data omap3_vp2_data;
138
139extern struct omap_vp_instance_data omap4_vp_mpu_data;
140extern struct omap_vp_instance_data omap4_vp_iva_data;
141extern struct omap_vp_instance_data omap4_vp_core_data;
142
143#endif
diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
new file mode 100644
index 000000000000..645217094e51
--- /dev/null
+++ b/arch/arm/mach-omap2/vp3xxx_data.c
@@ -0,0 +1,82 @@
1/*
2 * OMAP3 Voltage Processor (VP) data
3 *
4 * Copyright (C) 2007, 2010 Texas Instruments, Inc.
5 * Rajendra Nayak <rnayak@ti.com>
6 * Lesly A M <x0080970@ti.com>
7 * Thara Gopinath <thara@ti.com>
8 *
9 * Copyright (C) 2008, 2011 Nokia Corporation
10 * Kalle Jokiniemi
11 * Paul Walmsley
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/io.h>
19#include <linux/err.h>
20#include <linux/init.h>
21
22#include <plat/common.h>
23
24#include "prm-regbits-34xx.h"
25#include "voltage.h"
26
27#include "vp.h"
28
29/*
30 * VP data common to 34xx/36xx chips
31 * XXX This stuff presumably belongs in the vp3xxx.c or vp.c file.
32 */
33static const struct omap_vp_common_data omap3_vp_common = {
34 .vpconfig_erroroffset_shift = OMAP3430_ERROROFFSET_SHIFT,
35 .vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK,
36 .vpconfig_errorgain_shift = OMAP3430_ERRORGAIN_SHIFT,
37 .vpconfig_initvoltage_shift = OMAP3430_INITVOLTAGE_SHIFT,
38 .vpconfig_initvoltage_mask = OMAP3430_INITVOLTAGE_MASK,
39 .vpconfig_timeouten = OMAP3430_TIMEOUTEN_MASK,
40 .vpconfig_initvdd = OMAP3430_INITVDD_MASK,
41 .vpconfig_forceupdate = OMAP3430_FORCEUPDATE_MASK,
42 .vpconfig_vpenable = OMAP3430_VPENABLE_MASK,
43 .vstepmin_smpswaittimemin_shift = OMAP3430_SMPSWAITTIMEMIN_SHIFT,
44 .vstepmax_smpswaittimemax_shift = OMAP3430_SMPSWAITTIMEMAX_SHIFT,
45 .vstepmin_stepmin_shift = OMAP3430_VSTEPMIN_SHIFT,
46 .vstepmax_stepmax_shift = OMAP3430_VSTEPMAX_SHIFT,
47 .vlimitto_vddmin_shift = OMAP3430_VDDMIN_SHIFT,
48 .vlimitto_vddmax_shift = OMAP3430_VDDMAX_SHIFT,
49 .vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT,
50};
51
52static const struct omap_vp_prm_irqst_data omap3_vp1_prm_irqst_data = {
53 .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
54 .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
55};
56
57struct omap_vp_instance_data omap3_vp1_data = {
58 .vp_common = &omap3_vp_common,
59 .vpconfig = OMAP3_PRM_VP1_CONFIG_OFFSET,
60 .vstepmin = OMAP3_PRM_VP1_VSTEPMIN_OFFSET,
61 .vstepmax = OMAP3_PRM_VP1_VSTEPMAX_OFFSET,
62 .vlimitto = OMAP3_PRM_VP1_VLIMITTO_OFFSET,
63 .vstatus = OMAP3_PRM_VP1_STATUS_OFFSET,
64 .voltage = OMAP3_PRM_VP1_VOLTAGE_OFFSET,
65 .prm_irqst_data = &omap3_vp1_prm_irqst_data,
66};
67
68static const struct omap_vp_prm_irqst_data omap3_vp2_prm_irqst_data = {
69 .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
70 .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
71};
72
73struct omap_vp_instance_data omap3_vp2_data = {
74 .vp_common = &omap3_vp_common,
75 .vpconfig = OMAP3_PRM_VP2_CONFIG_OFFSET,
76 .vstepmin = OMAP3_PRM_VP2_VSTEPMIN_OFFSET,
77 .vstepmax = OMAP3_PRM_VP2_VSTEPMAX_OFFSET,
78 .vlimitto = OMAP3_PRM_VP2_VLIMITTO_OFFSET,
79 .vstatus = OMAP3_PRM_VP2_STATUS_OFFSET,
80 .voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET,
81 .prm_irqst_data = &omap3_vp2_prm_irqst_data,
82};
diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
new file mode 100644
index 000000000000..65d1ad63800a
--- /dev/null
+++ b/arch/arm/mach-omap2/vp44xx_data.c
@@ -0,0 +1,100 @@
1/*
2 * OMAP3 Voltage Processor (VP) data
3 *
4 * Copyright (C) 2007, 2010 Texas Instruments, Inc.
5 * Rajendra Nayak <rnayak@ti.com>
6 * Lesly A M <x0080970@ti.com>
7 * Thara Gopinath <thara@ti.com>
8 *
9 * Copyright (C) 2008, 2011 Nokia Corporation
10 * Kalle Jokiniemi
11 * Paul Walmsley
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/io.h>
19#include <linux/err.h>
20#include <linux/init.h>
21
22#include <plat/common.h>
23
24#include "prm44xx.h"
25#include "prm-regbits-44xx.h"
26#include "voltage.h"
27
28#include "vp.h"
29
30/*
31 * VP data common to 44xx chips
32 * XXX This stuff presumably belongs in the vp44xx.c or vp.c file.
33 */
34static const struct omap_vp_common_data omap4_vp_common = {
35 .vpconfig_erroroffset_shift = OMAP4430_ERROROFFSET_SHIFT,
36 .vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK,
37 .vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT,
38 .vpconfig_initvoltage_shift = OMAP4430_INITVOLTAGE_SHIFT,
39 .vpconfig_initvoltage_mask = OMAP4430_INITVOLTAGE_MASK,
40 .vpconfig_timeouten = OMAP4430_TIMEOUTEN_MASK,
41 .vpconfig_initvdd = OMAP4430_INITVDD_MASK,
42 .vpconfig_forceupdate = OMAP4430_FORCEUPDATE_MASK,
43 .vpconfig_vpenable = OMAP4430_VPENABLE_MASK,
44 .vstepmin_smpswaittimemin_shift = OMAP4430_SMPSWAITTIMEMIN_SHIFT,
45 .vstepmax_smpswaittimemax_shift = OMAP4430_SMPSWAITTIMEMAX_SHIFT,
46 .vstepmin_stepmin_shift = OMAP4430_VSTEPMIN_SHIFT,
47 .vstepmax_stepmax_shift = OMAP4430_VSTEPMAX_SHIFT,
48 .vlimitto_vddmin_shift = OMAP4430_VDDMIN_SHIFT,
49 .vlimitto_vddmax_shift = OMAP4430_VDDMAX_SHIFT,
50 .vlimitto_timeout_shift = OMAP4430_TIMEOUT_SHIFT,
51};
52
53static const struct omap_vp_prm_irqst_data omap4_vp_mpu_prm_irqst_data = {
54 .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
55 .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
56};
57
58struct omap_vp_instance_data omap4_vp_mpu_data = {
59 .vp_common = &omap4_vp_common,
60 .vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET,
61 .vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET,
62 .vstepmax = OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET,
63 .vlimitto = OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET,
64 .vstatus = OMAP4_PRM_VP_MPU_STATUS_OFFSET,
65 .voltage = OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET,
66 .prm_irqst_data = &omap4_vp_mpu_prm_irqst_data,
67};
68
69static const struct omap_vp_prm_irqst_data omap4_vp_iva_prm_irqst_data = {
70 .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
71 .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
72};
73
74struct omap_vp_instance_data omap4_vp_iva_data = {
75 .vp_common = &omap4_vp_common,
76 .vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET,
77 .vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET,
78 .vstepmax = OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET,
79 .vlimitto = OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET,
80 .vstatus = OMAP4_PRM_VP_IVA_STATUS_OFFSET,
81 .voltage = OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET,
82 .prm_irqst_data = &omap4_vp_iva_prm_irqst_data,
83};
84
85static const struct omap_vp_prm_irqst_data omap4_vp_core_prm_irqst_data = {
86 .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
87 .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
88};
89
90struct omap_vp_instance_data omap4_vp_core_data = {
91 .vp_common = &omap4_vp_common,
92 .vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET,
93 .vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET,
94 .vstepmax = OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET,
95 .vlimitto = OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET,
96 .vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET,
97 .voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET,
98 .prm_irqst_data = &omap4_vp_core_prm_irqst_data,
99};
100
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