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-rw-r--r--MAINTAINERS6
-rw-r--r--drivers/rtc/Kconfig90
-rw-r--r--drivers/rtc/Makefile1
-rw-r--r--drivers/rtc/rtc-ds1685.c2252
-rw-r--r--include/linux/rtc/ds1685.h375
5 files changed, 2724 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 6f2c849e6da3..d5ff4c3cdbac 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2963,6 +2963,12 @@ S: Supported
2963F: drivers/input/touchscreen/cyttsp* 2963F: drivers/input/touchscreen/cyttsp*
2964F: include/linux/input/cyttsp.h 2964F: include/linux/input/cyttsp.h
2965 2965
2966DALLAS/MAXIM DS1685-FAMILY REAL TIME CLOCK
2967M: Joshua Kinard <kumba@gentoo.org>
2968S: Maintained
2969F: drivers/rtc/rtc-ds1685.c
2970F: include/linux/rtc/ds1685.h
2971
2966DAMA SLAVE for AX.25 2972DAMA SLAVE for AX.25
2967M: Joerg Reuter <jreuter@yaina.de> 2973M: Joerg Reuter <jreuter@yaina.de>
2968W: http://yaina.de/jreuter/ 2974W: http://yaina.de/jreuter/
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 3bc9ddbe5cf7..0cf2e1d9cb17 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -801,6 +801,96 @@ config RTC_DRV_DS1553
801 This driver can also be built as a module. If so, the module 801 This driver can also be built as a module. If so, the module
802 will be called rtc-ds1553. 802 will be called rtc-ds1553.
803 803
804config RTC_DRV_DS1685_FAMILY
805 tristate "Dallas/Maxim DS1685 Family"
806 help
807 If you say yes here you get support for the Dallas/Maxim DS1685
808 family of real time chips. This family includes the DS1685/DS1687,
809 DS1689/DS1693, DS17285/DS17287, DS17485/DS17487, and
810 DS17885/DS17887 chips.
811
812 This driver can also be built as a module. If so, the module
813 will be called rtc-ds1685.
814
815choice
816 prompt "Subtype"
817 depends on RTC_DRV_DS1685_FAMILY
818 default RTC_DRV_DS1685
819
820config RTC_DRV_DS1685
821 bool "DS1685/DS1687"
822 help
823 This enables support for the Dallas/Maxim DS1685/DS1687 real time
824 clock chip.
825
826 This chip is commonly found in SGI O2 (IP32) and SGI Octane (IP30)
827 systems, as well as EPPC-405-UC modules by electronic system design
828 GmbH.
829
830config RTC_DRV_DS1689
831 bool "DS1689/DS1693"
832 help
833 This enables support for the Dallas/Maxim DS1689/DS1693 real time
834 clock chip.
835
836 This is an older RTC chip, supplanted by the DS1685/DS1687 above,
837 which supports a few minor features such as Vcc, Vbat, and Power
838 Cycle counters, plus a customer-specific, 8-byte ROM/Serial number.
839
840 It also works for the even older DS1688/DS1691 RTC chips, which are
841 virtually the same and carry the same model number. Both chips
842 have 114 bytes of user NVRAM.
843
844config RTC_DRV_DS17285
845 bool "DS17285/DS17287"
846 help
847 This enables support for the Dallas/Maxim DS17285/DS17287 real time
848 clock chip.
849
850 This chip features 2kb of extended NV-SRAM. It may possibly be
851 found in some SGI O2 systems (rare).
852
853config RTC_DRV_DS17485
854 bool "DS17485/DS17487"
855 help
856 This enables support for the Dallas/Maxim DS17485/DS17487 real time
857 clock chip.
858
859 This chip features 4kb of extended NV-SRAM.
860
861config RTC_DRV_DS17885
862 bool "DS17885/DS17887"
863 help
864 This enables support for the Dallas/Maxim DS17885/DS17887 real time
865 clock chip.
866
867 This chip features 8kb of extended NV-SRAM.
868
869endchoice
870
871config RTC_DS1685_PROC_REGS
872 bool "Display register values in /proc"
873 depends on RTC_DRV_DS1685_FAMILY && PROC_FS
874 help
875 Enable this to display a readout of all of the RTC registers in
876 /proc/drivers/rtc. Keep in mind that this can potentially lead
877 to lost interrupts, as reading Control Register C will clear
878 all pending IRQ flags.
879
880 Unless you are debugging this driver, choose N.
881
882config RTC_DS1685_SYSFS_REGS
883 bool "SysFS access to RTC register bits"
884 depends on RTC_DRV_DS1685_FAMILY && SYSFS
885 help
886 Enable this to provide access to the RTC control register bits
887 in /sys. Some of the bits are read-write, others are read-only.
888
889 Keep in mind that reading Control C's bits automatically clears
890 all pending IRQ flags - this can cause lost interrupts.
891
892 If you know that you need access to these bits, choose Y, Else N.
893
804config RTC_DRV_DS1742 894config RTC_DRV_DS1742
805 tristate "Maxim/Dallas DS1742/1743" 895 tristate "Maxim/Dallas DS1742/1743"
806 depends on HAS_IOMEM 896 depends on HAS_IOMEM
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 99ded8b75e95..69c87062b098 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_RTC_DRV_DS1390) += rtc-ds1390.o
54obj-$(CONFIG_RTC_DRV_DS1511) += rtc-ds1511.o 54obj-$(CONFIG_RTC_DRV_DS1511) += rtc-ds1511.o
55obj-$(CONFIG_RTC_DRV_DS1553) += rtc-ds1553.o 55obj-$(CONFIG_RTC_DRV_DS1553) += rtc-ds1553.o
56obj-$(CONFIG_RTC_DRV_DS1672) += rtc-ds1672.o 56obj-$(CONFIG_RTC_DRV_DS1672) += rtc-ds1672.o
57obj-$(CONFIG_RTC_DRV_DS1685_FAMILY) += rtc-ds1685.o
57obj-$(CONFIG_RTC_DRV_DS1742) += rtc-ds1742.o 58obj-$(CONFIG_RTC_DRV_DS1742) += rtc-ds1742.o
58obj-$(CONFIG_RTC_DRV_DS2404) += rtc-ds2404.o 59obj-$(CONFIG_RTC_DRV_DS2404) += rtc-ds2404.o
59obj-$(CONFIG_RTC_DRV_DS3232) += rtc-ds3232.o 60obj-$(CONFIG_RTC_DRV_DS3232) += rtc-ds3232.o
diff --git a/drivers/rtc/rtc-ds1685.c b/drivers/rtc/rtc-ds1685.c
new file mode 100644
index 000000000000..8c3bfcb115b7
--- /dev/null
+++ b/drivers/rtc/rtc-ds1685.c
@@ -0,0 +1,2252 @@
1/*
2 * An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time
3 * chips.
4 *
5 * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
6 * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
7 *
8 * References:
9 * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
10 * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
11 * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
12 * Application Note 90, Using the Multiplex Bus RTC Extended Features.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/bcd.h>
20#include <linux/delay.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/platform_device.h>
24#include <linux/rtc.h>
25#include <linux/workqueue.h>
26
27#include <linux/rtc/ds1685.h>
28
29#ifdef CONFIG_PROC_FS
30#include <linux/proc_fs.h>
31#endif
32
33#define DRV_VERSION "0.42.0"
34
35
36/* ----------------------------------------------------------------------- */
37/* Standard read/write functions if platform does not provide overrides */
38
39/**
40 * ds1685_read - read a value from an rtc register.
41 * @rtc: pointer to the ds1685 rtc structure.
42 * @reg: the register address to read.
43 */
44static u8
45ds1685_read(struct ds1685_priv *rtc, int reg)
46{
47 return readb((u8 __iomem *)rtc->regs +
48 (reg * rtc->regstep));
49}
50
51/**
52 * ds1685_write - write a value to an rtc register.
53 * @rtc: pointer to the ds1685 rtc structure.
54 * @reg: the register address to write.
55 * @value: value to write to the register.
56 */
57static void
58ds1685_write(struct ds1685_priv *rtc, int reg, u8 value)
59{
60 writeb(value, ((u8 __iomem *)rtc->regs +
61 (reg * rtc->regstep)));
62}
63/* ----------------------------------------------------------------------- */
64
65
66/* ----------------------------------------------------------------------- */
67/* Inlined functions */
68
69/**
70 * ds1685_rtc_bcd2bin - bcd2bin wrapper in case platform doesn't support BCD.
71 * @rtc: pointer to the ds1685 rtc structure.
72 * @val: u8 time value to consider converting.
73 * @bcd_mask: u8 mask value if BCD mode is used.
74 * @bin_mask: u8 mask value if BIN mode is used.
75 *
76 * Returns the value, converted to BIN if originally in BCD and bcd_mode TRUE.
77 */
78static inline u8
79ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask)
80{
81 if (rtc->bcd_mode)
82 return (bcd2bin(val) & bcd_mask);
83
84 return (val & bin_mask);
85}
86
87/**
88 * ds1685_rtc_bin2bcd - bin2bcd wrapper in case platform doesn't support BCD.
89 * @rtc: pointer to the ds1685 rtc structure.
90 * @val: u8 time value to consider converting.
91 * @bin_mask: u8 mask value if BIN mode is used.
92 * @bcd_mask: u8 mask value if BCD mode is used.
93 *
94 * Returns the value, converted to BCD if originally in BIN and bcd_mode TRUE.
95 */
96static inline u8
97ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask)
98{
99 if (rtc->bcd_mode)
100 return (bin2bcd(val) & bcd_mask);
101
102 return (val & bin_mask);
103}
104
105/**
106 * ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0.
107 * @rtc: pointer to the ds1685 rtc structure.
108 */
109static inline void
110ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc)
111{
112 rtc->write(rtc, RTC_CTRL_A,
113 (rtc->read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0)));
114}
115
116/**
117 * ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1.
118 * @rtc: pointer to the ds1685 rtc structure.
119 */
120static inline void
121ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc)
122{
123 rtc->write(rtc, RTC_CTRL_A,
124 (rtc->read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0));
125}
126
127/**
128 * ds1685_rtc_begin_data_access - prepare the rtc for data access.
129 * @rtc: pointer to the ds1685 rtc structure.
130 *
131 * This takes several steps to prepare the rtc for access to get/set time
132 * and alarm values from the rtc registers:
133 * - Sets the SET bit in Control Register B.
134 * - Reads Ext Control Register 4A and checks the INCR bit.
135 * - If INCR is active, a short delay is added before Ext Control Register 4A
136 * is read again in a loop until INCR is inactive.
137 * - Switches the rtc to bank 1. This allows access to all relevant
138 * data for normal rtc operation, as bank 0 contains only the nvram.
139 */
140static inline void
141ds1685_rtc_begin_data_access(struct ds1685_priv *rtc)
142{
143 /* Set the SET bit in Ctrl B */
144 rtc->write(rtc, RTC_CTRL_B,
145 (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
146
147 /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
148 while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
149 cpu_relax();
150
151 /* Switch to Bank 1 */
152 ds1685_rtc_switch_to_bank1(rtc);
153}
154
155/**
156 * ds1685_rtc_end_data_access - end data access on the rtc.
157 * @rtc: pointer to the ds1685 rtc structure.
158 *
159 * This ends what was started by ds1685_rtc_begin_data_access:
160 * - Switches the rtc back to bank 0.
161 * - Clears the SET bit in Control Register B.
162 */
163static inline void
164ds1685_rtc_end_data_access(struct ds1685_priv *rtc)
165{
166 /* Switch back to Bank 0 */
167 ds1685_rtc_switch_to_bank1(rtc);
168
169 /* Clear the SET bit in Ctrl B */
170 rtc->write(rtc, RTC_CTRL_B,
171 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
172}
173
174/**
175 * ds1685_rtc_begin_ctrl_access - prepare the rtc for ctrl access.
176 * @rtc: pointer to the ds1685 rtc structure.
177 * @flags: irq flags variable for spin_lock_irqsave.
178 *
179 * This takes several steps to prepare the rtc for access to read just the
180 * control registers:
181 * - Sets a spinlock on the rtc IRQ.
182 * - Switches the rtc to bank 1. This allows access to the two extended
183 * control registers.
184 *
185 * Only use this where you are certain another lock will not be held.
186 */
187static inline void
188ds1685_rtc_begin_ctrl_access(struct ds1685_priv *rtc, unsigned long flags)
189{
190 spin_lock_irqsave(&rtc->lock, flags);
191 ds1685_rtc_switch_to_bank1(rtc);
192}
193
194/**
195 * ds1685_rtc_end_ctrl_access - end ctrl access on the rtc.
196 * @rtc: pointer to the ds1685 rtc structure.
197 * @flags: irq flags variable for spin_unlock_irqrestore.
198 *
199 * This ends what was started by ds1685_rtc_begin_ctrl_access:
200 * - Switches the rtc back to bank 0.
201 * - Unsets the spinlock on the rtc IRQ.
202 */
203static inline void
204ds1685_rtc_end_ctrl_access(struct ds1685_priv *rtc, unsigned long flags)
205{
206 ds1685_rtc_switch_to_bank0(rtc);
207 spin_unlock_irqrestore(&rtc->lock, flags);
208}
209
210/**
211 * ds1685_rtc_get_ssn - retrieve the silicon serial number.
212 * @rtc: pointer to the ds1685 rtc structure.
213 * @ssn: u8 array to hold the bits of the silicon serial number.
214 *
215 * This number starts at 0x40, and is 8-bytes long, ending at 0x47. The
216 * first byte is the model number, the next six bytes are the serial number
217 * digits, and the final byte is a CRC check byte. Together, they form the
218 * silicon serial number.
219 *
220 * These values are stored in bank1, so ds1685_rtc_switch_to_bank1 must be
221 * called first before calling this function, else data will be read out of
222 * the bank0 NVRAM. Be sure to call ds1685_rtc_switch_to_bank0 when done.
223 */
224static inline void
225ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn)
226{
227 ssn[0] = rtc->read(rtc, RTC_BANK1_SSN_MODEL);
228 ssn[1] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_1);
229 ssn[2] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_2);
230 ssn[3] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_3);
231 ssn[4] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_4);
232 ssn[5] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_5);
233 ssn[6] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_6);
234 ssn[7] = rtc->read(rtc, RTC_BANK1_SSN_CRC);
235}
236/* ----------------------------------------------------------------------- */
237
238
239/* ----------------------------------------------------------------------- */
240/* Read/Set Time & Alarm functions */
241
242/**
243 * ds1685_rtc_read_time - reads the time registers.
244 * @dev: pointer to device structure.
245 * @tm: pointer to rtc_time structure.
246 */
247static int
248ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm)
249{
250 struct platform_device *pdev = to_platform_device(dev);
251 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
252 u8 ctrlb, century;
253 u8 seconds, minutes, hours, wday, mday, month, years;
254
255 /* Fetch the time info from the RTC registers. */
256 ds1685_rtc_begin_data_access(rtc);
257 seconds = rtc->read(rtc, RTC_SECS);
258 minutes = rtc->read(rtc, RTC_MINS);
259 hours = rtc->read(rtc, RTC_HRS);
260 wday = rtc->read(rtc, RTC_WDAY);
261 mday = rtc->read(rtc, RTC_MDAY);
262 month = rtc->read(rtc, RTC_MONTH);
263 years = rtc->read(rtc, RTC_YEAR);
264 century = rtc->read(rtc, RTC_CENTURY);
265 ctrlb = rtc->read(rtc, RTC_CTRL_B);
266 ds1685_rtc_end_data_access(rtc);
267
268 /* bcd2bin if needed, perform fixups, and store to rtc_time. */
269 years = ds1685_rtc_bcd2bin(rtc, years, RTC_YEAR_BCD_MASK,
270 RTC_YEAR_BIN_MASK);
271 century = ds1685_rtc_bcd2bin(rtc, century, RTC_CENTURY_MASK,
272 RTC_CENTURY_MASK);
273 tm->tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, RTC_SECS_BCD_MASK,
274 RTC_SECS_BIN_MASK);
275 tm->tm_min = ds1685_rtc_bcd2bin(rtc, minutes, RTC_MINS_BCD_MASK,
276 RTC_MINS_BIN_MASK);
277 tm->tm_hour = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_24_BCD_MASK,
278 RTC_HRS_24_BIN_MASK);
279 tm->tm_wday = (ds1685_rtc_bcd2bin(rtc, wday, RTC_WDAY_MASK,
280 RTC_WDAY_MASK) - 1);
281 tm->tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
282 RTC_MDAY_BIN_MASK);
283 tm->tm_mon = (ds1685_rtc_bcd2bin(rtc, month, RTC_MONTH_BCD_MASK,
284 RTC_MONTH_BIN_MASK) - 1);
285 tm->tm_year = ((years + (century * 100)) - 1900);
286 tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
287 tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */
288
289 return rtc_valid_tm(tm);
290}
291
292/**
293 * ds1685_rtc_set_time - sets the time registers.
294 * @dev: pointer to device structure.
295 * @tm: pointer to rtc_time structure.
296 */
297static int
298ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm)
299{
300 struct platform_device *pdev = to_platform_device(dev);
301 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
302 u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century;
303
304 /* Fetch the time info from rtc_time. */
305 seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK,
306 RTC_SECS_BCD_MASK);
307 minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK,
308 RTC_MINS_BCD_MASK);
309 hours = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK,
310 RTC_HRS_24_BCD_MASK);
311 wday = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK,
312 RTC_WDAY_MASK);
313 mday = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK,
314 RTC_MDAY_BCD_MASK);
315 month = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK,
316 RTC_MONTH_BCD_MASK);
317 years = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100),
318 RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK);
319 century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100),
320 RTC_CENTURY_MASK, RTC_CENTURY_MASK);
321
322 /*
323 * Perform Sanity Checks:
324 * - Months: !> 12, Month Day != 0.
325 * - Month Day !> Max days in current month.
326 * - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7.
327 */
328 if ((tm->tm_mon > 11) || (mday == 0))
329 return -EDOM;
330
331 if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year))
332 return -EDOM;
333
334 if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) ||
335 (tm->tm_sec >= 60) || (wday > 7))
336 return -EDOM;
337
338 /*
339 * Set the data mode to use and store the time values in the
340 * RTC registers.
341 */
342 ds1685_rtc_begin_data_access(rtc);
343 ctrlb = rtc->read(rtc, RTC_CTRL_B);
344 if (rtc->bcd_mode)
345 ctrlb &= ~(RTC_CTRL_B_DM);
346 else
347 ctrlb |= RTC_CTRL_B_DM;
348 rtc->write(rtc, RTC_CTRL_B, ctrlb);
349 rtc->write(rtc, RTC_SECS, seconds);
350 rtc->write(rtc, RTC_MINS, minutes);
351 rtc->write(rtc, RTC_HRS, hours);
352 rtc->write(rtc, RTC_WDAY, wday);
353 rtc->write(rtc, RTC_MDAY, mday);
354 rtc->write(rtc, RTC_MONTH, month);
355 rtc->write(rtc, RTC_YEAR, years);
356 rtc->write(rtc, RTC_CENTURY, century);
357 ds1685_rtc_end_data_access(rtc);
358
359 return 0;
360}
361
362/**
363 * ds1685_rtc_read_alarm - reads the alarm registers.
364 * @dev: pointer to device structure.
365 * @alrm: pointer to rtc_wkalrm structure.
366 *
367 * There are three primary alarm registers: seconds, minutes, and hours.
368 * A fourth alarm register for the month date is also available in bank1 for
369 * kickstart/wakeup features. The DS1685/DS1687 manual states that a
370 * "don't care" value ranging from 0xc0 to 0xff may be written into one or
371 * more of the three alarm bytes to act as a wildcard value. The fourth
372 * byte doesn't support a "don't care" value.
373 */
374static int
375ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
376{
377 struct platform_device *pdev = to_platform_device(dev);
378 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
379 u8 seconds, minutes, hours, mday, ctrlb, ctrlc;
380
381 /* Fetch the alarm info from the RTC alarm registers. */
382 ds1685_rtc_begin_data_access(rtc);
383 seconds = rtc->read(rtc, RTC_SECS_ALARM);
384 minutes = rtc->read(rtc, RTC_MINS_ALARM);
385 hours = rtc->read(rtc, RTC_HRS_ALARM);
386 mday = rtc->read(rtc, RTC_MDAY_ALARM);
387 ctrlb = rtc->read(rtc, RTC_CTRL_B);
388 ctrlc = rtc->read(rtc, RTC_CTRL_C);
389 ds1685_rtc_end_data_access(rtc);
390
391 /* Check month date. */
392 if (!(mday >= 1) && (mday <= 31))
393 return -EDOM;
394
395 /*
396 * Check the three alarm bytes.
397 *
398 * The Linux RTC system doesn't support the "don't care" capability
399 * of this RTC chip. We check for it anyways in case support is
400 * added in the future.
401 */
402 if (unlikely((seconds >= 0xc0) && (seconds <= 0xff)))
403 alrm->time.tm_sec = -1;
404 else
405 alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds,
406 RTC_SECS_BCD_MASK,
407 RTC_SECS_BIN_MASK);
408
409 if (unlikely((minutes >= 0xc0) && (minutes <= 0xff)))
410 alrm->time.tm_min = -1;
411 else
412 alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes,
413 RTC_MINS_BCD_MASK,
414 RTC_MINS_BIN_MASK);
415
416 if (unlikely((hours >= 0xc0) && (hours <= 0xff)))
417 alrm->time.tm_hour = -1;
418 else
419 alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours,
420 RTC_HRS_24_BCD_MASK,
421 RTC_HRS_24_BIN_MASK);
422
423 /* Write the data to rtc_wkalrm. */
424 alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
425 RTC_MDAY_BIN_MASK);
426 alrm->time.tm_mon = -1;
427 alrm->time.tm_year = -1;
428 alrm->time.tm_wday = -1;
429 alrm->time.tm_yday = -1;
430 alrm->time.tm_isdst = -1;
431 alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE);
432 alrm->pending = !!(ctrlc & RTC_CTRL_C_AF);
433
434 return 0;
435}
436
437/**
438 * ds1685_rtc_set_alarm - sets the alarm in registers.
439 * @dev: pointer to device structure.
440 * @alrm: pointer to rtc_wkalrm structure.
441 */
442static int
443ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
444{
445 struct platform_device *pdev = to_platform_device(dev);
446 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
447 u8 ctrlb, seconds, minutes, hours, mday;
448
449 /* Fetch the alarm info and convert to BCD. */
450 seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec,
451 RTC_SECS_BIN_MASK,
452 RTC_SECS_BCD_MASK);
453 minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min,
454 RTC_MINS_BIN_MASK,
455 RTC_MINS_BCD_MASK);
456 hours = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour,
457 RTC_HRS_24_BIN_MASK,
458 RTC_HRS_24_BCD_MASK);
459 mday = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday,
460 RTC_MDAY_BIN_MASK,
461 RTC_MDAY_BCD_MASK);
462
463 /* Check the month date for validity. */
464 if (!(mday >= 1) && (mday <= 31))
465 return -EDOM;
466
467 /*
468 * Check the three alarm bytes.
469 *
470 * The Linux RTC system doesn't support the "don't care" capability
471 * of this RTC chip because rtc_valid_tm tries to validate every
472 * field, and we only support four fields. We put the support
473 * here anyways for the future.
474 */
475 if (unlikely((seconds >= 0xc0) && (seconds <= 0xff)))
476 seconds = 0xff;
477
478 if (unlikely((minutes >= 0xc0) && (minutes <= 0xff)))
479 minutes = 0xff;
480
481 if (unlikely((hours >= 0xc0) && (hours <= 0xff)))
482 hours = 0xff;
483
484 alrm->time.tm_mon = -1;
485 alrm->time.tm_year = -1;
486 alrm->time.tm_wday = -1;
487 alrm->time.tm_yday = -1;
488 alrm->time.tm_isdst = -1;
489
490 /* Disable the alarm interrupt first. */
491 ds1685_rtc_begin_data_access(rtc);
492 ctrlb = rtc->read(rtc, RTC_CTRL_B);
493 rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE)));
494
495 /* Read ctrlc to clear RTC_CTRL_C_AF. */
496 rtc->read(rtc, RTC_CTRL_C);
497
498 /*
499 * Set the data mode to use and store the time values in the
500 * RTC registers.
501 */
502 ctrlb = rtc->read(rtc, RTC_CTRL_B);
503 if (rtc->bcd_mode)
504 ctrlb &= ~(RTC_CTRL_B_DM);
505 else
506 ctrlb |= RTC_CTRL_B_DM;
507 rtc->write(rtc, RTC_CTRL_B, ctrlb);
508 rtc->write(rtc, RTC_SECS_ALARM, seconds);
509 rtc->write(rtc, RTC_MINS_ALARM, minutes);
510 rtc->write(rtc, RTC_HRS_ALARM, hours);
511 rtc->write(rtc, RTC_MDAY_ALARM, mday);
512
513 /* Re-enable the alarm if needed. */
514 if (alrm->enabled) {
515 ctrlb = rtc->read(rtc, RTC_CTRL_B);
516 ctrlb |= RTC_CTRL_B_AIE;
517 rtc->write(rtc, RTC_CTRL_B, ctrlb);
518 }
519
520 /* Done! */
521 ds1685_rtc_end_data_access(rtc);
522
523 return 0;
524}
525/* ----------------------------------------------------------------------- */
526
527
528/* ----------------------------------------------------------------------- */
529/* /dev/rtcX Interface functions */
530
531#ifdef CONFIG_RTC_INTF_DEV
532/**
533 * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off.
534 * @dev: pointer to device structure.
535 * @enabled: flag indicating whether to enable or disable.
536 */
537static int
538ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
539{
540 struct ds1685_priv *rtc = dev_get_drvdata(dev);
541 unsigned long flags = 0;
542
543 /* Enable/disable the Alarm IRQ-Enable flag. */
544 spin_lock_irqsave(&rtc->lock, flags);
545
546 /* Flip the requisite interrupt-enable bit. */
547 if (enabled)
548 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) |
549 RTC_CTRL_B_AIE));
550 else
551 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) &
552 ~(RTC_CTRL_B_AIE)));
553
554 /* Read Control C to clear all the flag bits. */
555 rtc->read(rtc, RTC_CTRL_C);
556 spin_unlock_irqrestore(&rtc->lock, flags);
557
558 return 0;
559}
560#endif
561/* ----------------------------------------------------------------------- */
562
563
564/* ----------------------------------------------------------------------- */
565/* IRQ handler & workqueue. */
566
567/**
568 * ds1685_rtc_irq_handler - IRQ handler.
569 * @irq: IRQ number.
570 * @dev_id: platform device pointer.
571 */
572static irqreturn_t
573ds1685_rtc_irq_handler(int irq, void *dev_id)
574{
575 struct platform_device *pdev = dev_id;
576 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
577 u8 ctrlb, ctrlc;
578 unsigned long events = 0;
579 u8 num_irqs = 0;
580
581 /* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */
582 if (unlikely(!rtc))
583 return IRQ_HANDLED;
584
585 /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */
586 spin_lock(&rtc->lock);
587 ctrlb = rtc->read(rtc, RTC_CTRL_B);
588 ctrlc = rtc->read(rtc, RTC_CTRL_C);
589
590 /* Is the IRQF bit set? */
591 if (likely(ctrlc & RTC_CTRL_C_IRQF)) {
592 /*
593 * We need to determine if it was one of the standard
594 * events: PF, AF, or UF. If so, we handle them and
595 * update the RTC core.
596 */
597 if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) {
598 events = RTC_IRQF;
599
600 /* Check for a periodic interrupt. */
601 if ((ctrlb & RTC_CTRL_B_PIE) &&
602 (ctrlc & RTC_CTRL_C_PF)) {
603 events |= RTC_PF;
604 num_irqs++;
605 }
606
607 /* Check for an alarm interrupt. */
608 if ((ctrlb & RTC_CTRL_B_AIE) &&
609 (ctrlc & RTC_CTRL_C_AF)) {
610 events |= RTC_AF;
611 num_irqs++;
612 }
613
614 /* Check for an update interrupt. */
615 if ((ctrlb & RTC_CTRL_B_UIE) &&
616 (ctrlc & RTC_CTRL_C_UF)) {
617 events |= RTC_UF;
618 num_irqs++;
619 }
620
621 rtc_update_irq(rtc->dev, num_irqs, events);
622 } else {
623 /*
624 * One of the "extended" interrupts was received that
625 * is not recognized by the RTC core. These need to
626 * be handled in task context as they can call other
627 * functions and the time spent in irq context needs
628 * to be minimized. Schedule them into a workqueue
629 * and inform the RTC core that the IRQs were handled.
630 */
631 spin_unlock(&rtc->lock);
632 schedule_work(&rtc->work);
633 rtc_update_irq(rtc->dev, 0, 0);
634 return IRQ_HANDLED;
635 }
636 }
637 spin_unlock(&rtc->lock);
638
639 return events ? IRQ_HANDLED : IRQ_NONE;
640}
641
642/**
643 * ds1685_rtc_work_queue - work queue handler.
644 * @work: work_struct containing data to work on in task context.
645 */
646static void
647ds1685_rtc_work_queue(struct work_struct *work)
648{
649 struct ds1685_priv *rtc = container_of(work,
650 struct ds1685_priv, work);
651 struct platform_device *pdev = to_platform_device(&rtc->dev->dev);
652 struct mutex *rtc_mutex = &rtc->dev->ops_lock;
653 u8 ctrl4a, ctrl4b;
654
655 mutex_lock(rtc_mutex);
656
657 ds1685_rtc_switch_to_bank1(rtc);
658 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
659 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
660
661 /*
662 * Check for a kickstart interrupt. With Vcc applied, this
663 * typically means that the power button was pressed, so we
664 * begin the shutdown sequence.
665 */
666 if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) {
667 /* Briefly disable kickstarts to debounce button presses. */
668 rtc->write(rtc, RTC_EXT_CTRL_4B,
669 (rtc->read(rtc, RTC_EXT_CTRL_4B) &
670 ~(RTC_CTRL_4B_KSE)));
671
672 /* Clear the kickstart flag. */
673 rtc->write(rtc, RTC_EXT_CTRL_4A,
674 (ctrl4a & ~(RTC_CTRL_4A_KF)));
675
676
677 /*
678 * Sleep 500ms before re-enabling kickstarts. This allows
679 * adequate time to avoid reading signal jitter as additional
680 * button presses.
681 */
682 msleep(500);
683 rtc->write(rtc, RTC_EXT_CTRL_4B,
684 (rtc->read(rtc, RTC_EXT_CTRL_4B) |
685 RTC_CTRL_4B_KSE));
686
687 /* Call the platform pre-poweroff function. Else, shutdown. */
688 if (rtc->prepare_poweroff != NULL)
689 rtc->prepare_poweroff();
690 else
691 ds1685_rtc_poweroff(pdev);
692 }
693
694 /*
695 * Check for a wake-up interrupt. With Vcc applied, this is
696 * essentially a second alarm interrupt, except it takes into
697 * account the 'date' register in bank1 in addition to the
698 * standard three alarm registers.
699 */
700 if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) {
701 rtc->write(rtc, RTC_EXT_CTRL_4A,
702 (ctrl4a & ~(RTC_CTRL_4A_WF)));
703
704 /* Call the platform wake_alarm function if defined. */
705 if (rtc->wake_alarm != NULL)
706 rtc->wake_alarm();
707 else
708 dev_warn(&pdev->dev,
709 "Wake Alarm IRQ just occurred!\n");
710 }
711
712 /*
713 * Check for a ram-clear interrupt. This happens if RIE=1 and RF=0
714 * when RCE=1 in 4B. This clears all NVRAM bytes in bank0 by setting
715 * each byte to a logic 1. This has no effect on any extended
716 * NV-SRAM that might be present, nor on the time/calendar/alarm
717 * registers. After a ram-clear is completed, there is a minimum
718 * recovery time of ~150ms in which all reads/writes are locked out.
719 * NOTE: A ram-clear can still occur if RCE=1 and RIE=0. We cannot
720 * catch this scenario.
721 */
722 if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) {
723 rtc->write(rtc, RTC_EXT_CTRL_4A,
724 (ctrl4a & ~(RTC_CTRL_4A_RF)));
725 msleep(150);
726
727 /* Call the platform post_ram_clear function if defined. */
728 if (rtc->post_ram_clear != NULL)
729 rtc->post_ram_clear();
730 else
731 dev_warn(&pdev->dev,
732 "RAM-Clear IRQ just occurred!\n");
733 }
734 ds1685_rtc_switch_to_bank0(rtc);
735
736 mutex_unlock(rtc_mutex);
737}
738/* ----------------------------------------------------------------------- */
739
740
741/* ----------------------------------------------------------------------- */
742/* ProcFS interface */
743
744#ifdef CONFIG_PROC_FS
745#define NUM_REGS 6 /* Num of control registers. */
746#define NUM_BITS 8 /* Num bits per register. */
747#define NUM_SPACES 4 /* Num spaces between each bit. */
748
749/*
750 * Periodic Interrupt Rates.
751 */
752static const char *ds1685_rtc_pirq_rate[16] = {
753 "none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms",
754 "0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms",
755 "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms"
756};
757
758/*
759 * Square-Wave Output Frequencies.
760 */
761static const char *ds1685_rtc_sqw_freq[16] = {
762 "none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", "1024Hz",
763 "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", "8Hz", "4Hz", "2Hz"
764};
765
766#ifdef CONFIG_RTC_DS1685_PROC_REGS
767/**
768 * ds1685_rtc_print_regs - helper function to print register values.
769 * @hex: hex byte to convert into binary bits.
770 * @dest: destination char array.
771 *
772 * This is basically a hex->binary function, just with extra spacing between
773 * the digits. It only works on 1-byte values (8 bits).
774 */
775static char*
776ds1685_rtc_print_regs(u8 hex, char *dest)
777{
778 u32 i, j;
779 char *tmp = dest;
780
781 for (i = 0; i < NUM_BITS; i++) {
782 *tmp++ = ((hex & 0x80) != 0 ? '1' : '0');
783 for (j = 0; j < NUM_SPACES; j++)
784 *tmp++ = ' ';
785 hex <<= 1;
786 }
787 *tmp++ = '\0';
788
789 return dest;
790}
791#endif
792
793/**
794 * ds1685_rtc_proc - procfs access function.
795 * @dev: pointer to device structure.
796 * @seq: pointer to seq_file structure.
797 */
798static int
799ds1685_rtc_proc(struct device *dev, struct seq_file *seq)
800{
801 struct platform_device *pdev = to_platform_device(dev);
802 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
803 u8 ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b, ssn[8];
804 char *model = '\0';
805#ifdef CONFIG_RTC_DS1685_PROC_REGS
806 char bits[NUM_REGS][(NUM_BITS * NUM_SPACES) + NUM_BITS + 1];
807#endif
808
809 /* Read all the relevant data from the control registers. */
810 ds1685_rtc_switch_to_bank1(rtc);
811 ds1685_rtc_get_ssn(rtc, ssn);
812 ctrla = rtc->read(rtc, RTC_CTRL_A);
813 ctrlb = rtc->read(rtc, RTC_CTRL_B);
814 ctrlc = rtc->read(rtc, RTC_CTRL_C);
815 ctrld = rtc->read(rtc, RTC_CTRL_D);
816 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
817 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
818 ds1685_rtc_switch_to_bank0(rtc);
819
820 /* Determine the RTC model. */
821 switch (ssn[0]) {
822 case RTC_MODEL_DS1685:
823 model = "DS1685/DS1687\0";
824 break;
825 case RTC_MODEL_DS1689:
826 model = "DS1689/DS1693\0";
827 break;
828 case RTC_MODEL_DS17285:
829 model = "DS17285/DS17287\0";
830 break;
831 case RTC_MODEL_DS17485:
832 model = "DS17485/DS17487\0";
833 break;
834 case RTC_MODEL_DS17885:
835 model = "DS17885/DS17887\0";
836 break;
837 default:
838 model = "Unknown\0";
839 break;
840 }
841
842 /* Print out the information. */
843 seq_printf(seq,
844 "Model\t\t: %s\n"
845 "Oscillator\t: %s\n"
846 "12/24hr\t\t: %s\n"
847 "DST\t\t: %s\n"
848 "Data mode\t: %s\n"
849 "Battery\t\t: %s\n"
850 "Aux batt\t: %s\n"
851 "Update IRQ\t: %s\n"
852 "Periodic IRQ\t: %s\n"
853 "Periodic Rate\t: %s\n"
854 "SQW Freq\t: %s\n"
855#ifdef CONFIG_RTC_DS1685_PROC_REGS
856 "Serial #\t: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n"
857 "Register Status\t:\n"
858 " Ctrl A\t: UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0\n"
859 "\t\t: %s\n"
860 " Ctrl B\t: SET PIE AIE UIE SQWE DM 2412 DSE\n"
861 "\t\t: %s\n"
862 " Ctrl C\t: IRQF PF AF UF --- --- --- ---\n"
863 "\t\t: %s\n"
864 " Ctrl D\t: VRT --- --- --- --- --- --- ---\n"
865 "\t\t: %s\n"
866#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
867 " Ctrl 4A\t: VRT2 INCR BME --- PAB RF WF KF\n"
868#else
869 " Ctrl 4A\t: VRT2 INCR --- --- PAB RF WF KF\n"
870#endif
871 "\t\t: %s\n"
872 " Ctrl 4B\t: ABE E32k CS RCE PRS RIE WIE KSE\n"
873 "\t\t: %s\n",
874#else
875 "Serial #\t: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
876#endif
877 model,
878 ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"),
879 ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"),
880 ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"),
881 ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"),
882 ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"),
883 ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"),
884 ((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"),
885 ((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"),
886 (!(ctrl4b & RTC_CTRL_4B_E32K) ?
887 ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"),
888 (!((ctrl4b & RTC_CTRL_4B_E32K)) ?
889 ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"),
890#ifdef CONFIG_RTC_DS1685_PROC_REGS
891 ssn[0], ssn[1], ssn[2], ssn[3], ssn[4], ssn[5], ssn[6], ssn[7],
892 ds1685_rtc_print_regs(ctrla, bits[0]),
893 ds1685_rtc_print_regs(ctrlb, bits[1]),
894 ds1685_rtc_print_regs(ctrlc, bits[2]),
895 ds1685_rtc_print_regs(ctrld, bits[3]),
896 ds1685_rtc_print_regs(ctrl4a, bits[4]),
897 ds1685_rtc_print_regs(ctrl4b, bits[5]));
898#else
899 ssn[0], ssn[1], ssn[2], ssn[3], ssn[4], ssn[5], ssn[6], ssn[7]);
900#endif
901 return 0;
902}
903#else
904#define ds1685_rtc_proc NULL
905#endif /* CONFIG_PROC_FS */
906/* ----------------------------------------------------------------------- */
907
908
909/* ----------------------------------------------------------------------- */
910/* RTC Class operations */
911
912static const struct rtc_class_ops
913ds1685_rtc_ops = {
914 .proc = ds1685_rtc_proc,
915 .read_time = ds1685_rtc_read_time,
916 .set_time = ds1685_rtc_set_time,
917 .read_alarm = ds1685_rtc_read_alarm,
918 .set_alarm = ds1685_rtc_set_alarm,
919 .alarm_irq_enable = ds1685_rtc_alarm_irq_enable,
920};
921/* ----------------------------------------------------------------------- */
922
923
924/* ----------------------------------------------------------------------- */
925/* SysFS interface */
926
927#ifdef CONFIG_SYSFS
928/**
929 * ds1685_rtc_sysfs_nvram_read - reads rtc nvram via sysfs.
930 * @file: pointer to file structure.
931 * @kobj: pointer to kobject structure.
932 * @bin_attr: pointer to bin_attribute structure.
933 * @buf: pointer to char array to hold the output.
934 * @pos: current file position pointer.
935 * @size: size of the data to read.
936 */
937static ssize_t
938ds1685_rtc_sysfs_nvram_read(struct file *filp, struct kobject *kobj,
939 struct bin_attribute *bin_attr, char *buf,
940 loff_t pos, size_t size)
941{
942 struct platform_device *pdev =
943 to_platform_device(container_of(kobj, struct device, kobj));
944 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
945 ssize_t count;
946 unsigned long flags = 0;
947
948 spin_lock_irqsave(&rtc->lock, flags);
949 ds1685_rtc_switch_to_bank0(rtc);
950
951 /* Read NVRAM in time and bank0 registers. */
952 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
953 count++, size--) {
954 if (count < NVRAM_SZ_TIME)
955 *buf++ = rtc->read(rtc, (NVRAM_TIME_BASE + pos++));
956 else
957 *buf++ = rtc->read(rtc, (NVRAM_BANK0_BASE + pos++));
958 }
959
960#ifndef CONFIG_RTC_DRV_DS1689
961 if (size > 0) {
962 ds1685_rtc_switch_to_bank1(rtc);
963
964#ifndef CONFIG_RTC_DRV_DS1685
965 /* Enable burst-mode on DS17x85/DS17x87 */
966 rtc->write(rtc, RTC_EXT_CTRL_4A,
967 (rtc->read(rtc, RTC_EXT_CTRL_4A) |
968 RTC_CTRL_4A_BME));
969
970 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
971 * reading with burst-mode */
972 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
973 (pos - NVRAM_TOTAL_SZ_BANK0));
974#endif
975
976 /* Read NVRAM in bank1 registers. */
977 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
978 count++, size--) {
979#ifdef CONFIG_RTC_DRV_DS1685
980 /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
981 * before each read. */
982 rtc->write(rtc, RTC_BANK1_RAM_ADDR,
983 (pos - NVRAM_TOTAL_SZ_BANK0));
984#endif
985 *buf++ = rtc->read(rtc, RTC_BANK1_RAM_DATA_PORT);
986 pos++;
987 }
988
989#ifndef CONFIG_RTC_DRV_DS1685
990 /* Disable burst-mode on DS17x85/DS17x87 */
991 rtc->write(rtc, RTC_EXT_CTRL_4A,
992 (rtc->read(rtc, RTC_EXT_CTRL_4A) &
993 ~(RTC_CTRL_4A_BME)));
994#endif
995 ds1685_rtc_switch_to_bank0(rtc);
996 }
997#endif /* !CONFIG_RTC_DRV_DS1689 */
998 spin_unlock_irqrestore(&rtc->lock, flags);
999
1000 /*
1001 * XXX: Bug? this appears to cause the function to get executed
1002 * several times in succession. But it's the only way to actually get
1003 * data written out to a file.
1004 */
1005 return count;
1006}
1007
1008/**
1009 * ds1685_rtc_sysfs_nvram_write - writes rtc nvram via sysfs.
1010 * @file: pointer to file structure.
1011 * @kobj: pointer to kobject structure.
1012 * @bin_attr: pointer to bin_attribute structure.
1013 * @buf: pointer to char array to hold the input.
1014 * @pos: current file position pointer.
1015 * @size: size of the data to write.
1016 */
1017static ssize_t
1018ds1685_rtc_sysfs_nvram_write(struct file *filp, struct kobject *kobj,
1019 struct bin_attribute *bin_attr, char *buf,
1020 loff_t pos, size_t size)
1021{
1022 struct platform_device *pdev =
1023 to_platform_device(container_of(kobj, struct device, kobj));
1024 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1025 ssize_t count;
1026 unsigned long flags = 0;
1027
1028 spin_lock_irqsave(&rtc->lock, flags);
1029 ds1685_rtc_switch_to_bank0(rtc);
1030
1031 /* Write NVRAM in time and bank0 registers. */
1032 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
1033 count++, size--)
1034 if (count < NVRAM_SZ_TIME)
1035 rtc->write(rtc, (NVRAM_TIME_BASE + pos++),
1036 *buf++);
1037 else
1038 rtc->write(rtc, (NVRAM_BANK0_BASE), *buf++);
1039
1040#ifndef CONFIG_RTC_DRV_DS1689
1041 if (size > 0) {
1042 ds1685_rtc_switch_to_bank1(rtc);
1043
1044#ifndef CONFIG_RTC_DRV_DS1685
1045 /* Enable burst-mode on DS17x85/DS17x87 */
1046 rtc->write(rtc, RTC_EXT_CTRL_4A,
1047 (rtc->read(rtc, RTC_EXT_CTRL_4A) |
1048 RTC_CTRL_4A_BME));
1049
1050 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
1051 * writing with burst-mode */
1052 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
1053 (pos - NVRAM_TOTAL_SZ_BANK0));
1054#endif
1055
1056 /* Write NVRAM in bank1 registers. */
1057 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
1058 count++, size--) {
1059#ifdef CONFIG_RTC_DRV_DS1685
1060 /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
1061 * before each read. */
1062 rtc->write(rtc, RTC_BANK1_RAM_ADDR,
1063 (pos - NVRAM_TOTAL_SZ_BANK0));
1064#endif
1065 rtc->write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++);
1066 pos++;
1067 }
1068
1069#ifndef CONFIG_RTC_DRV_DS1685
1070 /* Disable burst-mode on DS17x85/DS17x87 */
1071 rtc->write(rtc, RTC_EXT_CTRL_4A,
1072 (rtc->read(rtc, RTC_EXT_CTRL_4A) &
1073 ~(RTC_CTRL_4A_BME)));
1074#endif
1075 ds1685_rtc_switch_to_bank0(rtc);
1076 }
1077#endif /* !CONFIG_RTC_DRV_DS1689 */
1078 spin_unlock_irqrestore(&rtc->lock, flags);
1079
1080 return count;
1081}
1082
1083/**
1084 * struct ds1685_rtc_sysfs_nvram_attr - sysfs attributes for rtc nvram.
1085 * @attr: nvram attributes.
1086 * @read: nvram read function.
1087 * @write: nvram write function.
1088 * @size: nvram total size (bank0 + extended).
1089 */
1090static struct bin_attribute
1091ds1685_rtc_sysfs_nvram_attr = {
1092 .attr = {
1093 .name = "nvram",
1094 .mode = S_IRUGO | S_IWUSR,
1095 },
1096 .read = ds1685_rtc_sysfs_nvram_read,
1097 .write = ds1685_rtc_sysfs_nvram_write,
1098 .size = NVRAM_TOTAL_SZ
1099};
1100
1101/**
1102 * ds1685_rtc_sysfs_battery_show - sysfs file for main battery status.
1103 * @dev: pointer to device structure.
1104 * @attr: pointer to device_attribute structure.
1105 * @buf: pointer to char array to hold the output.
1106 */
1107static ssize_t
1108ds1685_rtc_sysfs_battery_show(struct device *dev,
1109 struct device_attribute *attr, char *buf)
1110{
1111 struct platform_device *pdev = to_platform_device(dev);
1112 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1113 u8 ctrld;
1114
1115 ctrld = rtc->read(rtc, RTC_CTRL_D);
1116
1117 return snprintf(buf, 13, "%s\n",
1118 (ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A");
1119}
1120static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL);
1121
1122/**
1123 * ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status.
1124 * @dev: pointer to device structure.
1125 * @attr: pointer to device_attribute structure.
1126 * @buf: pointer to char array to hold the output.
1127 */
1128static ssize_t
1129ds1685_rtc_sysfs_auxbatt_show(struct device *dev,
1130 struct device_attribute *attr, char *buf)
1131{
1132 struct platform_device *pdev = to_platform_device(dev);
1133 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1134 u8 ctrl4a;
1135
1136 ds1685_rtc_switch_to_bank1(rtc);
1137 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
1138 ds1685_rtc_switch_to_bank0(rtc);
1139
1140 return snprintf(buf, 13, "%s\n",
1141 (ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A");
1142}
1143static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL);
1144
1145/**
1146 * ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number.
1147 * @dev: pointer to device structure.
1148 * @attr: pointer to device_attribute structure.
1149 * @buf: pointer to char array to hold the output.
1150 */
1151static ssize_t
1152ds1685_rtc_sysfs_serial_show(struct device *dev,
1153 struct device_attribute *attr, char *buf)
1154{
1155 struct platform_device *pdev = to_platform_device(dev);
1156 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1157 u8 ssn[8];
1158
1159 ds1685_rtc_switch_to_bank1(rtc);
1160 ds1685_rtc_get_ssn(rtc, ssn);
1161 ds1685_rtc_switch_to_bank0(rtc);
1162
1163 return snprintf(buf, 24, "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
1164 ssn[0], ssn[1], ssn[2], ssn[3], ssn[4], ssn[5],
1165 ssn[6], ssn[7]);
1166
1167 return 0;
1168}
1169static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL);
1170
1171/**
1172 * struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features.
1173 */
1174static struct attribute*
1175ds1685_rtc_sysfs_misc_attrs[] = {
1176 &dev_attr_battery.attr,
1177 &dev_attr_auxbatt.attr,
1178 &dev_attr_serial.attr,
1179 NULL,
1180};
1181
1182/**
1183 * struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features.
1184 */
1185static const struct attribute_group
1186ds1685_rtc_sysfs_misc_grp = {
1187 .name = "misc",
1188 .attrs = ds1685_rtc_sysfs_misc_attrs,
1189};
1190
1191#ifdef CONFIG_RTC_DS1685_SYSFS_REGS
1192/**
1193 * struct ds1685_rtc_ctrl_regs.
1194 * @name: char pointer for the bit name.
1195 * @reg: control register the bit is in.
1196 * @bit: the bit's offset in the register.
1197 */
1198struct ds1685_rtc_ctrl_regs {
1199 const char *name;
1200 const u8 reg;
1201 const u8 bit;
1202};
1203
1204/*
1205 * Ctrl register bit lookup table.
1206 */
1207static const struct ds1685_rtc_ctrl_regs
1208ds1685_ctrl_regs_table[] = {
1209 { "uip", RTC_CTRL_A, RTC_CTRL_A_UIP },
1210 { "dv2", RTC_CTRL_A, RTC_CTRL_A_DV2 },
1211 { "dv1", RTC_CTRL_A, RTC_CTRL_A_DV1 },
1212 { "dv0", RTC_CTRL_A, RTC_CTRL_A_DV0 },
1213 { "rs3", RTC_CTRL_A, RTC_CTRL_A_RS3 },
1214 { "rs2", RTC_CTRL_A, RTC_CTRL_A_RS2 },
1215 { "rs1", RTC_CTRL_A, RTC_CTRL_A_RS1 },
1216 { "rs0", RTC_CTRL_A, RTC_CTRL_A_RS0 },
1217 { "set", RTC_CTRL_B, RTC_CTRL_B_SET },
1218 { "pie", RTC_CTRL_B, RTC_CTRL_B_PIE },
1219 { "aie", RTC_CTRL_B, RTC_CTRL_B_AIE },
1220 { "uie", RTC_CTRL_B, RTC_CTRL_B_UIE },
1221 { "sqwe", RTC_CTRL_B, RTC_CTRL_B_SQWE },
1222 { "dm", RTC_CTRL_B, RTC_CTRL_B_DM },
1223 { "2412", RTC_CTRL_B, RTC_CTRL_B_2412 },
1224 { "dse", RTC_CTRL_B, RTC_CTRL_B_DSE },
1225 { "irqf", RTC_CTRL_C, RTC_CTRL_C_IRQF },
1226 { "pf", RTC_CTRL_C, RTC_CTRL_C_PF },
1227 { "af", RTC_CTRL_C, RTC_CTRL_C_AF },
1228 { "uf", RTC_CTRL_C, RTC_CTRL_C_UF },
1229 { "vrt", RTC_CTRL_D, RTC_CTRL_D_VRT },
1230 { "vrt2", RTC_EXT_CTRL_4A, RTC_CTRL_4A_VRT2 },
1231 { "incr", RTC_EXT_CTRL_4A, RTC_CTRL_4A_INCR },
1232 { "pab", RTC_EXT_CTRL_4A, RTC_CTRL_4A_PAB },
1233 { "rf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_RF },
1234 { "wf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_WF },
1235 { "kf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_KF },
1236#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
1237 { "bme", RTC_EXT_CTRL_4A, RTC_CTRL_4A_BME },
1238#endif
1239 { "abe", RTC_EXT_CTRL_4B, RTC_CTRL_4B_ABE },
1240 { "e32k", RTC_EXT_CTRL_4B, RTC_CTRL_4B_E32K },
1241 { "cs", RTC_EXT_CTRL_4B, RTC_CTRL_4B_CS },
1242 { "rce", RTC_EXT_CTRL_4B, RTC_CTRL_4B_RCE },
1243 { "prs", RTC_EXT_CTRL_4B, RTC_CTRL_4B_PRS },
1244 { "rie", RTC_EXT_CTRL_4B, RTC_CTRL_4B_RIE },
1245 { "wie", RTC_EXT_CTRL_4B, RTC_CTRL_4B_WIE },
1246 { "kse", RTC_EXT_CTRL_4B, RTC_CTRL_4B_KSE },
1247 { NULL, 0, 0 },
1248};
1249
1250/**
1251 * ds1685_rtc_sysfs_ctrl_regs_lookup - ctrl register bit lookup function.
1252 * @name: ctrl register bit to look up in ds1685_ctrl_regs_table.
1253 */
1254static const struct ds1685_rtc_ctrl_regs*
1255ds1685_rtc_sysfs_ctrl_regs_lookup(const char *name)
1256{
1257 const struct ds1685_rtc_ctrl_regs *p = ds1685_ctrl_regs_table;
1258
1259 for (; p->name != NULL; ++p)
1260 if (strcmp(p->name, name) == 0)
1261 return p;
1262
1263 return NULL;
1264}
1265
1266/**
1267 * ds1685_rtc_sysfs_ctrl_regs_show - reads a ctrl register bit via sysfs.
1268 * @dev: pointer to device structure.
1269 * @attr: pointer to device_attribute structure.
1270 * @buf: pointer to char array to hold the output.
1271 */
1272static ssize_t
1273ds1685_rtc_sysfs_ctrl_regs_show(struct device *dev,
1274 struct device_attribute *attr, char *buf)
1275{
1276 u8 tmp;
1277 struct ds1685_priv *rtc = dev_get_drvdata(dev);
1278 const struct ds1685_rtc_ctrl_regs *reg_info =
1279 ds1685_rtc_sysfs_ctrl_regs_lookup(attr->attr.name);
1280
1281 /* Make sure we actually matched something. */
1282 if (!reg_info)
1283 return -EINVAL;
1284
1285 /* No spinlock during a read -- mutex is already held. */
1286 ds1685_rtc_switch_to_bank1(rtc);
1287 tmp = rtc->read(rtc, reg_info->reg) & reg_info->bit;
1288 ds1685_rtc_switch_to_bank0(rtc);
1289
1290 return snprintf(buf, 2, "%d\n", (tmp ? 1 : 0));
1291}
1292
1293/**
1294 * ds1685_rtc_sysfs_ctrl_regs_store - writes a ctrl register bit via sysfs.
1295 * @dev: pointer to device structure.
1296 * @attr: pointer to device_attribute structure.
1297 * @buf: pointer to char array to hold the output.
1298 * @count: number of bytes written.
1299 */
1300static ssize_t
1301ds1685_rtc_sysfs_ctrl_regs_store(struct device *dev,
1302 struct device_attribute *attr,
1303 const char *buf, size_t count)
1304{
1305 struct ds1685_priv *rtc = dev_get_drvdata(dev);
1306 u8 reg = 0, bit = 0, tmp;
1307 unsigned long flags = 0;
1308 long int val = 0;
1309 const struct ds1685_rtc_ctrl_regs *reg_info =
1310 ds1685_rtc_sysfs_ctrl_regs_lookup(attr->attr.name);
1311
1312 /* We only accept numbers. */
1313 if (kstrtol(buf, 10, &val) < 0)
1314 return -EINVAL;
1315
1316 /* bits are binary, 0 or 1 only. */
1317 if ((val != 0) && (val != 1))
1318 return -ERANGE;
1319
1320 /* Make sure we actually matched something. */
1321 if (!reg_info)
1322 return -EINVAL;
1323
1324 reg = reg_info->reg;
1325 bit = reg_info->bit;
1326
1327 /* Safe to spinlock during a write. */
1328 ds1685_rtc_begin_ctrl_access(rtc, flags);
1329 tmp = rtc->read(rtc, reg);
1330 rtc->write(rtc, reg, (val ? (tmp | bit) : (tmp & ~(bit))));
1331 ds1685_rtc_end_ctrl_access(rtc, flags);
1332
1333 return count;
1334}
1335
1336/**
1337 * DS1685_RTC_SYSFS_CTRL_REG_RO - device_attribute for read-only register bit.
1338 * @bit: bit to read.
1339 */
1340#define DS1685_RTC_SYSFS_CTRL_REG_RO(bit) \
1341 static DEVICE_ATTR(bit, S_IRUGO, \
1342 ds1685_rtc_sysfs_ctrl_regs_show, NULL)
1343
1344/**
1345 * DS1685_RTC_SYSFS_CTRL_REG_RW - device_attribute for read-write register bit.
1346 * @bit: bit to read or write.
1347 */
1348#define DS1685_RTC_SYSFS_CTRL_REG_RW(bit) \
1349 static DEVICE_ATTR(bit, S_IRUGO | S_IWUSR, \
1350 ds1685_rtc_sysfs_ctrl_regs_show, \
1351 ds1685_rtc_sysfs_ctrl_regs_store)
1352
1353/*
1354 * Control Register A bits.
1355 */
1356DS1685_RTC_SYSFS_CTRL_REG_RO(uip);
1357DS1685_RTC_SYSFS_CTRL_REG_RW(dv2);
1358DS1685_RTC_SYSFS_CTRL_REG_RW(dv1);
1359DS1685_RTC_SYSFS_CTRL_REG_RO(dv0);
1360DS1685_RTC_SYSFS_CTRL_REG_RW(rs3);
1361DS1685_RTC_SYSFS_CTRL_REG_RW(rs2);
1362DS1685_RTC_SYSFS_CTRL_REG_RW(rs1);
1363DS1685_RTC_SYSFS_CTRL_REG_RW(rs0);
1364
1365static struct attribute*
1366ds1685_rtc_sysfs_ctrla_attrs[] = {
1367 &dev_attr_uip.attr,
1368 &dev_attr_dv2.attr,
1369 &dev_attr_dv1.attr,
1370 &dev_attr_dv0.attr,
1371 &dev_attr_rs3.attr,
1372 &dev_attr_rs2.attr,
1373 &dev_attr_rs1.attr,
1374 &dev_attr_rs0.attr,
1375 NULL,
1376};
1377
1378static const struct attribute_group
1379ds1685_rtc_sysfs_ctrla_grp = {
1380 .name = "ctrla",
1381 .attrs = ds1685_rtc_sysfs_ctrla_attrs,
1382};
1383
1384
1385/*
1386 * Control Register B bits.
1387 */
1388DS1685_RTC_SYSFS_CTRL_REG_RO(set);
1389DS1685_RTC_SYSFS_CTRL_REG_RW(pie);
1390DS1685_RTC_SYSFS_CTRL_REG_RW(aie);
1391DS1685_RTC_SYSFS_CTRL_REG_RW(uie);
1392DS1685_RTC_SYSFS_CTRL_REG_RW(sqwe);
1393DS1685_RTC_SYSFS_CTRL_REG_RO(dm);
1394DS1685_RTC_SYSFS_CTRL_REG_RO(2412);
1395DS1685_RTC_SYSFS_CTRL_REG_RO(dse);
1396
1397static struct attribute*
1398ds1685_rtc_sysfs_ctrlb_attrs[] = {
1399 &dev_attr_set.attr,
1400 &dev_attr_pie.attr,
1401 &dev_attr_aie.attr,
1402 &dev_attr_uie.attr,
1403 &dev_attr_sqwe.attr,
1404 &dev_attr_dm.attr,
1405 &dev_attr_2412.attr,
1406 &dev_attr_dse.attr,
1407 NULL,
1408};
1409
1410static const struct attribute_group
1411ds1685_rtc_sysfs_ctrlb_grp = {
1412 .name = "ctrlb",
1413 .attrs = ds1685_rtc_sysfs_ctrlb_attrs,
1414};
1415
1416/*
1417 * Control Register C bits.
1418 *
1419 * Reading Control C clears these bits! Reading them individually can
1420 * possibly cause an interrupt to be missed. Use the /proc interface
1421 * to see all the bits in this register simultaneously.
1422 */
1423DS1685_RTC_SYSFS_CTRL_REG_RO(irqf);
1424DS1685_RTC_SYSFS_CTRL_REG_RO(pf);
1425DS1685_RTC_SYSFS_CTRL_REG_RO(af);
1426DS1685_RTC_SYSFS_CTRL_REG_RO(uf);
1427
1428static struct attribute*
1429ds1685_rtc_sysfs_ctrlc_attrs[] = {
1430 &dev_attr_irqf.attr,
1431 &dev_attr_pf.attr,
1432 &dev_attr_af.attr,
1433 &dev_attr_uf.attr,
1434 NULL,
1435};
1436
1437static const struct attribute_group
1438ds1685_rtc_sysfs_ctrlc_grp = {
1439 .name = "ctrlc",
1440 .attrs = ds1685_rtc_sysfs_ctrlc_attrs,
1441};
1442
1443/*
1444 * Control Register D bits.
1445 */
1446DS1685_RTC_SYSFS_CTRL_REG_RO(vrt);
1447
1448static struct attribute*
1449ds1685_rtc_sysfs_ctrld_attrs[] = {
1450 &dev_attr_vrt.attr,
1451 NULL,
1452};
1453
1454static const struct attribute_group
1455ds1685_rtc_sysfs_ctrld_grp = {
1456 .name = "ctrld",
1457 .attrs = ds1685_rtc_sysfs_ctrld_attrs,
1458};
1459
1460/*
1461 * Control Register 4A bits.
1462 */
1463DS1685_RTC_SYSFS_CTRL_REG_RO(vrt2);
1464DS1685_RTC_SYSFS_CTRL_REG_RO(incr);
1465DS1685_RTC_SYSFS_CTRL_REG_RW(pab);
1466DS1685_RTC_SYSFS_CTRL_REG_RW(rf);
1467DS1685_RTC_SYSFS_CTRL_REG_RW(wf);
1468DS1685_RTC_SYSFS_CTRL_REG_RW(kf);
1469#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
1470DS1685_RTC_SYSFS_CTRL_REG_RO(bme);
1471#endif
1472
1473static struct attribute*
1474ds1685_rtc_sysfs_ctrl4a_attrs[] = {
1475 &dev_attr_vrt2.attr,
1476 &dev_attr_incr.attr,
1477 &dev_attr_pab.attr,
1478 &dev_attr_rf.attr,
1479 &dev_attr_wf.attr,
1480 &dev_attr_kf.attr,
1481#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
1482 &dev_attr_bme.attr,
1483#endif
1484 NULL,
1485};
1486
1487static const struct attribute_group
1488ds1685_rtc_sysfs_ctrl4a_grp = {
1489 .name = "ctrl4a",
1490 .attrs = ds1685_rtc_sysfs_ctrl4a_attrs,
1491};
1492
1493/*
1494 * Control Register 4B bits.
1495 */
1496DS1685_RTC_SYSFS_CTRL_REG_RW(abe);
1497DS1685_RTC_SYSFS_CTRL_REG_RW(e32k);
1498DS1685_RTC_SYSFS_CTRL_REG_RO(cs);
1499DS1685_RTC_SYSFS_CTRL_REG_RW(rce);
1500DS1685_RTC_SYSFS_CTRL_REG_RW(prs);
1501DS1685_RTC_SYSFS_CTRL_REG_RW(rie);
1502DS1685_RTC_SYSFS_CTRL_REG_RW(wie);
1503DS1685_RTC_SYSFS_CTRL_REG_RW(kse);
1504
1505static struct attribute*
1506ds1685_rtc_sysfs_ctrl4b_attrs[] = {
1507 &dev_attr_abe.attr,
1508 &dev_attr_e32k.attr,
1509 &dev_attr_cs.attr,
1510 &dev_attr_rce.attr,
1511 &dev_attr_prs.attr,
1512 &dev_attr_rie.attr,
1513 &dev_attr_wie.attr,
1514 &dev_attr_kse.attr,
1515 NULL,
1516};
1517
1518static const struct attribute_group
1519ds1685_rtc_sysfs_ctrl4b_grp = {
1520 .name = "ctrl4b",
1521 .attrs = ds1685_rtc_sysfs_ctrl4b_attrs,
1522};
1523
1524
1525/**
1526 * struct ds1685_rtc_ctrl_regs.
1527 * @name: char pointer for the bit name.
1528 * @reg: control register the bit is in.
1529 * @bit: the bit's offset in the register.
1530 */
1531struct ds1685_rtc_time_regs {
1532 const char *name;
1533 const u8 reg;
1534 const u8 mask;
1535 const u8 min;
1536 const u8 max;
1537};
1538
1539/*
1540 * Time/Date register lookup tables.
1541 */
1542static const struct ds1685_rtc_time_regs
1543ds1685_time_regs_bcd_table[] = {
1544 { "seconds", RTC_SECS, RTC_SECS_BCD_MASK, 0, 59 },
1545 { "minutes", RTC_MINS, RTC_MINS_BCD_MASK, 0, 59 },
1546 { "hours", RTC_HRS, RTC_HRS_24_BCD_MASK, 0, 23 },
1547 { "wday", RTC_WDAY, RTC_WDAY_MASK, 1, 7 },
1548 { "mday", RTC_MDAY, RTC_MDAY_BCD_MASK, 1, 31 },
1549 { "month", RTC_MONTH, RTC_MONTH_BCD_MASK, 1, 12 },
1550 { "year", RTC_YEAR, RTC_YEAR_BCD_MASK, 0, 99 },
1551 { "century", RTC_CENTURY, RTC_CENTURY_MASK, 0, 99 },
1552 { "alarm_seconds", RTC_SECS_ALARM, RTC_SECS_BCD_MASK, 0, 59 },
1553 { "alarm_minutes", RTC_MINS_ALARM, RTC_MINS_BCD_MASK, 0, 59 },
1554 { "alarm_hours", RTC_HRS_ALARM, RTC_HRS_24_BCD_MASK, 0, 23 },
1555 { "alarm_mday", RTC_MDAY_ALARM, RTC_MDAY_ALARM_MASK, 1, 31 },
1556 { NULL, 0, 0, 0, 0 },
1557};
1558
1559static const struct ds1685_rtc_time_regs
1560ds1685_time_regs_bin_table[] = {
1561 { "seconds", RTC_SECS, RTC_SECS_BIN_MASK, 0x00, 0x3b },
1562 { "minutes", RTC_MINS, RTC_MINS_BIN_MASK, 0x00, 0x3b },
1563 { "hours", RTC_HRS, RTC_HRS_24_BIN_MASK, 0x00, 0x17 },
1564 { "wday", RTC_WDAY, RTC_WDAY_MASK, 0x01, 0x07 },
1565 { "mday", RTC_MDAY, RTC_MDAY_BIN_MASK, 0x01, 0x1f },
1566 { "month", RTC_MONTH, RTC_MONTH_BIN_MASK, 0x01, 0x0c },
1567 { "year", RTC_YEAR, RTC_YEAR_BIN_MASK, 0x00, 0x63 },
1568 { "century", RTC_CENTURY, RTC_CENTURY_MASK, 0x00, 0x63 },
1569 { "alarm_seconds", RTC_SECS_ALARM, RTC_SECS_BIN_MASK, 0x00, 0x3b },
1570 { "alarm_minutes", RTC_MINS_ALARM, RTC_MINS_BIN_MASK, 0x00, 0x3b },
1571 { "alarm_hours", RTC_HRS_ALARM, RTC_HRS_24_BIN_MASK, 0x00, 0x17 },
1572 { "alarm_mday", RTC_MDAY_ALARM, RTC_MDAY_ALARM_MASK, 0x01, 0x1f },
1573 { NULL, 0, 0, 0x00, 0x00 },
1574};
1575
1576/**
1577 * ds1685_rtc_sysfs_time_regs_bcd_lookup - time/date reg bit lookup function.
1578 * @name: register bit to look up in ds1685_time_regs_bcd_table.
1579 */
1580static const struct ds1685_rtc_time_regs*
1581ds1685_rtc_sysfs_time_regs_lookup(const char *name, bool bcd_mode)
1582{
1583 const struct ds1685_rtc_time_regs *p;
1584
1585 if (bcd_mode)
1586 p = ds1685_time_regs_bcd_table;
1587 else
1588 p = ds1685_time_regs_bin_table;
1589
1590 for (; p->name != NULL; ++p)
1591 if (strcmp(p->name, name) == 0)
1592 return p;
1593
1594 return NULL;
1595}
1596
1597/**
1598 * ds1685_rtc_sysfs_time_regs_show - reads a time/date register via sysfs.
1599 * @dev: pointer to device structure.
1600 * @attr: pointer to device_attribute structure.
1601 * @buf: pointer to char array to hold the output.
1602 */
1603static ssize_t
1604ds1685_rtc_sysfs_time_regs_show(struct device *dev,
1605 struct device_attribute *attr, char *buf)
1606{
1607 u8 tmp;
1608 struct ds1685_priv *rtc = dev_get_drvdata(dev);
1609 const struct ds1685_rtc_time_regs *bcd_reg_info =
1610 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, true);
1611 const struct ds1685_rtc_time_regs *bin_reg_info =
1612 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, false);
1613
1614 /* Make sure we actually matched something. */
1615 if (!bcd_reg_info && !bin_reg_info)
1616 return -EINVAL;
1617
1618 /* bcd_reg_info->reg == bin_reg_info->reg. */
1619 ds1685_rtc_begin_data_access(rtc);
1620 tmp = rtc->read(rtc, bcd_reg_info->reg);
1621 ds1685_rtc_end_data_access(rtc);
1622
1623 tmp = ds1685_rtc_bcd2bin(rtc, tmp, bcd_reg_info->mask,
1624 bin_reg_info->mask);
1625
1626 return snprintf(buf, 4, "%d\n", tmp);
1627}
1628
1629/**
1630 * ds1685_rtc_sysfs_time_regs_store - writes a time/date register via sysfs.
1631 * @dev: pointer to device structure.
1632 * @attr: pointer to device_attribute structure.
1633 * @buf: pointer to char array to hold the output.
1634 * @count: number of bytes written.
1635 */
1636static ssize_t
1637ds1685_rtc_sysfs_time_regs_store(struct device *dev,
1638 struct device_attribute *attr,
1639 const char *buf, size_t count)
1640{
1641 long int val = 0;
1642 struct ds1685_priv *rtc = dev_get_drvdata(dev);
1643 const struct ds1685_rtc_time_regs *bcd_reg_info =
1644 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, true);
1645 const struct ds1685_rtc_time_regs *bin_reg_info =
1646 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, false);
1647
1648 /* We only accept numbers. */
1649 if (kstrtol(buf, 10, &val) < 0)
1650 return -EINVAL;
1651
1652 /* Make sure we actually matched something. */
1653 if (!bcd_reg_info && !bin_reg_info)
1654 return -EINVAL;
1655
1656 /* Check for a valid range. */
1657 if (rtc->bcd_mode) {
1658 if ((val < bcd_reg_info->min) || (val > bcd_reg_info->max))
1659 return -ERANGE;
1660 } else {
1661 if ((val < bin_reg_info->min) || (val > bin_reg_info->max))
1662 return -ERANGE;
1663 }
1664
1665 val = ds1685_rtc_bin2bcd(rtc, val, bin_reg_info->mask,
1666 bcd_reg_info->mask);
1667
1668 /* bcd_reg_info->reg == bin_reg_info->reg. */
1669 ds1685_rtc_begin_data_access(rtc);
1670 rtc->write(rtc, bcd_reg_info->reg, val);
1671 ds1685_rtc_end_data_access(rtc);
1672
1673 return count;
1674}
1675
1676/**
1677 * DS1685_RTC_SYSFS_REG_RW - device_attribute for a read-write time register.
1678 * @reg: time/date register to read or write.
1679 */
1680#define DS1685_RTC_SYSFS_TIME_REG_RW(reg) \
1681 static DEVICE_ATTR(reg, S_IRUGO | S_IWUSR, \
1682 ds1685_rtc_sysfs_time_regs_show, \
1683 ds1685_rtc_sysfs_time_regs_store)
1684
1685/*
1686 * Time/Date Register bits.
1687 */
1688DS1685_RTC_SYSFS_TIME_REG_RW(seconds);
1689DS1685_RTC_SYSFS_TIME_REG_RW(minutes);
1690DS1685_RTC_SYSFS_TIME_REG_RW(hours);
1691DS1685_RTC_SYSFS_TIME_REG_RW(wday);
1692DS1685_RTC_SYSFS_TIME_REG_RW(mday);
1693DS1685_RTC_SYSFS_TIME_REG_RW(month);
1694DS1685_RTC_SYSFS_TIME_REG_RW(year);
1695DS1685_RTC_SYSFS_TIME_REG_RW(century);
1696DS1685_RTC_SYSFS_TIME_REG_RW(alarm_seconds);
1697DS1685_RTC_SYSFS_TIME_REG_RW(alarm_minutes);
1698DS1685_RTC_SYSFS_TIME_REG_RW(alarm_hours);
1699DS1685_RTC_SYSFS_TIME_REG_RW(alarm_mday);
1700
1701static struct attribute*
1702ds1685_rtc_sysfs_time_attrs[] = {
1703 &dev_attr_seconds.attr,
1704 &dev_attr_minutes.attr,
1705 &dev_attr_hours.attr,
1706 &dev_attr_wday.attr,
1707 &dev_attr_mday.attr,
1708 &dev_attr_month.attr,
1709 &dev_attr_year.attr,
1710 &dev_attr_century.attr,
1711 NULL,
1712};
1713
1714static const struct attribute_group
1715ds1685_rtc_sysfs_time_grp = {
1716 .name = "datetime",
1717 .attrs = ds1685_rtc_sysfs_time_attrs,
1718};
1719
1720static struct attribute*
1721ds1685_rtc_sysfs_alarm_attrs[] = {
1722 &dev_attr_alarm_seconds.attr,
1723 &dev_attr_alarm_minutes.attr,
1724 &dev_attr_alarm_hours.attr,
1725 &dev_attr_alarm_mday.attr,
1726 NULL,
1727};
1728
1729static const struct attribute_group
1730ds1685_rtc_sysfs_alarm_grp = {
1731 .name = "alarm",
1732 .attrs = ds1685_rtc_sysfs_alarm_attrs,
1733};
1734#endif /* CONFIG_RTC_DS1685_SYSFS_REGS */
1735
1736
1737/**
1738 * ds1685_rtc_sysfs_register - register sysfs files.
1739 * @dev: pointer to device structure.
1740 */
1741static int
1742ds1685_rtc_sysfs_register(struct device *dev)
1743{
1744 int ret = 0;
1745
1746 sysfs_bin_attr_init(&ds1685_rtc_sysfs_nvram_attr);
1747 ret = sysfs_create_bin_file(&dev->kobj, &ds1685_rtc_sysfs_nvram_attr);
1748 if (ret)
1749 return ret;
1750
1751 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp);
1752 if (ret)
1753 return ret;
1754
1755#ifdef CONFIG_RTC_DS1685_SYSFS_REGS
1756 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrla_grp);
1757 if (ret)
1758 return ret;
1759
1760 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlb_grp);
1761 if (ret)
1762 return ret;
1763
1764 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlc_grp);
1765 if (ret)
1766 return ret;
1767
1768 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrld_grp);
1769 if (ret)
1770 return ret;
1771
1772 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4a_grp);
1773 if (ret)
1774 return ret;
1775
1776 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4b_grp);
1777 if (ret)
1778 return ret;
1779
1780 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_time_grp);
1781 if (ret)
1782 return ret;
1783
1784 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_alarm_grp);
1785 if (ret)
1786 return ret;
1787#endif
1788 return 0;
1789}
1790
1791/**
1792 * ds1685_rtc_sysfs_unregister - unregister sysfs files.
1793 * @dev: pointer to device structure.
1794 */
1795static int
1796ds1685_rtc_sysfs_unregister(struct device *dev)
1797{
1798 sysfs_remove_bin_file(&dev->kobj, &ds1685_rtc_sysfs_nvram_attr);
1799 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp);
1800
1801#ifdef CONFIG_RTC_DS1685_SYSFS_REGS
1802 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrla_grp);
1803 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlb_grp);
1804 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlc_grp);
1805 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrld_grp);
1806 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4a_grp);
1807 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4b_grp);
1808 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_time_grp);
1809 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_alarm_grp);
1810#endif
1811
1812 return 0;
1813}
1814#endif /* CONFIG_SYSFS */
1815
1816
1817
1818/* ----------------------------------------------------------------------- */
1819/* Driver Probe/Removal */
1820
1821/**
1822 * ds1685_rtc_probe - initializes rtc driver.
1823 * @pdev: pointer to platform_device structure.
1824 */
1825static int
1826ds1685_rtc_probe(struct platform_device *pdev)
1827{
1828 struct rtc_device *rtc_dev;
1829 struct resource *res;
1830 struct ds1685_priv *rtc;
1831 struct ds1685_rtc_platform_data *pdata;
1832 u8 ctrla, ctrlb, hours;
1833 unsigned char am_pm;
1834 int ret = 0;
1835
1836 /* Get the platform data. */
1837 pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data;
1838 if (!pdata)
1839 return -ENODEV;
1840
1841 /* Allocate memory for the rtc device. */
1842 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
1843 if (!rtc)
1844 return -ENOMEM;
1845
1846 /*
1847 * Allocate/setup any IORESOURCE_MEM resources, if required. Not all
1848 * platforms put the RTC in an easy-access place. Like the SGI Octane,
1849 * which attaches the RTC to a "ByteBus", hooked to a SuperIO chip
1850 * that sits behind the IOC3 PCI metadevice.
1851 */
1852 if (pdata->alloc_io_resources) {
1853 /* Get the platform resources. */
1854 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1855 if (!res)
1856 return -ENXIO;
1857 rtc->size = resource_size(res);
1858
1859 /* Request a memory region. */
1860 /* XXX: mmio-only for now. */
1861 if (!devm_request_mem_region(&pdev->dev, res->start, rtc->size,
1862 pdev->name))
1863 return -EBUSY;
1864
1865 /*
1866 * Set the base address for the rtc, and ioremap its
1867 * registers.
1868 */
1869 rtc->baseaddr = res->start;
1870 rtc->regs = devm_ioremap(&pdev->dev, res->start, rtc->size);
1871 if (!rtc->regs)
1872 return -ENOMEM;
1873 }
1874 rtc->alloc_io_resources = pdata->alloc_io_resources;
1875
1876 /* Get the register step size. */
1877 if (pdata->regstep > 0)
1878 rtc->regstep = pdata->regstep;
1879 else
1880 rtc->regstep = 1;
1881
1882 /* Platform read function, else default if mmio setup */
1883 if (pdata->plat_read)
1884 rtc->read = pdata->plat_read;
1885 else
1886 if (pdata->alloc_io_resources)
1887 rtc->read = ds1685_read;
1888 else
1889 return -ENXIO;
1890
1891 /* Platform write function, else default if mmio setup */
1892 if (pdata->plat_write)
1893 rtc->write = pdata->plat_write;
1894 else
1895 if (pdata->alloc_io_resources)
1896 rtc->write = ds1685_write;
1897 else
1898 return -ENXIO;
1899
1900 /* Platform pre-shutdown function, if defined. */
1901 if (pdata->plat_prepare_poweroff)
1902 rtc->prepare_poweroff = pdata->plat_prepare_poweroff;
1903
1904 /* Platform wake_alarm function, if defined. */
1905 if (pdata->plat_wake_alarm)
1906 rtc->wake_alarm = pdata->plat_wake_alarm;
1907
1908 /* Platform post_ram_clear function, if defined. */
1909 if (pdata->plat_post_ram_clear)
1910 rtc->post_ram_clear = pdata->plat_post_ram_clear;
1911
1912 /* Init the spinlock, workqueue, & set the driver data. */
1913 spin_lock_init(&rtc->lock);
1914 INIT_WORK(&rtc->work, ds1685_rtc_work_queue);
1915 platform_set_drvdata(pdev, rtc);
1916
1917 /* Turn the oscillator on if is not already on (DV1 = 1). */
1918 ctrla = rtc->read(rtc, RTC_CTRL_A);
1919 if (!(ctrla & RTC_CTRL_A_DV1))
1920 ctrla |= RTC_CTRL_A_DV1;
1921
1922 /* Enable the countdown chain (DV2 = 0) */
1923 ctrla &= ~(RTC_CTRL_A_DV2);
1924
1925 /* Clear RS3-RS0 in Control A. */
1926 ctrla &= ~(RTC_CTRL_A_RS_MASK);
1927
1928 /*
1929 * All done with Control A. Switch to Bank 1 for the remainder of
1930 * the RTC setup so we have access to the extended functions.
1931 */
1932 ctrla |= RTC_CTRL_A_DV0;
1933 rtc->write(rtc, RTC_CTRL_A, ctrla);
1934
1935 /* Default to 32768kHz output. */
1936 rtc->write(rtc, RTC_EXT_CTRL_4B,
1937 (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K));
1938
1939 /* Set the SET bit in Control B so we can do some housekeeping. */
1940 rtc->write(rtc, RTC_CTRL_B,
1941 (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
1942
1943 /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
1944 while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
1945 cpu_relax();
1946
1947 /*
1948 * If the platform supports BCD mode, then set DM=0 in Control B.
1949 * Otherwise, set DM=1 for BIN mode.
1950 */
1951 ctrlb = rtc->read(rtc, RTC_CTRL_B);
1952 if (pdata->bcd_mode)
1953 ctrlb &= ~(RTC_CTRL_B_DM);
1954 else
1955 ctrlb |= RTC_CTRL_B_DM;
1956 rtc->bcd_mode = pdata->bcd_mode;
1957
1958 /*
1959 * Disable Daylight Savings Time (DSE = 0).
1960 * The RTC has hardcoded timezone information that is rendered
1961 * obselete. We'll let the OS deal with DST settings instead.
1962 */
1963 if (ctrlb & RTC_CTRL_B_DSE)
1964 ctrlb &= ~(RTC_CTRL_B_DSE);
1965
1966 /* Force 24-hour mode (2412 = 1). */
1967 if (!(ctrlb & RTC_CTRL_B_2412)) {
1968 /* Reinitialize the time hours. */
1969 hours = rtc->read(rtc, RTC_HRS);
1970 am_pm = hours & RTC_HRS_AMPM_MASK;
1971 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
1972 RTC_HRS_12_BIN_MASK);
1973 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
1974
1975 /* Enable 24-hour mode. */
1976 ctrlb |= RTC_CTRL_B_2412;
1977
1978 /* Write back to Control B, including DM & DSE bits. */
1979 rtc->write(rtc, RTC_CTRL_B, ctrlb);
1980
1981 /* Write the time hours back. */
1982 rtc->write(rtc, RTC_HRS,
1983 ds1685_rtc_bin2bcd(rtc, hours,
1984 RTC_HRS_24_BIN_MASK,
1985 RTC_HRS_24_BCD_MASK));
1986
1987 /* Reinitialize the alarm hours. */
1988 hours = rtc->read(rtc, RTC_HRS_ALARM);
1989 am_pm = hours & RTC_HRS_AMPM_MASK;
1990 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
1991 RTC_HRS_12_BIN_MASK);
1992 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
1993
1994 /* Write the alarm hours back. */
1995 rtc->write(rtc, RTC_HRS_ALARM,
1996 ds1685_rtc_bin2bcd(rtc, hours,
1997 RTC_HRS_24_BIN_MASK,
1998 RTC_HRS_24_BCD_MASK));
1999 } else {
2000 /* 24-hour mode is already set, so write Control B back. */
2001 rtc->write(rtc, RTC_CTRL_B, ctrlb);
2002 }
2003
2004 /* Unset the SET bit in Control B so the RTC can update. */
2005 rtc->write(rtc, RTC_CTRL_B,
2006 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
2007
2008 /* Check the main battery. */
2009 if (!(rtc->read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT))
2010 dev_warn(&pdev->dev,
2011 "Main battery is exhausted! RTC may be invalid!\n");
2012
2013 /* Check the auxillary battery. It is optional. */
2014 if (!(rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2))
2015 dev_warn(&pdev->dev,
2016 "Aux battery is exhausted or not available.\n");
2017
2018 /* Read Ctrl B and clear PIE/AIE/UIE. */
2019 rtc->write(rtc, RTC_CTRL_B,
2020 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_PAU_MASK)));
2021
2022 /* Reading Ctrl C auto-clears PF/AF/UF. */
2023 rtc->read(rtc, RTC_CTRL_C);
2024
2025 /* Read Ctrl 4B and clear RIE/WIE/KSE. */
2026 rtc->write(rtc, RTC_EXT_CTRL_4B,
2027 (rtc->read(rtc, RTC_EXT_CTRL_4B) & ~(RTC_CTRL_4B_RWK_MASK)));
2028
2029 /* Clear RF/WF/KF in Ctrl 4A. */
2030 rtc->write(rtc, RTC_EXT_CTRL_4A,
2031 (rtc->read(rtc, RTC_EXT_CTRL_4A) & ~(RTC_CTRL_4A_RWK_MASK)));
2032
2033 /*
2034 * Re-enable KSE to handle power button events. We do not enable
2035 * WIE or RIE by default.
2036 */
2037 rtc->write(rtc, RTC_EXT_CTRL_4B,
2038 (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_KSE));
2039
2040 /*
2041 * Fetch the IRQ and setup the interrupt handler.
2042 *
2043 * Not all platforms have the IRQF pin tied to something. If not, the
2044 * RTC will still set the *IE / *F flags and raise IRQF in ctrlc, but
2045 * there won't be an automatic way of notifying the kernel about it,
2046 * unless ctrlc is explicitly polled.
2047 */
2048 if (!pdata->no_irq) {
2049 ret = platform_get_irq(pdev, 0);
2050 if (ret > 0) {
2051 rtc->irq_num = ret;
2052
2053 /* Request an IRQ. */
2054 ret = devm_request_irq(&pdev->dev, rtc->irq_num,
2055 ds1685_rtc_irq_handler,
2056 IRQF_SHARED, pdev->name, pdev);
2057
2058 /* Check to see if something came back. */
2059 if (unlikely(ret)) {
2060 dev_warn(&pdev->dev,
2061 "RTC interrupt not available\n");
2062 rtc->irq_num = 0;
2063 }
2064 } else
2065 return ret;
2066 }
2067 rtc->no_irq = pdata->no_irq;
2068
2069 /* Setup complete. */
2070 ds1685_rtc_switch_to_bank0(rtc);
2071
2072 /* Register the device as an RTC. */
2073 rtc_dev = rtc_device_register(pdev->name, &pdev->dev,
2074 &ds1685_rtc_ops, THIS_MODULE);
2075
2076 /* Success? */
2077 if (IS_ERR(rtc_dev))
2078 return PTR_ERR(rtc_dev);
2079
2080 /* Maximum periodic rate is 8192Hz (0.122070ms). */
2081 rtc_dev->max_user_freq = RTC_MAX_USER_FREQ;
2082
2083 /* See if the platform doesn't support UIE. */
2084 if (pdata->uie_unsupported)
2085 rtc_dev->uie_unsupported = 1;
2086 rtc->uie_unsupported = pdata->uie_unsupported;
2087
2088 rtc->dev = rtc_dev;
2089
2090#ifdef CONFIG_SYSFS
2091 ret = ds1685_rtc_sysfs_register(&pdev->dev);
2092 if (ret)
2093 rtc_device_unregister(rtc->dev);
2094#endif
2095
2096 /* Done! */
2097 return ret;
2098}
2099
2100/**
2101 * ds1685_rtc_remove - removes rtc driver.
2102 * @pdev: pointer to platform_device structure.
2103 */
2104static int
2105ds1685_rtc_remove(struct platform_device *pdev)
2106{
2107 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
2108
2109#ifdef CONFIG_SYSFS
2110 ds1685_rtc_sysfs_unregister(&pdev->dev);
2111#endif
2112
2113 rtc_device_unregister(rtc->dev);
2114
2115 /* Read Ctrl B and clear PIE/AIE/UIE. */
2116 rtc->write(rtc, RTC_CTRL_B,
2117 (rtc->read(rtc, RTC_CTRL_B) &
2118 ~(RTC_CTRL_B_PAU_MASK)));
2119
2120 /* Reading Ctrl C auto-clears PF/AF/UF. */
2121 rtc->read(rtc, RTC_CTRL_C);
2122
2123 /* Read Ctrl 4B and clear RIE/WIE/KSE. */
2124 rtc->write(rtc, RTC_EXT_CTRL_4B,
2125 (rtc->read(rtc, RTC_EXT_CTRL_4B) &
2126 ~(RTC_CTRL_4B_RWK_MASK)));
2127
2128 /* Manually clear RF/WF/KF in Ctrl 4A. */
2129 rtc->write(rtc, RTC_EXT_CTRL_4A,
2130 (rtc->read(rtc, RTC_EXT_CTRL_4A) &
2131 ~(RTC_CTRL_4A_RWK_MASK)));
2132
2133 cancel_work_sync(&rtc->work);
2134
2135 return 0;
2136}
2137
2138/**
2139 * ds1685_rtc_driver - rtc driver properties.
2140 */
2141static struct platform_driver ds1685_rtc_driver = {
2142 .driver = {
2143 .name = "rtc-ds1685",
2144 .owner = THIS_MODULE,
2145 },
2146 .probe = ds1685_rtc_probe,
2147 .remove = ds1685_rtc_remove,
2148};
2149
2150/**
2151 * ds1685_rtc_init - rtc module init.
2152 */
2153static int __init
2154ds1685_rtc_init(void)
2155{
2156 return platform_driver_register(&ds1685_rtc_driver);
2157}
2158
2159/**
2160 * ds1685_rtc_exit - rtc module exit.
2161 */
2162static void __exit
2163ds1685_rtc_exit(void)
2164{
2165 platform_driver_unregister(&ds1685_rtc_driver);
2166}
2167
2168module_init(ds1685_rtc_init);
2169module_exit(ds1685_rtc_exit);
2170/* ----------------------------------------------------------------------- */
2171
2172
2173/* ----------------------------------------------------------------------- */
2174/* Poweroff function */
2175
2176/**
2177 * ds1685_rtc_poweroff - uses the RTC chip to power the system off.
2178 * @pdev: pointer to platform_device structure.
2179 */
2180extern void __noreturn
2181ds1685_rtc_poweroff(struct platform_device *pdev)
2182{
2183 u8 ctrla, ctrl4a, ctrl4b;
2184 struct ds1685_priv *rtc;
2185
2186 /* Check for valid RTC data, else, spin forever. */
2187 if (unlikely(!pdev)) {
2188 pr_emerg("rtc-ds1685: platform device data not available, spinning forever ...\n");
2189 unreachable();
2190 } else {
2191 /* Get the rtc data. */
2192 rtc = platform_get_drvdata(pdev);
2193
2194 /*
2195 * Disable our IRQ. We're powering down, so we're not
2196 * going to worry about cleaning up. Most of that should
2197 * have been taken care of by the shutdown scripts and this
2198 * is the final function call.
2199 */
2200 if (!rtc->no_irq)
2201 disable_irq_nosync(rtc->irq_num);
2202
2203 /* Oscillator must be on and the countdown chain enabled. */
2204 ctrla = rtc->read(rtc, RTC_CTRL_A);
2205 ctrla |= RTC_CTRL_A_DV1;
2206 ctrla &= ~(RTC_CTRL_A_DV2);
2207 rtc->write(rtc, RTC_CTRL_A, ctrla);
2208
2209 /*
2210 * Read Control 4A and check the status of the auxillary
2211 * battery. This must be present and working (VRT2 = 1)
2212 * for wakeup and kickstart functionality to be useful.
2213 */
2214 ds1685_rtc_switch_to_bank1(rtc);
2215 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
2216 if (ctrl4a & RTC_CTRL_4A_VRT2) {
2217 /* Clear all of the interrupt flags on Control 4A. */
2218 ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK);
2219 rtc->write(rtc, RTC_EXT_CTRL_4A, ctrl4a);
2220
2221 /*
2222 * The auxillary battery is present and working.
2223 * Enable extended functions (ABE=1), enable
2224 * wake-up (WIE=1), and enable kickstart (KSE=1)
2225 * in Control 4B.
2226 */
2227 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
2228 ctrl4b |= (RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE |
2229 RTC_CTRL_4B_KSE);
2230 rtc->write(rtc, RTC_EXT_CTRL_4B, ctrl4b);
2231 }
2232
2233 /* Set PAB to 1 in Control 4A to power the system down. */
2234 dev_warn(&pdev->dev, "Powerdown.\n");
2235 msleep(20);
2236 rtc->write(rtc, RTC_EXT_CTRL_4A,
2237 (ctrl4a | RTC_CTRL_4A_PAB));
2238
2239 /* Spin ... we do not switch back to bank0. */
2240 unreachable();
2241 }
2242}
2243EXPORT_SYMBOL(ds1685_rtc_poweroff);
2244/* ----------------------------------------------------------------------- */
2245
2246
2247MODULE_AUTHOR("Joshua Kinard <kumba@gentoo.org>");
2248MODULE_AUTHOR("Matthias Fuchs <matthias.fuchs@esd-electronics.com>");
2249MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver");
2250MODULE_LICENSE("GPL");
2251MODULE_VERSION(DRV_VERSION);
2252MODULE_ALIAS("platform:rtc-ds1685");
diff --git a/include/linux/rtc/ds1685.h b/include/linux/rtc/ds1685.h
new file mode 100644
index 000000000000..e6337a56d741
--- /dev/null
+++ b/include/linux/rtc/ds1685.h
@@ -0,0 +1,375 @@
1/*
2 * Definitions for the registers, addresses, and platform data of the
3 * DS1685/DS1687-series RTC chips.
4 *
5 * This Driver also works for the DS17X85/DS17X87 RTC chips. Functionally
6 * similar to the DS1685/DS1687, they support a few extra features which
7 * include larger, battery-backed NV-SRAM, burst-mode access, and an RTC
8 * write counter.
9 *
10 * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
11 * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
12 *
13 * References:
14 * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
15 * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
16 * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
17 * Application Note 90, Using the Multiplex Bus RTC Extended Features.
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
22 */
23
24#ifndef _LINUX_RTC_DS1685_H_
25#define _LINUX_RTC_DS1685_H_
26
27#include <linux/rtc.h>
28#include <linux/platform_device.h>
29#include <linux/workqueue.h>
30
31/**
32 * struct ds1685_priv - DS1685 private data structure.
33 * @dev: pointer to the rtc_device structure.
34 * @regs: iomapped base address pointer of the RTC registers.
35 * @regstep: padding/step size between registers (optional).
36 * @baseaddr: base address of the RTC device.
37 * @size: resource size.
38 * @lock: private lock variable for spin locking/unlocking.
39 * @work: private workqueue.
40 * @irq: IRQ number assigned to the RTC device.
41 * @prepare_poweroff: pointer to platform pre-poweroff function.
42 * @wake_alarm: pointer to platform wake alarm function.
43 * @post_ram_clear: pointer to platform post ram-clear function.
44 */
45struct ds1685_priv {
46 struct rtc_device *dev;
47 void __iomem *regs;
48 u32 regstep;
49 resource_size_t baseaddr;
50 size_t size;
51 spinlock_t lock;
52 struct work_struct work;
53 int irq_num;
54 bool bcd_mode;
55 bool no_irq;
56 bool uie_unsupported;
57 bool alloc_io_resources;
58 u8 (*read)(struct ds1685_priv *, int);
59 void (*write)(struct ds1685_priv *, int, u8);
60 void (*prepare_poweroff)(void);
61 void (*wake_alarm)(void);
62 void (*post_ram_clear)(void);
63};
64
65
66/**
67 * struct ds1685_rtc_platform_data - platform data structure.
68 * @plat_prepare_poweroff: platform-specific pre-poweroff function.
69 * @plat_wake_alarm: platform-specific wake alarm function.
70 * @plat_post_ram_clear: platform-specific post ram-clear function.
71 *
72 * If your platform needs to use a custom padding/step size between
73 * registers, or uses one or more of the extended interrupts and needs special
74 * handling, then include this header file in your platform definition and
75 * set regstep and the plat_* pointers as appropriate.
76 */
77struct ds1685_rtc_platform_data {
78 const u32 regstep;
79 const bool bcd_mode;
80 const bool no_irq;
81 const bool uie_unsupported;
82 const bool alloc_io_resources;
83 u8 (*plat_read)(struct ds1685_priv *, int);
84 void (*plat_write)(struct ds1685_priv *, int, u8);
85 void (*plat_prepare_poweroff)(void);
86 void (*plat_wake_alarm)(void);
87 void (*plat_post_ram_clear)(void);
88};
89
90
91/*
92 * Time Registers.
93 */
94#define RTC_SECS 0x00 /* Seconds 00-59 */
95#define RTC_SECS_ALARM 0x01 /* Alarm Seconds 00-59 */
96#define RTC_MINS 0x02 /* Minutes 00-59 */
97#define RTC_MINS_ALARM 0x03 /* Alarm Minutes 00-59 */
98#define RTC_HRS 0x04 /* Hours 01-12 AM/PM || 00-23 */
99#define RTC_HRS_ALARM 0x05 /* Alarm Hours 01-12 AM/PM || 00-23 */
100#define RTC_WDAY 0x06 /* Day of Week 01-07 */
101#define RTC_MDAY 0x07 /* Day of Month 01-31 */
102#define RTC_MONTH 0x08 /* Month 01-12 */
103#define RTC_YEAR 0x09 /* Year 00-99 */
104#define RTC_CENTURY 0x48 /* Century 00-99 */
105#define RTC_MDAY_ALARM 0x49 /* Alarm Day of Month 01-31 */
106
107
108/*
109 * Bit masks for the Time registers in BCD Mode (DM = 0).
110 */
111#define RTC_SECS_BCD_MASK 0x7f /* - x x x x x x x */
112#define RTC_MINS_BCD_MASK 0x7f /* - x x x x x x x */
113#define RTC_HRS_12_BCD_MASK 0x1f /* - - - x x x x x */
114#define RTC_HRS_24_BCD_MASK 0x3f /* - - x x x x x x */
115#define RTC_MDAY_BCD_MASK 0x3f /* - - x x x x x x */
116#define RTC_MONTH_BCD_MASK 0x1f /* - - - x x x x x */
117#define RTC_YEAR_BCD_MASK 0xff /* x x x x x x x x */
118
119/*
120 * Bit masks for the Time registers in BIN Mode (DM = 1).
121 */
122#define RTC_SECS_BIN_MASK 0x3f /* - - x x x x x x */
123#define RTC_MINS_BIN_MASK 0x3f /* - - x x x x x x */
124#define RTC_HRS_12_BIN_MASK 0x0f /* - - - - x x x x */
125#define RTC_HRS_24_BIN_MASK 0x1f /* - - - x x x x x */
126#define RTC_MDAY_BIN_MASK 0x1f /* - - - x x x x x */
127#define RTC_MONTH_BIN_MASK 0x0f /* - - - - x x x x */
128#define RTC_YEAR_BIN_MASK 0x7f /* - x x x x x x x */
129
130/*
131 * Bit masks common for the Time registers in BCD or BIN Mode.
132 */
133#define RTC_WDAY_MASK 0x07 /* - - - - - x x x */
134#define RTC_CENTURY_MASK 0xff /* x x x x x x x x */
135#define RTC_MDAY_ALARM_MASK 0xff /* x x x x x x x x */
136#define RTC_HRS_AMPM_MASK BIT(7) /* Mask for the AM/PM bit */
137
138
139
140/*
141 * Control Registers.
142 */
143#define RTC_CTRL_A 0x0a /* Control Register A */
144#define RTC_CTRL_B 0x0b /* Control Register B */
145#define RTC_CTRL_C 0x0c /* Control Register C */
146#define RTC_CTRL_D 0x0d /* Control Register D */
147#define RTC_EXT_CTRL_4A 0x4a /* Extended Control Register 4A */
148#define RTC_EXT_CTRL_4B 0x4b /* Extended Control Register 4B */
149
150
151/*
152 * Bit names in Control Register A.
153 */
154#define RTC_CTRL_A_UIP BIT(7) /* Update In Progress */
155#define RTC_CTRL_A_DV2 BIT(6) /* Countdown Chain */
156#define RTC_CTRL_A_DV1 BIT(5) /* Oscillator Enable */
157#define RTC_CTRL_A_DV0 BIT(4) /* Bank Select */
158#define RTC_CTRL_A_RS2 BIT(2) /* Rate-Selection Bit 2 */
159#define RTC_CTRL_A_RS3 BIT(3) /* Rate-Selection Bit 3 */
160#define RTC_CTRL_A_RS1 BIT(1) /* Rate-Selection Bit 1 */
161#define RTC_CTRL_A_RS0 BIT(0) /* Rate-Selection Bit 0 */
162#define RTC_CTRL_A_RS_MASK 0x0f /* RS3 + RS2 + RS1 + RS0 */
163
164/*
165 * Bit names in Control Register B.
166 */
167#define RTC_CTRL_B_SET BIT(7) /* SET Bit */
168#define RTC_CTRL_B_PIE BIT(6) /* Periodic-Interrupt Enable */
169#define RTC_CTRL_B_AIE BIT(5) /* Alarm-Interrupt Enable */
170#define RTC_CTRL_B_UIE BIT(4) /* Update-Ended Interrupt-Enable */
171#define RTC_CTRL_B_SQWE BIT(3) /* Square-Wave Enable */
172#define RTC_CTRL_B_DM BIT(2) /* Data Mode */
173#define RTC_CTRL_B_2412 BIT(1) /* 12-Hr/24-Hr Mode */
174#define RTC_CTRL_B_DSE BIT(0) /* Daylight Savings Enable */
175#define RTC_CTRL_B_PAU_MASK 0x70 /* PIE + AIE + UIE */
176
177
178/*
179 * Bit names in Control Register C.
180 *
181 * BIT(0), BIT(1), BIT(2), & BIT(3) are unused, always return 0, and cannot
182 * be written to.
183 */
184#define RTC_CTRL_C_IRQF BIT(7) /* Interrupt-Request Flag */
185#define RTC_CTRL_C_PF BIT(6) /* Periodic-Interrupt Flag */
186#define RTC_CTRL_C_AF BIT(5) /* Alarm-Interrupt Flag */
187#define RTC_CTRL_C_UF BIT(4) /* Update-Ended Interrupt Flag */
188#define RTC_CTRL_C_PAU_MASK 0x70 /* PF + AF + UF */
189
190
191/*
192 * Bit names in Control Register D.
193 *
194 * BIT(0) through BIT(6) are unused, always return 0, and cannot
195 * be written to.
196 */
197#define RTC_CTRL_D_VRT BIT(7) /* Valid RAM and Time */
198
199
200/*
201 * Bit names in Extended Control Register 4A.
202 *
203 * On the DS1685/DS1687/DS1689/DS1693, BIT(4) and BIT(5) are reserved for
204 * future use. They can be read from and written to, but have no effect
205 * on the RTC's operation.
206 *
207 * On the DS17x85/DS17x87, BIT(5) is Burst-Mode Enable (BME), and allows
208 * access to the extended NV-SRAM by automatically incrementing the address
209 * register when they are read from or written to.
210 */
211#define RTC_CTRL_4A_VRT2 BIT(7) /* Auxillary Battery Status */
212#define RTC_CTRL_4A_INCR BIT(6) /* Increment-in-Progress Status */
213#define RTC_CTRL_4A_PAB BIT(3) /* Power-Active Bar Control */
214#define RTC_CTRL_4A_RF BIT(2) /* RAM-Clear Flag */
215#define RTC_CTRL_4A_WF BIT(1) /* Wake-Up Alarm Flag */
216#define RTC_CTRL_4A_KF BIT(0) /* Kickstart Flag */
217#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
218#define RTC_CTRL_4A_BME BIT(5) /* Burst-Mode Enable */
219#endif
220#define RTC_CTRL_4A_RWK_MASK 0x07 /* RF + WF + KF */
221
222
223/*
224 * Bit names in Extended Control Register 4B.
225 */
226#define RTC_CTRL_4B_ABE BIT(7) /* Auxillary Battery Enable */
227#define RTC_CTRL_4B_E32K BIT(6) /* Enable 32.768Hz on SQW Pin */
228#define RTC_CTRL_4B_CS BIT(5) /* Crystal Select */
229#define RTC_CTRL_4B_RCE BIT(4) /* RAM Clear-Enable */
230#define RTC_CTRL_4B_PRS BIT(3) /* PAB Reset-Select */
231#define RTC_CTRL_4B_RIE BIT(2) /* RAM Clear-Interrupt Enable */
232#define RTC_CTRL_4B_WIE BIT(1) /* Wake-Up Alarm-Interrupt Enable */
233#define RTC_CTRL_4B_KSE BIT(0) /* Kickstart Interrupt-Enable */
234#define RTC_CTRL_4B_RWK_MASK 0x07 /* RIE + WIE + KSE */
235
236
237/*
238 * Misc register names in Bank 1.
239 *
240 * The DV0 bit in Control Register A must be set to 1 for these registers
241 * to become available, including Extended Control Registers 4A & 4B.
242 */
243#define RTC_BANK1_SSN_MODEL 0x40 /* Model Number */
244#define RTC_BANK1_SSN_BYTE_1 0x41 /* 1st Byte of Serial Number */
245#define RTC_BANK1_SSN_BYTE_2 0x42 /* 2nd Byte of Serial Number */
246#define RTC_BANK1_SSN_BYTE_3 0x43 /* 3rd Byte of Serial Number */
247#define RTC_BANK1_SSN_BYTE_4 0x44 /* 4th Byte of Serial Number */
248#define RTC_BANK1_SSN_BYTE_5 0x45 /* 5th Byte of Serial Number */
249#define RTC_BANK1_SSN_BYTE_6 0x46 /* 6th Byte of Serial Number */
250#define RTC_BANK1_SSN_CRC 0x47 /* Serial CRC Byte */
251#define RTC_BANK1_RAM_DATA_PORT 0x53 /* Extended RAM Data Port */
252
253
254/*
255 * Model-specific registers in Bank 1.
256 *
257 * The addresses below differ depending on the model of the RTC chip
258 * selected in the kernel configuration. Not all of these features are
259 * supported in the main driver at present.
260 *
261 * DS1685/DS1687 - Extended NV-SRAM address (LSB only).
262 * DS1689/DS1693 - Vcc, Vbat, Pwr Cycle Counters & Customer-specific S/N.
263 * DS17x85/DS17x87 - Extended NV-SRAM addresses (MSB & LSB) & Write counter.
264 */
265#if defined(CONFIG_RTC_DRV_DS1685)
266#define RTC_BANK1_RAM_ADDR 0x50 /* NV-SRAM Addr */
267#elif defined(CONFIG_RTC_DRV_DS1689)
268#define RTC_BANK1_VCC_CTR_LSB 0x54 /* Vcc Counter Addr (LSB) */
269#define RTC_BANK1_VCC_CTR_MSB 0x57 /* Vcc Counter Addr (MSB) */
270#define RTC_BANK1_VBAT_CTR_LSB 0x58 /* Vbat Counter Addr (LSB) */
271#define RTC_BANK1_VBAT_CTR_MSB 0x5b /* Vbat Counter Addr (MSB) */
272#define RTC_BANK1_PWR_CTR_LSB 0x5c /* Pwr Cycle Counter Addr (LSB) */
273#define RTC_BANK1_PWR_CTR_MSB 0x5d /* Pwr Cycle Counter Addr (MSB) */
274#define RTC_BANK1_UNIQ_SN 0x60 /* Customer-specific S/N */
275#else /* DS17x85/DS17x87 */
276#define RTC_BANK1_RAM_ADDR_LSB 0x50 /* NV-SRAM Addr (LSB) */
277#define RTC_BANK1_RAM_ADDR_MSB 0x51 /* NV-SRAM Addr (MSB) */
278#define RTC_BANK1_WRITE_CTR 0x5e /* RTC Write Counter */
279#endif
280
281
282/*
283 * Model numbers.
284 *
285 * The DS1688/DS1691 and DS1689/DS1693 chips share the same model number
286 * and the manual doesn't indicate any major differences. As such, they
287 * are regarded as the same chip in this driver.
288 */
289#define RTC_MODEL_DS1685 0x71 /* DS1685/DS1687 */
290#define RTC_MODEL_DS17285 0x72 /* DS17285/DS17287 */
291#define RTC_MODEL_DS1689 0x73 /* DS1688/DS1691/DS1689/DS1693 */
292#define RTC_MODEL_DS17485 0x74 /* DS17485/DS17487 */
293#define RTC_MODEL_DS17885 0x78 /* DS17885/DS17887 */
294
295
296/*
297 * Periodic Interrupt Rates / Square-Wave Output Frequency
298 *
299 * Periodic rates are selected by setting the RS3-RS0 bits in Control
300 * Register A and enabled via either the E32K bit in Extended Control
301 * Register 4B or the SQWE bit in Control Register B.
302 *
303 * E32K overrides the settings of RS3-RS0 and outputs a frequency of 32768Hz
304 * on the SQW pin of the RTC chip. While there are 16 possible selections,
305 * the 1-of-16 decoder is only able to divide the base 32768Hz signal into 13
306 * smaller frequencies. The values 0x01 and 0x02 are not used and are
307 * synonymous with 0x08 and 0x09, respectively.
308 *
309 * When E32K is set to a logic 1, periodic interrupts are disabled and reading
310 * /dev/rtc will return -EINVAL. This also applies if the periodic interrupt
311 * frequency is set to 0Hz.
312 *
313 * Not currently used by the rtc-ds1685 driver because the RTC core removed
314 * support for hardware-generated periodic-interrupts in favour of
315 * hrtimer-generated interrupts. But these defines are kept around for use
316 * in userland, as documentation to the hardware, and possible future use if
317 * hardware-generated periodic interrupts are ever added back.
318 */
319 /* E32K RS3 RS2 RS1 RS0 */
320#define RTC_SQW_8192HZ 0x03 /* 0 0 0 1 1 */
321#define RTC_SQW_4096HZ 0x04 /* 0 0 1 0 0 */
322#define RTC_SQW_2048HZ 0x05 /* 0 0 1 0 1 */
323#define RTC_SQW_1024HZ 0x06 /* 0 0 1 1 0 */
324#define RTC_SQW_512HZ 0x07 /* 0 0 1 1 1 */
325#define RTC_SQW_256HZ 0x08 /* 0 1 0 0 0 */
326#define RTC_SQW_128HZ 0x09 /* 0 1 0 0 1 */
327#define RTC_SQW_64HZ 0x0a /* 0 1 0 1 0 */
328#define RTC_SQW_32HZ 0x0b /* 0 1 0 1 1 */
329#define RTC_SQW_16HZ 0x0c /* 0 1 1 0 0 */
330#define RTC_SQW_8HZ 0x0d /* 0 1 1 0 1 */
331#define RTC_SQW_4HZ 0x0e /* 0 1 1 1 0 */
332#define RTC_SQW_2HZ 0x0f /* 0 1 1 1 1 */
333#define RTC_SQW_0HZ 0x00 /* 0 0 0 0 0 */
334#define RTC_SQW_32768HZ 32768 /* 1 - - - - */
335#define RTC_MAX_USER_FREQ 8192
336
337
338/*
339 * NVRAM data & addresses:
340 * - 50 bytes of NVRAM are available just past the clock registers.
341 * - 64 additional bytes are available in Bank0.
342 *
343 * Extended, battery-backed NV-SRAM:
344 * - DS1685/DS1687 - 128 bytes.
345 * - DS1689/DS1693 - 0 bytes.
346 * - DS17285/DS17287 - 2048 bytes.
347 * - DS17485/DS17487 - 4096 bytes.
348 * - DS17885/DS17887 - 8192 bytes.
349 */
350#define NVRAM_TIME_BASE 0x0e /* NVRAM Addr in Time regs */
351#define NVRAM_BANK0_BASE 0x40 /* NVRAM Addr in Bank0 regs */
352#define NVRAM_SZ_TIME 50
353#define NVRAM_SZ_BANK0 64
354#if defined(CONFIG_RTC_DRV_DS1685)
355# define NVRAM_SZ_EXTND 128
356#elif defined(CONFIG_RTC_DRV_DS1689)
357# define NVRAM_SZ_EXTND 0
358#elif defined(CONFIG_RTC_DRV_DS17285)
359# define NVRAM_SZ_EXTND 2048
360#elif defined(CONFIG_RTC_DRV_DS17485)
361# define NVRAM_SZ_EXTND 4096
362#elif defined(CONFIG_RTC_DRV_DS17885)
363# define NVRAM_SZ_EXTND 8192
364#endif
365#define NVRAM_TOTAL_SZ_BANK0 (NVRAM_SZ_TIME + NVRAM_SZ_BANK0)
366#define NVRAM_TOTAL_SZ (NVRAM_TOTAL_SZ_BANK0 + NVRAM_SZ_EXTND)
367
368
369/*
370 * Function Prototypes.
371 */
372extern void __noreturn
373ds1685_rtc_poweroff(struct platform_device *pdev);
374
375#endif /* _LINUX_RTC_DS1685_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-19 03:14:53 -0500