diff options
164 files changed, 6029 insertions, 846 deletions
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt new file mode 100644 index 000000000000..2c28f1d12f45 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt | |||
| @@ -0,0 +1,11 @@ | |||
| 1 | Altera SOCFPGA Clock Manager | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible : "altr,clk-mgr" | ||
| 5 | - reg : Should contain base address and length for Clock Manager | ||
| 6 | |||
| 7 | Example: | ||
| 8 | clkmgr@ffd04000 { | ||
| 9 | compatible = "altr,clk-mgr"; | ||
| 10 | reg = <0xffd04000 0x1000>; | ||
| 11 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm,kona-timer.txt b/Documentation/devicetree/bindings/arm/bcm/bcm,kona-timer.txt new file mode 100644 index 000000000000..59fa6e68d4f6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/bcm,kona-timer.txt | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | Broadcom Kona Family timer | ||
| 2 | ----------------------------------------------------- | ||
| 3 | This timer is used in the following Broadcom SoCs: | ||
| 4 | BCM11130, BCM11140, BCM11351, BCM28145, BCM28155 | ||
| 5 | |||
| 6 | Required properties: | ||
| 7 | - compatible : "bcm,kona-timer" | ||
| 8 | - reg : Register range for the timer | ||
| 9 | - interrupts : interrupt for the timer | ||
| 10 | - clock-frequency: frequency that the clock operates | ||
| 11 | |||
| 12 | Example: | ||
| 13 | timer@35006000 { | ||
| 14 | compatible = "bcm,kona-timer"; | ||
| 15 | reg = <0x35006000 0x1000>; | ||
| 16 | interrupts = <0x0 7 0x4>; | ||
| 17 | clock-frequency = <32768>; | ||
| 18 | }; | ||
| 19 | |||
diff --git a/Documentation/devicetree/bindings/arm/msm/timer.txt b/Documentation/devicetree/bindings/arm/msm/timer.txt index 8c5907b9cae8..c6ef8f13dc7e 100644 --- a/Documentation/devicetree/bindings/arm/msm/timer.txt +++ b/Documentation/devicetree/bindings/arm/msm/timer.txt | |||
| @@ -3,36 +3,35 @@ | |||
| 3 | Properties: | 3 | Properties: |
| 4 | 4 | ||
| 5 | - compatible : Should at least contain "qcom,msm-timer". More specific | 5 | - compatible : Should at least contain "qcom,msm-timer". More specific |
| 6 | properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general | 6 | properties specify which subsystem the timers are paired with. |
| 7 | purpose timer and a debug timer respectively. | ||
| 8 | 7 | ||
| 9 | - interrupts : Interrupt indicating a match event. | 8 | "qcom,kpss-timer" - krait subsystem |
| 9 | "qcom,scss-timer" - scorpion subsystem | ||
| 10 | 10 | ||
| 11 | - reg : Specifies the base address of the timer registers. The second region | 11 | - interrupts : Interrupts for the the debug timer, the first general purpose |
| 12 | specifies an optional register used to configure the clock divider. | 12 | timer, and optionally a second general purpose timer in that |
| 13 | order. | ||
| 13 | 14 | ||
| 14 | - clock-frequency : The frequency of the timer in Hz. | 15 | - reg : Specifies the base address of the timer registers. |
| 16 | |||
| 17 | - clock-frequency : The frequency of the debug timer and the general purpose | ||
| 18 | timer(s) in Hz in that order. | ||
| 15 | 19 | ||
| 16 | Optional: | 20 | Optional: |
| 17 | 21 | ||
| 18 | - cpu-offset : per-cpu offset used when the timer is accessed without the | 22 | - cpu-offset : per-cpu offset used when the timer is accessed without the |
| 19 | CPU remapping facilities. The offset is cpu-offset * cpu-nr. | 23 | CPU remapping facilities. The offset is |
| 24 | cpu-offset + (0x10000 * cpu-nr). | ||
| 20 | 25 | ||
| 21 | Example: | 26 | Example: |
| 22 | 27 | ||
| 23 | timer@200a004 { | 28 | timer@200a000 { |
| 24 | compatible = "qcom,msm-gpt", "qcom,msm-timer"; | 29 | compatible = "qcom,scss-timer", "qcom,msm-timer"; |
| 25 | interrupts = <1 2 0x301>; | 30 | interrupts = <1 1 0x301>, |
| 26 | reg = <0x0200a004 0x10>; | 31 | <1 2 0x301>, |
| 27 | clock-frequency = <32768>; | 32 | <1 3 0x301>; |
| 28 | cpu-offset = <0x40000>; | 33 | reg = <0x0200a000 0x100>; |
| 29 | }; | 34 | clock-frequency = <19200000>, |
| 30 | 35 | <32768>; | |
| 31 | timer@200a024 { | ||
| 32 | compatible = "qcom,msm-dgt", "qcom,msm-timer"; | ||
| 33 | interrupts = <1 3 0x301>; | ||
| 34 | reg = <0x0200a024 0x10>, | ||
| 35 | <0x0200a034 0x4>; | ||
| 36 | clock-frequency = <6750000>; | ||
| 37 | cpu-offset = <0x40000>; | 36 | cpu-offset = <0x40000>; |
| 38 | }; | 37 | }; |
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt index b5846e21cc2e..1608a54e90e1 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt | |||
| @@ -1,19 +1,84 @@ | |||
| 1 | NVIDIA Tegra Power Management Controller (PMC) | 1 | NVIDIA Tegra Power Management Controller (PMC) |
| 2 | 2 | ||
| 3 | Properties: | 3 | The PMC block interacts with an external Power Management Unit. The PMC |
| 4 | mostly controls the entry and exit of the system from different sleep | ||
| 5 | modes. It provides power-gating controllers for SoC and CPU power-islands. | ||
| 6 | |||
| 7 | Required properties: | ||
| 4 | - name : Should be pmc | 8 | - name : Should be pmc |
| 5 | - compatible : Should contain "nvidia,tegra<chip>-pmc". | 9 | - compatible : Should contain "nvidia,tegra<chip>-pmc". |
| 6 | - reg : Offset and length of the register set for the device | 10 | - reg : Offset and length of the register set for the device |
| 11 | - clocks : Must contain an entry for each entry in clock-names. | ||
| 12 | - clock-names : Must include the following entries: | ||
| 13 | "pclk" (The Tegra clock of that name), | ||
| 14 | "clk32k_in" (The 32KHz clock input to Tegra). | ||
| 15 | |||
| 16 | Optional properties: | ||
| 7 | - nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. | 17 | - nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. |
| 8 | The PMU is an external Power Management Unit, whose interrupt output | 18 | The PMU is an external Power Management Unit, whose interrupt output |
| 9 | signal is fed into the PMC. This signal is optionally inverted, and then | 19 | signal is fed into the PMC. This signal is optionally inverted, and then |
| 10 | fed into the ARM GIC. The PMC is not involved in the detection or | 20 | fed into the ARM GIC. The PMC is not involved in the detection or |
| 11 | handling of this interrupt signal, merely its inversion. | 21 | handling of this interrupt signal, merely its inversion. |
| 22 | - nvidia,suspend-mode : The suspend mode that the platform should use. | ||
| 23 | Valid values are 0, 1 and 2: | ||
| 24 | 0 (LP0): CPU + Core voltage off and DRAM in self-refresh | ||
| 25 | 1 (LP1): CPU voltage off and DRAM in self-refresh | ||
| 26 | 2 (LP2): CPU voltage off | ||
| 27 | - nvidia,core-power-req-active-high : Boolean, core power request active-high | ||
| 28 | - nvidia,sys-clock-req-active-high : Boolean, system clock request active-high | ||
| 29 | - nvidia,combined-power-req : Boolean, combined power request for CPU & Core | ||
| 30 | - nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC) | ||
| 31 | is enabled. | ||
| 32 | |||
| 33 | Required properties when nvidia,suspend-mode is specified: | ||
| 34 | - nvidia,cpu-pwr-good-time : CPU power good time in uS. | ||
| 35 | - nvidia,cpu-pwr-off-time : CPU power off time in uS. | ||
| 36 | - nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time> | ||
| 37 | Core power good time in uS. | ||
| 38 | - nvidia,core-pwr-off-time : Core power off time in uS. | ||
| 39 | |||
| 40 | Required properties when nvidia,suspend-mode=<0>: | ||
| 41 | - nvidia,lp0-vec : <start length> Starting address and length of LP0 vector | ||
| 42 | The LP0 vector contains the warm boot code that is executed by AVP when | ||
| 43 | resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7 | ||
| 44 | processor and always being the first boot processor when chip is power on | ||
| 45 | or resume from deep sleep mode. When the system is resumed from the deep | ||
| 46 | sleep mode, the warm boot code will restore some PLLs, clocks and then | ||
| 47 | bring up CPU0 for resuming the system. | ||
| 12 | 48 | ||
| 13 | Example: | 49 | Example: |
| 14 | 50 | ||
| 51 | / SoC dts including file | ||
| 15 | pmc@7000f400 { | 52 | pmc@7000f400 { |
| 16 | compatible = "nvidia,tegra20-pmc"; | 53 | compatible = "nvidia,tegra20-pmc"; |
| 17 | reg = <0x7000e400 0x400>; | 54 | reg = <0x7000e400 0x400>; |
| 55 | clocks = <&tegra_car 110>, <&clk32k_in>; | ||
| 56 | clock-names = "pclk", "clk32k_in"; | ||
| 18 | nvidia,invert-interrupt; | 57 | nvidia,invert-interrupt; |
| 58 | nvidia,suspend-mode = <1>; | ||
| 59 | nvidia,cpu-pwr-good-time = <2000>; | ||
| 60 | nvidia,cpu-pwr-off-time = <100>; | ||
| 61 | nvidia,core-pwr-good-time = <3845 3845>; | ||
| 62 | nvidia,core-pwr-off-time = <458>; | ||
| 63 | nvidia,core-power-req-active-high; | ||
| 64 | nvidia,sys-clock-req-active-high; | ||
| 65 | nvidia,lp0-vec = <0xbdffd000 0x2000>; | ||
| 66 | }; | ||
| 67 | |||
| 68 | / Tegra board dts file | ||
| 69 | { | ||
| 70 | ... | ||
| 71 | clocks { | ||
| 72 | compatible = "simple-bus"; | ||
| 73 | #address-cells = <1>; | ||
| 74 | #size-cells = <0>; | ||
| 75 | |||
| 76 | clk32k_in: clock { | ||
| 77 | compatible = "fixed-clock"; | ||
| 78 | reg=<0>; | ||
| 79 | #clock-cells = <0>; | ||
| 80 | clock-frequency = <32768>; | ||
| 81 | }; | ||
| 82 | }; | ||
| 83 | ... | ||
| 19 | }; | 84 | }; |
diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt new file mode 100644 index 000000000000..bd0c8416a5c8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | Device Tree Clock bindings for Altera's SoCFPGA platform | ||
| 2 | |||
| 3 | This binding uses the common clock binding[1]. | ||
| 4 | |||
| 5 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
| 6 | |||
| 7 | Required properties: | ||
| 8 | - compatible : shall be one of the following: | ||
| 9 | "altr,socfpga-pll-clock" - for a PLL clock | ||
| 10 | "altr,socfpga-perip-clock" - The peripheral clock divided from the | ||
| 11 | PLL clock. | ||
| 12 | - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. | ||
| 13 | - clocks : shall be the input parent clock phandle for the clock. This is | ||
| 14 | either an oscillator or a pll output. | ||
| 15 | - #clock-cells : from common clock binding, shall be set to 0. | ||
| 16 | |||
| 17 | Optional properties: | ||
| 18 | - fixed-divider : If clocks have a fixed divider value, use this property. | ||
diff --git a/Documentation/devicetree/bindings/mmc/davinci_mmc.txt b/Documentation/devicetree/bindings/mmc/davinci_mmc.txt new file mode 100644 index 000000000000..e5a0140b2381 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/davinci_mmc.txt | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | * TI Highspeed MMC host controller for DaVinci | ||
| 2 | |||
| 3 | The Highspeed MMC Host Controller on TI DaVinci family | ||
| 4 | provides an interface for MMC, SD and SDIO types of memory cards. | ||
| 5 | |||
| 6 | This file documents the properties used by the davinci_mmc driver. | ||
| 7 | |||
| 8 | Required properties: | ||
| 9 | - compatible: | ||
| 10 | Should be "ti,da830-mmc": for da830, da850, dm365 | ||
| 11 | Should be "ti,dm355-mmc": for dm355, dm644x | ||
| 12 | |||
| 13 | Optional properties: | ||
| 14 | - bus-width: Number of data lines, can be <1>, <4>, or <8>, default <1> | ||
| 15 | - max-frequency: Maximum operating clock frequency, default 25MHz. | ||
| 16 | - dmas: List of DMA specifiers with the controller specific format | ||
| 17 | as described in the generic DMA client binding. A tx and rx | ||
| 18 | specifier is required. | ||
| 19 | - dma-names: RX and TX DMA request names. These strings correspond | ||
| 20 | 1:1 with the DMA specifiers listed in dmas. | ||
| 21 | |||
| 22 | Example: | ||
| 23 | mmc0: mmc@1c40000 { | ||
| 24 | compatible = "ti,da830-mmc", | ||
| 25 | reg = <0x40000 0x1000>; | ||
| 26 | interrupts = <16>; | ||
| 27 | status = "okay"; | ||
| 28 | bus-width = <4>; | ||
| 29 | max-frequency = <50000000>; | ||
| 30 | dmas = <&edma 16 | ||
| 31 | &edma 17>; | ||
| 32 | dma-names = "rx", "tx"; | ||
| 33 | }; | ||
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 8c01a0218a1e..9653cf2f9727 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt | |||
| @@ -45,6 +45,7 @@ parameter is applicable: | |||
| 45 | AX25 Appropriate AX.25 support is enabled. | 45 | AX25 Appropriate AX.25 support is enabled. |
| 46 | BLACKFIN Blackfin architecture is enabled. | 46 | BLACKFIN Blackfin architecture is enabled. |
| 47 | CLK Common clock infrastructure is enabled. | 47 | CLK Common clock infrastructure is enabled. |
| 48 | CMA Contiguous Memory Area support is enabled. | ||
| 48 | DRM Direct Rendering Management support is enabled. | 49 | DRM Direct Rendering Management support is enabled. |
| 49 | DYNAMIC_DEBUG Build in debug messages and enable them at runtime | 50 | DYNAMIC_DEBUG Build in debug messages and enable them at runtime |
| 50 | EDD BIOS Enhanced Disk Drive Services (EDD) is enabled | 51 | EDD BIOS Enhanced Disk Drive Services (EDD) is enabled |
| @@ -2724,6 +2725,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted. | |||
| 2724 | Useful for devices that are detected asynchronously | 2725 | Useful for devices that are detected asynchronously |
| 2725 | (e.g. USB and MMC devices). | 2726 | (e.g. USB and MMC devices). |
| 2726 | 2727 | ||
| 2728 | rproc_mem=nn[KMG][@address] | ||
| 2729 | [KNL,ARM,CMA] Remoteproc physical memory block. | ||
| 2730 | Memory area to be used by remote processor image, | ||
| 2731 | managed by CMA. | ||
| 2732 | |||
| 2727 | rw [KNL] Mount root device read-write on boot | 2733 | rw [KNL] Mount root device read-write on boot |
| 2728 | 2734 | ||
| 2729 | S [KNL] Run init in single mode | 2735 | S [KNL] Run init in single mode |
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7af7d1368942..bf11bf5427da 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -671,6 +671,7 @@ config ARCH_TEGRA | |||
| 671 | select HAVE_CLK | 671 | select HAVE_CLK |
| 672 | select HAVE_SMP | 672 | select HAVE_SMP |
| 673 | select MIGHT_HAVE_CACHE_L2X0 | 673 | select MIGHT_HAVE_CACHE_L2X0 |
| 674 | select SOC_BUS | ||
| 674 | select SPARSE_IRQ | 675 | select SPARSE_IRQ |
| 675 | select USE_OF | 676 | select USE_OF |
| 676 | help | 677 | help |
| @@ -1666,7 +1667,7 @@ config ARCH_NR_GPIO | |||
| 1666 | int | 1667 | int |
| 1667 | default 1024 if ARCH_SHMOBILE || ARCH_TEGRA | 1668 | default 1024 if ARCH_SHMOBILE || ARCH_TEGRA |
| 1668 | default 512 if SOC_OMAP5 | 1669 | default 512 if SOC_OMAP5 |
| 1669 | default 355 if ARCH_U8500 | 1670 | default 392 if ARCH_U8500 |
| 1670 | default 288 if ARCH_VT8500 || ARCH_SUNXI | 1671 | default 288 if ARCH_VT8500 || ARCH_SUNXI |
| 1671 | default 264 if MACH_H4700 | 1672 | default 264 if MACH_H4700 |
| 1672 | default 0 | 1673 | default 0 |
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 2be254709dcb..20358fb43450 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile | |||
| @@ -33,6 +33,11 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb | |||
| 33 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb | 33 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb |
| 34 | dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb | 34 | dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb |
| 35 | dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb | 35 | dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb |
| 36 | # sama5d3 | ||
| 37 | dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb | ||
| 38 | dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb | ||
| 39 | dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb | ||
| 40 | dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb | ||
| 36 | 41 | ||
| 37 | dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb | 42 | dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb |
| 38 | dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb | 43 | dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb |
diff --git a/arch/arm/boot/dts/atlas6-evb.dts b/arch/arm/boot/dts/atlas6-evb.dts new file mode 100644 index 000000000000..ab042ca8dea1 --- /dev/null +++ b/arch/arm/boot/dts/atlas6-evb.dts | |||
| @@ -0,0 +1,78 @@ | |||
| 1 | /* | ||
| 2 | * DTS file for CSR SiRFatlas6 Evaluation Board | ||
| 3 | * | ||
| 4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /dts-v1/; | ||
| 10 | |||
| 11 | /include/ "atlas6.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "CSR SiRFatlas6 Evaluation Board"; | ||
| 15 | compatible = "sirf,atlas6-cb", "sirf,atlas6"; | ||
| 16 | |||
| 17 | memory { | ||
| 18 | reg = <0x00000000 0x20000000>; | ||
| 19 | }; | ||
| 20 | |||
| 21 | axi { | ||
| 22 | peri-iobg { | ||
| 23 | uart@b0060000 { | ||
| 24 | pinctrl-names = "default"; | ||
| 25 | pinctrl-0 = <&uart1_pins_a>; | ||
| 26 | }; | ||
| 27 | spi@b00d0000 { | ||
| 28 | status = "okay"; | ||
| 29 | pinctrl-names = "default"; | ||
| 30 | pinctrl-0 = <&spi0_pins_a>; | ||
| 31 | spi@0 { | ||
| 32 | compatible = "spidev"; | ||
| 33 | reg = <0>; | ||
| 34 | spi-max-frequency = <1000000>; | ||
| 35 | }; | ||
| 36 | }; | ||
| 37 | spi@b0170000 { | ||
| 38 | pinctrl-names = "default"; | ||
| 39 | pinctrl-0 = <&spi1_pins_a>; | ||
| 40 | }; | ||
| 41 | i2c0: i2c@b00e0000 { | ||
| 42 | status = "okay"; | ||
| 43 | pinctrl-names = "default"; | ||
| 44 | pinctrl-0 = <&i2c0_pins_a>; | ||
| 45 | lcd@40 { | ||
| 46 | compatible = "sirf,lcd"; | ||
| 47 | reg = <0x40>; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | }; | ||
| 52 | disp-iobg { | ||
| 53 | lcd@90010000 { | ||
| 54 | status = "okay"; | ||
| 55 | pinctrl-names = "default"; | ||
| 56 | pinctrl-0 = <&lcd_24pins_a>; | ||
| 57 | }; | ||
| 58 | }; | ||
| 59 | }; | ||
| 60 | display: display@0 { | ||
| 61 | panels { | ||
| 62 | panel0: panel@0 { | ||
| 63 | panel-name = "Innolux TFT"; | ||
| 64 | hactive = <800>; | ||
| 65 | vactive = <480>; | ||
| 66 | left_margin = <20>; | ||
| 67 | right_margin = <234>; | ||
| 68 | upper_margin = <3>; | ||
| 69 | lower_margin = <41>; | ||
| 70 | hsync_len = <3>; | ||
| 71 | vsync_len = <2>; | ||
| 72 | pixclock = <33264000>; | ||
| 73 | sync = <3>; | ||
| 74 | timing = <0x88>; | ||
| 75 | }; | ||
| 76 | }; | ||
| 77 | }; | ||
| 78 | }; | ||
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi new file mode 100644 index 000000000000..7d1a27949c13 --- /dev/null +++ b/arch/arm/boot/dts/atlas6.dtsi | |||
| @@ -0,0 +1,668 @@ | |||
| 1 | /* | ||
| 2 | * DTS file for CSR SiRFatlas6 SoC | ||
| 3 | * | ||
| 4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /include/ "skeleton.dtsi" | ||
| 10 | / { | ||
| 11 | compatible = "sirf,atlas6"; | ||
| 12 | #address-cells = <1>; | ||
| 13 | #size-cells = <1>; | ||
| 14 | interrupt-parent = <&intc>; | ||
| 15 | |||
| 16 | cpus { | ||
| 17 | #address-cells = <1>; | ||
| 18 | #size-cells = <0>; | ||
| 19 | |||
| 20 | cpu@0 { | ||
| 21 | reg = <0x0>; | ||
| 22 | d-cache-line-size = <32>; | ||
| 23 | i-cache-line-size = <32>; | ||
| 24 | d-cache-size = <32768>; | ||
| 25 | i-cache-size = <32768>; | ||
| 26 | /* from bootloader */ | ||
| 27 | timebase-frequency = <0>; | ||
| 28 | bus-frequency = <0>; | ||
| 29 | clock-frequency = <0>; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | |||
| 33 | axi { | ||
| 34 | compatible = "simple-bus"; | ||
| 35 | #address-cells = <1>; | ||
| 36 | #size-cells = <1>; | ||
| 37 | ranges = <0x40000000 0x40000000 0x80000000>; | ||
| 38 | |||
| 39 | intc: interrupt-controller@80020000 { | ||
| 40 | #interrupt-cells = <1>; | ||
| 41 | interrupt-controller; | ||
| 42 | compatible = "sirf,prima2-intc"; | ||
| 43 | reg = <0x80020000 0x1000>; | ||
| 44 | }; | ||
| 45 | |||
| 46 | sys-iobg { | ||
| 47 | compatible = "simple-bus"; | ||
| 48 | #address-cells = <1>; | ||
| 49 | #size-cells = <1>; | ||
| 50 | ranges = <0x88000000 0x88000000 0x40000>; | ||
| 51 | |||
| 52 | clks: clock-controller@88000000 { | ||
| 53 | compatible = "sirf,atlas6-clkc"; | ||
| 54 | reg = <0x88000000 0x1000>; | ||
| 55 | interrupts = <3>; | ||
| 56 | #clock-cells = <1>; | ||
| 57 | }; | ||
| 58 | |||
| 59 | reset-controller@88010000 { | ||
| 60 | compatible = "sirf,prima2-rstc"; | ||
| 61 | reg = <0x88010000 0x1000>; | ||
| 62 | }; | ||
| 63 | |||
| 64 | rsc-controller@88020000 { | ||
| 65 | compatible = "sirf,prima2-rsc"; | ||
| 66 | reg = <0x88020000 0x1000>; | ||
| 67 | }; | ||
| 68 | }; | ||
| 69 | |||
| 70 | mem-iobg { | ||
| 71 | compatible = "simple-bus"; | ||
| 72 | #address-cells = <1>; | ||
| 73 | #size-cells = <1>; | ||
| 74 | ranges = <0x90000000 0x90000000 0x10000>; | ||
| 75 | |||
| 76 | memory-controller@90000000 { | ||
| 77 | compatible = "sirf,prima2-memc"; | ||
| 78 | reg = <0x90000000 0x10000>; | ||
| 79 | interrupts = <27>; | ||
| 80 | clocks = <&clks 5>; | ||
| 81 | }; | ||
| 82 | }; | ||
| 83 | |||
| 84 | disp-iobg { | ||
| 85 | compatible = "simple-bus"; | ||
| 86 | #address-cells = <1>; | ||
| 87 | #size-cells = <1>; | ||
| 88 | ranges = <0x90010000 0x90010000 0x30000>; | ||
| 89 | |||
| 90 | lcd@90010000 { | ||
| 91 | compatible = "sirf,prima2-lcd"; | ||
| 92 | reg = <0x90010000 0x20000>; | ||
| 93 | interrupts = <30>; | ||
| 94 | clocks = <&clks 34>; | ||
| 95 | display=<&display>; | ||
| 96 | /* later transfer to pwm */ | ||
| 97 | bl-gpio = <&gpio 7 0>; | ||
| 98 | default-panel = <&panel0>; | ||
| 99 | }; | ||
| 100 | |||
| 101 | vpp@90020000 { | ||
| 102 | compatible = "sirf,prima2-vpp"; | ||
| 103 | reg = <0x90020000 0x10000>; | ||
| 104 | interrupts = <31>; | ||
| 105 | clocks = <&clks 35>; | ||
| 106 | }; | ||
| 107 | }; | ||
| 108 | |||
| 109 | graphics-iobg { | ||
| 110 | compatible = "simple-bus"; | ||
| 111 | #address-cells = <1>; | ||
| 112 | #size-cells = <1>; | ||
| 113 | ranges = <0x98000000 0x98000000 0x8000000>; | ||
| 114 | |||
| 115 | graphics@98000000 { | ||
| 116 | compatible = "powervr,sgx510"; | ||
| 117 | reg = <0x98000000 0x8000000>; | ||
| 118 | interrupts = <6>; | ||
| 119 | clocks = <&clks 32>; | ||
| 120 | }; | ||
| 121 | }; | ||
| 122 | |||
| 123 | dsp-iobg { | ||
| 124 | compatible = "simple-bus"; | ||
| 125 | #address-cells = <1>; | ||
| 126 | #size-cells = <1>; | ||
| 127 | ranges = <0xa8000000 0xa8000000 0x2000000>; | ||
| 128 | |||
| 129 | dspif@a8000000 { | ||
| 130 | compatible = "sirf,prima2-dspif"; | ||
| 131 | reg = <0xa8000000 0x10000>; | ||
| 132 | interrupts = <9>; | ||
| 133 | }; | ||
| 134 | |||
| 135 | gps@a8010000 { | ||
| 136 | compatible = "sirf,prima2-gps"; | ||
| 137 | reg = <0xa8010000 0x10000>; | ||
| 138 | interrupts = <7>; | ||
| 139 | clocks = <&clks 9>; | ||
| 140 | }; | ||
| 141 | |||
| 142 | dsp@a9000000 { | ||
| 143 | compatible = "sirf,prima2-dsp"; | ||
| 144 | reg = <0xa9000000 0x1000000>; | ||
| 145 | interrupts = <8>; | ||
| 146 | clocks = <&clks 8>; | ||
| 147 | }; | ||
| 148 | }; | ||
| 149 | |||
| 150 | peri-iobg { | ||
| 151 | compatible = "simple-bus"; | ||
| 152 | #address-cells = <1>; | ||
| 153 | #size-cells = <1>; | ||
| 154 | ranges = <0xb0000000 0xb0000000 0x180000>, | ||
| 155 | <0x56000000 0x56000000 0x1b00000>; | ||
| 156 | |||
| 157 | timer@b0020000 { | ||
| 158 | compatible = "sirf,prima2-tick"; | ||
| 159 | reg = <0xb0020000 0x1000>; | ||
| 160 | interrupts = <0>; | ||
| 161 | }; | ||
| 162 | |||
| 163 | nand@b0030000 { | ||
| 164 | compatible = "sirf,prima2-nand"; | ||
| 165 | reg = <0xb0030000 0x10000>; | ||
| 166 | interrupts = <41>; | ||
| 167 | clocks = <&clks 26>; | ||
| 168 | }; | ||
| 169 | |||
| 170 | audio@b0040000 { | ||
| 171 | compatible = "sirf,prima2-audio"; | ||
| 172 | reg = <0xb0040000 0x10000>; | ||
| 173 | interrupts = <35>; | ||
| 174 | clocks = <&clks 27>; | ||
| 175 | }; | ||
| 176 | |||
| 177 | uart0: uart@b0050000 { | ||
| 178 | cell-index = <0>; | ||
| 179 | compatible = "sirf,prima2-uart"; | ||
| 180 | reg = <0xb0050000 0x1000>; | ||
| 181 | interrupts = <17>; | ||
| 182 | fifosize = <128>; | ||
| 183 | clocks = <&clks 13>; | ||
| 184 | }; | ||
| 185 | |||
| 186 | uart1: uart@b0060000 { | ||
| 187 | cell-index = <1>; | ||
| 188 | compatible = "sirf,prima2-uart"; | ||
| 189 | reg = <0xb0060000 0x1000>; | ||
| 190 | interrupts = <18>; | ||
| 191 | fifosize = <32>; | ||
| 192 | clocks = <&clks 14>; | ||
| 193 | }; | ||
| 194 | |||
| 195 | uart2: uart@b0070000 { | ||
| 196 | cell-index = <2>; | ||
| 197 | compatible = "sirf,prima2-uart"; | ||
| 198 | reg = <0xb0070000 0x1000>; | ||
| 199 | interrupts = <19>; | ||
| 200 | fifosize = <128>; | ||
| 201 | clocks = <&clks 15>; | ||
| 202 | }; | ||
| 203 | |||
| 204 | usp0: usp@b0080000 { | ||
| 205 | cell-index = <0>; | ||
| 206 | compatible = "sirf,prima2-usp"; | ||
| 207 | reg = <0xb0080000 0x10000>; | ||
| 208 | interrupts = <20>; | ||
| 209 | clocks = <&clks 28>; | ||
| 210 | }; | ||
| 211 | |||
| 212 | usp1: usp@b0090000 { | ||
| 213 | cell-index = <1>; | ||
| 214 | compatible = "sirf,prima2-usp"; | ||
| 215 | reg = <0xb0090000 0x10000>; | ||
| 216 | interrupts = <21>; | ||
| 217 | clocks = <&clks 29>; | ||
| 218 | }; | ||
| 219 | |||
| 220 | dmac0: dma-controller@b00b0000 { | ||
| 221 | cell-index = <0>; | ||
| 222 | compatible = "sirf,prima2-dmac"; | ||
| 223 | reg = <0xb00b0000 0x10000>; | ||
| 224 | interrupts = <12>; | ||
| 225 | clocks = <&clks 24>; | ||
| 226 | }; | ||
| 227 | |||
| 228 | dmac1: dma-controller@b0160000 { | ||
| 229 | cell-index = <1>; | ||
| 230 | compatible = "sirf,prima2-dmac"; | ||
| 231 | reg = <0xb0160000 0x10000>; | ||
| 232 | interrupts = <13>; | ||
| 233 | clocks = <&clks 25>; | ||
| 234 | }; | ||
| 235 | |||
| 236 | vip@b00C0000 { | ||
| 237 | compatible = "sirf,prima2-vip"; | ||
| 238 | reg = <0xb00C0000 0x10000>; | ||
| 239 | clocks = <&clks 31>; | ||
| 240 | }; | ||
| 241 | |||
| 242 | spi0: spi@b00d0000 { | ||
| 243 | cell-index = <0>; | ||
| 244 | compatible = "sirf,prima2-spi"; | ||
| 245 | reg = <0xb00d0000 0x10000>; | ||
| 246 | interrupts = <15>; | ||
| 247 | sirf,spi-num-chipselects = <1>; | ||
| 248 | cs-gpios = <&gpio 0 0>; | ||
| 249 | sirf,spi-dma-rx-channel = <25>; | ||
| 250 | sirf,spi-dma-tx-channel = <20>; | ||
| 251 | #address-cells = <1>; | ||
| 252 | #size-cells = <0>; | ||
| 253 | clocks = <&clks 19>; | ||
| 254 | status = "disabled"; | ||
| 255 | }; | ||
| 256 | |||
| 257 | spi1: spi@b0170000 { | ||
| 258 | cell-index = <1>; | ||
| 259 | compatible = "sirf,prima2-spi"; | ||
| 260 | reg = <0xb0170000 0x10000>; | ||
| 261 | interrupts = <16>; | ||
| 262 | clocks = <&clks 20>; | ||
| 263 | status = "disabled"; | ||
| 264 | }; | ||
| 265 | |||
| 266 | i2c0: i2c@b00e0000 { | ||
| 267 | cell-index = <0>; | ||
| 268 | compatible = "sirf,prima2-i2c"; | ||
| 269 | reg = <0xb00e0000 0x10000>; | ||
| 270 | interrupts = <24>; | ||
| 271 | #address-cells = <1>; | ||
| 272 | #size-cells = <0>; | ||
| 273 | clocks = <&clks 17>; | ||
| 274 | }; | ||
| 275 | |||
| 276 | i2c1: i2c@b00f0000 { | ||
| 277 | cell-index = <1>; | ||
| 278 | compatible = "sirf,prima2-i2c"; | ||
| 279 | reg = <0xb00f0000 0x10000>; | ||
| 280 | interrupts = <25>; | ||
| 281 | #address-cells = <1>; | ||
| 282 | #size-cells = <0>; | ||
| 283 | clocks = <&clks 18>; | ||
| 284 | }; | ||
| 285 | |||
| 286 | tsc@b0110000 { | ||
| 287 | compatible = "sirf,prima2-tsc"; | ||
| 288 | reg = <0xb0110000 0x10000>; | ||
| 289 | interrupts = <33>; | ||
| 290 | clocks = <&clks 16>; | ||
| 291 | }; | ||
| 292 | |||
| 293 | gpio: pinctrl@b0120000 { | ||
| 294 | #gpio-cells = <2>; | ||
| 295 | #interrupt-cells = <2>; | ||
| 296 | compatible = "sirf,atlas6-pinctrl"; | ||
| 297 | reg = <0xb0120000 0x10000>; | ||
| 298 | interrupts = <43 44 45 46 47>; | ||
| 299 | gpio-controller; | ||
| 300 | interrupt-controller; | ||
| 301 | |||
| 302 | lcd_16pins_a: lcd0@0 { | ||
| 303 | lcd { | ||
| 304 | sirf,pins = "lcd_16bitsgrp"; | ||
| 305 | sirf,function = "lcd_16bits"; | ||
| 306 | }; | ||
| 307 | }; | ||
| 308 | lcd_18pins_a: lcd0@1 { | ||
| 309 | lcd { | ||
| 310 | sirf,pins = "lcd_18bitsgrp"; | ||
| 311 | sirf,function = "lcd_18bits"; | ||
| 312 | }; | ||
| 313 | }; | ||
| 314 | lcd_24pins_a: lcd0@2 { | ||
| 315 | lcd { | ||
| 316 | sirf,pins = "lcd_24bitsgrp"; | ||
| 317 | sirf,function = "lcd_24bits"; | ||
| 318 | }; | ||
| 319 | }; | ||
| 320 | lcdrom_pins_a: lcdrom0@0 { | ||
| 321 | lcd { | ||
| 322 | sirf,pins = "lcdromgrp"; | ||
| 323 | sirf,function = "lcdrom"; | ||
| 324 | }; | ||
| 325 | }; | ||
| 326 | uart0_pins_a: uart0@0 { | ||
| 327 | uart { | ||
| 328 | sirf,pins = "uart0grp"; | ||
| 329 | sirf,function = "uart0"; | ||
| 330 | }; | ||
| 331 | }; | ||
| 332 | uart1_pins_a: uart1@0 { | ||
| 333 | uart { | ||
| 334 | sirf,pins = "uart1grp"; | ||
| 335 | sirf,function = "uart1"; | ||
| 336 | }; | ||
| 337 | }; | ||
| 338 | uart2_pins_a: uart2@0 { | ||
| 339 | uart { | ||
| 340 | sirf,pins = "uart2grp"; | ||
| 341 | sirf,function = "uart2"; | ||
| 342 | }; | ||
| 343 | }; | ||
| 344 | uart2_noflow_pins_a: uart2@1 { | ||
| 345 | uart { | ||
| 346 | sirf,pins = "uart2_nostreamctrlgrp"; | ||
| 347 | sirf,function = "uart2_nostreamctrl"; | ||
| 348 | }; | ||
| 349 | }; | ||
| 350 | spi0_pins_a: spi0@0 { | ||
| 351 | spi { | ||
| 352 | sirf,pins = "spi0grp"; | ||
| 353 | sirf,function = "spi0"; | ||
| 354 | }; | ||
| 355 | }; | ||
| 356 | spi1_pins_a: spi1@0 { | ||
| 357 | spi { | ||
| 358 | sirf,pins = "spi1grp"; | ||
| 359 | sirf,function = "spi1"; | ||
| 360 | }; | ||
| 361 | }; | ||
| 362 | i2c0_pins_a: i2c0@0 { | ||
| 363 | i2c { | ||
| 364 | sirf,pins = "i2c0grp"; | ||
| 365 | sirf,function = "i2c0"; | ||
| 366 | }; | ||
| 367 | }; | ||
| 368 | i2c1_pins_a: i2c1@0 { | ||
| 369 | i2c { | ||
| 370 | sirf,pins = "i2c1grp"; | ||
| 371 | sirf,function = "i2c1"; | ||
| 372 | }; | ||
| 373 | }; | ||
| 374 | pwm0_pins_a: pwm0@0 { | ||
| 375 | pwm { | ||
| 376 | sirf,pins = "pwm0grp"; | ||
| 377 | sirf,function = "pwm0"; | ||
| 378 | }; | ||
| 379 | }; | ||
| 380 | pwm1_pins_a: pwm1@0 { | ||
| 381 | pwm { | ||
| 382 | sirf,pins = "pwm1grp"; | ||
| 383 | sirf,function = "pwm1"; | ||
| 384 | }; | ||
| 385 | }; | ||
| 386 | pwm2_pins_a: pwm2@0 { | ||
| 387 | pwm { | ||
| 388 | sirf,pins = "pwm2grp"; | ||
| 389 | sirf,function = "pwm2"; | ||
| 390 | }; | ||
| 391 | }; | ||
| 392 | pwm3_pins_a: pwm3@0 { | ||
| 393 | pwm { | ||
| 394 | sirf,pins = "pwm3grp"; | ||
| 395 | sirf,function = "pwm3"; | ||
| 396 | }; | ||
| 397 | }; | ||
| 398 | pwm4_pins_a: pwm4@0 { | ||
| 399 | pwm { | ||
| 400 | sirf,pins = "pwm4grp"; | ||
| 401 | sirf,function = "pwm4"; | ||
| 402 | }; | ||
| 403 | }; | ||
| 404 | gps_pins_a: gps@0 { | ||
| 405 | gps { | ||
| 406 | sirf,pins = "gpsgrp"; | ||
| 407 | sirf,function = "gps"; | ||
| 408 | }; | ||
| 409 | }; | ||
| 410 | vip_pins_a: vip@0 { | ||
| 411 | vip { | ||
| 412 | sirf,pins = "vipgrp"; | ||
| 413 | sirf,function = "vip"; | ||
| 414 | }; | ||
| 415 | }; | ||
| 416 | sdmmc0_pins_a: sdmmc0@0 { | ||
| 417 | sdmmc0 { | ||
| 418 | sirf,pins = "sdmmc0grp"; | ||
| 419 | sirf,function = "sdmmc0"; | ||
| 420 | }; | ||
| 421 | }; | ||
| 422 | sdmmc1_pins_a: sdmmc1@0 { | ||
| 423 | sdmmc1 { | ||
| 424 | sirf,pins = "sdmmc1grp"; | ||
| 425 | sirf,function = "sdmmc1"; | ||
| 426 | }; | ||
| 427 | }; | ||
| 428 | sdmmc2_pins_a: sdmmc2@0 { | ||
| 429 | sdmmc2 { | ||
| 430 | sirf,pins = "sdmmc2grp"; | ||
| 431 | sirf,function = "sdmmc2"; | ||
| 432 | }; | ||
| 433 | }; | ||
| 434 | sdmmc2_nowp_pins_a: sdmmc2_nowp@0 { | ||
| 435 | sdmmc2_nowp { | ||
| 436 | sirf,pins = "sdmmc2_nowpgrp"; | ||
| 437 | sirf,function = "sdmmc2_nowp"; | ||
| 438 | }; | ||
| 439 | }; | ||
| 440 | sdmmc3_pins_a: sdmmc3@0 { | ||
| 441 | sdmmc3 { | ||
| 442 | sirf,pins = "sdmmc3grp"; | ||
| 443 | sirf,function = "sdmmc3"; | ||
| 444 | }; | ||
| 445 | }; | ||
| 446 | sdmmc5_pins_a: sdmmc5@0 { | ||
| 447 | sdmmc5 { | ||
| 448 | sirf,pins = "sdmmc5grp"; | ||
| 449 | sirf,function = "sdmmc5"; | ||
| 450 | }; | ||
| 451 | }; | ||
| 452 | i2s_pins_a: i2s@0 { | ||
| 453 | i2s { | ||
| 454 | sirf,pins = "i2sgrp"; | ||
| 455 | sirf,function = "i2s"; | ||
| 456 | }; | ||
| 457 | }; | ||
| 458 | i2s_no_din_pins_a: i2s_no_din@0 { | ||
| 459 | i2s_no_din { | ||
| 460 | sirf,pins = "i2s_no_dingrp"; | ||
| 461 | sirf,function = "i2s_no_din"; | ||
| 462 | }; | ||
| 463 | }; | ||
| 464 | i2s_6chn_pins_a: i2s_6chn@0 { | ||
| 465 | i2s_6chn { | ||
| 466 | sirf,pins = "i2s_6chngrp"; | ||
| 467 | sirf,function = "i2s_6chn"; | ||
| 468 | }; | ||
| 469 | }; | ||
| 470 | ac97_pins_a: ac97@0 { | ||
| 471 | ac97 { | ||
| 472 | sirf,pins = "ac97grp"; | ||
| 473 | sirf,function = "ac97"; | ||
| 474 | }; | ||
| 475 | }; | ||
| 476 | nand_pins_a: nand@0 { | ||
| 477 | nand { | ||
| 478 | sirf,pins = "nandgrp"; | ||
| 479 | sirf,function = "nand"; | ||
| 480 | }; | ||
| 481 | }; | ||
| 482 | usp0_pins_a: usp0@0 { | ||
| 483 | usp0 { | ||
| 484 | sirf,pins = "usp0grp"; | ||
| 485 | sirf,function = "usp0"; | ||
| 486 | }; | ||
| 487 | }; | ||
| 488 | usp1_pins_a: usp1@0 { | ||
| 489 | usp1 { | ||
| 490 | sirf,pins = "usp1grp"; | ||
| 491 | sirf,function = "usp1"; | ||
| 492 | }; | ||
| 493 | }; | ||
| 494 | usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 { | ||
| 495 | usb0_upli_drvbus { | ||
| 496 | sirf,pins = "usb0_upli_drvbusgrp"; | ||
| 497 | sirf,function = "usb0_upli_drvbus"; | ||
| 498 | }; | ||
| 499 | }; | ||
| 500 | usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { | ||
| 501 | usb1_utmi_drvbus { | ||
| 502 | sirf,pins = "usb1_utmi_drvbusgrp"; | ||
| 503 | sirf,function = "usb1_utmi_drvbus"; | ||
| 504 | }; | ||
| 505 | }; | ||
| 506 | warm_rst_pins_a: warm_rst@0 { | ||
| 507 | warm_rst { | ||
| 508 | sirf,pins = "warm_rstgrp"; | ||
| 509 | sirf,function = "warm_rst"; | ||
| 510 | }; | ||
| 511 | }; | ||
| 512 | pulse_count_pins_a: pulse_count@0 { | ||
| 513 | pulse_count { | ||
| 514 | sirf,pins = "pulse_countgrp"; | ||
| 515 | sirf,function = "pulse_count"; | ||
| 516 | }; | ||
| 517 | }; | ||
| 518 | cko0_rst_pins_a: cko0_rst@0 { | ||
| 519 | cko0_rst { | ||
| 520 | sirf,pins = "cko0_rstgrp"; | ||
| 521 | sirf,function = "cko0_rst"; | ||
| 522 | }; | ||
| 523 | }; | ||
| 524 | cko1_rst_pins_a: cko1_rst@0 { | ||
| 525 | cko1_rst { | ||
| 526 | sirf,pins = "cko1_rstgrp"; | ||
| 527 | sirf,function = "cko1_rst"; | ||
| 528 | }; | ||
| 529 | }; | ||
| 530 | }; | ||
| 531 | |||
| 532 | pwm@b0130000 { | ||
| 533 | compatible = "sirf,prima2-pwm"; | ||
| 534 | reg = <0xb0130000 0x10000>; | ||
| 535 | clocks = <&clks 21>; | ||
| 536 | }; | ||
| 537 | |||
| 538 | efusesys@b0140000 { | ||
| 539 | compatible = "sirf,prima2-efuse"; | ||
| 540 | reg = <0xb0140000 0x10000>; | ||
| 541 | clocks = <&clks 22>; | ||
| 542 | }; | ||
| 543 | |||
| 544 | pulsec@b0150000 { | ||
| 545 | compatible = "sirf,prima2-pulsec"; | ||
| 546 | reg = <0xb0150000 0x10000>; | ||
| 547 | interrupts = <48>; | ||
| 548 | clocks = <&clks 23>; | ||
| 549 | }; | ||
| 550 | |||
| 551 | pci-iobg { | ||
| 552 | compatible = "sirf,prima2-pciiobg", "simple-bus"; | ||
| 553 | #address-cells = <1>; | ||
| 554 | #size-cells = <1>; | ||
| 555 | ranges = <0x56000000 0x56000000 0x1b00000>; | ||
| 556 | |||
| 557 | sd0: sdhci@56000000 { | ||
| 558 | cell-index = <0>; | ||
| 559 | compatible = "sirf,prima2-sdhc"; | ||
| 560 | reg = <0x56000000 0x100000>; | ||
| 561 | interrupts = <38>; | ||
| 562 | bus-width = <8>; | ||
| 563 | clocks = <&clks 36>; | ||
| 564 | }; | ||
| 565 | |||
| 566 | sd1: sdhci@56100000 { | ||
| 567 | cell-index = <1>; | ||
| 568 | compatible = "sirf,prima2-sdhc"; | ||
| 569 | reg = <0x56100000 0x100000>; | ||
| 570 | interrupts = <38>; | ||
| 571 | status = "disabled"; | ||
| 572 | clocks = <&clks 36>; | ||
| 573 | }; | ||
| 574 | |||
| 575 | sd2: sdhci@56200000 { | ||
| 576 | cell-index = <2>; | ||
| 577 | compatible = "sirf,prima2-sdhc"; | ||
| 578 | reg = <0x56200000 0x100000>; | ||
| 579 | interrupts = <23>; | ||
| 580 | status = "disabled"; | ||
| 581 | clocks = <&clks 37>; | ||
| 582 | }; | ||
| 583 | |||
| 584 | sd3: sdhci@56300000 { | ||
| 585 | cell-index = <3>; | ||
| 586 | compatible = "sirf,prima2-sdhc"; | ||
| 587 | reg = <0x56300000 0x100000>; | ||
| 588 | interrupts = <23>; | ||
| 589 | status = "disabled"; | ||
| 590 | clocks = <&clks 37>; | ||
| 591 | }; | ||
| 592 | |||
| 593 | sd5: sdhci@56500000 { | ||
| 594 | cell-index = <5>; | ||
| 595 | compatible = "sirf,prima2-sdhc"; | ||
| 596 | reg = <0x56500000 0x100000>; | ||
| 597 | interrupts = <39>; | ||
| 598 | status = "disabled"; | ||
| 599 | clocks = <&clks 38>; | ||
| 600 | }; | ||
| 601 | |||
| 602 | pci-copy@57900000 { | ||
| 603 | compatible = "sirf,prima2-pcicp"; | ||
| 604 | reg = <0x57900000 0x100000>; | ||
| 605 | interrupts = <40>; | ||
| 606 | }; | ||
| 607 | |||
| 608 | rom-interface@57a00000 { | ||
| 609 | compatible = "sirf,prima2-romif"; | ||
| 610 | reg = <0x57a00000 0x100000>; | ||
| 611 | }; | ||
| 612 | }; | ||
| 613 | }; | ||
| 614 | |||
| 615 | rtc-iobg { | ||
| 616 | compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; | ||
| 617 | #address-cells = <1>; | ||
| 618 | #size-cells = <1>; | ||
| 619 | reg = <0x80030000 0x10000>; | ||
| 620 | |||
| 621 | gpsrtc@1000 { | ||
| 622 | compatible = "sirf,prima2-gpsrtc"; | ||
| 623 | reg = <0x1000 0x1000>; | ||
| 624 | interrupts = <55 56 57>; | ||
| 625 | }; | ||
| 626 | |||
| 627 | sysrtc@2000 { | ||
| 628 | compatible = "sirf,prima2-sysrtc"; | ||
| 629 | reg = <0x2000 0x1000>; | ||
| 630 | interrupts = <52 53 54>; | ||
| 631 | }; | ||
| 632 | |||
| 633 | pwrc@3000 { | ||
| 634 | compatible = "sirf,prima2-pwrc"; | ||
| 635 | reg = <0x3000 0x1000>; | ||
| 636 | interrupts = <32>; | ||
| 637 | }; | ||
| 638 | }; | ||
| 639 | |||
| 640 | uus-iobg { | ||
| 641 | compatible = "simple-bus"; | ||
| 642 | #address-cells = <1>; | ||
| 643 | #size-cells = <1>; | ||
| 644 | ranges = <0xb8000000 0xb8000000 0x40000>; | ||
| 645 | |||
| 646 | usb0: usb@b00e0000 { | ||
| 647 | compatible = "chipidea,ci13611a-prima2"; | ||
| 648 | reg = <0xb8000000 0x10000>; | ||
| 649 | interrupts = <10>; | ||
| 650 | clocks = <&clks 40>; | ||
| 651 | }; | ||
| 652 | |||
| 653 | usb1: usb@b00f0000 { | ||
| 654 | compatible = "chipidea,ci13611a-prima2"; | ||
| 655 | reg = <0xb8010000 0x10000>; | ||
| 656 | interrupts = <11>; | ||
| 657 | clocks = <&clks 41>; | ||
| 658 | }; | ||
| 659 | |||
| 660 | security@b00f0000 { | ||
| 661 | compatible = "sirf,prima2-security"; | ||
| 662 | reg = <0xb8030000 0x10000>; | ||
| 663 | interrupts = <42>; | ||
| 664 | clocks = <&clks 7>; | ||
| 665 | }; | ||
| 666 | }; | ||
| 667 | }; | ||
| 668 | }; | ||
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index ad135885bd2a..8f71f40722b9 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi | |||
| @@ -47,4 +47,12 @@ | |||
| 47 | cache-unified; | 47 | cache-unified; |
| 48 | cache-level = <2>; | 48 | cache-level = <2>; |
| 49 | }; | 49 | }; |
| 50 | |||
| 51 | timer@35006000 { | ||
| 52 | compatible = "bcm,kona-timer"; | ||
| 53 | reg = <0x35006000 0x1000>; | ||
| 54 | interrupts = <0x0 7 0x4>; | ||
| 55 | clock-frequency = <32768>; | ||
| 56 | }; | ||
| 57 | |||
| 50 | }; | 58 | }; |
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index f712fb607a42..c5834a6c5bf4 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts | |||
| @@ -35,14 +35,84 @@ | |||
| 35 | clock-frequency = <100000>; | 35 | clock-frequency = <100000>; |
| 36 | pinctrl-names = "default"; | 36 | pinctrl-names = "default"; |
| 37 | pinctrl-0 = <&i2c0_pins>; | 37 | pinctrl-0 = <&i2c0_pins>; |
| 38 | |||
| 39 | tps: tps@48 { | ||
| 40 | reg = <0x48>; | ||
| 41 | }; | ||
| 38 | }; | 42 | }; |
| 39 | wdt: wdt@1c21000 { | 43 | wdt: wdt@1c21000 { |
| 40 | status = "okay"; | 44 | status = "okay"; |
| 41 | }; | 45 | }; |
| 46 | mmc0: mmc@1c40000 { | ||
| 47 | max-frequency = <50000000>; | ||
| 48 | bus-width = <4>; | ||
| 49 | status = "okay"; | ||
| 50 | pinctrl-names = "default"; | ||
| 51 | pinctrl-0 = <&mmc0_pins>; | ||
| 52 | }; | ||
| 42 | }; | 53 | }; |
| 43 | nand_cs3@62000000 { | 54 | nand_cs3@62000000 { |
| 44 | status = "okay"; | 55 | status = "okay"; |
| 45 | pinctrl-names = "default"; | 56 | pinctrl-names = "default"; |
| 46 | pinctrl-0 = <&nand_cs3_pins>; | 57 | pinctrl-0 = <&nand_cs3_pins>; |
| 47 | }; | 58 | }; |
| 59 | vbat: fixedregulator@0 { | ||
| 60 | compatible = "regulator-fixed"; | ||
| 61 | regulator-name = "vbat"; | ||
| 62 | regulator-min-microvolt = <5000000>; | ||
| 63 | regulator-max-microvolt = <5000000>; | ||
| 64 | regulator-boot-on; | ||
| 65 | }; | ||
| 66 | }; | ||
| 67 | |||
| 68 | /include/ "tps6507x.dtsi" | ||
| 69 | |||
| 70 | &tps { | ||
| 71 | vdcdc1_2-supply = <&vbat>; | ||
| 72 | vdcdc3-supply = <&vbat>; | ||
| 73 | vldo1_2-supply = <&vbat>; | ||
| 74 | |||
| 75 | regulators { | ||
| 76 | vdcdc1_reg: regulator@0 { | ||
| 77 | regulator-name = "VDCDC1_3.3V"; | ||
| 78 | regulator-min-microvolt = <3150000>; | ||
| 79 | regulator-max-microvolt = <3450000>; | ||
| 80 | regulator-always-on; | ||
| 81 | regulator-boot-on; | ||
| 82 | }; | ||
| 83 | |||
| 84 | vdcdc2_reg: regulator@1 { | ||
| 85 | regulator-name = "VDCDC2_3.3V"; | ||
| 86 | regulator-min-microvolt = <1710000>; | ||
| 87 | regulator-max-microvolt = <3450000>; | ||
| 88 | regulator-always-on; | ||
| 89 | regulator-boot-on; | ||
| 90 | ti,defdcdc_default = <1>; | ||
| 91 | }; | ||
| 92 | |||
| 93 | vdcdc3_reg: regulator@2 { | ||
| 94 | regulator-name = "VDCDC3_1.2V"; | ||
| 95 | regulator-min-microvolt = <950000>; | ||
| 96 | regulator-max-microvolt = <1350000>; | ||
| 97 | regulator-always-on; | ||
| 98 | regulator-boot-on; | ||
| 99 | ti,defdcdc_default = <1>; | ||
| 100 | }; | ||
| 101 | |||
| 102 | ldo1_reg: regulator@3 { | ||
| 103 | regulator-name = "LDO1_1.8V"; | ||
| 104 | regulator-min-microvolt = <1710000>; | ||
| 105 | regulator-max-microvolt = <1890000>; | ||
| 106 | regulator-always-on; | ||
| 107 | regulator-boot-on; | ||
| 108 | }; | ||
| 109 | |||
| 110 | ldo2_reg: regulator@4 { | ||
| 111 | regulator-name = "LDO2_1.2V"; | ||
| 112 | regulator-min-microvolt = <1140000>; | ||
| 113 | regulator-max-microvolt = <1320000>; | ||
| 114 | regulator-always-on; | ||
| 115 | regulator-boot-on; | ||
| 116 | }; | ||
| 117 | }; | ||
| 48 | }; | 118 | }; |
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 3ec1bda64356..3ade343f13cc 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi | |||
| @@ -62,6 +62,15 @@ | |||
| 62 | 0x10 0x00002200 0x0000ff00 | 62 | 0x10 0x00002200 0x0000ff00 |
| 63 | >; | 63 | >; |
| 64 | }; | 64 | }; |
| 65 | mmc0_pins: pinmux_mmc_pins { | ||
| 66 | pinctrl-single,bits = < | ||
| 67 | /* MMCSD0_DAT[3] MMCSD0_DAT[2] | ||
| 68 | * MMCSD0_DAT[1] MMCSD0_DAT[0] | ||
| 69 | * MMCSD0_CMD MMCSD0_CLK | ||
| 70 | */ | ||
| 71 | 0x28 0x00222222 0x00ffffff | ||
| 72 | >; | ||
| 73 | }; | ||
| 65 | }; | 74 | }; |
| 66 | serial0: serial@1c42000 { | 75 | serial0: serial@1c42000 { |
| 67 | compatible = "ns16550a"; | 76 | compatible = "ns16550a"; |
| @@ -107,6 +116,12 @@ | |||
| 107 | reg = <0x21000 0x1000>; | 116 | reg = <0x21000 0x1000>; |
| 108 | status = "disabled"; | 117 | status = "disabled"; |
| 109 | }; | 118 | }; |
| 119 | mmc0: mmc@1c40000 { | ||
| 120 | compatible = "ti,da830-mmc"; | ||
| 121 | reg = <0x40000 0x1000>; | ||
| 122 | interrupts = <16>; | ||
| 123 | status = "disabled"; | ||
| 124 | }; | ||
| 110 | }; | 125 | }; |
| 111 | nand_cs3@62000000 { | 126 | nand_cs3@62000000 { |
| 112 | compatible = "ti,davinci-nand"; | 127 | compatible = "ti,davinci-nand"; |
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts index 67f8670c4d6a..9bf49b3826ea 100644 --- a/arch/arm/boot/dts/msm8660-surf.dts +++ b/arch/arm/boot/dts/msm8660-surf.dts | |||
| @@ -16,19 +16,13 @@ | |||
| 16 | }; | 16 | }; |
| 17 | 17 | ||
| 18 | timer@2000004 { | 18 | timer@2000004 { |
| 19 | compatible = "qcom,msm-gpt", "qcom,msm-timer"; | 19 | compatible = "qcom,scss-timer", "qcom,msm-timer"; |
| 20 | interrupts = <1 1 0x301>; | 20 | interrupts = <1 0 0x301>, |
| 21 | reg = <0x02000004 0x10>; | 21 | <1 1 0x301>, |
| 22 | clock-frequency = <32768>; | 22 | <1 2 0x301>; |
| 23 | cpu-offset = <0x40000>; | 23 | reg = <0x02000000 0x100>; |
| 24 | }; | 24 | clock-frequency = <27000000>, |
| 25 | 25 | <32768>; | |
| 26 | timer@2000024 { | ||
| 27 | compatible = "qcom,msm-dgt", "qcom,msm-timer"; | ||
| 28 | interrupts = <1 0 0x301>; | ||
| 29 | reg = <0x02000024 0x10>, | ||
| 30 | <0x02000034 0x4>; | ||
| 31 | clock-frequency = <6750000>; | ||
| 32 | cpu-offset = <0x40000>; | 26 | cpu-offset = <0x40000>; |
| 33 | }; | 27 | }; |
| 34 | 28 | ||
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts index c9b09a813a4b..2e4d87a125d6 100644 --- a/arch/arm/boot/dts/msm8960-cdp.dts +++ b/arch/arm/boot/dts/msm8960-cdp.dts | |||
| @@ -15,20 +15,14 @@ | |||
| 15 | < 0x02002000 0x1000 >; | 15 | < 0x02002000 0x1000 >; |
| 16 | }; | 16 | }; |
| 17 | 17 | ||
| 18 | timer@200a004 { | 18 | timer@200a000 { |
| 19 | compatible = "qcom,msm-gpt", "qcom,msm-timer"; | 19 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; |
| 20 | interrupts = <1 2 0x301>; | 20 | interrupts = <1 1 0x301>, |
| 21 | reg = <0x0200a004 0x10>; | 21 | <1 2 0x301>, |
| 22 | clock-frequency = <32768>; | 22 | <1 3 0x301>; |
| 23 | cpu-offset = <0x80000>; | 23 | reg = <0x0200a000 0x100>; |
| 24 | }; | 24 | clock-frequency = <27000000>, |
| 25 | 25 | <32768>; | |
| 26 | timer@200a024 { | ||
| 27 | compatible = "qcom,msm-dgt", "qcom,msm-timer"; | ||
| 28 | interrupts = <1 1 0x301>; | ||
| 29 | reg = <0x0200a024 0x10>, | ||
| 30 | <0x0200a034 0x4>; | ||
| 31 | clock-frequency = <6750000>; | ||
| 32 | cpu-offset = <0x80000>; | 26 | cpu-offset = <0x80000>; |
| 33 | }; | 27 | }; |
| 34 | 28 | ||
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi new file mode 100644 index 000000000000..fe5c6f213271 --- /dev/null +++ b/arch/arm/boot/dts/r8a7779.dtsi | |||
| @@ -0,0 +1,98 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree Source for Renesas r8a7779 | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Renesas Solutions Corp. | ||
| 5 | * Copyright (C) 2013 Simon Horman | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public License | ||
| 8 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 9 | * kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /include/ "skeleton.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | compatible = "renesas,r8a7779"; | ||
| 16 | |||
| 17 | cpus { | ||
| 18 | #address-cells = <1>; | ||
| 19 | #size-cells = <0>; | ||
| 20 | |||
| 21 | cpu@0 { | ||
| 22 | device_type = "cpu"; | ||
| 23 | compatible = "arm,cortex-a9"; | ||
| 24 | reg = <0>; | ||
| 25 | }; | ||
| 26 | cpu@1 { | ||
| 27 | device_type = "cpu"; | ||
| 28 | compatible = "arm,cortex-a9"; | ||
| 29 | reg = <1>; | ||
| 30 | }; | ||
| 31 | cpu@2 { | ||
| 32 | device_type = "cpu"; | ||
| 33 | compatible = "arm,cortex-a9"; | ||
| 34 | reg = <2>; | ||
| 35 | }; | ||
| 36 | cpu@3 { | ||
| 37 | device_type = "cpu"; | ||
| 38 | compatible = "arm,cortex-a9"; | ||
| 39 | reg = <3>; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | |||
| 43 | gic: interrupt-controller@f0001000 { | ||
| 44 | compatible = "arm,cortex-a9-gic"; | ||
| 45 | #interrupt-cells = <3>; | ||
| 46 | interrupt-controller; | ||
| 47 | reg = <0xf0001000 0x1000>, | ||
| 48 | <0xf0000100 0x100>; | ||
| 49 | }; | ||
| 50 | |||
| 51 | i2c0: i2c@0xffc70000 { | ||
| 52 | #address-cells = <1>; | ||
| 53 | #size-cells = <0>; | ||
| 54 | compatible = "renesas,rmobile-iic"; | ||
| 55 | reg = <0xffc70000 0x1000>; | ||
| 56 | interrupt-parent = <&gic>; | ||
| 57 | interrupts = <0 79 0x4>; | ||
| 58 | }; | ||
| 59 | |||
| 60 | i2c1: i2c@0xffc71000 { | ||
| 61 | #address-cells = <1>; | ||
| 62 | #size-cells = <0>; | ||
| 63 | compatible = "renesas,rmobile-iic"; | ||
| 64 | reg = <0xffc71000 0x1000>; | ||
| 65 | interrupt-parent = <&gic>; | ||
| 66 | interrupts = <0 82 0x4>; | ||
| 67 | }; | ||
| 68 | |||
| 69 | i2c2: i2c@0xffc72000 { | ||
| 70 | #address-cells = <1>; | ||
| 71 | #size-cells = <0>; | ||
| 72 | compatible = "renesas,rmobile-iic"; | ||
| 73 | reg = <0xffc72000 0x1000>; | ||
| 74 | interrupt-parent = <&gic>; | ||
| 75 | interrupts = <0 80 0x4>; | ||
| 76 | }; | ||
| 77 | |||
| 78 | i2c3: i2c@0xffc73000 { | ||
| 79 | #address-cells = <1>; | ||
| 80 | #size-cells = <0>; | ||
| 81 | compatible = "renesas,rmobile-iic"; | ||
| 82 | reg = <0xffc73000 0x1000>; | ||
| 83 | interrupt-parent = <&gic>; | ||
| 84 | interrupts = <0 81 0x4>; | ||
| 85 | }; | ||
| 86 | |||
| 87 | thermal@ffc48000 { | ||
| 88 | compatible = "renesas,rcar-thermal"; | ||
| 89 | reg = <0xffc48000 0x38>; | ||
| 90 | }; | ||
| 91 | |||
| 92 | sata: sata@fc600000 { | ||
| 93 | compatible = "renesas,rcar-sata"; | ||
| 94 | reg = <0xfc600000 0x2000>; | ||
| 95 | interrupt-parent = <&gic>; | ||
| 96 | interrupts = <0 100 0x4>; | ||
| 97 | }; | ||
| 98 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi new file mode 100644 index 000000000000..39b0458d365a --- /dev/null +++ b/arch/arm/boot/dts/sama5d3.dtsi | |||
| @@ -0,0 +1,1031 @@ | |||
| 1 | /* | ||
| 2 | * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC | ||
| 3 | * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC | ||
| 4 | * | ||
| 5 | * Copyright (C) 2013 Atmel, | ||
| 6 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 7 | * | ||
| 8 | * Licensed under GPLv2 or later. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /include/ "skeleton.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "Atmel SAMA5D3 family SoC"; | ||
| 15 | compatible = "atmel,sama5d3", "atmel,sama5"; | ||
| 16 | interrupt-parent = <&aic>; | ||
| 17 | |||
| 18 | aliases { | ||
| 19 | serial0 = &dbgu; | ||
| 20 | serial1 = &usart0; | ||
| 21 | serial2 = &usart1; | ||
| 22 | serial3 = &usart2; | ||
| 23 | serial4 = &usart3; | ||
| 24 | gpio0 = &pioA; | ||
| 25 | gpio1 = &pioB; | ||
| 26 | gpio2 = &pioC; | ||
| 27 | gpio3 = &pioD; | ||
| 28 | gpio4 = &pioE; | ||
| 29 | tcb0 = &tcb0; | ||
| 30 | tcb1 = &tcb1; | ||
| 31 | i2c0 = &i2c0; | ||
| 32 | i2c1 = &i2c1; | ||
| 33 | i2c2 = &i2c2; | ||
| 34 | ssc0 = &ssc0; | ||
| 35 | ssc1 = &ssc1; | ||
| 36 | }; | ||
| 37 | cpus { | ||
| 38 | cpu@0 { | ||
| 39 | compatible = "arm,cortex-a5"; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | |||
| 43 | memory { | ||
| 44 | reg = <0x20000000 0x8000000>; | ||
| 45 | }; | ||
| 46 | |||
| 47 | ahb { | ||
| 48 | compatible = "simple-bus"; | ||
| 49 | #address-cells = <1>; | ||
| 50 | #size-cells = <1>; | ||
| 51 | ranges; | ||
| 52 | |||
| 53 | apb { | ||
| 54 | compatible = "simple-bus"; | ||
| 55 | #address-cells = <1>; | ||
| 56 | #size-cells = <1>; | ||
| 57 | ranges; | ||
| 58 | |||
| 59 | mmc0: mmc@f0000000 { | ||
| 60 | compatible = "atmel,hsmci"; | ||
| 61 | reg = <0xf0000000 0x600>; | ||
| 62 | interrupts = <21 4 0>; | ||
| 63 | pinctrl-names = "default"; | ||
| 64 | pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; | ||
| 65 | status = "disabled"; | ||
| 66 | #address-cells = <1>; | ||
| 67 | #size-cells = <0>; | ||
| 68 | }; | ||
| 69 | |||
| 70 | spi0: spi@f0004000 { | ||
| 71 | #address-cells = <1>; | ||
| 72 | #size-cells = <0>; | ||
| 73 | compatible = "atmel,at91sam9x5-spi"; | ||
| 74 | reg = <0xf0004000 0x100>; | ||
| 75 | interrupts = <24 4 3>; | ||
| 76 | cs-gpios = <&pioD 13 0 | ||
| 77 | &pioD 14 0 /* conflicts with SCK0 and CANRX0 */ | ||
| 78 | &pioD 15 0 /* conflicts with CTS0 and CANTX0 */ | ||
| 79 | &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */ | ||
| 80 | >; | ||
| 81 | pinctrl-names = "default"; | ||
| 82 | pinctrl-0 = <&pinctrl_spi0>; | ||
| 83 | status = "disabled"; | ||
| 84 | }; | ||
| 85 | |||
| 86 | ssc0: ssc@f0008000 { | ||
| 87 | compatible = "atmel,at91sam9g45-ssc"; | ||
| 88 | reg = <0xf0008000 0x4000>; | ||
| 89 | interrupts = <38 4 4>; | ||
| 90 | pinctrl-names = "default"; | ||
| 91 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | ||
| 92 | status = "disabled"; | ||
| 93 | }; | ||
| 94 | |||
| 95 | can0: can@f000c000 { | ||
| 96 | compatible = "atmel,at91sam9x5-can"; | ||
| 97 | reg = <0xf000c000 0x300>; | ||
| 98 | interrupts = <40 4 3>; | ||
| 99 | pinctrl-names = "default"; | ||
| 100 | pinctrl-0 = <&pinctrl_can0_rx_tx>; | ||
| 101 | status = "disabled"; | ||
| 102 | }; | ||
| 103 | |||
| 104 | tcb0: timer@f0010000 { | ||
| 105 | compatible = "atmel,at91sam9x5-tcb"; | ||
| 106 | reg = <0xf0010000 0x100>; | ||
| 107 | interrupts = <26 4 0>; | ||
| 108 | }; | ||
| 109 | |||
| 110 | i2c0: i2c@f0014000 { | ||
| 111 | compatible = "atmel,at91sam9x5-i2c"; | ||
| 112 | reg = <0xf0014000 0x4000>; | ||
| 113 | interrupts = <18 4 6>; | ||
| 114 | pinctrl-names = "default"; | ||
| 115 | pinctrl-0 = <&pinctrl_i2c0>; | ||
| 116 | #address-cells = <1>; | ||
| 117 | #size-cells = <0>; | ||
| 118 | status = "disabled"; | ||
| 119 | }; | ||
| 120 | |||
| 121 | i2c1: i2c@f0018000 { | ||
| 122 | compatible = "atmel,at91sam9x5-i2c"; | ||
| 123 | reg = <0xf0018000 0x4000>; | ||
| 124 | interrupts = <19 4 6>; | ||
| 125 | pinctrl-names = "default"; | ||
| 126 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 127 | #address-cells = <1>; | ||
| 128 | #size-cells = <0>; | ||
| 129 | status = "disabled"; | ||
| 130 | }; | ||
| 131 | |||
| 132 | usart0: serial@f001c000 { | ||
| 133 | compatible = "atmel,at91sam9260-usart"; | ||
| 134 | reg = <0xf001c000 0x100>; | ||
| 135 | interrupts = <12 4 5>; | ||
| 136 | pinctrl-names = "default"; | ||
| 137 | pinctrl-0 = <&pinctrl_usart0>; | ||
| 138 | status = "disabled"; | ||
| 139 | }; | ||
| 140 | |||
| 141 | usart1: serial@f0020000 { | ||
| 142 | compatible = "atmel,at91sam9260-usart"; | ||
| 143 | reg = <0xf0020000 0x100>; | ||
| 144 | interrupts = <13 4 5>; | ||
| 145 | pinctrl-names = "default"; | ||
| 146 | pinctrl-0 = <&pinctrl_usart1>; | ||
| 147 | status = "disabled"; | ||
| 148 | }; | ||
| 149 | |||
| 150 | macb0: ethernet@f0028000 { | ||
| 151 | compatible = "cnds,pc302-gem", "cdns,gem"; | ||
| 152 | reg = <0xf0028000 0x100>; | ||
| 153 | interrupts = <34 4 3>; | ||
| 154 | pinctrl-names = "default"; | ||
| 155 | pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; | ||
| 156 | status = "disabled"; | ||
| 157 | }; | ||
| 158 | |||
| 159 | isi: isi@f0034000 { | ||
| 160 | compatible = "atmel,at91sam9g45-isi"; | ||
| 161 | reg = <0xf0034000 0x4000>; | ||
| 162 | interrupts = <37 4 5>; | ||
| 163 | status = "disabled"; | ||
| 164 | }; | ||
| 165 | |||
| 166 | mmc1: mmc@f8000000 { | ||
| 167 | compatible = "atmel,hsmci"; | ||
| 168 | reg = <0xf8000000 0x600>; | ||
| 169 | interrupts = <22 4 0>; | ||
| 170 | pinctrl-names = "default"; | ||
| 171 | pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; | ||
| 172 | status = "disabled"; | ||
| 173 | #address-cells = <1>; | ||
| 174 | #size-cells = <0>; | ||
| 175 | }; | ||
| 176 | |||
| 177 | mmc2: mmc@f8004000 { | ||
| 178 | compatible = "atmel,hsmci"; | ||
| 179 | reg = <0xf8004000 0x600>; | ||
| 180 | interrupts = <23 4 0>; | ||
| 181 | pinctrl-names = "default"; | ||
| 182 | pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; | ||
| 183 | status = "disabled"; | ||
| 184 | #address-cells = <1>; | ||
| 185 | #size-cells = <0>; | ||
| 186 | }; | ||
| 187 | |||
| 188 | spi1: spi@f8008000 { | ||
| 189 | #address-cells = <1>; | ||
| 190 | #size-cells = <0>; | ||
| 191 | compatible = "atmel,at91sam9x5-spi"; | ||
| 192 | reg = <0xf8008000 0x100>; | ||
| 193 | interrupts = <25 4 3>; | ||
| 194 | cs-gpios = <&pioC 25 0 | ||
| 195 | &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */ | ||
| 196 | &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */ | ||
| 197 | &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */ | ||
| 198 | >; | ||
| 199 | pinctrl-names = "default"; | ||
| 200 | pinctrl-0 = <&pinctrl_spi1>; | ||
| 201 | status = "disabled"; | ||
| 202 | }; | ||
| 203 | |||
| 204 | ssc1: ssc@f800c000 { | ||
| 205 | compatible = "atmel,at91sam9g45-ssc"; | ||
| 206 | reg = <0xf800c000 0x4000>; | ||
| 207 | interrupts = <39 4 4>; | ||
| 208 | pinctrl-names = "default"; | ||
| 209 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | ||
| 210 | status = "disabled"; | ||
| 211 | }; | ||
| 212 | |||
| 213 | can1: can@f8010000 { | ||
| 214 | compatible = "atmel,at91sam9x5-can"; | ||
| 215 | reg = <0xf8010000 0x300>; | ||
| 216 | interrupts = <41 4 3>; | ||
| 217 | pinctrl-names = "default"; | ||
| 218 | pinctrl-0 = <&pinctrl_can1_rx_tx>; | ||
| 219 | }; | ||
| 220 | |||
| 221 | tcb1: timer@f8014000 { | ||
| 222 | compatible = "atmel,at91sam9x5-tcb"; | ||
| 223 | reg = <0xf8014000 0x100>; | ||
| 224 | interrupts = <27 4 0>; | ||
| 225 | }; | ||
| 226 | |||
| 227 | adc0: adc@f8018000 { | ||
| 228 | compatible = "atmel,at91sam9260-adc"; | ||
| 229 | reg = <0xf8018000 0x100>; | ||
| 230 | interrupts = <29 4 5>; | ||
| 231 | pinctrl-names = "default"; | ||
| 232 | pinctrl-0 = < | ||
| 233 | &pinctrl_adc0_adtrg | ||
| 234 | &pinctrl_adc0_ad0 | ||
| 235 | &pinctrl_adc0_ad1 | ||
| 236 | &pinctrl_adc0_ad2 | ||
| 237 | &pinctrl_adc0_ad3 | ||
| 238 | &pinctrl_adc0_ad4 | ||
| 239 | &pinctrl_adc0_ad5 | ||
| 240 | &pinctrl_adc0_ad6 | ||
| 241 | &pinctrl_adc0_ad7 | ||
| 242 | &pinctrl_adc0_ad8 | ||
| 243 | &pinctrl_adc0_ad9 | ||
| 244 | &pinctrl_adc0_ad10 | ||
| 245 | &pinctrl_adc0_ad11 | ||
| 246 | >; | ||
| 247 | atmel,adc-channel-base = <0x50>; | ||
| 248 | atmel,adc-channels-used = <0xfff>; | ||
| 249 | atmel,adc-drdy-mask = <0x1000000>; | ||
| 250 | atmel,adc-num-channels = <12>; | ||
| 251 | atmel,adc-startup-time = <40>; | ||
| 252 | atmel,adc-status-register = <0x30>; | ||
| 253 | atmel,adc-trigger-register = <0xc0>; | ||
| 254 | atmel,adc-use-external; | ||
| 255 | atmel,adc-vref = <3000>; | ||
| 256 | atmel,adc-res = <10 12>; | ||
| 257 | atmel,adc-res-names = "lowres", "highres"; | ||
| 258 | status = "disabled"; | ||
| 259 | |||
| 260 | trigger@0 { | ||
| 261 | trigger-name = "external-rising"; | ||
| 262 | trigger-value = <0x1>; | ||
| 263 | trigger-external; | ||
| 264 | }; | ||
| 265 | trigger@1 { | ||
| 266 | trigger-name = "external-falling"; | ||
| 267 | trigger-value = <0x2>; | ||
| 268 | trigger-external; | ||
| 269 | }; | ||
| 270 | trigger@2 { | ||
| 271 | trigger-name = "external-any"; | ||
| 272 | trigger-value = <0x3>; | ||
| 273 | trigger-external; | ||
| 274 | }; | ||
| 275 | trigger@3 { | ||
| 276 | trigger-name = "continuous"; | ||
| 277 | trigger-value = <0x6>; | ||
| 278 | }; | ||
| 279 | }; | ||
| 280 | |||
| 281 | tsadcc: tsadcc@f8018000 { | ||
| 282 | compatible = "atmel,at91sam9x5-tsadcc"; | ||
| 283 | reg = <0xf8018000 0x4000>; | ||
| 284 | interrupts = <29 4 5>; | ||
| 285 | atmel,tsadcc_clock = <300000>; | ||
| 286 | atmel,filtering_average = <0x03>; | ||
| 287 | atmel,pendet_debounce = <0x08>; | ||
| 288 | atmel,pendet_sensitivity = <0x02>; | ||
| 289 | atmel,ts_sample_hold_time = <0x0a>; | ||
| 290 | status = "disabled"; | ||
| 291 | }; | ||
| 292 | |||
| 293 | i2c2: i2c@f801c000 { | ||
| 294 | compatible = "atmel,at91sam9x5-i2c"; | ||
| 295 | reg = <0xf801c000 0x4000>; | ||
| 296 | interrupts = <20 4 6>; | ||
| 297 | #address-cells = <1>; | ||
| 298 | #size-cells = <0>; | ||
| 299 | status = "disabled"; | ||
| 300 | }; | ||
| 301 | |||
| 302 | usart2: serial@f8020000 { | ||
| 303 | compatible = "atmel,at91sam9260-usart"; | ||
| 304 | reg = <0xf8020000 0x100>; | ||
| 305 | interrupts = <14 4 5>; | ||
| 306 | pinctrl-names = "default"; | ||
| 307 | pinctrl-0 = <&pinctrl_usart2>; | ||
| 308 | status = "disabled"; | ||
| 309 | }; | ||
| 310 | |||
| 311 | usart3: serial@f8024000 { | ||
| 312 | compatible = "atmel,at91sam9260-usart"; | ||
| 313 | reg = <0xf8024000 0x100>; | ||
| 314 | interrupts = <15 4 5>; | ||
| 315 | pinctrl-names = "default"; | ||
| 316 | pinctrl-0 = <&pinctrl_usart3>; | ||
| 317 | status = "disabled"; | ||
| 318 | }; | ||
| 319 | |||
| 320 | macb1: ethernet@f802c000 { | ||
| 321 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | ||
| 322 | reg = <0xf802c000 0x100>; | ||
| 323 | interrupts = <35 4 3>; | ||
| 324 | pinctrl-names = "default"; | ||
| 325 | pinctrl-0 = <&pinctrl_macb1_rmii>; | ||
| 326 | status = "disabled"; | ||
| 327 | }; | ||
| 328 | |||
| 329 | sha@f8034000 { | ||
| 330 | compatible = "atmel,sam9g46-sha"; | ||
| 331 | reg = <0xf8034000 0x100>; | ||
| 332 | interrupts = <42 4 0>; | ||
| 333 | }; | ||
| 334 | |||
| 335 | aes@f8038000 { | ||
| 336 | compatible = "atmel,sam9g46-aes"; | ||
| 337 | reg = <0xf8038000 0x100>; | ||
| 338 | interrupts = <43 4 0>; | ||
| 339 | }; | ||
| 340 | |||
| 341 | tdes@f803c000 { | ||
| 342 | compatible = "atmel,sam9g46-tdes"; | ||
| 343 | reg = <0xf803c000 0x100>; | ||
| 344 | interrupts = <44 4 0>; | ||
| 345 | }; | ||
| 346 | |||
| 347 | dma0: dma-controller@ffffe600 { | ||
| 348 | compatible = "atmel,at91sam9g45-dma"; | ||
| 349 | reg = <0xffffe600 0x200>; | ||
| 350 | interrupts = <30 4 0>; | ||
| 351 | #dma-cells = <1>; | ||
| 352 | }; | ||
| 353 | |||
| 354 | dma1: dma-controller@ffffe800 { | ||
| 355 | compatible = "atmel,at91sam9g45-dma"; | ||
| 356 | reg = <0xffffe800 0x200>; | ||
| 357 | interrupts = <31 4 0>; | ||
| 358 | #dma-cells = <1>; | ||
| 359 | }; | ||
| 360 | |||
| 361 | ramc0: ramc@ffffea00 { | ||
| 362 | compatible = "atmel,at91sam9g45-ddramc"; | ||
| 363 | reg = <0xffffea00 0x200>; | ||
| 364 | }; | ||
| 365 | |||
| 366 | dbgu: serial@ffffee00 { | ||
| 367 | compatible = "atmel,at91sam9260-usart"; | ||
| 368 | reg = <0xffffee00 0x200>; | ||
| 369 | interrupts = <2 4 7>; | ||
| 370 | pinctrl-names = "default"; | ||
| 371 | pinctrl-0 = <&pinctrl_dbgu>; | ||
| 372 | status = "disabled"; | ||
| 373 | }; | ||
| 374 | |||
| 375 | aic: interrupt-controller@fffff000 { | ||
| 376 | #interrupt-cells = <3>; | ||
| 377 | compatible = "atmel,sama5d3-aic"; | ||
| 378 | interrupt-controller; | ||
| 379 | reg = <0xfffff000 0x200>; | ||
| 380 | atmel,external-irqs = <47>; | ||
| 381 | }; | ||
| 382 | |||
| 383 | pinctrl@fffff200 { | ||
| 384 | #address-cells = <1>; | ||
| 385 | #size-cells = <1>; | ||
| 386 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; | ||
| 387 | ranges = <0xfffff200 0xfffff200 0xa00>; | ||
| 388 | atmel,mux-mask = < | ||
| 389 | /* A B C */ | ||
| 390 | 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ | ||
| 391 | 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ | ||
| 392 | 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ | ||
| 393 | 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ | ||
| 394 | 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ | ||
| 395 | >; | ||
| 396 | |||
| 397 | /* shared pinctrl settings */ | ||
| 398 | adc0 { | ||
| 399 | pinctrl_adc0_adtrg: adc0_adtrg { | ||
| 400 | atmel,pins = | ||
| 401 | <3 19 0x1 0x0>; /* PD19 periph A ADTRG */ | ||
| 402 | }; | ||
| 403 | pinctrl_adc0_ad0: adc0_ad0 { | ||
| 404 | atmel,pins = | ||
| 405 | <3 20 0x1 0x0>; /* PD20 periph A AD0 */ | ||
| 406 | }; | ||
| 407 | pinctrl_adc0_ad1: adc0_ad1 { | ||
| 408 | atmel,pins = | ||
| 409 | <3 21 0x1 0x0>; /* PD21 periph A AD1 */ | ||
| 410 | }; | ||
| 411 | pinctrl_adc0_ad2: adc0_ad2 { | ||
| 412 | atmel,pins = | ||
| 413 | <3 22 0x1 0x0>; /* PD22 periph A AD2 */ | ||
| 414 | }; | ||
| 415 | pinctrl_adc0_ad3: adc0_ad3 { | ||
| 416 | atmel,pins = | ||
| 417 | <3 23 0x1 0x0>; /* PD23 periph A AD3 */ | ||
| 418 | }; | ||
| 419 | pinctrl_adc0_ad4: adc0_ad4 { | ||
| 420 | atmel,pins = | ||
| 421 | <3 24 0x1 0x0>; /* PD24 periph A AD4 */ | ||
| 422 | }; | ||
| 423 | pinctrl_adc0_ad5: adc0_ad5 { | ||
| 424 | atmel,pins = | ||
| 425 | <3 25 0x1 0x0>; /* PD25 periph A AD5 */ | ||
| 426 | }; | ||
| 427 | pinctrl_adc0_ad6: adc0_ad6 { | ||
| 428 | atmel,pins = | ||
| 429 | <3 26 0x1 0x0>; /* PD26 periph A AD6 */ | ||
| 430 | }; | ||
| 431 | pinctrl_adc0_ad7: adc0_ad7 { | ||
| 432 | atmel,pins = | ||
| 433 | <3 27 0x1 0x0>; /* PD27 periph A AD7 */ | ||
| 434 | }; | ||
| 435 | pinctrl_adc0_ad8: adc0_ad8 { | ||
| 436 | atmel,pins = | ||
| 437 | <3 28 0x1 0x0>; /* PD28 periph A AD8 */ | ||
| 438 | }; | ||
| 439 | pinctrl_adc0_ad9: adc0_ad9 { | ||
| 440 | atmel,pins = | ||
| 441 | <3 29 0x1 0x0>; /* PD29 periph A AD9 */ | ||
| 442 | }; | ||
| 443 | pinctrl_adc0_ad10: adc0_ad10 { | ||
| 444 | atmel,pins = | ||
| 445 | <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */ | ||
| 446 | }; | ||
| 447 | pinctrl_adc0_ad11: adc0_ad11 { | ||
| 448 | atmel,pins = | ||
| 449 | <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */ | ||
| 450 | }; | ||
| 451 | }; | ||
| 452 | |||
| 453 | can0 { | ||
| 454 | pinctrl_can0_rx_tx: can0_rx_tx { | ||
| 455 | atmel,pins = | ||
| 456 | <3 14 0x3 0x0 /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ | ||
| 457 | 3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ | ||
| 458 | }; | ||
| 459 | }; | ||
| 460 | |||
| 461 | can1 { | ||
| 462 | pinctrl_can1_rx_tx: can1_rx_tx { | ||
| 463 | atmel,pins = | ||
| 464 | <1 14 0x2 0x0 /* PB14 periph B RX, conflicts with GCRS */ | ||
| 465 | 1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */ | ||
| 466 | }; | ||
| 467 | }; | ||
| 468 | |||
| 469 | dbgu { | ||
| 470 | pinctrl_dbgu: dbgu-0 { | ||
| 471 | atmel,pins = | ||
| 472 | <1 30 0x1 0x0 /* PB30 periph A */ | ||
| 473 | 1 31 0x1 0x1>; /* PB31 periph A with pullup */ | ||
| 474 | }; | ||
| 475 | }; | ||
| 476 | |||
| 477 | i2c0 { | ||
| 478 | pinctrl_i2c0: i2c0-0 { | ||
| 479 | atmel,pins = | ||
| 480 | <0 30 0x1 0x0 /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ | ||
| 481 | 0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ | ||
| 482 | }; | ||
| 483 | }; | ||
| 484 | |||
| 485 | i2c1 { | ||
| 486 | pinctrl_i2c1: i2c1-0 { | ||
| 487 | atmel,pins = | ||
| 488 | <2 26 0x2 0x0 /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ | ||
| 489 | 2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ | ||
| 490 | }; | ||
| 491 | }; | ||
| 492 | |||
| 493 | isi { | ||
| 494 | pinctrl_isi: isi-0 { | ||
| 495 | atmel,pins = | ||
| 496 | <0 16 0x3 0x0 /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ | ||
| 497 | 0 17 0x3 0x0 /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ | ||
| 498 | 0 18 0x3 0x0 /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ | ||
| 499 | 0 19 0x3 0x0 /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ | ||
| 500 | 0 20 0x3 0x0 /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ | ||
| 501 | 0 21 0x3 0x0 /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ | ||
| 502 | 0 22 0x3 0x0 /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ | ||
| 503 | 0 23 0x3 0x0 /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ | ||
| 504 | 2 30 0x3 0x0 /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ | ||
| 505 | 0 31 0x3 0x0 /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ | ||
| 506 | 0 30 0x3 0x0 /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ | ||
| 507 | 2 29 0x3 0x0 /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ | ||
| 508 | 2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ | ||
| 509 | }; | ||
| 510 | pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 { | ||
| 511 | atmel,pins = | ||
| 512 | <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */ | ||
| 513 | }; | ||
| 514 | }; | ||
| 515 | |||
| 516 | lcd { | ||
| 517 | pinctrl_lcd: lcd-0 { | ||
| 518 | atmel,pins = | ||
| 519 | <0 24 0x1 0x0 /* PA24 periph A LCDPWM */ | ||
| 520 | 0 26 0x1 0x0 /* PA26 periph A LCDVSYNC */ | ||
| 521 | 0 27 0x1 0x0 /* PA27 periph A LCDHSYNC */ | ||
| 522 | 0 25 0x1 0x0 /* PA25 periph A LCDDISP */ | ||
| 523 | 0 29 0x1 0x0 /* PA29 periph A LCDDEN */ | ||
| 524 | 0 28 0x1 0x0 /* PA28 periph A LCDPCK */ | ||
| 525 | 0 0 0x1 0x0 /* PA0 periph A LCDD0 pin */ | ||
| 526 | 0 1 0x1 0x0 /* PA1 periph A LCDD1 pin */ | ||
| 527 | 0 2 0x1 0x0 /* PA2 periph A LCDD2 pin */ | ||
| 528 | 0 3 0x1 0x0 /* PA3 periph A LCDD3 pin */ | ||
| 529 | 0 4 0x1 0x0 /* PA4 periph A LCDD4 pin */ | ||
| 530 | 0 5 0x1 0x0 /* PA5 periph A LCDD5 pin */ | ||
| 531 | 0 6 0x1 0x0 /* PA6 periph A LCDD6 pin */ | ||
| 532 | 0 7 0x1 0x0 /* PA7 periph A LCDD7 pin */ | ||
| 533 | 0 8 0x1 0x0 /* PA8 periph A LCDD8 pin */ | ||
| 534 | 0 9 0x1 0x0 /* PA9 periph A LCDD9 pin */ | ||
| 535 | 0 10 0x1 0x0 /* PA10 periph A LCDD10 pin */ | ||
| 536 | 0 11 0x1 0x0 /* PA11 periph A LCDD11 pin */ | ||
| 537 | 0 12 0x1 0x0 /* PA12 periph A LCDD12 pin */ | ||
| 538 | 0 13 0x1 0x0 /* PA13 periph A LCDD13 pin */ | ||
| 539 | 0 14 0x1 0x0 /* PA14 periph A LCDD14 pin */ | ||
| 540 | 0 15 0x1 0x0 /* PA15 periph A LCDD15 pin */ | ||
| 541 | 2 14 0x3 0x0 /* PC14 periph C LCDD16 pin */ | ||
| 542 | 2 13 0x3 0x0 /* PC13 periph C LCDD17 pin */ | ||
| 543 | 2 12 0x3 0x0 /* PC12 periph C LCDD18 pin */ | ||
| 544 | 2 11 0x3 0x0 /* PC11 periph C LCDD19 pin */ | ||
| 545 | 2 10 0x3 0x0 /* PC10 periph C LCDD20 pin */ | ||
| 546 | 2 15 0x3 0x0 /* PC15 periph C LCDD21 pin */ | ||
| 547 | 4 27 0x3 0x0 /* PE27 periph C LCDD22 pin */ | ||
| 548 | 4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */ | ||
| 549 | }; | ||
| 550 | }; | ||
| 551 | |||
| 552 | macb0 { | ||
| 553 | pinctrl_macb0_data_rgmii: macb0_data_rgmii { | ||
| 554 | atmel,pins = | ||
| 555 | <1 0 0x1 0x0 /* PB0 periph A GTX0, conflicts with PWMH0 */ | ||
| 556 | 1 1 0x1 0x0 /* PB1 periph A GTX1, conflicts with PWML0 */ | ||
| 557 | 1 2 0x1 0x0 /* PB2 periph A GTX2, conflicts with TK1 */ | ||
| 558 | 1 3 0x1 0x0 /* PB3 periph A GTX3, conflicts with TF1 */ | ||
| 559 | 1 4 0x1 0x0 /* PB4 periph A GRX0, conflicts with PWMH1 */ | ||
| 560 | 1 5 0x1 0x0 /* PB5 periph A GRX1, conflicts with PWML1 */ | ||
| 561 | 1 6 0x1 0x0 /* PB6 periph A GRX2, conflicts with TD1 */ | ||
| 562 | 1 7 0x1 0x0>; /* PB7 periph A GRX3, conflicts with RK1 */ | ||
| 563 | }; | ||
| 564 | pinctrl_macb0_data_gmii: macb0_data_gmii { | ||
| 565 | atmel,pins = | ||
| 566 | <1 19 0x2 0x0 /* PB19 periph B GTX4, conflicts with MCI1_CDA */ | ||
| 567 | 1 20 0x2 0x0 /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ | ||
| 568 | 1 21 0x2 0x0 /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ | ||
| 569 | 1 22 0x2 0x0 /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ | ||
| 570 | 1 23 0x2 0x0 /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ | ||
| 571 | 1 24 0x2 0x0 /* PB24 periph B GRX5, conflicts with MCI1_CK */ | ||
| 572 | 1 25 0x2 0x0 /* PB25 periph B GRX6, conflicts with SCK1 */ | ||
| 573 | 1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */ | ||
| 574 | }; | ||
| 575 | pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { | ||
| 576 | atmel,pins = | ||
| 577 | <1 8 0x1 0x0 /* PB8 periph A GTXCK, conflicts with PWMH2 */ | ||
| 578 | 1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ | ||
| 579 | 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ | ||
| 580 | 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ | ||
| 581 | 1 16 0x1 0x0 /* PB16 periph A GMDC */ | ||
| 582 | 1 17 0x1 0x0 /* PB17 periph A GMDIO */ | ||
| 583 | 1 18 0x1 0x0>; /* PB18 periph A G125CK */ | ||
| 584 | }; | ||
| 585 | pinctrl_macb0_signal_gmii: macb0_signal_gmii { | ||
| 586 | atmel,pins = | ||
| 587 | <1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ | ||
| 588 | 1 10 0x1 0x0 /* PB10 periph A GTXER, conflicts with RF1 */ | ||
| 589 | 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ | ||
| 590 | 1 12 0x1 0x0 /* PB12 periph A GRXDV, conflicts with PWMH3 */ | ||
| 591 | 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ | ||
| 592 | 1 14 0x1 0x0 /* PB14 periph A GCRS, conflicts with CANRX1 */ | ||
| 593 | 1 15 0x1 0x0 /* PB15 periph A GCOL, conflicts with CANTX1 */ | ||
| 594 | 1 16 0x1 0x0 /* PB16 periph A GMDC */ | ||
| 595 | 1 17 0x1 0x0 /* PB17 periph A GMDIO */ | ||
| 596 | 1 27 0x2 0x0>; /* PB27 periph B G125CKO */ | ||
| 597 | }; | ||
| 598 | |||
| 599 | }; | ||
| 600 | |||
| 601 | macb1 { | ||
| 602 | pinctrl_macb1_rmii: macb1_rmii-0 { | ||
| 603 | atmel,pins = | ||
| 604 | <2 0 0x1 0x0 /* PC0 periph A ETX0, conflicts with TIOA3 */ | ||
| 605 | 2 1 0x1 0x0 /* PC1 periph A ETX1, conflicts with TIOB3 */ | ||
| 606 | 2 2 0x1 0x0 /* PC2 periph A ERX0, conflicts with TCLK3 */ | ||
| 607 | 2 3 0x1 0x0 /* PC3 periph A ERX1, conflicts with TIOA4 */ | ||
| 608 | 2 4 0x1 0x0 /* PC4 periph A ETXEN, conflicts with TIOB4 */ | ||
| 609 | 2 5 0x1 0x0 /* PC5 periph A ECRSDV,conflicts with TCLK4 */ | ||
| 610 | 2 6 0x1 0x0 /* PC6 periph A ERXER, conflicts with TIOA5 */ | ||
| 611 | 2 7 0x1 0x0 /* PC7 periph A EREFCK, conflicts with TIOB5 */ | ||
| 612 | 2 8 0x1 0x0 /* PC8 periph A EMDC, conflicts with TCLK5 */ | ||
| 613 | 2 9 0x1 0x0>; /* PC9 periph A EMDIO */ | ||
| 614 | }; | ||
| 615 | }; | ||
| 616 | |||
| 617 | mmc0 { | ||
| 618 | pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { | ||
| 619 | atmel,pins = | ||
| 620 | <3 9 0x1 0x0 /* PD9 periph A MCI0_CK */ | ||
| 621 | 3 0 0x1 0x1 /* PD0 periph A MCI0_CDA with pullup */ | ||
| 622 | 3 1 0x1 0x1>; /* PD1 periph A MCI0_DA0 with pullup */ | ||
| 623 | }; | ||
| 624 | pinctrl_mmc0_dat1_3: mmc0_dat1_3 { | ||
| 625 | atmel,pins = | ||
| 626 | <3 2 0x1 0x1 /* PD2 periph A MCI0_DA1 with pullup */ | ||
| 627 | 3 3 0x1 0x1 /* PD3 periph A MCI0_DA2 with pullup */ | ||
| 628 | 3 4 0x1 0x1>; /* PD4 periph A MCI0_DA3 with pullup */ | ||
| 629 | }; | ||
| 630 | pinctrl_mmc0_dat4_7: mmc0_dat4_7 { | ||
| 631 | atmel,pins = | ||
| 632 | <3 5 0x1 0x1 /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ | ||
| 633 | 3 6 0x1 0x1 /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ | ||
| 634 | 3 7 0x1 0x1 /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ | ||
| 635 | 3 8 0x1 0x1>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ | ||
| 636 | }; | ||
| 637 | }; | ||
| 638 | |||
| 639 | mmc1 { | ||
| 640 | pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { | ||
| 641 | atmel,pins = | ||
| 642 | <1 24 0x1 0x0 /* PB24 periph A MCI1_CK, conflicts with GRX5 */ | ||
| 643 | 1 19 0x1 0x1 /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ | ||
| 644 | 1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ | ||
| 645 | }; | ||
| 646 | pinctrl_mmc1_dat1_3: mmc1_dat1_3 { | ||
| 647 | atmel,pins = | ||
| 648 | <1 21 0x1 0x1 /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ | ||
| 649 | 1 22 0x1 0x1 /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ | ||
| 650 | 1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ | ||
| 651 | }; | ||
| 652 | }; | ||
| 653 | |||
| 654 | mmc2 { | ||
| 655 | pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { | ||
| 656 | atmel,pins = | ||
| 657 | <2 15 0x1 0x0 /* PC15 periph A MCI2_CK, conflicts with PCK2 */ | ||
| 658 | 2 10 0x1 0x1 /* PC10 periph A MCI2_CDA with pullup */ | ||
| 659 | 2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */ | ||
| 660 | }; | ||
| 661 | pinctrl_mmc2_dat1_3: mmc2_dat1_3 { | ||
| 662 | atmel,pins = | ||
| 663 | <2 12 0x1 0x0 /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ | ||
| 664 | 2 13 0x1 0x0 /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ | ||
| 665 | 2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ | ||
| 666 | }; | ||
| 667 | }; | ||
| 668 | |||
| 669 | nand0 { | ||
| 670 | pinctrl_nand0_ale_cle: nand0_ale_cle-0 { | ||
| 671 | atmel,pins = | ||
| 672 | <4 21 0x1 0x1 /* PE21 periph A with pullup */ | ||
| 673 | 4 22 0x1 0x1>; /* PE22 periph A with pullup */ | ||
| 674 | }; | ||
| 675 | }; | ||
| 676 | |||
| 677 | pioA: gpio@fffff200 { | ||
| 678 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 679 | reg = <0xfffff200 0x100>; | ||
| 680 | interrupts = <6 4 1>; | ||
| 681 | #gpio-cells = <2>; | ||
| 682 | gpio-controller; | ||
| 683 | interrupt-controller; | ||
| 684 | #interrupt-cells = <2>; | ||
| 685 | }; | ||
| 686 | |||
| 687 | pioB: gpio@fffff400 { | ||
| 688 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 689 | reg = <0xfffff400 0x100>; | ||
| 690 | interrupts = <7 4 1>; | ||
| 691 | #gpio-cells = <2>; | ||
| 692 | gpio-controller; | ||
| 693 | interrupt-controller; | ||
| 694 | #interrupt-cells = <2>; | ||
| 695 | }; | ||
| 696 | |||
| 697 | pioC: gpio@fffff600 { | ||
| 698 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 699 | reg = <0xfffff600 0x100>; | ||
| 700 | interrupts = <8 4 1>; | ||
| 701 | #gpio-cells = <2>; | ||
| 702 | gpio-controller; | ||
| 703 | interrupt-controller; | ||
| 704 | #interrupt-cells = <2>; | ||
| 705 | }; | ||
| 706 | |||
| 707 | pioD: gpio@fffff800 { | ||
| 708 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 709 | reg = <0xfffff800 0x100>; | ||
| 710 | interrupts = <9 4 1>; | ||
| 711 | #gpio-cells = <2>; | ||
| 712 | gpio-controller; | ||
| 713 | interrupt-controller; | ||
| 714 | #interrupt-cells = <2>; | ||
| 715 | }; | ||
| 716 | |||
| 717 | pioE: gpio@fffffa00 { | ||
| 718 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | ||
| 719 | reg = <0xfffffa00 0x100>; | ||
| 720 | interrupts = <10 4 1>; | ||
| 721 | #gpio-cells = <2>; | ||
| 722 | gpio-controller; | ||
| 723 | interrupt-controller; | ||
| 724 | #interrupt-cells = <2>; | ||
| 725 | }; | ||
| 726 | |||
| 727 | spi0 { | ||
| 728 | pinctrl_spi0: spi0-0 { | ||
| 729 | atmel,pins = | ||
| 730 | <3 10 0x1 0x0 /* PD10 periph A SPI0_MISO pin */ | ||
| 731 | 3 11 0x1 0x0 /* PD11 periph A SPI0_MOSI pin */ | ||
| 732 | 3 12 0x1 0x0 /* PD12 periph A SPI0_SPCK pin */ | ||
| 733 | 3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */ | ||
| 734 | }; | ||
| 735 | }; | ||
| 736 | |||
| 737 | spi1 { | ||
| 738 | pinctrl_spi1: spi1-0 { | ||
| 739 | atmel,pins = | ||
| 740 | <2 22 0x1 0x0 /* PC22 periph A SPI1_MISO pin */ | ||
| 741 | 2 23 0x1 0x0 /* PC23 periph A SPI1_MOSI pin */ | ||
| 742 | 2 24 0x1 0x0 /* PC24 periph A SPI1_SPCK pin */ | ||
| 743 | 2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */ | ||
| 744 | }; | ||
| 745 | }; | ||
| 746 | |||
| 747 | ssc0 { | ||
| 748 | pinctrl_ssc0_tx: ssc0_tx { | ||
| 749 | atmel,pins = | ||
| 750 | <2 16 0x1 0x0 /* PC16 periph A TK0 */ | ||
| 751 | 2 17 0x1 0x0 /* PC17 periph A TF0 */ | ||
| 752 | 2 18 0x1 0x0>; /* PC18 periph A TD0 */ | ||
| 753 | }; | ||
| 754 | |||
| 755 | pinctrl_ssc0_rx: ssc0_rx { | ||
| 756 | atmel,pins = | ||
| 757 | <2 19 0x1 0x0 /* PC19 periph A RK0 */ | ||
| 758 | 2 20 0x1 0x0 /* PC20 periph A RF0 */ | ||
| 759 | 2 21 0x1 0x0>; /* PC21 periph A RD0 */ | ||
| 760 | }; | ||
| 761 | }; | ||
| 762 | |||
| 763 | ssc1 { | ||
| 764 | pinctrl_ssc1_tx: ssc1_tx { | ||
| 765 | atmel,pins = | ||
| 766 | <1 2 0x2 0x0 /* PB2 periph B TK1, conflicts with GTX2 */ | ||
| 767 | 1 3 0x2 0x0 /* PB3 periph B TF1, conflicts with GTX3 */ | ||
| 768 | 1 6 0x2 0x0>; /* PB6 periph B TD1, conflicts with TD1 */ | ||
| 769 | }; | ||
| 770 | |||
| 771 | pinctrl_ssc1_rx: ssc1_rx { | ||
| 772 | atmel,pins = | ||
| 773 | <1 7 0x2 0x0 /* PB7 periph B RK1, conflicts with EREFCK */ | ||
| 774 | 1 10 0x2 0x0 /* PB10 periph B RF1, conflicts with GTXER */ | ||
| 775 | 1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */ | ||
| 776 | }; | ||
| 777 | }; | ||
| 778 | |||
| 779 | uart0 { | ||
| 780 | pinctrl_uart0: uart0-0 { | ||
| 781 | atmel,pins = | ||
| 782 | <2 29 0x1 0x0 /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ | ||
| 783 | 2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ | ||
| 784 | }; | ||
| 785 | }; | ||
| 786 | |||
| 787 | uart1 { | ||
| 788 | pinctrl_uart1: uart1-0 { | ||
| 789 | atmel,pins = | ||
| 790 | <0 30 0x2 0x0 /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ | ||
| 791 | 0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ | ||
| 792 | }; | ||
| 793 | }; | ||
| 794 | |||
| 795 | usart0 { | ||
| 796 | pinctrl_usart0: usart0-0 { | ||
| 797 | atmel,pins = | ||
| 798 | <3 17 0x1 0x0 /* PD17 periph A */ | ||
| 799 | 3 18 0x1 0x1>; /* PD18 periph A with pullup */ | ||
| 800 | }; | ||
| 801 | |||
| 802 | pinctrl_usart0_rts_cts: usart0_rts_cts-0 { | ||
| 803 | atmel,pins = | ||
| 804 | <3 15 0x1 0x0 /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ | ||
| 805 | 3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ | ||
| 806 | }; | ||
| 807 | }; | ||
| 808 | |||
| 809 | usart1 { | ||
| 810 | pinctrl_usart1: usart1-0 { | ||
| 811 | atmel,pins = | ||
| 812 | <1 28 0x1 0x0 /* PB28 periph A */ | ||
| 813 | 1 29 0x1 0x1>; /* PB29 periph A with pullup */ | ||
| 814 | }; | ||
| 815 | |||
| 816 | pinctrl_usart1_rts_cts: usart1_rts_cts-0 { | ||
| 817 | atmel,pins = | ||
| 818 | <1 26 0x1 0x0 /* PB26 periph A, conflicts with GRX7 */ | ||
| 819 | 1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */ | ||
| 820 | }; | ||
| 821 | }; | ||
| 822 | |||
| 823 | usart2 { | ||
| 824 | pinctrl_usart2: usart2-0 { | ||
| 825 | atmel,pins = | ||
| 826 | <4 25 0x2 0x0 /* PE25 periph B, conflicts with A25 */ | ||
| 827 | 4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */ | ||
| 828 | }; | ||
| 829 | |||
| 830 | pinctrl_usart2_rts_cts: usart2_rts_cts-0 { | ||
| 831 | atmel,pins = | ||
| 832 | <4 23 0x2 0x0 /* PE23 periph B, conflicts with A23 */ | ||
| 833 | 4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */ | ||
| 834 | }; | ||
| 835 | }; | ||
| 836 | |||
| 837 | usart3 { | ||
| 838 | pinctrl_usart3: usart3-0 { | ||
| 839 | atmel,pins = | ||
| 840 | <4 18 0x2 0x0 /* PE18 periph B, conflicts with A18 */ | ||
| 841 | 4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */ | ||
| 842 | }; | ||
| 843 | |||
| 844 | pinctrl_usart3_rts_cts: usart3_rts_cts-0 { | ||
| 845 | atmel,pins = | ||
| 846 | <4 16 0x2 0x0 /* PE16 periph B, conflicts with A16 */ | ||
| 847 | 4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */ | ||
| 848 | }; | ||
| 849 | }; | ||
| 850 | }; | ||
| 851 | |||
| 852 | pmc: pmc@fffffc00 { | ||
| 853 | compatible = "atmel,at91rm9200-pmc"; | ||
| 854 | reg = <0xfffffc00 0x120>; | ||
| 855 | }; | ||
| 856 | |||
| 857 | rstc@fffffe00 { | ||
| 858 | compatible = "atmel,at91sam9g45-rstc"; | ||
| 859 | reg = <0xfffffe00 0x10>; | ||
| 860 | }; | ||
| 861 | |||
| 862 | pit: timer@fffffe30 { | ||
| 863 | compatible = "atmel,at91sam9260-pit"; | ||
| 864 | reg = <0xfffffe30 0xf>; | ||
| 865 | interrupts = <3 4 5>; | ||
| 866 | }; | ||
| 867 | |||
| 868 | watchdog@fffffe40 { | ||
| 869 | compatible = "atmel,at91sam9260-wdt"; | ||
| 870 | reg = <0xfffffe40 0x10>; | ||
| 871 | status = "disabled"; | ||
| 872 | }; | ||
| 873 | |||
| 874 | rtc@fffffeb0 { | ||
| 875 | compatible = "atmel,at91rm9200-rtc"; | ||
| 876 | reg = <0xfffffeb0 0x30>; | ||
| 877 | interrupts = <1 4 7>; | ||
| 878 | }; | ||
| 879 | }; | ||
| 880 | |||
| 881 | usb0: gadget@00500000 { | ||
| 882 | #address-cells = <1>; | ||
| 883 | #size-cells = <0>; | ||
| 884 | compatible = "atmel,at91sam9rl-udc"; | ||
| 885 | reg = <0x00500000 0x100000 | ||
| 886 | 0xf8030000 0x4000>; | ||
| 887 | interrupts = <33 4 2>; | ||
| 888 | status = "disabled"; | ||
| 889 | |||
| 890 | ep0 { | ||
| 891 | reg = <0>; | ||
| 892 | atmel,fifo-size = <64>; | ||
| 893 | atmel,nb-banks = <1>; | ||
| 894 | }; | ||
| 895 | |||
| 896 | ep1 { | ||
| 897 | reg = <1>; | ||
| 898 | atmel,fifo-size = <1024>; | ||
| 899 | atmel,nb-banks = <3>; | ||
| 900 | atmel,can-dma; | ||
| 901 | atmel,can-isoc; | ||
| 902 | }; | ||
| 903 | |||
| 904 | ep2 { | ||
| 905 | reg = <2>; | ||
| 906 | atmel,fifo-size = <1024>; | ||
| 907 | atmel,nb-banks = <3>; | ||
| 908 | atmel,can-dma; | ||
| 909 | atmel,can-isoc; | ||
| 910 | }; | ||
| 911 | |||
| 912 | ep3 { | ||
| 913 | reg = <3>; | ||
| 914 | atmel,fifo-size = <1024>; | ||
| 915 | atmel,nb-banks = <2>; | ||
| 916 | atmel,can-dma; | ||
| 917 | }; | ||
| 918 | |||
| 919 | ep4 { | ||
| 920 | reg = <4>; | ||
| 921 | atmel,fifo-size = <1024>; | ||
| 922 | atmel,nb-banks = <2>; | ||
| 923 | atmel,can-dma; | ||
| 924 | }; | ||
| 925 | |||
| 926 | ep5 { | ||
| 927 | reg = <5>; | ||
| 928 | atmel,fifo-size = <1024>; | ||
| 929 | atmel,nb-banks = <2>; | ||
| 930 | atmel,can-dma; | ||
| 931 | }; | ||
| 932 | |||
| 933 | ep6 { | ||
| 934 | reg = <6>; | ||
| 935 | atmel,fifo-size = <1024>; | ||
| 936 | atmel,nb-banks = <2>; | ||
| 937 | atmel,can-dma; | ||
| 938 | }; | ||
| 939 | |||
| 940 | ep7 { | ||
| 941 | reg = <7>; | ||
| 942 | atmel,fifo-size = <1024>; | ||
| 943 | atmel,nb-banks = <2>; | ||
| 944 | atmel,can-dma; | ||
| 945 | }; | ||
| 946 | |||
| 947 | ep8 { | ||
| 948 | reg = <8>; | ||
| 949 | atmel,fifo-size = <1024>; | ||
| 950 | atmel,nb-banks = <2>; | ||
| 951 | }; | ||
| 952 | |||
| 953 | ep9 { | ||
| 954 | reg = <9>; | ||
| 955 | atmel,fifo-size = <1024>; | ||
| 956 | atmel,nb-banks = <2>; | ||
| 957 | }; | ||
| 958 | |||
| 959 | ep10 { | ||
| 960 | reg = <10>; | ||
| 961 | atmel,fifo-size = <1024>; | ||
| 962 | atmel,nb-banks = <2>; | ||
| 963 | }; | ||
| 964 | |||
| 965 | ep11 { | ||
| 966 | reg = <11>; | ||
| 967 | atmel,fifo-size = <1024>; | ||
| 968 | atmel,nb-banks = <2>; | ||
| 969 | }; | ||
| 970 | |||
| 971 | ep12 { | ||
| 972 | reg = <12>; | ||
| 973 | atmel,fifo-size = <1024>; | ||
| 974 | atmel,nb-banks = <2>; | ||
| 975 | }; | ||
| 976 | |||
| 977 | ep13 { | ||
| 978 | reg = <13>; | ||
| 979 | atmel,fifo-size = <1024>; | ||
| 980 | atmel,nb-banks = <2>; | ||
| 981 | }; | ||
| 982 | |||
| 983 | ep14 { | ||
| 984 | reg = <14>; | ||
| 985 | atmel,fifo-size = <1024>; | ||
| 986 | atmel,nb-banks = <2>; | ||
| 987 | }; | ||
| 988 | |||
| 989 | ep15 { | ||
| 990 | reg = <15>; | ||
| 991 | atmel,fifo-size = <1024>; | ||
| 992 | atmel,nb-banks = <2>; | ||
| 993 | }; | ||
| 994 | }; | ||
| 995 | |||
| 996 | usb1: ohci@00600000 { | ||
| 997 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | ||
| 998 | reg = <0x00600000 0x100000>; | ||
| 999 | interrupts = <32 4 2>; | ||
| 1000 | status = "disabled"; | ||
| 1001 | }; | ||
| 1002 | |||
| 1003 | usb2: ehci@00700000 { | ||
| 1004 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | ||
| 1005 | reg = <0x00700000 0x100000>; | ||
| 1006 | interrupts = <32 4 2>; | ||
| 1007 | status = "disabled"; | ||
| 1008 | }; | ||
| 1009 | |||
| 1010 | nand0: nand@60000000 { | ||
| 1011 | compatible = "atmel,at91rm9200-nand"; | ||
| 1012 | #address-cells = <1>; | ||
| 1013 | #size-cells = <1>; | ||
| 1014 | reg = < 0x60000000 0x01000000 /* EBI CS3 */ | ||
| 1015 | 0xffffc070 0x00000490 /* SMC PMECC regs */ | ||
| 1016 | 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ | ||
| 1017 | 0x00100000 0x00100000 /* ROM code */ | ||
| 1018 | 0x70000000 0x10000000 /* NFC Command Registers */ | ||
| 1019 | 0xffffc000 0x00000070 /* NFC HSMC regs */ | ||
| 1020 | 0x00200000 0x00100000 /* NFC SRAM banks */ | ||
| 1021 | >; | ||
| 1022 | interrupts = <5 4 6>; | ||
| 1023 | atmel,nand-addr-offset = <21>; | ||
| 1024 | atmel,nand-cmd-offset = <22>; | ||
| 1025 | pinctrl-names = "default"; | ||
| 1026 | pinctrl-0 = <&pinctrl_nand0_ale_cle>; | ||
| 1027 | atmel,pmecc-lookup-table-offset = <0x10000 0x18000>; | ||
| 1028 | status = "disabled"; | ||
| 1029 | }; | ||
| 1030 | }; | ||
| 1031 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts new file mode 100644 index 000000000000..fa5d216f1db7 --- /dev/null +++ b/arch/arm/boot/dts/sama5d31ek.dts | |||
| @@ -0,0 +1,51 @@ | |||
| 1 | /* | ||
| 2 | * sama5d31ek.dts - Device Tree file for SAMA5D31-EK board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /dts-v1/; | ||
| 10 | /include/ "sama5d3xmb.dtsi" | ||
| 11 | /include/ "sama5d3xdm.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "Atmel SAMA5D31-EK"; | ||
| 15 | compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 16 | |||
| 17 | ahb { | ||
| 18 | apb { | ||
| 19 | spi0: spi@f0004000 { | ||
| 20 | status = "okay"; | ||
| 21 | }; | ||
| 22 | |||
| 23 | ssc0: ssc@f0008000 { | ||
| 24 | status = "okay"; | ||
| 25 | }; | ||
| 26 | |||
| 27 | i2c0: i2c@f0014000 { | ||
| 28 | status = "okay"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | i2c1: i2c@f0018000 { | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | macb1: ethernet@f802c000 { | ||
| 36 | status = "okay"; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 41 | leds { | ||
| 42 | d3 { | ||
| 43 | label = "d3"; | ||
| 44 | gpios = <&pioE 24 0>; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | |||
| 48 | sound { | ||
| 49 | status = "okay"; | ||
| 50 | }; | ||
| 51 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts new file mode 100644 index 000000000000..c38c9433d7a5 --- /dev/null +++ b/arch/arm/boot/dts/sama5d33ek.dts | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * sama5d33ek.dts - Device Tree file for SAMA5D33-EK board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /dts-v1/; | ||
| 10 | /include/ "sama5d3xmb.dtsi" | ||
| 11 | /include/ "sama5d3xdm.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "Atmel SAMA5D33-EK"; | ||
| 15 | compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 16 | |||
| 17 | ahb { | ||
| 18 | apb { | ||
| 19 | spi0: spi@f0004000 { | ||
| 20 | status = "okay"; | ||
| 21 | }; | ||
| 22 | |||
| 23 | ssc0: ssc@f0008000 { | ||
| 24 | status = "okay"; | ||
| 25 | }; | ||
| 26 | |||
| 27 | i2c0: i2c@f0014000 { | ||
| 28 | status = "okay"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | i2c1: i2c@f0018000 { | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | macb0: ethernet@f0028000 { | ||
| 36 | status = "okay"; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 41 | sound { | ||
| 42 | status = "okay"; | ||
| 43 | }; | ||
| 44 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts new file mode 100644 index 000000000000..d2739f8d7ae9 --- /dev/null +++ b/arch/arm/boot/dts/sama5d34ek.dts | |||
| @@ -0,0 +1,61 @@ | |||
| 1 | /* | ||
| 2 | * sama5d34ek.dts - Device Tree file for SAMA5D34-EK board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /dts-v1/; | ||
| 10 | /include/ "sama5d3xmb.dtsi" | ||
| 11 | /include/ "sama5d3xdm.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "Atmel SAMA5D34-EK"; | ||
| 15 | compatible = "atmel,sama5d34ek", "atmel,sama5ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 16 | |||
| 17 | ahb { | ||
| 18 | apb { | ||
| 19 | spi0: spi@f0004000 { | ||
| 20 | status = "okay"; | ||
| 21 | }; | ||
| 22 | |||
| 23 | ssc0: ssc@f0008000 { | ||
| 24 | status = "okay"; | ||
| 25 | }; | ||
| 26 | |||
| 27 | can0: can@f000c000 { | ||
| 28 | status = "okay"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | i2c0: i2c@f0014000 { | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | i2c1: i2c@f0018000 { | ||
| 36 | status = "okay"; | ||
| 37 | |||
| 38 | 24c256@50 { | ||
| 39 | compatible = "24c256"; | ||
| 40 | reg = <0x50>; | ||
| 41 | pagesize = <64>; | ||
| 42 | }; | ||
| 43 | }; | ||
| 44 | |||
| 45 | macb0: ethernet@f0028000 { | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | leds { | ||
| 52 | d3 { | ||
| 53 | label = "d3"; | ||
| 54 | gpios = <&pioE 24 0>; | ||
| 55 | }; | ||
| 56 | }; | ||
| 57 | |||
| 58 | sound { | ||
| 59 | status = "okay"; | ||
| 60 | }; | ||
| 61 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts new file mode 100644 index 000000000000..a488fc4e9777 --- /dev/null +++ b/arch/arm/boot/dts/sama5d35ek.dts | |||
| @@ -0,0 +1,56 @@ | |||
| 1 | /* | ||
| 2 | * sama5d35ek.dts - Device Tree file for SAMA5D35-EK board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /dts-v1/; | ||
| 10 | /include/ "sama5d3xmb.dtsi" | ||
| 11 | |||
| 12 | / { | ||
| 13 | model = "Atmel SAMA5D35-EK"; | ||
| 14 | compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 15 | |||
| 16 | ahb { | ||
| 17 | apb { | ||
| 18 | spi0: spi@f0004000 { | ||
| 19 | status = "okay"; | ||
| 20 | }; | ||
| 21 | |||
| 22 | can0: can@f000c000 { | ||
| 23 | status = "okay"; | ||
| 24 | }; | ||
| 25 | |||
| 26 | i2c1: i2c@f0018000 { | ||
| 27 | status = "okay"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | macb0: ethernet@f0028000 { | ||
| 31 | status = "okay"; | ||
| 32 | }; | ||
| 33 | |||
| 34 | isi: isi@f0034000 { | ||
| 35 | status = "okay"; | ||
| 36 | }; | ||
| 37 | |||
| 38 | macb1: ethernet@f802c000 { | ||
| 39 | status = "okay"; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | |||
| 44 | gpio_keys { | ||
| 45 | compatible = "gpio-keys"; | ||
| 46 | #address-cells = <1>; | ||
| 47 | #size-cells = <0>; | ||
| 48 | |||
| 49 | pb_user1 { | ||
| 50 | label = "pb_user1"; | ||
| 51 | gpios = <&pioE 27 0>; | ||
| 52 | linux,code = <0x100>; | ||
| 53 | gpio-key,wakeup; | ||
| 54 | }; | ||
| 55 | }; | ||
| 56 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi new file mode 100644 index 000000000000..1f8ed404626c --- /dev/null +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi | |||
| @@ -0,0 +1,91 @@ | |||
| 1 | /* | ||
| 2 | * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /include/ "sama5d3.dtsi" | ||
| 10 | |||
| 11 | / { | ||
| 12 | compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 13 | |||
| 14 | chosen { | ||
| 15 | bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs"; | ||
| 16 | }; | ||
| 17 | |||
| 18 | memory { | ||
| 19 | reg = <0x20000000 0x20000000>; | ||
| 20 | }; | ||
| 21 | |||
| 22 | clocks { | ||
| 23 | #address-cells = <1>; | ||
| 24 | #size-cells = <1>; | ||
| 25 | ranges; | ||
| 26 | |||
| 27 | main_clock: clock@0 { | ||
| 28 | compatible = "atmel,osc", "fixed-clock"; | ||
| 29 | clock-frequency = <12000000>; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | |||
| 33 | ahb { | ||
| 34 | apb { | ||
| 35 | macb0: ethernet@f0028000 { | ||
| 36 | phy-mode = "rgmii"; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | |||
| 40 | nand0: nand@60000000 { | ||
| 41 | nand-bus-width = <8>; | ||
| 42 | nand-ecc-mode = "hw"; | ||
| 43 | atmel,has-pmecc; | ||
| 44 | atmel,pmecc-cap = <4>; | ||
| 45 | atmel,pmecc-sector-size = <512>; | ||
| 46 | atmel,has-nfc; | ||
| 47 | atmel,use-nfc-sram; | ||
| 48 | nand-on-flash-bbt; | ||
| 49 | status = "okay"; | ||
| 50 | |||
| 51 | at91bootstrap@0 { | ||
| 52 | label = "at91bootstrap"; | ||
| 53 | reg = <0x0 0x40000>; | ||
| 54 | }; | ||
| 55 | |||
| 56 | bootloader@40000 { | ||
| 57 | label = "bootloader"; | ||
| 58 | reg = <0x40000 0x80000>; | ||
| 59 | }; | ||
| 60 | |||
| 61 | bootloaderenv@c0000 { | ||
| 62 | label = "bootloader env"; | ||
| 63 | reg = <0xc0000 0xc0000>; | ||
| 64 | }; | ||
| 65 | |||
| 66 | dtb@180000 { | ||
| 67 | label = "device tree"; | ||
| 68 | reg = <0x180000 0x80000>; | ||
| 69 | }; | ||
| 70 | |||
| 71 | kernel@200000 { | ||
| 72 | label = "kernel"; | ||
| 73 | reg = <0x200000 0x600000>; | ||
| 74 | }; | ||
| 75 | |||
| 76 | rootfs@800000 { | ||
| 77 | label = "rootfs"; | ||
| 78 | reg = <0x800000 0x0f800000>; | ||
| 79 | }; | ||
| 80 | }; | ||
| 81 | }; | ||
| 82 | |||
| 83 | leds { | ||
| 84 | compatible = "gpio-leds"; | ||
| 85 | |||
| 86 | d2 { | ||
| 87 | label = "d2"; | ||
| 88 | gpios = <&pioE 25 1>; /* PE25, conflicts with A25, RXD2 */ | ||
| 89 | }; | ||
| 90 | }; | ||
| 91 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi new file mode 100644 index 000000000000..4b8830eb2060 --- /dev/null +++ b/arch/arm/boot/dts/sama5d3xdm.dtsi | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | /* | ||
| 2 | * sama5d3dm.dtsi - Device Tree file for SAMA5 display module | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | |||
| 10 | / { | ||
| 11 | ahb { | ||
| 12 | apb { | ||
| 13 | i2c1: i2c@f0018000 { | ||
| 14 | qt1070: keyboard@1b { | ||
| 15 | compatible = "qt1070"; | ||
| 16 | reg = <0x1b>; | ||
| 17 | interrupt-parent = <&pioE>; | ||
| 18 | interrupts = <31 0x0>; | ||
| 19 | pinctrl-names = "default"; | ||
| 20 | pinctrl-0 = <&pinctrl_qt1070_irq>; | ||
| 21 | }; | ||
| 22 | }; | ||
| 23 | |||
| 24 | adc0: adc@f8018000 { | ||
| 25 | status = "disabled"; | ||
| 26 | }; | ||
| 27 | |||
| 28 | tsadcc: tsadcc@f8018000 { | ||
| 29 | status = "okay"; | ||
| 30 | }; | ||
| 31 | |||
| 32 | pinctrl@fffff200 { | ||
| 33 | board { | ||
| 34 | pinctrl_qt1070_irq: qt1070_irq { | ||
| 35 | atmel,pins = | ||
| 36 | <4 31 0x0 0x5>; /* PE31 GPIO with pull up deglith */ | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi new file mode 100644 index 000000000000..661d7ca9c309 --- /dev/null +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi | |||
| @@ -0,0 +1,166 @@ | |||
| 1 | /* | ||
| 2 | * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | /include/ "sama5d3xcm.dtsi" | ||
| 10 | |||
| 11 | / { | ||
| 12 | compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; | ||
| 13 | |||
| 14 | ahb { | ||
| 15 | apb { | ||
| 16 | mmc0: mmc@f0000000 { | ||
| 17 | pinctrl-names = "default"; | ||
| 18 | pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; | ||
| 19 | status = "okay"; | ||
| 20 | slot@0 { | ||
| 21 | reg = <0>; | ||
| 22 | bus-width = <4>; | ||
| 23 | cd-gpios = <&pioD 17 0>; | ||
| 24 | }; | ||
| 25 | }; | ||
| 26 | |||
| 27 | spi0: spi@f0004000 { | ||
| 28 | m25p80@0 { | ||
| 29 | compatible = "atmel,at25df321a"; | ||
| 30 | spi-max-frequency = <50000000>; | ||
| 31 | reg = <0>; | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | |||
| 35 | /* | ||
| 36 | * i2c0 conflicts with ISI: | ||
| 37 | * disable it to allow the use of ISI | ||
| 38 | * can not enable audio when i2c0 disabled | ||
| 39 | */ | ||
| 40 | i2c0: i2c@f0014000 { | ||
| 41 | wm8904: wm8904@1a { | ||
| 42 | compatible = "wm8904"; | ||
| 43 | reg = <0x1a>; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | |||
| 47 | usart1: serial@f0020000 { | ||
| 48 | pinctrl-names = "default"; | ||
| 49 | pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; | ||
| 50 | status = "okay"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | isi: isi@f0034000 { | ||
| 54 | pinctrl-names = "default"; | ||
| 55 | pinctrl-0 = <&pinctrl_isi &pinctrl_isi_pck_as_mck &pinctrl_isi_power &pinctrl_isi_reset>; | ||
| 56 | }; | ||
| 57 | |||
| 58 | mmc1: mmc@f8000000 { | ||
| 59 | pinctrl-names = "default"; | ||
| 60 | pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; | ||
| 61 | status = "okay"; | ||
| 62 | slot@0 { | ||
| 63 | reg = <0>; | ||
| 64 | bus-width = <4>; | ||
| 65 | cd-gpios = <&pioD 18 0>; | ||
| 66 | }; | ||
| 67 | }; | ||
| 68 | |||
| 69 | adc0: adc@f8018000 { | ||
| 70 | pinctrl-names = "default"; | ||
| 71 | pinctrl-0 = < | ||
| 72 | &pinctrl_adc0_adtrg | ||
| 73 | &pinctrl_adc0_ad0 | ||
| 74 | &pinctrl_adc0_ad1 | ||
| 75 | &pinctrl_adc0_ad2 | ||
| 76 | &pinctrl_adc0_ad3 | ||
| 77 | &pinctrl_adc0_ad4 | ||
| 78 | >; | ||
| 79 | status = "okay"; | ||
| 80 | }; | ||
| 81 | |||
| 82 | macb1: ethernet@f802c000 { | ||
| 83 | phy-mode = "rmii"; | ||
| 84 | }; | ||
| 85 | |||
| 86 | pinctrl@fffff200 { | ||
| 87 | board { | ||
| 88 | pinctrl_mmc0_cd: mmc0_cd { | ||
| 89 | atmel,pins = | ||
| 90 | <3 17 0x0 0x5>; /* PD17 GPIO with pullup deglitch */ | ||
| 91 | }; | ||
| 92 | |||
| 93 | pinctrl_mmc1_cd: mmc1_cd { | ||
| 94 | atmel,pins = | ||
| 95 | <3 18 0x0 0x5>; /* PD18 GPIO with pullup deglitch */ | ||
| 96 | }; | ||
| 97 | |||
| 98 | pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { | ||
| 99 | atmel,pins = | ||
| 100 | <3 30 0x2 0x0>; /* PD30 periph B */ | ||
| 101 | }; | ||
| 102 | |||
| 103 | pinctrl_isi_reset: isi_reset-0 { | ||
| 104 | atmel,pins = | ||
| 105 | <4 24 0x0 0x0>; /* PE24 gpio */ | ||
| 106 | }; | ||
| 107 | |||
| 108 | pinctrl_isi_power: isi_power-0 { | ||
| 109 | atmel,pins = | ||
| 110 | <4 29 0x0 0x0>; /* PE29 gpio */ | ||
| 111 | }; | ||
| 112 | |||
| 113 | pinctrl_usba_vbus: usba_vbus { | ||
| 114 | atmel,pins = | ||
| 115 | <3 29 0x0 0x4>; /* PD29 GPIO with deglitch */ | ||
| 116 | }; | ||
| 117 | }; | ||
| 118 | }; | ||
| 119 | |||
| 120 | dbgu: serial@ffffee00 { | ||
| 121 | status = "okay"; | ||
| 122 | }; | ||
| 123 | |||
| 124 | watchdog@fffffe40 { | ||
| 125 | status = "okay"; | ||
| 126 | }; | ||
| 127 | }; | ||
| 128 | |||
| 129 | usb0: gadget@00500000 { | ||
| 130 | atmel,vbus-gpio = <&pioD 29 0>; | ||
| 131 | pinctrl-names = "default"; | ||
| 132 | pinctrl-0 = <&pinctrl_usba_vbus>; | ||
| 133 | status = "okay"; | ||
| 134 | }; | ||
| 135 | |||
| 136 | usb1: ohci@00600000 { | ||
| 137 | num-ports = <3>; | ||
| 138 | atmel,vbus-gpio = <&pioD 25 0 | ||
| 139 | &pioD 26 1 | ||
| 140 | &pioD 27 1 | ||
| 141 | >; | ||
| 142 | status = "okay"; | ||
| 143 | }; | ||
| 144 | |||
| 145 | usb2: ehci@00700000 { | ||
| 146 | status = "okay"; | ||
| 147 | }; | ||
| 148 | }; | ||
| 149 | |||
| 150 | sound { | ||
| 151 | compatible = "atmel,sama5d3ek-wm8904"; | ||
| 152 | pinctrl-names = "default"; | ||
| 153 | pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; | ||
| 154 | |||
| 155 | atmel,model = "wm8904 @ SAMA5D3EK"; | ||
| 156 | atmel,audio-routing = | ||
| 157 | "Headphone Jack", "HPOUTL", | ||
| 158 | "Headphone Jack", "HPOUTR", | ||
| 159 | "IN2L", "Line In Jack", | ||
| 160 | "IN2R", "Line In Jack", | ||
| 161 | "IN1L", "Mic"; | ||
| 162 | |||
| 163 | atmel,ssc-controller = <&ssc0>; | ||
| 164 | atmel,audio-codec = <&wm8904>; | ||
| 165 | }; | ||
| 166 | }; | ||
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 7e8769bd5977..16a6e13e08b4 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi | |||
| @@ -81,6 +81,163 @@ | |||
| 81 | }; | 81 | }; |
| 82 | }; | 82 | }; |
| 83 | 83 | ||
| 84 | clkmgr@ffd04000 { | ||
| 85 | compatible = "altr,clk-mgr"; | ||
| 86 | reg = <0xffd04000 0x1000>; | ||
| 87 | |||
| 88 | clocks { | ||
| 89 | #address-cells = <1>; | ||
| 90 | #size-cells = <0>; | ||
| 91 | |||
| 92 | osc: osc1 { | ||
| 93 | #clock-cells = <0>; | ||
| 94 | compatible = "fixed-clock"; | ||
| 95 | }; | ||
| 96 | |||
| 97 | main_pll: main_pll { | ||
| 98 | #address-cells = <1>; | ||
| 99 | #size-cells = <0>; | ||
| 100 | #clock-cells = <0>; | ||
| 101 | compatible = "altr,socfpga-pll-clock"; | ||
| 102 | clocks = <&osc>; | ||
| 103 | reg = <0x40>; | ||
| 104 | |||
| 105 | mpuclk: mpuclk { | ||
| 106 | #clock-cells = <0>; | ||
| 107 | compatible = "altr,socfpga-perip-clk"; | ||
| 108 | clocks = <&main_pll>; | ||
| 109 | fixed-divider = <2>; | ||
| 110 | reg = <0x48>; | ||
| 111 | }; | ||
| 112 | |||
| 113 | mainclk: mainclk { | ||
| 114 | #clock-cells = <0>; | ||
| 115 | compatible = "altr,socfpga-perip-clk"; | ||
| 116 | clocks = <&main_pll>; | ||
| 117 | fixed-divider = <4>; | ||
| 118 | reg = <0x4C>; | ||
| 119 | }; | ||
| 120 | |||
| 121 | dbg_base_clk: dbg_base_clk { | ||
| 122 | #clock-cells = <0>; | ||
| 123 | compatible = "altr,socfpga-perip-clk"; | ||
| 124 | clocks = <&main_pll>; | ||
| 125 | fixed-divider = <4>; | ||
| 126 | reg = <0x50>; | ||
| 127 | }; | ||
| 128 | |||
| 129 | main_qspi_clk: main_qspi_clk { | ||
| 130 | #clock-cells = <0>; | ||
| 131 | compatible = "altr,socfpga-perip-clk"; | ||
| 132 | clocks = <&main_pll>; | ||
| 133 | reg = <0x54>; | ||
| 134 | }; | ||
| 135 | |||
| 136 | main_nand_sdmmc_clk: main_nand_sdmmc_clk { | ||
| 137 | #clock-cells = <0>; | ||
| 138 | compatible = "altr,socfpga-perip-clk"; | ||
| 139 | clocks = <&main_pll>; | ||
| 140 | reg = <0x58>; | ||
| 141 | }; | ||
| 142 | |||
| 143 | cfg_s2f_usr0_clk: cfg_s2f_usr0_clk { | ||
| 144 | #clock-cells = <0>; | ||
| 145 | compatible = "altr,socfpga-perip-clk"; | ||
| 146 | clocks = <&main_pll>; | ||
| 147 | reg = <0x5C>; | ||
| 148 | }; | ||
| 149 | }; | ||
| 150 | |||
| 151 | periph_pll: periph_pll { | ||
| 152 | #address-cells = <1>; | ||
| 153 | #size-cells = <0>; | ||
| 154 | #clock-cells = <0>; | ||
| 155 | compatible = "altr,socfpga-pll-clock"; | ||
| 156 | clocks = <&osc>; | ||
| 157 | reg = <0x80>; | ||
| 158 | |||
| 159 | emac0_clk: emac0_clk { | ||
| 160 | #clock-cells = <0>; | ||
| 161 | compatible = "altr,socfpga-perip-clk"; | ||
| 162 | clocks = <&periph_pll>; | ||
| 163 | reg = <0x88>; | ||
| 164 | }; | ||
| 165 | |||
| 166 | emac1_clk: emac1_clk { | ||
| 167 | #clock-cells = <0>; | ||
| 168 | compatible = "altr,socfpga-perip-clk"; | ||
| 169 | clocks = <&periph_pll>; | ||
| 170 | reg = <0x8C>; | ||
| 171 | }; | ||
| 172 | |||
| 173 | per_qspi_clk: per_qsi_clk { | ||
| 174 | #clock-cells = <0>; | ||
| 175 | compatible = "altr,socfpga-perip-clk"; | ||
| 176 | clocks = <&periph_pll>; | ||
| 177 | reg = <0x90>; | ||
| 178 | }; | ||
| 179 | |||
| 180 | per_nand_mmc_clk: per_nand_mmc_clk { | ||
| 181 | #clock-cells = <0>; | ||
| 182 | compatible = "altr,socfpga-perip-clk"; | ||
| 183 | clocks = <&periph_pll>; | ||
| 184 | reg = <0x94>; | ||
| 185 | }; | ||
| 186 | |||
| 187 | per_base_clk: per_base_clk { | ||
| 188 | #clock-cells = <0>; | ||
| 189 | compatible = "altr,socfpga-perip-clk"; | ||
| 190 | clocks = <&periph_pll>; | ||
| 191 | reg = <0x98>; | ||
| 192 | }; | ||
| 193 | |||
| 194 | s2f_usr1_clk: s2f_usr1_clk { | ||
| 195 | #clock-cells = <0>; | ||
| 196 | compatible = "altr,socfpga-perip-clk"; | ||
| 197 | clocks = <&periph_pll>; | ||
| 198 | reg = <0x9C>; | ||
| 199 | }; | ||
| 200 | }; | ||
| 201 | |||
| 202 | sdram_pll: sdram_pll { | ||
| 203 | #address-cells = <1>; | ||
| 204 | #size-cells = <0>; | ||
| 205 | #clock-cells = <0>; | ||
| 206 | compatible = "altr,socfpga-pll-clock"; | ||
| 207 | clocks = <&osc>; | ||
| 208 | reg = <0xC0>; | ||
| 209 | |||
| 210 | ddr_dqs_clk: ddr_dqs_clk { | ||
| 211 | #clock-cells = <0>; | ||
| 212 | compatible = "altr,socfpga-perip-clk"; | ||
| 213 | clocks = <&sdram_pll>; | ||
| 214 | reg = <0xC8>; | ||
| 215 | }; | ||
| 216 | |||
| 217 | ddr_2x_dqs_clk: ddr_2x_dqs_clk { | ||
| 218 | #clock-cells = <0>; | ||
| 219 | compatible = "altr,socfpga-perip-clk"; | ||
| 220 | clocks = <&sdram_pll>; | ||
| 221 | reg = <0xCC>; | ||
| 222 | }; | ||
| 223 | |||
| 224 | ddr_dq_clk: ddr_dq_clk { | ||
| 225 | #clock-cells = <0>; | ||
| 226 | compatible = "altr,socfpga-perip-clk"; | ||
| 227 | clocks = <&sdram_pll>; | ||
| 228 | reg = <0xD0>; | ||
| 229 | }; | ||
| 230 | |||
| 231 | s2f_usr2_clk: s2f_usr2_clk { | ||
| 232 | #clock-cells = <0>; | ||
| 233 | compatible = "altr,socfpga-perip-clk"; | ||
| 234 | clocks = <&sdram_pll>; | ||
| 235 | reg = <0xD4>; | ||
| 236 | }; | ||
| 237 | }; | ||
| 238 | }; | ||
| 239 | }; | ||
| 240 | |||
| 84 | gmac0: stmmac@ff700000 { | 241 | gmac0: stmmac@ff700000 { |
| 85 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; | 242 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; |
| 86 | reg = <0xff700000 0x2000>; | 243 | reg = <0xff700000 0x2000>; |
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts index 3ae8a83a0875..2495958f1016 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts | |||
| @@ -33,6 +33,14 @@ | |||
| 33 | }; | 33 | }; |
| 34 | 34 | ||
| 35 | soc { | 35 | soc { |
| 36 | clkmgr@ffd04000 { | ||
| 37 | clocks { | ||
| 38 | osc1 { | ||
| 39 | clock-frequency = <25000000>; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | |||
| 36 | timer0@ffc08000 { | 44 | timer0@ffc08000 { |
| 37 | clock-frequency = <100000000>; | 45 | clock-frequency = <100000000>; |
| 38 | }; | 46 | }; |
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index 1036eba40bbf..0bf035d607f0 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts | |||
| @@ -33,6 +33,14 @@ | |||
| 33 | }; | 33 | }; |
| 34 | 34 | ||
| 35 | soc { | 35 | soc { |
| 36 | clkmgr@ffd04000 { | ||
| 37 | clocks { | ||
| 38 | osc1 { | ||
| 39 | clock-frequency = <10000000>; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | |||
| 36 | timer0@ffc08000 { | 44 | timer0@ffc08000 { |
| 37 | clock-frequency = <7000000>; | 45 | clock-frequency = <7000000>; |
| 38 | }; | 46 | }; |
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index a30aca62658a..6ebc1b704190 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts | |||
| @@ -18,4 +18,17 @@ | |||
| 18 | pmc { | 18 | pmc { |
| 19 | nvidia,invert-interrupt; | 19 | nvidia,invert-interrupt; |
| 20 | }; | 20 | }; |
| 21 | |||
| 22 | clocks { | ||
| 23 | compatible = "simple-bus"; | ||
| 24 | #address-cells = <1>; | ||
| 25 | #size-cells = <0>; | ||
| 26 | |||
| 27 | clk32k_in: clock { | ||
| 28 | compatible = "fixed-clock"; | ||
| 29 | reg=<0>; | ||
| 30 | #clock-cells = <0>; | ||
| 31 | clock-frequency = <32768>; | ||
| 32 | }; | ||
| 33 | }; | ||
| 21 | }; | 34 | }; |
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts index 9bea8f57aa47..5deb8692b350 100644 --- a/arch/arm/boot/dts/tegra114-pluto.dts +++ b/arch/arm/boot/dts/tegra114-pluto.dts | |||
| @@ -18,4 +18,17 @@ | |||
| 18 | pmc { | 18 | pmc { |
| 19 | nvidia,invert-interrupt; | 19 | nvidia,invert-interrupt; |
| 20 | }; | 20 | }; |
| 21 | |||
| 22 | clocks { | ||
| 23 | compatible = "simple-bus"; | ||
| 24 | #address-cells = <1>; | ||
| 25 | #size-cells = <0>; | ||
| 26 | |||
| 27 | clk32k_in: clock { | ||
| 28 | compatible = "fixed-clock"; | ||
| 29 | reg=<0>; | ||
| 30 | #clock-cells = <0>; | ||
| 31 | clock-frequency = <32768>; | ||
| 32 | }; | ||
| 33 | }; | ||
| 21 | }; | 34 | }; |
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index e4ddeddcd437..c0b527d15fda 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi | |||
| @@ -101,6 +101,8 @@ | |||
| 101 | pmc { | 101 | pmc { |
| 102 | compatible = "nvidia,tegra114-pmc"; | 102 | compatible = "nvidia,tegra114-pmc"; |
| 103 | reg = <0x7000e400 0x400>; | 103 | reg = <0x7000e400 0x400>; |
| 104 | clocks = <&tegra_car 261>, <&clk32k_in>; | ||
| 105 | clock-names = "pclk", "clk32k_in"; | ||
| 104 | }; | 106 | }; |
| 105 | 107 | ||
| 106 | iommu { | 108 | iommu { |
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi index cb73e62d61a9..4e3afdef28a8 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi | |||
| @@ -447,6 +447,19 @@ | |||
| 447 | cd-gpios = <&gpio 23 1>; /* gpio PC7 */ | 447 | cd-gpios = <&gpio 23 1>; /* gpio PC7 */ |
| 448 | }; | 448 | }; |
| 449 | 449 | ||
| 450 | clocks { | ||
| 451 | compatible = "simple-bus"; | ||
| 452 | #address-cells = <1>; | ||
| 453 | #size-cells = <0>; | ||
| 454 | |||
| 455 | clk32k_in: clock { | ||
| 456 | compatible = "fixed-clock"; | ||
| 457 | reg=<0>; | ||
| 458 | #clock-cells = <0>; | ||
| 459 | clock-frequency = <32768>; | ||
| 460 | }; | ||
| 461 | }; | ||
| 462 | |||
| 450 | sound { | 463 | sound { |
| 451 | compatible = "nvidia,tegra-audio-wm9712-colibri_t20", | 464 | compatible = "nvidia,tegra-audio-wm9712-colibri_t20", |
| 452 | "nvidia,tegra-audio-wm9712"; | 465 | "nvidia,tegra-audio-wm9712"; |
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 1f79c0debb05..ae9d5a20834e 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts | |||
| @@ -451,6 +451,19 @@ | |||
| 451 | bus-width = <8>; | 451 | bus-width = <8>; |
| 452 | }; | 452 | }; |
| 453 | 453 | ||
| 454 | clocks { | ||
| 455 | compatible = "simple-bus"; | ||
| 456 | #address-cells = <1>; | ||
| 457 | #size-cells = <0>; | ||
| 458 | |||
| 459 | clk32k_in: clock { | ||
| 460 | compatible = "fixed-clock"; | ||
| 461 | reg=<0>; | ||
| 462 | #clock-cells = <0>; | ||
| 463 | clock-frequency = <32768>; | ||
| 464 | }; | ||
| 465 | }; | ||
| 466 | |||
| 454 | kbc { | 467 | kbc { |
| 455 | status = "okay"; | 468 | status = "okay"; |
| 456 | nvidia,debounce-delay-ms = <2>; | 469 | nvidia,debounce-delay-ms = <2>; |
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 9db36da8e023..fd60940e4063 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts | |||
| @@ -447,6 +447,19 @@ | |||
| 447 | bus-width = <8>; | 447 | bus-width = <8>; |
| 448 | }; | 448 | }; |
| 449 | 449 | ||
| 450 | clocks { | ||
| 451 | compatible = "simple-bus"; | ||
| 452 | #address-cells = <1>; | ||
| 453 | #size-cells = <0>; | ||
| 454 | |||
| 455 | clk32k_in: clock { | ||
| 456 | compatible = "fixed-clock"; | ||
| 457 | reg=<0>; | ||
| 458 | #clock-cells = <0>; | ||
| 459 | clock-frequency = <32768>; | ||
| 460 | }; | ||
| 461 | }; | ||
| 462 | |||
| 450 | gpio-keys { | 463 | gpio-keys { |
| 451 | compatible = "gpio-keys"; | 464 | compatible = "gpio-keys"; |
| 452 | 465 | ||
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 715a8b8dd9cd..4ee700a33ca5 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts | |||
| @@ -595,6 +595,19 @@ | |||
| 595 | bus-width = <8>; | 595 | bus-width = <8>; |
| 596 | }; | 596 | }; |
| 597 | 597 | ||
| 598 | clocks { | ||
| 599 | compatible = "simple-bus"; | ||
| 600 | #address-cells = <1>; | ||
| 601 | #size-cells = <0>; | ||
| 602 | |||
| 603 | clk32k_in: clock { | ||
| 604 | compatible = "fixed-clock"; | ||
| 605 | reg=<0>; | ||
| 606 | #clock-cells = <0>; | ||
| 607 | clock-frequency = <32768>; | ||
| 608 | }; | ||
| 609 | }; | ||
| 610 | |||
| 598 | gpio-keys { | 611 | gpio-keys { |
| 599 | compatible = "gpio-keys"; | 612 | compatible = "gpio-keys"; |
| 600 | 613 | ||
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 6e9d91fc6195..c19025725918 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi | |||
| @@ -471,6 +471,19 @@ | |||
| 471 | status = "okay"; | 471 | status = "okay"; |
| 472 | }; | 472 | }; |
| 473 | 473 | ||
| 474 | clocks { | ||
| 475 | compatible = "simple-bus"; | ||
| 476 | #address-cells = <1>; | ||
| 477 | #size-cells = <0>; | ||
| 478 | |||
| 479 | clk32k_in: clock { | ||
| 480 | compatible = "fixed-clock"; | ||
| 481 | reg=<0>; | ||
| 482 | #clock-cells = <0>; | ||
| 483 | clock-frequency = <32768>; | ||
| 484 | }; | ||
| 485 | }; | ||
| 486 | |||
| 474 | regulators { | 487 | regulators { |
| 475 | compatible = "simple-bus"; | 488 | compatible = "simple-bus"; |
| 476 | 489 | ||
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 98f3e44f2a51..a9f3f06580f5 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts | |||
| @@ -330,6 +330,19 @@ | |||
| 330 | bus-width = <4>; | 330 | bus-width = <4>; |
| 331 | }; | 331 | }; |
| 332 | 332 | ||
| 333 | clocks { | ||
| 334 | compatible = "simple-bus"; | ||
| 335 | #address-cells = <1>; | ||
| 336 | #size-cells = <0>; | ||
| 337 | |||
| 338 | clk32k_in: clock { | ||
| 339 | compatible = "fixed-clock"; | ||
| 340 | reg=<0>; | ||
| 341 | #clock-cells = <0>; | ||
| 342 | clock-frequency = <32768>; | ||
| 343 | }; | ||
| 344 | }; | ||
| 345 | |||
| 333 | poweroff { | 346 | poweroff { |
| 334 | compatible = "gpio-poweroff"; | 347 | compatible = "gpio-poweroff"; |
| 335 | gpios = <&gpio 191 1>; /* gpio PX7, active low */ | 348 | gpios = <&gpio 191 1>; /* gpio PX7, active low */ |
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 4aef56f2d96a..f544806e9618 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts | |||
| @@ -531,6 +531,19 @@ | |||
| 531 | bus-width = <8>; | 531 | bus-width = <8>; |
| 532 | }; | 532 | }; |
| 533 | 533 | ||
| 534 | clocks { | ||
| 535 | compatible = "simple-bus"; | ||
| 536 | #address-cells = <1>; | ||
| 537 | #size-cells = <0>; | ||
| 538 | |||
| 539 | clk32k_in: clock { | ||
| 540 | compatible = "fixed-clock"; | ||
| 541 | reg=<0>; | ||
| 542 | #clock-cells = <0>; | ||
| 543 | clock-frequency = <32768>; | ||
| 544 | }; | ||
| 545 | }; | ||
| 546 | |||
| 534 | regulators { | 547 | regulators { |
| 535 | compatible = "simple-bus"; | 548 | compatible = "simple-bus"; |
| 536 | #address-cells = <1>; | 549 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index 5762188c60ad..258cf945f515 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts | |||
| @@ -520,6 +520,19 @@ | |||
| 520 | bus-width = <8>; | 520 | bus-width = <8>; |
| 521 | }; | 521 | }; |
| 522 | 522 | ||
| 523 | clocks { | ||
| 524 | compatible = "simple-bus"; | ||
| 525 | #address-cells = <1>; | ||
| 526 | #size-cells = <0>; | ||
| 527 | |||
| 528 | clk32k_in: clock { | ||
| 529 | compatible = "fixed-clock"; | ||
| 530 | reg=<0>; | ||
| 531 | #clock-cells = <0>; | ||
| 532 | clock-frequency = <32768>; | ||
| 533 | }; | ||
| 534 | }; | ||
| 535 | |||
| 523 | kbc { | 536 | kbc { |
| 524 | status = "okay"; | 537 | status = "okay"; |
| 525 | nvidia,debounce-delay-ms = <20>; | 538 | nvidia,debounce-delay-ms = <20>; |
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index ad64c8cc9da7..fc7febc2b386 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi | |||
| @@ -418,6 +418,8 @@ | |||
| 418 | pmc { | 418 | pmc { |
| 419 | compatible = "nvidia,tegra20-pmc"; | 419 | compatible = "nvidia,tegra20-pmc"; |
| 420 | reg = <0x7000e400 0x400>; | 420 | reg = <0x7000e400 0x400>; |
| 421 | clocks = <&tegra_car 110>, <&clk32k_in>; | ||
| 422 | clock-names = "pclk", "clk32k_in"; | ||
| 421 | }; | 423 | }; |
| 422 | 424 | ||
| 423 | memory-controller@7000f000 { | 425 | memory-controller@7000f000 { |
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 0a2cd24df853..6248b2445b32 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts | |||
| @@ -268,6 +268,19 @@ | |||
| 268 | bus-width = <8>; | 268 | bus-width = <8>; |
| 269 | }; | 269 | }; |
| 270 | 270 | ||
| 271 | clocks { | ||
| 272 | compatible = "simple-bus"; | ||
| 273 | #address-cells = <1>; | ||
| 274 | #size-cells = <0>; | ||
| 275 | |||
| 276 | clk32k_in: clock { | ||
| 277 | compatible = "fixed-clock"; | ||
| 278 | reg=<0>; | ||
| 279 | #clock-cells = <0>; | ||
| 280 | clock-frequency = <32768>; | ||
| 281 | }; | ||
| 282 | }; | ||
| 283 | |||
| 271 | regulators { | 284 | regulators { |
| 272 | compatible = "simple-bus"; | 285 | compatible = "simple-bus"; |
| 273 | #address-cells = <1>; | 286 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 3e2d21018a5b..65bf2b63174e 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi | |||
| @@ -322,6 +322,19 @@ | |||
| 322 | bus-width = <8>; | 322 | bus-width = <8>; |
| 323 | }; | 323 | }; |
| 324 | 324 | ||
| 325 | clocks { | ||
| 326 | compatible = "simple-bus"; | ||
| 327 | #address-cells = <1>; | ||
| 328 | #size-cells = <0>; | ||
| 329 | |||
| 330 | clk32k_in: clock { | ||
| 331 | compatible = "fixed-clock"; | ||
| 332 | reg=<0>; | ||
| 333 | #clock-cells = <0>; | ||
| 334 | clock-frequency = <32768>; | ||
| 335 | }; | ||
| 336 | }; | ||
| 337 | |||
| 325 | regulators { | 338 | regulators { |
| 326 | compatible = "simple-bus"; | 339 | compatible = "simple-bus"; |
| 327 | #address-cells = <1>; | 340 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 9491edf1a067..9fe7a92b4c85 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi | |||
| @@ -427,6 +427,8 @@ | |||
| 427 | pmc { | 427 | pmc { |
| 428 | compatible = "nvidia,tegra30-pmc"; | 428 | compatible = "nvidia,tegra30-pmc"; |
| 429 | reg = <0x7000e400 0x400>; | 429 | reg = <0x7000e400 0x400>; |
| 430 | clocks = <&tegra_car 218>, <&clk32k_in>; | ||
| 431 | clock-names = "pclk", "clk32k_in"; | ||
| 430 | }; | 432 | }; |
| 431 | 433 | ||
| 432 | memory-controller { | 434 | memory-controller { |
diff --git a/arch/arm/boot/dts/tps6507x.dtsi b/arch/arm/boot/dts/tps6507x.dtsi new file mode 100644 index 000000000000..4c326e591e5a --- /dev/null +++ b/arch/arm/boot/dts/tps6507x.dtsi | |||
| @@ -0,0 +1,47 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* | ||
| 10 | * Integrated Power Management Chip | ||
| 11 | * http://www.ti.com/lit/ds/symlink/tps65070.pdf | ||
| 12 | */ | ||
| 13 | |||
| 14 | &tps { | ||
| 15 | compatible = "ti,tps6507x"; | ||
| 16 | |||
| 17 | regulators { | ||
| 18 | #address-cells = <1>; | ||
| 19 | #size-cells = <0>; | ||
| 20 | |||
| 21 | vdcdc1_reg: regulator@0 { | ||
| 22 | reg = <0>; | ||
| 23 | regulator-compatible = "VDCDC1"; | ||
| 24 | }; | ||
| 25 | |||
| 26 | vdcdc2_reg: regulator@1 { | ||
| 27 | reg = <1>; | ||
| 28 | regulator-compatible = "VDCDC2"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | vdcdc3_reg: regulator@2 { | ||
| 32 | reg = <2>; | ||
| 33 | regulator-compatible = "VDCDC3"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | ldo1_reg: regulator@3 { | ||
| 37 | reg = <3>; | ||
| 38 | regulator-compatible = "LDO1"; | ||
| 39 | }; | ||
| 40 | |||
| 41 | ldo2_reg: regulator@4 { | ||
| 42 | reg = <4>; | ||
| 43 | regulator-compatible = "LDO2"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | }; | ||
| 47 | }; | ||
diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig new file mode 100644 index 000000000000..dab5a7dfadc6 --- /dev/null +++ b/arch/arm/configs/ape6evm_defconfig | |||
| @@ -0,0 +1,95 @@ | |||
| 1 | CONFIG_SYSVIPC=y | ||
| 2 | CONFIG_POSIX_MQUEUE=y | ||
| 3 | CONFIG_NO_HZ=y | ||
| 4 | CONFIG_HIGH_RES_TIMERS=y | ||
| 5 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 6 | CONFIG_IKCONFIG=y | ||
| 7 | CONFIG_IKCONFIG_PROC=y | ||
| 8 | CONFIG_LOG_BUF_SHIFT=16 | ||
| 9 | CONFIG_CGROUPS=y | ||
| 10 | CONFIG_CGROUP_SCHED=y | ||
| 11 | CONFIG_KALLSYMS_ALL=y | ||
| 12 | CONFIG_EMBEDDED=y | ||
| 13 | CONFIG_PERF_EVENTS=y | ||
| 14 | CONFIG_SLAB=y | ||
| 15 | # CONFIG_BLOCK is not set | ||
| 16 | CONFIG_ARCH_SHMOBILE=y | ||
| 17 | CONFIG_ARCH_R8A73A4=y | ||
| 18 | CONFIG_MACH_APE6EVM=y | ||
| 19 | # CONFIG_ARM_THUMB is not set | ||
| 20 | CONFIG_CPU_BPREDICT_DISABLE=y | ||
| 21 | CONFIG_PL310_ERRATA_588369=y | ||
| 22 | CONFIG_ARM_ERRATA_754322=y | ||
| 23 | CONFIG_SMP=y | ||
| 24 | CONFIG_SCHED_MC=y | ||
| 25 | CONFIG_HAVE_ARM_ARCH_TIMER=y | ||
| 26 | CONFIG_NR_CPUS=8 | ||
| 27 | CONFIG_AEABI=y | ||
| 28 | CONFIG_HIGHMEM=y | ||
| 29 | CONFIG_HIGHPTE=y | ||
| 30 | # CONFIG_HW_PERF_EVENTS is not set | ||
| 31 | # CONFIG_COMPACTION is not set | ||
| 32 | # CONFIG_CROSS_MEMORY_ATTACH is not set | ||
| 33 | CONFIG_ARM_APPENDED_DTB=y | ||
| 34 | CONFIG_VFP=y | ||
| 35 | CONFIG_NEON=y | ||
| 36 | CONFIG_BINFMT_MISC=y | ||
| 37 | CONFIG_NET=y | ||
| 38 | CONFIG_PACKET=y | ||
| 39 | CONFIG_UNIX=y | ||
| 40 | CONFIG_XFRM_USER=y | ||
| 41 | CONFIG_NET_KEY=y | ||
| 42 | CONFIG_NET_KEY_MIGRATE=y | ||
| 43 | CONFIG_INET=y | ||
| 44 | CONFIG_IP_MULTICAST=y | ||
| 45 | CONFIG_IP_PNP=y | ||
| 46 | CONFIG_IP_PNP_DHCP=y | ||
| 47 | # CONFIG_INET_LRO is not set | ||
| 48 | # CONFIG_IPV6_SIT is not set | ||
| 49 | CONFIG_NETFILTER=y | ||
| 50 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 51 | # CONFIG_FW_LOADER_USER_HELPER is not set | ||
| 52 | CONFIG_NETDEVICES=y | ||
| 53 | # CONFIG_NET_CADENCE is not set | ||
| 54 | CONFIG_SMC91X=y | ||
| 55 | CONFIG_SMSC911X=y | ||
| 56 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 57 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 58 | # CONFIG_INPUT_MOUSE is not set | ||
| 59 | # CONFIG_SERIO is not set | ||
| 60 | CONFIG_SERIAL_NONSTANDARD=y | ||
| 61 | CONFIG_SERIAL_SH_SCI=y | ||
| 62 | CONFIG_SERIAL_SH_SCI_NR_UARTS=12 | ||
| 63 | CONFIG_SERIAL_SH_SCI_CONSOLE=y | ||
| 64 | CONFIG_GPIO_SH_PFC=y | ||
| 65 | CONFIG_GPIOLIB=y | ||
| 66 | # CONFIG_HWMON is not set | ||
| 67 | CONFIG_THERMAL=y | ||
| 68 | CONFIG_RCAR_THERMAL=y | ||
| 69 | CONFIG_REGULATOR=y | ||
| 70 | CONFIG_REGULATOR_FIXED_VOLTAGE=y | ||
| 71 | CONFIG_REGULATOR_GPIO=y | ||
| 72 | # CONFIG_HID is not set | ||
| 73 | # CONFIG_USB_SUPPORT is not set | ||
| 74 | # CONFIG_IOMMU_SUPPORT is not set | ||
| 75 | # CONFIG_DNOTIFY is not set | ||
| 76 | CONFIG_TMPFS=y | ||
| 77 | # CONFIG_MISC_FILESYSTEMS is not set | ||
| 78 | CONFIG_NFS_FS=y | ||
| 79 | CONFIG_NFS_V3_ACL=y | ||
| 80 | CONFIG_NFS_V4=y | ||
| 81 | CONFIG_NFS_V4_1=y | ||
| 82 | CONFIG_ROOT_NFS=y | ||
| 83 | CONFIG_MAGIC_SYSRQ=y | ||
| 84 | CONFIG_ENABLE_DEFAULT_TRACERS=y | ||
| 85 | CONFIG_CRYPTO_CBC=y | ||
| 86 | CONFIG_CRYPTO_ECB=y | ||
| 87 | CONFIG_CRYPTO_MD5=y | ||
| 88 | CONFIG_CRYPTO_MICHAEL_MIC=y | ||
| 89 | CONFIG_CRYPTO_TWOFISH=y | ||
| 90 | CONFIG_CRC_CCITT=y | ||
| 91 | CONFIG_CRC16=y | ||
| 92 | CONFIG_CRC_T10DIF=y | ||
| 93 | CONFIG_CRC_ITU_T=y | ||
| 94 | CONFIG_CRC7=y | ||
| 95 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig index 0b98100d2ae7..0f2d80da7378 100644 --- a/arch/arm/configs/armadillo800eva_defconfig +++ b/arch/arm/configs/armadillo800eva_defconfig | |||
| @@ -20,15 +20,19 @@ CONFIG_ARCH_R8A7740=y | |||
| 20 | CONFIG_MACH_ARMADILLO800EVA=y | 20 | CONFIG_MACH_ARMADILLO800EVA=y |
| 21 | # CONFIG_SH_TIMER_TMU is not set | 21 | # CONFIG_SH_TIMER_TMU is not set |
| 22 | CONFIG_ARM_THUMB=y | 22 | CONFIG_ARM_THUMB=y |
| 23 | CONFIG_CPU_BPREDICT_DISABLE=y | ||
| 24 | CONFIG_CACHE_L2X0=y | 23 | CONFIG_CACHE_L2X0=y |
| 25 | CONFIG_ARM_ERRATA_430973=y | 24 | CONFIG_ARM_ERRATA_430973=y |
| 26 | CONFIG_ARM_ERRATA_458693=y | 25 | CONFIG_ARM_ERRATA_458693=y |
| 27 | CONFIG_ARM_ERRATA_460075=y | 26 | CONFIG_ARM_ERRATA_460075=y |
| 27 | CONFIG_PL310_ERRATA_588369=y | ||
| 28 | CONFIG_ARM_ERRATA_720789=y | 28 | CONFIG_ARM_ERRATA_720789=y |
| 29 | CONFIG_PL310_ERRATA_727915=y | ||
| 29 | CONFIG_ARM_ERRATA_743622=y | 30 | CONFIG_ARM_ERRATA_743622=y |
| 30 | CONFIG_ARM_ERRATA_751472=y | 31 | CONFIG_ARM_ERRATA_751472=y |
| 32 | CONFIG_PL310_ERRATA_753970=y | ||
| 31 | CONFIG_ARM_ERRATA_754322=y | 33 | CONFIG_ARM_ERRATA_754322=y |
| 34 | CONFIG_PL310_ERRATA_769419=y | ||
| 35 | CONFIG_ARM_ERRATA_775420=y | ||
| 32 | CONFIG_AEABI=y | 36 | CONFIG_AEABI=y |
| 33 | # CONFIG_OABI_COMPAT is not set | 37 | # CONFIG_OABI_COMPAT is not set |
| 34 | CONFIG_FORCE_MAX_ZONEORDER=13 | 38 | CONFIG_FORCE_MAX_ZONEORDER=13 |
| @@ -37,6 +41,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0 | |||
| 37 | CONFIG_ARM_APPENDED_DTB=y | 41 | CONFIG_ARM_APPENDED_DTB=y |
| 38 | CONFIG_KEXEC=y | 42 | CONFIG_KEXEC=y |
| 39 | CONFIG_VFP=y | 43 | CONFIG_VFP=y |
| 44 | CONFIG_NEON=y | ||
| 40 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 45 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| 41 | CONFIG_PM_RUNTIME=y | 46 | CONFIG_PM_RUNTIME=y |
| 42 | CONFIG_NET=y | 47 | CONFIG_NET=y |
| @@ -88,6 +93,7 @@ CONFIG_I2C=y | |||
| 88 | CONFIG_I2C_GPIO=y | 93 | CONFIG_I2C_GPIO=y |
| 89 | CONFIG_I2C_SH_MOBILE=y | 94 | CONFIG_I2C_SH_MOBILE=y |
| 90 | # CONFIG_HWMON is not set | 95 | # CONFIG_HWMON is not set |
| 96 | CONFIG_REGULATOR=y | ||
| 91 | CONFIG_MEDIA_SUPPORT=y | 97 | CONFIG_MEDIA_SUPPORT=y |
| 92 | CONFIG_VIDEO_DEV=y | 98 | CONFIG_VIDEO_DEV=y |
| 93 | CONFIG_MEDIA_CAMERA_SUPPORT=y | 99 | CONFIG_MEDIA_CAMERA_SUPPORT=y |
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig index af472e4ed451..abc7c8d4631b 100644 --- a/arch/arm/configs/bcm2835_defconfig +++ b/arch/arm/configs/bcm2835_defconfig | |||
| @@ -59,10 +59,13 @@ CONFIG_DEVTMPFS_MOUNT=y | |||
| 59 | CONFIG_SERIAL_AMBA_PL011=y | 59 | CONFIG_SERIAL_AMBA_PL011=y |
| 60 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y | 60 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y |
| 61 | CONFIG_TTY_PRINTK=y | 61 | CONFIG_TTY_PRINTK=y |
| 62 | # CONFIG_HW_RANDOM is not set | 62 | CONFIG_HW_RANDOM=y |
| 63 | CONFIG_HW_RANDOM_BCM2835=y | ||
| 63 | CONFIG_I2C=y | 64 | CONFIG_I2C=y |
| 64 | CONFIG_I2C_CHARDEV=y | 65 | CONFIG_I2C_CHARDEV=y |
| 65 | CONFIG_I2C_BCM2835=y | 66 | CONFIG_I2C_BCM2835=y |
| 67 | CONFIG_SPI=y | ||
| 68 | CONFIG_SPI_BCM2835=y | ||
| 66 | CONFIG_GPIO_SYSFS=y | 69 | CONFIG_GPIO_SYSFS=y |
| 67 | # CONFIG_HWMON is not set | 70 | # CONFIG_HWMON is not set |
| 68 | # CONFIG_USB_SUPPORT is not set | 71 | # CONFIG_USB_SUPPORT is not set |
| @@ -108,9 +111,5 @@ CONFIG_TEST_KSTRTOX=y | |||
| 108 | CONFIG_STRICT_DEVMEM=y | 111 | CONFIG_STRICT_DEVMEM=y |
| 109 | CONFIG_DEBUG_LL=y | 112 | CONFIG_DEBUG_LL=y |
| 110 | CONFIG_EARLY_PRINTK=y | 113 | CONFIG_EARLY_PRINTK=y |
| 111 | # CONFIG_XZ_DEC_X86 is not set | ||
| 112 | # CONFIG_XZ_DEC_POWERPC is not set | ||
| 113 | # CONFIG_XZ_DEC_IA64 is not set | ||
| 114 | # CONFIG_XZ_DEC_ARM is not set | 114 | # CONFIG_XZ_DEC_ARM is not set |
| 115 | # CONFIG_XZ_DEC_ARMTHUMB is not set | 115 | # CONFIG_XZ_DEC_ARMTHUMB is not set |
| 116 | # CONFIG_XZ_DEC_SPARC is not set | ||
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig index 670c3b60f936..f6e585b353a4 100644 --- a/arch/arm/configs/kzm9g_defconfig +++ b/arch/arm/configs/kzm9g_defconfig | |||
| @@ -33,7 +33,6 @@ CONFIG_NO_HZ=y | |||
| 33 | CONFIG_HIGH_RES_TIMERS=y | 33 | CONFIG_HIGH_RES_TIMERS=y |
| 34 | CONFIG_SMP=y | 34 | CONFIG_SMP=y |
| 35 | CONFIG_SCHED_MC=y | 35 | CONFIG_SCHED_MC=y |
| 36 | CONFIG_PREEMPT=y | ||
| 37 | CONFIG_AEABI=y | 36 | CONFIG_AEABI=y |
| 38 | # CONFIG_OABI_COMPAT is not set | 37 | # CONFIG_OABI_COMPAT is not set |
| 39 | CONFIG_HIGHMEM=y | 38 | CONFIG_HIGHMEM=y |
| @@ -86,7 +85,6 @@ CONFIG_I2C_SH_MOBILE=y | |||
| 86 | CONFIG_GPIO_PCF857X=y | 85 | CONFIG_GPIO_PCF857X=y |
| 87 | # CONFIG_HWMON is not set | 86 | # CONFIG_HWMON is not set |
| 88 | CONFIG_REGULATOR=y | 87 | CONFIG_REGULATOR=y |
| 89 | CONFIG_REGULATOR_DUMMY=y | ||
| 90 | CONFIG_FB=y | 88 | CONFIG_FB=y |
| 91 | CONFIG_FB_SH_MOBILE_LCDC=y | 89 | CONFIG_FB_SH_MOBILE_LCDC=y |
| 92 | CONFIG_FRAMEBUFFER_CONSOLE=y | 90 | CONFIG_FRAMEBUFFER_CONSOLE=y |
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig index afa7249fac6e..398a367ffce8 100644 --- a/arch/arm/configs/lpc32xx_defconfig +++ b/arch/arm/configs/lpc32xx_defconfig | |||
| @@ -1,4 +1,3 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | 1 | CONFIG_SYSVIPC=y |
| 3 | CONFIG_NO_HZ=y | 2 | CONFIG_NO_HZ=y |
| 4 | CONFIG_HIGH_RES_TIMERS=y | 3 | CONFIG_HIGH_RES_TIMERS=y |
| @@ -18,6 +17,7 @@ CONFIG_MODULE_UNLOAD=y | |||
| 18 | # CONFIG_BLK_DEV_BSG is not set | 17 | # CONFIG_BLK_DEV_BSG is not set |
| 19 | CONFIG_PARTITION_ADVANCED=y | 18 | CONFIG_PARTITION_ADVANCED=y |
| 20 | CONFIG_ARCH_LPC32XX=y | 19 | CONFIG_ARCH_LPC32XX=y |
| 20 | CONFIG_GPIO_PCA953X=y | ||
| 21 | CONFIG_KEYBOARD_GPIO_POLLED=y | 21 | CONFIG_KEYBOARD_GPIO_POLLED=y |
| 22 | CONFIG_PREEMPT=y | 22 | CONFIG_PREEMPT=y |
| 23 | CONFIG_AEABI=y | 23 | CONFIG_AEABI=y |
| @@ -48,6 +48,8 @@ CONFIG_IPV6=y | |||
| 48 | CONFIG_IPV6_PRIVACY=y | 48 | CONFIG_IPV6_PRIVACY=y |
| 49 | # CONFIG_WIRELESS is not set | 49 | # CONFIG_WIRELESS is not set |
| 50 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 50 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 51 | CONFIG_DEVTMPFS=y | ||
| 52 | CONFIG_DEVTMPFS_MOUNT=y | ||
| 51 | # CONFIG_FW_LOADER is not set | 53 | # CONFIG_FW_LOADER is not set |
| 52 | CONFIG_MTD=y | 54 | CONFIG_MTD=y |
| 53 | CONFIG_MTD_CMDLINE_PARTS=y | 55 | CONFIG_MTD_CMDLINE_PARTS=y |
| @@ -55,7 +57,6 @@ CONFIG_MTD_CHAR=y | |||
| 55 | CONFIG_MTD_BLOCK=y | 57 | CONFIG_MTD_BLOCK=y |
| 56 | CONFIG_MTD_M25P80=y | 58 | CONFIG_MTD_M25P80=y |
| 57 | CONFIG_MTD_NAND=y | 59 | CONFIG_MTD_NAND=y |
| 58 | CONFIG_MTD_NAND_MUSEUM_IDS=y | ||
| 59 | CONFIG_MTD_NAND_SLC_LPC32XX=y | 60 | CONFIG_MTD_NAND_SLC_LPC32XX=y |
| 60 | CONFIG_MTD_NAND_MLC_LPC32XX=y | 61 | CONFIG_MTD_NAND_MLC_LPC32XX=y |
| 61 | CONFIG_BLK_DEV_LOOP=y | 62 | CONFIG_BLK_DEV_LOOP=y |
| @@ -70,7 +71,6 @@ CONFIG_BLK_DEV_SD=y | |||
| 70 | CONFIG_NETDEVICES=y | 71 | CONFIG_NETDEVICES=y |
| 71 | CONFIG_MII=y | 72 | CONFIG_MII=y |
| 72 | # CONFIG_NET_VENDOR_BROADCOM is not set | 73 | # CONFIG_NET_VENDOR_BROADCOM is not set |
| 73 | # CONFIG_NET_VENDOR_CHELSIO is not set | ||
| 74 | # CONFIG_NET_VENDOR_CIRRUS is not set | 74 | # CONFIG_NET_VENDOR_CIRRUS is not set |
| 75 | # CONFIG_NET_VENDOR_FARADAY is not set | 75 | # CONFIG_NET_VENDOR_FARADAY is not set |
| 76 | # CONFIG_NET_VENDOR_INTEL is not set | 76 | # CONFIG_NET_VENDOR_INTEL is not set |
| @@ -84,7 +84,6 @@ CONFIG_LPC_ENET=y | |||
| 84 | # CONFIG_NET_VENDOR_STMICRO is not set | 84 | # CONFIG_NET_VENDOR_STMICRO is not set |
| 85 | CONFIG_SMSC_PHY=y | 85 | CONFIG_SMSC_PHY=y |
| 86 | # CONFIG_WLAN is not set | 86 | # CONFIG_WLAN is not set |
| 87 | CONFIG_INPUT_MATRIXKMAP=y | ||
| 88 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 87 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
| 89 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=240 | 88 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=240 |
| 90 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320 | 89 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320 |
| @@ -108,6 +107,19 @@ CONFIG_I2C_PNX=y | |||
| 108 | CONFIG_SPI=y | 107 | CONFIG_SPI=y |
| 109 | CONFIG_SPI_PL022=y | 108 | CONFIG_SPI_PL022=y |
| 110 | CONFIG_GPIO_SYSFS=y | 109 | CONFIG_GPIO_SYSFS=y |
| 110 | CONFIG_GPIO_GENERIC_PLATFORM=y | ||
| 111 | CONFIG_GPIO_EM=y | ||
| 112 | CONFIG_GPIO_PL061=y | ||
| 113 | CONFIG_GPIO_MAX7300=y | ||
| 114 | CONFIG_GPIO_MAX732X=y | ||
| 115 | CONFIG_GPIO_PCF857X=y | ||
| 116 | CONFIG_GPIO_SX150X=y | ||
| 117 | CONFIG_GPIO_ADP5588=y | ||
| 118 | CONFIG_GPIO_ADNP=y | ||
| 119 | CONFIG_GPIO_MAX7301=y | ||
| 120 | CONFIG_GPIO_MCP23S08=y | ||
| 121 | CONFIG_GPIO_MC33880=y | ||
| 122 | CONFIG_GPIO_74X164=y | ||
| 111 | CONFIG_SENSORS_DS620=y | 123 | CONFIG_SENSORS_DS620=y |
| 112 | CONFIG_SENSORS_MAX6639=y | 124 | CONFIG_SENSORS_MAX6639=y |
| 113 | CONFIG_WATCHDOG=y | 125 | CONFIG_WATCHDOG=y |
| @@ -144,6 +156,7 @@ CONFIG_USB_G_SERIAL=m | |||
| 144 | CONFIG_MMC=y | 156 | CONFIG_MMC=y |
| 145 | # CONFIG_MMC_BLOCK_BOUNCE is not set | 157 | # CONFIG_MMC_BLOCK_BOUNCE is not set |
| 146 | CONFIG_MMC_ARMMMCI=y | 158 | CONFIG_MMC_ARMMMCI=y |
| 159 | CONFIG_MMC_SPI=y | ||
| 147 | CONFIG_NEW_LEDS=y | 160 | CONFIG_NEW_LEDS=y |
| 148 | CONFIG_LEDS_CLASS=y | 161 | CONFIG_LEDS_CLASS=y |
| 149 | CONFIG_LEDS_PCA9532=y | 162 | CONFIG_LEDS_PCA9532=y |
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig index 7594b3aff259..9fb11895b2e2 100644 --- a/arch/arm/configs/mackerel_defconfig +++ b/arch/arm/configs/mackerel_defconfig | |||
| @@ -75,6 +75,7 @@ CONFIG_I2C=y | |||
| 75 | CONFIG_I2C_SH_MOBILE=y | 75 | CONFIG_I2C_SH_MOBILE=y |
| 76 | # CONFIG_HWMON is not set | 76 | # CONFIG_HWMON is not set |
| 77 | # CONFIG_MFD_SUPPORT is not set | 77 | # CONFIG_MFD_SUPPORT is not set |
| 78 | CONFIG_REGULATOR=y | ||
| 78 | CONFIG_FB=y | 79 | CONFIG_FB=y |
| 79 | CONFIG_FB_MODE_HELPERS=y | 80 | CONFIG_FB_MODE_HELPERS=y |
| 80 | CONFIG_FB_SH_MOBILE_LCDC=y | 81 | CONFIG_FB_SH_MOBILE_LCDC=y |
| @@ -94,6 +95,9 @@ CONFIG_USB_RENESAS_USBHS=y | |||
| 94 | CONFIG_USB_STORAGE=y | 95 | CONFIG_USB_STORAGE=y |
| 95 | CONFIG_USB_GADGET=y | 96 | CONFIG_USB_GADGET=y |
| 96 | CONFIG_USB_RENESAS_USBHS_UDC=y | 97 | CONFIG_USB_RENESAS_USBHS_UDC=y |
| 98 | CONFIG_MMC=y | ||
| 99 | CONFIG_MMC_SDHI=y | ||
| 100 | CONFIG_MMC_SH_MMCIF=y | ||
| 97 | CONFIG_DMADEVICES=y | 101 | CONFIG_DMADEVICES=y |
| 98 | CONFIG_SH_DMAE=y | 102 | CONFIG_SH_DMAE=y |
| 99 | CONFIG_EXT2_FS=y | 103 | CONFIG_EXT2_FS=y |
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig index afb17d630d44..494e70aeb9e1 100644 --- a/arch/arm/configs/marzen_defconfig +++ b/arch/arm/configs/marzen_defconfig | |||
| @@ -49,6 +49,10 @@ CONFIG_DEVTMPFS_MOUNT=y | |||
| 49 | # CONFIG_FW_LOADER is not set | 49 | # CONFIG_FW_LOADER is not set |
| 50 | CONFIG_SCSI=y | 50 | CONFIG_SCSI=y |
| 51 | CONFIG_BLK_DEV_SD=y | 51 | CONFIG_BLK_DEV_SD=y |
| 52 | CONFIG_ATA=y | ||
| 53 | CONFIG_ATA_SFF=y | ||
| 54 | CONFIG_ATA_BMDMA=y | ||
| 55 | CONFIG_SATA_RCAR=y | ||
| 52 | CONFIG_NETDEVICES=y | 56 | CONFIG_NETDEVICES=y |
| 53 | # CONFIG_NET_VENDOR_BROADCOM is not set | 57 | # CONFIG_NET_VENDOR_BROADCOM is not set |
| 54 | # CONFIG_NET_VENDOR_FARADAY is not set | 58 | # CONFIG_NET_VENDOR_FARADAY is not set |
| @@ -75,6 +79,7 @@ CONFIG_I2C_RCAR=y | |||
| 75 | CONFIG_SPI=y | 79 | CONFIG_SPI=y |
| 76 | CONFIG_SPI_SH_HSPI=y | 80 | CONFIG_SPI_SH_HSPI=y |
| 77 | CONFIG_GPIO_SYSFS=y | 81 | CONFIG_GPIO_SYSFS=y |
| 82 | CONFIG_GPIO_RCAR=y | ||
| 78 | # CONFIG_HWMON is not set | 83 | # CONFIG_HWMON is not set |
| 79 | CONFIG_THERMAL=y | 84 | CONFIG_THERMAL=y |
| 80 | CONFIG_RCAR_THERMAL=y | 85 | CONFIG_RCAR_THERMAL=y |
| @@ -88,6 +93,9 @@ CONFIG_USB_OHCI_HCD=y | |||
| 88 | CONFIG_USB_OHCI_HCD_PLATFORM=y | 93 | CONFIG_USB_OHCI_HCD_PLATFORM=y |
| 89 | CONFIG_USB_EHCI_HCD_PLATFORM=y | 94 | CONFIG_USB_EHCI_HCD_PLATFORM=y |
| 90 | CONFIG_USB_STORAGE=y | 95 | CONFIG_USB_STORAGE=y |
| 96 | CONFIG_NEW_LEDS=y | ||
| 97 | CONFIG_LEDS_CLASS=y | ||
| 98 | CONFIG_LEDS_GPIO=y | ||
| 91 | CONFIG_UIO=y | 99 | CONFIG_UIO=y |
| 92 | CONFIG_UIO_PDRV_GENIRQ=y | 100 | CONFIG_UIO_PDRV_GENIRQ=y |
| 93 | # CONFIG_IOMMU_SUPPORT is not set | 101 | # CONFIG_IOMMU_SUPPORT is not set |
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 87924d671115..7ba48d22bcd9 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig | |||
| @@ -75,7 +75,7 @@ CONFIG_REALTEK_PHY=y | |||
| 75 | CONFIG_MICREL_PHY=y | 75 | CONFIG_MICREL_PHY=y |
| 76 | # CONFIG_WLAN is not set | 76 | # CONFIG_WLAN is not set |
| 77 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 77 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
| 78 | CONFIG_INPUT_EVDEV=m | 78 | CONFIG_INPUT_EVDEV=y |
| 79 | # CONFIG_INPUT_KEYBOARD is not set | 79 | # CONFIG_INPUT_KEYBOARD is not set |
| 80 | # CONFIG_INPUT_MOUSE is not set | 80 | # CONFIG_INPUT_MOUSE is not set |
| 81 | CONFIG_INPUT_TOUCHSCREEN=y | 81 | CONFIG_INPUT_TOUCHSCREEN=y |
| @@ -99,6 +99,8 @@ CONFIG_SPI_MXS=y | |||
| 99 | CONFIG_DEBUG_GPIO=y | 99 | CONFIG_DEBUG_GPIO=y |
| 100 | CONFIG_GPIO_SYSFS=y | 100 | CONFIG_GPIO_SYSFS=y |
| 101 | # CONFIG_HWMON is not set | 101 | # CONFIG_HWMON is not set |
| 102 | CONFIG_WATCHDOG=y | ||
| 103 | CONFIG_STMP3XXX_RTC_WATCHDOG=y | ||
| 102 | CONFIG_REGULATOR=y | 104 | CONFIG_REGULATOR=y |
| 103 | CONFIG_REGULATOR_FIXED_VOLTAGE=y | 105 | CONFIG_REGULATOR_FIXED_VOLTAGE=y |
| 104 | CONFIG_FB=y | 106 | CONFIG_FB=y |
| @@ -123,6 +125,7 @@ CONFIG_USB_STORAGE=y | |||
| 123 | CONFIG_USB_PHY=y | 125 | CONFIG_USB_PHY=y |
| 124 | CONFIG_USB_MXS_PHY=y | 126 | CONFIG_USB_MXS_PHY=y |
| 125 | CONFIG_MMC=y | 127 | CONFIG_MMC=y |
| 128 | CONFIG_MMC_UNSAFE_RESUME=y | ||
| 126 | CONFIG_MMC_MXS=y | 129 | CONFIG_MMC_MXS=y |
| 127 | CONFIG_NEW_LEDS=y | 130 | CONFIG_NEW_LEDS=y |
| 128 | CONFIG_LEDS_CLASS=y | 131 | CONFIG_LEDS_CLASS=y |
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig new file mode 100644 index 000000000000..4d0dc3c16063 --- /dev/null +++ b/arch/arm/configs/sama5_defconfig | |||
| @@ -0,0 +1,181 @@ | |||
| 1 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 2 | # CONFIG_SWAP is not set | ||
| 3 | CONFIG_SYSVIPC=y | ||
| 4 | CONFIG_IRQ_DOMAIN_DEBUG=y | ||
| 5 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 6 | CONFIG_SYSFS_DEPRECATED=y | ||
| 7 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 8 | CONFIG_BLK_DEV_INITRD=y | ||
| 9 | CONFIG_EMBEDDED=y | ||
| 10 | CONFIG_SLAB=y | ||
| 11 | CONFIG_MODULES=y | ||
| 12 | CONFIG_MODULE_FORCE_LOAD=y | ||
| 13 | CONFIG_MODULE_UNLOAD=y | ||
| 14 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 15 | # CONFIG_LBDAF is not set | ||
| 16 | # CONFIG_BLK_DEV_BSG is not set | ||
| 17 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 18 | # CONFIG_IOSCHED_CFQ is not set | ||
| 19 | CONFIG_ARCH_AT91=y | ||
| 20 | CONFIG_SOC_SAM_V7=y | ||
| 21 | CONFIG_SOC_SAMA5D3=y | ||
| 22 | CONFIG_MACH_SAMA5_DT=y | ||
| 23 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | ||
| 24 | CONFIG_AEABI=y | ||
| 25 | # CONFIG_OABI_COMPAT is not set | ||
| 26 | CONFIG_UACCESS_WITH_MEMCPY=y | ||
| 27 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 28 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 29 | CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" | ||
| 30 | CONFIG_AUTO_ZRELADDR=y | ||
| 31 | CONFIG_VFP=y | ||
| 32 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 33 | CONFIG_PM_RUNTIME=y | ||
| 34 | CONFIG_PM_DEBUG=y | ||
| 35 | CONFIG_PM_ADVANCED_DEBUG=y | ||
| 36 | CONFIG_NET=y | ||
| 37 | CONFIG_PACKET=y | ||
| 38 | CONFIG_UNIX=y | ||
| 39 | CONFIG_INET=y | ||
| 40 | CONFIG_IP_MULTICAST=y | ||
| 41 | CONFIG_IP_PNP=y | ||
| 42 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 43 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 44 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 45 | # CONFIG_INET_LRO is not set | ||
| 46 | # CONFIG_INET_DIAG is not set | ||
| 47 | CONFIG_IPV6=y | ||
| 48 | # CONFIG_INET6_XFRM_MODE_TRANSPORT is not set | ||
| 49 | # CONFIG_INET6_XFRM_MODE_TUNNEL is not set | ||
| 50 | # CONFIG_INET6_XFRM_MODE_BEET is not set | ||
| 51 | CONFIG_IPV6_SIT_6RD=y | ||
| 52 | CONFIG_CAN=y | ||
| 53 | CONFIG_CAN_AT91=y | ||
| 54 | CONFIG_CFG80211=y | ||
| 55 | CONFIG_MAC80211=y | ||
| 56 | CONFIG_MAC80211_LEDS=y | ||
| 57 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 58 | CONFIG_DEVTMPFS=y | ||
| 59 | CONFIG_DEVTMPFS_MOUNT=y | ||
| 60 | # CONFIG_STANDALONE is not set | ||
| 61 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | ||
| 62 | CONFIG_MTD=y | ||
| 63 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 64 | CONFIG_MTD_CHAR=y | ||
| 65 | CONFIG_MTD_BLOCK=y | ||
| 66 | CONFIG_MTD_CFI=y | ||
| 67 | CONFIG_MTD_M25P80=y | ||
| 68 | CONFIG_MTD_NAND=y | ||
| 69 | CONFIG_MTD_NAND_ATMEL=y | ||
| 70 | CONFIG_MTD_UBI=y | ||
| 71 | CONFIG_BLK_DEV_LOOP=y | ||
| 72 | CONFIG_BLK_DEV_RAM=y | ||
| 73 | CONFIG_BLK_DEV_RAM_COUNT=4 | ||
| 74 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 75 | CONFIG_ATMEL_TCLIB=y | ||
| 76 | CONFIG_ATMEL_SSC=y | ||
| 77 | CONFIG_EEPROM_AT24=y | ||
| 78 | CONFIG_SCSI=y | ||
| 79 | CONFIG_BLK_DEV_SD=y | ||
| 80 | CONFIG_SCSI_MULTI_LUN=y | ||
| 81 | # CONFIG_SCSI_LOWLEVEL is not set | ||
| 82 | CONFIG_NETDEVICES=y | ||
| 83 | CONFIG_MII=y | ||
| 84 | CONFIG_MACB=y | ||
| 85 | # CONFIG_NET_VENDOR_BROADCOM is not set | ||
| 86 | # CONFIG_NET_VENDOR_CIRRUS is not set | ||
| 87 | # CONFIG_NET_VENDOR_FARADAY is not set | ||
| 88 | # CONFIG_NET_VENDOR_INTEL is not set | ||
| 89 | # CONFIG_NET_VENDOR_MARVELL is not set | ||
| 90 | # CONFIG_NET_VENDOR_MICREL is not set | ||
| 91 | # CONFIG_NET_VENDOR_MICROCHIP is not set | ||
| 92 | # CONFIG_NET_VENDOR_NATSEMI is not set | ||
| 93 | # CONFIG_NET_VENDOR_SEEQ is not set | ||
| 94 | # CONFIG_NET_VENDOR_SMSC is not set | ||
| 95 | # CONFIG_NET_VENDOR_STMICRO is not set | ||
| 96 | # CONFIG_NET_VENDOR_WIZNET is not set | ||
| 97 | CONFIG_MICREL_PHY=y | ||
| 98 | # CONFIG_WLAN is not set | ||
| 99 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 100 | CONFIG_INPUT_EVDEV=y | ||
| 101 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 102 | CONFIG_KEYBOARD_QT1070=y | ||
| 103 | CONFIG_KEYBOARD_GPIO=y | ||
| 104 | # CONFIG_INPUT_MOUSE is not set | ||
| 105 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 106 | CONFIG_TOUCHSCREEN_ATMEL_MXT=y | ||
| 107 | CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y | ||
| 108 | # CONFIG_SERIO is not set | ||
| 109 | CONFIG_LEGACY_PTY_COUNT=4 | ||
| 110 | CONFIG_SERIAL_ATMEL=y | ||
| 111 | CONFIG_SERIAL_ATMEL_CONSOLE=y | ||
| 112 | CONFIG_HW_RANDOM=y | ||
| 113 | CONFIG_I2C=y | ||
| 114 | CONFIG_I2C_CHARDEV=y | ||
| 115 | CONFIG_I2C_AT91=y | ||
| 116 | CONFIG_I2C_GPIO=y | ||
| 117 | CONFIG_SPI=y | ||
| 118 | CONFIG_SPI_ATMEL=y | ||
| 119 | CONFIG_SPI_GPIO=y | ||
| 120 | CONFIG_GPIO_SYSFS=y | ||
| 121 | # CONFIG_HWMON is not set | ||
| 122 | CONFIG_SSB=m | ||
| 123 | CONFIG_FB=y | ||
| 124 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 125 | # CONFIG_LCD_CLASS_DEVICE is not set | ||
| 126 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | ||
| 127 | # CONFIG_BACKLIGHT_GENERIC is not set | ||
| 128 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 129 | # CONFIG_HID_GENERIC is not set | ||
| 130 | CONFIG_USB=y | ||
| 131 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 132 | CONFIG_USB_EHCI_HCD=y | ||
| 133 | CONFIG_USB_OHCI_HCD=y | ||
| 134 | CONFIG_USB_ACM=y | ||
| 135 | CONFIG_USB_STORAGE=y | ||
| 136 | CONFIG_USB_GADGET=y | ||
| 137 | CONFIG_USB_AT91=y | ||
| 138 | CONFIG_USB_MASS_STORAGE=m | ||
| 139 | CONFIG_MMC=y | ||
| 140 | # CONFIG_MMC_BLOCK_BOUNCE is not set | ||
| 141 | CONFIG_MMC_ATMELMCI=y | ||
| 142 | CONFIG_NEW_LEDS=y | ||
| 143 | CONFIG_LEDS_CLASS=y | ||
| 144 | CONFIG_LEDS_GPIO=y | ||
| 145 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 146 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 147 | CONFIG_LEDS_TRIGGER_GPIO=y | ||
| 148 | CONFIG_RTC_CLASS=y | ||
| 149 | CONFIG_RTC_DRV_AT91RM9200=y | ||
| 150 | CONFIG_DMADEVICES=y | ||
| 151 | # CONFIG_IOMMU_SUPPORT is not set | ||
| 152 | CONFIG_IIO=y | ||
| 153 | CONFIG_AT91_ADC=y | ||
| 154 | CONFIG_EXT2_FS=y | ||
| 155 | CONFIG_FANOTIFY=y | ||
| 156 | CONFIG_VFAT_FS=y | ||
| 157 | CONFIG_TMPFS=y | ||
| 158 | CONFIG_JFFS2_FS=y | ||
| 159 | CONFIG_JFFS2_SUMMARY=y | ||
| 160 | CONFIG_UBIFS_FS=y | ||
| 161 | CONFIG_NFS_FS=y | ||
| 162 | CONFIG_ROOT_NFS=y | ||
| 163 | CONFIG_NLS_CODEPAGE_437=y | ||
| 164 | CONFIG_NLS_CODEPAGE_850=y | ||
| 165 | CONFIG_NLS_ISO8859_1=y | ||
| 166 | CONFIG_STRIP_ASM_SYMS=y | ||
| 167 | CONFIG_DEBUG_FS=y | ||
| 168 | # CONFIG_SCHED_DEBUG is not set | ||
| 169 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 170 | # CONFIG_FTRACE is not set | ||
| 171 | CONFIG_DEBUG_USER=y | ||
| 172 | CONFIG_DEBUG_LL=y | ||
| 173 | CONFIG_EARLY_PRINTK=y | ||
| 174 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 175 | CONFIG_CRYPTO_USER_API_HASH=m | ||
| 176 | CONFIG_CRYPTO_USER_API_SKCIPHER=m | ||
| 177 | CONFIG_CRYPTO_DEV_ATMEL_AES=y | ||
| 178 | CONFIG_CRYPTO_DEV_ATMEL_TDES=y | ||
| 179 | CONFIG_CRYPTO_DEV_ATMEL_SHA=y | ||
| 180 | CONFIG_CRC_CCITT=m | ||
| 181 | CONFIG_CRC_ITU_T=m | ||
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index aba4881d20e5..a5f0485133cf 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig | |||
| @@ -1,4 +1,3 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_NO_HZ=y | 1 | CONFIG_NO_HZ=y |
| 3 | CONFIG_HIGH_RES_TIMERS=y | 2 | CONFIG_HIGH_RES_TIMERS=y |
| 4 | CONFIG_IKCONFIG=y | 3 | CONFIG_IKCONFIG=y |
| @@ -20,15 +19,14 @@ CONFIG_MODULE_UNLOAD=y | |||
| 20 | CONFIG_MODULE_FORCE_UNLOAD=y | 19 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 21 | # CONFIG_BLK_DEV_BSG is not set | 20 | # CONFIG_BLK_DEV_BSG is not set |
| 22 | CONFIG_PARTITION_ADVANCED=y | 21 | CONFIG_PARTITION_ADVANCED=y |
| 23 | CONFIG_EFI_PARTITION=y | ||
| 24 | # CONFIG_IOSCHED_DEADLINE is not set | 22 | # CONFIG_IOSCHED_DEADLINE is not set |
| 25 | # CONFIG_IOSCHED_CFQ is not set | 23 | # CONFIG_IOSCHED_CFQ is not set |
| 26 | CONFIG_ARCH_TEGRA=y | 24 | CONFIG_ARCH_TEGRA=y |
| 27 | CONFIG_GPIO_PCA953X=y | 25 | CONFIG_GPIO_PCA953X=y |
| 28 | CONFIG_ARCH_TEGRA_2x_SOC=y | 26 | CONFIG_ARCH_TEGRA_2x_SOC=y |
| 29 | CONFIG_ARCH_TEGRA_3x_SOC=y | 27 | CONFIG_ARCH_TEGRA_3x_SOC=y |
| 28 | CONFIG_ARCH_TEGRA_114_SOC=y | ||
| 30 | CONFIG_TEGRA_PCI=y | 29 | CONFIG_TEGRA_PCI=y |
| 31 | CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA=y | ||
| 32 | CONFIG_TEGRA_EMC_SCALING_ENABLE=y | 30 | CONFIG_TEGRA_EMC_SCALING_ENABLE=y |
| 33 | CONFIG_SMP=y | 31 | CONFIG_SMP=y |
| 34 | CONFIG_PREEMPT=y | 32 | CONFIG_PREEMPT=y |
| @@ -37,8 +35,8 @@ CONFIG_AEABI=y | |||
| 37 | CONFIG_HIGHMEM=y | 35 | CONFIG_HIGHMEM=y |
| 38 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 36 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 39 | CONFIG_ZBOOT_ROM_BSS=0x0 | 37 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 40 | CONFIG_AUTO_ZRELADDR=y | ||
| 41 | CONFIG_KEXEC=y | 38 | CONFIG_KEXEC=y |
| 39 | CONFIG_AUTO_ZRELADDR=y | ||
| 42 | CONFIG_CPU_FREQ=y | 40 | CONFIG_CPU_FREQ=y |
| 43 | CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y | 41 | CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y |
| 44 | CONFIG_CPU_IDLE=y | 42 | CONFIG_CPU_IDLE=y |
| @@ -108,6 +106,7 @@ CONFIG_RT2X00=y | |||
| 108 | CONFIG_RT2800USB=m | 106 | CONFIG_RT2800USB=m |
| 109 | CONFIG_INPUT_EVDEV=y | 107 | CONFIG_INPUT_EVDEV=y |
| 110 | CONFIG_KEYBOARD_TEGRA=y | 108 | CONFIG_KEYBOARD_TEGRA=y |
| 109 | CONFIG_KEYBOARD_GPIO=y | ||
| 111 | CONFIG_INPUT_MISC=y | 110 | CONFIG_INPUT_MISC=y |
| 112 | CONFIG_INPUT_MPU3050=y | 111 | CONFIG_INPUT_MPU3050=y |
| 113 | # CONFIG_LEGACY_PTYS is not set | 112 | # CONFIG_LEGACY_PTYS is not set |
| @@ -117,7 +116,6 @@ CONFIG_SERIAL_8250_CONSOLE=y | |||
| 117 | CONFIG_SERIAL_TEGRA=y | 116 | CONFIG_SERIAL_TEGRA=y |
| 118 | CONFIG_SERIAL_OF_PLATFORM=y | 117 | CONFIG_SERIAL_OF_PLATFORM=y |
| 119 | # CONFIG_HW_RANDOM is not set | 118 | # CONFIG_HW_RANDOM is not set |
| 120 | CONFIG_I2C=y | ||
| 121 | # CONFIG_I2C_COMPAT is not set | 119 | # CONFIG_I2C_COMPAT is not set |
| 122 | CONFIG_I2C_MUX=y | 120 | CONFIG_I2C_MUX=y |
| 123 | CONFIG_I2C_MUX_PINCTRL=y | 121 | CONFIG_I2C_MUX_PINCTRL=y |
| @@ -126,6 +124,7 @@ CONFIG_SPI=y | |||
| 126 | CONFIG_SPI_TEGRA20_SFLASH=y | 124 | CONFIG_SPI_TEGRA20_SFLASH=y |
| 127 | CONFIG_SPI_TEGRA20_SLINK=y | 125 | CONFIG_SPI_TEGRA20_SLINK=y |
| 128 | CONFIG_GPIO_PCA953X_IRQ=y | 126 | CONFIG_GPIO_PCA953X_IRQ=y |
| 127 | CONFIG_GPIO_PALMAS=y | ||
| 129 | CONFIG_GPIO_TPS6586X=y | 128 | CONFIG_GPIO_TPS6586X=y |
| 130 | CONFIG_GPIO_TPS65910=y | 129 | CONFIG_GPIO_TPS65910=y |
| 131 | CONFIG_POWER_SUPPLY=y | 130 | CONFIG_POWER_SUPPLY=y |
| @@ -136,12 +135,17 @@ CONFIG_SENSORS_LM90=y | |||
| 136 | CONFIG_MFD_TPS6586X=y | 135 | CONFIG_MFD_TPS6586X=y |
| 137 | CONFIG_MFD_TPS65910=y | 136 | CONFIG_MFD_TPS65910=y |
| 138 | CONFIG_MFD_MAX8907=y | 137 | CONFIG_MFD_MAX8907=y |
| 138 | CONFIG_MFD_TPS65090=y | ||
| 139 | CONFIG_MFD_PALMAS=y | ||
| 139 | CONFIG_REGULATOR=y | 140 | CONFIG_REGULATOR=y |
| 140 | CONFIG_REGULATOR_FIXED_VOLTAGE=y | 141 | CONFIG_REGULATOR_FIXED_VOLTAGE=y |
| 141 | CONFIG_REGULATOR_VIRTUAL_CONSUMER=y | 142 | CONFIG_REGULATOR_VIRTUAL_CONSUMER=y |
| 142 | CONFIG_REGULATOR_GPIO=y | 143 | CONFIG_REGULATOR_GPIO=y |
| 143 | CONFIG_REGULATOR_MAX8907=y | 144 | CONFIG_REGULATOR_MAX8907=y |
| 145 | CONFIG_REGULATOR_PALMAS=y | ||
| 146 | CONFIG_REGULATOR_TPS51632=y | ||
| 144 | CONFIG_REGULATOR_TPS62360=y | 147 | CONFIG_REGULATOR_TPS62360=y |
| 148 | CONFIG_REGULATOR_TPS65090=y | ||
| 145 | CONFIG_REGULATOR_TPS6586X=y | 149 | CONFIG_REGULATOR_TPS6586X=y |
| 146 | CONFIG_REGULATOR_TPS65910=y | 150 | CONFIG_REGULATOR_TPS65910=y |
| 147 | CONFIG_MEDIA_SUPPORT=y | 151 | CONFIG_MEDIA_SUPPORT=y |
| @@ -187,10 +191,8 @@ CONFIG_LEDS_GPIO=y | |||
| 187 | CONFIG_LEDS_TRIGGERS=y | 191 | CONFIG_LEDS_TRIGGERS=y |
| 188 | CONFIG_LEDS_TRIGGER_GPIO=y | 192 | CONFIG_LEDS_TRIGGER_GPIO=y |
| 189 | CONFIG_RTC_CLASS=y | 193 | CONFIG_RTC_CLASS=y |
| 190 | CONFIG_RTC_INTF_SYSFS=y | ||
| 191 | CONFIG_RTC_INTF_PROC=y | ||
| 192 | CONFIG_RTC_INTF_DEV=y | ||
| 193 | CONFIG_RTC_DRV_MAX8907=y | 194 | CONFIG_RTC_DRV_MAX8907=y |
| 195 | CONFIG_RTC_DRV_PALMAS=y | ||
| 194 | CONFIG_RTC_DRV_TPS6586X=y | 196 | CONFIG_RTC_DRV_TPS6586X=y |
| 195 | CONFIG_RTC_DRV_TPS65910=y | 197 | CONFIG_RTC_DRV_TPS65910=y |
| 196 | CONFIG_RTC_DRV_EM3027=y | 198 | CONFIG_RTC_DRV_EM3027=y |
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index 426270fe080d..c037aa1065b7 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig | |||
| @@ -5,7 +5,6 @@ CONFIG_BLK_DEV_INITRD=y | |||
| 5 | CONFIG_KALLSYMS_ALL=y | 5 | CONFIG_KALLSYMS_ALL=y |
| 6 | CONFIG_MODULES=y | 6 | CONFIG_MODULES=y |
| 7 | CONFIG_MODULE_UNLOAD=y | 7 | CONFIG_MODULE_UNLOAD=y |
| 8 | # CONFIG_LBDAF is not set | ||
| 9 | # CONFIG_BLK_DEV_BSG is not set | 8 | # CONFIG_BLK_DEV_BSG is not set |
| 10 | CONFIG_ARCH_U8500=y | 9 | CONFIG_ARCH_U8500=y |
| 11 | CONFIG_MACH_HREFV60=y | 10 | CONFIG_MACH_HREFV60=y |
| @@ -90,6 +89,8 @@ CONFIG_LEDS_CLASS=y | |||
| 90 | CONFIG_LEDS_LM3530=y | 89 | CONFIG_LEDS_LM3530=y |
| 91 | CONFIG_LEDS_LP5521=y | 90 | CONFIG_LEDS_LP5521=y |
| 92 | CONFIG_LEDS_GPIO=y | 91 | CONFIG_LEDS_GPIO=y |
| 92 | CONFIG_LEDS_TRIGGERS=y | ||
| 93 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 93 | CONFIG_RTC_CLASS=y | 94 | CONFIG_RTC_CLASS=y |
| 94 | CONFIG_RTC_DRV_AB8500=y | 95 | CONFIG_RTC_DRV_AB8500=y |
| 95 | CONFIG_RTC_DRV_PL031=y | 96 | CONFIG_RTC_DRV_PL031=y |
| @@ -103,6 +104,7 @@ CONFIG_EXT2_FS_XATTR=y | |||
| 103 | CONFIG_EXT2_FS_POSIX_ACL=y | 104 | CONFIG_EXT2_FS_POSIX_ACL=y |
| 104 | CONFIG_EXT2_FS_SECURITY=y | 105 | CONFIG_EXT2_FS_SECURITY=y |
| 105 | CONFIG_EXT3_FS=y | 106 | CONFIG_EXT3_FS=y |
| 107 | CONFIG_EXT4_FS=y | ||
| 106 | CONFIG_VFAT_FS=y | 108 | CONFIG_VFAT_FS=y |
| 107 | CONFIG_TMPFS=y | 109 | CONFIG_TMPFS=y |
| 108 | CONFIG_TMPFS_POSIX_ACL=y | 110 | CONFIG_TMPFS_POSIX_ACL=y |
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 440682b708f3..02802386b894 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig | |||
| @@ -6,6 +6,10 @@ config HAVE_AT91_DBGU0 | |||
| 6 | config HAVE_AT91_DBGU1 | 6 | config HAVE_AT91_DBGU1 |
| 7 | bool | 7 | bool |
| 8 | 8 | ||
| 9 | config AT91_PMC_UNIT | ||
| 10 | bool | ||
| 11 | default !ARCH_AT91X40 | ||
| 12 | |||
| 9 | config AT91_SAM9_ALT_RESET | 13 | config AT91_SAM9_ALT_RESET |
| 10 | bool | 14 | bool |
| 11 | default !ARCH_AT91X40 | 15 | default !ARCH_AT91X40 |
| @@ -14,17 +18,59 @@ config AT91_SAM9G45_RESET | |||
| 14 | bool | 18 | bool |
| 15 | default !ARCH_AT91X40 | 19 | default !ARCH_AT91X40 |
| 16 | 20 | ||
| 21 | config AT91_SAM9_TIME | ||
| 22 | bool | ||
| 23 | |||
| 17 | config SOC_AT91SAM9 | 24 | config SOC_AT91SAM9 |
| 18 | bool | 25 | bool |
| 26 | select AT91_SAM9_TIME | ||
| 19 | select CPU_ARM926T | 27 | select CPU_ARM926T |
| 20 | select GENERIC_CLOCKEVENTS | 28 | select GENERIC_CLOCKEVENTS |
| 21 | select MULTI_IRQ_HANDLER | 29 | select MULTI_IRQ_HANDLER |
| 22 | select SPARSE_IRQ | 30 | select SPARSE_IRQ |
| 23 | 31 | ||
| 32 | config SOC_SAMA5 | ||
| 33 | bool | ||
| 34 | select AT91_SAM9_TIME | ||
| 35 | select CPU_V7 | ||
| 36 | select GENERIC_CLOCKEVENTS | ||
| 37 | select MULTI_IRQ_HANDLER | ||
| 38 | select SPARSE_IRQ | ||
| 39 | |||
| 24 | menu "Atmel AT91 System-on-Chip" | 40 | menu "Atmel AT91 System-on-Chip" |
| 25 | 41 | ||
| 42 | choice | ||
| 43 | |||
| 44 | prompt "Core type" | ||
| 45 | |||
| 46 | config SOC_SAM_V4_V5 | ||
| 47 | bool "ARM7/ARM9" | ||
| 48 | help | ||
| 49 | Select this if you are using one of Atmel's AT91SAM9, AT91RM9200 | ||
| 50 | or AT91X40 SoC. | ||
| 51 | |||
| 52 | config SOC_SAM_V7 | ||
| 53 | bool "Cortex A5" | ||
| 54 | help | ||
| 55 | Select this if you are using one of Atmel's SAMA5D3 SoC. | ||
| 56 | |||
| 57 | endchoice | ||
| 58 | |||
| 26 | comment "Atmel AT91 Processor" | 59 | comment "Atmel AT91 Processor" |
| 27 | 60 | ||
| 61 | if SOC_SAM_V7 | ||
| 62 | config SOC_SAMA5D3 | ||
| 63 | bool "SAMA5D3 family" | ||
| 64 | depends on SOC_SAM_V7 | ||
| 65 | select SOC_SAMA5 | ||
| 66 | select HAVE_FB_ATMEL | ||
| 67 | select HAVE_AT91_DBGU1 | ||
| 68 | help | ||
| 69 | Select this if you are using one of Atmel's SAMA5D3 family SoC. | ||
| 70 | This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35. | ||
| 71 | endif | ||
| 72 | |||
| 73 | if SOC_SAM_V4_V5 | ||
| 28 | config SOC_AT91RM9200 | 74 | config SOC_AT91RM9200 |
| 29 | bool "AT91RM9200" | 75 | bool "AT91RM9200" |
| 30 | select CPU_ARM920T | 76 | select CPU_ARM920T |
| @@ -90,13 +136,10 @@ config SOC_AT91SAM9N12 | |||
| 90 | help | 136 | help |
| 91 | Select this if you are using Atmel's AT91SAM9N12 SoC. | 137 | Select this if you are using Atmel's AT91SAM9N12 SoC. |
| 92 | 138 | ||
| 93 | config AT91_PMC_UNIT | ||
| 94 | bool | ||
| 95 | default !ARCH_AT91X40 | ||
| 96 | |||
| 97 | # ---------------------------------------------------------- | 139 | # ---------------------------------------------------------- |
| 98 | 140 | ||
| 99 | source arch/arm/mach-at91/Kconfig.non_dt | 141 | source arch/arm/mach-at91/Kconfig.non_dt |
| 142 | endif # SOC_SAM_V4_V5 | ||
| 100 | 143 | ||
| 101 | comment "Generic Board Type" | 144 | comment "Generic Board Type" |
| 102 | 145 | ||
| @@ -116,6 +159,14 @@ config MACH_AT91SAM9_DT | |||
| 116 | Select this if you want to experiment device-tree with | 159 | Select this if you want to experiment device-tree with |
| 117 | an Atmel Evaluation Kit. | 160 | an Atmel Evaluation Kit. |
| 118 | 161 | ||
| 162 | config MACH_SAMA5_DT | ||
| 163 | bool "Atmel SAMA5 Evaluation Kits with device-tree support" | ||
| 164 | depends on SOC_SAMA5 | ||
| 165 | select USE_OF | ||
| 166 | help | ||
| 167 | Select this if you want to experiment device-tree with | ||
| 168 | an Atmel Evaluation Kit. | ||
| 169 | |||
| 119 | # ---------------------------------------------------------- | 170 | # ---------------------------------------------------------- |
| 120 | 171 | ||
| 121 | comment "AT91 Feature Selections" | 172 | comment "AT91 Feature Selections" |
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 505fed961eb0..788562dccb43 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile | |||
| @@ -10,7 +10,8 @@ obj- := | |||
| 10 | obj-$(CONFIG_AT91_PMC_UNIT) += clock.o | 10 | obj-$(CONFIG_AT91_PMC_UNIT) += clock.o |
| 11 | obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o | 11 | obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o |
| 12 | obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o | 12 | obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o |
| 13 | obj-$(CONFIG_SOC_AT91SAM9) += at91sam926x_time.o sam9_smc.o | 13 | obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o |
| 14 | obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o | ||
| 14 | 15 | ||
| 15 | # CPU-specific support | 16 | # CPU-specific support |
| 16 | obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o at91rm9200_time.o | 17 | obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o at91rm9200_time.o |
| @@ -21,6 +22,7 @@ obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o | |||
| 21 | obj-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12.o | 22 | obj-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12.o |
| 22 | obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o | 23 | obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o |
| 23 | obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o | 24 | obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o |
| 25 | obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o | ||
| 24 | 26 | ||
| 25 | obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o | 27 | obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o |
| 26 | obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o | 28 | obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o |
| @@ -90,6 +92,9 @@ obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o | |||
| 90 | obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o | 92 | obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o |
| 91 | obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o | 93 | obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o |
| 92 | 94 | ||
| 95 | # SAMA5 board with device-tree | ||
| 96 | obj-$(CONFIG_MACH_SAMA5_DT) += board-dt-sama5.o | ||
| 97 | |||
| 93 | # AT91X40 board-specific support | 98 | # AT91X40 board-specific support |
| 94 | obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o | 99 | obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o |
| 95 | 100 | ||
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index 36b05fc28816..d193a409bc45 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c | |||
| @@ -385,7 +385,7 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { | |||
| 385 | 0 /* Advanced Interrupt Controller (IRQ6) */ | 385 | 0 /* Advanced Interrupt Controller (IRQ6) */ |
| 386 | }; | 386 | }; |
| 387 | 387 | ||
| 388 | AT91_SOC_START(rm9200) | 388 | AT91_SOC_START(at91rm9200) |
| 389 | .map_io = at91rm9200_map_io, | 389 | .map_io = at91rm9200_map_io, |
| 390 | .default_irq_priority = at91rm9200_default_irq_priority, | 390 | .default_irq_priority = at91rm9200_default_irq_priority, |
| 391 | .ioremap_registers = at91rm9200_ioremap_registers, | 391 | .ioremap_registers = at91rm9200_ioremap_registers, |
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index 44199bc2c665..a8ce24538da6 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c | |||
| @@ -397,7 +397,7 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = { | |||
| 397 | 0, /* Advanced Interrupt Controller */ | 397 | 0, /* Advanced Interrupt Controller */ |
| 398 | }; | 398 | }; |
| 399 | 399 | ||
| 400 | AT91_SOC_START(sam9260) | 400 | AT91_SOC_START(at91sam9260) |
| 401 | .map_io = at91sam9260_map_io, | 401 | .map_io = at91sam9260_map_io, |
| 402 | .default_irq_priority = at91sam9260_default_irq_priority, | 402 | .default_irq_priority = at91sam9260_default_irq_priority, |
| 403 | .ioremap_registers = at91sam9260_ioremap_registers, | 403 | .ioremap_registers = at91sam9260_ioremap_registers, |
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 2998a08afc2d..ac7a341bd0ff 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c | |||
| @@ -337,7 +337,7 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = { | |||
| 337 | 0, /* Advanced Interrupt Controller */ | 337 | 0, /* Advanced Interrupt Controller */ |
| 338 | }; | 338 | }; |
| 339 | 339 | ||
| 340 | AT91_SOC_START(sam9261) | 340 | AT91_SOC_START(at91sam9261) |
| 341 | .map_io = at91sam9261_map_io, | 341 | .map_io = at91sam9261_map_io, |
| 342 | .default_irq_priority = at91sam9261_default_irq_priority, | 342 | .default_irq_priority = at91sam9261_default_irq_priority, |
| 343 | .ioremap_registers = at91sam9261_ioremap_registers, | 343 | .ioremap_registers = at91sam9261_ioremap_registers, |
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index b9fc60d1b33a..8e2d9f4a9a45 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c | |||
| @@ -374,7 +374,7 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = { | |||
| 374 | 0, /* Advanced Interrupt Controller (IRQ1) */ | 374 | 0, /* Advanced Interrupt Controller (IRQ1) */ |
| 375 | }; | 375 | }; |
| 376 | 376 | ||
| 377 | AT91_SOC_START(sam9263) | 377 | AT91_SOC_START(at91sam9263) |
| 378 | .map_io = at91sam9263_map_io, | 378 | .map_io = at91sam9263_map_io, |
| 379 | .default_irq_priority = at91sam9263_default_irq_priority, | 379 | .default_irq_priority = at91sam9263_default_irq_priority, |
| 380 | .ioremap_registers = at91sam9263_ioremap_registers, | 380 | .ioremap_registers = at91sam9263_ioremap_registers, |
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 2ec5efea3f03..a6c224fc9542 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c | |||
| @@ -420,7 +420,7 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = { | |||
| 420 | 0, /* Advanced Interrupt Controller (IRQ0) */ | 420 | 0, /* Advanced Interrupt Controller (IRQ0) */ |
| 421 | }; | 421 | }; |
| 422 | 422 | ||
| 423 | AT91_SOC_START(sam9g45) | 423 | AT91_SOC_START(at91sam9g45) |
| 424 | .map_io = at91sam9g45_map_io, | 424 | .map_io = at91sam9g45_map_io, |
| 425 | .default_irq_priority = at91sam9g45_default_irq_priority, | 425 | .default_irq_priority = at91sam9g45_default_irq_priority, |
| 426 | .ioremap_registers = at91sam9g45_ioremap_registers, | 426 | .ioremap_registers = at91sam9g45_ioremap_registers, |
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c index ccd078355eed..13cdbcd48f51 100644 --- a/arch/arm/mach-at91/at91sam9n12.c +++ b/arch/arm/mach-at91/at91sam9n12.c | |||
| @@ -228,7 +228,7 @@ void __init at91sam9n12_initialize(void) | |||
| 228 | at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0); | 228 | at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0); |
| 229 | } | 229 | } |
| 230 | 230 | ||
| 231 | AT91_SOC_START(sam9n12) | 231 | AT91_SOC_START(at91sam9n12) |
| 232 | .map_io = at91sam9n12_map_io, | 232 | .map_io = at91sam9n12_map_io, |
| 233 | .register_clocks = at91sam9n12_register_clocks, | 233 | .register_clocks = at91sam9n12_register_clocks, |
| 234 | .init = at91sam9n12_initialize, | 234 | .init = at91sam9n12_initialize, |
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index eb98704db2d9..c39600764236 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c | |||
| @@ -340,7 +340,7 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = { | |||
| 340 | 0, /* Advanced Interrupt Controller */ | 340 | 0, /* Advanced Interrupt Controller */ |
| 341 | }; | 341 | }; |
| 342 | 342 | ||
| 343 | AT91_SOC_START(sam9rl) | 343 | AT91_SOC_START(at91sam9rl) |
| 344 | .map_io = at91sam9rl_map_io, | 344 | .map_io = at91sam9rl_map_io, |
| 345 | .default_irq_priority = at91sam9rl_default_irq_priority, | 345 | .default_irq_priority = at91sam9rl_default_irq_priority, |
| 346 | .ioremap_registers = at91sam9rl_ioremap_registers, | 346 | .ioremap_registers = at91sam9rl_ioremap_registers, |
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index a200d8a17123..e631fec040ce 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c | |||
| @@ -322,7 +322,7 @@ static void __init at91sam9x5_map_io(void) | |||
| 322 | * Interrupt initialization | 322 | * Interrupt initialization |
| 323 | * -------------------------------------------------------------------- */ | 323 | * -------------------------------------------------------------------- */ |
| 324 | 324 | ||
| 325 | AT91_SOC_START(sam9x5) | 325 | AT91_SOC_START(at91sam9x5) |
| 326 | .map_io = at91sam9x5_map_io, | 326 | .map_io = at91sam9x5_map_io, |
| 327 | .register_clocks = at91sam9x5_register_clocks, | 327 | .register_clocks = at91sam9x5_register_clocks, |
| 328 | AT91_SOC_END | 328 | AT91_SOC_END |
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c new file mode 100644 index 000000000000..705305e62bbc --- /dev/null +++ b/arch/arm/mach-at91/board-dt-sama5.c | |||
| @@ -0,0 +1,86 @@ | |||
| 1 | /* | ||
| 2 | * Setup code for SAMA5 Evaluation Kits with Device Tree support | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/types.h> | ||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/gpio.h> | ||
| 14 | #include <linux/micrel_phy.h> | ||
| 15 | #include <linux/of.h> | ||
| 16 | #include <linux/of_irq.h> | ||
| 17 | #include <linux/of_platform.h> | ||
| 18 | #include <linux/phy.h> | ||
| 19 | |||
| 20 | #include <asm/setup.h> | ||
| 21 | #include <asm/irq.h> | ||
| 22 | #include <asm/mach/arch.h> | ||
| 23 | #include <asm/mach/map.h> | ||
| 24 | #include <asm/mach/irq.h> | ||
| 25 | |||
| 26 | #include "at91_aic.h" | ||
| 27 | #include "generic.h" | ||
| 28 | |||
| 29 | |||
| 30 | static const struct of_device_id irq_of_match[] __initconst = { | ||
| 31 | |||
| 32 | { .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init }, | ||
| 33 | { /*sentinel*/ } | ||
| 34 | }; | ||
| 35 | |||
| 36 | static void __init at91_dt_init_irq(void) | ||
| 37 | { | ||
| 38 | of_irq_init(irq_of_match); | ||
| 39 | } | ||
| 40 | |||
| 41 | static int ksz9021rn_phy_fixup(struct phy_device *phy) | ||
| 42 | { | ||
| 43 | int value; | ||
| 44 | |||
| 45 | #define GMII_RCCPSR 260 | ||
| 46 | #define GMII_RRDPSR 261 | ||
| 47 | #define GMII_ERCR 11 | ||
| 48 | #define GMII_ERDWR 12 | ||
| 49 | |||
| 50 | /* Set delay values */ | ||
| 51 | value = GMII_RCCPSR | 0x8000; | ||
| 52 | phy_write(phy, GMII_ERCR, value); | ||
| 53 | value = 0xF2F4; | ||
| 54 | phy_write(phy, GMII_ERDWR, value); | ||
| 55 | value = GMII_RRDPSR | 0x8000; | ||
| 56 | phy_write(phy, GMII_ERCR, value); | ||
| 57 | value = 0x2222; | ||
| 58 | phy_write(phy, GMII_ERDWR, value); | ||
| 59 | |||
| 60 | return 0; | ||
| 61 | } | ||
| 62 | |||
| 63 | static void __init sama5_dt_device_init(void) | ||
| 64 | { | ||
| 65 | if (of_machine_is_compatible("atmel,sama5d3xcm")) | ||
| 66 | phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, | ||
| 67 | ksz9021rn_phy_fixup); | ||
| 68 | |||
| 69 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | ||
| 70 | } | ||
| 71 | |||
| 72 | static const char *sama5_dt_board_compat[] __initdata = { | ||
| 73 | "atmel,sama5", | ||
| 74 | NULL | ||
| 75 | }; | ||
| 76 | |||
| 77 | DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)") | ||
| 78 | /* Maintainer: Atmel */ | ||
| 79 | .init_time = at91sam926x_pit_init, | ||
| 80 | .map_io = at91_map_io, | ||
| 81 | .handle_irq = at91_aic5_handle_irq, | ||
| 82 | .init_early = at91_dt_initialize, | ||
| 83 | .init_irq = at91_dt_init_irq, | ||
| 84 | .init_machine = sama5_dt_device_init, | ||
| 85 | .dt_compat = sama5_dt_board_compat, | ||
| 86 | MACHINE_END | ||
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 33361505c0cd..da841885d01c 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c | |||
| @@ -54,7 +54,10 @@ EXPORT_SYMBOL_GPL(at91_pmc_base); | |||
| 54 | */ | 54 | */ |
| 55 | #define cpu_has_utmi() ( cpu_is_at91sam9rl() \ | 55 | #define cpu_has_utmi() ( cpu_is_at91sam9rl() \ |
| 56 | || cpu_is_at91sam9g45() \ | 56 | || cpu_is_at91sam9g45() \ |
| 57 | || cpu_is_at91sam9x5()) | 57 | || cpu_is_at91sam9x5() \ |
| 58 | || cpu_is_sama5d3()) | ||
| 59 | |||
| 60 | #define cpu_has_1056M_plla() (cpu_is_sama5d3()) | ||
| 58 | 61 | ||
| 59 | #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ | 62 | #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ |
| 60 | || cpu_is_at91sam9g45() \ | 63 | || cpu_is_at91sam9g45() \ |
| @@ -75,7 +78,8 @@ EXPORT_SYMBOL_GPL(at91_pmc_base); | |||
| 75 | || cpu_is_at91sam9n12())) | 78 | || cpu_is_at91sam9n12())) |
| 76 | 79 | ||
| 77 | #define cpu_has_upll() (cpu_is_at91sam9g45() \ | 80 | #define cpu_has_upll() (cpu_is_at91sam9g45() \ |
| 78 | || cpu_is_at91sam9x5()) | 81 | || cpu_is_at91sam9x5() \ |
| 82 | || cpu_is_sama5d3()) | ||
| 79 | 83 | ||
| 80 | /* USB host HS & FS */ | 84 | /* USB host HS & FS */ |
| 81 | #define cpu_has_uhp() (!cpu_is_at91sam9rl()) | 85 | #define cpu_has_uhp() (!cpu_is_at91sam9rl()) |
| @@ -83,18 +87,22 @@ EXPORT_SYMBOL_GPL(at91_pmc_base); | |||
| 83 | /* USB device FS only */ | 87 | /* USB device FS only */ |
| 84 | #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \ | 88 | #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \ |
| 85 | || cpu_is_at91sam9g45() \ | 89 | || cpu_is_at91sam9g45() \ |
| 86 | || cpu_is_at91sam9x5())) | 90 | || cpu_is_at91sam9x5() \ |
| 91 | || cpu_is_sama5d3())) | ||
| 87 | 92 | ||
| 88 | #define cpu_has_plladiv2() (cpu_is_at91sam9g45() \ | 93 | #define cpu_has_plladiv2() (cpu_is_at91sam9g45() \ |
| 89 | || cpu_is_at91sam9x5() \ | 94 | || cpu_is_at91sam9x5() \ |
| 90 | || cpu_is_at91sam9n12()) | 95 | || cpu_is_at91sam9n12() \ |
| 96 | || cpu_is_sama5d3()) | ||
| 91 | 97 | ||
| 92 | #define cpu_has_mdiv3() (cpu_is_at91sam9g45() \ | 98 | #define cpu_has_mdiv3() (cpu_is_at91sam9g45() \ |
| 93 | || cpu_is_at91sam9x5() \ | 99 | || cpu_is_at91sam9x5() \ |
| 94 | || cpu_is_at91sam9n12()) | 100 | || cpu_is_at91sam9n12() \ |
| 101 | || cpu_is_sama5d3()) | ||
| 95 | 102 | ||
| 96 | #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \ | 103 | #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \ |
| 97 | || cpu_is_at91sam9n12()) | 104 | || cpu_is_at91sam9n12() \ |
| 105 | || cpu_is_sama5d3()) | ||
| 98 | 106 | ||
| 99 | static LIST_HEAD(clocks); | 107 | static LIST_HEAD(clocks); |
| 100 | static DEFINE_SPINLOCK(clk_lock); | 108 | static DEFINE_SPINLOCK(clk_lock); |
| @@ -210,10 +218,26 @@ struct clk mck = { | |||
| 210 | 218 | ||
| 211 | static void pmc_periph_mode(struct clk *clk, int is_on) | 219 | static void pmc_periph_mode(struct clk *clk, int is_on) |
| 212 | { | 220 | { |
| 213 | if (is_on) | 221 | u32 regval = 0; |
| 214 | at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask); | 222 | |
| 215 | else | 223 | /* |
| 216 | at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask); | 224 | * With sama5d3 devices, we are managing clock division so we have to |
| 225 | * use the Peripheral Control Register introduced from at91sam9x5 | ||
| 226 | * devices. | ||
| 227 | */ | ||
| 228 | if (cpu_is_sama5d3()) { | ||
| 229 | regval |= AT91_PMC_PCR_CMD; /* write command */ | ||
| 230 | regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */ | ||
| 231 | regval |= AT91_PMC_PCR_DIV(clk->div); | ||
| 232 | if (is_on) | ||
| 233 | regval |= AT91_PMC_PCR_EN; /* enable clock */ | ||
| 234 | at91_pmc_write(AT91_PMC_PCR, regval); | ||
| 235 | } else { | ||
| 236 | if (is_on) | ||
| 237 | at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask); | ||
| 238 | else | ||
| 239 | at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask); | ||
| 240 | } | ||
| 217 | } | 241 | } |
| 218 | 242 | ||
| 219 | static struct clk __init *at91_css_to_clk(unsigned long css) | 243 | static struct clk __init *at91_css_to_clk(unsigned long css) |
| @@ -443,14 +467,18 @@ static void __init init_programmable_clock(struct clk *clk) | |||
| 443 | 467 | ||
| 444 | static int at91_clk_show(struct seq_file *s, void *unused) | 468 | static int at91_clk_show(struct seq_file *s, void *unused) |
| 445 | { | 469 | { |
| 446 | u32 scsr, pcsr, uckr = 0, sr; | 470 | u32 scsr, pcsr, pcsr1 = 0, uckr = 0, sr; |
| 447 | struct clk *clk; | 471 | struct clk *clk; |
| 448 | 472 | ||
| 449 | scsr = at91_pmc_read(AT91_PMC_SCSR); | 473 | scsr = at91_pmc_read(AT91_PMC_SCSR); |
| 450 | pcsr = at91_pmc_read(AT91_PMC_PCSR); | 474 | pcsr = at91_pmc_read(AT91_PMC_PCSR); |
| 475 | if (cpu_is_sama5d3()) | ||
| 476 | pcsr1 = at91_pmc_read(AT91_PMC_PCSR1); | ||
| 451 | sr = at91_pmc_read(AT91_PMC_SR); | 477 | sr = at91_pmc_read(AT91_PMC_SR); |
| 452 | seq_printf(s, "SCSR = %8x\n", scsr); | 478 | seq_printf(s, "SCSR = %8x\n", scsr); |
| 453 | seq_printf(s, "PCSR = %8x\n", pcsr); | 479 | seq_printf(s, "PCSR = %8x\n", pcsr); |
| 480 | if (cpu_is_sama5d3()) | ||
| 481 | seq_printf(s, "PCSR1 = %8x\n", pcsr1); | ||
| 454 | seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR)); | 482 | seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR)); |
| 455 | seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR)); | 483 | seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR)); |
| 456 | seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR)); | 484 | seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR)); |
| @@ -470,20 +498,30 @@ static int at91_clk_show(struct seq_file *s, void *unused) | |||
| 470 | list_for_each_entry(clk, &clocks, node) { | 498 | list_for_each_entry(clk, &clocks, node) { |
| 471 | char *state; | 499 | char *state; |
| 472 | 500 | ||
| 473 | if (clk->mode == pmc_sys_mode) | 501 | if (clk->mode == pmc_sys_mode) { |
| 474 | state = (scsr & clk->pmc_mask) ? "on" : "off"; | 502 | state = (scsr & clk->pmc_mask) ? "on" : "off"; |
| 475 | else if (clk->mode == pmc_periph_mode) | 503 | } else if (clk->mode == pmc_periph_mode) { |
| 476 | state = (pcsr & clk->pmc_mask) ? "on" : "off"; | 504 | if (cpu_is_sama5d3()) { |
| 477 | else if (clk->mode == pmc_uckr_mode) | 505 | u32 pmc_mask = 1 << (clk->pid % 32); |
| 506 | |||
| 507 | if (clk->pid > 31) | ||
| 508 | state = (pcsr1 & pmc_mask) ? "on" : "off"; | ||
| 509 | else | ||
| 510 | state = (pcsr & pmc_mask) ? "on" : "off"; | ||
| 511 | } else { | ||
| 512 | state = (pcsr & clk->pmc_mask) ? "on" : "off"; | ||
| 513 | } | ||
| 514 | } else if (clk->mode == pmc_uckr_mode) { | ||
| 478 | state = (uckr & clk->pmc_mask) ? "on" : "off"; | 515 | state = (uckr & clk->pmc_mask) ? "on" : "off"; |
| 479 | else if (clk->pmc_mask) | 516 | } else if (clk->pmc_mask) { |
| 480 | state = (sr & clk->pmc_mask) ? "on" : "off"; | 517 | state = (sr & clk->pmc_mask) ? "on" : "off"; |
| 481 | else if (clk == &clk32k || clk == &main_clk) | 518 | } else if (clk == &clk32k || clk == &main_clk) { |
| 482 | state = "on"; | 519 | state = "on"; |
| 483 | else | 520 | } else { |
| 484 | state = ""; | 521 | state = ""; |
| 522 | } | ||
| 485 | 523 | ||
| 486 | seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n", | 524 | seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n", |
| 487 | clk->name, clk->users, state, clk_get_rate(clk), | 525 | clk->name, clk->users, state, clk_get_rate(clk), |
| 488 | clk->parent ? clk->parent->name : ""); | 526 | clk->parent ? clk->parent->name : ""); |
| 489 | } | 527 | } |
| @@ -530,6 +568,9 @@ int __init clk_register(struct clk *clk) | |||
| 530 | if (clk_is_peripheral(clk)) { | 568 | if (clk_is_peripheral(clk)) { |
| 531 | if (!clk->parent) | 569 | if (!clk->parent) |
| 532 | clk->parent = &mck; | 570 | clk->parent = &mck; |
| 571 | if (cpu_is_sama5d3()) | ||
| 572 | clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz, | ||
| 573 | 1 << clk->div); | ||
| 533 | clk->mode = pmc_periph_mode; | 574 | clk->mode = pmc_periph_mode; |
| 534 | } | 575 | } |
| 535 | else if (clk_is_sys(clk)) { | 576 | else if (clk_is_sys(clk)) { |
| @@ -555,7 +596,11 @@ static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg) | |||
| 555 | unsigned mul, div; | 596 | unsigned mul, div; |
| 556 | 597 | ||
| 557 | div = reg & 0xff; | 598 | div = reg & 0xff; |
| 558 | mul = (reg >> 16) & 0x7ff; | 599 | if (cpu_is_sama5d3()) |
| 600 | mul = AT91_PMC3_MUL_GET(reg); | ||
| 601 | else | ||
| 602 | mul = AT91_PMC_MUL_GET(reg); | ||
| 603 | |||
| 559 | if (div && mul) { | 604 | if (div && mul) { |
| 560 | freq /= div; | 605 | freq /= div; |
| 561 | freq *= mul + 1; | 606 | freq *= mul + 1; |
| @@ -706,12 +751,15 @@ static int __init at91_pmc_init(unsigned long main_clock) | |||
| 706 | 751 | ||
| 707 | /* report if PLLA is more than mildly overclocked */ | 752 | /* report if PLLA is more than mildly overclocked */ |
| 708 | plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR)); | 753 | plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR)); |
| 709 | if (cpu_has_300M_plla()) { | 754 | if (cpu_has_1056M_plla()) { |
| 710 | if (plla.rate_hz > 300000000) | 755 | if (plla.rate_hz > 1056000000) |
| 711 | pll_overclock = true; | 756 | pll_overclock = true; |
| 712 | } else if (cpu_has_800M_plla()) { | 757 | } else if (cpu_has_800M_plla()) { |
| 713 | if (plla.rate_hz > 800000000) | 758 | if (plla.rate_hz > 800000000) |
| 714 | pll_overclock = true; | 759 | pll_overclock = true; |
| 760 | } else if (cpu_has_300M_plla()) { | ||
| 761 | if (plla.rate_hz > 300000000) | ||
| 762 | pll_overclock = true; | ||
| 715 | } else if (cpu_has_240M_plla()) { | 763 | } else if (cpu_has_240M_plla()) { |
| 716 | if (plla.rate_hz > 240000000) | 764 | if (plla.rate_hz > 240000000) |
| 717 | pll_overclock = true; | 765 | pll_overclock = true; |
| @@ -872,6 +920,7 @@ int __init at91_clock_init(unsigned long main_clock) | |||
| 872 | static int __init at91_clock_reset(void) | 920 | static int __init at91_clock_reset(void) |
| 873 | { | 921 | { |
| 874 | unsigned long pcdr = 0; | 922 | unsigned long pcdr = 0; |
| 923 | unsigned long pcdr1 = 0; | ||
| 875 | unsigned long scdr = 0; | 924 | unsigned long scdr = 0; |
| 876 | struct clk *clk; | 925 | struct clk *clk; |
| 877 | 926 | ||
| @@ -879,8 +928,17 @@ static int __init at91_clock_reset(void) | |||
| 879 | if (clk->users > 0) | 928 | if (clk->users > 0) |
| 880 | continue; | 929 | continue; |
| 881 | 930 | ||
| 882 | if (clk->mode == pmc_periph_mode) | 931 | if (clk->mode == pmc_periph_mode) { |
| 883 | pcdr |= clk->pmc_mask; | 932 | if (cpu_is_sama5d3()) { |
| 933 | u32 pmc_mask = 1 << (clk->pid % 32); | ||
| 934 | |||
| 935 | if (clk->pid > 31) | ||
| 936 | pcdr1 |= pmc_mask; | ||
| 937 | else | ||
| 938 | pcdr |= pmc_mask; | ||
| 939 | } else | ||
| 940 | pcdr |= clk->pmc_mask; | ||
| 941 | } | ||
| 884 | 942 | ||
| 885 | if (clk->mode == pmc_sys_mode) | 943 | if (clk->mode == pmc_sys_mode) |
| 886 | scdr |= clk->pmc_mask; | 944 | scdr |= clk->pmc_mask; |
| @@ -888,8 +946,9 @@ static int __init at91_clock_reset(void) | |||
| 888 | pr_debug("Clocks: disable unused %s\n", clk->name); | 946 | pr_debug("Clocks: disable unused %s\n", clk->name); |
| 889 | } | 947 | } |
| 890 | 948 | ||
| 891 | at91_pmc_write(AT91_PMC_PCDR, pcdr); | ||
| 892 | at91_pmc_write(AT91_PMC_SCDR, scdr); | 949 | at91_pmc_write(AT91_PMC_SCDR, scdr); |
| 950 | if (cpu_is_sama5d3()) | ||
| 951 | at91_pmc_write(AT91_PMC_PCDR1, pcdr1); | ||
| 893 | 952 | ||
| 894 | return 0; | 953 | return 0; |
| 895 | } | 954 | } |
diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h index c2e63e47dcbe..a98a39bbd883 100644 --- a/arch/arm/mach-at91/clock.h +++ b/arch/arm/mach-at91/clock.h | |||
| @@ -20,7 +20,9 @@ struct clk { | |||
| 20 | const char *name; /* unique clock name */ | 20 | const char *name; /* unique clock name */ |
| 21 | struct clk_lookup cl; | 21 | struct clk_lookup cl; |
| 22 | unsigned long rate_hz; | 22 | unsigned long rate_hz; |
| 23 | unsigned div; /* parent clock divider */ | ||
| 23 | struct clk *parent; | 24 | struct clk *parent; |
| 25 | unsigned pid; /* peripheral ID */ | ||
| 24 | u32 pmc_mask; | 26 | u32 pmc_mask; |
| 25 | void (*mode)(struct clk *, int); | 27 | void (*mode)(struct clk *, int); |
| 26 | unsigned id:3; /* PCK0..4, or 32k/main/a/b */ | 28 | unsigned id:3; /* PCK0..4, or 32k/main/a/b */ |
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index ea2c57a86ca6..31df12029c4e 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h | |||
| @@ -75,6 +75,9 @@ extern void __iomem *at91_pmc_base; | |||
| 75 | #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ | 75 | #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ |
| 76 | #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ | 76 | #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ |
| 77 | #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ | 77 | #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ |
| 78 | #define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff) | ||
| 79 | #define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */ | ||
| 80 | #define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f) | ||
| 78 | #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ | 81 | #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ |
| 79 | #define AT91_PMC_USBDIV_1 (0 << 28) | 82 | #define AT91_PMC_USBDIV_1 (0 << 28) |
| 80 | #define AT91_PMC_USBDIV_2 (1 << 28) | 83 | #define AT91_PMC_USBDIV_2 (1 << 28) |
| @@ -167,11 +170,18 @@ extern void __iomem *at91_pmc_base; | |||
| 167 | #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ | 170 | #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ |
| 168 | #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ | 171 | #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ |
| 169 | 172 | ||
| 170 | #define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9] */ | 173 | #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/ |
| 174 | #define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */ | ||
| 175 | #define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ | ||
| 176 | |||
| 177 | #define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ | ||
| 171 | #define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ | 178 | #define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ |
| 172 | #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */ | 179 | #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ |
| 173 | #define AT91_PMC_PCR_DIV (0x3 << 16) /* Divisor Value */ | 180 | #define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */ |
| 174 | #define AT91_PMC_PCRDIV(n) (((n) << 16) & AT91_PMC_PCR_DIV) | 181 | #define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ |
| 182 | #define AT91_PMC_PCR_DIV2 0x2 /* Peripheral clock is MCK/2 */ | ||
| 183 | #define AT91_PMC_PCR_DIV4 0x4 /* Peripheral clock is MCK/4 */ | ||
| 184 | #define AT91_PMC_PCR_DIV8 0x8 /* Peripheral clock is MCK/8 */ | ||
| 175 | #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ | 185 | #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ |
| 176 | 186 | ||
| 177 | #endif | 187 | #endif |
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index b6504c19d55c..0f3379fe645f 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h | |||
| @@ -36,6 +36,8 @@ | |||
| 36 | #define ARCH_ID_AT91M40807 0x14080745 | 36 | #define ARCH_ID_AT91M40807 0x14080745 |
| 37 | #define ARCH_ID_AT91R40008 0x44000840 | 37 | #define ARCH_ID_AT91R40008 0x44000840 |
| 38 | 38 | ||
| 39 | #define ARCH_ID_SAMA5D3 0x8A5C07C0 | ||
| 40 | |||
| 39 | #define ARCH_EXID_AT91SAM9M11 0x00000001 | 41 | #define ARCH_EXID_AT91SAM9M11 0x00000001 |
| 40 | #define ARCH_EXID_AT91SAM9M10 0x00000002 | 42 | #define ARCH_EXID_AT91SAM9M10 0x00000002 |
| 41 | #define ARCH_EXID_AT91SAM9G46 0x00000003 | 43 | #define ARCH_EXID_AT91SAM9G46 0x00000003 |
| @@ -47,6 +49,11 @@ | |||
| 47 | #define ARCH_EXID_AT91SAM9G25 0x00000003 | 49 | #define ARCH_EXID_AT91SAM9G25 0x00000003 |
| 48 | #define ARCH_EXID_AT91SAM9X25 0x00000004 | 50 | #define ARCH_EXID_AT91SAM9X25 0x00000004 |
| 49 | 51 | ||
| 52 | #define ARCH_EXID_SAMA5D31 0x00444300 | ||
| 53 | #define ARCH_EXID_SAMA5D33 0x00414300 | ||
| 54 | #define ARCH_EXID_SAMA5D34 0x00414301 | ||
| 55 | #define ARCH_EXID_SAMA5D35 0x00584300 | ||
| 56 | |||
| 50 | #define ARCH_FAMILY_AT91X92 0x09200000 | 57 | #define ARCH_FAMILY_AT91X92 0x09200000 |
| 51 | #define ARCH_FAMILY_AT91SAM9 0x01900000 | 58 | #define ARCH_FAMILY_AT91SAM9 0x01900000 |
| 52 | #define ARCH_FAMILY_AT91SAM9XE 0x02900000 | 59 | #define ARCH_FAMILY_AT91SAM9XE 0x02900000 |
| @@ -75,6 +82,9 @@ enum at91_soc_type { | |||
| 75 | /* SAM9N12 */ | 82 | /* SAM9N12 */ |
| 76 | AT91_SOC_SAM9N12, | 83 | AT91_SOC_SAM9N12, |
| 77 | 84 | ||
| 85 | /* SAMA5D3 */ | ||
| 86 | AT91_SOC_SAMA5D3, | ||
| 87 | |||
| 78 | /* Unknown type */ | 88 | /* Unknown type */ |
| 79 | AT91_SOC_NONE | 89 | AT91_SOC_NONE |
| 80 | }; | 90 | }; |
| @@ -93,6 +103,10 @@ enum at91_soc_subtype { | |||
| 93 | AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35, | 103 | AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35, |
| 94 | AT91_SOC_SAM9G25, AT91_SOC_SAM9X25, | 104 | AT91_SOC_SAM9G25, AT91_SOC_SAM9X25, |
| 95 | 105 | ||
| 106 | /* SAMA5D3 */ | ||
| 107 | AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34, | ||
| 108 | AT91_SOC_SAMA5D35, | ||
| 109 | |||
| 96 | /* Unknown subtype */ | 110 | /* Unknown subtype */ |
| 97 | AT91_SOC_SUBTYPE_NONE | 111 | AT91_SOC_SUBTYPE_NONE |
| 98 | }; | 112 | }; |
| @@ -187,6 +201,12 @@ static inline int at91_soc_is_detected(void) | |||
| 187 | #define cpu_is_at91sam9n12() (0) | 201 | #define cpu_is_at91sam9n12() (0) |
| 188 | #endif | 202 | #endif |
| 189 | 203 | ||
| 204 | #ifdef CONFIG_SOC_SAMA5D3 | ||
| 205 | #define cpu_is_sama5d3() (at91_soc_initdata.type == AT91_SOC_SAMA5D3) | ||
| 206 | #else | ||
| 207 | #define cpu_is_sama5d3() (0) | ||
| 208 | #endif | ||
| 209 | |||
| 190 | /* | 210 | /* |
| 191 | * Since this is ARM, we will never run on any AVR32 CPU. But these | 211 | * Since this is ARM, we will never run on any AVR32 CPU. But these |
| 192 | * definitions may reduce clutter in common drivers. | 212 | * definitions may reduce clutter in common drivers. |
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h new file mode 100644 index 000000000000..6dc81ee38048 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5d3.h | |||
| @@ -0,0 +1,73 @@ | |||
| 1 | /* | ||
| 2 | * Chip-specific header file for the SAMA5D3 family | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Common definitions. | ||
| 8 | * Based on SAMA5D3 datasheet. | ||
| 9 | * | ||
| 10 | * Licensed under GPLv2 or later. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef SAMA5D3_H | ||
| 14 | #define SAMA5D3_H | ||
| 15 | |||
| 16 | /* | ||
| 17 | * Peripheral identifiers/interrupts. | ||
| 18 | */ | ||
| 19 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 20 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
| 21 | #define SAMA5D3_ID_DBGU 2 /* debug Unit (usually no special interrupt line) */ | ||
| 22 | #define AT91_ID_PIT 3 /* PIT */ | ||
| 23 | #define SAMA5D3_ID_WDT 4 /* Watchdog Timer Interrupt */ | ||
| 24 | #define SAMA5D3_ID_HSMC 5 /* Static Memory Controller */ | ||
| 25 | #define SAMA5D3_ID_PIOA 6 /* PIOA */ | ||
| 26 | #define SAMA5D3_ID_PIOB 7 /* PIOB */ | ||
| 27 | #define SAMA5D3_ID_PIOC 8 /* PIOC */ | ||
| 28 | #define SAMA5D3_ID_PIOD 9 /* PIOD */ | ||
| 29 | #define SAMA5D3_ID_PIOE 10 /* PIOE */ | ||
| 30 | #define SAMA5D3_ID_SMD 11 /* SMD Soft Modem */ | ||
| 31 | #define SAMA5D3_ID_USART0 12 /* USART0 */ | ||
| 32 | #define SAMA5D3_ID_USART1 13 /* USART1 */ | ||
| 33 | #define SAMA5D3_ID_USART2 14 /* USART2 */ | ||
| 34 | #define SAMA5D3_ID_USART3 15 /* USART3 */ | ||
| 35 | #define SAMA5D3_ID_UART0 16 /* UART 0 */ | ||
| 36 | #define SAMA5D3_ID_UART1 17 /* UART 1 */ | ||
| 37 | #define SAMA5D3_ID_TWI0 18 /* Two-Wire Interface 0 */ | ||
| 38 | #define SAMA5D3_ID_TWI1 19 /* Two-Wire Interface 1 */ | ||
| 39 | #define SAMA5D3_ID_TWI2 20 /* Two-Wire Interface 2 */ | ||
| 40 | #define SAMA5D3_ID_HSMCI0 21 /* MCI */ | ||
| 41 | #define SAMA5D3_ID_HSMCI1 22 /* MCI */ | ||
| 42 | #define SAMA5D3_ID_HSMCI2 23 /* MCI */ | ||
| 43 | #define SAMA5D3_ID_SPI0 24 /* Serial Peripheral Interface 0 */ | ||
| 44 | #define SAMA5D3_ID_SPI1 25 /* Serial Peripheral Interface 1 */ | ||
| 45 | #define SAMA5D3_ID_TC0 26 /* Timer Counter 0 */ | ||
| 46 | #define SAMA5D3_ID_TC1 27 /* Timer Counter 2 */ | ||
| 47 | #define SAMA5D3_ID_PWM 28 /* Pulse Width Modulation Controller */ | ||
| 48 | #define SAMA5D3_ID_ADC 29 /* Touch Screen ADC Controller */ | ||
| 49 | #define SAMA5D3_ID_DMA0 30 /* DMA Controller 0 */ | ||
| 50 | #define SAMA5D3_ID_DMA1 31 /* DMA Controller 1 */ | ||
| 51 | #define SAMA5D3_ID_UHPHS 32 /* USB Host High Speed */ | ||
| 52 | #define SAMA5D3_ID_UDPHS 33 /* USB Device High Speed */ | ||
| 53 | #define SAMA5D3_ID_GMAC 34 /* Gigabit Ethernet MAC */ | ||
| 54 | #define SAMA5D3_ID_EMAC 35 /* Ethernet MAC */ | ||
| 55 | #define SAMA5D3_ID_LCDC 36 /* LCD Controller */ | ||
| 56 | #define SAMA5D3_ID_ISI 37 /* Image Sensor Interface */ | ||
| 57 | #define SAMA5D3_ID_SSC0 38 /* Synchronous Serial Controller 0 */ | ||
| 58 | #define SAMA5D3_ID_SSC1 39 /* Synchronous Serial Controller 1 */ | ||
| 59 | #define SAMA5D3_ID_CAN0 40 /* CAN Controller 0 */ | ||
| 60 | #define SAMA5D3_ID_CAN1 41 /* CAN Controller 1 */ | ||
| 61 | #define SAMA5D3_ID_SHA 42 /* Secure Hash Algorithm */ | ||
| 62 | #define SAMA5D3_ID_AES 43 /* Advanced Encryption Standard */ | ||
| 63 | #define SAMA5D3_ID_TDES 44 /* Triple Data Encryption Standard */ | ||
| 64 | #define SAMA5D3_ID_TRNG 45 /* True Random Generator Number */ | ||
| 65 | #define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 66 | |||
| 67 | /* | ||
| 68 | * Internal Memory | ||
| 69 | */ | ||
| 70 | #define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */ | ||
| 71 | #define SAMA5D3_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size (128Kb) */ | ||
| 72 | |||
| 73 | #endif | ||
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c new file mode 100644 index 000000000000..401279715ab1 --- /dev/null +++ b/arch/arm/mach-at91/sama5d3.c | |||
| @@ -0,0 +1,377 @@ | |||
| 1 | /* | ||
| 2 | * Chip-specific setup code for the SAMA5D3 family | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Atmel, | ||
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/module.h> | ||
| 11 | #include <linux/dma-mapping.h> | ||
| 12 | |||
| 13 | #include <asm/irq.h> | ||
| 14 | #include <asm/mach/arch.h> | ||
| 15 | #include <asm/mach/map.h> | ||
| 16 | #include <mach/sama5d3.h> | ||
| 17 | #include <mach/at91_pmc.h> | ||
| 18 | #include <mach/cpu.h> | ||
| 19 | |||
| 20 | #include "soc.h" | ||
| 21 | #include "generic.h" | ||
| 22 | #include "clock.h" | ||
| 23 | #include "sam9_smc.h" | ||
| 24 | |||
| 25 | /* -------------------------------------------------------------------- | ||
| 26 | * Clocks | ||
| 27 | * -------------------------------------------------------------------- */ | ||
| 28 | |||
| 29 | /* | ||
| 30 | * The peripheral clocks. | ||
| 31 | */ | ||
| 32 | |||
| 33 | static struct clk pioA_clk = { | ||
| 34 | .name = "pioA_clk", | ||
| 35 | .pid = SAMA5D3_ID_PIOA, | ||
| 36 | .type = CLK_TYPE_PERIPHERAL, | ||
| 37 | }; | ||
| 38 | static struct clk pioB_clk = { | ||
| 39 | .name = "pioB_clk", | ||
| 40 | .pid = SAMA5D3_ID_PIOB, | ||
| 41 | .type = CLK_TYPE_PERIPHERAL, | ||
| 42 | }; | ||
| 43 | static struct clk pioC_clk = { | ||
| 44 | .name = "pioC_clk", | ||
| 45 | .pid = SAMA5D3_ID_PIOC, | ||
| 46 | .type = CLK_TYPE_PERIPHERAL, | ||
| 47 | }; | ||
| 48 | static struct clk pioD_clk = { | ||
| 49 | .name = "pioD_clk", | ||
| 50 | .pid = SAMA5D3_ID_PIOD, | ||
| 51 | .type = CLK_TYPE_PERIPHERAL, | ||
| 52 | }; | ||
| 53 | static struct clk pioE_clk = { | ||
| 54 | .name = "pioE_clk", | ||
| 55 | .pid = SAMA5D3_ID_PIOE, | ||
| 56 | .type = CLK_TYPE_PERIPHERAL, | ||
| 57 | }; | ||
| 58 | static struct clk usart0_clk = { | ||
| 59 | .name = "usart0_clk", | ||
| 60 | .pid = SAMA5D3_ID_USART0, | ||
| 61 | .type = CLK_TYPE_PERIPHERAL, | ||
| 62 | .div = AT91_PMC_PCR_DIV2, | ||
| 63 | }; | ||
| 64 | static struct clk usart1_clk = { | ||
| 65 | .name = "usart1_clk", | ||
| 66 | .pid = SAMA5D3_ID_USART1, | ||
| 67 | .type = CLK_TYPE_PERIPHERAL, | ||
| 68 | .div = AT91_PMC_PCR_DIV2, | ||
| 69 | }; | ||
| 70 | static struct clk usart2_clk = { | ||
| 71 | .name = "usart2_clk", | ||
| 72 | .pid = SAMA5D3_ID_USART2, | ||
| 73 | .type = CLK_TYPE_PERIPHERAL, | ||
| 74 | .div = AT91_PMC_PCR_DIV2, | ||
| 75 | }; | ||
| 76 | static struct clk usart3_clk = { | ||
| 77 | .name = "usart3_clk", | ||
| 78 | .pid = SAMA5D3_ID_USART3, | ||
| 79 | .type = CLK_TYPE_PERIPHERAL, | ||
| 80 | .div = AT91_PMC_PCR_DIV2, | ||
| 81 | }; | ||
| 82 | static struct clk uart0_clk = { | ||
| 83 | .name = "uart0_clk", | ||
| 84 | .pid = SAMA5D3_ID_UART0, | ||
| 85 | .type = CLK_TYPE_PERIPHERAL, | ||
| 86 | .div = AT91_PMC_PCR_DIV2, | ||
| 87 | }; | ||
| 88 | static struct clk uart1_clk = { | ||
| 89 | .name = "uart1_clk", | ||
| 90 | .pid = SAMA5D3_ID_UART1, | ||
| 91 | .type = CLK_TYPE_PERIPHERAL, | ||
| 92 | .div = AT91_PMC_PCR_DIV2, | ||
| 93 | }; | ||
| 94 | static struct clk twi0_clk = { | ||
| 95 | .name = "twi0_clk", | ||
| 96 | .pid = SAMA5D3_ID_TWI0, | ||
| 97 | .type = CLK_TYPE_PERIPHERAL, | ||
| 98 | .div = AT91_PMC_PCR_DIV2, | ||
| 99 | }; | ||
| 100 | static struct clk twi1_clk = { | ||
| 101 | .name = "twi1_clk", | ||
| 102 | .pid = SAMA5D3_ID_TWI1, | ||
| 103 | .type = CLK_TYPE_PERIPHERAL, | ||
| 104 | .div = AT91_PMC_PCR_DIV2, | ||
| 105 | }; | ||
| 106 | static struct clk twi2_clk = { | ||
| 107 | .name = "twi2_clk", | ||
| 108 | .pid = SAMA5D3_ID_TWI2, | ||
| 109 | .type = CLK_TYPE_PERIPHERAL, | ||
| 110 | .div = AT91_PMC_PCR_DIV2, | ||
| 111 | }; | ||
| 112 | static struct clk mmc0_clk = { | ||
| 113 | .name = "mci0_clk", | ||
| 114 | .pid = SAMA5D3_ID_HSMCI0, | ||
| 115 | .type = CLK_TYPE_PERIPHERAL, | ||
| 116 | }; | ||
| 117 | static struct clk mmc1_clk = { | ||
| 118 | .name = "mci1_clk", | ||
| 119 | .pid = SAMA5D3_ID_HSMCI1, | ||
| 120 | .type = CLK_TYPE_PERIPHERAL, | ||
| 121 | }; | ||
| 122 | static struct clk mmc2_clk = { | ||
| 123 | .name = "mci2_clk", | ||
| 124 | .pid = SAMA5D3_ID_HSMCI2, | ||
| 125 | .type = CLK_TYPE_PERIPHERAL, | ||
| 126 | }; | ||
| 127 | static struct clk spi0_clk = { | ||
| 128 | .name = "spi0_clk", | ||
| 129 | .pid = SAMA5D3_ID_SPI0, | ||
| 130 | .type = CLK_TYPE_PERIPHERAL, | ||
| 131 | }; | ||
| 132 | static struct clk spi1_clk = { | ||
| 133 | .name = "spi1_clk", | ||
| 134 | .pid = SAMA5D3_ID_SPI1, | ||
| 135 | .type = CLK_TYPE_PERIPHERAL, | ||
| 136 | }; | ||
| 137 | static struct clk tcb0_clk = { | ||
| 138 | .name = "tcb0_clk", | ||
| 139 | .pid = SAMA5D3_ID_TC0, | ||
| 140 | .type = CLK_TYPE_PERIPHERAL, | ||
| 141 | .div = AT91_PMC_PCR_DIV2, | ||
| 142 | }; | ||
| 143 | static struct clk tcb1_clk = { | ||
| 144 | .name = "tcb1_clk", | ||
| 145 | .pid = SAMA5D3_ID_TC1, | ||
| 146 | .type = CLK_TYPE_PERIPHERAL, | ||
| 147 | .div = AT91_PMC_PCR_DIV2, | ||
| 148 | }; | ||
| 149 | static struct clk adc_clk = { | ||
| 150 | .name = "adc_clk", | ||
| 151 | .pid = SAMA5D3_ID_ADC, | ||
| 152 | .type = CLK_TYPE_PERIPHERAL, | ||
| 153 | .div = AT91_PMC_PCR_DIV2, | ||
| 154 | }; | ||
| 155 | static struct clk adc_op_clk = { | ||
| 156 | .name = "adc_op_clk", | ||
| 157 | .type = CLK_TYPE_PERIPHERAL, | ||
| 158 | .rate_hz = 5000000, | ||
| 159 | }; | ||
| 160 | static struct clk dma0_clk = { | ||
| 161 | .name = "dma0_clk", | ||
| 162 | .pid = SAMA5D3_ID_DMA0, | ||
| 163 | .type = CLK_TYPE_PERIPHERAL, | ||
| 164 | }; | ||
| 165 | static struct clk dma1_clk = { | ||
| 166 | .name = "dma1_clk", | ||
| 167 | .pid = SAMA5D3_ID_DMA1, | ||
| 168 | .type = CLK_TYPE_PERIPHERAL, | ||
| 169 | }; | ||
| 170 | static struct clk uhphs_clk = { | ||
| 171 | .name = "uhphs", | ||
| 172 | .pid = SAMA5D3_ID_UHPHS, | ||
| 173 | .type = CLK_TYPE_PERIPHERAL, | ||
| 174 | }; | ||
| 175 | static struct clk udphs_clk = { | ||
| 176 | .name = "udphs_clk", | ||
| 177 | .pid = SAMA5D3_ID_UDPHS, | ||
| 178 | .type = CLK_TYPE_PERIPHERAL, | ||
| 179 | }; | ||
| 180 | /* gmac only for sama5d33, sama5d34, sama5d35 */ | ||
| 181 | static struct clk macb0_clk = { | ||
| 182 | .name = "macb0_clk", | ||
| 183 | .pid = SAMA5D3_ID_GMAC, | ||
| 184 | .type = CLK_TYPE_PERIPHERAL, | ||
| 185 | }; | ||
| 186 | /* emac only for sama5d31, sama5d35 */ | ||
| 187 | static struct clk macb1_clk = { | ||
| 188 | .name = "macb1_clk", | ||
| 189 | .pid = SAMA5D3_ID_EMAC, | ||
| 190 | .type = CLK_TYPE_PERIPHERAL, | ||
| 191 | }; | ||
| 192 | /* lcd only for sama5d31, sama5d33, sama5d34 */ | ||
| 193 | static struct clk lcdc_clk = { | ||
| 194 | .name = "lcdc_clk", | ||
| 195 | .pid = SAMA5D3_ID_LCDC, | ||
| 196 | .type = CLK_TYPE_PERIPHERAL, | ||
| 197 | }; | ||
| 198 | /* isi only for sama5d33, sama5d35 */ | ||
| 199 | static struct clk isi_clk = { | ||
| 200 | .name = "isi_clk", | ||
| 201 | .pid = SAMA5D3_ID_ISI, | ||
| 202 | .type = CLK_TYPE_PERIPHERAL, | ||
| 203 | }; | ||
| 204 | static struct clk can0_clk = { | ||
| 205 | .name = "can0_clk", | ||
| 206 | .pid = SAMA5D3_ID_CAN0, | ||
| 207 | .type = CLK_TYPE_PERIPHERAL, | ||
| 208 | .div = AT91_PMC_PCR_DIV2, | ||
| 209 | }; | ||
| 210 | static struct clk can1_clk = { | ||
| 211 | .name = "can1_clk", | ||
| 212 | .pid = SAMA5D3_ID_CAN1, | ||
| 213 | .type = CLK_TYPE_PERIPHERAL, | ||
| 214 | .div = AT91_PMC_PCR_DIV2, | ||
| 215 | }; | ||
| 216 | static struct clk ssc0_clk = { | ||
| 217 | .name = "ssc0_clk", | ||
| 218 | .pid = SAMA5D3_ID_SSC0, | ||
| 219 | .type = CLK_TYPE_PERIPHERAL, | ||
| 220 | .div = AT91_PMC_PCR_DIV2, | ||
| 221 | }; | ||
| 222 | static struct clk ssc1_clk = { | ||
| 223 | .name = "ssc1_clk", | ||
| 224 | .pid = SAMA5D3_ID_SSC1, | ||
| 225 | .type = CLK_TYPE_PERIPHERAL, | ||
| 226 | .div = AT91_PMC_PCR_DIV2, | ||
| 227 | }; | ||
| 228 | static struct clk sha_clk = { | ||
| 229 | .name = "sha_clk", | ||
| 230 | .pid = SAMA5D3_ID_SHA, | ||
| 231 | .type = CLK_TYPE_PERIPHERAL, | ||
| 232 | .div = AT91_PMC_PCR_DIV8, | ||
| 233 | }; | ||
| 234 | static struct clk aes_clk = { | ||
| 235 | .name = "aes_clk", | ||
| 236 | .pid = SAMA5D3_ID_AES, | ||
| 237 | .type = CLK_TYPE_PERIPHERAL, | ||
| 238 | }; | ||
| 239 | static struct clk tdes_clk = { | ||
| 240 | .name = "tdes_clk", | ||
| 241 | .pid = SAMA5D3_ID_TDES, | ||
| 242 | .type = CLK_TYPE_PERIPHERAL, | ||
| 243 | }; | ||
| 244 | |||
| 245 | static struct clk *periph_clocks[] __initdata = { | ||
| 246 | &pioA_clk, | ||
| 247 | &pioB_clk, | ||
| 248 | &pioC_clk, | ||
| 249 | &pioD_clk, | ||
| 250 | &pioE_clk, | ||
| 251 | &usart0_clk, | ||
| 252 | &usart1_clk, | ||
| 253 | &usart2_clk, | ||
| 254 | &usart3_clk, | ||
| 255 | &uart0_clk, | ||
| 256 | &uart1_clk, | ||
| 257 | &twi0_clk, | ||
| 258 | &twi1_clk, | ||
| 259 | &twi2_clk, | ||
| 260 | &mmc0_clk, | ||
| 261 | &mmc1_clk, | ||
| 262 | &mmc2_clk, | ||
| 263 | &spi0_clk, | ||
| 264 | &spi1_clk, | ||
| 265 | &tcb0_clk, | ||
| 266 | &tcb1_clk, | ||
| 267 | &adc_clk, | ||
| 268 | &adc_op_clk, | ||
| 269 | &dma0_clk, | ||
| 270 | &dma1_clk, | ||
| 271 | &uhphs_clk, | ||
| 272 | &udphs_clk, | ||
| 273 | &macb0_clk, | ||
| 274 | &macb1_clk, | ||
| 275 | &lcdc_clk, | ||
| 276 | &isi_clk, | ||
| 277 | &can0_clk, | ||
| 278 | &can1_clk, | ||
| 279 | &ssc0_clk, | ||
| 280 | &ssc1_clk, | ||
| 281 | &sha_clk, | ||
| 282 | &aes_clk, | ||
| 283 | &tdes_clk, | ||
| 284 | }; | ||
| 285 | |||
| 286 | static struct clk pck0 = { | ||
| 287 | .name = "pck0", | ||
| 288 | .pmc_mask = AT91_PMC_PCK0, | ||
| 289 | .type = CLK_TYPE_PROGRAMMABLE, | ||
| 290 | .id = 0, | ||
| 291 | }; | ||
| 292 | |||
| 293 | static struct clk pck1 = { | ||
| 294 | .name = "pck1", | ||
| 295 | .pmc_mask = AT91_PMC_PCK1, | ||
| 296 | .type = CLK_TYPE_PROGRAMMABLE, | ||
| 297 | .id = 1, | ||
| 298 | }; | ||
| 299 | |||
| 300 | static struct clk pck2 = { | ||
| 301 | .name = "pck2", | ||
| 302 | .pmc_mask = AT91_PMC_PCK2, | ||
| 303 | .type = CLK_TYPE_PROGRAMMABLE, | ||
| 304 | .id = 2, | ||
| 305 | }; | ||
| 306 | |||
| 307 | static struct clk_lookup periph_clocks_lookups[] = { | ||
| 308 | /* lookup table for DT entries */ | ||
| 309 | CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck), | ||
| 310 | CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk), | ||
| 311 | CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk), | ||
| 312 | CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk), | ||
| 313 | CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk), | ||
| 314 | CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk), | ||
| 315 | CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk), | ||
| 316 | CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk), | ||
| 317 | CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk), | ||
| 318 | CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk), | ||
| 319 | CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk), | ||
| 320 | CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk), | ||
| 321 | CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk), | ||
| 322 | CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk), | ||
| 323 | CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk), | ||
| 324 | CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk), | ||
| 325 | CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk), | ||
| 326 | CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk), | ||
| 327 | CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk), | ||
| 328 | CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk), | ||
| 329 | CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk), | ||
| 330 | CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk), | ||
| 331 | CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk), | ||
| 332 | CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk), | ||
| 333 | CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk), | ||
| 334 | CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk), | ||
| 335 | CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk), | ||
| 336 | CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk), | ||
| 337 | CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk), | ||
| 338 | CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk), | ||
| 339 | CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk), | ||
| 340 | CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk), | ||
| 341 | CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk), | ||
| 342 | CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk), | ||
| 343 | CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk), | ||
| 344 | CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk), | ||
| 345 | CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk), | ||
| 346 | CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk), | ||
| 347 | CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk), | ||
| 348 | }; | ||
| 349 | |||
| 350 | static void __init sama5d3_register_clocks(void) | ||
| 351 | { | ||
| 352 | int i; | ||
| 353 | |||
| 354 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) | ||
| 355 | clk_register(periph_clocks[i]); | ||
| 356 | |||
| 357 | clkdev_add_table(periph_clocks_lookups, | ||
| 358 | ARRAY_SIZE(periph_clocks_lookups)); | ||
| 359 | |||
| 360 | clk_register(&pck0); | ||
| 361 | clk_register(&pck1); | ||
| 362 | clk_register(&pck2); | ||
| 363 | } | ||
| 364 | |||
| 365 | /* -------------------------------------------------------------------- | ||
| 366 | * AT91SAM9x5 processor initialization | ||
| 367 | * -------------------------------------------------------------------- */ | ||
| 368 | |||
| 369 | static void __init sama5d3_map_io(void) | ||
| 370 | { | ||
| 371 | at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE); | ||
| 372 | } | ||
| 373 | |||
| 374 | AT91_SOC_START(sama5d3) | ||
| 375 | .map_io = sama5d3_map_io, | ||
| 376 | .register_clocks = sama5d3_register_clocks, | ||
| 377 | AT91_SOC_END | ||
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index 9e7c1e1528e5..e8491e77b1f7 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c | |||
| @@ -151,6 +151,11 @@ static void __init soc_detect(u32 dbgu_base) | |||
| 151 | at91_soc_initdata.type = AT91_SOC_SAM9N12; | 151 | at91_soc_initdata.type = AT91_SOC_SAM9N12; |
| 152 | at91_boot_soc = at91sam9n12_soc; | 152 | at91_boot_soc = at91sam9n12_soc; |
| 153 | break; | 153 | break; |
| 154 | |||
| 155 | case ARCH_ID_SAMA5D3: | ||
| 156 | at91_soc_initdata.type = AT91_SOC_SAMA5D3; | ||
| 157 | at91_boot_soc = sama5d3_soc; | ||
| 158 | break; | ||
| 154 | } | 159 | } |
| 155 | 160 | ||
| 156 | /* at91sam9g10 */ | 161 | /* at91sam9g10 */ |
| @@ -206,6 +211,23 @@ static void __init soc_detect(u32 dbgu_base) | |||
| 206 | break; | 211 | break; |
| 207 | } | 212 | } |
| 208 | } | 213 | } |
| 214 | |||
| 215 | if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) { | ||
| 216 | switch (at91_soc_initdata.exid) { | ||
| 217 | case ARCH_EXID_SAMA5D31: | ||
| 218 | at91_soc_initdata.subtype = AT91_SOC_SAMA5D31; | ||
| 219 | break; | ||
| 220 | case ARCH_EXID_SAMA5D33: | ||
| 221 | at91_soc_initdata.subtype = AT91_SOC_SAMA5D33; | ||
| 222 | break; | ||
| 223 | case ARCH_EXID_SAMA5D34: | ||
| 224 | at91_soc_initdata.subtype = AT91_SOC_SAMA5D34; | ||
| 225 | break; | ||
| 226 | case ARCH_EXID_SAMA5D35: | ||
| 227 | at91_soc_initdata.subtype = AT91_SOC_SAMA5D35; | ||
| 228 | break; | ||
| 229 | } | ||
| 230 | } | ||
| 209 | } | 231 | } |
| 210 | 232 | ||
| 211 | static const char *soc_name[] = { | 233 | static const char *soc_name[] = { |
| @@ -219,6 +241,7 @@ static const char *soc_name[] = { | |||
| 219 | [AT91_SOC_SAM9RL] = "at91sam9rl", | 241 | [AT91_SOC_SAM9RL] = "at91sam9rl", |
| 220 | [AT91_SOC_SAM9X5] = "at91sam9x5", | 242 | [AT91_SOC_SAM9X5] = "at91sam9x5", |
| 221 | [AT91_SOC_SAM9N12] = "at91sam9n12", | 243 | [AT91_SOC_SAM9N12] = "at91sam9n12", |
| 244 | [AT91_SOC_SAMA5D3] = "sama5d3", | ||
| 222 | [AT91_SOC_NONE] = "Unknown" | 245 | [AT91_SOC_NONE] = "Unknown" |
| 223 | }; | 246 | }; |
| 224 | 247 | ||
| @@ -241,6 +264,10 @@ static const char *soc_subtype_name[] = { | |||
| 241 | [AT91_SOC_SAM9X35] = "at91sam9x35", | 264 | [AT91_SOC_SAM9X35] = "at91sam9x35", |
| 242 | [AT91_SOC_SAM9G25] = "at91sam9g25", | 265 | [AT91_SOC_SAM9G25] = "at91sam9g25", |
| 243 | [AT91_SOC_SAM9X25] = "at91sam9x25", | 266 | [AT91_SOC_SAM9X25] = "at91sam9x25", |
| 267 | [AT91_SOC_SAMA5D31] = "sama5d31", | ||
| 268 | [AT91_SOC_SAMA5D33] = "sama5d33", | ||
| 269 | [AT91_SOC_SAMA5D34] = "sama5d34", | ||
| 270 | [AT91_SOC_SAMA5D35] = "sama5d35", | ||
| 244 | [AT91_SOC_SUBTYPE_NONE] = "Unknown" | 271 | [AT91_SOC_SUBTYPE_NONE] = "Unknown" |
| 245 | }; | 272 | }; |
| 246 | 273 | ||
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h index 9c6d3d4f9a23..43a225f9e713 100644 --- a/arch/arm/mach-at91/soc.h +++ b/arch/arm/mach-at91/soc.h | |||
| @@ -22,9 +22,10 @@ extern struct at91_init_soc at91sam9g45_soc; | |||
| 22 | extern struct at91_init_soc at91sam9rl_soc; | 22 | extern struct at91_init_soc at91sam9rl_soc; |
| 23 | extern struct at91_init_soc at91sam9x5_soc; | 23 | extern struct at91_init_soc at91sam9x5_soc; |
| 24 | extern struct at91_init_soc at91sam9n12_soc; | 24 | extern struct at91_init_soc at91sam9n12_soc; |
| 25 | extern struct at91_init_soc sama5d3_soc; | ||
| 25 | 26 | ||
| 26 | #define AT91_SOC_START(_name) \ | 27 | #define AT91_SOC_START(_name) \ |
| 27 | struct at91_init_soc __initdata at91##_name##_soc \ | 28 | struct at91_init_soc __initdata _name##_soc \ |
| 28 | __used \ | 29 | __used \ |
| 29 | = { \ | 30 | = { \ |
| 30 | .builtin = 1, \ | 31 | .builtin = 1, \ |
| @@ -68,3 +69,7 @@ static inline int at91_soc_is_enabled(void) | |||
| 68 | #if !defined(CONFIG_SOC_AT91SAM9N12) | 69 | #if !defined(CONFIG_SOC_AT91SAM9N12) |
| 69 | #define at91sam9n12_soc at91_boot_soc | 70 | #define at91sam9n12_soc at91_boot_soc |
| 70 | #endif | 71 | #endif |
| 72 | |||
| 73 | #if !defined(CONFIG_SOC_SAMA5D3) | ||
| 74 | #define sama5d3_soc at91_boot_soc | ||
| 75 | #endif | ||
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 6da25eebf911..12e6f756361d 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c | |||
| @@ -246,7 +246,6 @@ static struct davinci_mmc_config da830_evm_mmc_config = { | |||
| 246 | .wires = 8, | 246 | .wires = 8, |
| 247 | .max_freq = 50000000, | 247 | .max_freq = 50000000, |
| 248 | .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, | 248 | .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, |
| 249 | .version = MMC_CTLR_VERSION_2, | ||
| 250 | }; | 249 | }; |
| 251 | 250 | ||
| 252 | static inline void da830_evm_init_mmc(void) | 251 | static inline void da830_evm_init_mmc(void) |
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index c2dfe06563df..dcc8710936a5 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c | |||
| @@ -802,7 +802,6 @@ static struct davinci_mmc_config da850_mmc_config = { | |||
| 802 | .wires = 4, | 802 | .wires = 4, |
| 803 | .max_freq = 50000000, | 803 | .max_freq = 50000000, |
| 804 | .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, | 804 | .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, |
| 805 | .version = MMC_CTLR_VERSION_2, | ||
| 806 | }; | 805 | }; |
| 807 | 806 | ||
| 808 | static const short da850_evm_mmcsd0_pins[] __initconst = { | 807 | static const short da850_evm_mmcsd0_pins[] __initconst = { |
| @@ -1372,7 +1371,6 @@ static struct davinci_mmc_config da850_wl12xx_mmc_config = { | |||
| 1372 | .max_freq = 25000000, | 1371 | .max_freq = 25000000, |
| 1373 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NONREMOVABLE | | 1372 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NONREMOVABLE | |
| 1374 | MMC_CAP_POWER_OFF_CARD, | 1373 | MMC_CAP_POWER_OFF_CARD, |
| 1375 | .version = MMC_CTLR_VERSION_2, | ||
| 1376 | }; | 1374 | }; |
| 1377 | 1375 | ||
| 1378 | static const short da850_wl12xx_pins[] __initconst = { | 1376 | static const short da850_wl12xx_pins[] __initconst = { |
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index 886481c12173..c2a0a67d09e0 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c | |||
| @@ -345,7 +345,6 @@ static struct davinci_mmc_config dm355evm_mmc_config = { | |||
| 345 | .wires = 4, | 345 | .wires = 4, |
| 346 | .max_freq = 50000000, | 346 | .max_freq = 50000000, |
| 347 | .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, | 347 | .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, |
| 348 | .version = MMC_CTLR_VERSION_1, | ||
| 349 | }; | 348 | }; |
| 350 | 349 | ||
| 351 | /* Don't connect anything to J10 unless you're only using USB host | 350 | /* Don't connect anything to J10 unless you're only using USB host |
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 2a6674356585..fd38c8d22e3c 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c | |||
| @@ -255,7 +255,6 @@ static struct davinci_mmc_config dm365evm_mmc_config = { | |||
| 255 | .wires = 4, | 255 | .wires = 4, |
| 256 | .max_freq = 50000000, | 256 | .max_freq = 50000000, |
| 257 | .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, | 257 | .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, |
| 258 | .version = MMC_CTLR_VERSION_2, | ||
| 259 | }; | 258 | }; |
| 260 | 259 | ||
| 261 | static void dm365evm_emac_configure(void) | 260 | static void dm365evm_emac_configure(void) |
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 745280d4144c..e62108fd7926 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c | |||
| @@ -570,7 +570,6 @@ static struct davinci_mmc_config dm6446evm_mmc_config = { | |||
| 570 | .get_cd = dm6444evm_mmc_get_cd, | 570 | .get_cd = dm6444evm_mmc_get_cd, |
| 571 | .get_ro = dm6444evm_mmc_get_ro, | 571 | .get_ro = dm6444evm_mmc_get_ro, |
| 572 | .wires = 4, | 572 | .wires = 4, |
| 573 | .version = MMC_CTLR_VERSION_1 | ||
| 574 | }; | 573 | }; |
| 575 | 574 | ||
| 576 | static struct i2c_board_info __initdata i2c_info[] = { | 575 | static struct i2c_board_info __initdata i2c_info[] = { |
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c index 1c98107527fa..b70e83c03bed 100644 --- a/arch/arm/mach-davinci/board-neuros-osd2.c +++ b/arch/arm/mach-davinci/board-neuros-osd2.c | |||
| @@ -164,7 +164,6 @@ static void __init davinci_ntosd2_map_io(void) | |||
| 164 | 164 | ||
| 165 | static struct davinci_mmc_config davinci_ntosd2_mmc_config = { | 165 | static struct davinci_mmc_config davinci_ntosd2_mmc_config = { |
| 166 | .wires = 4, | 166 | .wires = 4, |
| 167 | .version = MMC_CTLR_VERSION_1 | ||
| 168 | }; | 167 | }; |
| 169 | 168 | ||
| 170 | 169 | ||
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c index 5a2bd44da54d..328dbd8a37f5 100644 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ b/arch/arm/mach-davinci/board-omapl138-hawk.c | |||
| @@ -136,7 +136,6 @@ static struct davinci_mmc_config da850_mmc_config = { | |||
| 136 | .wires = 4, | 136 | .wires = 4, |
| 137 | .max_freq = 50000000, | 137 | .max_freq = 50000000, |
| 138 | .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, | 138 | .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, |
| 139 | .version = MMC_CTLR_VERSION_2, | ||
| 140 | }; | 139 | }; |
| 141 | 140 | ||
| 142 | static __init void omapl138_hawk_mmc_init(void) | 141 | static __init void omapl138_hawk_mmc_init(void) |
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c index 4f416023d4e2..ba798370fc96 100644 --- a/arch/arm/mach-davinci/board-tnetv107x-evm.c +++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c | |||
| @@ -85,7 +85,6 @@ static struct davinci_mmc_config mmc_config = { | |||
| 85 | .wires = 4, | 85 | .wires = 4, |
| 86 | .max_freq = 50000000, | 86 | .max_freq = 50000000, |
| 87 | .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, | 87 | .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, |
| 88 | .version = MMC_CTLR_VERSION_1, | ||
| 89 | }; | 88 | }; |
| 90 | 89 | ||
| 91 | static const short sdio1_pins[] __initconst = { | 90 | static const short sdio1_pins[] __initconst = { |
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index d458558ee84a..dc9a470ff9c5 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c | |||
| @@ -35,19 +35,26 @@ static void __clk_enable(struct clk *clk) | |||
| 35 | { | 35 | { |
| 36 | if (clk->parent) | 36 | if (clk->parent) |
| 37 | __clk_enable(clk->parent); | 37 | __clk_enable(clk->parent); |
| 38 | if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) | 38 | if (clk->usecount++ == 0) { |
| 39 | davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, | 39 | if (clk->flags & CLK_PSC) |
| 40 | true, clk->flags); | 40 | davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, |
| 41 | true, clk->flags); | ||
| 42 | else if (clk->clk_enable) | ||
| 43 | clk->clk_enable(clk); | ||
| 44 | } | ||
| 41 | } | 45 | } |
| 42 | 46 | ||
| 43 | static void __clk_disable(struct clk *clk) | 47 | static void __clk_disable(struct clk *clk) |
| 44 | { | 48 | { |
| 45 | if (WARN_ON(clk->usecount == 0)) | 49 | if (WARN_ON(clk->usecount == 0)) |
| 46 | return; | 50 | return; |
| 47 | if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) && | 51 | if (--clk->usecount == 0) { |
| 48 | (clk->flags & CLK_PSC)) | 52 | if (!(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC)) |
| 49 | davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, | 53 | davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, |
| 50 | false, clk->flags); | 54 | false, clk->flags); |
| 55 | else if (clk->clk_disable) | ||
| 56 | clk->clk_disable(clk); | ||
| 57 | } | ||
| 51 | if (clk->parent) | 58 | if (clk->parent) |
| 52 | __clk_disable(clk->parent); | 59 | __clk_disable(clk->parent); |
| 53 | } | 60 | } |
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 8694b395fc92..1e4e836173a1 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h | |||
| @@ -104,6 +104,8 @@ struct clk { | |||
| 104 | int (*set_rate) (struct clk *clk, unsigned long rate); | 104 | int (*set_rate) (struct clk *clk, unsigned long rate); |
| 105 | int (*round_rate) (struct clk *clk, unsigned long rate); | 105 | int (*round_rate) (struct clk *clk, unsigned long rate); |
| 106 | int (*reset) (struct clk *clk, bool reset); | 106 | int (*reset) (struct clk *clk, bool reset); |
| 107 | void (*clk_enable) (struct clk *clk); | ||
| 108 | void (*clk_disable) (struct clk *clk); | ||
| 107 | }; | 109 | }; |
| 108 | 110 | ||
| 109 | /* Clock flags: SoC-specific flags start at BIT(16) */ | 111 | /* Clock flags: SoC-specific flags start at BIT(16) */ |
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index 678a54a64dae..abbaf0270be6 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c | |||
| @@ -394,7 +394,7 @@ static struct clk_lookup da830_clks[] = { | |||
| 394 | CLK(NULL, "tpcc", &tpcc_clk), | 394 | CLK(NULL, "tpcc", &tpcc_clk), |
| 395 | CLK(NULL, "tptc0", &tptc0_clk), | 395 | CLK(NULL, "tptc0", &tptc0_clk), |
| 396 | CLK(NULL, "tptc1", &tptc1_clk), | 396 | CLK(NULL, "tptc1", &tptc1_clk), |
| 397 | CLK("davinci_mmc.0", NULL, &mmcsd_clk), | 397 | CLK("da830-mmc.0", NULL, &mmcsd_clk), |
| 398 | CLK(NULL, "uart0", &uart0_clk), | 398 | CLK(NULL, "uart0", &uart0_clk), |
| 399 | CLK(NULL, "uart1", &uart1_clk), | 399 | CLK(NULL, "uart1", &uart1_clk), |
| 400 | CLK(NULL, "uart2", &uart2_clk), | 400 | CLK(NULL, "uart2", &uart2_clk), |
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 0c4a26ddebba..4d6933848abf 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c | |||
| @@ -383,6 +383,49 @@ static struct clk dsp_clk = { | |||
| 383 | .flags = PSC_LRST | PSC_FORCE, | 383 | .flags = PSC_LRST | PSC_FORCE, |
| 384 | }; | 384 | }; |
| 385 | 385 | ||
| 386 | static struct clk ehrpwm_clk = { | ||
| 387 | .name = "ehrpwm", | ||
| 388 | .parent = &pll0_sysclk2, | ||
| 389 | .lpsc = DA8XX_LPSC1_PWM, | ||
| 390 | .gpsc = 1, | ||
| 391 | .flags = DA850_CLK_ASYNC3, | ||
| 392 | }; | ||
| 393 | |||
| 394 | #define DA8XX_EHRPWM_TBCLKSYNC BIT(12) | ||
| 395 | |||
| 396 | static void ehrpwm_tblck_enable(struct clk *clk) | ||
| 397 | { | ||
| 398 | u32 val; | ||
| 399 | |||
| 400 | val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG)); | ||
| 401 | val |= DA8XX_EHRPWM_TBCLKSYNC; | ||
| 402 | writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG)); | ||
| 403 | } | ||
| 404 | |||
| 405 | static void ehrpwm_tblck_disable(struct clk *clk) | ||
| 406 | { | ||
| 407 | u32 val; | ||
| 408 | |||
| 409 | val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG)); | ||
| 410 | val &= ~DA8XX_EHRPWM_TBCLKSYNC; | ||
| 411 | writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG)); | ||
| 412 | } | ||
| 413 | |||
| 414 | static struct clk ehrpwm_tbclk = { | ||
| 415 | .name = "ehrpwm_tbclk", | ||
| 416 | .parent = &ehrpwm_clk, | ||
| 417 | .clk_enable = ehrpwm_tblck_enable, | ||
| 418 | .clk_disable = ehrpwm_tblck_disable, | ||
| 419 | }; | ||
| 420 | |||
| 421 | static struct clk ecap_clk = { | ||
| 422 | .name = "ecap", | ||
| 423 | .parent = &pll0_sysclk2, | ||
| 424 | .lpsc = DA8XX_LPSC1_ECAP, | ||
| 425 | .gpsc = 1, | ||
| 426 | .flags = DA850_CLK_ASYNC3, | ||
| 427 | }; | ||
| 428 | |||
| 386 | static struct clk_lookup da850_clks[] = { | 429 | static struct clk_lookup da850_clks[] = { |
| 387 | CLK(NULL, "ref", &ref_clk), | 430 | CLK(NULL, "ref", &ref_clk), |
| 388 | CLK(NULL, "pll0", &pll0_clk), | 431 | CLK(NULL, "pll0", &pll0_clk), |
| @@ -420,8 +463,8 @@ static struct clk_lookup da850_clks[] = { | |||
| 420 | CLK("davinci_emac.1", NULL, &emac_clk), | 463 | CLK("davinci_emac.1", NULL, &emac_clk), |
| 421 | CLK("davinci-mcasp.0", NULL, &mcasp_clk), | 464 | CLK("davinci-mcasp.0", NULL, &mcasp_clk), |
| 422 | CLK("da8xx_lcdc.0", "fck", &lcdc_clk), | 465 | CLK("da8xx_lcdc.0", "fck", &lcdc_clk), |
| 423 | CLK("davinci_mmc.0", NULL, &mmcsd0_clk), | 466 | CLK("da830-mmc.0", NULL, &mmcsd0_clk), |
| 424 | CLK("davinci_mmc.1", NULL, &mmcsd1_clk), | 467 | CLK("da830-mmc.1", NULL, &mmcsd1_clk), |
| 425 | CLK(NULL, "aemif", &aemif_clk), | 468 | CLK(NULL, "aemif", &aemif_clk), |
| 426 | CLK(NULL, "usb11", &usb11_clk), | 469 | CLK(NULL, "usb11", &usb11_clk), |
| 427 | CLK(NULL, "usb20", &usb20_clk), | 470 | CLK(NULL, "usb20", &usb20_clk), |
| @@ -430,6 +473,9 @@ static struct clk_lookup da850_clks[] = { | |||
| 430 | CLK("vpif", NULL, &vpif_clk), | 473 | CLK("vpif", NULL, &vpif_clk), |
| 431 | CLK("ahci", NULL, &sata_clk), | 474 | CLK("ahci", NULL, &sata_clk), |
| 432 | CLK("davinci-rproc.0", NULL, &dsp_clk), | 475 | CLK("davinci-rproc.0", NULL, &dsp_clk), |
| 476 | CLK("ehrpwm", "fck", &ehrpwm_clk), | ||
| 477 | CLK("ehrpwm", "tbclk", &ehrpwm_tbclk), | ||
| 478 | CLK("ecap", "fck", &ecap_clk), | ||
| 433 | CLK(NULL, NULL, NULL), | 479 | CLK(NULL, NULL, NULL), |
| 434 | }; | 480 | }; |
| 435 | 481 | ||
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c index 6b7a0a27fbd1..b1c0a5958275 100644 --- a/arch/arm/mach-davinci/da8xx-dt.c +++ b/arch/arm/mach-davinci/da8xx-dt.c | |||
| @@ -20,7 +20,7 @@ | |||
| 20 | 20 | ||
| 21 | #define DA8XX_NUM_UARTS 3 | 21 | #define DA8XX_NUM_UARTS 3 |
| 22 | 22 | ||
| 23 | void __init da8xx_uart_clk_enable(void) | 23 | static void __init da8xx_uart_clk_enable(void) |
| 24 | { | 24 | { |
| 25 | int i; | 25 | int i; |
| 26 | for (i = 0; i < DA8XX_NUM_UARTS; i++) | 26 | for (i = 0; i < DA8XX_NUM_UARTS; i++) |
| @@ -37,9 +37,10 @@ static void __init da8xx_init_irq(void) | |||
| 37 | of_irq_init(da8xx_irq_match); | 37 | of_irq_init(da8xx_irq_match); |
| 38 | } | 38 | } |
| 39 | 39 | ||
| 40 | struct of_dev_auxdata da850_auxdata_lookup[] __initdata = { | 40 | static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = { |
| 41 | OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL), | 41 | OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL), |
| 42 | OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "watchdog", NULL), | 42 | OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "watchdog", NULL), |
| 43 | OF_DEV_AUXDATA("ti,da830-mmc", 0x01c40000, "da830-mmc.0", NULL), | ||
| 43 | {} | 44 | {} |
| 44 | }; | 45 | }; |
| 45 | 46 | ||
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index fc50243b1481..bf572525175d 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c | |||
| @@ -12,7 +12,7 @@ | |||
| 12 | */ | 12 | */ |
| 13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
| 14 | #include <linux/platform_device.h> | 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/dma-mapping.h> | 15 | #include <linux/dma-contiguous.h> |
| 16 | #include <linux/serial_8250.h> | 16 | #include <linux/serial_8250.h> |
| 17 | #include <linux/ahci_platform.h> | 17 | #include <linux/ahci_platform.h> |
| 18 | #include <linux/clk.h> | 18 | #include <linux/clk.h> |
| @@ -664,7 +664,7 @@ static struct resource da8xx_mmcsd0_resources[] = { | |||
| 664 | }; | 664 | }; |
| 665 | 665 | ||
| 666 | static struct platform_device da8xx_mmcsd0_device = { | 666 | static struct platform_device da8xx_mmcsd0_device = { |
| 667 | .name = "davinci_mmc", | 667 | .name = "da830-mmc", |
| 668 | .id = 0, | 668 | .id = 0, |
| 669 | .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), | 669 | .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), |
| 670 | .resource = da8xx_mmcsd0_resources, | 670 | .resource = da8xx_mmcsd0_resources, |
| @@ -701,7 +701,7 @@ static struct resource da850_mmcsd1_resources[] = { | |||
| 701 | }; | 701 | }; |
| 702 | 702 | ||
| 703 | static struct platform_device da850_mmcsd1_device = { | 703 | static struct platform_device da850_mmcsd1_device = { |
| 704 | .name = "davinci_mmc", | 704 | .name = "da830-mmc", |
| 705 | .id = 1, | 705 | .id = 1, |
| 706 | .num_resources = ARRAY_SIZE(da850_mmcsd1_resources), | 706 | .num_resources = ARRAY_SIZE(da850_mmcsd1_resources), |
| 707 | .resource = da850_mmcsd1_resources, | 707 | .resource = da850_mmcsd1_resources, |
| @@ -714,6 +714,92 @@ int __init da850_register_mmcsd1(struct davinci_mmc_config *config) | |||
| 714 | } | 714 | } |
| 715 | #endif | 715 | #endif |
| 716 | 716 | ||
| 717 | static struct resource da8xx_rproc_resources[] = { | ||
| 718 | { /* DSP boot address */ | ||
| 719 | .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG, | ||
| 720 | .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3, | ||
| 721 | .flags = IORESOURCE_MEM, | ||
| 722 | }, | ||
| 723 | { /* DSP interrupt registers */ | ||
| 724 | .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG, | ||
| 725 | .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7, | ||
| 726 | .flags = IORESOURCE_MEM, | ||
| 727 | }, | ||
| 728 | { /* dsp irq */ | ||
| 729 | .start = IRQ_DA8XX_CHIPINT0, | ||
| 730 | .end = IRQ_DA8XX_CHIPINT0, | ||
| 731 | .flags = IORESOURCE_IRQ, | ||
| 732 | }, | ||
| 733 | }; | ||
| 734 | |||
| 735 | static struct platform_device da8xx_dsp = { | ||
| 736 | .name = "davinci-rproc", | ||
| 737 | .dev = { | ||
| 738 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 739 | }, | ||
| 740 | .num_resources = ARRAY_SIZE(da8xx_rproc_resources), | ||
| 741 | .resource = da8xx_rproc_resources, | ||
| 742 | }; | ||
| 743 | |||
| 744 | #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC) | ||
| 745 | |||
| 746 | static phys_addr_t rproc_base __initdata; | ||
| 747 | static unsigned long rproc_size __initdata; | ||
| 748 | |||
| 749 | static int __init early_rproc_mem(char *p) | ||
| 750 | { | ||
| 751 | char *endp; | ||
| 752 | |||
| 753 | if (p == NULL) | ||
| 754 | return 0; | ||
| 755 | |||
| 756 | rproc_size = memparse(p, &endp); | ||
| 757 | if (*endp == '@') | ||
| 758 | rproc_base = memparse(endp + 1, NULL); | ||
| 759 | |||
| 760 | return 0; | ||
| 761 | } | ||
| 762 | early_param("rproc_mem", early_rproc_mem); | ||
| 763 | |||
| 764 | void __init da8xx_rproc_reserve_cma(void) | ||
| 765 | { | ||
| 766 | int ret; | ||
| 767 | |||
| 768 | if (!rproc_base || !rproc_size) { | ||
| 769 | pr_err("%s: 'rproc_mem=nn@address' badly specified\n" | ||
| 770 | " 'nn' and 'address' must both be non-zero\n", | ||
| 771 | __func__); | ||
| 772 | |||
| 773 | return; | ||
| 774 | } | ||
| 775 | |||
| 776 | pr_info("%s: reserving 0x%lx @ 0x%lx...\n", | ||
| 777 | __func__, rproc_size, (unsigned long)rproc_base); | ||
| 778 | |||
| 779 | ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0); | ||
| 780 | if (ret) | ||
| 781 | pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret); | ||
| 782 | } | ||
| 783 | |||
| 784 | #else | ||
| 785 | |||
| 786 | void __init da8xx_rproc_reserve_cma(void) | ||
| 787 | { | ||
| 788 | } | ||
| 789 | |||
| 790 | #endif | ||
| 791 | |||
| 792 | int __init da8xx_register_rproc(void) | ||
| 793 | { | ||
| 794 | int ret; | ||
| 795 | |||
| 796 | ret = platform_device_register(&da8xx_dsp); | ||
| 797 | if (ret) | ||
| 798 | pr_err("%s: can't register DSP device: %d\n", __func__, ret); | ||
| 799 | |||
| 800 | return ret; | ||
| 801 | }; | ||
| 802 | |||
| 717 | static struct resource da8xx_rtc_resources[] = { | 803 | static struct resource da8xx_rtc_resources[] = { |
| 718 | { | 804 | { |
| 719 | .start = DA8XX_RTC_BASE, | 805 | .start = DA8XX_RTC_BASE, |
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c index 773ab07a71a0..cfb194df18ed 100644 --- a/arch/arm/mach-davinci/devices-tnetv107x.c +++ b/arch/arm/mach-davinci/devices-tnetv107x.c | |||
| @@ -218,7 +218,7 @@ static u64 mmc1_dma_mask = DMA_BIT_MASK(32); | |||
| 218 | 218 | ||
| 219 | static struct platform_device mmc_devices[2] = { | 219 | static struct platform_device mmc_devices[2] = { |
| 220 | { | 220 | { |
| 221 | .name = "davinci_mmc", | 221 | .name = "dm6441-mmc", |
| 222 | .id = 0, | 222 | .id = 0, |
| 223 | .dev = { | 223 | .dev = { |
| 224 | .dma_mask = &mmc0_dma_mask, | 224 | .dma_mask = &mmc0_dma_mask, |
| @@ -228,7 +228,7 @@ static struct platform_device mmc_devices[2] = { | |||
| 228 | .resource = mmc0_resources | 228 | .resource = mmc0_resources |
| 229 | }, | 229 | }, |
| 230 | { | 230 | { |
| 231 | .name = "davinci_mmc", | 231 | .name = "dm6441-mmc", |
| 232 | .id = 1, | 232 | .id = 1, |
| 233 | .dev = { | 233 | .dev = { |
| 234 | .dma_mask = &mmc1_dma_mask, | 234 | .dma_mask = &mmc1_dma_mask, |
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 4c48a36ee567..f6927df2dda8 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c | |||
| @@ -150,7 +150,7 @@ static struct resource mmcsd0_resources[] = { | |||
| 150 | }; | 150 | }; |
| 151 | 151 | ||
| 152 | static struct platform_device davinci_mmcsd0_device = { | 152 | static struct platform_device davinci_mmcsd0_device = { |
| 153 | .name = "davinci_mmc", | 153 | .name = "dm6441-mmc", |
| 154 | .id = 0, | 154 | .id = 0, |
| 155 | .dev = { | 155 | .dev = { |
| 156 | .dma_mask = &mmcsd0_dma_mask, | 156 | .dma_mask = &mmcsd0_dma_mask, |
| @@ -187,7 +187,7 @@ static struct resource mmcsd1_resources[] = { | |||
| 187 | }; | 187 | }; |
| 188 | 188 | ||
| 189 | static struct platform_device davinci_mmcsd1_device = { | 189 | static struct platform_device davinci_mmcsd1_device = { |
| 190 | .name = "davinci_mmc", | 190 | .name = "dm6441-mmc", |
| 191 | .id = 1, | 191 | .id = 1, |
| 192 | .dev = { | 192 | .dev = { |
| 193 | .dma_mask = &mmcsd1_dma_mask, | 193 | .dma_mask = &mmcsd1_dma_mask, |
| @@ -235,6 +235,7 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) | |||
| 235 | mmcsd1_resources[0].end = DM365_MMCSD1_BASE + | 235 | mmcsd1_resources[0].end = DM365_MMCSD1_BASE + |
| 236 | SZ_4K - 1; | 236 | SZ_4K - 1; |
| 237 | mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1; | 237 | mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1; |
| 238 | davinci_mmcsd1_device.name = "da830-mmc"; | ||
| 238 | } else | 239 | } else |
| 239 | break; | 240 | break; |
| 240 | 241 | ||
| @@ -256,6 +257,7 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) | |||
| 256 | mmcsd0_resources[0].end = DM365_MMCSD0_BASE + | 257 | mmcsd0_resources[0].end = DM365_MMCSD0_BASE + |
| 257 | SZ_4K - 1; | 258 | SZ_4K - 1; |
| 258 | mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0; | 259 | mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0; |
| 260 | davinci_mmcsd0_device.name = "da830-mmc"; | ||
| 259 | } else if (cpu_is_davinci_dm644x()) { | 261 | } else if (cpu_is_davinci_dm644x()) { |
| 260 | /* REVISIT: should this be in board-init code? */ | 262 | /* REVISIT: should this be in board-init code? */ |
| 261 | /* Power-on 3.3V IO cells */ | 263 | /* Power-on 3.3V IO cells */ |
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index bf9a9d4ad9f5..a11034a358f1 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c | |||
| @@ -363,8 +363,8 @@ static struct clk_lookup dm355_clks[] = { | |||
| 363 | CLK("i2c_davinci.1", NULL, &i2c_clk), | 363 | CLK("i2c_davinci.1", NULL, &i2c_clk), |
| 364 | CLK("davinci-mcbsp.0", NULL, &asp0_clk), | 364 | CLK("davinci-mcbsp.0", NULL, &asp0_clk), |
| 365 | CLK("davinci-mcbsp.1", NULL, &asp1_clk), | 365 | CLK("davinci-mcbsp.1", NULL, &asp1_clk), |
| 366 | CLK("davinci_mmc.0", NULL, &mmcsd0_clk), | 366 | CLK("dm6441-mmc.0", NULL, &mmcsd0_clk), |
| 367 | CLK("davinci_mmc.1", NULL, &mmcsd1_clk), | 367 | CLK("dm6441-mmc.1", NULL, &mmcsd1_clk), |
| 368 | CLK("spi_davinci.0", NULL, &spi0_clk), | 368 | CLK("spi_davinci.0", NULL, &spi0_clk), |
| 369 | CLK("spi_davinci.1", NULL, &spi1_clk), | 369 | CLK("spi_davinci.1", NULL, &spi1_clk), |
| 370 | CLK("spi_davinci.2", NULL, &spi2_clk), | 370 | CLK("spi_davinci.2", NULL, &spi2_clk), |
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index ff771ceac3f1..40fa4fee9331 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c | |||
| @@ -458,8 +458,8 @@ static struct clk_lookup dm365_clks[] = { | |||
| 458 | CLK(NULL, "uart0", &uart0_clk), | 458 | CLK(NULL, "uart0", &uart0_clk), |
| 459 | CLK(NULL, "uart1", &uart1_clk), | 459 | CLK(NULL, "uart1", &uart1_clk), |
| 460 | CLK("i2c_davinci.1", NULL, &i2c_clk), | 460 | CLK("i2c_davinci.1", NULL, &i2c_clk), |
| 461 | CLK("davinci_mmc.0", NULL, &mmcsd0_clk), | 461 | CLK("da830-mmc.0", NULL, &mmcsd0_clk), |
| 462 | CLK("davinci_mmc.1", NULL, &mmcsd1_clk), | 462 | CLK("da830-mmc.1", NULL, &mmcsd1_clk), |
| 463 | CLK("spi_davinci.0", NULL, &spi0_clk), | 463 | CLK("spi_davinci.0", NULL, &spi0_clk), |
| 464 | CLK("spi_davinci.1", NULL, &spi1_clk), | 464 | CLK("spi_davinci.1", NULL, &spi1_clk), |
| 465 | CLK("spi_davinci.2", NULL, &spi2_clk), | 465 | CLK("spi_davinci.2", NULL, &spi2_clk), |
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index c2a9273330bf..4d37d3e2a193 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c | |||
| @@ -310,7 +310,7 @@ static struct clk_lookup dm644x_clks[] = { | |||
| 310 | CLK("i2c_davinci.1", NULL, &i2c_clk), | 310 | CLK("i2c_davinci.1", NULL, &i2c_clk), |
| 311 | CLK("palm_bk3710", NULL, &ide_clk), | 311 | CLK("palm_bk3710", NULL, &ide_clk), |
| 312 | CLK("davinci-mcbsp", NULL, &asp_clk), | 312 | CLK("davinci-mcbsp", NULL, &asp_clk), |
| 313 | CLK("davinci_mmc.0", NULL, &mmcsd_clk), | 313 | CLK("dm6441-mmc.0", NULL, &mmcsd_clk), |
| 314 | CLK(NULL, "spi", &spi_clk), | 314 | CLK(NULL, "spi", &spi_clk), |
| 315 | CLK(NULL, "gpio", &gpio_clk), | 315 | CLK(NULL, "gpio", &gpio_clk), |
| 316 | CLK(NULL, "usb", &usb_clk), | 316 | CLK(NULL, "usb", &usb_clk), |
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index de439b7b9af1..2e1c9eae0a58 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h | |||
| @@ -54,7 +54,10 @@ extern unsigned int da850_max_speed; | |||
| 54 | #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000) | 54 | #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000) |
| 55 | #define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) | 55 | #define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) |
| 56 | #define DA8XX_JTAG_ID_REG 0x18 | 56 | #define DA8XX_JTAG_ID_REG 0x18 |
| 57 | #define DA8XX_HOST1CFG_REG 0x44 | ||
| 58 | #define DA8XX_CHIPSIG_REG 0x174 | ||
| 57 | #define DA8XX_CFGCHIP0_REG 0x17c | 59 | #define DA8XX_CFGCHIP0_REG 0x17c |
| 60 | #define DA8XX_CFGCHIP1_REG 0x180 | ||
| 58 | #define DA8XX_CFGCHIP2_REG 0x184 | 61 | #define DA8XX_CFGCHIP2_REG 0x184 |
| 59 | #define DA8XX_CFGCHIP3_REG 0x188 | 62 | #define DA8XX_CFGCHIP3_REG 0x188 |
| 60 | 63 | ||
| @@ -104,6 +107,8 @@ int __init da850_register_vpif_display | |||
| 104 | int __init da850_register_vpif_capture | 107 | int __init da850_register_vpif_capture |
| 105 | (struct vpif_capture_config *capture_config); | 108 | (struct vpif_capture_config *capture_config); |
| 106 | void da8xx_restart(char mode, const char *cmd); | 109 | void da8xx_restart(char mode, const char *cmd); |
| 110 | void da8xx_rproc_reserve_cma(void); | ||
| 111 | int da8xx_register_rproc(void); | ||
| 107 | 112 | ||
| 108 | extern struct platform_device da8xx_serial_device; | 113 | extern struct platform_device da8xx_serial_device; |
| 109 | extern struct emac_platform_data da8xx_emac_pdata; | 114 | extern struct emac_platform_data da8xx_emac_pdata; |
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S index 34290d14754b..b18b8ebc6508 100644 --- a/arch/arm/mach-davinci/include/mach/debug-macro.S +++ b/arch/arm/mach-davinci/include/mach/debug-macro.S | |||
| @@ -24,8 +24,6 @@ | |||
| 24 | 24 | ||
| 25 | #if defined(CONFIG_DEBUG_DAVINCI_DMx_UART0) | 25 | #if defined(CONFIG_DEBUG_DAVINCI_DMx_UART0) |
| 26 | #define UART_BASE DAVINCI_UART0_BASE | 26 | #define UART_BASE DAVINCI_UART0_BASE |
| 27 | #elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART0) | ||
| 28 | #define UART_BASE DA8XX_UART0_BASE | ||
| 29 | #elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART1) | 27 | #elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART1) |
| 30 | #define UART_BASE DA8XX_UART1_BASE | 28 | #define UART_BASE DA8XX_UART1_BASE |
| 31 | #elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART2) | 29 | #elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART2) |
diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c index eb8360b33aa9..a508fe587af7 100644 --- a/arch/arm/mach-davinci/pm.c +++ b/arch/arm/mach-davinci/pm.c | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <asm/delay.h> | 19 | #include <asm/delay.h> |
| 20 | #include <asm/io.h> | 20 | #include <asm/io.h> |
| 21 | 21 | ||
| 22 | #include <mach/common.h> | ||
| 22 | #include <mach/da8xx.h> | 23 | #include <mach/da8xx.h> |
| 23 | #include <mach/sram.h> | 24 | #include <mach/sram.h> |
| 24 | #include <mach/pm.h> | 25 | #include <mach/pm.h> |
diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c index c5f7ee5cc80a..f18928b073f5 100644 --- a/arch/arm/mach-davinci/sram.c +++ b/arch/arm/mach-davinci/sram.c | |||
| @@ -62,7 +62,7 @@ static int __init sram_init(void) | |||
| 62 | phys_addr_t phys = davinci_soc_info.sram_dma; | 62 | phys_addr_t phys = davinci_soc_info.sram_dma; |
| 63 | unsigned len = davinci_soc_info.sram_len; | 63 | unsigned len = davinci_soc_info.sram_len; |
| 64 | int status = 0; | 64 | int status = 0; |
| 65 | void *addr; | 65 | void __iomem *addr; |
| 66 | 66 | ||
| 67 | if (len) { | 67 | if (len) { |
| 68 | len = min_t(unsigned, len, SRAM_SIZE); | 68 | len = min_t(unsigned, len, SRAM_SIZE); |
| @@ -75,7 +75,7 @@ static int __init sram_init(void) | |||
| 75 | addr = ioremap(phys, len); | 75 | addr = ioremap(phys, len); |
| 76 | if (!addr) | 76 | if (!addr) |
| 77 | return -ENOMEM; | 77 | return -ENOMEM; |
| 78 | status = gen_pool_add_virt(sram_pool, (unsigned)addr, | 78 | status = gen_pool_add_virt(sram_pool, (unsigned long) addr, |
| 79 | phys, len, -1); | 79 | phys, len, -1); |
| 80 | if (status < 0) | 80 | if (status < 0) |
| 81 | iounmap(addr); | 81 | iounmap(addr); |
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c index dc1a209b9b66..3b2a70d43efa 100644 --- a/arch/arm/mach-davinci/tnetv107x.c +++ b/arch/arm/mach-davinci/tnetv107x.c | |||
| @@ -272,7 +272,7 @@ static struct clk_lookup clks[] = { | |||
| 272 | CLK("tnetv107x-keypad.0", NULL, &clk_keypad), | 272 | CLK("tnetv107x-keypad.0", NULL, &clk_keypad), |
| 273 | CLK(NULL, "clk_gpio", &clk_gpio), | 273 | CLK(NULL, "clk_gpio", &clk_gpio), |
| 274 | CLK(NULL, "clk_mdio", &clk_mdio), | 274 | CLK(NULL, "clk_mdio", &clk_mdio), |
| 275 | CLK("davinci_mmc.0", NULL, &clk_sdio0), | 275 | CLK("dm6441-mmc.0", NULL, &clk_sdio0), |
| 276 | CLK(NULL, "uart0", &clk_uart0), | 276 | CLK(NULL, "uart0", &clk_uart0), |
| 277 | CLK(NULL, "uart1", &clk_uart1), | 277 | CLK(NULL, "uart1", &clk_uart1), |
| 278 | CLK(NULL, "timer0", &clk_timer0), | 278 | CLK(NULL, "timer0", &clk_timer0), |
| @@ -292,7 +292,7 @@ static struct clk_lookup clks[] = { | |||
| 292 | CLK(NULL, "clk_system", &clk_system), | 292 | CLK(NULL, "clk_system", &clk_system), |
| 293 | CLK(NULL, "clk_imcop", &clk_imcop), | 293 | CLK(NULL, "clk_imcop", &clk_imcop), |
| 294 | CLK(NULL, "clk_spare", &clk_spare), | 294 | CLK(NULL, "clk_spare", &clk_spare), |
| 295 | CLK("davinci_mmc.1", NULL, &clk_sdio1), | 295 | CLK("dm6441-mmc.1", NULL, &clk_sdio1), |
| 296 | CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst), | 296 | CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst), |
| 297 | CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst), | 297 | CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst), |
| 298 | CLK(NULL, NULL, NULL), | 298 | CLK(NULL, NULL, NULL), |
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c index 34509ffba221..2b4c648f99b6 100644 --- a/arch/arm/mach-davinci/usb.c +++ b/arch/arm/mach-davinci/usb.c | |||
| @@ -10,6 +10,7 @@ | |||
| 10 | #include <mach/common.h> | 10 | #include <mach/common.h> |
| 11 | #include <mach/irqs.h> | 11 | #include <mach/irqs.h> |
| 12 | #include <mach/cputype.h> | 12 | #include <mach/cputype.h> |
| 13 | #include <mach/da8xx.h> | ||
| 13 | #include <linux/platform_data/usb-davinci.h> | 14 | #include <linux/platform_data/usb-davinci.h> |
| 14 | 15 | ||
| 15 | #define DAVINCI_USB_OTG_BASE 0x01c64000 | 16 | #define DAVINCI_USB_OTG_BASE 0x01c64000 |
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 1b0fa7afc7f8..15718da30c45 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c | |||
| @@ -463,6 +463,8 @@ void __init exynos4_init_irq(void) | |||
| 463 | * uses GIC instead of VIC. | 463 | * uses GIC instead of VIC. |
| 464 | */ | 464 | */ |
| 465 | s5p_init_irq(NULL, 0); | 465 | s5p_init_irq(NULL, 0); |
| 466 | |||
| 467 | gic_arch_extn.irq_set_wake = s3c_irq_wake; | ||
| 466 | } | 468 | } |
| 467 | 469 | ||
| 468 | void __init exynos5_init_irq(void) | 470 | void __init exynos5_init_irq(void) |
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index 498a7a23e260..17a18ff3d71e 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c | |||
| @@ -41,23 +41,24 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev, | |||
| 41 | struct cpuidle_driver *drv, | 41 | struct cpuidle_driver *drv, |
| 42 | int index); | 42 | int index); |
| 43 | 43 | ||
| 44 | static struct cpuidle_state exynos4_cpuidle_set[] __initdata = { | ||
| 45 | [0] = ARM_CPUIDLE_WFI_STATE, | ||
| 46 | [1] = { | ||
| 47 | .enter = exynos4_enter_lowpower, | ||
| 48 | .exit_latency = 300, | ||
| 49 | .target_residency = 100000, | ||
| 50 | .flags = CPUIDLE_FLAG_TIME_VALID, | ||
| 51 | .name = "C1", | ||
| 52 | .desc = "ARM power down", | ||
| 53 | }, | ||
| 54 | }; | ||
| 55 | |||
| 56 | static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device); | 44 | static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device); |
| 57 | 45 | ||
| 58 | static struct cpuidle_driver exynos4_idle_driver = { | 46 | static struct cpuidle_driver exynos4_idle_driver = { |
| 59 | .name = "exynos4_idle", | 47 | .name = "exynos4_idle", |
| 60 | .owner = THIS_MODULE, | 48 | .owner = THIS_MODULE, |
| 49 | .states = { | ||
| 50 | [0] = ARM_CPUIDLE_WFI_STATE, | ||
| 51 | [1] = { | ||
| 52 | .enter = exynos4_enter_lowpower, | ||
| 53 | .exit_latency = 300, | ||
| 54 | .target_residency = 100000, | ||
| 55 | .flags = CPUIDLE_FLAG_TIME_VALID, | ||
| 56 | .name = "C1", | ||
| 57 | .desc = "ARM power down", | ||
| 58 | }, | ||
| 59 | }, | ||
| 60 | .state_count = 2, | ||
| 61 | .safe_state_index = 0, | ||
| 61 | }; | 62 | }; |
| 62 | 63 | ||
| 63 | /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ | 64 | /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ |
| @@ -192,37 +193,30 @@ static void __init exynos5_core_down_clk(void) | |||
| 192 | 193 | ||
| 193 | static int __init exynos4_init_cpuidle(void) | 194 | static int __init exynos4_init_cpuidle(void) |
| 194 | { | 195 | { |
| 195 | int i, max_cpuidle_state, cpu_id; | 196 | int cpu_id, ret; |
| 196 | struct cpuidle_device *device; | 197 | struct cpuidle_device *device; |
| 197 | struct cpuidle_driver *drv = &exynos4_idle_driver; | ||
| 198 | 198 | ||
| 199 | if (soc_is_exynos5250()) | 199 | if (soc_is_exynos5250()) |
| 200 | exynos5_core_down_clk(); | 200 | exynos5_core_down_clk(); |
| 201 | 201 | ||
| 202 | /* Setup cpuidle driver */ | 202 | ret = cpuidle_register_driver(&exynos4_idle_driver); |
| 203 | drv->state_count = (sizeof(exynos4_cpuidle_set) / | 203 | if (ret) { |
| 204 | sizeof(struct cpuidle_state)); | 204 | printk(KERN_ERR "CPUidle failed to register driver\n"); |
| 205 | max_cpuidle_state = drv->state_count; | 205 | return ret; |
| 206 | for (i = 0; i < max_cpuidle_state; i++) { | ||
| 207 | memcpy(&drv->states[i], &exynos4_cpuidle_set[i], | ||
| 208 | sizeof(struct cpuidle_state)); | ||
| 209 | } | 206 | } |
| 210 | drv->safe_state_index = 0; | ||
| 211 | cpuidle_register_driver(&exynos4_idle_driver); | ||
| 212 | 207 | ||
| 213 | for_each_cpu(cpu_id, cpu_online_mask) { | 208 | for_each_online_cpu(cpu_id) { |
| 214 | device = &per_cpu(exynos4_cpuidle_device, cpu_id); | 209 | device = &per_cpu(exynos4_cpuidle_device, cpu_id); |
| 215 | device->cpu = cpu_id; | 210 | device->cpu = cpu_id; |
| 216 | 211 | ||
| 217 | if (cpu_id == 0) | 212 | /* Support IDLE only */ |
| 218 | device->state_count = (sizeof(exynos4_cpuidle_set) / | 213 | if (cpu_id != 0) |
| 219 | sizeof(struct cpuidle_state)); | 214 | device->state_count = 1; |
| 220 | else | ||
| 221 | device->state_count = 1; /* Support IDLE only */ | ||
| 222 | 215 | ||
| 223 | if (cpuidle_register_device(device)) { | 216 | ret = cpuidle_register_device(device); |
| 224 | printk(KERN_ERR "CPUidle register device failed\n,"); | 217 | if (ret) { |
| 225 | return -EIO; | 218 | printk(KERN_ERR "CPUidle register device failed\n"); |
| 219 | return ret; | ||
| 226 | } | 220 | } |
| 227 | } | 221 | } |
| 228 | 222 | ||
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h index a67ecfaf1216..7dbbfec13ea5 100644 --- a/arch/arm/mach-exynos/include/mach/pm-core.h +++ b/arch/arm/mach-exynos/include/mach/pm-core.h | |||
| @@ -27,13 +27,8 @@ static inline void s3c_pm_debug_init_uart(void) | |||
| 27 | 27 | ||
| 28 | static inline void s3c_pm_arch_prepare_irqs(void) | 28 | static inline void s3c_pm_arch_prepare_irqs(void) |
| 29 | { | 29 | { |
| 30 | unsigned int tmp; | 30 | __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK); |
| 31 | tmp = __raw_readl(S5P_WAKEUP_MASK); | 31 | __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); |
| 32 | tmp &= ~(1 << 31); | ||
| 33 | __raw_writel(tmp, S5P_WAKEUP_MASK); | ||
| 34 | |||
| 35 | __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK); | ||
| 36 | __raw_writel(s3c_irqwake_eintmask & 0xFFFFFFFE, S5P_EINT_WAKEUP_MASK); | ||
| 37 | } | 32 | } |
| 38 | 33 | ||
| 39 | static inline void s3c_pm_arch_stop_clocks(void) | 34 | static inline void s3c_pm_arch_stop_clocks(void) |
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index f9fd77e8f1f5..284313f3e02c 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c | |||
| @@ -30,19 +30,22 @@ | |||
| 30 | 30 | ||
| 31 | #include "common.h" | 31 | #include "common.h" |
| 32 | 32 | ||
| 33 | #define TIMER_MATCH_VAL 0x0000 | 33 | #define TIMER_MATCH_VAL 0x0000 |
| 34 | #define TIMER_COUNT_VAL 0x0004 | 34 | #define TIMER_COUNT_VAL 0x0004 |
| 35 | #define TIMER_ENABLE 0x0008 | 35 | #define TIMER_ENABLE 0x0008 |
| 36 | #define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1) | 36 | #define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1) |
| 37 | #define TIMER_ENABLE_EN BIT(0) | 37 | #define TIMER_ENABLE_EN BIT(0) |
| 38 | #define TIMER_CLEAR 0x000C | 38 | #define TIMER_CLEAR 0x000C |
| 39 | #define DGT_CLK_CTL_DIV_4 0x3 | 39 | #define DGT_CLK_CTL 0x10 |
| 40 | #define DGT_CLK_CTL_DIV_4 0x3 | ||
| 41 | #define TIMER_STS_GPT0_CLR_PEND BIT(10) | ||
| 40 | 42 | ||
| 41 | #define GPT_HZ 32768 | 43 | #define GPT_HZ 32768 |
| 42 | 44 | ||
| 43 | #define MSM_DGT_SHIFT 5 | 45 | #define MSM_DGT_SHIFT 5 |
| 44 | 46 | ||
| 45 | static void __iomem *event_base; | 47 | static void __iomem *event_base; |
| 48 | static void __iomem *sts_base; | ||
| 46 | 49 | ||
| 47 | static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) | 50 | static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) |
| 48 | { | 51 | { |
| @@ -67,6 +70,11 @@ static int msm_timer_set_next_event(unsigned long cycles, | |||
| 67 | 70 | ||
| 68 | writel_relaxed(ctrl, event_base + TIMER_CLEAR); | 71 | writel_relaxed(ctrl, event_base + TIMER_CLEAR); |
| 69 | writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); | 72 | writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); |
| 73 | |||
| 74 | if (sts_base) | ||
| 75 | while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND) | ||
| 76 | cpu_relax(); | ||
| 77 | |||
| 70 | writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); | 78 | writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); |
| 71 | return 0; | 79 | return 0; |
| 72 | } | 80 | } |
| @@ -137,9 +145,6 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt) | |||
| 137 | if (!smp_processor_id()) | 145 | if (!smp_processor_id()) |
| 138 | return 0; | 146 | return 0; |
| 139 | 147 | ||
| 140 | writel_relaxed(0, event_base + TIMER_ENABLE); | ||
| 141 | writel_relaxed(0, event_base + TIMER_CLEAR); | ||
| 142 | writel_relaxed(~0, event_base + TIMER_MATCH_VAL); | ||
| 143 | evt->irq = msm_clockevent.irq; | 148 | evt->irq = msm_clockevent.irq; |
| 144 | evt->name = "local_timer"; | 149 | evt->name = "local_timer"; |
| 145 | evt->features = msm_clockevent.features; | 150 | evt->features = msm_clockevent.features; |
| @@ -177,9 +182,6 @@ static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq, | |||
| 177 | struct clocksource *cs = &msm_clocksource; | 182 | struct clocksource *cs = &msm_clocksource; |
| 178 | int res; | 183 | int res; |
| 179 | 184 | ||
| 180 | writel_relaxed(0, event_base + TIMER_ENABLE); | ||
| 181 | writel_relaxed(0, event_base + TIMER_CLEAR); | ||
| 182 | writel_relaxed(~0, event_base + TIMER_MATCH_VAL); | ||
| 183 | ce->cpumask = cpumask_of(0); | 185 | ce->cpumask = cpumask_of(0); |
| 184 | ce->irq = irq; | 186 | ce->irq = irq; |
| 185 | 187 | ||
| @@ -217,13 +219,9 @@ err: | |||
| 217 | } | 219 | } |
| 218 | 220 | ||
| 219 | #ifdef CONFIG_OF | 221 | #ifdef CONFIG_OF |
| 220 | static const struct of_device_id msm_dgt_match[] __initconst = { | 222 | static const struct of_device_id msm_timer_match[] __initconst = { |
| 221 | { .compatible = "qcom,msm-dgt" }, | 223 | { .compatible = "qcom,kpss-timer" }, |
| 222 | { }, | 224 | { .compatible = "qcom,scss-timer" }, |
| 223 | }; | ||
| 224 | |||
| 225 | static const struct of_device_id msm_gpt_match[] __initconst = { | ||
| 226 | { .compatible = "qcom,msm-gpt" }, | ||
| 227 | { }, | 225 | { }, |
| 228 | }; | 226 | }; |
| 229 | 227 | ||
| @@ -234,33 +232,29 @@ void __init msm_dt_timer_init(void) | |||
| 234 | int irq; | 232 | int irq; |
| 235 | struct resource res; | 233 | struct resource res; |
| 236 | u32 percpu_offset; | 234 | u32 percpu_offset; |
| 237 | void __iomem *dgt_clk_ctl; | 235 | void __iomem *base; |
| 236 | void __iomem *cpu0_base; | ||
| 238 | 237 | ||
| 239 | np = of_find_matching_node(NULL, msm_gpt_match); | 238 | np = of_find_matching_node(NULL, msm_timer_match); |
| 240 | if (!np) { | 239 | if (!np) { |
| 241 | pr_err("Can't find GPT DT node\n"); | 240 | pr_err("Can't find msm timer DT node\n"); |
| 242 | return; | 241 | return; |
| 243 | } | 242 | } |
| 244 | 243 | ||
| 245 | event_base = of_iomap(np, 0); | 244 | base = of_iomap(np, 0); |
| 246 | if (!event_base) { | 245 | if (!base) { |
| 247 | pr_err("Failed to map event base\n"); | 246 | pr_err("Failed to map event base\n"); |
| 248 | return; | 247 | return; |
| 249 | } | 248 | } |
| 250 | 249 | ||
| 251 | irq = irq_of_parse_and_map(np, 0); | 250 | /* We use GPT0 for the clockevent */ |
| 251 | irq = irq_of_parse_and_map(np, 1); | ||
| 252 | if (irq <= 0) { | 252 | if (irq <= 0) { |
| 253 | pr_err("Can't get irq\n"); | 253 | pr_err("Can't get irq\n"); |
| 254 | return; | 254 | return; |
| 255 | } | 255 | } |
| 256 | of_node_put(np); | ||
| 257 | |||
| 258 | np = of_find_matching_node(NULL, msm_dgt_match); | ||
| 259 | if (!np) { | ||
| 260 | pr_err("Can't find DGT DT node\n"); | ||
| 261 | return; | ||
| 262 | } | ||
| 263 | 256 | ||
| 257 | /* We use CPU0's DGT for the clocksource */ | ||
| 264 | if (of_property_read_u32(np, "cpu-offset", &percpu_offset)) | 258 | if (of_property_read_u32(np, "cpu-offset", &percpu_offset)) |
| 265 | percpu_offset = 0; | 259 | percpu_offset = 0; |
| 266 | 260 | ||
| @@ -269,45 +263,43 @@ void __init msm_dt_timer_init(void) | |||
| 269 | return; | 263 | return; |
| 270 | } | 264 | } |
| 271 | 265 | ||
| 272 | source_base = ioremap(res.start + percpu_offset, resource_size(&res)); | 266 | cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res)); |
| 273 | if (!source_base) { | 267 | if (!cpu0_base) { |
| 274 | pr_err("Failed to map source base\n"); | 268 | pr_err("Failed to map source base\n"); |
| 275 | return; | 269 | return; |
| 276 | } | 270 | } |
| 277 | 271 | ||
| 278 | if (!of_address_to_resource(np, 1, &res)) { | ||
| 279 | dgt_clk_ctl = ioremap(res.start + percpu_offset, | ||
| 280 | resource_size(&res)); | ||
| 281 | if (!dgt_clk_ctl) { | ||
| 282 | pr_err("Failed to map DGT control base\n"); | ||
| 283 | return; | ||
| 284 | } | ||
| 285 | writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl); | ||
| 286 | iounmap(dgt_clk_ctl); | ||
| 287 | } | ||
| 288 | |||
| 289 | if (of_property_read_u32(np, "clock-frequency", &freq)) { | 272 | if (of_property_read_u32(np, "clock-frequency", &freq)) { |
| 290 | pr_err("Unknown frequency\n"); | 273 | pr_err("Unknown frequency\n"); |
| 291 | return; | 274 | return; |
| 292 | } | 275 | } |
| 293 | of_node_put(np); | 276 | of_node_put(np); |
| 294 | 277 | ||
| 278 | event_base = base + 0x4; | ||
| 279 | sts_base = base + 0x88; | ||
| 280 | source_base = cpu0_base + 0x24; | ||
| 281 | freq /= 4; | ||
| 282 | writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL); | ||
| 283 | |||
| 295 | msm_timer_init(freq, 32, irq, !!percpu_offset); | 284 | msm_timer_init(freq, 32, irq, !!percpu_offset); |
| 296 | } | 285 | } |
| 297 | #endif | 286 | #endif |
| 298 | 287 | ||
| 299 | static int __init msm_timer_map(phys_addr_t event, phys_addr_t source) | 288 | static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source, |
| 289 | u32 sts) | ||
| 300 | { | 290 | { |
| 301 | event_base = ioremap(event, SZ_64); | 291 | void __iomem *base; |
| 302 | if (!event_base) { | 292 | |
| 303 | pr_err("Failed to map event base\n"); | 293 | base = ioremap(addr, SZ_256); |
| 304 | return 1; | 294 | if (!base) { |
| 305 | } | 295 | pr_err("Failed to map timer base\n"); |
| 306 | source_base = ioremap(source, SZ_64); | 296 | return -ENOMEM; |
| 307 | if (!source_base) { | ||
| 308 | pr_err("Failed to map source base\n"); | ||
| 309 | return 1; | ||
| 310 | } | 297 | } |
| 298 | event_base = base + event; | ||
| 299 | source_base = base + source; | ||
| 300 | if (sts) | ||
| 301 | sts_base = base + sts; | ||
| 302 | |||
| 311 | return 0; | 303 | return 0; |
| 312 | } | 304 | } |
| 313 | 305 | ||
| @@ -315,7 +307,7 @@ void __init msm7x01_timer_init(void) | |||
| 315 | { | 307 | { |
| 316 | struct clocksource *cs = &msm_clocksource; | 308 | struct clocksource *cs = &msm_clocksource; |
| 317 | 309 | ||
| 318 | if (msm_timer_map(0xc0100000, 0xc0100010)) | 310 | if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0)) |
| 319 | return; | 311 | return; |
| 320 | cs->read = msm_read_timer_count_shift; | 312 | cs->read = msm_read_timer_count_shift; |
| 321 | cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)); | 313 | cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)); |
| @@ -326,14 +318,14 @@ void __init msm7x01_timer_init(void) | |||
| 326 | 318 | ||
| 327 | void __init msm7x30_timer_init(void) | 319 | void __init msm7x30_timer_init(void) |
| 328 | { | 320 | { |
| 329 | if (msm_timer_map(0xc0100004, 0xc0100024)) | 321 | if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80)) |
| 330 | return; | 322 | return; |
| 331 | msm_timer_init(24576000 / 4, 32, 1, false); | 323 | msm_timer_init(24576000 / 4, 32, 1, false); |
| 332 | } | 324 | } |
| 333 | 325 | ||
| 334 | void __init qsd8x50_timer_init(void) | 326 | void __init qsd8x50_timer_init(void) |
| 335 | { | 327 | { |
| 336 | if (msm_timer_map(0xAC100000, 0xAC100010)) | 328 | if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34)) |
| 337 | return; | 329 | return; |
| 338 | msm_timer_init(19200000 / 4, 32, 7, false); | 330 | msm_timer_init(19200000 / 4, 32, 7, false); |
| 339 | } | 331 | } |
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index ecc431909d6f..c4495a13751a 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig | |||
| @@ -3,6 +3,7 @@ if ARCH_MXS | |||
| 3 | config SOC_IMX23 | 3 | config SOC_IMX23 |
| 4 | bool | 4 | bool |
| 5 | select ARM_AMBA | 5 | select ARM_AMBA |
| 6 | select ARM_CPU_SUSPEND if PM | ||
| 6 | select CPU_ARM926T | 7 | select CPU_ARM926T |
| 7 | select HAVE_PWM | 8 | select HAVE_PWM |
| 8 | select PINCTRL_IMX23 | 9 | select PINCTRL_IMX23 |
| @@ -10,6 +11,7 @@ config SOC_IMX23 | |||
| 10 | config SOC_IMX28 | 11 | config SOC_IMX28 |
| 11 | bool | 12 | bool |
| 12 | select ARM_AMBA | 13 | select ARM_AMBA |
| 14 | select ARM_CPU_SUSPEND if PM | ||
| 13 | select CPU_ARM926T | 15 | select CPU_ARM926T |
| 14 | select HAVE_CAN_FLEXCAN if CAN | 16 | select HAVE_CAN_FLEXCAN if CAN |
| 15 | select HAVE_PWM | 17 | select HAVE_PWM |
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 4dc34ae6a857..5c27c4747469 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
| @@ -15,6 +15,7 @@ config ARCH_OMAP2PLUS | |||
| 15 | select OMAP_DM_TIMER | 15 | select OMAP_DM_TIMER |
| 16 | select PINCTRL | 16 | select PINCTRL |
| 17 | select PROC_DEVICETREE if PROC_FS | 17 | select PROC_DEVICETREE if PROC_FS |
| 18 | select SOC_BUS | ||
| 18 | select SPARSE_IRQ | 19 | select SPARSE_IRQ |
| 19 | select USE_OF | 20 | select USE_OF |
| 20 | help | 21 | help |
| @@ -99,6 +100,8 @@ config ARCH_OMAP4 | |||
| 99 | select PM_RUNTIME if CPU_IDLE | 100 | select PM_RUNTIME if CPU_IDLE |
| 100 | select USB_ARCH_HAS_EHCI if USB_SUPPORT | 101 | select USB_ARCH_HAS_EHCI if USB_SUPPORT |
| 101 | select COMMON_CLK | 102 | select COMMON_CLK |
| 103 | select ARM_ERRATA_754322 | ||
| 104 | select ARM_ERRATA_775420 | ||
| 102 | 105 | ||
| 103 | config SOC_OMAP5 | 106 | config SOC_OMAP5 |
| 104 | bool "TI OMAP5" | 107 | bool "TI OMAP5" |
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c index bda353b2f7d9..5e4b037bb24c 100644 --- a/arch/arm/mach-omap2/cclock2430_data.c +++ b/arch/arm/mach-omap2/cclock2430_data.c | |||
| @@ -1978,9 +1978,11 @@ static struct omap_clk omap2430_clks[] = { | |||
| 1978 | CLK(NULL, "sdrc_ick", &sdrc_ick), | 1978 | CLK(NULL, "sdrc_ick", &sdrc_ick), |
| 1979 | CLK(NULL, "des_ick", &des_ick), | 1979 | CLK(NULL, "des_ick", &des_ick), |
| 1980 | CLK("omap-sham", "ick", &sha_ick), | 1980 | CLK("omap-sham", "ick", &sha_ick), |
| 1981 | CLK("omap_rng", "ick", &rng_ick), | 1981 | CLK(NULL, "sha_ick", &sha_ick), |
| 1982 | CLK("omap_rng", "ick", &rng_ick), | ||
| 1982 | CLK(NULL, "rng_ick", &rng_ick), | 1983 | CLK(NULL, "rng_ick", &rng_ick), |
| 1983 | CLK("omap-aes", "ick", &aes_ick), | 1984 | CLK("omap-aes", "ick", &aes_ick), |
| 1985 | CLK(NULL, "aes_ick", &aes_ick), | ||
| 1984 | CLK(NULL, "pka_ick", &pka_ick), | 1986 | CLK(NULL, "pka_ick", &pka_ick), |
| 1985 | CLK(NULL, "usb_fck", &usb_fck), | 1987 | CLK(NULL, "usb_fck", &usb_fck), |
| 1986 | CLK("musb-omap2430", "ick", &usbhs_ick), | 1988 | CLK("musb-omap2430", "ick", &usbhs_ick), |
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index 332c6d3e55a9..6ebc7803bc3e 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c | |||
| @@ -413,6 +413,14 @@ static struct clk smartreflex1_fck; | |||
| 413 | DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL); | 413 | DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL); |
| 414 | DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null); | 414 | DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null); |
| 415 | 415 | ||
| 416 | static struct clk sha0_fck; | ||
| 417 | DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL); | ||
| 418 | DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null); | ||
| 419 | |||
| 420 | static struct clk aes0_fck; | ||
| 421 | DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL); | ||
| 422 | DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null); | ||
| 423 | |||
| 416 | /* | 424 | /* |
| 417 | * Modules clock nodes | 425 | * Modules clock nodes |
| 418 | * | 426 | * |
| @@ -878,6 +886,8 @@ static struct omap_clk am33xx_clks[] = { | |||
| 878 | CLK(NULL, "mmu_fck", &mmu_fck), | 886 | CLK(NULL, "mmu_fck", &mmu_fck), |
| 879 | CLK(NULL, "smartreflex0_fck", &smartreflex0_fck), | 887 | CLK(NULL, "smartreflex0_fck", &smartreflex0_fck), |
| 880 | CLK(NULL, "smartreflex1_fck", &smartreflex1_fck), | 888 | CLK(NULL, "smartreflex1_fck", &smartreflex1_fck), |
| 889 | CLK(NULL, "sha0_fck", &sha0_fck), | ||
| 890 | CLK(NULL, "aes0_fck", &aes0_fck), | ||
| 881 | CLK(NULL, "timer1_fck", &timer1_fck), | 891 | CLK(NULL, "timer1_fck", &timer1_fck), |
| 882 | CLK(NULL, "timer2_fck", &timer2_fck), | 892 | CLK(NULL, "timer2_fck", &timer2_fck), |
| 883 | CLK(NULL, "timer3_fck", &timer3_fck), | 893 | CLK(NULL, "timer3_fck", &timer3_fck), |
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c index 438d13341e23..45cd26430d1f 100644 --- a/arch/arm/mach-omap2/cclock3xxx_data.c +++ b/arch/arm/mach-omap2/cclock3xxx_data.c | |||
| @@ -3471,8 +3471,10 @@ static struct omap_clk omap3xxx_clks[] = { | |||
| 3471 | CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck), | 3471 | CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck), |
| 3472 | CLK(NULL, "init_60m_fclk", &dummy_ck), | 3472 | CLK(NULL, "init_60m_fclk", &dummy_ck), |
| 3473 | CLK(NULL, "gpt1_fck", &gpt1_fck), | 3473 | CLK(NULL, "gpt1_fck", &gpt1_fck), |
| 3474 | CLK(NULL, "aes2_ick", &aes2_ick), | ||
| 3474 | CLK(NULL, "wkup_32k_fck", &wkup_32k_fck), | 3475 | CLK(NULL, "wkup_32k_fck", &wkup_32k_fck), |
| 3475 | CLK(NULL, "gpio1_dbck", &gpio1_dbck), | 3476 | CLK(NULL, "gpio1_dbck", &gpio1_dbck), |
| 3477 | CLK(NULL, "sha12_ick", &sha12_ick), | ||
| 3476 | CLK(NULL, "wdt2_fck", &wdt2_fck), | 3478 | CLK(NULL, "wdt2_fck", &wdt2_fck), |
| 3477 | CLK("omap_wdt", "ick", &wdt2_ick), | 3479 | CLK("omap_wdt", "ick", &wdt2_ick), |
| 3478 | CLK(NULL, "wdt2_ick", &wdt2_ick), | 3480 | CLK(NULL, "wdt2_ick", &wdt2_ick), |
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 14522d077c88..df00e7580aa7 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h | |||
| @@ -110,6 +110,14 @@ void am35xx_init_late(void); | |||
| 110 | void ti81xx_init_late(void); | 110 | void ti81xx_init_late(void); |
| 111 | int omap2_common_pm_late_init(void); | 111 | int omap2_common_pm_late_init(void); |
| 112 | 112 | ||
| 113 | #ifdef CONFIG_SOC_BUS | ||
| 114 | void omap_soc_device_init(void); | ||
| 115 | #else | ||
| 116 | static inline void omap_soc_device_init(void) | ||
| 117 | { | ||
| 118 | } | ||
| 119 | #endif | ||
| 120 | |||
| 113 | #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) | 121 | #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) |
| 114 | void omap2xxx_restart(char mode, const char *cmd); | 122 | void omap2xxx_restart(char mode, const char *cmd); |
| 115 | #else | 123 | #else |
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 1ec7f0597710..4269fc145698 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c | |||
| @@ -504,140 +504,31 @@ static void omap_init_rng(void) | |||
| 504 | WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n"); | 504 | WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n"); |
| 505 | } | 505 | } |
| 506 | 506 | ||
| 507 | #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE) | 507 | static void __init omap_init_sham(void) |
| 508 | |||
| 509 | #ifdef CONFIG_ARCH_OMAP2 | ||
| 510 | static struct resource omap2_sham_resources[] = { | ||
| 511 | { | ||
| 512 | .start = OMAP24XX_SEC_SHA1MD5_BASE, | ||
| 513 | .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64, | ||
| 514 | .flags = IORESOURCE_MEM, | ||
| 515 | }, | ||
| 516 | { | ||
| 517 | .start = 51 + OMAP_INTC_START, | ||
| 518 | .flags = IORESOURCE_IRQ, | ||
| 519 | } | ||
| 520 | }; | ||
| 521 | static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources); | ||
| 522 | #else | ||
| 523 | #define omap2_sham_resources NULL | ||
| 524 | #define omap2_sham_resources_sz 0 | ||
| 525 | #endif | ||
| 526 | |||
| 527 | #ifdef CONFIG_ARCH_OMAP3 | ||
| 528 | static struct resource omap3_sham_resources[] = { | ||
| 529 | { | ||
| 530 | .start = OMAP34XX_SEC_SHA1MD5_BASE, | ||
| 531 | .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64, | ||
| 532 | .flags = IORESOURCE_MEM, | ||
| 533 | }, | ||
| 534 | { | ||
| 535 | .start = 49 + OMAP_INTC_START, | ||
| 536 | .flags = IORESOURCE_IRQ, | ||
| 537 | }, | ||
| 538 | { | ||
| 539 | .start = OMAP34XX_DMA_SHA1MD5_RX, | ||
| 540 | .flags = IORESOURCE_DMA, | ||
| 541 | } | ||
| 542 | }; | ||
| 543 | static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources); | ||
| 544 | #else | ||
| 545 | #define omap3_sham_resources NULL | ||
| 546 | #define omap3_sham_resources_sz 0 | ||
| 547 | #endif | ||
| 548 | |||
| 549 | static struct platform_device sham_device = { | ||
| 550 | .name = "omap-sham", | ||
| 551 | .id = -1, | ||
| 552 | }; | ||
| 553 | |||
| 554 | static void omap_init_sham(void) | ||
| 555 | { | 508 | { |
| 556 | if (cpu_is_omap24xx()) { | 509 | struct omap_hwmod *oh; |
| 557 | sham_device.resource = omap2_sham_resources; | 510 | struct platform_device *pdev; |
| 558 | sham_device.num_resources = omap2_sham_resources_sz; | ||
| 559 | } else if (cpu_is_omap34xx()) { | ||
| 560 | sham_device.resource = omap3_sham_resources; | ||
| 561 | sham_device.num_resources = omap3_sham_resources_sz; | ||
| 562 | } else { | ||
| 563 | pr_err("%s: platform not supported\n", __func__); | ||
| 564 | return; | ||
| 565 | } | ||
| 566 | platform_device_register(&sham_device); | ||
| 567 | } | ||
| 568 | #else | ||
| 569 | static inline void omap_init_sham(void) { } | ||
| 570 | #endif | ||
| 571 | |||
| 572 | #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE) | ||
| 573 | |||
| 574 | #ifdef CONFIG_ARCH_OMAP2 | ||
| 575 | static struct resource omap2_aes_resources[] = { | ||
| 576 | { | ||
| 577 | .start = OMAP24XX_SEC_AES_BASE, | ||
| 578 | .end = OMAP24XX_SEC_AES_BASE + 0x4C, | ||
| 579 | .flags = IORESOURCE_MEM, | ||
| 580 | }, | ||
| 581 | { | ||
| 582 | .start = OMAP24XX_DMA_AES_TX, | ||
| 583 | .flags = IORESOURCE_DMA, | ||
| 584 | }, | ||
| 585 | { | ||
| 586 | .start = OMAP24XX_DMA_AES_RX, | ||
| 587 | .flags = IORESOURCE_DMA, | ||
| 588 | } | ||
| 589 | }; | ||
| 590 | static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources); | ||
| 591 | #else | ||
| 592 | #define omap2_aes_resources NULL | ||
| 593 | #define omap2_aes_resources_sz 0 | ||
| 594 | #endif | ||
| 595 | 511 | ||
| 596 | #ifdef CONFIG_ARCH_OMAP3 | 512 | oh = omap_hwmod_lookup("sham"); |
| 597 | static struct resource omap3_aes_resources[] = { | 513 | if (!oh) |
| 598 | { | 514 | return; |
| 599 | .start = OMAP34XX_SEC_AES_BASE, | ||
| 600 | .end = OMAP34XX_SEC_AES_BASE + 0x4C, | ||
| 601 | .flags = IORESOURCE_MEM, | ||
| 602 | }, | ||
| 603 | { | ||
| 604 | .start = OMAP34XX_DMA_AES2_TX, | ||
| 605 | .flags = IORESOURCE_DMA, | ||
| 606 | }, | ||
| 607 | { | ||
| 608 | .start = OMAP34XX_DMA_AES2_RX, | ||
| 609 | .flags = IORESOURCE_DMA, | ||
| 610 | } | ||
| 611 | }; | ||
| 612 | static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources); | ||
| 613 | #else | ||
| 614 | #define omap3_aes_resources NULL | ||
| 615 | #define omap3_aes_resources_sz 0 | ||
| 616 | #endif | ||
| 617 | 515 | ||
| 618 | static struct platform_device aes_device = { | 516 | pdev = omap_device_build("omap-sham", -1, oh, NULL, 0); |
| 619 | .name = "omap-aes", | 517 | WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n"); |
| 620 | .id = -1, | 518 | } |
| 621 | }; | ||
| 622 | 519 | ||
| 623 | static void omap_init_aes(void) | 520 | static void __init omap_init_aes(void) |
| 624 | { | 521 | { |
| 625 | if (cpu_is_omap24xx()) { | 522 | struct omap_hwmod *oh; |
| 626 | aes_device.resource = omap2_aes_resources; | 523 | struct platform_device *pdev; |
| 627 | aes_device.num_resources = omap2_aes_resources_sz; | 524 | |
| 628 | } else if (cpu_is_omap34xx()) { | 525 | oh = omap_hwmod_lookup("aes"); |
| 629 | aes_device.resource = omap3_aes_resources; | 526 | if (!oh) |
| 630 | aes_device.num_resources = omap3_aes_resources_sz; | ||
| 631 | } else { | ||
| 632 | pr_err("%s: platform not supported\n", __func__); | ||
| 633 | return; | 527 | return; |
| 634 | } | ||
| 635 | platform_device_register(&aes_device); | ||
| 636 | } | ||
| 637 | 528 | ||
| 638 | #else | 529 | pdev = omap_device_build("omap-aes", -1, oh, NULL, 0); |
| 639 | static inline void omap_init_aes(void) { } | 530 | WARN(IS_ERR(pdev), "Can't build omap_device for omap-aes\n"); |
| 640 | #endif | 531 | } |
| 641 | 532 | ||
| 642 | /*-------------------------------------------------------------------------*/ | 533 | /*-------------------------------------------------------------------------*/ |
| 643 | 534 | ||
| @@ -764,11 +655,11 @@ static int __init omap2_init_devices(void) | |||
| 764 | omap_init_dmic(); | 655 | omap_init_dmic(); |
| 765 | omap_init_mcpdm(); | 656 | omap_init_mcpdm(); |
| 766 | omap_init_mcspi(); | 657 | omap_init_mcspi(); |
| 658 | omap_init_sham(); | ||
| 659 | omap_init_aes(); | ||
| 767 | } | 660 | } |
| 768 | omap_init_sti(); | 661 | omap_init_sti(); |
| 769 | omap_init_rng(); | 662 | omap_init_rng(); |
| 770 | omap_init_sham(); | ||
| 771 | omap_init_aes(); | ||
| 772 | omap_init_vout(); | 663 | omap_init_vout(); |
| 773 | omap_init_ocp2scp(); | 664 | omap_init_ocp2scp(); |
| 774 | 665 | ||
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index ff0bc9e51aa7..2fb17caa8683 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c | |||
| @@ -18,6 +18,11 @@ | |||
| 18 | #include <linux/kernel.h> | 18 | #include <linux/kernel.h> |
| 19 | #include <linux/init.h> | 19 | #include <linux/init.h> |
| 20 | #include <linux/io.h> | 20 | #include <linux/io.h> |
| 21 | #include <linux/slab.h> | ||
| 22 | |||
| 23 | #ifdef CONFIG_SOC_BUS | ||
| 24 | #include <linux/sys_soc.h> | ||
| 25 | #endif | ||
| 21 | 26 | ||
| 22 | #include <asm/cputype.h> | 27 | #include <asm/cputype.h> |
| 23 | 28 | ||
| @@ -31,8 +36,11 @@ | |||
| 31 | #define OMAP4_SILICON_TYPE_STANDARD 0x01 | 36 | #define OMAP4_SILICON_TYPE_STANDARD 0x01 |
| 32 | #define OMAP4_SILICON_TYPE_PERFORMANCE 0x02 | 37 | #define OMAP4_SILICON_TYPE_PERFORMANCE 0x02 |
| 33 | 38 | ||
| 39 | #define OMAP_SOC_MAX_NAME_LENGTH 16 | ||
| 40 | |||
| 34 | static unsigned int omap_revision; | 41 | static unsigned int omap_revision; |
| 35 | static const char *cpu_rev; | 42 | static char soc_name[OMAP_SOC_MAX_NAME_LENGTH]; |
| 43 | static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH]; | ||
| 36 | u32 omap_features; | 44 | u32 omap_features; |
| 37 | 45 | ||
| 38 | unsigned int omap_rev(void) | 46 | unsigned int omap_rev(void) |
| @@ -169,9 +177,12 @@ void __init omap2xxx_check_revision(void) | |||
| 169 | j = i; | 177 | j = i; |
| 170 | } | 178 | } |
| 171 | 179 | ||
| 172 | pr_info("OMAP%04x", omap_rev() >> 16); | 180 | sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); |
| 181 | sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf); | ||
| 182 | |||
| 183 | pr_info("%s", soc_name); | ||
| 173 | if ((omap_rev() >> 8) & 0x0f) | 184 | if ((omap_rev() >> 8) & 0x0f) |
| 174 | pr_info("ES%x", (omap_rev() >> 12) & 0xf); | 185 | pr_info("%s", soc_rev); |
| 175 | pr_info("\n"); | 186 | pr_info("\n"); |
| 176 | } | 187 | } |
| 177 | 188 | ||
| @@ -211,8 +222,10 @@ static void __init omap3_cpuinfo(void) | |||
| 211 | cpu_name = "OMAP3503"; | 222 | cpu_name = "OMAP3503"; |
| 212 | } | 223 | } |
| 213 | 224 | ||
| 225 | sprintf(soc_name, "%s", cpu_name); | ||
| 226 | |||
| 214 | /* Print verbose information */ | 227 | /* Print verbose information */ |
| 215 | pr_info("%s ES%s (", cpu_name, cpu_rev); | 228 | pr_info("%s %s (", soc_name, soc_rev); |
| 216 | 229 | ||
| 217 | OMAP3_SHOW_FEATURE(l2cache); | 230 | OMAP3_SHOW_FEATURE(l2cache); |
| 218 | OMAP3_SHOW_FEATURE(iva); | 231 | OMAP3_SHOW_FEATURE(iva); |
| @@ -291,6 +304,7 @@ void __init ti81xx_check_features(void) | |||
| 291 | 304 | ||
| 292 | void __init omap3xxx_check_revision(void) | 305 | void __init omap3xxx_check_revision(void) |
| 293 | { | 306 | { |
| 307 | const char *cpu_rev; | ||
| 294 | u32 cpuid, idcode; | 308 | u32 cpuid, idcode; |
| 295 | u16 hawkeye; | 309 | u16 hawkeye; |
| 296 | u8 rev; | 310 | u8 rev; |
| @@ -438,6 +452,7 @@ void __init omap3xxx_check_revision(void) | |||
| 438 | cpu_rev = "1.2"; | 452 | cpu_rev = "1.2"; |
| 439 | pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n"); | 453 | pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n"); |
| 440 | } | 454 | } |
| 455 | sprintf(soc_rev, "ES%s", cpu_rev); | ||
| 441 | } | 456 | } |
| 442 | 457 | ||
| 443 | void __init omap4xxx_check_revision(void) | 458 | void __init omap4xxx_check_revision(void) |
| @@ -512,8 +527,10 @@ void __init omap4xxx_check_revision(void) | |||
| 512 | omap_revision = OMAP4430_REV_ES2_3; | 527 | omap_revision = OMAP4430_REV_ES2_3; |
| 513 | } | 528 | } |
| 514 | 529 | ||
| 515 | pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16, | 530 | sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); |
| 516 | ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf)); | 531 | sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf, |
| 532 | (omap_rev() >> 8) & 0xf); | ||
| 533 | pr_info("%s %s\n", soc_name, soc_rev); | ||
| 517 | } | 534 | } |
| 518 | 535 | ||
| 519 | void __init omap5xxx_check_revision(void) | 536 | void __init omap5xxx_check_revision(void) |
| @@ -553,8 +570,10 @@ void __init omap5xxx_check_revision(void) | |||
| 553 | omap_revision = OMAP5430_REV_ES2_0; | 570 | omap_revision = OMAP5430_REV_ES2_0; |
| 554 | } | 571 | } |
| 555 | 572 | ||
| 556 | pr_info("OMAP%04x ES%d.0\n", | 573 | sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); |
| 557 | omap_rev() >> 16, ((omap_rev() >> 12) & 0xf)); | 574 | sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf); |
| 575 | |||
| 576 | pr_info("%s %s\n", soc_name, soc_rev); | ||
| 558 | } | 577 | } |
| 559 | 578 | ||
| 560 | /* | 579 | /* |
| @@ -575,3 +594,63 @@ void __init omap2_set_globals_tap(u32 class, void __iomem *tap) | |||
| 575 | else | 594 | else |
| 576 | tap_prod_id = 0x0208; | 595 | tap_prod_id = 0x0208; |
| 577 | } | 596 | } |
| 597 | |||
| 598 | #ifdef CONFIG_SOC_BUS | ||
| 599 | |||
| 600 | static const char const *omap_types[] = { | ||
| 601 | [OMAP2_DEVICE_TYPE_TEST] = "TST", | ||
| 602 | [OMAP2_DEVICE_TYPE_EMU] = "EMU", | ||
| 603 | [OMAP2_DEVICE_TYPE_SEC] = "HS", | ||
| 604 | [OMAP2_DEVICE_TYPE_GP] = "GP", | ||
| 605 | [OMAP2_DEVICE_TYPE_BAD] = "BAD", | ||
| 606 | }; | ||
| 607 | |||
| 608 | static const char * __init omap_get_family(void) | ||
| 609 | { | ||
| 610 | if (cpu_is_omap24xx()) | ||
| 611 | return kasprintf(GFP_KERNEL, "OMAP2"); | ||
| 612 | else if (cpu_is_omap34xx()) | ||
| 613 | return kasprintf(GFP_KERNEL, "OMAP3"); | ||
| 614 | else if (cpu_is_omap44xx()) | ||
| 615 | return kasprintf(GFP_KERNEL, "OMAP4"); | ||
| 616 | else if (soc_is_omap54xx()) | ||
| 617 | return kasprintf(GFP_KERNEL, "OMAP5"); | ||
| 618 | else | ||
| 619 | return kasprintf(GFP_KERNEL, "Unknown"); | ||
| 620 | } | ||
| 621 | |||
| 622 | static ssize_t omap_get_type(struct device *dev, | ||
| 623 | struct device_attribute *attr, | ||
| 624 | char *buf) | ||
| 625 | { | ||
| 626 | return sprintf(buf, "%s\n", omap_types[omap_type()]); | ||
| 627 | } | ||
| 628 | |||
| 629 | static struct device_attribute omap_soc_attr = | ||
| 630 | __ATTR(type, S_IRUGO, omap_get_type, NULL); | ||
| 631 | |||
| 632 | void __init omap_soc_device_init(void) | ||
| 633 | { | ||
| 634 | struct device *parent; | ||
| 635 | struct soc_device *soc_dev; | ||
| 636 | struct soc_device_attribute *soc_dev_attr; | ||
| 637 | |||
| 638 | soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); | ||
| 639 | if (!soc_dev_attr) | ||
| 640 | return; | ||
| 641 | |||
| 642 | soc_dev_attr->machine = soc_name; | ||
| 643 | soc_dev_attr->family = omap_get_family(); | ||
| 644 | soc_dev_attr->revision = soc_rev; | ||
| 645 | |||
| 646 | soc_dev = soc_device_register(soc_dev_attr); | ||
| 647 | if (IS_ERR_OR_NULL(soc_dev)) { | ||
| 648 | kfree(soc_dev_attr); | ||
| 649 | return; | ||
| 650 | } | ||
| 651 | |||
| 652 | parent = soc_device_to_device(soc_dev); | ||
| 653 | if (!IS_ERR_OR_NULL(parent)) | ||
| 654 | device_create_file(parent, &omap_soc_attr); | ||
| 655 | } | ||
| 656 | #endif /* CONFIG_SOC_BUS */ | ||
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index e210fa830f8d..09abf99e9e57 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
| @@ -394,6 +394,13 @@ static void __init omap_hwmod_init_postsetup(void) | |||
| 394 | omap_pm_if_early_init(); | 394 | omap_pm_if_early_init(); |
| 395 | } | 395 | } |
| 396 | 396 | ||
| 397 | static void __init omap_common_late_init(void) | ||
| 398 | { | ||
| 399 | omap_mux_late_init(); | ||
| 400 | omap2_common_pm_late_init(); | ||
| 401 | omap_soc_device_init(); | ||
| 402 | } | ||
| 403 | |||
| 397 | #ifdef CONFIG_SOC_OMAP2420 | 404 | #ifdef CONFIG_SOC_OMAP2420 |
| 398 | void __init omap2420_init_early(void) | 405 | void __init omap2420_init_early(void) |
| 399 | { | 406 | { |
| @@ -417,8 +424,7 @@ void __init omap2420_init_early(void) | |||
| 417 | 424 | ||
| 418 | void __init omap2420_init_late(void) | 425 | void __init omap2420_init_late(void) |
| 419 | { | 426 | { |
| 420 | omap_mux_late_init(); | 427 | omap_common_late_init(); |
| 421 | omap2_common_pm_late_init(); | ||
| 422 | omap2_pm_init(); | 428 | omap2_pm_init(); |
| 423 | omap2_clk_enable_autoidle_all(); | 429 | omap2_clk_enable_autoidle_all(); |
| 424 | } | 430 | } |
| @@ -447,8 +453,7 @@ void __init omap2430_init_early(void) | |||
| 447 | 453 | ||
| 448 | void __init omap2430_init_late(void) | 454 | void __init omap2430_init_late(void) |
| 449 | { | 455 | { |
| 450 | omap_mux_late_init(); | 456 | omap_common_late_init(); |
| 451 | omap2_common_pm_late_init(); | ||
| 452 | omap2_pm_init(); | 457 | omap2_pm_init(); |
| 453 | omap2_clk_enable_autoidle_all(); | 458 | omap2_clk_enable_autoidle_all(); |
| 454 | } | 459 | } |
| @@ -520,48 +525,42 @@ void __init ti81xx_init_early(void) | |||
| 520 | 525 | ||
| 521 | void __init omap3_init_late(void) | 526 | void __init omap3_init_late(void) |
| 522 | { | 527 | { |
| 523 | omap_mux_late_init(); | 528 | omap_common_late_init(); |
| 524 | omap2_common_pm_late_init(); | ||
| 525 | omap3_pm_init(); | 529 | omap3_pm_init(); |
| 526 | omap2_clk_enable_autoidle_all(); | 530 | omap2_clk_enable_autoidle_all(); |
| 527 | } | 531 | } |
| 528 | 532 | ||
| 529 | void __init omap3430_init_late(void) | 533 | void __init omap3430_init_late(void) |
| 530 | { | 534 | { |
| 531 | omap_mux_late_init(); | 535 | omap_common_late_init(); |
| 532 | omap2_common_pm_late_init(); | ||
| 533 | omap3_pm_init(); | 536 | omap3_pm_init(); |
| 534 | omap2_clk_enable_autoidle_all(); | 537 | omap2_clk_enable_autoidle_all(); |
| 535 | } | 538 | } |
| 536 | 539 | ||
| 537 | void __init omap35xx_init_late(void) | 540 | void __init omap35xx_init_late(void) |
| 538 | { | 541 | { |
| 539 | omap_mux_late_init(); | 542 | omap_common_late_init(); |
| 540 | omap2_common_pm_late_init(); | ||
| 541 | omap3_pm_init(); | 543 | omap3_pm_init(); |
| 542 | omap2_clk_enable_autoidle_all(); | 544 | omap2_clk_enable_autoidle_all(); |
| 543 | } | 545 | } |
| 544 | 546 | ||
| 545 | void __init omap3630_init_late(void) | 547 | void __init omap3630_init_late(void) |
| 546 | { | 548 | { |
| 547 | omap_mux_late_init(); | 549 | omap_common_late_init(); |
| 548 | omap2_common_pm_late_init(); | ||
| 549 | omap3_pm_init(); | 550 | omap3_pm_init(); |
| 550 | omap2_clk_enable_autoidle_all(); | 551 | omap2_clk_enable_autoidle_all(); |
| 551 | } | 552 | } |
| 552 | 553 | ||
| 553 | void __init am35xx_init_late(void) | 554 | void __init am35xx_init_late(void) |
| 554 | { | 555 | { |
| 555 | omap_mux_late_init(); | 556 | omap_common_late_init(); |
| 556 | omap2_common_pm_late_init(); | ||
| 557 | omap3_pm_init(); | 557 | omap3_pm_init(); |
| 558 | omap2_clk_enable_autoidle_all(); | 558 | omap2_clk_enable_autoidle_all(); |
| 559 | } | 559 | } |
| 560 | 560 | ||
| 561 | void __init ti81xx_init_late(void) | 561 | void __init ti81xx_init_late(void) |
| 562 | { | 562 | { |
| 563 | omap_mux_late_init(); | 563 | omap_common_late_init(); |
| 564 | omap2_common_pm_late_init(); | ||
| 565 | omap3_pm_init(); | 564 | omap3_pm_init(); |
| 566 | omap2_clk_enable_autoidle_all(); | 565 | omap2_clk_enable_autoidle_all(); |
| 567 | } | 566 | } |
| @@ -613,8 +612,7 @@ void __init omap4430_init_early(void) | |||
| 613 | 612 | ||
| 614 | void __init omap4430_init_late(void) | 613 | void __init omap4430_init_late(void) |
| 615 | { | 614 | { |
| 616 | omap_mux_late_init(); | 615 | omap_common_late_init(); |
| 617 | omap2_common_pm_late_init(); | ||
| 618 | omap4_pm_init(); | 616 | omap4_pm_init(); |
| 619 | omap2_clk_enable_autoidle_all(); | 617 | omap2_clk_enable_autoidle_all(); |
| 620 | } | 618 | } |
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 6a764af6c6d3..5137cc84b504 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c | |||
| @@ -610,6 +610,8 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { | |||
| 610 | &omap2420_l4_core__mcbsp2, | 610 | &omap2420_l4_core__mcbsp2, |
| 611 | &omap2420_l4_core__msdi1, | 611 | &omap2420_l4_core__msdi1, |
| 612 | &omap2xxx_l4_core__rng, | 612 | &omap2xxx_l4_core__rng, |
| 613 | &omap2xxx_l4_core__sham, | ||
| 614 | &omap2xxx_l4_core__aes, | ||
| 613 | &omap2420_l4_core__hdq1w, | 615 | &omap2420_l4_core__hdq1w, |
| 614 | &omap2420_l4_wkup__counter_32k, | 616 | &omap2420_l4_wkup__counter_32k, |
| 615 | &omap2420_l3__gpmc, | 617 | &omap2420_l3__gpmc, |
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index d2d3840557c3..4ce999ee3ee9 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c | |||
| @@ -963,6 +963,8 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { | |||
| 963 | &omap2430_l4_core__mcbsp5, | 963 | &omap2430_l4_core__mcbsp5, |
| 964 | &omap2430_l4_core__hdq1w, | 964 | &omap2430_l4_core__hdq1w, |
| 965 | &omap2xxx_l4_core__rng, | 965 | &omap2xxx_l4_core__rng, |
| 966 | &omap2xxx_l4_core__sham, | ||
| 967 | &omap2xxx_l4_core__aes, | ||
| 966 | &omap2430_l4_wkup__counter_32k, | 968 | &omap2430_l4_wkup__counter_32k, |
| 967 | &omap2430_l3__gpmc, | 969 | &omap2430_l3__gpmc, |
| 968 | NULL, | 970 | NULL, |
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c index 47901a5e76de..5fd40d4a989e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c | |||
| @@ -138,6 +138,24 @@ static struct omap_hwmod_addr_space omap2_rng_addr_space[] = { | |||
| 138 | { } | 138 | { } |
| 139 | }; | 139 | }; |
| 140 | 140 | ||
| 141 | static struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = { | ||
| 142 | { | ||
| 143 | .pa_start = 0x480a4000, | ||
| 144 | .pa_end = 0x480a4000 + 0x64 - 1, | ||
| 145 | .flags = ADDR_TYPE_RT | ||
| 146 | }, | ||
| 147 | { } | ||
| 148 | }; | ||
| 149 | |||
| 150 | static struct omap_hwmod_addr_space omap2xxx_aes_addrs[] = { | ||
| 151 | { | ||
| 152 | .pa_start = 0x480a6000, | ||
| 153 | .pa_end = 0x480a6000 + 0x50 - 1, | ||
| 154 | .flags = ADDR_TYPE_RT | ||
| 155 | }, | ||
| 156 | { } | ||
| 157 | }; | ||
| 158 | |||
| 141 | /* | 159 | /* |
| 142 | * Common interconnect data | 160 | * Common interconnect data |
| 143 | */ | 161 | */ |
| @@ -389,3 +407,21 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = { | |||
| 389 | .addr = omap2_rng_addr_space, | 407 | .addr = omap2_rng_addr_space, |
| 390 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 408 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 391 | }; | 409 | }; |
| 410 | |||
| 411 | /* l4 core -> sham interface */ | ||
| 412 | struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = { | ||
| 413 | .master = &omap2xxx_l4_core_hwmod, | ||
| 414 | .slave = &omap2xxx_sham_hwmod, | ||
| 415 | .clk = "sha_ick", | ||
| 416 | .addr = omap2xxx_sham_addrs, | ||
| 417 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 418 | }; | ||
| 419 | |||
| 420 | /* l4 core -> aes interface */ | ||
| 421 | struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = { | ||
| 422 | .master = &omap2xxx_l4_core_hwmod, | ||
| 423 | .slave = &omap2xxx_aes_hwmod, | ||
| 424 | .clk = "aes_ick", | ||
| 425 | .addr = omap2xxx_aes_addrs, | ||
| 426 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 427 | }; | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index e596117004d4..c8c64b3e1acc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | |||
| @@ -864,3 +864,84 @@ struct omap_hwmod omap2xxx_rng_hwmod = { | |||
| 864 | .flags = HWMOD_INIT_NO_RESET, | 864 | .flags = HWMOD_INIT_NO_RESET, |
| 865 | .class = &omap2_rng_hwmod_class, | 865 | .class = &omap2_rng_hwmod_class, |
| 866 | }; | 866 | }; |
| 867 | |||
| 868 | /* SHAM */ | ||
| 869 | |||
| 870 | static struct omap_hwmod_class_sysconfig omap2_sham_sysc = { | ||
| 871 | .rev_offs = 0x5c, | ||
| 872 | .sysc_offs = 0x60, | ||
| 873 | .syss_offs = 0x64, | ||
| 874 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | ||
| 875 | SYSS_HAS_RESET_STATUS), | ||
| 876 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 877 | }; | ||
| 878 | |||
| 879 | static struct omap_hwmod_class omap2xxx_sham_class = { | ||
| 880 | .name = "sham", | ||
| 881 | .sysc = &omap2_sham_sysc, | ||
| 882 | }; | ||
| 883 | |||
| 884 | static struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = { | ||
| 885 | { .irq = 51 + OMAP_INTC_START, }, | ||
| 886 | { .irq = -1 } | ||
| 887 | }; | ||
| 888 | |||
| 889 | static struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = { | ||
| 890 | { .name = "rx", .dma_req = 13 }, | ||
| 891 | { .dma_req = -1 } | ||
| 892 | }; | ||
| 893 | |||
| 894 | struct omap_hwmod omap2xxx_sham_hwmod = { | ||
| 895 | .name = "sham", | ||
| 896 | .mpu_irqs = omap2_sham_mpu_irqs, | ||
| 897 | .sdma_reqs = omap2_sham_sdma_chs, | ||
| 898 | .main_clk = "l4_ck", | ||
| 899 | .prcm = { | ||
| 900 | .omap2 = { | ||
| 901 | .module_offs = CORE_MOD, | ||
| 902 | .prcm_reg_id = 4, | ||
| 903 | .module_bit = OMAP24XX_EN_SHA_SHIFT, | ||
| 904 | .idlest_reg_id = 4, | ||
| 905 | .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT, | ||
| 906 | }, | ||
| 907 | }, | ||
| 908 | .class = &omap2xxx_sham_class, | ||
| 909 | }; | ||
| 910 | |||
| 911 | /* AES */ | ||
| 912 | |||
| 913 | static struct omap_hwmod_class_sysconfig omap2_aes_sysc = { | ||
| 914 | .rev_offs = 0x44, | ||
| 915 | .sysc_offs = 0x48, | ||
| 916 | .syss_offs = 0x4c, | ||
| 917 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | ||
| 918 | SYSS_HAS_RESET_STATUS), | ||
| 919 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 920 | }; | ||
| 921 | |||
| 922 | static struct omap_hwmod_class omap2xxx_aes_class = { | ||
| 923 | .name = "aes", | ||
| 924 | .sysc = &omap2_aes_sysc, | ||
| 925 | }; | ||
| 926 | |||
| 927 | static struct omap_hwmod_dma_info omap2_aes_sdma_chs[] = { | ||
| 928 | { .name = "tx", .dma_req = 9 }, | ||
| 929 | { .name = "rx", .dma_req = 10 }, | ||
| 930 | { .dma_req = -1 } | ||
| 931 | }; | ||
| 932 | |||
| 933 | struct omap_hwmod omap2xxx_aes_hwmod = { | ||
| 934 | .name = "aes", | ||
| 935 | .sdma_reqs = omap2_aes_sdma_chs, | ||
| 936 | .main_clk = "l4_ck", | ||
| 937 | .prcm = { | ||
| 938 | .omap2 = { | ||
| 939 | .module_offs = CORE_MOD, | ||
| 940 | .prcm_reg_id = 4, | ||
| 941 | .module_bit = OMAP24XX_EN_AES_SHIFT, | ||
| 942 | .idlest_reg_id = 4, | ||
| 943 | .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT, | ||
| 944 | }, | ||
| 945 | }, | ||
| 946 | .class = &omap2xxx_aes_class, | ||
| 947 | }; | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 31bea1ce3de1..01d8f324450a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c | |||
| @@ -418,8 +418,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = { | |||
| 418 | * - clkdiv32k | 418 | * - clkdiv32k |
| 419 | * - debugss | 419 | * - debugss |
| 420 | * - ocp watch point | 420 | * - ocp watch point |
| 421 | * - aes0 | ||
| 422 | * - sha0 | ||
| 423 | */ | 421 | */ |
| 424 | #if 0 | 422 | #if 0 |
| 425 | /* | 423 | /* |
| @@ -500,25 +498,41 @@ static struct omap_hwmod am33xx_ocpwp_hwmod = { | |||
| 500 | }, | 498 | }, |
| 501 | }, | 499 | }, |
| 502 | }; | 500 | }; |
| 501 | #endif | ||
| 503 | 502 | ||
| 504 | /* | 503 | /* |
| 505 | * 'aes' class | 504 | * 'aes0' class |
| 506 | */ | 505 | */ |
| 507 | static struct omap_hwmod_class am33xx_aes_hwmod_class = { | 506 | static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = { |
| 508 | .name = "aes", | 507 | .rev_offs = 0x80, |
| 508 | .sysc_offs = 0x84, | ||
| 509 | .syss_offs = 0x88, | ||
| 510 | .sysc_flags = SYSS_HAS_RESET_STATUS, | ||
| 511 | }; | ||
| 512 | |||
| 513 | static struct omap_hwmod_class am33xx_aes0_hwmod_class = { | ||
| 514 | .name = "aes0", | ||
| 515 | .sysc = &am33xx_aes0_sysc, | ||
| 509 | }; | 516 | }; |
| 510 | 517 | ||
| 511 | static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = { | 518 | static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = { |
| 512 | { .irq = 102 + OMAP_INTC_START, }, | 519 | { .irq = 103 + OMAP_INTC_START, }, |
| 513 | { .irq = -1 }, | 520 | { .irq = -1 }, |
| 514 | }; | 521 | }; |
| 515 | 522 | ||
| 523 | static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = { | ||
| 524 | { .name = "tx", .dma_req = 6, }, | ||
| 525 | { .name = "rx", .dma_req = 5, }, | ||
| 526 | { .dma_req = -1 } | ||
| 527 | }; | ||
| 528 | |||
| 516 | static struct omap_hwmod am33xx_aes0_hwmod = { | 529 | static struct omap_hwmod am33xx_aes0_hwmod = { |
| 517 | .name = "aes0", | 530 | .name = "aes", |
| 518 | .class = &am33xx_aes_hwmod_class, | 531 | .class = &am33xx_aes0_hwmod_class, |
| 519 | .clkdm_name = "l3_clkdm", | 532 | .clkdm_name = "l3_clkdm", |
| 520 | .mpu_irqs = am33xx_aes0_irqs, | 533 | .mpu_irqs = am33xx_aes0_irqs, |
| 521 | .main_clk = "l3_gclk", | 534 | .sdma_reqs = am33xx_aes0_edma_reqs, |
| 535 | .main_clk = "aes0_fck", | ||
| 522 | .prcm = { | 536 | .prcm = { |
| 523 | .omap4 = { | 537 | .omap4 = { |
| 524 | .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET, | 538 | .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET, |
| @@ -527,21 +541,35 @@ static struct omap_hwmod am33xx_aes0_hwmod = { | |||
| 527 | }, | 541 | }, |
| 528 | }; | 542 | }; |
| 529 | 543 | ||
| 530 | /* sha0 */ | 544 | /* sha0 HIB2 (the 'P' (public) device) */ |
| 545 | static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = { | ||
| 546 | .rev_offs = 0x100, | ||
| 547 | .sysc_offs = 0x110, | ||
| 548 | .syss_offs = 0x114, | ||
| 549 | .sysc_flags = SYSS_HAS_RESET_STATUS, | ||
| 550 | }; | ||
| 551 | |||
| 531 | static struct omap_hwmod_class am33xx_sha0_hwmod_class = { | 552 | static struct omap_hwmod_class am33xx_sha0_hwmod_class = { |
| 532 | .name = "sha0", | 553 | .name = "sha0", |
| 554 | .sysc = &am33xx_sha0_sysc, | ||
| 533 | }; | 555 | }; |
| 534 | 556 | ||
| 535 | static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = { | 557 | static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = { |
| 536 | { .irq = 108 + OMAP_INTC_START, }, | 558 | { .irq = 109 + OMAP_INTC_START, }, |
| 537 | { .irq = -1 }, | 559 | { .irq = -1 }, |
| 538 | }; | 560 | }; |
| 539 | 561 | ||
| 562 | static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = { | ||
| 563 | { .name = "rx", .dma_req = 36, }, | ||
| 564 | { .dma_req = -1 } | ||
| 565 | }; | ||
| 566 | |||
| 540 | static struct omap_hwmod am33xx_sha0_hwmod = { | 567 | static struct omap_hwmod am33xx_sha0_hwmod = { |
| 541 | .name = "sha0", | 568 | .name = "sham", |
| 542 | .class = &am33xx_sha0_hwmod_class, | 569 | .class = &am33xx_sha0_hwmod_class, |
| 543 | .clkdm_name = "l3_clkdm", | 570 | .clkdm_name = "l3_clkdm", |
| 544 | .mpu_irqs = am33xx_sha0_irqs, | 571 | .mpu_irqs = am33xx_sha0_irqs, |
| 572 | .sdma_reqs = am33xx_sha0_edma_reqs, | ||
| 545 | .main_clk = "l3_gclk", | 573 | .main_clk = "l3_gclk", |
| 546 | .prcm = { | 574 | .prcm = { |
| 547 | .omap4 = { | 575 | .omap4 = { |
| @@ -551,8 +579,6 @@ static struct omap_hwmod am33xx_sha0_hwmod = { | |||
| 551 | }, | 579 | }, |
| 552 | }; | 580 | }; |
| 553 | 581 | ||
| 554 | #endif | ||
| 555 | |||
| 556 | /* ocmcram */ | 582 | /* ocmcram */ |
| 557 | static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { | 583 | static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { |
| 558 | .name = "ocmcram", | 584 | .name = "ocmcram", |
| @@ -3449,6 +3475,42 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { | |||
| 3449 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3475 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3450 | }; | 3476 | }; |
| 3451 | 3477 | ||
| 3478 | /* l3 main -> sha0 HIB2 */ | ||
| 3479 | static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = { | ||
| 3480 | { | ||
| 3481 | .pa_start = 0x53100000, | ||
| 3482 | .pa_end = 0x53100000 + SZ_512 - 1, | ||
| 3483 | .flags = ADDR_TYPE_RT | ||
| 3484 | }, | ||
| 3485 | { } | ||
| 3486 | }; | ||
| 3487 | |||
| 3488 | static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = { | ||
| 3489 | .master = &am33xx_l3_main_hwmod, | ||
| 3490 | .slave = &am33xx_sha0_hwmod, | ||
| 3491 | .clk = "sha0_fck", | ||
| 3492 | .addr = am33xx_sha0_addrs, | ||
| 3493 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 3494 | }; | ||
| 3495 | |||
| 3496 | /* l3 main -> AES0 HIB2 */ | ||
| 3497 | static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = { | ||
| 3498 | { | ||
| 3499 | .pa_start = 0x53500000, | ||
| 3500 | .pa_end = 0x53500000 + SZ_1M - 1, | ||
| 3501 | .flags = ADDR_TYPE_RT | ||
| 3502 | }, | ||
| 3503 | { } | ||
| 3504 | }; | ||
| 3505 | |||
| 3506 | static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { | ||
| 3507 | .master = &am33xx_l3_main_hwmod, | ||
| 3508 | .slave = &am33xx_aes0_hwmod, | ||
| 3509 | .clk = "aes0_fck", | ||
| 3510 | .addr = am33xx_aes0_addrs, | ||
| 3511 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 3512 | }; | ||
| 3513 | |||
| 3452 | static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { | 3514 | static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { |
| 3453 | &am33xx_l4_fw__emif_fw, | 3515 | &am33xx_l4_fw__emif_fw, |
| 3454 | &am33xx_l3_main__emif, | 3516 | &am33xx_l3_main__emif, |
| @@ -3529,6 +3591,8 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { | |||
| 3529 | &am33xx_l3_s__usbss, | 3591 | &am33xx_l3_s__usbss, |
| 3530 | &am33xx_l4_hs__cpgmac0, | 3592 | &am33xx_l4_hs__cpgmac0, |
| 3531 | &am33xx_cpgmac0__mdio, | 3593 | &am33xx_cpgmac0__mdio, |
| 3594 | &am33xx_l3_main__sha0, | ||
| 3595 | &am33xx_l3_main__aes0, | ||
| 3532 | NULL, | 3596 | NULL, |
| 3533 | }; | 3597 | }; |
| 3534 | 3598 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 5112d04e7b79..4083606ea1da 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | |||
| @@ -3550,6 +3550,132 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = { | |||
| 3550 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3550 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3551 | }; | 3551 | }; |
| 3552 | 3552 | ||
| 3553 | /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */ | ||
| 3554 | static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = { | ||
| 3555 | .sidle_shift = 4, | ||
| 3556 | .srst_shift = 1, | ||
| 3557 | .autoidle_shift = 0, | ||
| 3558 | }; | ||
| 3559 | |||
| 3560 | static struct omap_hwmod_class_sysconfig omap3_sham_sysc = { | ||
| 3561 | .rev_offs = 0x5c, | ||
| 3562 | .sysc_offs = 0x60, | ||
| 3563 | .syss_offs = 0x64, | ||
| 3564 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | ||
| 3565 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | ||
| 3566 | .sysc_fields = &omap3_sham_sysc_fields, | ||
| 3567 | }; | ||
| 3568 | |||
| 3569 | static struct omap_hwmod_class omap3xxx_sham_class = { | ||
| 3570 | .name = "sham", | ||
| 3571 | .sysc = &omap3_sham_sysc, | ||
| 3572 | }; | ||
| 3573 | |||
| 3574 | static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = { | ||
| 3575 | { .irq = 49 + OMAP_INTC_START, }, | ||
| 3576 | { .irq = -1 } | ||
| 3577 | }; | ||
| 3578 | |||
| 3579 | static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = { | ||
| 3580 | { .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, }, | ||
| 3581 | { .dma_req = -1 } | ||
| 3582 | }; | ||
| 3583 | |||
| 3584 | static struct omap_hwmod omap3xxx_sham_hwmod = { | ||
| 3585 | .name = "sham", | ||
| 3586 | .mpu_irqs = omap3_sham_mpu_irqs, | ||
| 3587 | .sdma_reqs = omap3_sham_sdma_reqs, | ||
| 3588 | .main_clk = "sha12_ick", | ||
| 3589 | .prcm = { | ||
| 3590 | .omap2 = { | ||
| 3591 | .module_offs = CORE_MOD, | ||
| 3592 | .prcm_reg_id = 1, | ||
| 3593 | .module_bit = OMAP3430_EN_SHA12_SHIFT, | ||
| 3594 | .idlest_reg_id = 1, | ||
| 3595 | .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT, | ||
| 3596 | }, | ||
| 3597 | }, | ||
| 3598 | .class = &omap3xxx_sham_class, | ||
| 3599 | }; | ||
| 3600 | |||
| 3601 | static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = { | ||
| 3602 | { | ||
| 3603 | .pa_start = 0x480c3000, | ||
| 3604 | .pa_end = 0x480c3000 + 0x64 - 1, | ||
| 3605 | .flags = ADDR_TYPE_RT | ||
| 3606 | }, | ||
| 3607 | { } | ||
| 3608 | }; | ||
| 3609 | |||
| 3610 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = { | ||
| 3611 | .master = &omap3xxx_l4_core_hwmod, | ||
| 3612 | .slave = &omap3xxx_sham_hwmod, | ||
| 3613 | .clk = "sha12_ick", | ||
| 3614 | .addr = omap3xxx_sham_addrs, | ||
| 3615 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 3616 | }; | ||
| 3617 | |||
| 3618 | /* l4_core -> AES */ | ||
| 3619 | static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = { | ||
| 3620 | .sidle_shift = 6, | ||
| 3621 | .srst_shift = 1, | ||
| 3622 | .autoidle_shift = 0, | ||
| 3623 | }; | ||
| 3624 | |||
| 3625 | static struct omap_hwmod_class_sysconfig omap3_aes_sysc = { | ||
| 3626 | .rev_offs = 0x44, | ||
| 3627 | .sysc_offs = 0x48, | ||
| 3628 | .syss_offs = 0x4c, | ||
| 3629 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | ||
| 3630 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | ||
| 3631 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
| 3632 | .sysc_fields = &omap3xxx_aes_sysc_fields, | ||
| 3633 | }; | ||
| 3634 | |||
| 3635 | static struct omap_hwmod_class omap3xxx_aes_class = { | ||
| 3636 | .name = "aes", | ||
| 3637 | .sysc = &omap3_aes_sysc, | ||
| 3638 | }; | ||
| 3639 | |||
| 3640 | static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = { | ||
| 3641 | { .name = "tx", .dma_req = OMAP34XX_DMA_AES2_TX, }, | ||
| 3642 | { .name = "rx", .dma_req = OMAP34XX_DMA_AES2_RX, }, | ||
| 3643 | { .dma_req = -1 } | ||
| 3644 | }; | ||
| 3645 | |||
| 3646 | static struct omap_hwmod omap3xxx_aes_hwmod = { | ||
| 3647 | .name = "aes", | ||
| 3648 | .sdma_reqs = omap3_aes_sdma_reqs, | ||
| 3649 | .main_clk = "aes2_ick", | ||
| 3650 | .prcm = { | ||
| 3651 | .omap2 = { | ||
| 3652 | .module_offs = CORE_MOD, | ||
| 3653 | .prcm_reg_id = 1, | ||
| 3654 | .module_bit = OMAP3430_EN_AES2_SHIFT, | ||
| 3655 | .idlest_reg_id = 1, | ||
| 3656 | .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT, | ||
| 3657 | }, | ||
| 3658 | }, | ||
| 3659 | .class = &omap3xxx_aes_class, | ||
| 3660 | }; | ||
| 3661 | |||
| 3662 | static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = { | ||
| 3663 | { | ||
| 3664 | .pa_start = 0x480c5000, | ||
| 3665 | .pa_end = 0x480c5000 + 0x50 - 1, | ||
| 3666 | .flags = ADDR_TYPE_RT | ||
| 3667 | }, | ||
| 3668 | { } | ||
| 3669 | }; | ||
| 3670 | |||
| 3671 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = { | ||
| 3672 | .master = &omap3xxx_l4_core_hwmod, | ||
| 3673 | .slave = &omap3xxx_aes_hwmod, | ||
| 3674 | .clk = "aes2_ick", | ||
| 3675 | .addr = omap3xxx_aes_addrs, | ||
| 3676 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 3677 | }; | ||
| 3678 | |||
| 3553 | static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { | 3679 | static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { |
| 3554 | &omap3xxx_l3_main__l4_core, | 3680 | &omap3xxx_l3_main__l4_core, |
| 3555 | &omap3xxx_l3_main__l4_per, | 3681 | &omap3xxx_l3_main__l4_per, |
| @@ -3601,8 +3727,32 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { | |||
| 3601 | }; | 3727 | }; |
| 3602 | 3728 | ||
| 3603 | /* GP-only hwmod links */ | 3729 | /* GP-only hwmod links */ |
| 3604 | static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = { | 3730 | static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = { |
| 3605 | &omap3xxx_l4_sec__timer12, | 3731 | &omap3xxx_l4_sec__timer12, |
| 3732 | &omap3xxx_l4_core__sham, | ||
| 3733 | &omap3xxx_l4_core__aes, | ||
| 3734 | NULL | ||
| 3735 | }; | ||
| 3736 | |||
| 3737 | static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = { | ||
| 3738 | &omap3xxx_l4_sec__timer12, | ||
| 3739 | &omap3xxx_l4_core__sham, | ||
| 3740 | &omap3xxx_l4_core__aes, | ||
| 3741 | NULL | ||
| 3742 | }; | ||
| 3743 | |||
| 3744 | static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = { | ||
| 3745 | &omap3xxx_l4_sec__timer12, | ||
| 3746 | /* | ||
| 3747 | * Apparently the SHA/MD5 and AES accelerator IP blocks are | ||
| 3748 | * only present on some AM35xx chips, and no one knows which | ||
| 3749 | * ones. See | ||
| 3750 | * http://www.spinics.net/lists/arm-kernel/msg215466.html So | ||
| 3751 | * if you need these IP blocks on an AM35xx, try uncommenting | ||
| 3752 | * the following lines. | ||
| 3753 | */ | ||
| 3754 | /* &omap3xxx_l4_core__sham, */ | ||
| 3755 | /* &omap3xxx_l4_core__aes, */ | ||
| 3606 | NULL | 3756 | NULL |
| 3607 | }; | 3757 | }; |
| 3608 | 3758 | ||
| @@ -3709,7 +3859,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { | |||
| 3709 | int __init omap3xxx_hwmod_init(void) | 3859 | int __init omap3xxx_hwmod_init(void) |
| 3710 | { | 3860 | { |
| 3711 | int r; | 3861 | int r; |
| 3712 | struct omap_hwmod_ocp_if **h = NULL; | 3862 | struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL; |
| 3713 | unsigned int rev; | 3863 | unsigned int rev; |
| 3714 | 3864 | ||
| 3715 | omap_hwmod_init(); | 3865 | omap_hwmod_init(); |
| @@ -3719,13 +3869,6 @@ int __init omap3xxx_hwmod_init(void) | |||
| 3719 | if (r < 0) | 3869 | if (r < 0) |
| 3720 | return r; | 3870 | return r; |
| 3721 | 3871 | ||
| 3722 | /* Register GP-only hwmod links. */ | ||
| 3723 | if (omap_type() == OMAP2_DEVICE_TYPE_GP) { | ||
| 3724 | r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs); | ||
| 3725 | if (r < 0) | ||
| 3726 | return r; | ||
| 3727 | } | ||
| 3728 | |||
| 3729 | rev = omap_rev(); | 3872 | rev = omap_rev(); |
| 3730 | 3873 | ||
| 3731 | /* | 3874 | /* |
| @@ -3737,11 +3880,14 @@ int __init omap3xxx_hwmod_init(void) | |||
| 3737 | rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || | 3880 | rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || |
| 3738 | rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { | 3881 | rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { |
| 3739 | h = omap34xx_hwmod_ocp_ifs; | 3882 | h = omap34xx_hwmod_ocp_ifs; |
| 3883 | h_gp = omap34xx_gp_hwmod_ocp_ifs; | ||
| 3740 | } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { | 3884 | } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { |
| 3741 | h = am35xx_hwmod_ocp_ifs; | 3885 | h = am35xx_hwmod_ocp_ifs; |
| 3886 | h_gp = am35xx_gp_hwmod_ocp_ifs; | ||
| 3742 | } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || | 3887 | } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || |
| 3743 | rev == OMAP3630_REV_ES1_2) { | 3888 | rev == OMAP3630_REV_ES1_2) { |
| 3744 | h = omap36xx_hwmod_ocp_ifs; | 3889 | h = omap36xx_hwmod_ocp_ifs; |
| 3890 | h_gp = omap36xx_gp_hwmod_ocp_ifs; | ||
| 3745 | } else { | 3891 | } else { |
| 3746 | WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); | 3892 | WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); |
| 3747 | return -EINVAL; | 3893 | return -EINVAL; |
| @@ -3751,6 +3897,14 @@ int __init omap3xxx_hwmod_init(void) | |||
| 3751 | if (r < 0) | 3897 | if (r < 0) |
| 3752 | return r; | 3898 | return r; |
| 3753 | 3899 | ||
| 3900 | /* Register GP-only hwmod links. */ | ||
| 3901 | if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) { | ||
| 3902 | r = omap_hwmod_register_links(h_gp); | ||
| 3903 | if (r < 0) | ||
| 3904 | return r; | ||
| 3905 | } | ||
| 3906 | |||
| 3907 | |||
| 3754 | /* | 3908 | /* |
| 3755 | * Register hwmod links specific to certain ES levels of a | 3909 | * Register hwmod links specific to certain ES levels of a |
| 3756 | * particular family of silicon (e.g., 34xx ES1.0) | 3910 | * particular family of silicon (e.g., 34xx ES1.0) |
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index cfcce299177c..6e04ff7065e1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h | |||
| @@ -78,6 +78,8 @@ extern struct omap_hwmod omap2xxx_mcspi2_hwmod; | |||
| 78 | extern struct omap_hwmod omap2xxx_counter_32k_hwmod; | 78 | extern struct omap_hwmod omap2xxx_counter_32k_hwmod; |
| 79 | extern struct omap_hwmod omap2xxx_gpmc_hwmod; | 79 | extern struct omap_hwmod omap2xxx_gpmc_hwmod; |
| 80 | extern struct omap_hwmod omap2xxx_rng_hwmod; | 80 | extern struct omap_hwmod omap2xxx_rng_hwmod; |
| 81 | extern struct omap_hwmod omap2xxx_sham_hwmod; | ||
| 82 | extern struct omap_hwmod omap2xxx_aes_hwmod; | ||
| 81 | 83 | ||
| 82 | /* Common interface data across OMAP2xxx */ | 84 | /* Common interface data across OMAP2xxx */ |
| 83 | extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core; | 85 | extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core; |
| @@ -105,6 +107,8 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc; | |||
| 105 | extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi; | 107 | extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi; |
| 106 | extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc; | 108 | extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc; |
| 107 | extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng; | 109 | extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng; |
| 110 | extern struct omap_hwmod_ocp_if omap2xxx_l4_core__sham; | ||
| 111 | extern struct omap_hwmod_ocp_if omap2xxx_l4_core__aes; | ||
| 108 | 112 | ||
| 109 | /* Common IP block data */ | 113 | /* Common IP block data */ |
| 110 | extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[]; | 114 | extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[]; |
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig index 4f7379fe01e2..b3be7994a2b1 100644 --- a/arch/arm/mach-prima2/Kconfig +++ b/arch/arm/mach-prima2/Kconfig | |||
| @@ -1,6 +1,14 @@ | |||
| 1 | if ARCH_SIRF | 1 | if ARCH_SIRF |
| 2 | 2 | ||
| 3 | menu "CSR SiRF primaII/Marco/Polo Specific Features" | 3 | menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features" |
| 4 | |||
| 5 | config ARCH_ATLAS6 | ||
| 6 | bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform" | ||
| 7 | default y | ||
| 8 | select CPU_V7 | ||
| 9 | select SIRF_IRQ | ||
| 10 | help | ||
| 11 | Support for CSR SiRFSoC ARM Cortex A9 Platform | ||
| 4 | 12 | ||
| 5 | config ARCH_PRIMA2 | 13 | config ARCH_PRIMA2 |
| 6 | bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" | 14 | bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" |
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index 2d57aa479a7b..72efb4ff2803 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c | |||
| @@ -37,6 +37,27 @@ static __init void sirfsoc_map_io(void) | |||
| 37 | sirfsoc_map_scu(); | 37 | sirfsoc_map_scu(); |
| 38 | } | 38 | } |
| 39 | 39 | ||
| 40 | #ifdef CONFIG_ARCH_ATLAS6 | ||
| 41 | static const char *atlas6_dt_match[] __initdata = { | ||
| 42 | "sirf,atlas6", | ||
| 43 | NULL | ||
| 44 | }; | ||
| 45 | |||
| 46 | DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") | ||
| 47 | /* Maintainer: Barry Song <baohua.song@csr.com> */ | ||
| 48 | .map_io = sirfsoc_map_io, | ||
| 49 | .init_irq = sirfsoc_of_irq_init, | ||
| 50 | .init_time = sirfsoc_prima2_timer_init, | ||
| 51 | #ifdef CONFIG_MULTI_IRQ_HANDLER | ||
| 52 | .handle_irq = sirfsoc_handle_irq, | ||
| 53 | #endif | ||
| 54 | .init_machine = sirfsoc_mach_init, | ||
| 55 | .init_late = sirfsoc_init_late, | ||
| 56 | .dt_compat = atlas6_dt_match, | ||
| 57 | .restart = sirfsoc_restart, | ||
| 58 | MACHINE_END | ||
| 59 | #endif | ||
| 60 | |||
| 40 | #ifdef CONFIG_ARCH_PRIMA2 | 61 | #ifdef CONFIG_ARCH_PRIMA2 |
| 41 | static const char *prima2_dt_match[] __initdata = { | 62 | static const char *prima2_dt_match[] __initdata = { |
| 42 | "sirf,prima2", | 63 | "sirf,prima2", |
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index 6af1aa1ef213..759846c28d12 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c | |||
| @@ -509,6 +509,7 @@ int s3c2410_dma_request(enum dma_ch channel, | |||
| 509 | chan->client = client; | 509 | chan->client = client; |
| 510 | chan->in_use = 1; | 510 | chan->in_use = 1; |
| 511 | chan->peripheral = channel; | 511 | chan->peripheral = channel; |
| 512 | chan->flags = 0; | ||
| 512 | 513 | ||
| 513 | local_irq_restore(flags); | 514 | local_irq_restore(flags); |
| 514 | 515 | ||
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c index bf3d1c09b085..a946b759fabd 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c | |||
| @@ -210,6 +210,7 @@ static struct arizona_pdata wm5102_reva_pdata = { | |||
| 210 | .gpio_base = CODEC_GPIO_BASE, | 210 | .gpio_base = CODEC_GPIO_BASE, |
| 211 | .irq_active_high = true, | 211 | .irq_active_high = true, |
| 212 | .micd_pol_gpio = CODEC_GPIO_BASE + 4, | 212 | .micd_pol_gpio = CODEC_GPIO_BASE + 4, |
| 213 | .micd_rate = 6, | ||
| 213 | .gpio_defaults = { | 214 | .gpio_defaults = { |
| 214 | [2] = 0x10000, /* AIF3TXLRCLK */ | 215 | [2] = 0x10000, /* AIF3TXLRCLK */ |
| 215 | [3] = 0x4, /* OPCLK */ | 216 | [3] = 0x4, /* OPCLK */ |
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index e1fac57514b9..b646ff4d742a 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile | |||
| @@ -14,10 +14,9 @@ obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o | |||
| 14 | 14 | ||
| 15 | # SMP objects | 15 | # SMP objects |
| 16 | smp-y := platsmp.o headsmp.o | 16 | smp-y := platsmp.o headsmp.o |
| 17 | smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 17 | smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o |
| 18 | smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-sh73a0.o | 18 | smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o |
| 19 | smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o | 19 | smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o |
| 20 | smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o | ||
| 21 | 20 | ||
| 22 | # IRQ objects | 21 | # IRQ objects |
| 23 | obj-$(CONFIG_ARCH_SH7372) += entry-intc.o | 22 | obj-$(CONFIG_ARCH_SH7372) += entry-intc.o |
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index 19ce885a3b43..1feb9a2286a8 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c | |||
| @@ -593,29 +593,42 @@ static struct clk_lookup lookups[] = { | |||
| 593 | CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP128]), | 593 | CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP128]), |
| 594 | 594 | ||
| 595 | CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), | 595 | CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), |
| 596 | CLKDEV_DEV_ID("e6c80000.sci", &mstp_clks[MSTP200]), | ||
| 596 | CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), | 597 | CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), |
| 598 | CLKDEV_DEV_ID("e6c70000.sci", &mstp_clks[MSTP201]), | ||
| 597 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), | 599 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), |
| 600 | CLKDEV_DEV_ID("e6c60000.sci", &mstp_clks[MSTP202]), | ||
| 598 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), | 601 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), |
| 602 | CLKDEV_DEV_ID("e6c50000.sci", &mstp_clks[MSTP203]), | ||
| 599 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), | 603 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), |
| 604 | CLKDEV_DEV_ID("e6c40000.sci", &mstp_clks[MSTP204]), | ||
| 600 | CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), | 605 | CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), |
| 606 | CLKDEV_DEV_ID("e6c30000.sci", &mstp_clks[MSTP206]), | ||
| 601 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), | 607 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), |
| 608 | CLKDEV_DEV_ID("e6cb0000.sci", &mstp_clks[MSTP207]), | ||
| 602 | CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), | 609 | CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), |
| 603 | CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), | 610 | CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), |
| 604 | CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), | 611 | CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), |
| 605 | CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), | 612 | CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), |
| 606 | CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]), | 613 | CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]), |
| 614 | CLKDEV_DEV_ID("e6cd0000.sci", &mstp_clks[MSTP222]), | ||
| 607 | CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]), | 615 | CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]), |
| 616 | CLKDEV_DEV_ID("e6cc0000.sci", &mstp_clks[MSTP230]), | ||
| 608 | 617 | ||
| 609 | CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), | 618 | CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), |
| 610 | CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), | 619 | CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), |
| 611 | CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), | 620 | CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), |
| 612 | CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), | 621 | CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), |
| 613 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), | 622 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), |
| 623 | CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), | ||
| 614 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), | 624 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), |
| 625 | CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]), | ||
| 615 | CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]), | 626 | CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]), |
| 627 | CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), | ||
| 616 | CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]), | 628 | CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]), |
| 617 | 629 | ||
| 618 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), | 630 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), |
| 631 | CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), | ||
| 619 | 632 | ||
| 620 | /* ICK */ | 633 | /* ICK */ |
| 621 | CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]), | 634 | CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]), |
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index 1db36537255c..d9edeaf66007 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c | |||
| @@ -87,7 +87,8 @@ static struct clk div4_clks[DIV4_NR] = { | |||
| 87 | }; | 87 | }; |
| 88 | 88 | ||
| 89 | enum { MSTP323, MSTP322, MSTP321, MSTP320, | 89 | enum { MSTP323, MSTP322, MSTP321, MSTP320, |
| 90 | MSTP101, MSTP100, | 90 | MSTP115, |
| 91 | MSTP103, MSTP101, MSTP100, | ||
| 91 | MSTP030, | 92 | MSTP030, |
| 92 | MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, | 93 | MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, |
| 93 | MSTP016, MSTP015, MSTP014, | 94 | MSTP016, MSTP015, MSTP014, |
| @@ -99,6 +100,8 @@ static struct clk mstp_clks[MSTP_NR] = { | |||
| 99 | [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */ | 100 | [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */ |
| 100 | [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */ | 101 | [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */ |
| 101 | [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */ | 102 | [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */ |
| 103 | [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), /* SATA */ | ||
| 104 | [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1, 3, 0), /* DU */ | ||
| 102 | [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */ | 105 | [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */ |
| 103 | [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */ | 106 | [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */ |
| 104 | [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */ | 107 | [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */ |
| @@ -156,6 +159,8 @@ static struct clk_lookup lookups[] = { | |||
| 156 | CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), | 159 | CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), |
| 157 | 160 | ||
| 158 | /* MSTP32 clocks */ | 161 | /* MSTP32 clocks */ |
| 162 | CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ | ||
| 163 | CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */ | ||
| 159 | CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */ | 164 | CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */ |
| 160 | CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */ | 165 | CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */ |
| 161 | CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ | 166 | CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ |
| @@ -180,6 +185,7 @@ static struct clk_lookup lookups[] = { | |||
| 180 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ | 185 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ |
| 181 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ | 186 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ |
| 182 | CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ | 187 | CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ |
| 188 | CLKDEV_DEV_ID("rcar-du.0", &mstp_clks[MSTP103]), /* DU */ | ||
| 183 | }; | 189 | }; |
| 184 | 190 | ||
| 185 | void __init r8a7779_clock_init(void) | 191 | void __init r8a7779_clock_init(void) |
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index afa5423a0f93..71843dd39e16 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c | |||
| @@ -265,12 +265,12 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, | |||
| 265 | 265 | ||
| 266 | static struct clk div4_clks[DIV4_NR] = { | 266 | static struct clk div4_clks[DIV4_NR] = { |
| 267 | [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT), | 267 | [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT), |
| 268 | [DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT), | 268 | [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT), |
| 269 | [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT), | 269 | [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT), |
| 270 | [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT), | 270 | [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT), |
| 271 | [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0), | 271 | [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0), |
| 272 | [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0), | 272 | [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0), |
| 273 | [DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0), | 273 | [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0), |
| 274 | [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0), | 274 | [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0), |
| 275 | [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0), | 275 | [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0), |
| 276 | [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0), | 276 | [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0), |
| @@ -581,10 +581,13 @@ static struct clk_lookup lookups[] = { | |||
| 581 | CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */ | 581 | CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */ |
| 582 | CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */ | 582 | CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */ |
| 583 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ | 583 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ |
| 584 | CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */ | ||
| 584 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ | 585 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ |
| 586 | CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */ | ||
| 585 | CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ | 587 | CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ |
| 586 | CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */ | 588 | CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */ |
| 587 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */ | 589 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */ |
| 590 | CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */ | ||
| 588 | CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */ | 591 | CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */ |
| 589 | CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */ | 592 | CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */ |
| 590 | CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */ | 593 | CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */ |
diff --git a/arch/arm/mach-shmobile/headsmp-sh73a0.S b/arch/arm/mach-shmobile/headsmp-scu.S index bec4c0d9b713..7d113f898e7f 100644 --- a/arch/arm/mach-shmobile/headsmp-sh73a0.S +++ b/arch/arm/mach-shmobile/headsmp-scu.S | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * SMP support for SoC sh73a0 | 2 | * Shared SCU setup for mach-shmobile |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2012 Bastian Hecht | 4 | * Copyright (C) 2012 Bastian Hecht |
| 5 | * | 5 | * |
| @@ -35,11 +35,12 @@ | |||
| 35 | * the physical address as the MMU is still turned off. | 35 | * the physical address as the MMU is still turned off. |
| 36 | */ | 36 | */ |
| 37 | .align 12 | 37 | .align 12 |
| 38 | ENTRY(sh73a0_secondary_vector) | 38 | ENTRY(shmobile_secondary_vector_scu) |
| 39 | mrc p15, 0, r0, c0, c0, 5 @ read MIPDR | 39 | mrc p15, 0, r0, c0, c0, 5 @ read MIPDR |
| 40 | and r0, r0, #3 @ mask out cpu ID | 40 | and r0, r0, #3 @ mask out cpu ID |
| 41 | lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits | 41 | lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits |
| 42 | mov r1, #0xf0000000 @ SCU base address | 42 | ldr r1, 2f |
| 43 | ldr r1, [r1] @ SCU base address | ||
| 43 | ldr r2, [r1, #8] @ SCU Power Status Register | 44 | ldr r2, [r1, #8] @ SCU Power Status Register |
| 44 | mov r3, #3 | 45 | mov r3, #3 |
| 45 | bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode) | 46 | bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode) |
| @@ -47,4 +48,10 @@ ENTRY(sh73a0_secondary_vector) | |||
| 47 | 48 | ||
| 48 | ldr pc, 1f | 49 | ldr pc, 1f |
| 49 | 1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET | 50 | 1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET |
| 50 | ENDPROC(sh73a0_secondary_vector) | 51 | 2: .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET |
| 52 | ENDPROC(shmobile_secondary_vector_scu) | ||
| 53 | |||
| 54 | .text | ||
| 55 | .globl shmobile_scu_base | ||
| 56 | shmobile_scu_base: | ||
| 57 | .space 4 | ||
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c deleted file mode 100644 index a1524e3367b0..000000000000 --- a/arch/arm/mach-shmobile/hotplug.c +++ /dev/null | |||
| @@ -1,68 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * SMP support for R-Mobile / SH-Mobile | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Magnus Damm | ||
| 5 | * | ||
| 6 | * Based on realview, Copyright (C) 2002 ARM Ltd, All Rights Reserved | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/errno.h> | ||
| 14 | #include <linux/smp.h> | ||
| 15 | #include <linux/cpumask.h> | ||
| 16 | #include <linux/delay.h> | ||
| 17 | #include <linux/of.h> | ||
| 18 | #include <mach/common.h> | ||
| 19 | #include <mach/r8a7779.h> | ||
| 20 | #include <mach/emev2.h> | ||
| 21 | #include <asm/cacheflush.h> | ||
| 22 | #include <asm/mach-types.h> | ||
| 23 | |||
| 24 | static cpumask_t dead_cpus; | ||
| 25 | |||
| 26 | void shmobile_cpu_die(unsigned int cpu) | ||
| 27 | { | ||
| 28 | /* hardware shutdown code running on the CPU that is being offlined */ | ||
| 29 | flush_cache_all(); | ||
| 30 | dsb(); | ||
| 31 | |||
| 32 | /* notify platform_cpu_kill() that hardware shutdown is finished */ | ||
| 33 | cpumask_set_cpu(cpu, &dead_cpus); | ||
| 34 | |||
| 35 | /* wait for SoC code in platform_cpu_kill() to shut off CPU core | ||
| 36 | * power. CPU bring up starts from the reset vector. | ||
| 37 | */ | ||
| 38 | while (1) { | ||
| 39 | /* | ||
| 40 | * here's the WFI | ||
| 41 | */ | ||
| 42 | asm(".word 0xe320f003\n" | ||
| 43 | : | ||
| 44 | : | ||
| 45 | : "memory", "cc"); | ||
| 46 | } | ||
| 47 | } | ||
| 48 | |||
| 49 | int shmobile_cpu_disable(unsigned int cpu) | ||
| 50 | { | ||
| 51 | cpumask_clear_cpu(cpu, &dead_cpus); | ||
| 52 | /* | ||
| 53 | * we don't allow CPU 0 to be shutdown (it is still too special | ||
| 54 | * e.g. clock tick interrupts) | ||
| 55 | */ | ||
| 56 | return cpu == 0 ? -EPERM : 0; | ||
| 57 | } | ||
| 58 | |||
| 59 | int shmobile_cpu_disable_any(unsigned int cpu) | ||
| 60 | { | ||
| 61 | cpumask_clear_cpu(cpu, &dead_cpus); | ||
| 62 | return 0; | ||
| 63 | } | ||
| 64 | |||
| 65 | int shmobile_cpu_is_dead(unsigned int cpu) | ||
| 66 | { | ||
| 67 | return cpumask_test_cpu(cpu, &dead_cpus); | ||
| 68 | } | ||
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 362f9b2d2c02..62c04c252418 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h | |||
| @@ -8,6 +8,7 @@ extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz, | |||
| 8 | struct twd_local_timer; | 8 | struct twd_local_timer; |
| 9 | extern void shmobile_setup_console(void); | 9 | extern void shmobile_setup_console(void); |
| 10 | extern void shmobile_secondary_vector(void); | 10 | extern void shmobile_secondary_vector(void); |
| 11 | extern void shmobile_secondary_vector_scu(void); | ||
| 11 | struct clk; | 12 | struct clk; |
| 12 | extern int shmobile_clk_init(void); | 13 | extern int shmobile_clk_init(void); |
| 13 | extern void shmobile_handle_irq_intc(struct pt_regs *); | 14 | extern void shmobile_handle_irq_intc(struct pt_regs *); |
| @@ -30,23 +31,23 @@ extern int sh7372_do_idle_sysc(unsigned long sleep_mode); | |||
| 30 | extern struct clk sh7372_extal1_clk; | 31 | extern struct clk sh7372_extal1_clk; |
| 31 | extern struct clk sh7372_extal2_clk; | 32 | extern struct clk sh7372_extal2_clk; |
| 32 | 33 | ||
| 34 | extern void sh73a0_init_delay(void); | ||
| 33 | extern void sh73a0_init_irq(void); | 35 | extern void sh73a0_init_irq(void); |
| 34 | extern void sh73a0_init_irq_dt(void); | 36 | extern void sh73a0_init_irq_dt(void); |
| 35 | extern void sh73a0_map_io(void); | 37 | extern void sh73a0_map_io(void); |
| 36 | extern void sh73a0_earlytimer_init(void); | 38 | extern void sh73a0_earlytimer_init(void); |
| 37 | extern void sh73a0_add_early_devices(void); | 39 | extern void sh73a0_add_early_devices(void); |
| 38 | extern void sh73a0_add_early_devices_dt(void); | ||
| 39 | extern void sh73a0_add_standard_devices(void); | 40 | extern void sh73a0_add_standard_devices(void); |
| 40 | extern void sh73a0_add_standard_devices_dt(void); | 41 | extern void sh73a0_add_standard_devices_dt(void); |
| 41 | extern void sh73a0_clock_init(void); | 42 | extern void sh73a0_clock_init(void); |
| 42 | extern void sh73a0_pinmux_init(void); | 43 | extern void sh73a0_pinmux_init(void); |
| 43 | extern void sh73a0_pm_init(void); | 44 | extern void sh73a0_pm_init(void); |
| 44 | extern void sh73a0_secondary_vector(void); | ||
| 45 | extern struct clk sh73a0_extal1_clk; | 45 | extern struct clk sh73a0_extal1_clk; |
| 46 | extern struct clk sh73a0_extal2_clk; | 46 | extern struct clk sh73a0_extal2_clk; |
| 47 | extern struct clk sh73a0_extcki_clk; | 47 | extern struct clk sh73a0_extcki_clk; |
| 48 | extern struct clk sh73a0_extalr_clk; | 48 | extern struct clk sh73a0_extalr_clk; |
| 49 | 49 | ||
| 50 | extern void r8a7740_meram_workaround(void); | ||
| 50 | extern void r8a7740_init_irq(void); | 51 | extern void r8a7740_init_irq(void); |
| 51 | extern void r8a7740_map_io(void); | 52 | extern void r8a7740_map_io(void); |
| 52 | extern void r8a7740_add_early_devices(void); | 53 | extern void r8a7740_add_early_devices(void); |
| @@ -55,16 +56,17 @@ extern void r8a7740_clock_init(u8 md_ck); | |||
| 55 | extern void r8a7740_pinmux_init(void); | 56 | extern void r8a7740_pinmux_init(void); |
| 56 | extern void r8a7740_pm_init(void); | 57 | extern void r8a7740_pm_init(void); |
| 57 | 58 | ||
| 59 | extern void r8a7779_init_delay(void); | ||
| 58 | extern void r8a7779_init_irq(void); | 60 | extern void r8a7779_init_irq(void); |
| 61 | extern void r8a7779_init_irq_dt(void); | ||
| 59 | extern void r8a7779_map_io(void); | 62 | extern void r8a7779_map_io(void); |
| 60 | extern void r8a7779_earlytimer_init(void); | 63 | extern void r8a7779_earlytimer_init(void); |
| 61 | extern void r8a7779_add_early_devices(void); | 64 | extern void r8a7779_add_early_devices(void); |
| 62 | extern void r8a7779_add_standard_devices(void); | 65 | extern void r8a7779_add_standard_devices(void); |
| 66 | extern void r8a7779_add_standard_devices_dt(void); | ||
| 63 | extern void r8a7779_clock_init(void); | 67 | extern void r8a7779_clock_init(void); |
| 64 | extern void r8a7779_pinmux_init(void); | 68 | extern void r8a7779_pinmux_init(void); |
| 65 | extern void r8a7779_pm_init(void); | 69 | extern void r8a7779_pm_init(void); |
| 66 | extern void r8a7740_meram_workaround(void); | ||
| 67 | |||
| 68 | extern void r8a7779_register_twd(void); | 70 | extern void r8a7779_register_twd(void); |
| 69 | 71 | ||
| 70 | #ifdef CONFIG_SUSPEND | 72 | #ifdef CONFIG_SUSPEND |
| @@ -79,16 +81,7 @@ int shmobile_cpuidle_init(void); | |||
| 79 | static inline int shmobile_cpuidle_init(void) { return 0; } | 81 | static inline int shmobile_cpuidle_init(void) { return 0; } |
| 80 | #endif | 82 | #endif |
| 81 | 83 | ||
| 82 | extern void shmobile_cpu_die(unsigned int cpu); | 84 | extern void __iomem *shmobile_scu_base; |
| 83 | extern int shmobile_cpu_disable(unsigned int cpu); | ||
| 84 | extern int shmobile_cpu_disable_any(unsigned int cpu); | ||
| 85 | |||
| 86 | #ifdef CONFIG_HOTPLUG_CPU | ||
| 87 | extern int shmobile_cpu_is_dead(unsigned int cpu); | ||
| 88 | #else | ||
| 89 | static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; } | ||
| 90 | #endif | ||
| 91 | |||
| 92 | extern void shmobile_smp_init_cpus(unsigned int ncores); | 85 | extern void shmobile_smp_init_cpus(unsigned int ncores); |
| 93 | 86 | ||
| 94 | static inline void __init shmobile_init_late(void) | 87 | static inline void __init shmobile_init_late(void) |
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h index 06a5da3c3050..992ed213cec1 100644 --- a/arch/arm/mach-shmobile/include/mach/irqs.h +++ b/arch/arm/mach-shmobile/include/mach/irqs.h | |||
| @@ -5,6 +5,7 @@ | |||
| 5 | 5 | ||
| 6 | /* GIC */ | 6 | /* GIC */ |
| 7 | #define gic_spi(nr) ((nr) + 32) | 7 | #define gic_spi(nr) ((nr) + 32) |
| 8 | #define gic_iid(nr) (nr) /* ICCIAR / interrupt ID */ | ||
| 8 | 9 | ||
| 9 | /* INTCS */ | 10 | /* INTCS */ |
| 10 | #define INTCS_VECT_BASE 0x3400 | 11 | #define INTCS_VECT_BASE 0x3400 |
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c index 8807c27f71f9..f9cc4bc9c798 100644 --- a/arch/arm/mach-shmobile/intc-r8a7779.c +++ b/arch/arm/mach-shmobile/intc-r8a7779.c | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
| 25 | #include <linux/irqchip/arm-gic.h> | 25 | #include <linux/irqchip/arm-gic.h> |
| 26 | #include <mach/common.h> | 26 | #include <mach/common.h> |
| 27 | #include <linux/irqchip.h> | ||
| 27 | #include <mach/intc.h> | 28 | #include <mach/intc.h> |
| 28 | #include <mach/r8a7779.h> | 29 | #include <mach/r8a7779.h> |
| 29 | #include <asm/mach-types.h> | 30 | #include <asm/mach-types.h> |
| @@ -43,13 +44,8 @@ static int r8a7779_set_wake(struct irq_data *data, unsigned int on) | |||
| 43 | return 0; /* always allow wakeup */ | 44 | return 0; /* always allow wakeup */ |
| 44 | } | 45 | } |
| 45 | 46 | ||
| 46 | void __init r8a7779_init_irq(void) | 47 | static void __init r8a7779_init_irq_common(void) |
| 47 | { | 48 | { |
| 48 | void __iomem *gic_dist_base = IOMEM(0xf0001000); | ||
| 49 | void __iomem *gic_cpu_base = IOMEM(0xf0000100); | ||
| 50 | |||
| 51 | /* use GIC to handle interrupts */ | ||
| 52 | gic_init(0, 29, gic_dist_base, gic_cpu_base); | ||
| 53 | gic_arch_extn.irq_set_wake = r8a7779_set_wake; | 49 | gic_arch_extn.irq_set_wake = r8a7779_set_wake; |
| 54 | 50 | ||
| 55 | /* route all interrupts to ARM */ | 51 | /* route all interrupts to ARM */ |
| @@ -63,3 +59,22 @@ void __init r8a7779_init_irq(void) | |||
| 63 | __raw_writel(0xbffffffc, INT2SMSKCR3); | 59 | __raw_writel(0xbffffffc, INT2SMSKCR3); |
| 64 | __raw_writel(0x003fee3f, INT2SMSKCR4); | 60 | __raw_writel(0x003fee3f, INT2SMSKCR4); |
| 65 | } | 61 | } |
| 62 | |||
| 63 | void __init r8a7779_init_irq(void) | ||
| 64 | { | ||
| 65 | void __iomem *gic_dist_base = IOMEM(0xf0001000); | ||
| 66 | void __iomem *gic_cpu_base = IOMEM(0xf0000100); | ||
| 67 | |||
| 68 | /* use GIC to handle interrupts */ | ||
| 69 | gic_init(0, 29, gic_dist_base, gic_cpu_base); | ||
| 70 | |||
| 71 | r8a7779_init_irq_common(); | ||
| 72 | } | ||
| 73 | |||
| 74 | #ifdef CONFIG_OF | ||
| 75 | void __init r8a7779_init_irq_dt(void) | ||
| 76 | { | ||
| 77 | irqchip_init(); | ||
| 78 | r8a7779_init_irq_common(); | ||
| 79 | } | ||
| 80 | #endif | ||
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c index 91faba666d46..a81a1d804e2e 100644 --- a/arch/arm/mach-shmobile/intc-sh73a0.c +++ b/arch/arm/mach-shmobile/intc-sh73a0.c | |||
| @@ -460,11 +460,3 @@ void __init sh73a0_init_irq(void) | |||
| 460 | sh73a0_pint1_cascade.handler = sh73a0_pint1_demux; | 460 | sh73a0_pint1_cascade.handler = sh73a0_pint1_demux; |
| 461 | setup_irq(gic_spi(34), &sh73a0_pint1_cascade); | 461 | setup_irq(gic_spi(34), &sh73a0_pint1_cascade); |
| 462 | } | 462 | } |
| 463 | |||
| 464 | #ifdef CONFIG_OF | ||
| 465 | void __init sh73a0_init_irq_dt(void) | ||
| 466 | { | ||
| 467 | irqchip_init(); | ||
| 468 | gic_arch_extn.irq_set_wake = sh73a0_set_wake; | ||
| 469 | } | ||
| 470 | #endif | ||
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c index 47662a581c0a..e4545c152722 100644 --- a/arch/arm/mach-shmobile/setup-emev2.c +++ b/arch/arm/mach-shmobile/setup-emev2.c | |||
| @@ -404,7 +404,7 @@ void __init emev2_add_standard_devices(void) | |||
| 404 | ARRAY_SIZE(emev2_late_devices)); | 404 | ARRAY_SIZE(emev2_late_devices)); |
| 405 | } | 405 | } |
| 406 | 406 | ||
| 407 | void __init emev2_init_delay(void) | 407 | static void __init emev2_init_delay(void) |
| 408 | { | 408 | { |
| 409 | shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ | 409 | shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ |
| 410 | } | 410 | } |
| @@ -439,7 +439,7 @@ static const struct of_dev_auxdata emev2_auxdata_lookup[] __initconst = { | |||
| 439 | { } | 439 | { } |
| 440 | }; | 440 | }; |
| 441 | 441 | ||
| 442 | void __init emev2_add_standard_devices_dt(void) | 442 | static void __init emev2_add_standard_devices_dt(void) |
| 443 | { | 443 | { |
| 444 | of_platform_populate(NULL, of_default_bus_match_table, | 444 | of_platform_populate(NULL, of_default_bus_match_table, |
| 445 | emev2_auxdata_lookup, NULL); | 445 | emev2_auxdata_lookup, NULL); |
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index c54ff9b29fe5..042df35e71a0 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c | |||
| @@ -21,6 +21,7 @@ | |||
| 21 | #include <linux/init.h> | 21 | #include <linux/init.h> |
| 22 | #include <linux/interrupt.h> | 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/irq.h> | 23 | #include <linux/irq.h> |
| 24 | #include <linux/of_platform.h> | ||
| 24 | #include <linux/platform_device.h> | 25 | #include <linux/platform_device.h> |
| 25 | #include <linux/delay.h> | 26 | #include <linux/delay.h> |
| 26 | #include <linux/input.h> | 27 | #include <linux/input.h> |
| @@ -28,6 +29,7 @@ | |||
| 28 | #include <linux/serial_sci.h> | 29 | #include <linux/serial_sci.h> |
| 29 | #include <linux/sh_intc.h> | 30 | #include <linux/sh_intc.h> |
| 30 | #include <linux/sh_timer.h> | 31 | #include <linux/sh_timer.h> |
| 32 | #include <linux/dma-mapping.h> | ||
| 31 | #include <mach/hardware.h> | 33 | #include <mach/hardware.h> |
| 32 | #include <mach/irqs.h> | 34 | #include <mach/irqs.h> |
| 33 | #include <mach/r8a7779.h> | 35 | #include <mach/r8a7779.h> |
| @@ -91,7 +93,7 @@ static struct plat_sci_port scif0_platform_data = { | |||
| 91 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 93 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
| 92 | .scbrr_algo_id = SCBRR_ALGO_2, | 94 | .scbrr_algo_id = SCBRR_ALGO_2, |
| 93 | .type = PORT_SCIF, | 95 | .type = PORT_SCIF, |
| 94 | .irqs = SCIx_IRQ_MUXED(gic_spi(88)), | 96 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x78)), |
| 95 | }; | 97 | }; |
| 96 | 98 | ||
| 97 | static struct platform_device scif0_device = { | 99 | static struct platform_device scif0_device = { |
| @@ -108,7 +110,7 @@ static struct plat_sci_port scif1_platform_data = { | |||
| 108 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 110 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
| 109 | .scbrr_algo_id = SCBRR_ALGO_2, | 111 | .scbrr_algo_id = SCBRR_ALGO_2, |
| 110 | .type = PORT_SCIF, | 112 | .type = PORT_SCIF, |
| 111 | .irqs = SCIx_IRQ_MUXED(gic_spi(89)), | 113 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x79)), |
| 112 | }; | 114 | }; |
| 113 | 115 | ||
| 114 | static struct platform_device scif1_device = { | 116 | static struct platform_device scif1_device = { |
| @@ -125,7 +127,7 @@ static struct plat_sci_port scif2_platform_data = { | |||
| 125 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 127 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
| 126 | .scbrr_algo_id = SCBRR_ALGO_2, | 128 | .scbrr_algo_id = SCBRR_ALGO_2, |
| 127 | .type = PORT_SCIF, | 129 | .type = PORT_SCIF, |
| 128 | .irqs = SCIx_IRQ_MUXED(gic_spi(90)), | 130 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)), |
| 129 | }; | 131 | }; |
| 130 | 132 | ||
| 131 | static struct platform_device scif2_device = { | 133 | static struct platform_device scif2_device = { |
| @@ -142,7 +144,7 @@ static struct plat_sci_port scif3_platform_data = { | |||
| 142 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 144 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
| 143 | .scbrr_algo_id = SCBRR_ALGO_2, | 145 | .scbrr_algo_id = SCBRR_ALGO_2, |
| 144 | .type = PORT_SCIF, | 146 | .type = PORT_SCIF, |
| 145 | .irqs = SCIx_IRQ_MUXED(gic_spi(91)), | 147 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)), |
| 146 | }; | 148 | }; |
| 147 | 149 | ||
| 148 | static struct platform_device scif3_device = { | 150 | static struct platform_device scif3_device = { |
| @@ -159,7 +161,7 @@ static struct plat_sci_port scif4_platform_data = { | |||
| 159 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 161 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
| 160 | .scbrr_algo_id = SCBRR_ALGO_2, | 162 | .scbrr_algo_id = SCBRR_ALGO_2, |
| 161 | .type = PORT_SCIF, | 163 | .type = PORT_SCIF, |
| 162 | .irqs = SCIx_IRQ_MUXED(gic_spi(92)), | 164 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)), |
| 163 | }; | 165 | }; |
| 164 | 166 | ||
| 165 | static struct platform_device scif4_device = { | 167 | static struct platform_device scif4_device = { |
| @@ -176,7 +178,7 @@ static struct plat_sci_port scif5_platform_data = { | |||
| 176 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 178 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
| 177 | .scbrr_algo_id = SCBRR_ALGO_2, | 179 | .scbrr_algo_id = SCBRR_ALGO_2, |
| 178 | .type = PORT_SCIF, | 180 | .type = PORT_SCIF, |
| 179 | .irqs = SCIx_IRQ_MUXED(gic_spi(93)), | 181 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)), |
| 180 | }; | 182 | }; |
| 181 | 183 | ||
| 182 | static struct platform_device scif5_device = { | 184 | static struct platform_device scif5_device = { |
| @@ -203,7 +205,7 @@ static struct resource tmu00_resources[] = { | |||
| 203 | .flags = IORESOURCE_MEM, | 205 | .flags = IORESOURCE_MEM, |
| 204 | }, | 206 | }, |
| 205 | [1] = { | 207 | [1] = { |
| 206 | .start = gic_spi(32), | 208 | .start = gic_iid(0x40), |
| 207 | .flags = IORESOURCE_IRQ, | 209 | .flags = IORESOURCE_IRQ, |
| 208 | }, | 210 | }, |
| 209 | }; | 211 | }; |
| @@ -233,7 +235,7 @@ static struct resource tmu01_resources[] = { | |||
| 233 | .flags = IORESOURCE_MEM, | 235 | .flags = IORESOURCE_MEM, |
| 234 | }, | 236 | }, |
| 235 | [1] = { | 237 | [1] = { |
| 236 | .start = gic_spi(33), | 238 | .start = gic_iid(0x41), |
| 237 | .flags = IORESOURCE_IRQ, | 239 | .flags = IORESOURCE_IRQ, |
| 238 | }, | 240 | }, |
| 239 | }; | 241 | }; |
| @@ -255,7 +257,7 @@ static struct resource rcar_i2c0_res[] = { | |||
| 255 | .end = 0xffc70fff, | 257 | .end = 0xffc70fff, |
| 256 | .flags = IORESOURCE_MEM, | 258 | .flags = IORESOURCE_MEM, |
| 257 | }, { | 259 | }, { |
| 258 | .start = gic_spi(79), | 260 | .start = gic_iid(0x6f), |
| 259 | .flags = IORESOURCE_IRQ, | 261 | .flags = IORESOURCE_IRQ, |
| 260 | }, | 262 | }, |
| 261 | }; | 263 | }; |
| @@ -273,7 +275,7 @@ static struct resource rcar_i2c1_res[] = { | |||
| 273 | .end = 0xffc71fff, | 275 | .end = 0xffc71fff, |
| 274 | .flags = IORESOURCE_MEM, | 276 | .flags = IORESOURCE_MEM, |
| 275 | }, { | 277 | }, { |
| 276 | .start = gic_spi(82), | 278 | .start = gic_iid(0x72), |
| 277 | .flags = IORESOURCE_IRQ, | 279 | .flags = IORESOURCE_IRQ, |
| 278 | }, | 280 | }, |
| 279 | }; | 281 | }; |
| @@ -291,7 +293,7 @@ static struct resource rcar_i2c2_res[] = { | |||
| 291 | .end = 0xffc72fff, | 293 | .end = 0xffc72fff, |
| 292 | .flags = IORESOURCE_MEM, | 294 | .flags = IORESOURCE_MEM, |
| 293 | }, { | 295 | }, { |
| 294 | .start = gic_spi(80), | 296 | .start = gic_iid(0x70), |
| 295 | .flags = IORESOURCE_IRQ, | 297 | .flags = IORESOURCE_IRQ, |
| 296 | }, | 298 | }, |
| 297 | }; | 299 | }; |
| @@ -309,7 +311,7 @@ static struct resource rcar_i2c3_res[] = { | |||
| 309 | .end = 0xffc73fff, | 311 | .end = 0xffc73fff, |
| 310 | .flags = IORESOURCE_MEM, | 312 | .flags = IORESOURCE_MEM, |
| 311 | }, { | 313 | }, { |
| 312 | .start = gic_spi(81), | 314 | .start = gic_iid(0x71), |
| 313 | .flags = IORESOURCE_IRQ, | 315 | .flags = IORESOURCE_IRQ, |
| 314 | }, | 316 | }, |
| 315 | }; | 317 | }; |
| @@ -321,7 +323,31 @@ static struct platform_device i2c3_device = { | |||
| 321 | .num_resources = ARRAY_SIZE(rcar_i2c3_res), | 323 | .num_resources = ARRAY_SIZE(rcar_i2c3_res), |
| 322 | }; | 324 | }; |
| 323 | 325 | ||
| 324 | static struct platform_device *r8a7779_early_devices[] __initdata = { | 326 | static struct resource sata_resources[] = { |
| 327 | [0] = { | ||
| 328 | .name = "rcar-sata", | ||
| 329 | .start = 0xfc600000, | ||
| 330 | .end = 0xfc601fff, | ||
| 331 | .flags = IORESOURCE_MEM, | ||
| 332 | }, | ||
| 333 | [1] = { | ||
| 334 | .start = gic_iid(0x84), | ||
| 335 | .flags = IORESOURCE_IRQ, | ||
| 336 | }, | ||
| 337 | }; | ||
| 338 | |||
| 339 | static struct platform_device sata_device = { | ||
| 340 | .name = "sata_rcar", | ||
| 341 | .id = -1, | ||
| 342 | .resource = sata_resources, | ||
| 343 | .num_resources = ARRAY_SIZE(sata_resources), | ||
| 344 | .dev = { | ||
| 345 | .dma_mask = &sata_device.dev.coherent_dma_mask, | ||
| 346 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 347 | }, | ||
| 348 | }; | ||
| 349 | |||
| 350 | static struct platform_device *r8a7779_devices_dt[] __initdata = { | ||
| 325 | &scif0_device, | 351 | &scif0_device, |
| 326 | &scif1_device, | 352 | &scif1_device, |
| 327 | &scif2_device, | 353 | &scif2_device, |
| @@ -330,13 +356,14 @@ static struct platform_device *r8a7779_early_devices[] __initdata = { | |||
| 330 | &scif5_device, | 356 | &scif5_device, |
| 331 | &tmu00_device, | 357 | &tmu00_device, |
| 332 | &tmu01_device, | 358 | &tmu01_device, |
| 359 | }; | ||
| 360 | |||
| 361 | static struct platform_device *r8a7779_late_devices[] __initdata = { | ||
| 333 | &i2c0_device, | 362 | &i2c0_device, |
| 334 | &i2c1_device, | 363 | &i2c1_device, |
| 335 | &i2c2_device, | 364 | &i2c2_device, |
| 336 | &i2c3_device, | 365 | &i2c3_device, |
| 337 | }; | 366 | &sata_device, |
| 338 | |||
| 339 | static struct platform_device *r8a7779_late_devices[] __initdata = { | ||
| 340 | }; | 367 | }; |
| 341 | 368 | ||
| 342 | void __init r8a7779_add_standard_devices(void) | 369 | void __init r8a7779_add_standard_devices(void) |
| @@ -349,8 +376,8 @@ void __init r8a7779_add_standard_devices(void) | |||
| 349 | 376 | ||
| 350 | r8a7779_init_pm_domains(); | 377 | r8a7779_init_pm_domains(); |
| 351 | 378 | ||
| 352 | platform_add_devices(r8a7779_early_devices, | 379 | platform_add_devices(r8a7779_devices_dt, |
| 353 | ARRAY_SIZE(r8a7779_early_devices)); | 380 | ARRAY_SIZE(r8a7779_devices_dt)); |
| 354 | platform_add_devices(r8a7779_late_devices, | 381 | platform_add_devices(r8a7779_late_devices, |
| 355 | ARRAY_SIZE(r8a7779_late_devices)); | 382 | ARRAY_SIZE(r8a7779_late_devices)); |
| 356 | } | 383 | } |
| @@ -367,8 +394,8 @@ void __init r8a7779_earlytimer_init(void) | |||
| 367 | 394 | ||
| 368 | void __init r8a7779_add_early_devices(void) | 395 | void __init r8a7779_add_early_devices(void) |
| 369 | { | 396 | { |
| 370 | early_platform_add_devices(r8a7779_early_devices, | 397 | early_platform_add_devices(r8a7779_devices_dt, |
| 371 | ARRAY_SIZE(r8a7779_early_devices)); | 398 | ARRAY_SIZE(r8a7779_devices_dt)); |
| 372 | 399 | ||
| 373 | /* Early serial console setup is not included here due to | 400 | /* Early serial console setup is not included here due to |
| 374 | * memory map collisions. The SCIF serial ports in r8a7779 | 401 | * memory map collisions. The SCIF serial ports in r8a7779 |
| @@ -386,3 +413,40 @@ void __init r8a7779_add_early_devices(void) | |||
| 386 | * command line in case of the marzen board. | 413 | * command line in case of the marzen board. |
| 387 | */ | 414 | */ |
| 388 | } | 415 | } |
| 416 | |||
| 417 | #ifdef CONFIG_USE_OF | ||
| 418 | void __init r8a7779_init_delay(void) | ||
| 419 | { | ||
| 420 | shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */ | ||
| 421 | } | ||
| 422 | |||
| 423 | static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = { | ||
| 424 | {}, | ||
| 425 | }; | ||
| 426 | |||
| 427 | void __init r8a7779_add_standard_devices_dt(void) | ||
| 428 | { | ||
| 429 | /* clocks are setup late during boot in the case of DT */ | ||
| 430 | r8a7779_clock_init(); | ||
| 431 | |||
| 432 | platform_add_devices(r8a7779_devices_dt, | ||
| 433 | ARRAY_SIZE(r8a7779_devices_dt)); | ||
| 434 | of_platform_populate(NULL, of_default_bus_match_table, | ||
| 435 | r8a7779_auxdata_lookup, NULL); | ||
| 436 | } | ||
| 437 | |||
| 438 | static const char *r8a7779_compat_dt[] __initdata = { | ||
| 439 | "renesas,r8a7779", | ||
| 440 | NULL, | ||
| 441 | }; | ||
| 442 | |||
| 443 | DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") | ||
| 444 | .map_io = r8a7779_map_io, | ||
| 445 | .init_early = r8a7779_init_delay, | ||
| 446 | .nr_irqs = NR_IRQS_LEGACY, | ||
| 447 | .init_irq = r8a7779_init_irq_dt, | ||
| 448 | .init_machine = r8a7779_add_standard_devices_dt, | ||
| 449 | .init_time = shmobile_timer_init, | ||
| 450 | .dt_compat = r8a7779_compat_dt, | ||
| 451 | MACHINE_END | ||
| 452 | #endif /* CONFIG_USE_OF */ | ||
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index bdab575f88bc..2257a915746d 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/init.h> | 22 | #include <linux/init.h> |
| 23 | #include <linux/interrupt.h> | 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/irq.h> | 24 | #include <linux/irq.h> |
| 25 | #include <linux/irqchip.h> | ||
| 25 | #include <linux/platform_device.h> | 26 | #include <linux/platform_device.h> |
| 26 | #include <linux/of_platform.h> | 27 | #include <linux/of_platform.h> |
| 27 | #include <linux/delay.h> | 28 | #include <linux/delay.h> |
| @@ -810,7 +811,7 @@ static struct platform_device ipmmu_device = { | |||
| 810 | .num_resources = ARRAY_SIZE(ipmmu_resources), | 811 | .num_resources = ARRAY_SIZE(ipmmu_resources), |
| 811 | }; | 812 | }; |
| 812 | 813 | ||
| 813 | static struct platform_device *sh73a0_early_devices_dt[] __initdata = { | 814 | static struct platform_device *sh73a0_devices_dt[] __initdata = { |
| 814 | &scif0_device, | 815 | &scif0_device, |
| 815 | &scif1_device, | 816 | &scif1_device, |
| 816 | &scif2_device, | 817 | &scif2_device, |
| @@ -847,8 +848,8 @@ void __init sh73a0_add_standard_devices(void) | |||
| 847 | /* Clear software reset bit on SY-DMAC module */ | 848 | /* Clear software reset bit on SY-DMAC module */ |
| 848 | __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); | 849 | __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); |
| 849 | 850 | ||
| 850 | platform_add_devices(sh73a0_early_devices_dt, | 851 | platform_add_devices(sh73a0_devices_dt, |
| 851 | ARRAY_SIZE(sh73a0_early_devices_dt)); | 852 | ARRAY_SIZE(sh73a0_devices_dt)); |
| 852 | platform_add_devices(sh73a0_early_devices, | 853 | platform_add_devices(sh73a0_early_devices, |
| 853 | ARRAY_SIZE(sh73a0_early_devices)); | 854 | ARRAY_SIZE(sh73a0_early_devices)); |
| 854 | platform_add_devices(sh73a0_late_devices, | 855 | platform_add_devices(sh73a0_late_devices, |
| @@ -867,8 +868,8 @@ void __init sh73a0_earlytimer_init(void) | |||
| 867 | 868 | ||
| 868 | void __init sh73a0_add_early_devices(void) | 869 | void __init sh73a0_add_early_devices(void) |
| 869 | { | 870 | { |
| 870 | early_platform_add_devices(sh73a0_early_devices_dt, | 871 | early_platform_add_devices(sh73a0_devices_dt, |
| 871 | ARRAY_SIZE(sh73a0_early_devices_dt)); | 872 | ARRAY_SIZE(sh73a0_devices_dt)); |
| 872 | early_platform_add_devices(sh73a0_early_devices, | 873 | early_platform_add_devices(sh73a0_early_devices, |
| 873 | ARRAY_SIZE(sh73a0_early_devices)); | 874 | ARRAY_SIZE(sh73a0_early_devices)); |
| 874 | 875 | ||
| @@ -878,23 +879,9 @@ void __init sh73a0_add_early_devices(void) | |||
| 878 | 879 | ||
| 879 | #ifdef CONFIG_USE_OF | 880 | #ifdef CONFIG_USE_OF |
| 880 | 881 | ||
| 881 | /* Please note that the clock initialisation shcheme used in | 882 | void __init sh73a0_init_delay(void) |
| 882 | * sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt() | ||
| 883 | * does not work with SMP as there is a yet to be resolved lock-up in | ||
| 884 | * workqueue initialisation. | ||
| 885 | * | ||
| 886 | * CONFIG_SMP should be disabled when using this code. | ||
| 887 | */ | ||
| 888 | |||
| 889 | void __init sh73a0_add_early_devices_dt(void) | ||
| 890 | { | 883 | { |
| 891 | shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ | 884 | shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ |
| 892 | |||
| 893 | early_platform_add_devices(sh73a0_early_devices_dt, | ||
| 894 | ARRAY_SIZE(sh73a0_early_devices_dt)); | ||
| 895 | |||
| 896 | /* setup early console here as well */ | ||
| 897 | shmobile_setup_console(); | ||
| 898 | } | 885 | } |
| 899 | 886 | ||
| 900 | static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = { | 887 | static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = { |
| @@ -906,8 +893,8 @@ void __init sh73a0_add_standard_devices_dt(void) | |||
| 906 | /* clocks are setup late during boot in the case of DT */ | 893 | /* clocks are setup late during boot in the case of DT */ |
| 907 | sh73a0_clock_init(); | 894 | sh73a0_clock_init(); |
| 908 | 895 | ||
| 909 | platform_add_devices(sh73a0_early_devices_dt, | 896 | platform_add_devices(sh73a0_devices_dt, |
| 910 | ARRAY_SIZE(sh73a0_early_devices_dt)); | 897 | ARRAY_SIZE(sh73a0_devices_dt)); |
| 911 | of_platform_populate(NULL, of_default_bus_match_table, | 898 | of_platform_populate(NULL, of_default_bus_match_table, |
| 912 | sh73a0_auxdata_lookup, NULL); | 899 | sh73a0_auxdata_lookup, NULL); |
| 913 | } | 900 | } |
| @@ -918,10 +905,11 @@ static const char *sh73a0_boards_compat_dt[] __initdata = { | |||
| 918 | }; | 905 | }; |
| 919 | 906 | ||
| 920 | DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") | 907 | DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") |
| 908 | .smp = smp_ops(sh73a0_smp_ops), | ||
| 921 | .map_io = sh73a0_map_io, | 909 | .map_io = sh73a0_map_io, |
| 922 | .init_early = sh73a0_add_early_devices_dt, | 910 | .init_early = sh73a0_init_delay, |
| 923 | .nr_irqs = NR_IRQS_LEGACY, | 911 | .nr_irqs = NR_IRQS_LEGACY, |
| 924 | .init_irq = sh73a0_init_irq_dt, | 912 | .init_irq = irqchip_init, |
| 925 | .init_machine = sh73a0_add_standard_devices_dt, | 913 | .init_machine = sh73a0_add_standard_devices_dt, |
| 926 | .init_time = shmobile_timer_init, | 914 | .init_time = shmobile_timer_init, |
| 927 | .dt_compat = sh73a0_boards_compat_dt, | 915 | .dt_compat = sh73a0_boards_compat_dt, |
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 384e27dd3601..e38691b4d0dd 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c | |||
| @@ -27,90 +27,35 @@ | |||
| 27 | #include <mach/emev2.h> | 27 | #include <mach/emev2.h> |
| 28 | #include <asm/smp_plat.h> | 28 | #include <asm/smp_plat.h> |
| 29 | #include <asm/smp_scu.h> | 29 | #include <asm/smp_scu.h> |
| 30 | #include <asm/cacheflush.h> | ||
| 31 | 30 | ||
| 32 | #define EMEV2_SCU_BASE 0x1e000000 | 31 | #define EMEV2_SCU_BASE 0x1e000000 |
| 33 | 32 | ||
| 34 | static DEFINE_SPINLOCK(scu_lock); | ||
| 35 | static void __iomem *scu_base; | ||
| 36 | |||
| 37 | static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) | ||
| 38 | { | ||
| 39 | unsigned long tmp; | ||
| 40 | |||
| 41 | /* we assume this code is running on a different cpu | ||
| 42 | * than the one that is changing coherency setting */ | ||
| 43 | spin_lock(&scu_lock); | ||
| 44 | tmp = readl(scu_base + 8); | ||
| 45 | tmp &= ~clr; | ||
| 46 | tmp |= set; | ||
| 47 | writel(tmp, scu_base + 8); | ||
| 48 | spin_unlock(&scu_lock); | ||
| 49 | |||
| 50 | } | ||
| 51 | |||
| 52 | static unsigned int __init emev2_get_core_count(void) | ||
| 53 | { | ||
| 54 | if (!scu_base) { | ||
| 55 | scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); | ||
| 56 | emev2_clock_init(); /* need ioremapped SMU */ | ||
| 57 | } | ||
| 58 | |||
| 59 | WARN_ON_ONCE(!scu_base); | ||
| 60 | |||
| 61 | return scu_base ? scu_get_core_count(scu_base) : 1; | ||
| 62 | } | ||
| 63 | |||
| 64 | static int emev2_platform_cpu_kill(unsigned int cpu) | ||
| 65 | { | ||
| 66 | return 0; /* not supported yet */ | ||
| 67 | } | ||
| 68 | |||
| 69 | static int __maybe_unused emev2_cpu_kill(unsigned int cpu) | ||
| 70 | { | ||
| 71 | int k; | ||
| 72 | |||
| 73 | /* this function is running on another CPU than the offline target, | ||
| 74 | * here we need wait for shutdown code in platform_cpu_die() to | ||
| 75 | * finish before asking SoC-specific code to power off the CPU core. | ||
| 76 | */ | ||
| 77 | for (k = 0; k < 1000; k++) { | ||
| 78 | if (shmobile_cpu_is_dead(cpu)) | ||
| 79 | return emev2_platform_cpu_kill(cpu); | ||
| 80 | mdelay(1); | ||
| 81 | } | ||
| 82 | |||
| 83 | return 0; | ||
| 84 | } | ||
| 85 | |||
| 86 | |||
| 87 | static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) | 33 | static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 88 | { | 34 | { |
| 89 | cpu = cpu_logical_map(cpu); | 35 | arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu))); |
| 90 | |||
| 91 | /* enable cache coherency */ | ||
| 92 | modify_scu_cpu_psr(0, 3 << (cpu * 8)); | ||
| 93 | |||
| 94 | /* Tell ROM loader about our vector (in headsmp.S) */ | ||
| 95 | emev2_set_boot_vector(__pa(shmobile_secondary_vector)); | ||
| 96 | |||
| 97 | arch_send_wakeup_ipi_mask(cpumask_of(cpu)); | ||
| 98 | return 0; | 36 | return 0; |
| 99 | } | 37 | } |
| 100 | 38 | ||
| 101 | static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) | 39 | static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) |
| 102 | { | 40 | { |
| 103 | int cpu = cpu_logical_map(0); | 41 | scu_enable(shmobile_scu_base); |
| 104 | 42 | ||
| 105 | scu_enable(scu_base); | 43 | /* Tell ROM loader about our vector (in headsmp-scu.S) */ |
| 44 | emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu)); | ||
| 106 | 45 | ||
| 107 | /* enable cache coherency on CPU0 */ | 46 | /* enable cache coherency on booting CPU */ |
| 108 | modify_scu_cpu_psr(0, 3 << (cpu * 8)); | 47 | scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); |
| 109 | } | 48 | } |
| 110 | 49 | ||
| 111 | static void __init emev2_smp_init_cpus(void) | 50 | static void __init emev2_smp_init_cpus(void) |
| 112 | { | 51 | { |
| 113 | unsigned int ncores = emev2_get_core_count(); | 52 | unsigned int ncores; |
| 53 | |||
| 54 | /* setup EMEV2 specific SCU base */ | ||
| 55 | shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); | ||
| 56 | emev2_clock_init(); /* need ioremapped SMU */ | ||
| 57 | |||
| 58 | ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1; | ||
| 114 | 59 | ||
| 115 | shmobile_smp_init_cpus(ncores); | 60 | shmobile_smp_init_cpus(ncores); |
| 116 | } | 61 | } |
| @@ -119,9 +64,4 @@ struct smp_operations emev2_smp_ops __initdata = { | |||
| 119 | .smp_init_cpus = emev2_smp_init_cpus, | 64 | .smp_init_cpus = emev2_smp_init_cpus, |
| 120 | .smp_prepare_cpus = emev2_smp_prepare_cpus, | 65 | .smp_prepare_cpus = emev2_smp_prepare_cpus, |
| 121 | .smp_boot_secondary = emev2_boot_secondary, | 66 | .smp_boot_secondary = emev2_boot_secondary, |
| 122 | #ifdef CONFIG_HOTPLUG_CPU | ||
| 123 | .cpu_kill = emev2_cpu_kill, | ||
| 124 | .cpu_die = shmobile_cpu_die, | ||
| 125 | .cpu_disable = shmobile_cpu_disable, | ||
| 126 | #endif | ||
| 127 | }; | 67 | }; |
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 994906560edd..a853bf182ed5 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c | |||
| @@ -25,11 +25,13 @@ | |||
| 25 | #include <linux/delay.h> | 25 | #include <linux/delay.h> |
| 26 | #include <mach/common.h> | 26 | #include <mach/common.h> |
| 27 | #include <mach/r8a7779.h> | 27 | #include <mach/r8a7779.h> |
| 28 | #include <asm/cacheflush.h> | ||
| 28 | #include <asm/smp_plat.h> | 29 | #include <asm/smp_plat.h> |
| 29 | #include <asm/smp_scu.h> | 30 | #include <asm/smp_scu.h> |
| 30 | #include <asm/smp_twd.h> | 31 | #include <asm/smp_twd.h> |
| 31 | 32 | ||
| 32 | #define AVECR IOMEM(0xfe700040) | 33 | #define AVECR IOMEM(0xfe700040) |
| 34 | #define R8A7779_SCU_BASE 0xf0000000 | ||
| 33 | 35 | ||
| 34 | static struct r8a7779_pm_ch r8a7779_ch_cpu1 = { | 36 | static struct r8a7779_pm_ch r8a7779_ch_cpu1 = { |
| 35 | .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ | 37 | .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ |
| @@ -55,44 +57,14 @@ static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = { | |||
| 55 | [3] = &r8a7779_ch_cpu3, | 57 | [3] = &r8a7779_ch_cpu3, |
| 56 | }; | 58 | }; |
| 57 | 59 | ||
| 58 | static void __iomem *scu_base_addr(void) | ||
| 59 | { | ||
| 60 | return (void __iomem *)0xf0000000; | ||
| 61 | } | ||
| 62 | |||
| 63 | static DEFINE_SPINLOCK(scu_lock); | ||
| 64 | static unsigned long tmp; | ||
| 65 | |||
| 66 | #ifdef CONFIG_HAVE_ARM_TWD | 60 | #ifdef CONFIG_HAVE_ARM_TWD |
| 67 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); | 61 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29); |
| 68 | |||
| 69 | void __init r8a7779_register_twd(void) | 62 | void __init r8a7779_register_twd(void) |
| 70 | { | 63 | { |
| 71 | twd_local_timer_register(&twd_local_timer); | 64 | twd_local_timer_register(&twd_local_timer); |
| 72 | } | 65 | } |
| 73 | #endif | 66 | #endif |
| 74 | 67 | ||
| 75 | static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) | ||
| 76 | { | ||
| 77 | void __iomem *scu_base = scu_base_addr(); | ||
| 78 | |||
| 79 | spin_lock(&scu_lock); | ||
| 80 | tmp = __raw_readl(scu_base + 8); | ||
| 81 | tmp &= ~clr; | ||
| 82 | tmp |= set; | ||
| 83 | spin_unlock(&scu_lock); | ||
| 84 | |||
| 85 | /* disable cache coherency after releasing the lock */ | ||
| 86 | __raw_writel(tmp, scu_base + 8); | ||
| 87 | } | ||
| 88 | |||
| 89 | static unsigned int __init r8a7779_get_core_count(void) | ||
| 90 | { | ||
| 91 | void __iomem *scu_base = scu_base_addr(); | ||
| 92 | |||
| 93 | return scu_get_core_count(scu_base); | ||
| 94 | } | ||
| 95 | |||
| 96 | static int r8a7779_platform_cpu_kill(unsigned int cpu) | 68 | static int r8a7779_platform_cpu_kill(unsigned int cpu) |
| 97 | { | 69 | { |
| 98 | struct r8a7779_pm_ch *ch = NULL; | 70 | struct r8a7779_pm_ch *ch = NULL; |
| @@ -100,9 +72,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu) | |||
| 100 | 72 | ||
| 101 | cpu = cpu_logical_map(cpu); | 73 | cpu = cpu_logical_map(cpu); |
| 102 | 74 | ||
| 103 | /* disable cache coherency */ | ||
| 104 | modify_scu_cpu_psr(3 << (cpu * 8), 0); | ||
| 105 | |||
| 106 | if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) | 75 | if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) |
| 107 | ch = r8a7779_ch_cpu[cpu]; | 76 | ch = r8a7779_ch_cpu[cpu]; |
| 108 | 77 | ||
| @@ -112,25 +81,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu) | |||
| 112 | return ret ? ret : 1; | 81 | return ret ? ret : 1; |
| 113 | } | 82 | } |
| 114 | 83 | ||
| 115 | static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu) | ||
| 116 | { | ||
| 117 | int k; | ||
| 118 | |||
| 119 | /* this function is running on another CPU than the offline target, | ||
| 120 | * here we need wait for shutdown code in platform_cpu_die() to | ||
| 121 | * finish before asking SoC-specific code to power off the CPU core. | ||
| 122 | */ | ||
| 123 | for (k = 0; k < 1000; k++) { | ||
| 124 | if (shmobile_cpu_is_dead(cpu)) | ||
| 125 | return r8a7779_platform_cpu_kill(cpu); | ||
| 126 | |||
| 127 | mdelay(1); | ||
| 128 | } | ||
| 129 | |||
| 130 | return 0; | ||
| 131 | } | ||
| 132 | |||
| 133 | |||
| 134 | static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) | 84 | static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 135 | { | 85 | { |
| 136 | struct r8a7779_pm_ch *ch = NULL; | 86 | struct r8a7779_pm_ch *ch = NULL; |
| @@ -138,9 +88,6 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct | |||
| 138 | 88 | ||
| 139 | cpu = cpu_logical_map(cpu); | 89 | cpu = cpu_logical_map(cpu); |
| 140 | 90 | ||
| 141 | /* enable cache coherency */ | ||
| 142 | modify_scu_cpu_psr(0, 3 << (cpu * 8)); | ||
| 143 | |||
| 144 | if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) | 91 | if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) |
| 145 | ch = r8a7779_ch_cpu[cpu]; | 92 | ch = r8a7779_ch_cpu[cpu]; |
| 146 | 93 | ||
| @@ -152,15 +99,13 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct | |||
| 152 | 99 | ||
| 153 | static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) | 100 | static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) |
| 154 | { | 101 | { |
| 155 | int cpu = cpu_logical_map(0); | 102 | scu_enable(shmobile_scu_base); |
| 156 | 103 | ||
| 157 | scu_enable(scu_base_addr()); | 104 | /* Map the reset vector (in headsmp-scu.S) */ |
| 105 | __raw_writel(__pa(shmobile_secondary_vector_scu), AVECR); | ||
| 158 | 106 | ||
| 159 | /* Map the reset vector (in headsmp.S) */ | 107 | /* enable cache coherency on booting CPU */ |
| 160 | __raw_writel(__pa(shmobile_secondary_vector), AVECR); | 108 | scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); |
| 161 | |||
| 162 | /* enable cache coherency on CPU0 */ | ||
| 163 | modify_scu_cpu_psr(0, 3 << (cpu * 8)); | ||
| 164 | 109 | ||
| 165 | r8a7779_pm_init(); | 110 | r8a7779_pm_init(); |
| 166 | 111 | ||
| @@ -172,10 +117,60 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) | |||
| 172 | 117 | ||
| 173 | static void __init r8a7779_smp_init_cpus(void) | 118 | static void __init r8a7779_smp_init_cpus(void) |
| 174 | { | 119 | { |
| 175 | unsigned int ncores = r8a7779_get_core_count(); | 120 | /* setup r8a7779 specific SCU base */ |
| 121 | shmobile_scu_base = IOMEM(R8A7779_SCU_BASE); | ||
| 122 | |||
| 123 | shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base)); | ||
| 124 | } | ||
| 176 | 125 | ||
| 177 | shmobile_smp_init_cpus(ncores); | 126 | #ifdef CONFIG_HOTPLUG_CPU |
| 127 | static int r8a7779_scu_psr_core_disabled(int cpu) | ||
| 128 | { | ||
| 129 | unsigned long mask = 3 << (cpu * 8); | ||
| 130 | |||
| 131 | if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask) | ||
| 132 | return 1; | ||
| 133 | |||
| 134 | return 0; | ||
| 135 | } | ||
| 136 | |||
| 137 | static int r8a7779_cpu_kill(unsigned int cpu) | ||
| 138 | { | ||
| 139 | int k; | ||
| 140 | |||
| 141 | /* this function is running on another CPU than the offline target, | ||
| 142 | * here we need wait for shutdown code in platform_cpu_die() to | ||
| 143 | * finish before asking SoC-specific code to power off the CPU core. | ||
| 144 | */ | ||
| 145 | for (k = 0; k < 1000; k++) { | ||
| 146 | if (r8a7779_scu_psr_core_disabled(cpu)) | ||
| 147 | return r8a7779_platform_cpu_kill(cpu); | ||
| 148 | |||
| 149 | mdelay(1); | ||
| 150 | } | ||
| 151 | |||
| 152 | return 0; | ||
| 153 | } | ||
| 154 | |||
| 155 | static void r8a7779_cpu_die(unsigned int cpu) | ||
| 156 | { | ||
| 157 | dsb(); | ||
| 158 | flush_cache_all(); | ||
| 159 | |||
| 160 | /* disable cache coherency */ | ||
| 161 | scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); | ||
| 162 | |||
| 163 | /* Endless loop until power off from r8a7779_cpu_kill() */ | ||
| 164 | while (1) | ||
| 165 | cpu_do_idle(); | ||
| 166 | } | ||
| 167 | |||
| 168 | static int r8a7779_cpu_disable(unsigned int cpu) | ||
| 169 | { | ||
| 170 | /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */ | ||
| 171 | return cpu == 0 ? -EPERM : 0; | ||
| 178 | } | 172 | } |
| 173 | #endif /* CONFIG_HOTPLUG_CPU */ | ||
| 179 | 174 | ||
| 180 | struct smp_operations r8a7779_smp_ops __initdata = { | 175 | struct smp_operations r8a7779_smp_ops __initdata = { |
| 181 | .smp_init_cpus = r8a7779_smp_init_cpus, | 176 | .smp_init_cpus = r8a7779_smp_init_cpus, |
| @@ -183,7 +178,7 @@ struct smp_operations r8a7779_smp_ops __initdata = { | |||
| 183 | .smp_boot_secondary = r8a7779_boot_secondary, | 178 | .smp_boot_secondary = r8a7779_boot_secondary, |
| 184 | #ifdef CONFIG_HOTPLUG_CPU | 179 | #ifdef CONFIG_HOTPLUG_CPU |
| 185 | .cpu_kill = r8a7779_cpu_kill, | 180 | .cpu_kill = r8a7779_cpu_kill, |
| 186 | .cpu_die = shmobile_cpu_die, | 181 | .cpu_die = r8a7779_cpu_die, |
| 187 | .cpu_disable = shmobile_cpu_disable, | 182 | .cpu_disable = r8a7779_cpu_disable, |
| 188 | #endif | 183 | #endif |
| 189 | }; | 184 | }; |
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index d0f9aca22477..bf79626ee5a4 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c | |||
| @@ -38,26 +38,16 @@ | |||
| 38 | 38 | ||
| 39 | #define PSTR_SHUTDOWN_MODE 3 | 39 | #define PSTR_SHUTDOWN_MODE 3 |
| 40 | 40 | ||
| 41 | static void __iomem *scu_base_addr(void) | 41 | #define SH73A0_SCU_BASE 0xf0000000 |
| 42 | { | ||
| 43 | return (void __iomem *)0xf0000000; | ||
| 44 | } | ||
| 45 | 42 | ||
| 46 | #ifdef CONFIG_HAVE_ARM_TWD | 43 | #ifdef CONFIG_HAVE_ARM_TWD |
| 47 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); | 44 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29); |
| 48 | void __init sh73a0_register_twd(void) | 45 | void __init sh73a0_register_twd(void) |
| 49 | { | 46 | { |
| 50 | twd_local_timer_register(&twd_local_timer); | 47 | twd_local_timer_register(&twd_local_timer); |
| 51 | } | 48 | } |
| 52 | #endif | 49 | #endif |
| 53 | 50 | ||
| 54 | static unsigned int __init sh73a0_get_core_count(void) | ||
| 55 | { | ||
| 56 | void __iomem *scu_base = scu_base_addr(); | ||
| 57 | |||
| 58 | return scu_get_core_count(scu_base); | ||
| 59 | } | ||
| 60 | |||
| 61 | static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) | 51 | static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 62 | { | 52 | { |
| 63 | cpu = cpu_logical_map(cpu); | 53 | cpu = cpu_logical_map(cpu); |
| @@ -72,21 +62,22 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct | |||
| 72 | 62 | ||
| 73 | static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) | 63 | static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) |
| 74 | { | 64 | { |
| 75 | scu_enable(scu_base_addr()); | 65 | scu_enable(shmobile_scu_base); |
| 76 | 66 | ||
| 77 | /* Map the reset vector (in headsmp-sh73a0.S) */ | 67 | /* Map the reset vector (in headsmp-scu.S) */ |
| 78 | __raw_writel(0, APARMBAREA); /* 4k */ | 68 | __raw_writel(0, APARMBAREA); /* 4k */ |
| 79 | __raw_writel(__pa(sh73a0_secondary_vector), SBAR); | 69 | __raw_writel(__pa(shmobile_secondary_vector_scu), SBAR); |
| 80 | 70 | ||
| 81 | /* enable cache coherency on booting CPU */ | 71 | /* enable cache coherency on booting CPU */ |
| 82 | scu_power_mode(scu_base_addr(), SCU_PM_NORMAL); | 72 | scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); |
| 83 | } | 73 | } |
| 84 | 74 | ||
| 85 | static void __init sh73a0_smp_init_cpus(void) | 75 | static void __init sh73a0_smp_init_cpus(void) |
| 86 | { | 76 | { |
| 87 | unsigned int ncores = sh73a0_get_core_count(); | 77 | /* setup sh73a0 specific SCU base */ |
| 78 | shmobile_scu_base = IOMEM(SH73A0_SCU_BASE); | ||
| 88 | 79 | ||
| 89 | shmobile_smp_init_cpus(ncores); | 80 | shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base)); |
| 90 | } | 81 | } |
| 91 | 82 | ||
| 92 | #ifdef CONFIG_HOTPLUG_CPU | 83 | #ifdef CONFIG_HOTPLUG_CPU |
| @@ -122,11 +113,16 @@ static void sh73a0_cpu_die(unsigned int cpu) | |||
| 122 | flush_cache_all(); | 113 | flush_cache_all(); |
| 123 | 114 | ||
| 124 | /* Set power off mode. This takes the CPU out of the MP cluster */ | 115 | /* Set power off mode. This takes the CPU out of the MP cluster */ |
| 125 | scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF); | 116 | scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); |
| 126 | 117 | ||
| 127 | /* Enter shutdown mode */ | 118 | /* Enter shutdown mode */ |
| 128 | cpu_do_idle(); | 119 | cpu_do_idle(); |
| 129 | } | 120 | } |
| 121 | |||
| 122 | static int sh73a0_cpu_disable(unsigned int cpu) | ||
| 123 | { | ||
| 124 | return 0; /* CPU0 and CPU1 supported */ | ||
| 125 | } | ||
| 130 | #endif /* CONFIG_HOTPLUG_CPU */ | 126 | #endif /* CONFIG_HOTPLUG_CPU */ |
| 131 | 127 | ||
| 132 | struct smp_operations sh73a0_smp_ops __initdata = { | 128 | struct smp_operations sh73a0_smp_ops __initdata = { |
| @@ -136,6 +132,6 @@ struct smp_operations sh73a0_smp_ops __initdata = { | |||
| 136 | #ifdef CONFIG_HOTPLUG_CPU | 132 | #ifdef CONFIG_HOTPLUG_CPU |
| 137 | .cpu_kill = sh73a0_cpu_kill, | 133 | .cpu_kill = sh73a0_cpu_kill, |
| 138 | .cpu_die = sh73a0_cpu_die, | 134 | .cpu_die = sh73a0_cpu_die, |
| 139 | .cpu_disable = shmobile_cpu_disable_any, | 135 | .cpu_disable = sh73a0_cpu_disable, |
| 140 | #endif | 136 | #endif |
| 141 | }; | 137 | }; |
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index 315edff610f2..572b8f719ffb 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h | |||
| @@ -20,12 +20,23 @@ | |||
| 20 | #ifndef __MACH_CORE_H | 20 | #ifndef __MACH_CORE_H |
| 21 | #define __MACH_CORE_H | 21 | #define __MACH_CORE_H |
| 22 | 22 | ||
| 23 | #define SOCFPGA_RSTMGR_CTRL 0x04 | ||
| 24 | #define SOCFPGA_RSTMGR_MODPERRST 0x14 | ||
| 25 | #define SOCFPGA_RSTMGR_BRGMODRST 0x1c | ||
| 26 | |||
| 27 | /* System Manager bits */ | ||
| 28 | #define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ | ||
| 29 | #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ | ||
| 30 | |||
| 23 | extern void socfpga_secondary_startup(void); | 31 | extern void socfpga_secondary_startup(void); |
| 24 | extern void __iomem *socfpga_scu_base_addr; | 32 | extern void __iomem *socfpga_scu_base_addr; |
| 25 | 33 | ||
| 26 | extern void socfpga_init_clocks(void); | 34 | extern void socfpga_init_clocks(void); |
| 27 | extern void socfpga_sysmgr_init(void); | 35 | extern void socfpga_sysmgr_init(void); |
| 28 | 36 | ||
| 37 | extern void __iomem *sys_manager_base_addr; | ||
| 38 | extern void __iomem *rst_manager_base_addr; | ||
| 39 | |||
| 29 | extern struct smp_operations socfpga_smp_ops; | 40 | extern struct smp_operations socfpga_smp_ops; |
| 30 | extern char secondary_trampoline, secondary_trampoline_end; | 41 | extern char secondary_trampoline, secondary_trampoline_end; |
| 31 | 42 | ||
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c index ca14d1d5ac7f..b51ce8c7929d 100644 --- a/arch/arm/mach-socfpga/platsmp.c +++ b/arch/arm/mach-socfpga/platsmp.c | |||
| @@ -29,9 +29,6 @@ | |||
| 29 | 29 | ||
| 30 | #include "core.h" | 30 | #include "core.h" |
| 31 | 31 | ||
| 32 | extern void __iomem *sys_manager_base_addr; | ||
| 33 | extern void __iomem *rst_manager_base_addr; | ||
| 34 | |||
| 35 | static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) | 32 | static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 36 | { | 33 | { |
| 37 | int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; | 34 | int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; |
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 1042c023cf24..46a051359f02 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c | |||
| @@ -15,6 +15,7 @@ | |||
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ | 16 | */ |
| 17 | #include <linux/dw_apb_timer.h> | 17 | #include <linux/dw_apb_timer.h> |
| 18 | #include <linux/clk-provider.h> | ||
| 18 | #include <linux/irqchip.h> | 19 | #include <linux/irqchip.h> |
| 19 | #include <linux/of_address.h> | 20 | #include <linux/of_address.h> |
| 20 | #include <linux/of_irq.h> | 21 | #include <linux/of_irq.h> |
| @@ -29,6 +30,7 @@ | |||
| 29 | void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE)); | 30 | void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE)); |
| 30 | void __iomem *sys_manager_base_addr; | 31 | void __iomem *sys_manager_base_addr; |
| 31 | void __iomem *rst_manager_base_addr; | 32 | void __iomem *rst_manager_base_addr; |
| 33 | void __iomem *clk_mgr_base_addr; | ||
| 32 | unsigned long cpu1start_addr; | 34 | unsigned long cpu1start_addr; |
| 33 | 35 | ||
| 34 | static struct map_desc scu_io_desc __initdata = { | 36 | static struct map_desc scu_io_desc __initdata = { |
| @@ -77,6 +79,9 @@ void __init socfpga_sysmgr_init(void) | |||
| 77 | 79 | ||
| 78 | np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr"); | 80 | np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr"); |
| 79 | rst_manager_base_addr = of_iomap(np, 0); | 81 | rst_manager_base_addr = of_iomap(np, 0); |
| 82 | |||
| 83 | np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); | ||
| 84 | clk_mgr_base_addr = of_iomap(np, 0); | ||
| 80 | } | 85 | } |
| 81 | 86 | ||
| 82 | static void __init socfpga_init_irq(void) | 87 | static void __init socfpga_init_irq(void) |
| @@ -87,13 +92,22 @@ static void __init socfpga_init_irq(void) | |||
| 87 | 92 | ||
| 88 | static void socfpga_cyclone5_restart(char mode, const char *cmd) | 93 | static void socfpga_cyclone5_restart(char mode, const char *cmd) |
| 89 | { | 94 | { |
| 90 | /* TODO: */ | 95 | u32 temp; |
| 96 | |||
| 97 | temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); | ||
| 98 | |||
| 99 | if (mode == 'h') | ||
| 100 | temp |= RSTMGR_CTRL_SWCOLDRSTREQ; | ||
| 101 | else | ||
| 102 | temp |= RSTMGR_CTRL_SWWARMRSTREQ; | ||
| 103 | writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); | ||
| 91 | } | 104 | } |
| 92 | 105 | ||
| 93 | static void __init socfpga_cyclone5_init(void) | 106 | static void __init socfpga_cyclone5_init(void) |
| 94 | { | 107 | { |
| 95 | l2x0_of_init(0, ~0UL); | 108 | l2x0_of_init(0, ~0UL); |
| 96 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 109 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
| 110 | of_clk_init(NULL); | ||
| 97 | socfpga_init_clocks(); | 111 | socfpga_init_clocks(); |
| 98 | } | 112 | } |
| 99 | 113 | ||
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index c1970005f805..b78f0d71b328 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile | |||
| @@ -27,6 +27,7 @@ obj-$(CONFIG_SMP) += platsmp.o headsmp.o | |||
| 27 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 27 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
| 28 | obj-$(CONFIG_TEGRA_PCI) += pcie.o | 28 | obj-$(CONFIG_TEGRA_PCI) += pcie.o |
| 29 | 29 | ||
| 30 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o | ||
| 30 | ifeq ($(CONFIG_CPU_IDLE),y) | 31 | ifeq ($(CONFIG_CPU_IDLE),y) |
| 31 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o | 32 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o |
| 32 | endif | 33 | endif |
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index f0315c95c76d..eb1f3c8c74cc 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | #include "common.h" | 33 | #include "common.h" |
| 34 | #include "fuse.h" | 34 | #include "fuse.h" |
| 35 | #include "iomap.h" | 35 | #include "iomap.h" |
| 36 | #include "irq.h" | ||
| 36 | #include "pmc.h" | 37 | #include "pmc.h" |
| 37 | #include "apbio.h" | 38 | #include "apbio.h" |
| 38 | #include "sleep.h" | 39 | #include "sleep.h" |
| @@ -61,8 +62,10 @@ u32 tegra_uart_config[4] = { | |||
| 61 | void __init tegra_dt_init_irq(void) | 62 | void __init tegra_dt_init_irq(void) |
| 62 | { | 63 | { |
| 63 | tegra_clocks_init(); | 64 | tegra_clocks_init(); |
| 65 | tegra_pmc_init(); | ||
| 64 | tegra_init_irq(); | 66 | tegra_init_irq(); |
| 65 | irqchip_init(); | 67 | irqchip_init(); |
| 68 | tegra_legacy_irq_syscore_init(); | ||
| 66 | } | 69 | } |
| 67 | #endif | 70 | #endif |
| 68 | 71 | ||
| @@ -100,12 +103,12 @@ void __init tegra_init_early(void) | |||
| 100 | tegra_apb_io_init(); | 103 | tegra_apb_io_init(); |
| 101 | tegra_init_fuse(); | 104 | tegra_init_fuse(); |
| 102 | tegra_init_cache(); | 105 | tegra_init_cache(); |
| 103 | tegra_pmc_init(); | ||
| 104 | tegra_powergate_init(); | 106 | tegra_powergate_init(); |
| 105 | tegra_hotplug_init(); | 107 | tegra_hotplug_init(); |
| 106 | } | 108 | } |
| 107 | 109 | ||
| 108 | void __init tegra_init_late(void) | 110 | void __init tegra_init_late(void) |
| 109 | { | 111 | { |
| 112 | tegra_init_suspend(); | ||
| 110 | tegra_powergate_debugfs_init(); | 113 | tegra_powergate_debugfs_init(); |
| 111 | } | 114 | } |
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index 590ec25855dd..0cdba8de8c77 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c | |||
| @@ -131,10 +131,6 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, | |||
| 131 | struct cpuidle_driver *drv, | 131 | struct cpuidle_driver *drv, |
| 132 | int index) | 132 | int index) |
| 133 | { | 133 | { |
| 134 | struct cpuidle_state *state = &drv->states[index]; | ||
| 135 | u32 cpu_on_time = state->exit_latency; | ||
| 136 | u32 cpu_off_time = state->target_residency - state->exit_latency; | ||
| 137 | |||
| 138 | while (tegra20_cpu_is_resettable_soon()) | 134 | while (tegra20_cpu_is_resettable_soon()) |
| 139 | cpu_relax(); | 135 | cpu_relax(); |
| 140 | 136 | ||
| @@ -143,7 +139,7 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, | |||
| 143 | 139 | ||
| 144 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); | 140 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); |
| 145 | 141 | ||
| 146 | tegra_idle_lp2_last(cpu_on_time, cpu_off_time); | 142 | tegra_idle_lp2_last(); |
| 147 | 143 | ||
| 148 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); | 144 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); |
| 149 | 145 | ||
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index 9387daeeadc8..3cf9aca5f3ea 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c | |||
| @@ -69,10 +69,6 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev, | |||
| 69 | struct cpuidle_driver *drv, | 69 | struct cpuidle_driver *drv, |
| 70 | int index) | 70 | int index) |
| 71 | { | 71 | { |
| 72 | struct cpuidle_state *state = &drv->states[index]; | ||
| 73 | u32 cpu_on_time = state->exit_latency; | ||
| 74 | u32 cpu_off_time = state->target_residency - state->exit_latency; | ||
| 75 | |||
| 76 | /* All CPUs entering LP2 is not working. | 72 | /* All CPUs entering LP2 is not working. |
| 77 | * Don't let CPU0 enter LP2 when any secondary CPU is online. | 73 | * Don't let CPU0 enter LP2 when any secondary CPU is online. |
| 78 | */ | 74 | */ |
| @@ -83,7 +79,7 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev, | |||
| 83 | 79 | ||
| 84 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); | 80 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); |
| 85 | 81 | ||
| 86 | tegra_idle_lp2_last(cpu_on_time, cpu_off_time); | 82 | tegra_idle_lp2_last(); |
| 87 | 83 | ||
| 88 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); | 84 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); |
| 89 | 85 | ||
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index f7db0782a6b6..e035cd284a6e 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c | |||
| @@ -2,6 +2,7 @@ | |||
| 2 | * arch/arm/mach-tegra/fuse.c | 2 | * arch/arm/mach-tegra/fuse.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2010 Google, Inc. | 4 | * Copyright (C) 2010 Google, Inc. |
| 5 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. | ||
| 5 | * | 6 | * |
| 6 | * Author: | 7 | * Author: |
| 7 | * Colin Cross <ccross@android.com> | 8 | * Colin Cross <ccross@android.com> |
| @@ -137,6 +138,9 @@ void tegra_init_fuse(void) | |||
| 137 | tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT; | 138 | tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT; |
| 138 | tegra_init_speedo_data = &tegra30_init_speedo_data; | 139 | tegra_init_speedo_data = &tegra30_init_speedo_data; |
| 139 | break; | 140 | break; |
| 141 | case TEGRA114: | ||
| 142 | tegra_init_speedo_data = &tegra114_init_speedo_data; | ||
| 143 | break; | ||
| 140 | default: | 144 | default: |
| 141 | pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id); | 145 | pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id); |
| 142 | tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT; | 146 | tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT; |
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h index da78434678c7..aacc00d05980 100644 --- a/arch/arm/mach-tegra/fuse.h +++ b/arch/arm/mach-tegra/fuse.h | |||
| @@ -1,5 +1,6 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2010 Google, Inc. | 2 | * Copyright (C) 2010 Google, Inc. |
| 3 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. | ||
| 3 | * | 4 | * |
| 4 | * Author: | 5 | * Author: |
| 5 | * Colin Cross <ccross@android.com> | 6 | * Colin Cross <ccross@android.com> |
| @@ -66,4 +67,10 @@ void tegra30_init_speedo_data(void); | |||
| 66 | static inline void tegra30_init_speedo_data(void) {} | 67 | static inline void tegra30_init_speedo_data(void) {} |
| 67 | #endif | 68 | #endif |
| 68 | 69 | ||
| 70 | #ifdef CONFIG_ARCH_TEGRA_114_SOC | ||
| 71 | void tegra114_init_speedo_data(void); | ||
| 72 | #else | ||
| 73 | static inline void tegra114_init_speedo_data(void) {} | ||
| 74 | #endif | ||
| 75 | |||
| 69 | #endif | 76 | #endif |
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 1952e82797cc..0de4eed1493d 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c | |||
| @@ -4,7 +4,7 @@ | |||
| 4 | * Author: | 4 | * Author: |
| 5 | * Colin Cross <ccross@android.com> | 5 | * Colin Cross <ccross@android.com> |
| 6 | * | 6 | * |
| 7 | * Copyright (C) 2010, NVIDIA Corporation | 7 | * Copyright (C) 2010,2013, NVIDIA Corporation |
| 8 | * | 8 | * |
| 9 | * This software is licensed under the terms of the GNU General Public | 9 | * This software is licensed under the terms of the GNU General Public |
| 10 | * License version 2, as published by the Free Software Foundation, and | 10 | * License version 2, as published by the Free Software Foundation, and |
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | #include <linux/of.h> | 24 | #include <linux/of.h> |
| 25 | #include <linux/irqchip/arm-gic.h> | 25 | #include <linux/irqchip/arm-gic.h> |
| 26 | #include <linux/syscore_ops.h> | ||
| 26 | 27 | ||
| 27 | #include "board.h" | 28 | #include "board.h" |
| 28 | #include "iomap.h" | 29 | #include "iomap.h" |
| @@ -43,6 +44,7 @@ | |||
| 43 | #define ICTLR_COP_IEP_CLASS 0x3c | 44 | #define ICTLR_COP_IEP_CLASS 0x3c |
| 44 | 45 | ||
| 45 | #define FIRST_LEGACY_IRQ 32 | 46 | #define FIRST_LEGACY_IRQ 32 |
| 47 | #define TEGRA_MAX_NUM_ICTLRS 5 | ||
| 46 | 48 | ||
| 47 | #define SGI_MASK 0xFFFF | 49 | #define SGI_MASK 0xFFFF |
| 48 | 50 | ||
| @@ -56,6 +58,15 @@ static void __iomem *ictlr_reg_base[] = { | |||
| 56 | IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE), | 58 | IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE), |
| 57 | }; | 59 | }; |
| 58 | 60 | ||
| 61 | #ifdef CONFIG_PM_SLEEP | ||
| 62 | static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS]; | ||
| 63 | static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS]; | ||
| 64 | static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS]; | ||
| 65 | static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS]; | ||
| 66 | |||
| 67 | static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS]; | ||
| 68 | #endif | ||
| 69 | |||
| 59 | bool tegra_pending_sgi(void) | 70 | bool tegra_pending_sgi(void) |
| 60 | { | 71 | { |
| 61 | u32 pending_set; | 72 | u32 pending_set; |
| @@ -125,6 +136,87 @@ static int tegra_retrigger(struct irq_data *d) | |||
| 125 | return 1; | 136 | return 1; |
| 126 | } | 137 | } |
| 127 | 138 | ||
| 139 | #ifdef CONFIG_PM_SLEEP | ||
| 140 | static int tegra_set_wake(struct irq_data *d, unsigned int enable) | ||
| 141 | { | ||
| 142 | u32 irq = d->irq; | ||
| 143 | u32 index, mask; | ||
| 144 | |||
| 145 | if (irq < FIRST_LEGACY_IRQ || | ||
| 146 | irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32) | ||
| 147 | return -EINVAL; | ||
| 148 | |||
| 149 | index = ((irq - FIRST_LEGACY_IRQ) / 32); | ||
| 150 | mask = BIT((irq - FIRST_LEGACY_IRQ) % 32); | ||
| 151 | if (enable) | ||
| 152 | ictlr_wake_mask[index] |= mask; | ||
| 153 | else | ||
| 154 | ictlr_wake_mask[index] &= ~mask; | ||
| 155 | |||
| 156 | return 0; | ||
| 157 | } | ||
| 158 | |||
| 159 | static int tegra_legacy_irq_suspend(void) | ||
| 160 | { | ||
| 161 | unsigned long flags; | ||
| 162 | int i; | ||
| 163 | |||
| 164 | local_irq_save(flags); | ||
| 165 | for (i = 0; i < num_ictlrs; i++) { | ||
| 166 | void __iomem *ictlr = ictlr_reg_base[i]; | ||
| 167 | /* Save interrupt state */ | ||
| 168 | cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER); | ||
| 169 | cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS); | ||
| 170 | cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER); | ||
| 171 | cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS); | ||
| 172 | |||
| 173 | /* Disable COP interrupts */ | ||
| 174 | writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); | ||
| 175 | |||
| 176 | /* Disable CPU interrupts */ | ||
| 177 | writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR); | ||
| 178 | |||
| 179 | /* Enable the wakeup sources of ictlr */ | ||
| 180 | writel_relaxed(ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET); | ||
| 181 | } | ||
| 182 | local_irq_restore(flags); | ||
| 183 | |||
| 184 | return 0; | ||
| 185 | } | ||
| 186 | |||
| 187 | static void tegra_legacy_irq_resume(void) | ||
| 188 | { | ||
| 189 | unsigned long flags; | ||
| 190 | int i; | ||
| 191 | |||
| 192 | local_irq_save(flags); | ||
| 193 | for (i = 0; i < num_ictlrs; i++) { | ||
| 194 | void __iomem *ictlr = ictlr_reg_base[i]; | ||
| 195 | writel_relaxed(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS); | ||
| 196 | writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR); | ||
| 197 | writel_relaxed(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET); | ||
| 198 | writel_relaxed(cop_iep[i], ictlr + ICTLR_COP_IEP_CLASS); | ||
| 199 | writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); | ||
| 200 | writel_relaxed(cop_ier[i], ictlr + ICTLR_COP_IER_SET); | ||
| 201 | } | ||
| 202 | local_irq_restore(flags); | ||
| 203 | } | ||
| 204 | |||
| 205 | static struct syscore_ops tegra_legacy_irq_syscore_ops = { | ||
| 206 | .suspend = tegra_legacy_irq_suspend, | ||
| 207 | .resume = tegra_legacy_irq_resume, | ||
| 208 | }; | ||
| 209 | |||
| 210 | int tegra_legacy_irq_syscore_init(void) | ||
| 211 | { | ||
| 212 | register_syscore_ops(&tegra_legacy_irq_syscore_ops); | ||
| 213 | |||
| 214 | return 0; | ||
| 215 | } | ||
| 216 | #else | ||
| 217 | #define tegra_set_wake NULL | ||
| 218 | #endif | ||
| 219 | |||
| 128 | void __init tegra_init_irq(void) | 220 | void __init tegra_init_irq(void) |
| 129 | { | 221 | { |
| 130 | int i; | 222 | int i; |
| @@ -150,6 +242,8 @@ void __init tegra_init_irq(void) | |||
| 150 | gic_arch_extn.irq_mask = tegra_mask; | 242 | gic_arch_extn.irq_mask = tegra_mask; |
| 151 | gic_arch_extn.irq_unmask = tegra_unmask; | 243 | gic_arch_extn.irq_unmask = tegra_unmask; |
| 152 | gic_arch_extn.irq_retrigger = tegra_retrigger; | 244 | gic_arch_extn.irq_retrigger = tegra_retrigger; |
| 245 | gic_arch_extn.irq_set_wake = tegra_set_wake; | ||
| 246 | gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND; | ||
| 153 | 247 | ||
| 154 | /* | 248 | /* |
| 155 | * Check if there is a devicetree present, since the GIC will be | 249 | * Check if there is a devicetree present, since the GIC will be |
diff --git a/arch/arm/mach-tegra/irq.h b/arch/arm/mach-tegra/irq.h index 5142649bba05..bc05ce5613fb 100644 --- a/arch/arm/mach-tegra/irq.h +++ b/arch/arm/mach-tegra/irq.h | |||
| @@ -19,4 +19,10 @@ | |||
| 19 | 19 | ||
| 20 | bool tegra_pending_sgi(void); | 20 | bool tegra_pending_sgi(void); |
| 21 | 21 | ||
| 22 | #ifdef CONFIG_PM_SLEEP | ||
| 23 | int tegra_legacy_irq_syscore_init(void); | ||
| 24 | #else | ||
| 25 | static inline int tegra_legacy_irq_syscore_init(void) { return 0; } | ||
| 26 | #endif | ||
| 27 | |||
| 22 | #endif | 28 | #endif |
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index c31db797e199..0c4963bd4b44 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c | |||
| @@ -138,6 +138,12 @@ remove_clamps: | |||
| 138 | return 0; | 138 | return 0; |
| 139 | } | 139 | } |
| 140 | 140 | ||
| 141 | static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle) | ||
| 142 | { | ||
| 143 | cpu = cpu_logical_map(cpu); | ||
| 144 | return tegra_pmc_cpu_power_on(cpu); | ||
| 145 | } | ||
| 146 | |||
| 141 | static int __cpuinit tegra_boot_secondary(unsigned int cpu, | 147 | static int __cpuinit tegra_boot_secondary(unsigned int cpu, |
| 142 | struct task_struct *idle) | 148 | struct task_struct *idle) |
| 143 | { | 149 | { |
| @@ -145,6 +151,8 @@ static int __cpuinit tegra_boot_secondary(unsigned int cpu, | |||
| 145 | return tegra20_boot_secondary(cpu, idle); | 151 | return tegra20_boot_secondary(cpu, idle); |
| 146 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30) | 152 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30) |
| 147 | return tegra30_boot_secondary(cpu, idle); | 153 | return tegra30_boot_secondary(cpu, idle); |
| 154 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114) | ||
| 155 | return tegra114_boot_secondary(cpu, idle); | ||
| 148 | 156 | ||
| 149 | return -EINVAL; | 157 | return -EINVAL; |
| 150 | } | 158 | } |
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 891fb70d0aa7..45cf52c7e528 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c | |||
| @@ -22,7 +22,7 @@ | |||
| 22 | #include <linux/cpumask.h> | 22 | #include <linux/cpumask.h> |
| 23 | #include <linux/delay.h> | 23 | #include <linux/delay.h> |
| 24 | #include <linux/cpu_pm.h> | 24 | #include <linux/cpu_pm.h> |
| 25 | #include <linux/clk.h> | 25 | #include <linux/suspend.h> |
| 26 | #include <linux/err.h> | 26 | #include <linux/err.h> |
| 27 | #include <linux/clk/tegra.h> | 27 | #include <linux/clk/tegra.h> |
| 28 | 28 | ||
| @@ -37,52 +37,13 @@ | |||
| 37 | #include "reset.h" | 37 | #include "reset.h" |
| 38 | #include "flowctrl.h" | 38 | #include "flowctrl.h" |
| 39 | #include "fuse.h" | 39 | #include "fuse.h" |
| 40 | #include "pmc.h" | ||
| 40 | #include "sleep.h" | 41 | #include "sleep.h" |
| 41 | 42 | ||
| 42 | #define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ | ||
| 43 | |||
| 44 | #define PMC_CTRL 0x0 | ||
| 45 | #define PMC_CPUPWRGOOD_TIMER 0xc8 | ||
| 46 | #define PMC_CPUPWROFF_TIMER 0xcc | ||
| 47 | |||
| 48 | #ifdef CONFIG_PM_SLEEP | 43 | #ifdef CONFIG_PM_SLEEP |
| 49 | static DEFINE_SPINLOCK(tegra_lp2_lock); | 44 | static DEFINE_SPINLOCK(tegra_lp2_lock); |
| 50 | static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); | ||
| 51 | static struct clk *tegra_pclk; | ||
| 52 | void (*tegra_tear_down_cpu)(void); | 45 | void (*tegra_tear_down_cpu)(void); |
| 53 | 46 | ||
| 54 | static void set_power_timers(unsigned long us_on, unsigned long us_off) | ||
| 55 | { | ||
| 56 | unsigned long long ticks; | ||
| 57 | unsigned long long pclk; | ||
| 58 | unsigned long rate; | ||
| 59 | static unsigned long tegra_last_pclk; | ||
| 60 | |||
| 61 | if (tegra_pclk == NULL) { | ||
| 62 | tegra_pclk = clk_get_sys(NULL, "pclk"); | ||
| 63 | WARN_ON(IS_ERR(tegra_pclk)); | ||
| 64 | } | ||
| 65 | |||
| 66 | rate = clk_get_rate(tegra_pclk); | ||
| 67 | |||
| 68 | if (WARN_ON_ONCE(rate <= 0)) | ||
| 69 | pclk = 100000000; | ||
| 70 | else | ||
| 71 | pclk = rate; | ||
| 72 | |||
| 73 | if ((rate != tegra_last_pclk)) { | ||
| 74 | ticks = (us_on * pclk) + 999999ull; | ||
| 75 | do_div(ticks, 1000000); | ||
| 76 | writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER); | ||
| 77 | |||
| 78 | ticks = (us_off * pclk) + 999999ull; | ||
| 79 | do_div(ticks, 1000000); | ||
| 80 | writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER); | ||
| 81 | wmb(); | ||
| 82 | } | ||
| 83 | tegra_last_pclk = pclk; | ||
| 84 | } | ||
| 85 | |||
| 86 | /* | 47 | /* |
| 87 | * restore_cpu_complex | 48 | * restore_cpu_complex |
| 88 | * | 49 | * |
| @@ -178,16 +139,9 @@ static int tegra_sleep_cpu(unsigned long v2p) | |||
| 178 | return 0; | 139 | return 0; |
| 179 | } | 140 | } |
| 180 | 141 | ||
| 181 | void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time) | 142 | void tegra_idle_lp2_last(void) |
| 182 | { | 143 | { |
| 183 | u32 mode; | 144 | tegra_pmc_pm_set(TEGRA_SUSPEND_LP2); |
| 184 | |||
| 185 | /* Only the last cpu down does the final suspend steps */ | ||
| 186 | mode = readl(pmc + PMC_CTRL); | ||
| 187 | mode |= TEGRA_POWER_CPU_PWRREQ_OE; | ||
| 188 | writel(mode, pmc + PMC_CTRL); | ||
| 189 | |||
| 190 | set_power_timers(cpu_on_time, cpu_off_time); | ||
| 191 | 145 | ||
| 192 | cpu_cluster_pm_enter(); | 146 | cpu_cluster_pm_enter(); |
| 193 | suspend_cpu_complex(); | 147 | suspend_cpu_complex(); |
| @@ -197,4 +151,81 @@ void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time) | |||
| 197 | restore_cpu_complex(); | 151 | restore_cpu_complex(); |
| 198 | cpu_cluster_pm_exit(); | 152 | cpu_cluster_pm_exit(); |
| 199 | } | 153 | } |
| 154 | |||
| 155 | enum tegra_suspend_mode tegra_pm_validate_suspend_mode( | ||
| 156 | enum tegra_suspend_mode mode) | ||
| 157 | { | ||
| 158 | /* Tegra114 didn't support any suspending mode yet. */ | ||
| 159 | if (tegra_chip_id == TEGRA114) | ||
| 160 | return TEGRA_SUSPEND_NONE; | ||
| 161 | |||
| 162 | /* | ||
| 163 | * The Tegra devices only support suspending to LP2 currently. | ||
| 164 | */ | ||
| 165 | if (mode > TEGRA_SUSPEND_LP2) | ||
| 166 | return TEGRA_SUSPEND_LP2; | ||
| 167 | |||
| 168 | return mode; | ||
| 169 | } | ||
| 170 | |||
| 171 | static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = { | ||
| 172 | [TEGRA_SUSPEND_NONE] = "none", | ||
| 173 | [TEGRA_SUSPEND_LP2] = "LP2", | ||
| 174 | [TEGRA_SUSPEND_LP1] = "LP1", | ||
| 175 | [TEGRA_SUSPEND_LP0] = "LP0", | ||
| 176 | }; | ||
| 177 | |||
| 178 | static int __cpuinit tegra_suspend_enter(suspend_state_t state) | ||
| 179 | { | ||
| 180 | enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode(); | ||
| 181 | |||
| 182 | if (WARN_ON(mode < TEGRA_SUSPEND_NONE || | ||
| 183 | mode >= TEGRA_MAX_SUSPEND_MODE)) | ||
| 184 | return -EINVAL; | ||
| 185 | |||
| 186 | pr_info("Entering suspend state %s\n", lp_state[mode]); | ||
| 187 | |||
| 188 | tegra_pmc_pm_set(mode); | ||
| 189 | |||
| 190 | local_fiq_disable(); | ||
| 191 | |||
| 192 | suspend_cpu_complex(); | ||
| 193 | switch (mode) { | ||
| 194 | case TEGRA_SUSPEND_LP2: | ||
| 195 | tegra_set_cpu_in_lp2(0); | ||
| 196 | break; | ||
| 197 | default: | ||
| 198 | break; | ||
| 199 | } | ||
| 200 | |||
| 201 | cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); | ||
| 202 | |||
| 203 | switch (mode) { | ||
| 204 | case TEGRA_SUSPEND_LP2: | ||
| 205 | tegra_clear_cpu_in_lp2(0); | ||
| 206 | break; | ||
| 207 | default: | ||
| 208 | break; | ||
| 209 | } | ||
| 210 | restore_cpu_complex(); | ||
| 211 | |||
| 212 | local_fiq_enable(); | ||
| 213 | |||
| 214 | return 0; | ||
| 215 | } | ||
| 216 | |||
| 217 | static const struct platform_suspend_ops tegra_suspend_ops = { | ||
| 218 | .valid = suspend_valid_only_mem, | ||
| 219 | .enter = tegra_suspend_enter, | ||
| 220 | }; | ||
| 221 | |||
| 222 | void __init tegra_init_suspend(void) | ||
| 223 | { | ||
| 224 | if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE) | ||
| 225 | return; | ||
| 226 | |||
| 227 | tegra_pmc_suspend_init(); | ||
| 228 | |||
| 229 | suspend_set_ops(&tegra_suspend_ops); | ||
| 230 | } | ||
| 200 | #endif | 231 | #endif |
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 787335cc964c..778a4aa7c3fa 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h | |||
| @@ -21,6 +21,8 @@ | |||
| 21 | #ifndef _MACH_TEGRA_PM_H_ | 21 | #ifndef _MACH_TEGRA_PM_H_ |
| 22 | #define _MACH_TEGRA_PM_H_ | 22 | #define _MACH_TEGRA_PM_H_ |
| 23 | 23 | ||
| 24 | #include "pmc.h" | ||
| 25 | |||
| 24 | extern unsigned long l2x0_saved_regs_addr; | 26 | extern unsigned long l2x0_saved_regs_addr; |
| 25 | 27 | ||
| 26 | void save_cpu_arch_register(void); | 28 | void save_cpu_arch_register(void); |
| @@ -29,7 +31,20 @@ void restore_cpu_arch_register(void); | |||
| 29 | void tegra_clear_cpu_in_lp2(int phy_cpu_id); | 31 | void tegra_clear_cpu_in_lp2(int phy_cpu_id); |
| 30 | bool tegra_set_cpu_in_lp2(int phy_cpu_id); | 32 | bool tegra_set_cpu_in_lp2(int phy_cpu_id); |
| 31 | 33 | ||
| 32 | void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time); | 34 | void tegra_idle_lp2_last(void); |
| 33 | extern void (*tegra_tear_down_cpu)(void); | 35 | extern void (*tegra_tear_down_cpu)(void); |
| 34 | 36 | ||
| 37 | #ifdef CONFIG_PM_SLEEP | ||
| 38 | enum tegra_suspend_mode tegra_pm_validate_suspend_mode( | ||
| 39 | enum tegra_suspend_mode mode); | ||
| 40 | void tegra_init_suspend(void); | ||
| 41 | #else | ||
| 42 | static inline enum tegra_suspend_mode tegra_pm_validate_suspend_mode( | ||
| 43 | enum tegra_suspend_mode mode) | ||
| 44 | { | ||
| 45 | return TEGRA_SUSPEND_NONE; | ||
| 46 | } | ||
| 47 | static inline void tegra_init_suspend(void) {} | ||
| 48 | #endif | ||
| 49 | |||
| 35 | #endif /* _MACH_TEGRA_PM_H_ */ | 50 | #endif /* _MACH_TEGRA_PM_H_ */ |
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index b30e921cc3a9..32360e540ce6 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c | |||
| @@ -16,10 +16,20 @@ | |||
| 16 | */ | 16 | */ |
| 17 | 17 | ||
| 18 | #include <linux/kernel.h> | 18 | #include <linux/kernel.h> |
| 19 | #include <linux/clk.h> | ||
| 19 | #include <linux/io.h> | 20 | #include <linux/io.h> |
| 20 | #include <linux/of.h> | 21 | #include <linux/of.h> |
| 21 | #include <linux/of_address.h> | 22 | #include <linux/of_address.h> |
| 22 | 23 | ||
| 24 | #include "fuse.h" | ||
| 25 | #include "pm.h" | ||
| 26 | #include "pmc.h" | ||
| 27 | #include "sleep.h" | ||
| 28 | |||
| 29 | #define TEGRA_POWER_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */ | ||
| 30 | #define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */ | ||
| 31 | #define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ | ||
| 32 | |||
| 23 | #define PMC_CTRL 0x0 | 33 | #define PMC_CTRL 0x0 |
| 24 | #define PMC_CTRL_INTR_LOW (1 << 17) | 34 | #define PMC_CTRL_INTR_LOW (1 << 17) |
| 25 | #define PMC_PWRGATE_TOGGLE 0x30 | 35 | #define PMC_PWRGATE_TOGGLE 0x30 |
| @@ -27,6 +37,9 @@ | |||
| 27 | #define PMC_REMOVE_CLAMPING 0x34 | 37 | #define PMC_REMOVE_CLAMPING 0x34 |
| 28 | #define PMC_PWRGATE_STATUS 0x38 | 38 | #define PMC_PWRGATE_STATUS 0x38 |
| 29 | 39 | ||
| 40 | #define PMC_CPUPWRGOOD_TIMER 0xc8 | ||
| 41 | #define PMC_CPUPWROFF_TIMER 0xcc | ||
| 42 | |||
| 30 | #define TEGRA_POWERGATE_PCIE 3 | 43 | #define TEGRA_POWERGATE_PCIE 3 |
| 31 | #define TEGRA_POWERGATE_VDEC 4 | 44 | #define TEGRA_POWERGATE_VDEC 4 |
| 32 | #define TEGRA_POWERGATE_CPU1 9 | 45 | #define TEGRA_POWERGATE_CPU1 9 |
| @@ -43,6 +56,23 @@ static DEFINE_SPINLOCK(tegra_powergate_lock); | |||
| 43 | 56 | ||
| 44 | static void __iomem *tegra_pmc_base; | 57 | static void __iomem *tegra_pmc_base; |
| 45 | static bool tegra_pmc_invert_interrupt; | 58 | static bool tegra_pmc_invert_interrupt; |
| 59 | static struct clk *tegra_pclk; | ||
| 60 | |||
| 61 | struct pmc_pm_data { | ||
| 62 | u32 cpu_good_time; /* CPU power good time in uS */ | ||
| 63 | u32 cpu_off_time; /* CPU power off time in uS */ | ||
| 64 | u32 core_osc_time; /* Core power good osc time in uS */ | ||
| 65 | u32 core_pmu_time; /* Core power good pmu time in uS */ | ||
| 66 | u32 core_off_time; /* Core power off time in uS */ | ||
| 67 | bool corereq_high; /* Core power request active-high */ | ||
| 68 | bool sysclkreq_high; /* System clock request active-high */ | ||
| 69 | bool combined_req; /* Combined pwr req for CPU & Core */ | ||
| 70 | bool cpu_pwr_good_en; /* CPU power good signal is enabled */ | ||
| 71 | u32 lp0_vec_phy_addr; /* The phy addr of LP0 warm boot code */ | ||
| 72 | u32 lp0_vec_size; /* The size of LP0 warm boot code */ | ||
| 73 | enum tegra_suspend_mode suspend_mode; | ||
| 74 | }; | ||
| 75 | static struct pmc_pm_data pmc_pm_data; | ||
| 46 | 76 | ||
| 47 | static inline u32 tegra_pmc_readl(u32 reg) | 77 | static inline u32 tegra_pmc_readl(u32 reg) |
| 48 | { | 78 | { |
| @@ -133,6 +163,70 @@ int tegra_pmc_cpu_remove_clamping(int cpuid) | |||
| 133 | return tegra_pmc_powergate_remove_clamping(id); | 163 | return tegra_pmc_powergate_remove_clamping(id); |
| 134 | } | 164 | } |
| 135 | 165 | ||
| 166 | #ifdef CONFIG_PM_SLEEP | ||
| 167 | static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate) | ||
| 168 | { | ||
| 169 | unsigned long long ticks; | ||
| 170 | unsigned long long pclk; | ||
| 171 | static unsigned long tegra_last_pclk; | ||
| 172 | |||
| 173 | if (WARN_ON_ONCE(rate <= 0)) | ||
| 174 | pclk = 100000000; | ||
| 175 | else | ||
| 176 | pclk = rate; | ||
| 177 | |||
| 178 | if ((rate != tegra_last_pclk)) { | ||
| 179 | ticks = (us_on * pclk) + 999999ull; | ||
| 180 | do_div(ticks, 1000000); | ||
| 181 | tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER); | ||
| 182 | |||
| 183 | ticks = (us_off * pclk) + 999999ull; | ||
| 184 | do_div(ticks, 1000000); | ||
| 185 | tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER); | ||
| 186 | wmb(); | ||
| 187 | } | ||
| 188 | tegra_last_pclk = pclk; | ||
| 189 | } | ||
| 190 | |||
| 191 | enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) | ||
| 192 | { | ||
| 193 | return pmc_pm_data.suspend_mode; | ||
| 194 | } | ||
| 195 | |||
| 196 | void tegra_pmc_pm_set(enum tegra_suspend_mode mode) | ||
| 197 | { | ||
| 198 | u32 reg; | ||
| 199 | unsigned long rate = 0; | ||
| 200 | |||
| 201 | reg = tegra_pmc_readl(PMC_CTRL); | ||
| 202 | reg |= TEGRA_POWER_CPU_PWRREQ_OE; | ||
| 203 | reg &= ~TEGRA_POWER_EFFECT_LP0; | ||
| 204 | |||
| 205 | switch (mode) { | ||
| 206 | case TEGRA_SUSPEND_LP2: | ||
| 207 | rate = clk_get_rate(tegra_pclk); | ||
| 208 | break; | ||
| 209 | default: | ||
| 210 | break; | ||
| 211 | } | ||
| 212 | |||
| 213 | set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time, | ||
| 214 | rate); | ||
| 215 | |||
| 216 | tegra_pmc_writel(reg, PMC_CTRL); | ||
| 217 | } | ||
| 218 | |||
| 219 | void tegra_pmc_suspend_init(void) | ||
| 220 | { | ||
| 221 | u32 reg; | ||
| 222 | |||
| 223 | /* Always enable CPU power request */ | ||
| 224 | reg = tegra_pmc_readl(PMC_CTRL); | ||
| 225 | reg |= TEGRA_POWER_CPU_PWRREQ_OE; | ||
| 226 | tegra_pmc_writel(reg, PMC_CTRL); | ||
| 227 | } | ||
| 228 | #endif | ||
| 229 | |||
| 136 | static const struct of_device_id matches[] __initconst = { | 230 | static const struct of_device_id matches[] __initconst = { |
| 137 | { .compatible = "nvidia,tegra114-pmc" }, | 231 | { .compatible = "nvidia,tegra114-pmc" }, |
| 138 | { .compatible = "nvidia,tegra30-pmc" }, | 232 | { .compatible = "nvidia,tegra30-pmc" }, |
| @@ -143,6 +237,10 @@ static const struct of_device_id matches[] __initconst = { | |||
| 143 | static void tegra_pmc_parse_dt(void) | 237 | static void tegra_pmc_parse_dt(void) |
| 144 | { | 238 | { |
| 145 | struct device_node *np; | 239 | struct device_node *np; |
| 240 | u32 prop; | ||
| 241 | enum tegra_suspend_mode suspend_mode; | ||
| 242 | u32 core_good_time[2] = {0, 0}; | ||
| 243 | u32 lp0_vec[2] = {0, 0}; | ||
| 146 | 244 | ||
| 147 | np = of_find_matching_node(NULL, matches); | 245 | np = of_find_matching_node(NULL, matches); |
| 148 | BUG_ON(!np); | 246 | BUG_ON(!np); |
| @@ -151,6 +249,70 @@ static void tegra_pmc_parse_dt(void) | |||
| 151 | 249 | ||
| 152 | tegra_pmc_invert_interrupt = of_property_read_bool(np, | 250 | tegra_pmc_invert_interrupt = of_property_read_bool(np, |
| 153 | "nvidia,invert-interrupt"); | 251 | "nvidia,invert-interrupt"); |
| 252 | tegra_pclk = of_clk_get_by_name(np, "pclk"); | ||
| 253 | WARN_ON(IS_ERR(tegra_pclk)); | ||
| 254 | |||
| 255 | /* Grabbing the power management configurations */ | ||
| 256 | if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) { | ||
| 257 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
| 258 | } else { | ||
| 259 | switch (prop) { | ||
| 260 | case 0: | ||
| 261 | suspend_mode = TEGRA_SUSPEND_LP0; | ||
| 262 | break; | ||
| 263 | case 1: | ||
| 264 | suspend_mode = TEGRA_SUSPEND_LP1; | ||
| 265 | break; | ||
| 266 | case 2: | ||
| 267 | suspend_mode = TEGRA_SUSPEND_LP2; | ||
| 268 | break; | ||
| 269 | default: | ||
| 270 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
| 271 | break; | ||
| 272 | } | ||
| 273 | } | ||
| 274 | suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode); | ||
| 275 | |||
| 276 | if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop)) | ||
| 277 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
| 278 | pmc_pm_data.cpu_good_time = prop; | ||
| 279 | |||
| 280 | if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop)) | ||
| 281 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
| 282 | pmc_pm_data.cpu_off_time = prop; | ||
| 283 | |||
| 284 | if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", | ||
| 285 | core_good_time, ARRAY_SIZE(core_good_time))) | ||
| 286 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
| 287 | pmc_pm_data.core_osc_time = core_good_time[0]; | ||
| 288 | pmc_pm_data.core_pmu_time = core_good_time[1]; | ||
| 289 | |||
| 290 | if (of_property_read_u32(np, "nvidia,core-pwr-off-time", | ||
| 291 | &prop)) | ||
| 292 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
| 293 | pmc_pm_data.core_off_time = prop; | ||
| 294 | |||
| 295 | pmc_pm_data.corereq_high = of_property_read_bool(np, | ||
| 296 | "nvidia,core-power-req-active-high"); | ||
| 297 | |||
| 298 | pmc_pm_data.sysclkreq_high = of_property_read_bool(np, | ||
| 299 | "nvidia,sys-clock-req-active-high"); | ||
| 300 | |||
| 301 | pmc_pm_data.combined_req = of_property_read_bool(np, | ||
| 302 | "nvidia,combined-power-req"); | ||
| 303 | |||
| 304 | pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np, | ||
| 305 | "nvidia,cpu-pwr-good-en"); | ||
| 306 | |||
| 307 | if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec, | ||
| 308 | ARRAY_SIZE(lp0_vec))) | ||
| 309 | if (suspend_mode == TEGRA_SUSPEND_LP0) | ||
| 310 | suspend_mode = TEGRA_SUSPEND_LP1; | ||
| 311 | |||
| 312 | pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0]; | ||
| 313 | pmc_pm_data.lp0_vec_size = lp0_vec[1]; | ||
| 314 | |||
| 315 | pmc_pm_data.suspend_mode = suspend_mode; | ||
| 154 | } | 316 | } |
| 155 | 317 | ||
| 156 | void __init tegra_pmc_init(void) | 318 | void __init tegra_pmc_init(void) |
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h index 7d44710368be..e1c2df272f7d 100644 --- a/arch/arm/mach-tegra/pmc.h +++ b/arch/arm/mach-tegra/pmc.h | |||
| @@ -18,6 +18,20 @@ | |||
| 18 | #ifndef __MACH_TEGRA_PMC_H | 18 | #ifndef __MACH_TEGRA_PMC_H |
| 19 | #define __MACH_TEGRA_PMC_H | 19 | #define __MACH_TEGRA_PMC_H |
| 20 | 20 | ||
| 21 | enum tegra_suspend_mode { | ||
| 22 | TEGRA_SUSPEND_NONE = 0, | ||
| 23 | TEGRA_SUSPEND_LP2, /* CPU voltage off */ | ||
| 24 | TEGRA_SUSPEND_LP1, /* CPU voltage off, DRAM self-refresh */ | ||
| 25 | TEGRA_SUSPEND_LP0, /* CPU + core voltage off, DRAM self-refresh */ | ||
| 26 | TEGRA_MAX_SUSPEND_MODE, | ||
| 27 | }; | ||
| 28 | |||
| 29 | #ifdef CONFIG_PM_SLEEP | ||
| 30 | enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void); | ||
| 31 | void tegra_pmc_pm_set(enum tegra_suspend_mode mode); | ||
| 32 | void tegra_pmc_suspend_init(void); | ||
| 33 | #endif | ||
| 34 | |||
| 21 | bool tegra_pmc_cpu_is_powered(int cpuid); | 35 | bool tegra_pmc_cpu_is_powered(int cpuid); |
| 22 | int tegra_pmc_cpu_power_on(int cpuid); | 36 | int tegra_pmc_cpu_power_on(int cpuid); |
| 23 | int tegra_pmc_cpu_remove_clamping(int cpuid); | 37 | int tegra_pmc_cpu_remove_clamping(int cpuid); |
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 27232c901a22..84deeab23ee7 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c | |||
| @@ -33,6 +33,8 @@ | |||
| 33 | #include <linux/io.h> | 33 | #include <linux/io.h> |
| 34 | #include <linux/i2c.h> | 34 | #include <linux/i2c.h> |
| 35 | #include <linux/i2c-tegra.h> | 35 | #include <linux/i2c-tegra.h> |
| 36 | #include <linux/slab.h> | ||
| 37 | #include <linux/sys_soc.h> | ||
| 36 | #include <linux/usb/tegra_usb_phy.h> | 38 | #include <linux/usb/tegra_usb_phy.h> |
| 37 | 39 | ||
| 38 | #include <asm/mach-types.h> | 40 | #include <asm/mach-types.h> |
| @@ -42,6 +44,7 @@ | |||
| 42 | 44 | ||
| 43 | #include "board.h" | 45 | #include "board.h" |
| 44 | #include "common.h" | 46 | #include "common.h" |
| 47 | #include "fuse.h" | ||
| 45 | #include "iomap.h" | 48 | #include "iomap.h" |
| 46 | 49 | ||
| 47 | static struct tegra_ehci_platform_data tegra_ehci1_pdata = { | 50 | static struct tegra_ehci_platform_data tegra_ehci1_pdata = { |
| @@ -80,12 +83,36 @@ static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { | |||
| 80 | 83 | ||
| 81 | static void __init tegra_dt_init(void) | 84 | static void __init tegra_dt_init(void) |
| 82 | { | 85 | { |
| 86 | struct soc_device_attribute *soc_dev_attr; | ||
| 87 | struct soc_device *soc_dev; | ||
| 88 | struct device *parent = NULL; | ||
| 89 | |||
| 90 | soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); | ||
| 91 | if (!soc_dev_attr) | ||
| 92 | goto out; | ||
| 93 | |||
| 94 | soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra"); | ||
| 95 | soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_revision); | ||
| 96 | soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%d", tegra_chip_id); | ||
| 97 | |||
| 98 | soc_dev = soc_device_register(soc_dev_attr); | ||
| 99 | if (IS_ERR(soc_dev)) { | ||
| 100 | kfree(soc_dev_attr->family); | ||
| 101 | kfree(soc_dev_attr->revision); | ||
| 102 | kfree(soc_dev_attr->soc_id); | ||
| 103 | kfree(soc_dev_attr); | ||
| 104 | goto out; | ||
| 105 | } | ||
| 106 | |||
| 107 | parent = soc_device_to_device(soc_dev); | ||
| 108 | |||
| 83 | /* | 109 | /* |
| 84 | * Finished with the static registrations now; fill in the missing | 110 | * Finished with the static registrations now; fill in the missing |
| 85 | * devices | 111 | * devices |
| 86 | */ | 112 | */ |
| 113 | out: | ||
| 87 | of_platform_populate(NULL, of_default_bus_match_table, | 114 | of_platform_populate(NULL, of_default_bus_match_table, |
| 88 | tegra20_auxdata_lookup, NULL); | 115 | tegra20_auxdata_lookup, parent); |
| 89 | } | 116 | } |
| 90 | 117 | ||
| 91 | static void __init trimslice_init(void) | 118 | static void __init trimslice_init(void) |
diff --git a/arch/arm/mach-tegra/tegra114_speedo.c b/arch/arm/mach-tegra/tegra114_speedo.c new file mode 100644 index 000000000000..5218d4853cd3 --- /dev/null +++ b/arch/arm/mach-tegra/tegra114_speedo.c | |||
| @@ -0,0 +1,104 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it | ||
| 5 | * under the terms and conditions of the GNU General Public License, | ||
| 6 | * version 2, as published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 11 | * more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/bug.h> | ||
| 19 | |||
| 20 | #include "fuse.h" | ||
| 21 | |||
| 22 | #define CORE_PROCESS_CORNERS_NUM 2 | ||
| 23 | #define CPU_PROCESS_CORNERS_NUM 2 | ||
| 24 | |||
| 25 | enum { | ||
| 26 | THRESHOLD_INDEX_0, | ||
| 27 | THRESHOLD_INDEX_1, | ||
| 28 | THRESHOLD_INDEX_COUNT, | ||
| 29 | }; | ||
| 30 | |||
| 31 | static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = { | ||
| 32 | {1123, UINT_MAX}, | ||
| 33 | {0, UINT_MAX}, | ||
| 34 | }; | ||
| 35 | |||
| 36 | static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = { | ||
| 37 | {1695, UINT_MAX}, | ||
| 38 | {0, UINT_MAX}, | ||
| 39 | }; | ||
| 40 | |||
| 41 | static void rev_sku_to_speedo_ids(int rev, int sku, int *threshold) | ||
| 42 | { | ||
| 43 | u32 tmp; | ||
| 44 | |||
| 45 | switch (sku) { | ||
| 46 | case 0x00: | ||
| 47 | case 0x10: | ||
| 48 | case 0x05: | ||
| 49 | case 0x06: | ||
| 50 | tegra_cpu_speedo_id = 1; | ||
| 51 | tegra_soc_speedo_id = 0; | ||
| 52 | *threshold = THRESHOLD_INDEX_0; | ||
| 53 | break; | ||
| 54 | |||
| 55 | case 0x03: | ||
| 56 | case 0x04: | ||
| 57 | tegra_cpu_speedo_id = 2; | ||
| 58 | tegra_soc_speedo_id = 1; | ||
| 59 | *threshold = THRESHOLD_INDEX_1; | ||
| 60 | break; | ||
| 61 | |||
| 62 | default: | ||
| 63 | pr_err("Tegra114 Unknown SKU %d\n", sku); | ||
| 64 | tegra_cpu_speedo_id = 0; | ||
| 65 | tegra_soc_speedo_id = 0; | ||
| 66 | *threshold = THRESHOLD_INDEX_0; | ||
| 67 | break; | ||
| 68 | } | ||
| 69 | |||
| 70 | if (rev == TEGRA_REVISION_A01) { | ||
| 71 | tmp = tegra_fuse_readl(0x270) << 1; | ||
| 72 | tmp |= tegra_fuse_readl(0x26c); | ||
| 73 | if (!tmp) | ||
| 74 | tegra_cpu_speedo_id = 0; | ||
| 75 | } | ||
| 76 | } | ||
| 77 | |||
| 78 | void tegra114_init_speedo_data(void) | ||
| 79 | { | ||
| 80 | u32 cpu_speedo_val; | ||
| 81 | u32 core_speedo_val; | ||
| 82 | int threshold; | ||
| 83 | int i; | ||
| 84 | |||
| 85 | BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != | ||
| 86 | THRESHOLD_INDEX_COUNT); | ||
| 87 | BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != | ||
| 88 | THRESHOLD_INDEX_COUNT); | ||
| 89 | |||
| 90 | rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id, &threshold); | ||
| 91 | |||
| 92 | cpu_speedo_val = tegra_fuse_readl(0x12c) + 1024; | ||
| 93 | core_speedo_val = tegra_fuse_readl(0x134); | ||
| 94 | |||
| 95 | for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) | ||
| 96 | if (cpu_speedo_val < cpu_process_speedos[threshold][i]) | ||
| 97 | break; | ||
| 98 | tegra_cpu_process_id = i; | ||
| 99 | |||
| 100 | for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) | ||
| 101 | if (core_speedo_val < core_process_speedos[threshold][i]) | ||
| 102 | break; | ||
| 103 | tegra_core_process_id = i; | ||
| 104 | } | ||
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index 1c1609da76ce..f815efe54c73 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c | |||
| @@ -47,8 +47,8 @@ static int __init ux500_l2x0_init(void) | |||
| 47 | /* Unlock before init */ | 47 | /* Unlock before init */ |
| 48 | ux500_l2x0_unlock(); | 48 | ux500_l2x0_unlock(); |
| 49 | 49 | ||
| 50 | /* DB9540's L2 has 128KB way size */ | 50 | /* DBx540's L2 has 128KB way size */ |
| 51 | if (cpu_is_u9540()) | 51 | if (cpu_is_ux540_family()) |
| 52 | /* 128KB way size */ | 52 | /* 128KB way size */ |
| 53 | aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); | 53 | aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); |
| 54 | else | 54 | else |
diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S index bdf6dadf8790..a030e7301da8 100644 --- a/arch/arm/plat-samsung/s5p-sleep.S +++ b/arch/arm/plat-samsung/s5p-sleep.S | |||
| @@ -25,6 +25,9 @@ | |||
| 25 | #include <asm/asm-offsets.h> | 25 | #include <asm/asm-offsets.h> |
| 26 | #include <asm/hardware/cache-l2x0.h> | 26 | #include <asm/hardware/cache-l2x0.h> |
| 27 | 27 | ||
| 28 | #define CPU_MASK 0xff0ffff0 | ||
| 29 | #define CPU_CORTEX_A9 0x410fc090 | ||
| 30 | |||
| 28 | /* | 31 | /* |
| 29 | * The following code is located into the .data section. This is to | 32 | * The following code is located into the .data section. This is to |
| 30 | * allow l2x0_regs_phys to be accessed with a relative load while we | 33 | * allow l2x0_regs_phys to be accessed with a relative load while we |
| @@ -51,6 +54,12 @@ | |||
| 51 | 54 | ||
| 52 | ENTRY(s3c_cpu_resume) | 55 | ENTRY(s3c_cpu_resume) |
| 53 | #ifdef CONFIG_CACHE_L2X0 | 56 | #ifdef CONFIG_CACHE_L2X0 |
| 57 | mrc p15, 0, r0, c0, c0, 0 | ||
| 58 | ldr r1, =CPU_MASK | ||
| 59 | and r0, r0, r1 | ||
| 60 | ldr r1, =CPU_CORTEX_A9 | ||
| 61 | cmp r0, r1 | ||
| 62 | bne resume_l2on | ||
| 54 | adr r0, l2x0_regs_phys | 63 | adr r0, l2x0_regs_phys |
| 55 | ldr r0, [r0] | 64 | ldr r0, [r0] |
| 56 | ldr r1, [r0, #L2X0_R_PHY_BASE] | 65 | ldr r1, [r0, #L2X0_R_PHY_BASE] |
diff --git a/arch/arm/plat-samsung/setup-mipiphy.c b/arch/arm/plat-samsung/setup-mipiphy.c index 147459327601..66df315990a7 100644 --- a/arch/arm/plat-samsung/setup-mipiphy.c +++ b/arch/arm/plat-samsung/setup-mipiphy.c | |||
| @@ -8,6 +8,7 @@ | |||
| 8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include <linux/export.h> | ||
| 11 | #include <linux/kernel.h> | 12 | #include <linux/kernel.h> |
| 12 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 13 | #include <linux/io.h> | 14 | #include <linux/io.h> |
| @@ -50,8 +51,10 @@ int s5p_csis_phy_enable(int id, bool on) | |||
| 50 | { | 51 | { |
| 51 | return __s5p_mipi_phy_control(id, on, S5P_MIPI_DPHY_SRESETN); | 52 | return __s5p_mipi_phy_control(id, on, S5P_MIPI_DPHY_SRESETN); |
| 52 | } | 53 | } |
| 54 | EXPORT_SYMBOL(s5p_csis_phy_enable); | ||
| 53 | 55 | ||
| 54 | int s5p_dsim_phy_enable(struct platform_device *pdev, bool on) | 56 | int s5p_dsim_phy_enable(struct platform_device *pdev, bool on) |
| 55 | { | 57 | { |
| 56 | return __s5p_mipi_phy_control(pdev->id, on, S5P_MIPI_DPHY_MRESETN); | 58 | return __s5p_mipi_phy_control(pdev->id, on, S5P_MIPI_DPHY_MRESETN); |
| 57 | } | 59 | } |
| 60 | EXPORT_SYMBOL(s5p_dsim_phy_enable); | ||
diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c index 2c855a6394ff..bd11315cf5ab 100644 --- a/drivers/clk/socfpga/clk.c +++ b/drivers/clk/socfpga/clk.c | |||
| @@ -1,5 +1,6 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> | 2 | * Copyright 2011-2012 Calxeda, Inc. |
| 3 | * Copyright (C) 2012-2013 Altera Corporation <www.altera.com> | ||
| 3 | * | 4 | * |
| 4 | * This program is free software; you can redistribute it and/or modify | 5 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by | 6 | * it under the terms of the GNU General Public License as published by |
| @@ -11,41 +12,161 @@ | |||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. | 13 | * GNU General Public License for more details. |
| 13 | * | 14 | * |
| 15 | * Based from clk-highbank.c | ||
| 16 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | 17 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ | 19 | */ |
| 17 | #include <linux/clk.h> | 20 | #include <linux/clk.h> |
| 18 | #include <linux/clkdev.h> | 21 | #include <linux/clkdev.h> |
| 19 | #include <linux/clk-provider.h> | 22 | #include <linux/clk-provider.h> |
| 23 | #include <linux/io.h> | ||
| 24 | #include <linux/of.h> | ||
| 20 | 25 | ||
| 21 | #define SOCFPGA_OSC1_CLK 10000000 | 26 | /* Clock Manager offsets */ |
| 22 | #define SOCFPGA_MPU_CLK 800000000 | 27 | #define CLKMGR_CTRL 0x0 |
| 23 | #define SOCFPGA_MAIN_QSPI_CLK 432000000 | 28 | #define CLKMGR_BYPASS 0x4 |
| 24 | #define SOCFPGA_MAIN_NAND_SDMMC_CLK 250000000 | ||
| 25 | #define SOCFPGA_S2F_USR_CLK 125000000 | ||
| 26 | 29 | ||
| 27 | void __init socfpga_init_clocks(void) | 30 | /* Clock bypass bits */ |
| 31 | #define MAINPLL_BYPASS (1<<0) | ||
| 32 | #define SDRAMPLL_BYPASS (1<<1) | ||
| 33 | #define SDRAMPLL_SRC_BYPASS (1<<2) | ||
| 34 | #define PERPLL_BYPASS (1<<3) | ||
| 35 | #define PERPLL_SRC_BYPASS (1<<4) | ||
| 36 | |||
| 37 | #define SOCFPGA_PLL_BG_PWRDWN 0 | ||
| 38 | #define SOCFPGA_PLL_EXT_ENA 1 | ||
| 39 | #define SOCFPGA_PLL_PWR_DOWN 2 | ||
| 40 | #define SOCFPGA_PLL_DIVF_MASK 0x0000FFF8 | ||
| 41 | #define SOCFPGA_PLL_DIVF_SHIFT 3 | ||
| 42 | #define SOCFPGA_PLL_DIVQ_MASK 0x003F0000 | ||
| 43 | #define SOCFPGA_PLL_DIVQ_SHIFT 16 | ||
| 44 | |||
| 45 | extern void __iomem *clk_mgr_base_addr; | ||
| 46 | |||
| 47 | struct socfpga_clk { | ||
| 48 | struct clk_gate hw; | ||
| 49 | char *parent_name; | ||
| 50 | char *clk_name; | ||
| 51 | u32 fixed_div; | ||
| 52 | }; | ||
| 53 | #define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw) | ||
| 54 | |||
| 55 | static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, | ||
| 56 | unsigned long parent_rate) | ||
| 28 | { | 57 | { |
| 58 | struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk); | ||
| 59 | unsigned long divf, divq, vco_freq, reg; | ||
| 60 | unsigned long bypass; | ||
| 61 | |||
| 62 | reg = readl(socfpgaclk->hw.reg); | ||
| 63 | bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS); | ||
| 64 | if (bypass & MAINPLL_BYPASS) | ||
| 65 | return parent_rate; | ||
| 66 | |||
| 67 | divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; | ||
| 68 | divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; | ||
| 69 | vco_freq = parent_rate * (divf + 1); | ||
| 70 | return vco_freq / (1 + divq); | ||
| 71 | } | ||
| 72 | |||
| 73 | |||
| 74 | static struct clk_ops clk_pll_ops = { | ||
| 75 | .recalc_rate = clk_pll_recalc_rate, | ||
| 76 | }; | ||
| 77 | |||
| 78 | static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk, | ||
| 79 | unsigned long parent_rate) | ||
| 80 | { | ||
| 81 | struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk); | ||
| 82 | u32 div; | ||
| 83 | |||
| 84 | if (socfpgaclk->fixed_div) | ||
| 85 | div = socfpgaclk->fixed_div; | ||
| 86 | else | ||
| 87 | div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1); | ||
| 88 | |||
| 89 | return parent_rate / div; | ||
| 90 | } | ||
| 91 | |||
| 92 | static const struct clk_ops periclk_ops = { | ||
| 93 | .recalc_rate = clk_periclk_recalc_rate, | ||
| 94 | }; | ||
| 95 | |||
| 96 | static __init struct clk *socfpga_clk_init(struct device_node *node, | ||
| 97 | const struct clk_ops *ops) | ||
| 98 | { | ||
| 99 | u32 reg; | ||
| 29 | struct clk *clk; | 100 | struct clk *clk; |
| 101 | struct socfpga_clk *socfpga_clk; | ||
| 102 | const char *clk_name = node->name; | ||
| 103 | const char *parent_name; | ||
| 104 | struct clk_init_data init; | ||
| 105 | int rc; | ||
| 106 | u32 fixed_div; | ||
| 107 | |||
| 108 | rc = of_property_read_u32(node, "reg", ®); | ||
| 109 | if (WARN_ON(rc)) | ||
| 110 | return NULL; | ||
| 111 | |||
| 112 | socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); | ||
| 113 | if (WARN_ON(!socfpga_clk)) | ||
| 114 | return NULL; | ||
| 115 | |||
| 116 | socfpga_clk->hw.reg = clk_mgr_base_addr + reg; | ||
| 117 | |||
| 118 | rc = of_property_read_u32(node, "fixed-divider", &fixed_div); | ||
| 119 | if (rc) | ||
| 120 | socfpga_clk->fixed_div = 0; | ||
| 121 | else | ||
| 122 | socfpga_clk->fixed_div = fixed_div; | ||
| 123 | |||
| 124 | of_property_read_string(node, "clock-output-names", &clk_name); | ||
| 125 | |||
| 126 | init.name = clk_name; | ||
| 127 | init.ops = ops; | ||
| 128 | init.flags = 0; | ||
| 129 | parent_name = of_clk_get_parent_name(node, 0); | ||
| 130 | init.parent_names = &parent_name; | ||
| 131 | init.num_parents = 1; | ||
| 30 | 132 | ||
| 31 | clk = clk_register_fixed_rate(NULL, "osc1_clk", NULL, CLK_IS_ROOT, SOCFPGA_OSC1_CLK); | 133 | socfpga_clk->hw.hw.init = &init; |
| 32 | clk_register_clkdev(clk, "osc1_clk", NULL); | ||
| 33 | 134 | ||
| 34 | clk = clk_register_fixed_rate(NULL, "mpu_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK); | 135 | if (strcmp(clk_name, "main_pll") || strcmp(clk_name, "periph_pll") || |
| 35 | clk_register_clkdev(clk, "mpu_clk", NULL); | 136 | strcmp(clk_name, "sdram_pll")) { |
| 137 | socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; | ||
| 138 | clk_pll_ops.enable = clk_gate_ops.enable; | ||
| 139 | clk_pll_ops.disable = clk_gate_ops.disable; | ||
| 140 | } | ||
| 36 | 141 | ||
| 37 | clk = clk_register_fixed_rate(NULL, "main_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2); | 142 | clk = clk_register(NULL, &socfpga_clk->hw.hw); |
| 38 | clk_register_clkdev(clk, "main_clk", NULL); | 143 | if (WARN_ON(IS_ERR(clk))) { |
| 144 | kfree(socfpga_clk); | ||
| 145 | return NULL; | ||
| 146 | } | ||
| 147 | rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); | ||
| 148 | return clk; | ||
| 149 | } | ||
| 39 | 150 | ||
| 40 | clk = clk_register_fixed_rate(NULL, "dbg_base_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2); | 151 | static void __init socfpga_pll_init(struct device_node *node) |
| 41 | clk_register_clkdev(clk, "dbg_base_clk", NULL); | 152 | { |
| 153 | socfpga_clk_init(node, &clk_pll_ops); | ||
| 154 | } | ||
| 155 | CLK_OF_DECLARE(socfpga_pll, "altr,socfpga-pll-clock", socfpga_pll_init); | ||
| 42 | 156 | ||
| 43 | clk = clk_register_fixed_rate(NULL, "main_qspi_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_QSPI_CLK); | 157 | static void __init socfpga_periph_init(struct device_node *node) |
| 44 | clk_register_clkdev(clk, "main_qspi_clk", NULL); | 158 | { |
| 159 | socfpga_clk_init(node, &periclk_ops); | ||
| 160 | } | ||
| 161 | CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init); | ||
| 45 | 162 | ||
| 46 | clk = clk_register_fixed_rate(NULL, "main_nand_sdmmc_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_NAND_SDMMC_CLK); | 163 | void __init socfpga_init_clocks(void) |
| 47 | clk_register_clkdev(clk, "main_nand_sdmmc_clk", NULL); | 164 | { |
| 165 | struct clk *clk; | ||
| 166 | int ret; | ||
| 48 | 167 | ||
| 49 | clk = clk_register_fixed_rate(NULL, "s2f_usr_clk", NULL, CLK_IS_ROOT, SOCFPGA_S2F_USR_CLK); | 168 | clk = clk_register_fixed_factor(NULL, "smp_twd", "mpuclk", 0, 1, 4); |
| 50 | clk_register_clkdev(clk, "s2f_usr_clk", NULL); | 169 | ret = clk_register_clkdev(clk, NULL, "smp_twd"); |
| 170 | if (ret) | ||
| 171 | pr_err("smp_twd alias not registered\n"); | ||
| 51 | } | 172 | } |
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c index 8e2155548888..dde0656ea951 100644 --- a/drivers/gpio/gpio-tegra.c +++ b/drivers/gpio/gpio-tegra.c | |||
| @@ -71,6 +71,7 @@ struct tegra_gpio_bank { | |||
| 71 | u32 oe[4]; | 71 | u32 oe[4]; |
| 72 | u32 int_enb[4]; | 72 | u32 int_enb[4]; |
| 73 | u32 int_lvl[4]; | 73 | u32 int_lvl[4]; |
| 74 | u32 wake_enb[4]; | ||
| 74 | #endif | 75 | #endif |
| 75 | }; | 76 | }; |
| 76 | 77 | ||
| @@ -332,15 +333,31 @@ static int tegra_gpio_suspend(struct device *dev) | |||
| 332 | bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio)); | 333 | bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio)); |
| 333 | bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio)); | 334 | bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio)); |
| 334 | bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio)); | 335 | bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio)); |
| 336 | |||
| 337 | /* Enable gpio irq for wake up source */ | ||
| 338 | tegra_gpio_writel(bank->wake_enb[p], | ||
| 339 | GPIO_INT_ENB(gpio)); | ||
| 335 | } | 340 | } |
| 336 | } | 341 | } |
| 337 | local_irq_restore(flags); | 342 | local_irq_restore(flags); |
| 338 | return 0; | 343 | return 0; |
| 339 | } | 344 | } |
| 340 | 345 | ||
| 341 | static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) | 346 | static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) |
| 342 | { | 347 | { |
| 343 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); | 348 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
| 349 | int gpio = d->hwirq; | ||
| 350 | u32 port, bit, mask; | ||
| 351 | |||
| 352 | port = GPIO_PORT(gpio); | ||
| 353 | bit = GPIO_BIT(gpio); | ||
| 354 | mask = BIT(bit); | ||
| 355 | |||
| 356 | if (enable) | ||
| 357 | bank->wake_enb[port] |= mask; | ||
| 358 | else | ||
| 359 | bank->wake_enb[port] &= ~mask; | ||
| 360 | |||
| 344 | return irq_set_irq_wake(bank->irq, enable); | 361 | return irq_set_irq_wake(bank->irq, enable); |
| 345 | } | 362 | } |
| 346 | #endif | 363 | #endif |
| @@ -352,7 +369,7 @@ static struct irq_chip tegra_gpio_irq_chip = { | |||
| 352 | .irq_unmask = tegra_gpio_irq_unmask, | 369 | .irq_unmask = tegra_gpio_irq_unmask, |
| 353 | .irq_set_type = tegra_gpio_irq_set_type, | 370 | .irq_set_type = tegra_gpio_irq_set_type, |
| 354 | #ifdef CONFIG_PM_SLEEP | 371 | #ifdef CONFIG_PM_SLEEP |
| 355 | .irq_set_wake = tegra_gpio_wake_enable, | 372 | .irq_set_wake = tegra_gpio_irq_set_wake, |
| 356 | #endif | 373 | #endif |
| 357 | }; | 374 | }; |
| 358 | 375 | ||
diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c index 20636772c09b..f8a96d652e9e 100644 --- a/drivers/mmc/host/davinci_mmc.c +++ b/drivers/mmc/host/davinci_mmc.c | |||
| @@ -34,6 +34,8 @@ | |||
| 34 | #include <linux/dma-mapping.h> | 34 | #include <linux/dma-mapping.h> |
| 35 | #include <linux/edma.h> | 35 | #include <linux/edma.h> |
| 36 | #include <linux/mmc/mmc.h> | 36 | #include <linux/mmc/mmc.h> |
| 37 | #include <linux/of.h> | ||
| 38 | #include <linux/of_device.h> | ||
| 37 | 39 | ||
| 38 | #include <linux/platform_data/mmc-davinci.h> | 40 | #include <linux/platform_data/mmc-davinci.h> |
| 39 | 41 | ||
| @@ -522,14 +524,16 @@ static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host) | |||
| 522 | dma_cap_set(DMA_SLAVE, mask); | 524 | dma_cap_set(DMA_SLAVE, mask); |
| 523 | 525 | ||
| 524 | host->dma_tx = | 526 | host->dma_tx = |
| 525 | dma_request_channel(mask, edma_filter_fn, &host->txdma); | 527 | dma_request_slave_channel_compat(mask, edma_filter_fn, |
| 528 | &host->txdma, mmc_dev(host->mmc), "tx"); | ||
| 526 | if (!host->dma_tx) { | 529 | if (!host->dma_tx) { |
| 527 | dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n"); | 530 | dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n"); |
| 528 | return -ENODEV; | 531 | return -ENODEV; |
| 529 | } | 532 | } |
| 530 | 533 | ||
| 531 | host->dma_rx = | 534 | host->dma_rx = |
| 532 | dma_request_channel(mask, edma_filter_fn, &host->rxdma); | 535 | dma_request_slave_channel_compat(mask, edma_filter_fn, |
| 536 | &host->rxdma, mmc_dev(host->mmc), "rx"); | ||
| 533 | if (!host->dma_rx) { | 537 | if (!host->dma_rx) { |
| 534 | dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n"); | 538 | dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n"); |
| 535 | r = -ENODEV; | 539 | r = -ENODEV; |
| @@ -1157,16 +1161,86 @@ static void __init init_mmcsd_host(struct mmc_davinci_host *host) | |||
| 1157 | mmc_davinci_reset_ctrl(host, 0); | 1161 | mmc_davinci_reset_ctrl(host, 0); |
| 1158 | } | 1162 | } |
| 1159 | 1163 | ||
| 1160 | static int __init davinci_mmcsd_probe(struct platform_device *pdev) | 1164 | static struct platform_device_id davinci_mmc_devtype[] = { |
| 1165 | { | ||
| 1166 | .name = "dm6441-mmc", | ||
| 1167 | .driver_data = MMC_CTLR_VERSION_1, | ||
| 1168 | }, { | ||
| 1169 | .name = "da830-mmc", | ||
| 1170 | .driver_data = MMC_CTLR_VERSION_2, | ||
| 1171 | }, | ||
| 1172 | {}, | ||
| 1173 | }; | ||
| 1174 | MODULE_DEVICE_TABLE(platform, davinci_mmc_devtype); | ||
| 1175 | |||
| 1176 | static const struct of_device_id davinci_mmc_dt_ids[] = { | ||
| 1177 | { | ||
| 1178 | .compatible = "ti,dm6441-mmc", | ||
| 1179 | .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_1], | ||
| 1180 | }, | ||
| 1181 | { | ||
| 1182 | .compatible = "ti,da830-mmc", | ||
| 1183 | .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_2], | ||
| 1184 | }, | ||
| 1185 | {}, | ||
| 1186 | }; | ||
| 1187 | MODULE_DEVICE_TABLE(of, davinci_mmc_dt_ids); | ||
| 1188 | |||
| 1189 | static struct davinci_mmc_config | ||
| 1190 | *mmc_parse_pdata(struct platform_device *pdev) | ||
| 1161 | { | 1191 | { |
| 1192 | struct device_node *np; | ||
| 1162 | struct davinci_mmc_config *pdata = pdev->dev.platform_data; | 1193 | struct davinci_mmc_config *pdata = pdev->dev.platform_data; |
| 1194 | const struct of_device_id *match = | ||
| 1195 | of_match_device(of_match_ptr(davinci_mmc_dt_ids), &pdev->dev); | ||
| 1196 | u32 data; | ||
| 1197 | |||
| 1198 | np = pdev->dev.of_node; | ||
| 1199 | if (!np) | ||
| 1200 | return pdata; | ||
| 1201 | |||
| 1202 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | ||
| 1203 | if (!pdata) { | ||
| 1204 | dev_err(&pdev->dev, "Failed to allocate memory for struct davinci_mmc_config\n"); | ||
| 1205 | goto nodata; | ||
| 1206 | } | ||
| 1207 | |||
| 1208 | if (match) | ||
| 1209 | pdev->id_entry = match->data; | ||
| 1210 | |||
| 1211 | if (of_property_read_u32(np, "max-frequency", &pdata->max_freq)) | ||
| 1212 | dev_info(&pdev->dev, "'max-frequency' property not specified, defaulting to 25MHz\n"); | ||
| 1213 | |||
| 1214 | of_property_read_u32(np, "bus-width", &data); | ||
| 1215 | switch (data) { | ||
| 1216 | case 1: | ||
| 1217 | case 4: | ||
| 1218 | case 8: | ||
| 1219 | pdata->wires = data; | ||
| 1220 | break; | ||
| 1221 | default: | ||
| 1222 | pdata->wires = 1; | ||
| 1223 | dev_info(&pdev->dev, "Unsupported buswidth, defaulting to 1 bit\n"); | ||
| 1224 | } | ||
| 1225 | nodata: | ||
| 1226 | return pdata; | ||
| 1227 | } | ||
| 1228 | |||
| 1229 | static int __init davinci_mmcsd_probe(struct platform_device *pdev) | ||
| 1230 | { | ||
| 1231 | struct davinci_mmc_config *pdata = NULL; | ||
| 1163 | struct mmc_davinci_host *host = NULL; | 1232 | struct mmc_davinci_host *host = NULL; |
| 1164 | struct mmc_host *mmc = NULL; | 1233 | struct mmc_host *mmc = NULL; |
| 1165 | struct resource *r, *mem = NULL; | 1234 | struct resource *r, *mem = NULL; |
| 1166 | int ret = 0, irq = 0; | 1235 | int ret = 0, irq = 0; |
| 1167 | size_t mem_size; | 1236 | size_t mem_size; |
| 1237 | const struct platform_device_id *id_entry; | ||
| 1168 | 1238 | ||
| 1169 | /* REVISIT: when we're fully converted, fail if pdata is NULL */ | 1239 | pdata = mmc_parse_pdata(pdev); |
| 1240 | if (pdata == NULL) { | ||
| 1241 | dev_err(&pdev->dev, "Couldn't get platform data\n"); | ||
| 1242 | return -ENOENT; | ||
| 1243 | } | ||
| 1170 | 1244 | ||
| 1171 | ret = -ENODEV; | 1245 | ret = -ENODEV; |
| 1172 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1246 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| @@ -1237,7 +1311,9 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev) | |||
| 1237 | if (pdata && (pdata->wires == 8)) | 1311 | if (pdata && (pdata->wires == 8)) |
| 1238 | mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); | 1312 | mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); |
| 1239 | 1313 | ||
| 1240 | host->version = pdata->version; | 1314 | id_entry = platform_get_device_id(pdev); |
| 1315 | if (id_entry) | ||
| 1316 | host->version = id_entry->driver_data; | ||
| 1241 | 1317 | ||
| 1242 | mmc->ops = &mmc_davinci_ops; | 1318 | mmc->ops = &mmc_davinci_ops; |
| 1243 | mmc->f_min = 312500; | 1319 | mmc->f_min = 312500; |
| @@ -1406,8 +1482,10 @@ static struct platform_driver davinci_mmcsd_driver = { | |||
| 1406 | .name = "davinci_mmc", | 1482 | .name = "davinci_mmc", |
| 1407 | .owner = THIS_MODULE, | 1483 | .owner = THIS_MODULE, |
| 1408 | .pm = davinci_mmcsd_pm_ops, | 1484 | .pm = davinci_mmcsd_pm_ops, |
| 1485 | .of_match_table = of_match_ptr(davinci_mmc_dt_ids), | ||
| 1409 | }, | 1486 | }, |
| 1410 | .remove = __exit_p(davinci_mmcsd_remove), | 1487 | .remove = __exit_p(davinci_mmcsd_remove), |
| 1488 | .id_table = davinci_mmc_devtype, | ||
| 1411 | }; | 1489 | }; |
| 1412 | 1490 | ||
| 1413 | static int __init davinci_mmcsd_init(void) | 1491 | static int __init davinci_mmcsd_init(void) |
diff --git a/include/linux/platform_data/mmc-davinci.h b/include/linux/platform_data/mmc-davinci.h index 5ba6b22ce338..9cea4ee377b5 100644 --- a/include/linux/platform_data/mmc-davinci.h +++ b/include/linux/platform_data/mmc-davinci.h | |||
| @@ -23,9 +23,6 @@ struct davinci_mmc_config { | |||
| 23 | /* any additional host capabilities: OR'd in to mmc->f_caps */ | 23 | /* any additional host capabilities: OR'd in to mmc->f_caps */ |
| 24 | u32 caps; | 24 | u32 caps; |
| 25 | 25 | ||
| 26 | /* Version of the MMC/SD controller */ | ||
| 27 | u8 version; | ||
| 28 | |||
| 29 | /* Number of sg segments */ | 26 | /* Number of sg segments */ |
| 30 | u8 nr_sg; | 27 | u8 nr_sg; |
| 31 | }; | 28 | }; |