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-rw-r--r--drivers/spi/davinci_spi.c33
1 files changed, 2 insertions, 31 deletions
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index a92f507eaff7..7bd0a55f5bbd 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -54,16 +54,12 @@
54#define SPIFMT_WDELAY_SHIFT 24 54#define SPIFMT_WDELAY_SHIFT 24
55#define SPIFMT_CHARLEN_MASK 0x0000001Fu 55#define SPIFMT_CHARLEN_MASK 0x0000001Fu
56 56
57/* SPIGCR1 */
58#define SPIGCR1_SPIENA_MASK 0x01000000u
59 57
60/* SPIPC0 */ 58/* SPIPC0 */
61#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ 59#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
62#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ 60#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
63#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ 61#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
64#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ 62#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
65#define SPIPC0_EN1FUN_MASK BIT(1)
66#define SPIPC0_EN0FUN_MASK BIT(0)
67 63
68#define SPIINT_MASKALL 0x0101035F 64#define SPIINT_MASKALL 0x0101035F
69#define SPI_INTLVL_1 0x000001FFu 65#define SPI_INTLVL_1 0x000001FFu
@@ -75,6 +71,7 @@
75#define SPIGCR1_CLKMOD_MASK BIT(1) 71#define SPIGCR1_CLKMOD_MASK BIT(1)
76#define SPIGCR1_MASTER_MASK BIT(0) 72#define SPIGCR1_MASTER_MASK BIT(0)
77#define SPIGCR1_LOOPBACK_MASK BIT(16) 73#define SPIGCR1_LOOPBACK_MASK BIT(16)
74#define SPIGCR1_SPIENA_MASK BIT(24)
78 75
79/* SPIBUF */ 76/* SPIBUF */
80#define SPIBUF_TXFULL_MASK BIT(29) 77#define SPIBUF_TXFULL_MASK BIT(29)
@@ -90,23 +87,12 @@
90#define SPIFLG_RX_INTR_MASK BIT(8) 87#define SPIFLG_RX_INTR_MASK BIT(8)
91#define SPIFLG_TX_INTR_MASK BIT(9) 88#define SPIFLG_TX_INTR_MASK BIT(9)
92#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) 89#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
93#define SPIFLG_MASK (SPIFLG_DLEN_ERR_MASK \ 90
94 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
95 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
96 | SPIFLG_OVRRUN_MASK | SPIFLG_RX_INTR_MASK \
97 | SPIFLG_TX_INTR_MASK \
98 | SPIFLG_BUF_INIT_ACTIVE_MASK)
99
100#define SPIINT_DLEN_ERR_INTR BIT(0)
101#define SPIINT_TIMEOUT_INTR BIT(1)
102#define SPIINT_PARERR_INTR BIT(2)
103#define SPIINT_DESYNC_INTR BIT(3)
104#define SPIINT_BITERR_INTR BIT(4) 91#define SPIINT_BITERR_INTR BIT(4)
105#define SPIINT_OVRRUN_INTR BIT(6) 92#define SPIINT_OVRRUN_INTR BIT(6)
106#define SPIINT_RX_INTR BIT(8) 93#define SPIINT_RX_INTR BIT(8)
107#define SPIINT_TX_INTR BIT(9) 94#define SPIINT_TX_INTR BIT(9)
108#define SPIINT_DMA_REQ_EN BIT(16) 95#define SPIINT_DMA_REQ_EN BIT(16)
109#define SPIINT_ENABLE_HIGHZ BIT(24)
110 96
111#define SPI_T2CDELAY_SHIFT 16 97#define SPI_T2CDELAY_SHIFT 16
112#define SPI_C2TDELAY_SHIFT 24 98#define SPI_C2TDELAY_SHIFT 24
@@ -118,26 +104,11 @@
118#define SPILVL 0x0c 104#define SPILVL 0x0c
119#define SPIFLG 0x10 105#define SPIFLG 0x10
120#define SPIPC0 0x14 106#define SPIPC0 0x14
121#define SPIPC1 0x18
122#define SPIPC2 0x1c
123#define SPIPC3 0x20
124#define SPIPC4 0x24
125#define SPIPC5 0x28
126#define SPIPC6 0x2c
127#define SPIPC7 0x30
128#define SPIPC8 0x34
129#define SPIDAT0 0x38
130#define SPIDAT1 0x3c 107#define SPIDAT1 0x3c
131#define SPIBUF 0x40 108#define SPIBUF 0x40
132#define SPIEMU 0x44
133#define SPIDELAY 0x48 109#define SPIDELAY 0x48
134#define SPIDEF 0x4c 110#define SPIDEF 0x4c
135#define SPIFMT0 0x50 111#define SPIFMT0 0x50
136#define SPIFMT1 0x54
137#define SPIFMT2 0x58
138#define SPIFMT3 0x5c
139#define TGINTVEC0 0x60
140#define TGINTVEC1 0x64
141 112
142struct davinci_spi_slave { 113struct davinci_spi_slave {
143 u32 cmd_to_write; 114 u32 cmd_to_write;