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-rw-r--r--include/sound/max98095.h26
-rw-r--r--sound/soc/codecs/Kconfig4
-rw-r--r--sound/soc/codecs/Makefile2
-rw-r--r--sound/soc/codecs/max98095.c2009
-rw-r--r--sound/soc/codecs/max98095.h284
5 files changed, 2325 insertions, 0 deletions
diff --git a/include/sound/max98095.h b/include/sound/max98095.h
new file mode 100644
index 000000000000..3381765b503e
--- /dev/null
+++ b/include/sound/max98095.h
@@ -0,0 +1,26 @@
1/*
2 * Platform data for MAX98095
3 *
4 * Copyright 2011 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12
13#ifndef __SOUND_MAX98095_PDATA_H__
14#define __SOUND_MAX98095_PDATA_H__
15
16/* codec platform data */
17struct max98095_pdata {
18 /* Analog/digital microphone configuration:
19 * 0 = analog microphone input (normal setting)
20 * 1 = digital microphone input
21 */
22 unsigned int digmic_left_mode:1;
23 unsigned int digmic_right_mode:1;
24};
25
26#endif
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index b814ed0a1636..78da05b5e5eb 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -33,6 +33,7 @@ config SND_SOC_ALL_CODECS
33 select SND_SOC_JZ4740_CODEC if SOC_JZ4740 33 select SND_SOC_JZ4740_CODEC if SOC_JZ4740
34 select SND_SOC_LM4857 if I2C 34 select SND_SOC_LM4857 if I2C
35 select SND_SOC_MAX98088 if I2C 35 select SND_SOC_MAX98088 if I2C
36 select SND_SOC_MAX98095 if I2C
36 select SND_SOC_MAX9850 if I2C 37 select SND_SOC_MAX9850 if I2C
37 select SND_SOC_MAX9877 if I2C 38 select SND_SOC_MAX9877 if I2C
38 select SND_SOC_PCM3008 39 select SND_SOC_PCM3008
@@ -187,6 +188,9 @@ config SND_SOC_DMIC
187config SND_SOC_MAX98088 188config SND_SOC_MAX98088
188 tristate 189 tristate
189 190
191config SND_SOC_MAX98095
192 tristate
193
190config SND_SOC_MAX9850 194config SND_SOC_MAX9850
191 tristate 195 tristate
192 196
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 49121ad0e172..f030c1826746 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -19,6 +19,7 @@ snd-soc-dfbmcs320-objs := dfbmcs320.o
19snd-soc-dmic-objs := dmic.o 19snd-soc-dmic-objs := dmic.o
20snd-soc-l3-objs := l3.o 20snd-soc-l3-objs := l3.o
21snd-soc-max98088-objs := max98088.o 21snd-soc-max98088-objs := max98088.o
22snd-soc-max98095-objs := max98095.o
22snd-soc-max9850-objs := max9850.o 23snd-soc-max9850-objs := max9850.o
23snd-soc-pcm3008-objs := pcm3008.o 24snd-soc-pcm3008-objs := pcm3008.o
24snd-soc-sgtl5000-objs := sgtl5000.o 25snd-soc-sgtl5000-objs := sgtl5000.o
@@ -108,6 +109,7 @@ obj-$(CONFIG_SND_SOC_DMIC) += snd-soc-dmic.o
108obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o 109obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o
109obj-$(CONFIG_SND_SOC_JZ4740_CODEC) += snd-soc-jz4740-codec.o 110obj-$(CONFIG_SND_SOC_JZ4740_CODEC) += snd-soc-jz4740-codec.o
110obj-$(CONFIG_SND_SOC_MAX98088) += snd-soc-max98088.o 111obj-$(CONFIG_SND_SOC_MAX98088) += snd-soc-max98088.o
112obj-$(CONFIG_SND_SOC_MAX98095) += snd-soc-max98095.o
111obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o 113obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o
112obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o 114obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o
113obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o 115obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o
diff --git a/sound/soc/codecs/max98095.c b/sound/soc/codecs/max98095.c
new file mode 100644
index 000000000000..9c77f17a6afb
--- /dev/null
+++ b/sound/soc/codecs/max98095.c
@@ -0,0 +1,2009 @@
1/*
2 * max98095.c -- MAX98095 ALSA SoC Audio driver
3 *
4 * Copyright 2011 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <sound/core.h>
20#include <sound/pcm.h>
21#include <sound/pcm_params.h>
22#include <sound/soc.h>
23#include <sound/initval.h>
24#include <sound/tlv.h>
25#include <linux/slab.h>
26#include <asm/div64.h>
27#include <sound/max98095.h>
28#include "max98095.h"
29
30enum max98095_type {
31 MAX98095,
32};
33
34struct max98095_cdata {
35 unsigned int rate;
36 unsigned int fmt;
37};
38
39struct max98095_priv {
40 enum max98095_type devtype;
41 void *control_data;
42 struct max98095_pdata *pdata;
43 unsigned int sysclk;
44 struct max98095_cdata dai[3];
45 u8 lin_state;
46 unsigned int mic1pre;
47 unsigned int mic2pre;
48};
49
50static const u8 max98095_reg_def[M98095_REG_CNT] = {
51 0x00, /* 00 */
52 0x00, /* 01 */
53 0x00, /* 02 */
54 0x00, /* 03 */
55 0x00, /* 04 */
56 0x00, /* 05 */
57 0x00, /* 06 */
58 0x00, /* 07 */
59 0x00, /* 08 */
60 0x00, /* 09 */
61 0x00, /* 0A */
62 0x00, /* 0B */
63 0x00, /* 0C */
64 0x00, /* 0D */
65 0x00, /* 0E */
66 0x00, /* 0F */
67 0x00, /* 10 */
68 0x00, /* 11 */
69 0x00, /* 12 */
70 0x00, /* 13 */
71 0x00, /* 14 */
72 0x00, /* 15 */
73 0x00, /* 16 */
74 0x00, /* 17 */
75 0x00, /* 18 */
76 0x00, /* 19 */
77 0x00, /* 1A */
78 0x00, /* 1B */
79 0x00, /* 1C */
80 0x00, /* 1D */
81 0x00, /* 1E */
82 0x00, /* 1F */
83 0x00, /* 20 */
84 0x00, /* 21 */
85 0x00, /* 22 */
86 0x00, /* 23 */
87 0x00, /* 24 */
88 0x00, /* 25 */
89 0x00, /* 26 */
90 0x00, /* 27 */
91 0x00, /* 28 */
92 0x00, /* 29 */
93 0x00, /* 2A */
94 0x00, /* 2B */
95 0x00, /* 2C */
96 0x00, /* 2D */
97 0x00, /* 2E */
98 0x00, /* 2F */
99 0x00, /* 30 */
100 0x00, /* 31 */
101 0x00, /* 32 */
102 0x00, /* 33 */
103 0x00, /* 34 */
104 0x00, /* 35 */
105 0x00, /* 36 */
106 0x00, /* 37 */
107 0x00, /* 38 */
108 0x00, /* 39 */
109 0x00, /* 3A */
110 0x00, /* 3B */
111 0x00, /* 3C */
112 0x00, /* 3D */
113 0x00, /* 3E */
114 0x00, /* 3F */
115 0x00, /* 40 */
116 0x00, /* 41 */
117 0x00, /* 42 */
118 0x00, /* 43 */
119 0x00, /* 44 */
120 0x00, /* 45 */
121 0x00, /* 46 */
122 0x00, /* 47 */
123 0x00, /* 48 */
124 0x00, /* 49 */
125 0x00, /* 4A */
126 0x00, /* 4B */
127 0x00, /* 4C */
128 0x00, /* 4D */
129 0x00, /* 4E */
130 0x00, /* 4F */
131 0x00, /* 50 */
132 0x00, /* 51 */
133 0x00, /* 52 */
134 0x00, /* 53 */
135 0x00, /* 54 */
136 0x00, /* 55 */
137 0x00, /* 56 */
138 0x00, /* 57 */
139 0x00, /* 58 */
140 0x00, /* 59 */
141 0x00, /* 5A */
142 0x00, /* 5B */
143 0x00, /* 5C */
144 0x00, /* 5D */
145 0x00, /* 5E */
146 0x00, /* 5F */
147 0x00, /* 60 */
148 0x00, /* 61 */
149 0x00, /* 62 */
150 0x00, /* 63 */
151 0x00, /* 64 */
152 0x00, /* 65 */
153 0x00, /* 66 */
154 0x00, /* 67 */
155 0x00, /* 68 */
156 0x00, /* 69 */
157 0x00, /* 6A */
158 0x00, /* 6B */
159 0x00, /* 6C */
160 0x00, /* 6D */
161 0x00, /* 6E */
162 0x00, /* 6F */
163 0x00, /* 70 */
164 0x00, /* 71 */
165 0x00, /* 72 */
166 0x00, /* 73 */
167 0x00, /* 74 */
168 0x00, /* 75 */
169 0x00, /* 76 */
170 0x00, /* 77 */
171 0x00, /* 78 */
172 0x00, /* 79 */
173 0x00, /* 7A */
174 0x00, /* 7B */
175 0x00, /* 7C */
176 0x00, /* 7D */
177 0x00, /* 7E */
178 0x00, /* 7F */
179 0x00, /* 80 */
180 0x00, /* 81 */
181 0x00, /* 82 */
182 0x00, /* 83 */
183 0x00, /* 84 */
184 0x00, /* 85 */
185 0x00, /* 86 */
186 0x00, /* 87 */
187 0x00, /* 88 */
188 0x00, /* 89 */
189 0x00, /* 8A */
190 0x00, /* 8B */
191 0x00, /* 8C */
192 0x00, /* 8D */
193 0x00, /* 8E */
194 0x00, /* 8F */
195 0x00, /* 90 */
196 0x00, /* 91 */
197 0x30, /* 92 */
198 0xF0, /* 93 */
199 0x00, /* 94 */
200 0x00, /* 95 */
201 0x3F, /* 96 */
202 0x00, /* 97 */
203 0x00, /* 98 */
204 0x00, /* 99 */
205 0x00, /* 9A */
206 0x00, /* 9B */
207 0x00, /* 9C */
208 0x00, /* 9D */
209 0x00, /* 9E */
210 0x00, /* 9F */
211 0x00, /* A0 */
212 0x00, /* A1 */
213 0x00, /* A2 */
214 0x00, /* A3 */
215 0x00, /* A4 */
216 0x00, /* A5 */
217 0x00, /* A6 */
218 0x00, /* A7 */
219 0x00, /* A8 */
220 0x00, /* A9 */
221 0x00, /* AA */
222 0x00, /* AB */
223 0x00, /* AC */
224 0x00, /* AD */
225 0x00, /* AE */
226 0x00, /* AF */
227 0x00, /* B0 */
228 0x00, /* B1 */
229 0x00, /* B2 */
230 0x00, /* B3 */
231 0x00, /* B4 */
232 0x00, /* B5 */
233 0x00, /* B6 */
234 0x00, /* B7 */
235 0x00, /* B8 */
236 0x00, /* B9 */
237 0x00, /* BA */
238 0x00, /* BB */
239 0x00, /* BC */
240 0x00, /* BD */
241 0x00, /* BE */
242 0x00, /* BF */
243 0x00, /* C0 */
244 0x00, /* C1 */
245 0x00, /* C2 */
246 0x00, /* C3 */
247 0x00, /* C4 */
248 0x00, /* C5 */
249 0x00, /* C6 */
250 0x00, /* C7 */
251 0x00, /* C8 */
252 0x00, /* C9 */
253 0x00, /* CA */
254 0x00, /* CB */
255 0x00, /* CC */
256 0x00, /* CD */
257 0x00, /* CE */
258 0x00, /* CF */
259 0x00, /* D0 */
260 0x00, /* D1 */
261 0x00, /* D2 */
262 0x00, /* D3 */
263 0x00, /* D4 */
264 0x00, /* D5 */
265 0x00, /* D6 */
266 0x00, /* D7 */
267 0x00, /* D8 */
268 0x00, /* D9 */
269 0x00, /* DA */
270 0x00, /* DB */
271 0x00, /* DC */
272 0x00, /* DD */
273 0x00, /* DE */
274 0x00, /* DF */
275 0x00, /* E0 */
276 0x00, /* E1 */
277 0x00, /* E2 */
278 0x00, /* E3 */
279 0x00, /* E4 */
280 0x00, /* E5 */
281 0x00, /* E6 */
282 0x00, /* E7 */
283 0x00, /* E8 */
284 0x00, /* E9 */
285 0x00, /* EA */
286 0x00, /* EB */
287 0x00, /* EC */
288 0x00, /* ED */
289 0x00, /* EE */
290 0x00, /* EF */
291 0x00, /* F0 */
292 0x00, /* F1 */
293 0x00, /* F2 */
294 0x00, /* F3 */
295 0x00, /* F4 */
296 0x00, /* F5 */
297 0x00, /* F6 */
298 0x00, /* F7 */
299 0x00, /* F8 */
300 0x00, /* F9 */
301 0x00, /* FA */
302 0x00, /* FB */
303 0x00, /* FC */
304 0x00, /* FD */
305 0x00, /* FE */
306 0x00, /* FF */
307};
308
309static struct {
310 int readable;
311 int writable;
312} max98095_access[M98095_REG_CNT] = {
313 { 0x00, 0x00 }, /* 00 */
314 { 0xFF, 0x00 }, /* 01 */
315 { 0xFF, 0x00 }, /* 02 */
316 { 0xFF, 0x00 }, /* 03 */
317 { 0xFF, 0x00 }, /* 04 */
318 { 0xFF, 0x00 }, /* 05 */
319 { 0xFF, 0x00 }, /* 06 */
320 { 0xFF, 0x00 }, /* 07 */
321 { 0xFF, 0x00 }, /* 08 */
322 { 0xFF, 0x00 }, /* 09 */
323 { 0xFF, 0x00 }, /* 0A */
324 { 0xFF, 0x00 }, /* 0B */
325 { 0xFF, 0x00 }, /* 0C */
326 { 0xFF, 0x00 }, /* 0D */
327 { 0xFF, 0x00 }, /* 0E */
328 { 0xFF, 0x9F }, /* 0F */
329 { 0xFF, 0xFF }, /* 10 */
330 { 0xFF, 0xFF }, /* 11 */
331 { 0xFF, 0xFF }, /* 12 */
332 { 0xFF, 0xFF }, /* 13 */
333 { 0xFF, 0xFF }, /* 14 */
334 { 0xFF, 0xFF }, /* 15 */
335 { 0xFF, 0xFF }, /* 16 */
336 { 0xFF, 0xFF }, /* 17 */
337 { 0xFF, 0xFF }, /* 18 */
338 { 0xFF, 0xFF }, /* 19 */
339 { 0xFF, 0xFF }, /* 1A */
340 { 0xFF, 0xFF }, /* 1B */
341 { 0xFF, 0xFF }, /* 1C */
342 { 0xFF, 0xFF }, /* 1D */
343 { 0xFF, 0x77 }, /* 1E */
344 { 0xFF, 0x77 }, /* 1F */
345 { 0xFF, 0x77 }, /* 20 */
346 { 0xFF, 0x77 }, /* 21 */
347 { 0xFF, 0x77 }, /* 22 */
348 { 0xFF, 0x77 }, /* 23 */
349 { 0xFF, 0xFF }, /* 24 */
350 { 0xFF, 0x7F }, /* 25 */
351 { 0xFF, 0x31 }, /* 26 */
352 { 0xFF, 0xFF }, /* 27 */
353 { 0xFF, 0xFF }, /* 28 */
354 { 0xFF, 0xFF }, /* 29 */
355 { 0xFF, 0xF7 }, /* 2A */
356 { 0xFF, 0x2F }, /* 2B */
357 { 0xFF, 0xEF }, /* 2C */
358 { 0xFF, 0xFF }, /* 2D */
359 { 0xFF, 0xFF }, /* 2E */
360 { 0xFF, 0xFF }, /* 2F */
361 { 0xFF, 0xFF }, /* 30 */
362 { 0xFF, 0xFF }, /* 31 */
363 { 0xFF, 0xFF }, /* 32 */
364 { 0xFF, 0xFF }, /* 33 */
365 { 0xFF, 0xF7 }, /* 34 */
366 { 0xFF, 0x2F }, /* 35 */
367 { 0xFF, 0xCF }, /* 36 */
368 { 0xFF, 0xFF }, /* 37 */
369 { 0xFF, 0xFF }, /* 38 */
370 { 0xFF, 0xFF }, /* 39 */
371 { 0xFF, 0xFF }, /* 3A */
372 { 0xFF, 0xFF }, /* 3B */
373 { 0xFF, 0xFF }, /* 3C */
374 { 0xFF, 0xFF }, /* 3D */
375 { 0xFF, 0xF7 }, /* 3E */
376 { 0xFF, 0x2F }, /* 3F */
377 { 0xFF, 0xCF }, /* 40 */
378 { 0xFF, 0xFF }, /* 41 */
379 { 0xFF, 0x77 }, /* 42 */
380 { 0xFF, 0xFF }, /* 43 */
381 { 0xFF, 0xFF }, /* 44 */
382 { 0xFF, 0xFF }, /* 45 */
383 { 0xFF, 0xFF }, /* 46 */
384 { 0xFF, 0xFF }, /* 47 */
385 { 0xFF, 0xFF }, /* 48 */
386 { 0xFF, 0x0F }, /* 49 */
387 { 0xFF, 0xFF }, /* 4A */
388 { 0xFF, 0xFF }, /* 4B */
389 { 0xFF, 0x3F }, /* 4C */
390 { 0xFF, 0x3F }, /* 4D */
391 { 0xFF, 0x3F }, /* 4E */
392 { 0xFF, 0xFF }, /* 4F */
393 { 0xFF, 0x7F }, /* 50 */
394 { 0xFF, 0x7F }, /* 51 */
395 { 0xFF, 0x0F }, /* 52 */
396 { 0xFF, 0x3F }, /* 53 */
397 { 0xFF, 0x3F }, /* 54 */
398 { 0xFF, 0x3F }, /* 55 */
399 { 0xFF, 0xFF }, /* 56 */
400 { 0xFF, 0xFF }, /* 57 */
401 { 0xFF, 0xBF }, /* 58 */
402 { 0xFF, 0x1F }, /* 59 */
403 { 0xFF, 0xBF }, /* 5A */
404 { 0xFF, 0x1F }, /* 5B */
405 { 0xFF, 0xBF }, /* 5C */
406 { 0xFF, 0x3F }, /* 5D */
407 { 0xFF, 0x3F }, /* 5E */
408 { 0xFF, 0x7F }, /* 5F */
409 { 0xFF, 0x7F }, /* 60 */
410 { 0xFF, 0x47 }, /* 61 */
411 { 0xFF, 0x9F }, /* 62 */
412 { 0xFF, 0x9F }, /* 63 */
413 { 0xFF, 0x9F }, /* 64 */
414 { 0xFF, 0x9F }, /* 65 */
415 { 0xFF, 0x9F }, /* 66 */
416 { 0xFF, 0xBF }, /* 67 */
417 { 0xFF, 0xBF }, /* 68 */
418 { 0xFF, 0xFF }, /* 69 */
419 { 0xFF, 0xFF }, /* 6A */
420 { 0xFF, 0x7F }, /* 6B */
421 { 0xFF, 0xF7 }, /* 6C */
422 { 0xFF, 0xFF }, /* 6D */
423 { 0xFF, 0xFF }, /* 6E */
424 { 0xFF, 0x1F }, /* 6F */
425 { 0xFF, 0xF7 }, /* 70 */
426 { 0xFF, 0xFF }, /* 71 */
427 { 0xFF, 0xFF }, /* 72 */
428 { 0xFF, 0x1F }, /* 73 */
429 { 0xFF, 0xF7 }, /* 74 */
430 { 0xFF, 0xFF }, /* 75 */
431 { 0xFF, 0xFF }, /* 76 */
432 { 0xFF, 0x1F }, /* 77 */
433 { 0xFF, 0xF7 }, /* 78 */
434 { 0xFF, 0xFF }, /* 79 */
435 { 0xFF, 0xFF }, /* 7A */
436 { 0xFF, 0x1F }, /* 7B */
437 { 0xFF, 0xF7 }, /* 7C */
438 { 0xFF, 0xFF }, /* 7D */
439 { 0xFF, 0xFF }, /* 7E */
440 { 0xFF, 0x1F }, /* 7F */
441 { 0xFF, 0xF7 }, /* 80 */
442 { 0xFF, 0xFF }, /* 81 */
443 { 0xFF, 0xFF }, /* 82 */
444 { 0xFF, 0x1F }, /* 83 */
445 { 0xFF, 0x7F }, /* 84 */
446 { 0xFF, 0x0F }, /* 85 */
447 { 0xFF, 0xD8 }, /* 86 */
448 { 0xFF, 0xFF }, /* 87 */
449 { 0xFF, 0xEF }, /* 88 */
450 { 0xFF, 0xFE }, /* 89 */
451 { 0xFF, 0xFE }, /* 8A */
452 { 0xFF, 0xFF }, /* 8B */
453 { 0xFF, 0xFF }, /* 8C */
454 { 0xFF, 0x3F }, /* 8D */
455 { 0xFF, 0xFF }, /* 8E */
456 { 0xFF, 0x3F }, /* 8F */
457 { 0xFF, 0x8F }, /* 90 */
458 { 0xFF, 0xFF }, /* 91 */
459 { 0xFF, 0x3F }, /* 92 */
460 { 0xFF, 0xFF }, /* 93 */
461 { 0xFF, 0xFF }, /* 94 */
462 { 0xFF, 0x0F }, /* 95 */
463 { 0xFF, 0x3F }, /* 96 */
464 { 0xFF, 0x8C }, /* 97 */
465 { 0x00, 0x00 }, /* 98 */
466 { 0x00, 0x00 }, /* 99 */
467 { 0x00, 0x00 }, /* 9A */
468 { 0x00, 0x00 }, /* 9B */
469 { 0x00, 0x00 }, /* 9C */
470 { 0x00, 0x00 }, /* 9D */
471 { 0x00, 0x00 }, /* 9E */
472 { 0x00, 0x00 }, /* 9F */
473 { 0x00, 0x00 }, /* A0 */
474 { 0x00, 0x00 }, /* A1 */
475 { 0x00, 0x00 }, /* A2 */
476 { 0x00, 0x00 }, /* A3 */
477 { 0x00, 0x00 }, /* A4 */
478 { 0x00, 0x00 }, /* A5 */
479 { 0x00, 0x00 }, /* A6 */
480 { 0x00, 0x00 }, /* A7 */
481 { 0x00, 0x00 }, /* A8 */
482 { 0x00, 0x00 }, /* A9 */
483 { 0x00, 0x00 }, /* AA */
484 { 0x00, 0x00 }, /* AB */
485 { 0x00, 0x00 }, /* AC */
486 { 0x00, 0x00 }, /* AD */
487 { 0x00, 0x00 }, /* AE */
488 { 0x00, 0x00 }, /* AF */
489 { 0x00, 0x00 }, /* B0 */
490 { 0x00, 0x00 }, /* B1 */
491 { 0x00, 0x00 }, /* B2 */
492 { 0x00, 0x00 }, /* B3 */
493 { 0x00, 0x00 }, /* B4 */
494 { 0x00, 0x00 }, /* B5 */
495 { 0x00, 0x00 }, /* B6 */
496 { 0x00, 0x00 }, /* B7 */
497 { 0x00, 0x00 }, /* B8 */
498 { 0x00, 0x00 }, /* B9 */
499 { 0x00, 0x00 }, /* BA */
500 { 0x00, 0x00 }, /* BB */
501 { 0x00, 0x00 }, /* BC */
502 { 0x00, 0x00 }, /* BD */
503 { 0x00, 0x00 }, /* BE */
504 { 0x00, 0x00 }, /* BF */
505 { 0x00, 0x00 }, /* C0 */
506 { 0x00, 0x00 }, /* C1 */
507 { 0x00, 0x00 }, /* C2 */
508 { 0x00, 0x00 }, /* C3 */
509 { 0x00, 0x00 }, /* C4 */
510 { 0x00, 0x00 }, /* C5 */
511 { 0x00, 0x00 }, /* C6 */
512 { 0x00, 0x00 }, /* C7 */
513 { 0x00, 0x00 }, /* C8 */
514 { 0x00, 0x00 }, /* C9 */
515 { 0x00, 0x00 }, /* CA */
516 { 0x00, 0x00 }, /* CB */
517 { 0x00, 0x00 }, /* CC */
518 { 0x00, 0x00 }, /* CD */
519 { 0x00, 0x00 }, /* CE */
520 { 0x00, 0x00 }, /* CF */
521 { 0x00, 0x00 }, /* D0 */
522 { 0x00, 0x00 }, /* D1 */
523 { 0x00, 0x00 }, /* D2 */
524 { 0x00, 0x00 }, /* D3 */
525 { 0x00, 0x00 }, /* D4 */
526 { 0x00, 0x00 }, /* D5 */
527 { 0x00, 0x00 }, /* D6 */
528 { 0x00, 0x00 }, /* D7 */
529 { 0x00, 0x00 }, /* D8 */
530 { 0x00, 0x00 }, /* D9 */
531 { 0x00, 0x00 }, /* DA */
532 { 0x00, 0x00 }, /* DB */
533 { 0x00, 0x00 }, /* DC */
534 { 0x00, 0x00 }, /* DD */
535 { 0x00, 0x00 }, /* DE */
536 { 0x00, 0x00 }, /* DF */
537 { 0x00, 0x00 }, /* E0 */
538 { 0x00, 0x00 }, /* E1 */
539 { 0x00, 0x00 }, /* E2 */
540 { 0x00, 0x00 }, /* E3 */
541 { 0x00, 0x00 }, /* E4 */
542 { 0x00, 0x00 }, /* E5 */
543 { 0x00, 0x00 }, /* E6 */
544 { 0x00, 0x00 }, /* E7 */
545 { 0x00, 0x00 }, /* E8 */
546 { 0x00, 0x00 }, /* E9 */
547 { 0x00, 0x00 }, /* EA */
548 { 0x00, 0x00 }, /* EB */
549 { 0x00, 0x00 }, /* EC */
550 { 0x00, 0x00 }, /* ED */
551 { 0x00, 0x00 }, /* EE */
552 { 0x00, 0x00 }, /* EF */
553 { 0x00, 0x00 }, /* F0 */
554 { 0x00, 0x00 }, /* F1 */
555 { 0x00, 0x00 }, /* F2 */
556 { 0x00, 0x00 }, /* F3 */
557 { 0x00, 0x00 }, /* F4 */
558 { 0x00, 0x00 }, /* F5 */
559 { 0x00, 0x00 }, /* F6 */
560 { 0x00, 0x00 }, /* F7 */
561 { 0x00, 0x00 }, /* F8 */
562 { 0x00, 0x00 }, /* F9 */
563 { 0x00, 0x00 }, /* FA */
564 { 0x00, 0x00 }, /* FB */
565 { 0x00, 0x00 }, /* FC */
566 { 0x00, 0x00 }, /* FD */
567 { 0x00, 0x00 }, /* FE */
568 { 0xFF, 0x00 }, /* FF */
569};
570
571static int max98095_readable(struct snd_soc_codec *codec, unsigned int reg)
572{
573 if (reg >= M98095_REG_CNT)
574 return 0;
575 return max98095_access[reg].readable != 0;
576}
577
578static int max98095_volatile(struct snd_soc_codec *codec, unsigned int reg)
579{
580 if (reg > M98095_REG_MAX_CACHED)
581 return 1;
582
583 switch (reg) {
584 case M98095_000_HOST_DATA:
585 case M98095_001_HOST_INT_STS:
586 case M98095_002_HOST_RSP_STS:
587 case M98095_003_HOST_CMD_STS:
588 case M98095_004_CODEC_STS:
589 case M98095_005_DAI1_ALC_STS:
590 case M98095_006_DAI2_ALC_STS:
591 case M98095_007_JACK_AUTO_STS:
592 case M98095_008_JACK_MANUAL_STS:
593 case M98095_009_JACK_VBAT_STS:
594 case M98095_00A_ACC_ADC_STS:
595 case M98095_00B_MIC_NG_AGC_STS:
596 case M98095_00C_SPK_L_VOLT_STS:
597 case M98095_00D_SPK_R_VOLT_STS:
598 case M98095_00E_TEMP_SENSOR_STS:
599 return 1;
600 }
601
602 return 0;
603}
604
605static const char * const max98095_fltr_mode[] = { "Voice", "Music" };
606static const struct soc_enum max98095_dai1_filter_mode_enum[] = {
607 SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 7, 2, max98095_fltr_mode),
608};
609static const struct soc_enum max98095_dai2_filter_mode_enum[] = {
610 SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 7, 2, max98095_fltr_mode),
611};
612
613static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" };
614
615static const struct soc_enum max98095_extmic_enum =
616 SOC_ENUM_SINGLE(M98095_087_CFG_MIC, 0, 3, max98095_extmic_text);
617
618static const struct snd_kcontrol_new max98095_extmic_mux =
619 SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum);
620
621static const char * const max98095_linein_text[] = { "INA", "INB" };
622
623static const struct soc_enum max98095_linein_enum =
624 SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 6, 2, max98095_linein_text);
625
626static const struct snd_kcontrol_new max98095_linein_mux =
627 SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum);
628
629static const char * const max98095_line_mode_text[] = {
630 "Stereo", "Differential"};
631
632static const struct soc_enum max98095_linein_mode_enum =
633 SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 7, 2, max98095_line_mode_text);
634
635static const struct soc_enum max98095_lineout_mode_enum =
636 SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 4, 2, max98095_line_mode_text);
637
638static const char * const max98095_dai_fltr[] = {
639 "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k",
640 "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"};
641static const struct soc_enum max98095_dai1_dac_filter_enum[] = {
642 SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 0, 6, max98095_dai_fltr),
643};
644static const struct soc_enum max98095_dai2_dac_filter_enum[] = {
645 SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 0, 6, max98095_dai_fltr),
646};
647static const struct soc_enum max98095_dai3_dac_filter_enum[] = {
648 SOC_ENUM_SINGLE(M98095_042_DAI3_FILTERS, 0, 6, max98095_dai_fltr),
649};
650
651static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol,
652 struct snd_ctl_elem_value *ucontrol)
653{
654 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
655 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
656 unsigned int sel = ucontrol->value.integer.value[0];
657
658 max98095->mic1pre = sel;
659 snd_soc_update_bits(codec, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK,
660 (1+sel)<<M98095_MICPRE_SHIFT);
661
662 return 0;
663}
664
665static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol,
666 struct snd_ctl_elem_value *ucontrol)
667{
668 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
669 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
670
671 ucontrol->value.integer.value[0] = max98095->mic1pre;
672 return 0;
673}
674
675static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol,
676 struct snd_ctl_elem_value *ucontrol)
677{
678 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
679 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
680 unsigned int sel = ucontrol->value.integer.value[0];
681
682 max98095->mic2pre = sel;
683 snd_soc_update_bits(codec, M98095_060_LVL_MIC2, M98095_MICPRE_MASK,
684 (1+sel)<<M98095_MICPRE_SHIFT);
685
686 return 0;
687}
688
689static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol,
690 struct snd_ctl_elem_value *ucontrol)
691{
692 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
693 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
694
695 ucontrol->value.integer.value[0] = max98095->mic2pre;
696 return 0;
697}
698
699static const unsigned int max98095_micboost_tlv[] = {
700 TLV_DB_RANGE_HEAD(2),
701 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
702 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
703};
704
705static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0);
706static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0);
707static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0);
708
709static const unsigned int max98095_hp_tlv[] = {
710 TLV_DB_RANGE_HEAD(5),
711 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
712 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
713 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
714 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
715 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
716};
717
718static const unsigned int max98095_spk_tlv[] = {
719 TLV_DB_RANGE_HEAD(4),
720 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0),
721 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0),
722 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0),
723 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0),
724};
725
726static const unsigned int max98095_rcv_lout_tlv[] = {
727 TLV_DB_RANGE_HEAD(5),
728 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
729 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
730 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
731 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
732 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
733};
734
735static const unsigned int max98095_lin_tlv[] = {
736 TLV_DB_RANGE_HEAD(3),
737 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0),
738 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0),
739 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
740};
741
742static const struct snd_kcontrol_new max98095_snd_controls[] = {
743
744 SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L,
745 M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv),
746
747 SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L,
748 M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv),
749
750 SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV,
751 0, 31, 0, max98095_rcv_lout_tlv),
752
753 SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1,
754 M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv),
755
756 SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L,
757 M98095_065_LVL_HP_R, 7, 1, 1),
758
759 SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L,
760 M98095_068_LVL_SPK_R, 7, 1, 1),
761
762 SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1),
763
764 SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1,
765 M98095_063_LVL_LINEOUT2, 7, 1, 1),
766
767 SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1,
768 max98095_mic_tlv),
769
770 SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1,
771 max98095_mic_tlv),
772
773 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
774 M98095_05F_LVL_MIC1, 5, 2, 0,
775 max98095_mic1pre_get, max98095_mic1pre_set,
776 max98095_micboost_tlv),
777 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
778 M98095_060_LVL_MIC2, 5, 2, 0,
779 max98095_mic2pre_get, max98095_mic2pre_set,
780 max98095_micboost_tlv),
781
782 SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1,
783 max98095_lin_tlv),
784
785 SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1,
786 max98095_adc_tlv),
787 SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1,
788 max98095_adc_tlv),
789
790 SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0,
791 max98095_adcboost_tlv),
792 SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0,
793 max98095_adcboost_tlv),
794
795 SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum),
796 SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum),
797 SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum),
798 SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum),
799 SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum),
800
801 SOC_ENUM("Linein Mode", max98095_linein_mode_enum),
802 SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum),
803};
804
805/* Left speaker mixer switch */
806static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = {
807 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0),
808 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0),
809 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
810 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
811 SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0),
812 SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0),
813 SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0),
814 SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0),
815};
816
817/* Right speaker mixer switch */
818static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = {
819 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0),
820 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0),
821 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
822 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
823 SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0),
824 SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0),
825 SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0),
826 SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0),
827};
828
829/* Left headphone mixer switch */
830static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = {
831 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0),
832 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0),
833 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0),
834 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0),
835 SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0),
836 SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0),
837};
838
839/* Right headphone mixer switch */
840static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = {
841 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0),
842 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0),
843 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0),
844 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0),
845 SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0),
846 SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0),
847};
848
849/* Receiver earpiece mixer switch */
850static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = {
851 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0),
852 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0),
853 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0),
854 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0),
855 SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0),
856 SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0),
857};
858
859/* Left lineout mixer switch */
860static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = {
861 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0),
862 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0),
863 SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0),
864 SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0),
865 SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0),
866 SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0),
867};
868
869/* Right lineout mixer switch */
870static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = {
871 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0),
872 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0),
873 SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0),
874 SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0),
875 SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0),
876 SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0),
877};
878
879/* Left ADC mixer switch */
880static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = {
881 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0),
882 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0),
883 SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0),
884 SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0),
885};
886
887/* Right ADC mixer switch */
888static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = {
889 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0),
890 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0),
891 SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0),
892 SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0),
893};
894
895static int max98095_mic_event(struct snd_soc_dapm_widget *w,
896 struct snd_kcontrol *kcontrol, int event)
897{
898 struct snd_soc_codec *codec = w->codec;
899 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
900
901 switch (event) {
902 case SND_SOC_DAPM_POST_PMU:
903 if (w->reg == M98095_05F_LVL_MIC1) {
904 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK,
905 (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT);
906 } else {
907 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK,
908 (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT);
909 }
910 break;
911 case SND_SOC_DAPM_POST_PMD:
912 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 0);
913 break;
914 default:
915 return -EINVAL;
916 }
917
918 return 0;
919}
920
921/*
922 * The line inputs are stereo inputs with the left and right
923 * channels sharing a common PGA power control signal.
924 */
925static int max98095_line_pga(struct snd_soc_dapm_widget *w,
926 int event, u8 channel)
927{
928 struct snd_soc_codec *codec = w->codec;
929 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
930 u8 *state;
931
932 BUG_ON(!((channel == 1) || (channel == 2)));
933
934 state = &max98095->lin_state;
935
936 switch (event) {
937 case SND_SOC_DAPM_POST_PMU:
938 *state |= channel;
939 snd_soc_update_bits(codec, w->reg,
940 (1 << w->shift), (1 << w->shift));
941 break;
942 case SND_SOC_DAPM_POST_PMD:
943 *state &= ~channel;
944 if (*state == 0) {
945 snd_soc_update_bits(codec, w->reg,
946 (1 << w->shift), 0);
947 }
948 break;
949 default:
950 return -EINVAL;
951 }
952
953 return 0;
954}
955
956static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w,
957 struct snd_kcontrol *k, int event)
958{
959 return max98095_line_pga(w, event, 1);
960}
961
962static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w,
963 struct snd_kcontrol *k, int event)
964{
965 return max98095_line_pga(w, event, 2);
966}
967
968/*
969 * The stereo line out mixer outputs to two stereo line outs.
970 * The 2nd pair has a separate set of enables.
971 */
972static int max98095_lineout_event(struct snd_soc_dapm_widget *w,
973 struct snd_kcontrol *kcontrol, int event)
974{
975 struct snd_soc_codec *codec = w->codec;
976
977 switch (event) {
978 case SND_SOC_DAPM_POST_PMU:
979 snd_soc_update_bits(codec, w->reg,
980 (1 << (w->shift+2)), (1 << (w->shift+2)));
981 break;
982 case SND_SOC_DAPM_POST_PMD:
983 snd_soc_update_bits(codec, w->reg,
984 (1 << (w->shift+2)), 0);
985 break;
986 default:
987 return -EINVAL;
988 }
989
990 return 0;
991}
992
993static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = {
994
995 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0),
996 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0),
997
998 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
999 M98095_091_PWR_EN_OUT, 0, 0),
1000 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
1001 M98095_091_PWR_EN_OUT, 1, 0),
1002 SND_SOC_DAPM_DAC("DACM2", "Aux Playback",
1003 M98095_091_PWR_EN_OUT, 2, 0),
1004 SND_SOC_DAPM_DAC("DACM3", "Voice Playback",
1005 M98095_091_PWR_EN_OUT, 2, 0),
1006
1007 SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT,
1008 6, 0, NULL, 0),
1009 SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT,
1010 7, 0, NULL, 0),
1011
1012 SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT,
1013 4, 0, NULL, 0),
1014 SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT,
1015 5, 0, NULL, 0),
1016
1017 SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT,
1018 3, 0, NULL, 0),
1019
1020 SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT,
1021 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
1022 SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT,
1023 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
1024
1025 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
1026 &max98095_extmic_mux),
1027
1028 SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0,
1029 &max98095_linein_mux),
1030
1031 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1032 &max98095_left_hp_mixer_controls[0],
1033 ARRAY_SIZE(max98095_left_hp_mixer_controls)),
1034
1035 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1036 &max98095_right_hp_mixer_controls[0],
1037 ARRAY_SIZE(max98095_right_hp_mixer_controls)),
1038
1039 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1040 &max98095_left_speaker_mixer_controls[0],
1041 ARRAY_SIZE(max98095_left_speaker_mixer_controls)),
1042
1043 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1044 &max98095_right_speaker_mixer_controls[0],
1045 ARRAY_SIZE(max98095_right_speaker_mixer_controls)),
1046
1047 SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0,
1048 &max98095_mono_rcv_mixer_controls[0],
1049 ARRAY_SIZE(max98095_mono_rcv_mixer_controls)),
1050
1051 SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0,
1052 &max98095_left_lineout_mixer_controls[0],
1053 ARRAY_SIZE(max98095_left_lineout_mixer_controls)),
1054
1055 SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0,
1056 &max98095_right_lineout_mixer_controls[0],
1057 ARRAY_SIZE(max98095_right_lineout_mixer_controls)),
1058
1059 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1060 &max98095_left_ADC_mixer_controls[0],
1061 ARRAY_SIZE(max98095_left_ADC_mixer_controls)),
1062
1063 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1064 &max98095_right_ADC_mixer_controls[0],
1065 ARRAY_SIZE(max98095_right_ADC_mixer_controls)),
1066
1067 SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1,
1068 5, 0, NULL, 0, max98095_mic_event,
1069 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1070
1071 SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2,
1072 5, 0, NULL, 0, max98095_mic_event,
1073 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1074
1075 SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN,
1076 7, 0, NULL, 0, max98095_pga_in1_event,
1077 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1078
1079 SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN,
1080 7, 0, NULL, 0, max98095_pga_in2_event,
1081 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1082
1083 SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0),
1084 SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0),
1085
1086 SND_SOC_DAPM_OUTPUT("HPL"),
1087 SND_SOC_DAPM_OUTPUT("HPR"),
1088 SND_SOC_DAPM_OUTPUT("SPKL"),
1089 SND_SOC_DAPM_OUTPUT("SPKR"),
1090 SND_SOC_DAPM_OUTPUT("RCV"),
1091 SND_SOC_DAPM_OUTPUT("OUT1"),
1092 SND_SOC_DAPM_OUTPUT("OUT2"),
1093 SND_SOC_DAPM_OUTPUT("OUT3"),
1094 SND_SOC_DAPM_OUTPUT("OUT4"),
1095
1096 SND_SOC_DAPM_INPUT("MIC1"),
1097 SND_SOC_DAPM_INPUT("MIC2"),
1098 SND_SOC_DAPM_INPUT("INA1"),
1099 SND_SOC_DAPM_INPUT("INA2"),
1100 SND_SOC_DAPM_INPUT("INB1"),
1101 SND_SOC_DAPM_INPUT("INB2"),
1102};
1103
1104static const struct snd_soc_dapm_route max98095_audio_map[] = {
1105 /* Left headphone output mixer */
1106 {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"},
1107 {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"},
1108 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1109 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1110 {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"},
1111 {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"},
1112
1113 /* Right headphone output mixer */
1114 {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"},
1115 {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"},
1116 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1117 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1118 {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"},
1119 {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"},
1120
1121 /* Left speaker output mixer */
1122 {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"},
1123 {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"},
1124 {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
1125 {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
1126 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1127 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1128 {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"},
1129 {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"},
1130
1131 /* Right speaker output mixer */
1132 {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"},
1133 {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"},
1134 {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
1135 {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
1136 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1137 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1138 {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"},
1139 {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"},
1140
1141 /* Earpiece/Receiver output mixer */
1142 {"Receiver Mixer", "Left DAC1 Switch", "DACL1"},
1143 {"Receiver Mixer", "Right DAC1 Switch", "DACR1"},
1144 {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1145 {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1146 {"Receiver Mixer", "IN1 Switch", "IN1 Input"},
1147 {"Receiver Mixer", "IN2 Switch", "IN2 Input"},
1148
1149 /* Left Lineout output mixer */
1150 {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"},
1151 {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"},
1152 {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
1153 {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
1154 {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"},
1155 {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"},
1156
1157 /* Right lineout output mixer */
1158 {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"},
1159 {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"},
1160 {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
1161 {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
1162 {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"},
1163 {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"},
1164
1165 {"HP Left Out", NULL, "Left Headphone Mixer"},
1166 {"HP Right Out", NULL, "Right Headphone Mixer"},
1167 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1168 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1169 {"RCV Mono Out", NULL, "Receiver Mixer"},
1170 {"LINE Left Out", NULL, "Left Lineout Mixer"},
1171 {"LINE Right Out", NULL, "Right Lineout Mixer"},
1172
1173 {"HPL", NULL, "HP Left Out"},
1174 {"HPR", NULL, "HP Right Out"},
1175 {"SPKL", NULL, "SPK Left Out"},
1176 {"SPKR", NULL, "SPK Right Out"},
1177 {"RCV", NULL, "RCV Mono Out"},
1178 {"OUT1", NULL, "LINE Left Out"},
1179 {"OUT2", NULL, "LINE Right Out"},
1180 {"OUT3", NULL, "LINE Left Out"},
1181 {"OUT4", NULL, "LINE Right Out"},
1182
1183 /* Left ADC input mixer */
1184 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1185 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1186 {"Left ADC Mixer", "IN1 Switch", "IN1 Input"},
1187 {"Left ADC Mixer", "IN2 Switch", "IN2 Input"},
1188
1189 /* Right ADC input mixer */
1190 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1191 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1192 {"Right ADC Mixer", "IN1 Switch", "IN1 Input"},
1193 {"Right ADC Mixer", "IN2 Switch", "IN2 Input"},
1194
1195 /* Inputs */
1196 {"ADCL", NULL, "Left ADC Mixer"},
1197 {"ADCR", NULL, "Right ADC Mixer"},
1198
1199 {"IN1 Input", NULL, "INA1"},
1200 {"IN2 Input", NULL, "INA2"},
1201
1202 {"MIC1 Input", NULL, "MIC1"},
1203 {"MIC2 Input", NULL, "MIC2"},
1204};
1205
1206static int max98095_add_widgets(struct snd_soc_codec *codec)
1207{
1208 snd_soc_add_controls(codec, max98095_snd_controls,
1209 ARRAY_SIZE(max98095_snd_controls));
1210
1211 return 0;
1212}
1213
1214/* codec mclk clock divider coefficients */
1215static const struct {
1216 u32 rate;
1217 u8 sr;
1218} rate_table[] = {
1219 {8000, 0x01},
1220 {11025, 0x02},
1221 {16000, 0x03},
1222 {22050, 0x04},
1223 {24000, 0x05},
1224 {32000, 0x06},
1225 {44100, 0x07},
1226 {48000, 0x08},
1227 {88200, 0x09},
1228 {96000, 0x0A},
1229};
1230
1231static int rate_value(int rate, u8 *value)
1232{
1233 int i;
1234
1235 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
1236 if (rate_table[i].rate >= rate) {
1237 *value = rate_table[i].sr;
1238 return 0;
1239 }
1240 }
1241 *value = rate_table[0].sr;
1242 return -EINVAL;
1243}
1244
1245static int max98095_dai1_hw_params(struct snd_pcm_substream *substream,
1246 struct snd_pcm_hw_params *params,
1247 struct snd_soc_dai *dai)
1248{
1249 struct snd_soc_codec *codec = dai->codec;
1250 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1251 struct max98095_cdata *cdata;
1252 unsigned long long ni;
1253 unsigned int rate;
1254 u8 regval;
1255
1256 cdata = &max98095->dai[0];
1257
1258 rate = params_rate(params);
1259
1260 switch (params_format(params)) {
1261 case SNDRV_PCM_FORMAT_S16_LE:
1262 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1263 M98095_DAI_WS, 0);
1264 break;
1265 case SNDRV_PCM_FORMAT_S24_LE:
1266 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1267 M98095_DAI_WS, M98095_DAI_WS);
1268 break;
1269 default:
1270 return -EINVAL;
1271 }
1272
1273 if (rate_value(rate, &regval))
1274 return -EINVAL;
1275
1276 snd_soc_update_bits(codec, M98095_027_DAI1_CLKMODE,
1277 M98095_CLKMODE_MASK, regval);
1278 cdata->rate = rate;
1279
1280 /* Configure NI when operating as master */
1281 if (snd_soc_read(codec, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
1282 if (max98095->sysclk == 0) {
1283 dev_err(codec->dev, "Invalid system clock frequency\n");
1284 return -EINVAL;
1285 }
1286 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1287 * (unsigned long long int)rate;
1288 do_div(ni, (unsigned long long int)max98095->sysclk);
1289 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI,
1290 (ni >> 8) & 0x7F);
1291 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO,
1292 ni & 0xFF);
1293 }
1294
1295 /* Update sample rate mode */
1296 if (rate < 50000)
1297 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS,
1298 M98095_DAI_DHF, 0);
1299 else
1300 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS,
1301 M98095_DAI_DHF, M98095_DAI_DHF);
1302
1303 return 0;
1304}
1305
1306static int max98095_dai2_hw_params(struct snd_pcm_substream *substream,
1307 struct snd_pcm_hw_params *params,
1308 struct snd_soc_dai *dai)
1309{
1310 struct snd_soc_codec *codec = dai->codec;
1311 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1312 struct max98095_cdata *cdata;
1313 unsigned long long ni;
1314 unsigned int rate;
1315 u8 regval;
1316
1317 cdata = &max98095->dai[1];
1318
1319 rate = params_rate(params);
1320
1321 switch (params_format(params)) {
1322 case SNDRV_PCM_FORMAT_S16_LE:
1323 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1324 M98095_DAI_WS, 0);
1325 break;
1326 case SNDRV_PCM_FORMAT_S24_LE:
1327 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1328 M98095_DAI_WS, M98095_DAI_WS);
1329 break;
1330 default:
1331 return -EINVAL;
1332 }
1333
1334 if (rate_value(rate, &regval))
1335 return -EINVAL;
1336
1337 snd_soc_update_bits(codec, M98095_031_DAI2_CLKMODE,
1338 M98095_CLKMODE_MASK, regval);
1339 cdata->rate = rate;
1340
1341 /* Configure NI when operating as master */
1342 if (snd_soc_read(codec, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
1343 if (max98095->sysclk == 0) {
1344 dev_err(codec->dev, "Invalid system clock frequency\n");
1345 return -EINVAL;
1346 }
1347 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1348 * (unsigned long long int)rate;
1349 do_div(ni, (unsigned long long int)max98095->sysclk);
1350 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI,
1351 (ni >> 8) & 0x7F);
1352 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO,
1353 ni & 0xFF);
1354 }
1355
1356 /* Update sample rate mode */
1357 if (rate < 50000)
1358 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS,
1359 M98095_DAI_DHF, 0);
1360 else
1361 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS,
1362 M98095_DAI_DHF, M98095_DAI_DHF);
1363
1364 return 0;
1365}
1366
1367static int max98095_dai3_hw_params(struct snd_pcm_substream *substream,
1368 struct snd_pcm_hw_params *params,
1369 struct snd_soc_dai *dai)
1370{
1371 struct snd_soc_codec *codec = dai->codec;
1372 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1373 struct max98095_cdata *cdata;
1374 unsigned long long ni;
1375 unsigned int rate;
1376 u8 regval;
1377
1378 cdata = &max98095->dai[2];
1379
1380 rate = params_rate(params);
1381
1382 switch (params_format(params)) {
1383 case SNDRV_PCM_FORMAT_S16_LE:
1384 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1385 M98095_DAI_WS, 0);
1386 break;
1387 case SNDRV_PCM_FORMAT_S24_LE:
1388 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1389 M98095_DAI_WS, M98095_DAI_WS);
1390 break;
1391 default:
1392 return -EINVAL;
1393 }
1394
1395 if (rate_value(rate, &regval))
1396 return -EINVAL;
1397
1398 snd_soc_update_bits(codec, M98095_03B_DAI3_CLKMODE,
1399 M98095_CLKMODE_MASK, regval);
1400 cdata->rate = rate;
1401
1402 /* Configure NI when operating as master */
1403 if (snd_soc_read(codec, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
1404 if (max98095->sysclk == 0) {
1405 dev_err(codec->dev, "Invalid system clock frequency\n");
1406 return -EINVAL;
1407 }
1408 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1409 * (unsigned long long int)rate;
1410 do_div(ni, (unsigned long long int)max98095->sysclk);
1411 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI,
1412 (ni >> 8) & 0x7F);
1413 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO,
1414 ni & 0xFF);
1415 }
1416
1417 /* Update sample rate mode */
1418 if (rate < 50000)
1419 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS,
1420 M98095_DAI_DHF, 0);
1421 else
1422 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS,
1423 M98095_DAI_DHF, M98095_DAI_DHF);
1424
1425 return 0;
1426}
1427
1428static int max98095_dai_set_sysclk(struct snd_soc_dai *dai,
1429 int clk_id, unsigned int freq, int dir)
1430{
1431 struct snd_soc_codec *codec = dai->codec;
1432 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1433
1434 /* Requested clock frequency is already setup */
1435 if (freq == max98095->sysclk)
1436 return 0;
1437
1438 max98095->sysclk = freq; /* remember current sysclk */
1439
1440 /* Setup clocks for slave mode, and using the PLL
1441 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1442 * 0x02 (when master clk is 20MHz to 40MHz)..
1443 * 0x03 (when master clk is 40MHz to 60MHz)..
1444 */
1445 if ((freq >= 10000000) && (freq < 20000000)) {
1446 snd_soc_write(codec, M98095_026_SYS_CLK, 0x10);
1447 } else if ((freq >= 20000000) && (freq < 40000000)) {
1448 snd_soc_write(codec, M98095_026_SYS_CLK, 0x20);
1449 } else if ((freq >= 40000000) && (freq < 60000000)) {
1450 snd_soc_write(codec, M98095_026_SYS_CLK, 0x30);
1451 } else {
1452 dev_err(codec->dev, "Invalid master clock frequency\n");
1453 return -EINVAL;
1454 }
1455
1456 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1457
1458 max98095->sysclk = freq;
1459 return 0;
1460}
1461
1462static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1463 unsigned int fmt)
1464{
1465 struct snd_soc_codec *codec = codec_dai->codec;
1466 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1467 struct max98095_cdata *cdata;
1468 u8 regval = 0;
1469
1470 cdata = &max98095->dai[0];
1471
1472 if (fmt != cdata->fmt) {
1473 cdata->fmt = fmt;
1474
1475 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1476 case SND_SOC_DAIFMT_CBS_CFS:
1477 /* Slave mode PLL */
1478 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI,
1479 0x80);
1480 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO,
1481 0x00);
1482 break;
1483 case SND_SOC_DAIFMT_CBM_CFM:
1484 /* Set to master mode */
1485 regval |= M98095_DAI_MAS;
1486 break;
1487 case SND_SOC_DAIFMT_CBS_CFM:
1488 case SND_SOC_DAIFMT_CBM_CFS:
1489 default:
1490 dev_err(codec->dev, "Clock mode unsupported");
1491 return -EINVAL;
1492 }
1493
1494 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1495 case SND_SOC_DAIFMT_I2S:
1496 regval |= M98095_DAI_DLY;
1497 break;
1498 case SND_SOC_DAIFMT_LEFT_J:
1499 break;
1500 default:
1501 return -EINVAL;
1502 }
1503
1504 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1505 case SND_SOC_DAIFMT_NB_NF:
1506 break;
1507 case SND_SOC_DAIFMT_NB_IF:
1508 regval |= M98095_DAI_WCI;
1509 break;
1510 case SND_SOC_DAIFMT_IB_NF:
1511 regval |= M98095_DAI_BCI;
1512 break;
1513 case SND_SOC_DAIFMT_IB_IF:
1514 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1515 break;
1516 default:
1517 return -EINVAL;
1518 }
1519
1520 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1521 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1522 M98095_DAI_WCI, regval);
1523
1524 snd_soc_write(codec, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64);
1525 }
1526
1527 return 0;
1528}
1529
1530static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1531 unsigned int fmt)
1532{
1533 struct snd_soc_codec *codec = codec_dai->codec;
1534 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1535 struct max98095_cdata *cdata;
1536 u8 regval = 0;
1537
1538 cdata = &max98095->dai[1];
1539
1540 if (fmt != cdata->fmt) {
1541 cdata->fmt = fmt;
1542
1543 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1544 case SND_SOC_DAIFMT_CBS_CFS:
1545 /* Slave mode PLL */
1546 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI,
1547 0x80);
1548 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO,
1549 0x00);
1550 break;
1551 case SND_SOC_DAIFMT_CBM_CFM:
1552 /* Set to master mode */
1553 regval |= M98095_DAI_MAS;
1554 break;
1555 case SND_SOC_DAIFMT_CBS_CFM:
1556 case SND_SOC_DAIFMT_CBM_CFS:
1557 default:
1558 dev_err(codec->dev, "Clock mode unsupported");
1559 return -EINVAL;
1560 }
1561
1562 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1563 case SND_SOC_DAIFMT_I2S:
1564 regval |= M98095_DAI_DLY;
1565 break;
1566 case SND_SOC_DAIFMT_LEFT_J:
1567 break;
1568 default:
1569 return -EINVAL;
1570 }
1571
1572 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1573 case SND_SOC_DAIFMT_NB_NF:
1574 break;
1575 case SND_SOC_DAIFMT_NB_IF:
1576 regval |= M98095_DAI_WCI;
1577 break;
1578 case SND_SOC_DAIFMT_IB_NF:
1579 regval |= M98095_DAI_BCI;
1580 break;
1581 case SND_SOC_DAIFMT_IB_IF:
1582 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1583 break;
1584 default:
1585 return -EINVAL;
1586 }
1587
1588 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1589 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1590 M98095_DAI_WCI, regval);
1591
1592 snd_soc_write(codec, M98095_035_DAI2_CLOCK,
1593 M98095_DAI_BSEL64);
1594 }
1595
1596 return 0;
1597}
1598
1599static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai,
1600 unsigned int fmt)
1601{
1602 struct snd_soc_codec *codec = codec_dai->codec;
1603 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1604 struct max98095_cdata *cdata;
1605 u8 regval = 0;
1606
1607 cdata = &max98095->dai[2];
1608
1609 if (fmt != cdata->fmt) {
1610 cdata->fmt = fmt;
1611
1612 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1613 case SND_SOC_DAIFMT_CBS_CFS:
1614 /* Slave mode PLL */
1615 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI,
1616 0x80);
1617 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO,
1618 0x00);
1619 break;
1620 case SND_SOC_DAIFMT_CBM_CFM:
1621 /* Set to master mode */
1622 regval |= M98095_DAI_MAS;
1623 break;
1624 case SND_SOC_DAIFMT_CBS_CFM:
1625 case SND_SOC_DAIFMT_CBM_CFS:
1626 default:
1627 dev_err(codec->dev, "Clock mode unsupported");
1628 return -EINVAL;
1629 }
1630
1631 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1632 case SND_SOC_DAIFMT_I2S:
1633 regval |= M98095_DAI_DLY;
1634 break;
1635 case SND_SOC_DAIFMT_LEFT_J:
1636 break;
1637 default:
1638 return -EINVAL;
1639 }
1640
1641 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1642 case SND_SOC_DAIFMT_NB_NF:
1643 break;
1644 case SND_SOC_DAIFMT_NB_IF:
1645 regval |= M98095_DAI_WCI;
1646 break;
1647 case SND_SOC_DAIFMT_IB_NF:
1648 regval |= M98095_DAI_BCI;
1649 break;
1650 case SND_SOC_DAIFMT_IB_IF:
1651 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1652 break;
1653 default:
1654 return -EINVAL;
1655 }
1656
1657 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1658 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1659 M98095_DAI_WCI, regval);
1660
1661 snd_soc_write(codec, M98095_03F_DAI3_CLOCK,
1662 M98095_DAI_BSEL64);
1663 }
1664
1665 return 0;
1666}
1667
1668static int max98095_set_bias_level(struct snd_soc_codec *codec,
1669 enum snd_soc_bias_level level)
1670{
1671 int ret;
1672
1673 switch (level) {
1674 case SND_SOC_BIAS_ON:
1675 break;
1676
1677 case SND_SOC_BIAS_PREPARE:
1678 break;
1679
1680 case SND_SOC_BIAS_STANDBY:
1681 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1682 ret = snd_soc_cache_sync(codec);
1683
1684 if (ret != 0) {
1685 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
1686 return ret;
1687 }
1688 }
1689
1690 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
1691 M98095_MBEN, M98095_MBEN);
1692 break;
1693
1694 case SND_SOC_BIAS_OFF:
1695 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
1696 M98095_MBEN, 0);
1697 codec->cache_sync = 1;
1698 break;
1699 }
1700 codec->dapm.bias_level = level;
1701 return 0;
1702}
1703
1704#define MAX98095_RATES SNDRV_PCM_RATE_8000_96000
1705#define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1706
1707static struct snd_soc_dai_ops max98095_dai1_ops = {
1708 .set_sysclk = max98095_dai_set_sysclk,
1709 .set_fmt = max98095_dai1_set_fmt,
1710 .hw_params = max98095_dai1_hw_params,
1711};
1712
1713static struct snd_soc_dai_ops max98095_dai2_ops = {
1714 .set_sysclk = max98095_dai_set_sysclk,
1715 .set_fmt = max98095_dai2_set_fmt,
1716 .hw_params = max98095_dai2_hw_params,
1717};
1718
1719static struct snd_soc_dai_ops max98095_dai3_ops = {
1720 .set_sysclk = max98095_dai_set_sysclk,
1721 .set_fmt = max98095_dai3_set_fmt,
1722 .hw_params = max98095_dai3_hw_params,
1723};
1724
1725static struct snd_soc_dai_driver max98095_dai[] = {
1726{
1727 .name = "HiFi",
1728 .playback = {
1729 .stream_name = "HiFi Playback",
1730 .channels_min = 1,
1731 .channels_max = 2,
1732 .rates = MAX98095_RATES,
1733 .formats = MAX98095_FORMATS,
1734 },
1735 .capture = {
1736 .stream_name = "HiFi Capture",
1737 .channels_min = 1,
1738 .channels_max = 2,
1739 .rates = MAX98095_RATES,
1740 .formats = MAX98095_FORMATS,
1741 },
1742 .ops = &max98095_dai1_ops,
1743},
1744{
1745 .name = "Aux",
1746 .playback = {
1747 .stream_name = "Aux Playback",
1748 .channels_min = 1,
1749 .channels_max = 1,
1750 .rates = MAX98095_RATES,
1751 .formats = MAX98095_FORMATS,
1752 },
1753 .ops = &max98095_dai2_ops,
1754},
1755{
1756 .name = "Voice",
1757 .playback = {
1758 .stream_name = "Voice Playback",
1759 .channels_min = 1,
1760 .channels_max = 1,
1761 .rates = MAX98095_RATES,
1762 .formats = MAX98095_FORMATS,
1763 },
1764 .ops = &max98095_dai3_ops,
1765}
1766
1767};
1768
1769static void max98095_handle_pdata(struct snd_soc_codec *codec)
1770{
1771 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1772 struct max98095_pdata *pdata = max98095->pdata;
1773 u8 regval = 0;
1774
1775 if (!pdata) {
1776 dev_dbg(codec->dev, "No platform data\n");
1777 return;
1778 }
1779
1780 /* Configure mic for analog/digital mic mode */
1781 if (pdata->digmic_left_mode)
1782 regval |= M98095_DIGMIC_L;
1783
1784 if (pdata->digmic_right_mode)
1785 regval |= M98095_DIGMIC_R;
1786
1787 snd_soc_write(codec, M98095_087_CFG_MIC, regval);
1788}
1789
1790#ifdef CONFIG_PM
1791static int max98095_suspend(struct snd_soc_codec *codec, pm_message_t state)
1792{
1793 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF);
1794
1795 return 0;
1796}
1797
1798static int max98095_resume(struct snd_soc_codec *codec)
1799{
1800 max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1801
1802 return 0;
1803}
1804#else
1805#define max98095_suspend NULL
1806#define max98095_resume NULL
1807#endif
1808
1809static int max98095_reset(struct snd_soc_codec *codec)
1810{
1811 int i, ret;
1812
1813 /* Gracefully reset the DSP core and the codec hardware
1814 * in a proper sequence */
1815 ret = snd_soc_write(codec, M98095_00F_HOST_CFG, 0);
1816 if (ret < 0) {
1817 dev_err(codec->dev, "Failed to reset DSP: %d\n", ret);
1818 return ret;
1819 }
1820
1821 ret = snd_soc_write(codec, M98095_097_PWR_SYS, 0);
1822 if (ret < 0) {
1823 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
1824 return ret;
1825 }
1826
1827 /* Reset to hardware default for registers, as there is not
1828 * a soft reset hardware control register */
1829 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
1830 ret = snd_soc_write(codec, i, max98095_reg_def[i]);
1831 if (ret < 0) {
1832 dev_err(codec->dev, "Failed to reset: %d\n", ret);
1833 return ret;
1834 }
1835 }
1836
1837 return ret;
1838}
1839
1840static int max98095_probe(struct snd_soc_codec *codec)
1841{
1842 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1843 struct max98095_cdata *cdata;
1844 int ret = 0;
1845
1846 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
1847 if (ret != 0) {
1848 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1849 return ret;
1850 }
1851
1852 /* reset the codec, the DSP core, and disable all interrupts */
1853 max98095_reset(codec);
1854
1855 /* initialize private data */
1856
1857 max98095->sysclk = (unsigned)-1;
1858
1859 cdata = &max98095->dai[0];
1860 cdata->rate = (unsigned)-1;
1861 cdata->fmt = (unsigned)-1;
1862
1863 cdata = &max98095->dai[1];
1864 cdata->rate = (unsigned)-1;
1865 cdata->fmt = (unsigned)-1;
1866
1867 cdata = &max98095->dai[2];
1868 cdata->rate = (unsigned)-1;
1869 cdata->fmt = (unsigned)-1;
1870
1871 max98095->lin_state = 0;
1872 max98095->mic1pre = 0;
1873 max98095->mic2pre = 0;
1874
1875 ret = snd_soc_read(codec, M98095_0FF_REV_ID);
1876 if (ret < 0) {
1877 dev_err(codec->dev, "Failed to read device revision: %d\n",
1878 ret);
1879 goto err_access;
1880 }
1881 dev_info(codec->dev, "revision %c\n", ret + 'A');
1882
1883 snd_soc_write(codec, M98095_097_PWR_SYS, M98095_PWRSV);
1884
1885 /* initialize registers cache to hardware default */
1886 max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1887
1888 snd_soc_write(codec, M98095_048_MIX_DAC_LR,
1889 M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR);
1890
1891 snd_soc_write(codec, M98095_049_MIX_DAC_M,
1892 M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM);
1893
1894 snd_soc_write(codec, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM);
1895 snd_soc_write(codec, M98095_045_CFG_DSP, M98095_DSPNORMAL);
1896 snd_soc_write(codec, M98095_04E_CFG_HP, M98095_HPNORMAL);
1897
1898 snd_soc_write(codec, M98095_02C_DAI1_IOCFG,
1899 M98095_S1NORMAL|M98095_SDATA);
1900
1901 snd_soc_write(codec, M98095_036_DAI2_IOCFG,
1902 M98095_S2NORMAL|M98095_SDATA);
1903
1904 snd_soc_write(codec, M98095_040_DAI3_IOCFG,
1905 M98095_S3NORMAL|M98095_SDATA);
1906
1907 max98095_handle_pdata(codec);
1908
1909 /* take the codec out of the shut down */
1910 snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN,
1911 M98095_SHDNRUN);
1912
1913 max98095_add_widgets(codec);
1914
1915err_access:
1916 return ret;
1917}
1918
1919static int max98095_remove(struct snd_soc_codec *codec)
1920{
1921 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF);
1922
1923 return 0;
1924}
1925
1926static struct snd_soc_codec_driver soc_codec_dev_max98095 = {
1927 .probe = max98095_probe,
1928 .remove = max98095_remove,
1929 .suspend = max98095_suspend,
1930 .resume = max98095_resume,
1931 .set_bias_level = max98095_set_bias_level,
1932 .reg_cache_size = ARRAY_SIZE(max98095_reg_def),
1933 .reg_word_size = sizeof(u8),
1934 .reg_cache_default = max98095_reg_def,
1935 .readable_register = max98095_readable,
1936 .volatile_register = max98095_volatile,
1937 .dapm_widgets = max98095_dapm_widgets,
1938 .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets),
1939 .dapm_routes = max98095_audio_map,
1940 .num_dapm_routes = ARRAY_SIZE(max98095_audio_map),
1941};
1942
1943static int max98095_i2c_probe(struct i2c_client *i2c,
1944 const struct i2c_device_id *id)
1945{
1946 struct max98095_priv *max98095;
1947 int ret;
1948
1949 max98095 = kzalloc(sizeof(struct max98095_priv), GFP_KERNEL);
1950 if (max98095 == NULL)
1951 return -ENOMEM;
1952
1953 max98095->devtype = id->driver_data;
1954 i2c_set_clientdata(i2c, max98095);
1955 max98095->control_data = i2c;
1956 max98095->pdata = i2c->dev.platform_data;
1957
1958 ret = snd_soc_register_codec(&i2c->dev,
1959 &soc_codec_dev_max98095, &max98095_dai[0], 3);
1960 if (ret < 0)
1961 kfree(max98095);
1962 return ret;
1963}
1964
1965static int __devexit max98095_i2c_remove(struct i2c_client *client)
1966{
1967 snd_soc_unregister_codec(&client->dev);
1968 kfree(i2c_get_clientdata(client));
1969
1970 return 0;
1971}
1972
1973static const struct i2c_device_id max98095_i2c_id[] = {
1974 { "max98095", MAX98095 },
1975 { }
1976};
1977MODULE_DEVICE_TABLE(i2c, max98095_i2c_id);
1978
1979static struct i2c_driver max98095_i2c_driver = {
1980 .driver = {
1981 .name = "max98095",
1982 .owner = THIS_MODULE,
1983 },
1984 .probe = max98095_i2c_probe,
1985 .remove = __devexit_p(max98095_i2c_remove),
1986 .id_table = max98095_i2c_id,
1987};
1988
1989static int __init max98095_init(void)
1990{
1991 int ret;
1992
1993 ret = i2c_add_driver(&max98095_i2c_driver);
1994 if (ret)
1995 pr_err("Failed to register max98095 I2C driver: %d\n", ret);
1996
1997 return ret;
1998}
1999module_init(max98095_init);
2000
2001static void __exit max98095_exit(void)
2002{
2003 i2c_del_driver(&max98095_i2c_driver);
2004}
2005module_exit(max98095_exit);
2006
2007MODULE_DESCRIPTION("ALSA SoC MAX98095 driver");
2008MODULE_AUTHOR("Peter Hsiang");
2009MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/max98095.h b/sound/soc/codecs/max98095.h
new file mode 100644
index 000000000000..5b22bc8dbede
--- /dev/null
+++ b/sound/soc/codecs/max98095.h
@@ -0,0 +1,284 @@
1/*
2 * max98095.h -- MAX98095 ALSA SoC Audio driver
3 *
4 * Copyright 2011 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef _MAX98095_H
12#define _MAX98095_H
13
14/*
15 * MAX98095 Registers Definition
16 */
17
18#define M98095_000_HOST_DATA 0x00
19#define M98095_001_HOST_INT_STS 0x01
20#define M98095_002_HOST_RSP_STS 0x02
21#define M98095_003_HOST_CMD_STS 0x03
22#define M98095_004_CODEC_STS 0x04
23#define M98095_005_DAI1_ALC_STS 0x05
24#define M98095_006_DAI2_ALC_STS 0x06
25#define M98095_007_JACK_AUTO_STS 0x07
26#define M98095_008_JACK_MANUAL_STS 0x08
27#define M98095_009_JACK_VBAT_STS 0x09
28#define M98095_00A_ACC_ADC_STS 0x0A
29#define M98095_00B_MIC_NG_AGC_STS 0x0B
30#define M98095_00C_SPK_L_VOLT_STS 0x0C
31#define M98095_00D_SPK_R_VOLT_STS 0x0D
32#define M98095_00E_TEMP_SENSOR_STS 0x0E
33#define M98095_00F_HOST_CFG 0x0F
34#define M98095_010_HOST_INT_CFG 0x10
35#define M98095_011_HOST_INT_EN 0x11
36#define M98095_012_CODEC_INT_EN 0x12
37#define M98095_013_JACK_INT_EN 0x13
38#define M98095_014_JACK_INT_EN 0x14
39#define M98095_015_DEC 0x15
40#define M98095_016_RESERVED 0x16
41#define M98095_017_RESERVED 0x17
42#define M98095_018_KEYCODE3 0x18
43#define M98095_019_KEYCODE2 0x19
44#define M98095_01A_KEYCODE1 0x1A
45#define M98095_01B_KEYCODE0 0x1B
46#define M98095_01C_OEMCODE1 0x1C
47#define M98095_01D_OEMCODE0 0x1D
48#define M98095_01E_XCFG1 0x1E
49#define M98095_01F_XCFG2 0x1F
50#define M98095_020_XCFG3 0x20
51#define M98095_021_XCFG4 0x21
52#define M98095_022_XCFG5 0x22
53#define M98095_023_XCFG6 0x23
54#define M98095_024_XGPIO 0x24
55#define M98095_025_XCLKCFG 0x25
56#define M98095_026_SYS_CLK 0x26
57#define M98095_027_DAI1_CLKMODE 0x27
58#define M98095_028_DAI1_CLKCFG_HI 0x28
59#define M98095_029_DAI1_CLKCFG_LO 0x29
60#define M98095_02A_DAI1_FORMAT 0x2A
61#define M98095_02B_DAI1_CLOCK 0x2B
62#define M98095_02C_DAI1_IOCFG 0x2C
63#define M98095_02D_DAI1_TDM 0x2D
64#define M98095_02E_DAI1_FILTERS 0x2E
65#define M98095_02F_DAI1_LVL1 0x2F
66#define M98095_030_DAI1_LVL2 0x30
67#define M98095_031_DAI2_CLKMODE 0x31
68#define M98095_032_DAI2_CLKCFG_HI 0x32
69#define M98095_033_DAI2_CLKCFG_LO 0x33
70#define M98095_034_DAI2_FORMAT 0x34
71#define M98095_035_DAI2_CLOCK 0x35
72#define M98095_036_DAI2_IOCFG 0x36
73#define M98095_037_DAI2_TDM 0x37
74#define M98095_038_DAI2_FILTERS 0x38
75#define M98095_039_DAI2_LVL1 0x39
76#define M98095_03A_DAI2_LVL2 0x3A
77#define M98095_03B_DAI3_CLKMODE 0x3B
78#define M98095_03C_DAI3_CLKCFG_HI 0x3C
79#define M98095_03D_DAI3_CLKCFG_LO 0x3D
80#define M98095_03E_DAI3_FORMAT 0x3E
81#define M98095_03F_DAI3_CLOCK 0x3F
82#define M98095_040_DAI3_IOCFG 0x40
83#define M98095_041_DAI3_TDM 0x41
84#define M98095_042_DAI3_FILTERS 0x42
85#define M98095_043_DAI3_LVL1 0x43
86#define M98095_044_DAI3_LVL2 0x44
87#define M98095_045_CFG_DSP 0x45
88#define M98095_046_DAC_CTRL1 0x46
89#define M98095_047_DAC_CTRL2 0x47
90#define M98095_048_MIX_DAC_LR 0x48
91#define M98095_049_MIX_DAC_M 0x49
92#define M98095_04A_MIX_ADC_LEFT 0x4A
93#define M98095_04B_MIX_ADC_RIGHT 0x4B
94#define M98095_04C_MIX_HP_LEFT 0x4C
95#define M98095_04D_MIX_HP_RIGHT 0x4D
96#define M98095_04E_CFG_HP 0x4E
97#define M98095_04F_MIX_RCV 0x4F
98#define M98095_050_MIX_SPK_LEFT 0x50
99#define M98095_051_MIX_SPK_RIGHT 0x51
100#define M98095_052_MIX_SPK_CFG 0x52
101#define M98095_053_MIX_LINEOUT1 0x53
102#define M98095_054_MIX_LINEOUT2 0x54
103#define M98095_055_MIX_LINEOUT_CFG 0x55
104#define M98095_056_LVL_SIDETONE_DAI12 0x56
105#define M98095_057_LVL_SIDETONE_DAI3 0x57
106#define M98095_058_LVL_DAI1_PLAY 0x58
107#define M98095_059_LVL_DAI1_EQ 0x59
108#define M98095_05A_LVL_DAI2_PLAY 0x5A
109#define M98095_05B_LVL_DAI2_EQ 0x5B
110#define M98095_05C_LVL_DAI3_PLAY 0x5C
111#define M98095_05D_LVL_ADC_L 0x5D
112#define M98095_05E_LVL_ADC_R 0x5E
113#define M98095_05F_LVL_MIC1 0x5F
114#define M98095_060_LVL_MIC2 0x60
115#define M98095_061_LVL_LINEIN 0x61
116#define M98095_062_LVL_LINEOUT1 0x62
117#define M98095_063_LVL_LINEOUT2 0x63
118#define M98095_064_LVL_HP_L 0x64
119#define M98095_065_LVL_HP_R 0x65
120#define M98095_066_LVL_RCV 0x66
121#define M98095_067_LVL_SPK_L 0x67
122#define M98095_068_LVL_SPK_R 0x68
123#define M98095_069_MICAGC_CFG 0x69
124#define M98095_06A_MICAGC_THRESH 0x6A
125#define M98095_06B_SPK_NOISEGATE 0x6B
126#define M98095_06C_DAI1_ALC1_TIME 0x6C
127#define M98095_06D_DAI1_ALC1_COMP 0x6D
128#define M98095_06E_DAI1_ALC1_EXPN 0x6E
129#define M98095_06F_DAI1_ALC1_GAIN 0x6F
130#define M98095_070_DAI1_ALC2_TIME 0x70
131#define M98095_071_DAI1_ALC2_COMP 0x71
132#define M98095_072_DAI1_ALC2_EXPN 0x72
133#define M98095_073_DAI1_ALC2_GAIN 0x73
134#define M98095_074_DAI1_ALC3_TIME 0x74
135#define M98095_075_DAI1_ALC3_COMP 0x75
136#define M98095_076_DAI1_ALC3_EXPN 0x76
137#define M98095_077_DAI1_ALC3_GAIN 0x77
138#define M98095_078_DAI2_ALC1_TIME 0x78
139#define M98095_079_DAI2_ALC1_COMP 0x79
140#define M98095_07A_DAI2_ALC1_EXPN 0x7A
141#define M98095_07B_DAI2_ALC1_GAIN 0x7B
142#define M98095_07C_DAI2_ALC2_TIME 0x7C
143#define M98095_07D_DAI2_ALC2_COMP 0x7D
144#define M98095_07E_DAI2_ALC2_EXPN 0x7E
145#define M98095_07F_DAI2_ALC2_GAIN 0x7F
146#define M98095_080_DAI2_ALC3_TIME 0x80
147#define M98095_081_DAI2_ALC3_COMP 0x81
148#define M98095_082_DAI2_ALC3_EXPN 0x82
149#define M98095_083_DAI2_ALC3_GAIN 0x83
150#define M98095_084_HP_NOISE_GATE 0x84
151#define M98095_085_AUX_ADC 0x85
152#define M98095_086_CFG_LINE 0x86
153#define M98095_087_CFG_MIC 0x87
154#define M98095_088_CFG_LEVEL 0x88
155#define M98095_089_JACK_DET_AUTO 0x89
156#define M98095_08A_JACK_DET_MANUAL 0x8A
157#define M98095_08B_JACK_KEYSCAN_DBC 0x8B
158#define M98095_08C_JACK_KEYSCAN_DLY 0x8C
159#define M98095_08D_JACK_KEY_THRESH 0x8D
160#define M98095_08E_JACK_DC_SLEW 0x8E
161#define M98095_08F_JACK_TEST_CFG 0x8F
162#define M98095_090_PWR_EN_IN 0x90
163#define M98095_091_PWR_EN_OUT 0x91
164#define M98095_092_PWR_EN_OUT 0x92
165#define M98095_093_BIAS_CTRL 0x93
166#define M98095_094_PWR_DAC_21 0x94
167#define M98095_095_PWR_DAC_03 0x95
168#define M98095_096_PWR_DAC_CK 0x96
169#define M98095_097_PWR_SYS 0x97
170
171#define M98095_0FF_REV_ID 0xFF
172
173#define M98095_REG_CNT (0xFF+1)
174#define M98095_REG_MAX_CACHED 0X97
175
176/* MAX98095 Registers Bit Fields */
177
178/* M98095_00F_HOST_CFG */
179 #define M98095_SEG (1<<0)
180 #define M98095_XTEN (1<<1)
181 #define M98095_MDLLEN (1<<2)
182
183/* M98095_027_DAI1_CLKMODE, M98095_031_DAI2_CLKMODE, M98095_03B_DAI3_CLKMODE */
184 #define M98095_CLKMODE_MASK 0xFF
185
186/* M98095_02A_DAI1_FORMAT, M98095_034_DAI2_FORMAT, M98095_03E_DAI3_FORMAT */
187 #define M98095_DAI_MAS (1<<7)
188 #define M98095_DAI_WCI (1<<6)
189 #define M98095_DAI_BCI (1<<5)
190 #define M98095_DAI_DLY (1<<4)
191 #define M98095_DAI_TDM (1<<2)
192 #define M98095_DAI_FSW (1<<1)
193 #define M98095_DAI_WS (1<<0)
194
195/* M98095_02B_DAI1_CLOCK, M98095_035_DAI2_CLOCK, M98095_03F_DAI3_CLOCK */
196 #define M98095_DAI_BSEL64 (1<<0)
197 #define M98095_DAI_DOSR_DIV2 (0<<5)
198 #define M98095_DAI_DOSR_DIV4 (1<<5)
199
200/* M98095_02C_DAI1_IOCFG, M98095_036_DAI2_IOCFG, M98095_040_DAI3_IOCFG */
201 #define M98095_S1NORMAL (1<<6)
202 #define M98095_S2NORMAL (2<<6)
203 #define M98095_S3NORMAL (3<<6)
204 #define M98095_SDATA (3<<0)
205
206/* M98095_02E_DAI1_FILTERS, M98095_038_DAI2_FILTERS, M98095_042_DAI3_FILTERS */
207 #define M98095_DAI_DHF (1<<3)
208
209/* M98095_045_DSP_CFG */
210 #define M98095_DSPNORMAL (5<<4)
211
212/* M98095_048_MIX_DAC_LR */
213 #define M98095_DAI1L_TO_DACR (1<<7)
214 #define M98095_DAI1R_TO_DACR (1<<6)
215 #define M98095_DAI2M_TO_DACR (1<<5)
216 #define M98095_DAI1L_TO_DACL (1<<3)
217 #define M98095_DAI1R_TO_DACL (1<<2)
218 #define M98095_DAI2M_TO_DACL (1<<1)
219 #define M98095_DAI3M_TO_DACL (1<<0)
220
221/* M98095_049_MIX_DAC_M */
222 #define M98095_DAI1L_TO_DACM (1<<3)
223 #define M98095_DAI1R_TO_DACM (1<<2)
224 #define M98095_DAI2M_TO_DACM (1<<1)
225 #define M98095_DAI3M_TO_DACM (1<<0)
226
227/* M98095_04E_MIX_HP_CFG */
228 #define M98095_HPNORMAL (3<<4)
229
230/* M98095_05F_LVL_MIC1, M98095_060_LVL_MIC2 */
231 #define M98095_MICPRE_MASK (3<<5)
232 #define M98095_MICPRE_SHIFT 5
233
234/* M98095_064_LVL_HP_L, M98095_065_LVL_HP_R */
235 #define M98095_HP_MUTE (1<<7)
236
237/* M98095_066_LVL_RCV */
238 #define M98095_REC_MUTE (1<<7)
239
240/* M98095_067_LVL_SPK_L, M98095_068_LVL_SPK_R */
241 #define M98095_SP_MUTE (1<<7)
242
243/* M98095_087_CFG_MIC */
244 #define M98095_MICSEL_MASK (3<<0)
245 #define M98095_DIGMIC_L (1<<2)
246 #define M98095_DIGMIC_R (1<<3)
247 #define M98095_DIGMIC2L (1<<4)
248 #define M98095_DIGMIC2R (1<<5)
249
250/* M98095_088_CFG_LEVEL */
251 #define M98095_VSEN (1<<6)
252 #define M98095_ZDEN (1<<5)
253 #define M98095_EQ2EN (1<<1)
254 #define M98095_EQ1EN (1<<0)
255
256/* M98095_090_PWR_EN_IN */
257 #define M98095_INEN (1<<7)
258 #define M98095_MB2EN (1<<3)
259 #define M98095_MB1EN (1<<2)
260 #define M98095_MBEN (3<<2)
261 #define M98095_ADREN (1<<1)
262 #define M98095_ADLEN (1<<0)
263
264/* M98095_091_PWR_EN_OUT */
265 #define M98095_HPLEN (1<<7)
266 #define M98095_HPREN (1<<6)
267 #define M98095_SPLEN (1<<5)
268 #define M98095_SPREN (1<<4)
269 #define M98095_RECEN (1<<3)
270 #define M98095_DALEN (1<<1)
271 #define M98095_DAREN (1<<0)
272
273/* M98095_092_PWR_EN_OUT */
274 #define M98095_SPK_FIXEDSPECTRUM (0<<4)
275 #define M98095_SPK_SPREADSPECTRUM (1<<4)
276
277/* M98095_097_PWR_SYS */
278 #define M98095_SHDNRUN (1<<7)
279 #define M98095_PERFMODE (1<<3)
280 #define M98095_HPPLYBACK (1<<2)
281 #define M98095_PWRSV8K (1<<1)
282 #define M98095_PWRSV (1<<0)
283
284#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-08 09:10:22 -0500