diff options
-rw-r--r-- | arch/sh/drivers/pci/Kconfig | 3 | ||||
-rw-r--r-- | arch/sh/drivers/pci/Makefile | 2 | ||||
-rw-r--r-- | arch/sh/drivers/pci/ops-landisk.c | 31 | ||||
-rw-r--r-- | arch/sh/drivers/pci/ops-lboxre2.c | 33 | ||||
-rw-r--r-- | arch/sh/drivers/pci/ops-rts7751r2d.c | 34 | ||||
-rw-r--r-- | arch/sh/drivers/pci/ops-sh03.c | 45 | ||||
-rw-r--r-- | arch/sh/drivers/pci/ops-snapgear.c | 49 | ||||
-rw-r--r-- | arch/sh/drivers/pci/ops-titan.c | 36 | ||||
-rw-r--r-- | arch/sh/drivers/pci/pci-sh7751.c | 135 | ||||
-rw-r--r-- | arch/sh/drivers/pci/pci-sh7751.h | 13 |
10 files changed, 76 insertions, 305 deletions
diff --git a/arch/sh/drivers/pci/Kconfig b/arch/sh/drivers/pci/Kconfig index f9fb1d1b623e..5aaee3c707b0 100644 --- a/arch/sh/drivers/pci/Kconfig +++ b/arch/sh/drivers/pci/Kconfig | |||
@@ -23,7 +23,8 @@ config PCI_NEW | |||
23 | bool | 23 | bool |
24 | depends on PCI | 24 | depends on PCI |
25 | default y if CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7780 || \ | 25 | default y if CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7780 || \ |
26 | CPU_SUBTYPE_SH7785 || CPU_SH5 | 26 | CPU_SUBTYPE_SH7785 || CPU_SH5 || \ |
27 | CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R | ||
27 | 28 | ||
28 | # This is also board-specific | 29 | # This is also board-specific |
29 | config PCI_AUTO | 30 | config PCI_AUTO |
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile index cb2190c3e36b..b8667de19ece 100644 --- a/arch/sh/drivers/pci/Makefile +++ b/arch/sh/drivers/pci/Makefile | |||
@@ -16,7 +16,7 @@ obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \ | |||
16 | pci-dreamcast.o | 16 | pci-dreamcast.o |
17 | obj-$(CONFIG_SH_SECUREEDGE5410) += ops-snapgear.o | 17 | obj-$(CONFIG_SH_SECUREEDGE5410) += ops-snapgear.o |
18 | obj-$(CONFIG_SH_RTS7751R2D) += ops-rts7751r2d.o fixups-rts7751r2d.o | 18 | obj-$(CONFIG_SH_RTS7751R2D) += ops-rts7751r2d.o fixups-rts7751r2d.o |
19 | obj-$(CONFIG_SH_SH03) += ops-sh03.o fixups-sh03.o | 19 | obj-$(CONFIG_SH_SH03) += fixups-sh03.o |
20 | obj-$(CONFIG_SH_HIGHLANDER) += fixups-r7780rp.o | 20 | obj-$(CONFIG_SH_HIGHLANDER) += fixups-r7780rp.o |
21 | obj-$(CONFIG_SH_SH7785LCR) += fixups-r7780rp.o | 21 | obj-$(CONFIG_SH_SH7785LCR) += fixups-r7780rp.o |
22 | obj-$(CONFIG_SH_SDK7780) += fixups-sdk7780.o | 22 | obj-$(CONFIG_SH_SDK7780) += fixups-sdk7780.o |
diff --git a/arch/sh/drivers/pci/ops-landisk.c b/arch/sh/drivers/pci/ops-landisk.c index 178b77828aa9..bb1a6bb5149e 100644 --- a/arch/sh/drivers/pci/ops-landisk.c +++ b/arch/sh/drivers/pci/ops-landisk.c | |||
@@ -15,37 +15,6 @@ | |||
15 | #include <linux/pci.h> | 15 | #include <linux/pci.h> |
16 | #include "pci-sh4.h" | 16 | #include "pci-sh4.h" |
17 | 17 | ||
18 | static struct resource sh7751_io_resource = { | ||
19 | .name = "SH7751 IO", | ||
20 | .start = SH7751_PCI_IO_BASE, | ||
21 | .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1, | ||
22 | .flags = IORESOURCE_IO | ||
23 | }; | ||
24 | |||
25 | static struct resource sh7751_mem_resource = { | ||
26 | .name = "SH7751 mem", | ||
27 | .start = SH7751_PCI_MEMORY_BASE, | ||
28 | .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1, | ||
29 | .flags = IORESOURCE_MEM | ||
30 | }; | ||
31 | |||
32 | struct pci_channel board_pci_channels[] = { | ||
33 | { sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0x3ff}, | ||
34 | {NULL, NULL, NULL, 0, 0}, | ||
35 | }; | ||
36 | |||
37 | static struct sh4_pci_address_map sh7751_pci_map = { | ||
38 | .window0 = { | ||
39 | .base = SH7751_CS3_BASE_ADDR, | ||
40 | .size = (64 << 20), /* 64MB */ | ||
41 | }, | ||
42 | }; | ||
43 | |||
44 | int __init pcibios_init_platform(void) | ||
45 | { | ||
46 | return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map); | ||
47 | } | ||
48 | |||
49 | int pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) | 18 | int pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) |
50 | { | 19 | { |
51 | /* | 20 | /* |
diff --git a/arch/sh/drivers/pci/ops-lboxre2.c b/arch/sh/drivers/pci/ops-lboxre2.c index 91cabd84f028..6db2c209737f 100644 --- a/arch/sh/drivers/pci/ops-lboxre2.c +++ b/arch/sh/drivers/pci/ops-lboxre2.c | |||
@@ -21,36 +21,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) | |||
21 | { | 21 | { |
22 | return lboxre2_irq_tab[slot]; | 22 | return lboxre2_irq_tab[slot]; |
23 | } | 23 | } |
24 | |||
25 | static struct resource sh7751_io_resource = { | ||
26 | .name = "SH7751_IO", | ||
27 | .start = SH7751_PCI_IO_BASE , | ||
28 | .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1, | ||
29 | .flags = IORESOURCE_IO | ||
30 | }; | ||
31 | |||
32 | static struct resource sh7751_mem_resource = { | ||
33 | .name = "SH7751_mem", | ||
34 | .start = SH7751_PCI_MEMORY_BASE, | ||
35 | .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1, | ||
36 | .flags = IORESOURCE_MEM | ||
37 | }; | ||
38 | |||
39 | extern struct pci_ops sh7751_pci_ops; | ||
40 | |||
41 | struct pci_channel board_pci_channels[] = { | ||
42 | { sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, | ||
43 | { NULL, NULL, NULL, 0, 0 }, | ||
44 | }; | ||
45 | |||
46 | static struct sh4_pci_address_map sh7751_pci_map = { | ||
47 | .window0 = { | ||
48 | .base = SH7751_CS3_BASE_ADDR, | ||
49 | .size = 0x04000000, | ||
50 | }, | ||
51 | }; | ||
52 | |||
53 | int __init pcibios_init_platform(void) | ||
54 | { | ||
55 | return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map); | ||
56 | } | ||
diff --git a/arch/sh/drivers/pci/ops-rts7751r2d.c b/arch/sh/drivers/pci/ops-rts7751r2d.c index 96b916c0d6c5..d950b8ab25f1 100644 --- a/arch/sh/drivers/pci/ops-rts7751r2d.c +++ b/arch/sh/drivers/pci/ops-rts7751r2d.c | |||
@@ -29,37 +29,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) | |||
29 | { | 29 | { |
30 | return rts7751r2d_irq_tab[slot]; | 30 | return rts7751r2d_irq_tab[slot]; |
31 | } | 31 | } |
32 | |||
33 | static struct resource sh7751_io_resource = { | ||
34 | .name = "SH7751_IO", | ||
35 | .start = 0x4000, | ||
36 | .end = SH7751_PCI_IO_SIZE - 1, | ||
37 | .flags = IORESOURCE_IO | ||
38 | }; | ||
39 | |||
40 | static struct resource sh7751_mem_resource = { | ||
41 | .name = "SH7751_mem", | ||
42 | .start = SH7751_PCI_MEMORY_BASE, | ||
43 | .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1, | ||
44 | .flags = IORESOURCE_MEM | ||
45 | }; | ||
46 | |||
47 | extern struct pci_ops sh7751_pci_ops; | ||
48 | |||
49 | struct pci_channel board_pci_channels[] = { | ||
50 | { sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, | ||
51 | { NULL, NULL, NULL, 0, 0 }, | ||
52 | }; | ||
53 | |||
54 | static struct sh4_pci_address_map sh7751_pci_map = { | ||
55 | .window0 = { | ||
56 | .base = SH7751_CS3_BASE_ADDR, | ||
57 | .size = 0x04000000, | ||
58 | }, | ||
59 | }; | ||
60 | |||
61 | int __init pcibios_init_platform(void) | ||
62 | { | ||
63 | return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map); | ||
64 | } | ||
65 | |||
diff --git a/arch/sh/drivers/pci/ops-sh03.c b/arch/sh/drivers/pci/ops-sh03.c deleted file mode 100644 index 0218135f0bb8..000000000000 --- a/arch/sh/drivers/pci/ops-sh03.c +++ /dev/null | |||
@@ -1,45 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/sh/drivers/pci/ops-sh03.c | ||
3 | * | ||
4 | * PCI initialization for the Interface CTP/PCI-SH03 board | ||
5 | */ | ||
6 | |||
7 | #include <linux/kernel.h> | ||
8 | #include <linux/types.h> | ||
9 | #include <linux/init.h> | ||
10 | #include <linux/delay.h> | ||
11 | #include <linux/pci.h> | ||
12 | #include <asm/io.h> | ||
13 | #include "pci-sh7751.h" | ||
14 | |||
15 | /* | ||
16 | * Description: This function sets up and initializes the pcic, sets | ||
17 | * up the BARS, maps the DRAM into the address space etc, etc. | ||
18 | */ | ||
19 | int __init pcibios_init_platform(void) | ||
20 | { | ||
21 | __set_io_port_base(SH7751_PCI_IO_BASE); | ||
22 | return 1; | ||
23 | } | ||
24 | |||
25 | static struct resource sh7751_io_resource = { | ||
26 | .name = "SH03 IO", | ||
27 | .start = SH7751_PCI_IO_BASE, | ||
28 | .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1, | ||
29 | .flags = IORESOURCE_IO | ||
30 | }; | ||
31 | |||
32 | static struct resource sh7751_mem_resource = { | ||
33 | .name = "SH03 mem", | ||
34 | .start = SH7751_PCI_MEMORY_BASE, | ||
35 | .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1, | ||
36 | .flags = IORESOURCE_MEM | ||
37 | }; | ||
38 | |||
39 | extern struct pci_ops sh4_pci_ops; | ||
40 | |||
41 | struct pci_channel board_pci_channels[] = { | ||
42 | { sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, | ||
43 | { NULL, NULL, NULL, 0, 0 }, | ||
44 | }; | ||
45 | |||
diff --git a/arch/sh/drivers/pci/ops-snapgear.c b/arch/sh/drivers/pci/ops-snapgear.c index b64f2b91be8e..5a39ecc1adb8 100644 --- a/arch/sh/drivers/pci/ops-snapgear.c +++ b/arch/sh/drivers/pci/ops-snapgear.c | |||
@@ -18,55 +18,6 @@ | |||
18 | #include <linux/pci.h> | 18 | #include <linux/pci.h> |
19 | #include "pci-sh4.h" | 19 | #include "pci-sh4.h" |
20 | 20 | ||
21 | #define SNAPGEAR_PCI_IO 0x4000 | ||
22 | #define SNAPGEAR_PCI_MEM 0xfd000000 | ||
23 | |||
24 | /* PCI: default LOCAL memory window sizes (seen from PCI bus) */ | ||
25 | #define SNAPGEAR_LSR0_SIZE (64*(1<<20)) //64MB | ||
26 | #define SNAPGEAR_LSR1_SIZE (64*(1<<20)) //64MB | ||
27 | |||
28 | static struct resource sh7751_io_resource = { | ||
29 | .name = "SH7751 IO", | ||
30 | .start = SNAPGEAR_PCI_IO, | ||
31 | .end = SNAPGEAR_PCI_IO + (64*1024) - 1, /* 64KiB I/O */ | ||
32 | .flags = IORESOURCE_IO, | ||
33 | }; | ||
34 | |||
35 | static struct resource sh7751_mem_resource = { | ||
36 | .name = "SH7751 mem", | ||
37 | .start = SNAPGEAR_PCI_MEM, | ||
38 | .end = SNAPGEAR_PCI_MEM + (64*1024*1024) - 1, /* 64MiB mem */ | ||
39 | .flags = IORESOURCE_MEM, | ||
40 | }; | ||
41 | |||
42 | struct pci_channel board_pci_channels[] = { | ||
43 | { sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, | ||
44 | { 0, } | ||
45 | }; | ||
46 | |||
47 | static struct sh4_pci_address_map sh7751_pci_map = { | ||
48 | .window0 = { | ||
49 | .base = SH7751_CS2_BASE_ADDR, | ||
50 | .size = SNAPGEAR_LSR0_SIZE, | ||
51 | }, | ||
52 | |||
53 | .window1 = { | ||
54 | .base = SH7751_CS2_BASE_ADDR, | ||
55 | .size = SNAPGEAR_LSR1_SIZE, | ||
56 | }, | ||
57 | }; | ||
58 | |||
59 | /* | ||
60 | * Initialize the SnapGear PCI interface | ||
61 | * Setup hardware to be Central Funtion | ||
62 | * Copy the BSR regs to the PCI interface | ||
63 | * Setup PCI windows into local RAM | ||
64 | */ | ||
65 | int __init pcibios_init_platform(void) | ||
66 | { | ||
67 | return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map); | ||
68 | } | ||
69 | |||
70 | int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) | 21 | int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) |
71 | { | 22 | { |
72 | int irq = -1; | 23 | int irq = -1; |
diff --git a/arch/sh/drivers/pci/ops-titan.c b/arch/sh/drivers/pci/ops-titan.c index e45bb62bf8ce..3a79fa8254a6 100644 --- a/arch/sh/drivers/pci/ops-titan.c +++ b/arch/sh/drivers/pci/ops-titan.c | |||
@@ -36,39 +36,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) | |||
36 | 36 | ||
37 | return irq; | 37 | return irq; |
38 | } | 38 | } |
39 | |||
40 | static struct resource sh7751_io_resource = { | ||
41 | .name = "SH7751_IO", | ||
42 | .start = SH7751_PCI_IO_BASE, | ||
43 | .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1, | ||
44 | .flags = IORESOURCE_IO | ||
45 | }; | ||
46 | |||
47 | static struct resource sh7751_mem_resource = { | ||
48 | .name = "SH7751_mem", | ||
49 | .start = SH7751_PCI_MEMORY_BASE, | ||
50 | .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1, | ||
51 | .flags = IORESOURCE_MEM | ||
52 | }; | ||
53 | |||
54 | struct pci_channel board_pci_channels[] = { | ||
55 | { sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, | ||
56 | { NULL, NULL, NULL, 0, 0 }, | ||
57 | }; | ||
58 | |||
59 | static struct sh4_pci_address_map sh7751_pci_map = { | ||
60 | .window0 = { | ||
61 | .base = SH7751_CS2_BASE_ADDR, | ||
62 | .size = SH7751_MEM_REGION_SIZE*2, /* cs2 and cs3 */ | ||
63 | }, | ||
64 | |||
65 | .window1 = { | ||
66 | .base = SH7751_CS2_BASE_ADDR, | ||
67 | .size = SH7751_MEM_REGION_SIZE*2, | ||
68 | }, | ||
69 | }; | ||
70 | |||
71 | int __init pcibios_init_platform(void) | ||
72 | { | ||
73 | return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map); | ||
74 | } | ||
diff --git a/arch/sh/drivers/pci/pci-sh7751.c b/arch/sh/drivers/pci/pci-sh7751.c index 4c08fd7f665d..c4fa0bb13976 100644 --- a/arch/sh/drivers/pci/pci-sh7751.c +++ b/arch/sh/drivers/pci/pci-sh7751.c | |||
@@ -1,78 +1,41 @@ | |||
1 | /* | 1 | /* |
2 | * Low-Level PCI Support for the SH7751 | 2 | * Low-Level PCI Support for the SH7751 |
3 | * | 3 | * |
4 | * Dustin McIntire (dustin@sensoria.com) | 4 | * Copyright (C) 2003 - 2009 Paul Mundt |
5 | * Derived from arch/i386/kernel/pci-*.c which bore the message: | 5 | * Copyright (C) 2001 Dustin McIntire |
6 | * (c) 1999--2000 Martin Mares <mj@ucw.cz> | ||
7 | * | 6 | * |
8 | * Ported to the new API by Paul Mundt <lethal@linux-sh.org> | 7 | * With cleanup by Paul van Gool <pvangool@mimotech.com>, 2003. |
9 | * With cleanup by Paul van Gool <pvangool@mimotech.com> | ||
10 | * | ||
11 | * May be copied or modified under the terms of the GNU General Public | ||
12 | * License. See linux/COPYING for more information. | ||
13 | * | 8 | * |
9 | * This file is subject to the terms and conditions of the GNU General Public | ||
10 | * License. See the file "COPYING" in the main directory of this archive | ||
11 | * for more details. | ||
14 | */ | 12 | */ |
15 | #undef DEBUG | ||
16 | |||
17 | #include <linux/init.h> | 13 | #include <linux/init.h> |
18 | #include <linux/pci.h> | 14 | #include <linux/pci.h> |
19 | #include <linux/types.h> | 15 | #include <linux/types.h> |
20 | #include <linux/errno.h> | 16 | #include <linux/errno.h> |
21 | #include <linux/delay.h> | 17 | #include <linux/io.h> |
22 | #include "pci-sh4.h" | 18 | #include "pci-sh4.h" |
23 | #include <asm/addrspace.h> | 19 | #include <asm/addrspace.h> |
24 | #include <asm/io.h> | ||
25 | |||
26 | /* | ||
27 | * Initialization. Try all known PCI access methods. Note that we support | ||
28 | * using both PCI BIOS and direct access: in such cases, we use I/O ports | ||
29 | * to access config space. | ||
30 | * | ||
31 | * Note that the platform specific initialization (BSC registers, and memory | ||
32 | * space mapping) will be called via the platform defined function | ||
33 | * pcibios_init_platform(). | ||
34 | */ | ||
35 | int __init sh7751_pci_init(struct pci_channel *chan) | ||
36 | { | ||
37 | unsigned int id; | ||
38 | int ret; | ||
39 | |||
40 | pr_debug("PCI: Starting intialization.\n"); | ||
41 | |||
42 | chan->reg_base = 0xfe200000; | ||
43 | |||
44 | /* check for SH7751/SH7751R hardware */ | ||
45 | id = pci_read_reg(chan, SH7751_PCICONF0); | ||
46 | if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) && | ||
47 | id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) { | ||
48 | pr_debug("PCI: This is not an SH7751(R) (%x)\n", id); | ||
49 | return -ENODEV; | ||
50 | } | ||
51 | |||
52 | if ((ret = sh4_pci_check_direct(chan)) != 0) | ||
53 | return ret; | ||
54 | |||
55 | return pcibios_init_platform(); | ||
56 | } | ||
57 | 20 | ||
58 | static int __init __area_sdram_check(struct pci_channel *chan, | 21 | static int __init __area_sdram_check(struct pci_channel *chan, |
59 | unsigned int area) | 22 | unsigned int area) |
60 | { | 23 | { |
61 | u32 word; | 24 | unsigned long word; |
62 | 25 | ||
63 | word = ctrl_inl(SH7751_BCR1); | 26 | word = __raw_readl(SH7751_BCR1); |
64 | /* check BCR for SDRAM in area */ | 27 | /* check BCR for SDRAM in area */ |
65 | if (((word >> area) & 1) == 0) { | 28 | if (((word >> area) & 1) == 0) { |
66 | printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n", | 29 | printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n", |
67 | area, word); | 30 | area, word); |
68 | return 0; | 31 | return 0; |
69 | } | 32 | } |
70 | pci_write_reg(chan, word, SH4_PCIBCR1); | 33 | pci_write_reg(chan, word, SH4_PCIBCR1); |
71 | 34 | ||
72 | word = (u16)ctrl_inw(SH7751_BCR2); | 35 | word = __raw_readw(SH7751_BCR2); |
73 | /* check BCR2 for 32bit SDRAM interface*/ | 36 | /* check BCR2 for 32bit SDRAM interface*/ |
74 | if (((word >> (area << 1)) & 0x3) != 0x3) { | 37 | if (((word >> (area << 1)) & 0x3) != 0x3) { |
75 | printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n", | 38 | printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n", |
76 | area, word); | 39 | area, word); |
77 | return 0; | 40 | return 0; |
78 | } | 41 | } |
@@ -81,11 +44,56 @@ static int __init __area_sdram_check(struct pci_channel *chan, | |||
81 | return 1; | 44 | return 1; |
82 | } | 45 | } |
83 | 46 | ||
84 | int __init sh7751_pcic_init(struct pci_channel *chan, | 47 | static struct resource sh7751_io_resource = { |
85 | struct sh4_pci_address_map *map) | 48 | .name = "SH7751_IO", |
49 | .start = SH7751_PCI_IO_BASE, | ||
50 | .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1, | ||
51 | .flags = IORESOURCE_IO | ||
52 | }; | ||
53 | |||
54 | static struct resource sh7751_mem_resource = { | ||
55 | .name = "SH7785_mem", | ||
56 | .start = SH7751_PCI_MEMORY_BASE, | ||
57 | .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1, | ||
58 | .flags = IORESOURCE_MEM | ||
59 | }; | ||
60 | |||
61 | static struct pci_channel sh7751_pci_controller = { | ||
62 | .pci_ops = &sh4_pci_ops, | ||
63 | .mem_resource = &sh7751_mem_resource, | ||
64 | .mem_offset = 0x00000000, | ||
65 | .io_resource = &sh7751_io_resource, | ||
66 | .io_offset = 0x00000000, | ||
67 | }; | ||
68 | |||
69 | static struct sh4_pci_address_map sh7751_pci_map = { | ||
70 | .window0 = { | ||
71 | .base = SH7751_CS3_BASE_ADDR, | ||
72 | .size = 0x04000000, | ||
73 | }, | ||
74 | }; | ||
75 | |||
76 | static int __init sh7751_pci_init(void) | ||
86 | { | 77 | { |
87 | u32 reg; | 78 | struct pci_channel *chan = &sh7751_pci_controller; |
88 | u32 word; | 79 | unsigned int id; |
80 | u32 word, reg; | ||
81 | int ret; | ||
82 | |||
83 | printk(KERN_NOTICE "PCI: Starting intialization.\n"); | ||
84 | |||
85 | chan->reg_base = 0xfe200000; | ||
86 | |||
87 | /* check for SH7751/SH7751R hardware */ | ||
88 | id = pci_read_reg(chan, SH7751_PCICONF0); | ||
89 | if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) && | ||
90 | id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) { | ||
91 | pr_debug("PCI: This is not an SH7751(R) (%x)\n", id); | ||
92 | return -ENODEV; | ||
93 | } | ||
94 | |||
95 | if ((ret = sh4_pci_check_direct(chan)) != 0) | ||
96 | return ret; | ||
89 | 97 | ||
90 | /* Set the BCR's to enable PCI access */ | 98 | /* Set the BCR's to enable PCI access */ |
91 | reg = ctrl_inl(SH7751_BCR1); | 99 | reg = ctrl_inl(SH7751_BCR1); |
@@ -112,21 +120,13 @@ int __init sh7751_pcic_init(struct pci_channel *chan, | |||
112 | 120 | ||
113 | /* Set IO and Mem windows to local address | 121 | /* Set IO and Mem windows to local address |
114 | * Make PCI and local address the same for easy 1 to 1 mapping | 122 | * Make PCI and local address the same for easy 1 to 1 mapping |
115 | * Window0 = map->window0.size @ non-cached area base = SDRAM | ||
116 | * Window1 = map->window1.size @ cached area base = SDRAM | ||
117 | */ | 123 | */ |
118 | word = map->window0.size - 1; | 124 | word = sh7751_pci_map.window0.size - 1; |
119 | pci_write_reg(chan, word, SH4_PCILSR0); | 125 | pci_write_reg(chan, word, SH4_PCILSR0); |
120 | word = map->window1.size - 1; | ||
121 | pci_write_reg(chan, word, SH4_PCILSR1); | ||
122 | /* Set the values on window 0 PCI config registers */ | 126 | /* Set the values on window 0 PCI config registers */ |
123 | word = P2SEGADDR(map->window0.base); | 127 | word = P2SEGADDR(sh7751_pci_map.window0.base); |
124 | pci_write_reg(chan, word, SH4_PCILAR0); | 128 | pci_write_reg(chan, word, SH4_PCILAR0); |
125 | pci_write_reg(chan, word, SH7751_PCICONF5); | 129 | pci_write_reg(chan, word, SH7751_PCICONF5); |
126 | /* Set the values on window 1 PCI config registers */ | ||
127 | word = PHYSADDR(map->window1.base); | ||
128 | pci_write_reg(chan, word, SH4_PCILAR1); | ||
129 | pci_write_reg(chan, word, SH7751_PCICONF6); | ||
130 | 130 | ||
131 | /* Set the local 16MB PCI memory space window to | 131 | /* Set the local 16MB PCI memory space window to |
132 | * the lowest PCI mapped address | 132 | * the lowest PCI mapped address |
@@ -144,7 +144,7 @@ int __init sh7751_pcic_init(struct pci_channel *chan, | |||
144 | /* Set PCI WCRx, BCRx's, copy from BSC locations */ | 144 | /* Set PCI WCRx, BCRx's, copy from BSC locations */ |
145 | 145 | ||
146 | /* check BCR for SDRAM in specified area */ | 146 | /* check BCR for SDRAM in specified area */ |
147 | switch (map->window0.base) { | 147 | switch (sh7751_pci_map.window0.base) { |
148 | case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(chan, 0); break; | 148 | case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(chan, 0); break; |
149 | case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(chan, 1); break; | 149 | case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(chan, 1); break; |
150 | case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(chan, 2); break; | 150 | case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(chan, 2); break; |
@@ -179,5 +179,10 @@ int __init sh7751_pcic_init(struct pci_channel *chan, | |||
179 | word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM; | 179 | word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM; |
180 | pci_write_reg(chan, word, SH4_PCICR); | 180 | pci_write_reg(chan, word, SH4_PCICR); |
181 | 181 | ||
182 | __set_io_port_base(SH7751_PCI_IO_BASE); | ||
183 | |||
184 | register_pci_controller(chan); | ||
185 | |||
182 | return 0; | 186 | return 0; |
183 | } | 187 | } |
188 | arch_initcall(sh7751_pci_init); | ||
diff --git a/arch/sh/drivers/pci/pci-sh7751.h b/arch/sh/drivers/pci/pci-sh7751.h index c390dd2f5e1a..4983a4d20355 100644 --- a/arch/sh/drivers/pci/pci-sh7751.h +++ b/arch/sh/drivers/pci/pci-sh7751.h | |||
@@ -57,7 +57,7 @@ | |||
57 | #define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */ | 57 | #define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */ |
58 | #define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */ | 58 | #define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */ |
59 | #define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */ | 59 | #define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */ |
60 | #define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */ | 60 | #define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */ |
61 | #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */ | 61 | #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */ |
62 | #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */ | 62 | #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */ |
63 | #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */ | 63 | #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */ |
@@ -72,12 +72,12 @@ | |||
72 | #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */ | 72 | #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */ |
73 | #define SH7751_PCICONF5_LAP 0x00000008 /* Prefetch Enabled */ | 73 | #define SH7751_PCICONF5_LAP 0x00000008 /* Prefetch Enabled */ |
74 | #define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */ | 74 | #define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */ |
75 | #define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */ | 75 | #define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */ |
76 | #define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */ | 76 | #define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */ |
77 | #define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */ | 77 | #define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */ |
78 | #define SH7751_PCICONF6_LAP 0x00000008 /* Prefetch Enabled */ | 78 | #define SH7751_PCICONF6_LAP 0x00000008 /* Prefetch Enabled */ |
79 | #define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */ | 79 | #define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */ |
80 | #define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */ | 80 | #define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */ |
81 | /* PCICONF7 - PCICONF10 are undefined */ | 81 | /* PCICONF7 - PCICONF10 are undefined */ |
82 | #define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */ | 82 | #define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */ |
83 | #define SH7751_PCICONF11_SSID 0xFFFF0000 /* Subsystem ID */ | 83 | #define SH7751_PCICONF11_SSID 0xFFFF0000 /* Subsystem ID */ |
@@ -126,11 +126,4 @@ | |||
126 | #define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE) | 126 | #define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE) |
127 | #define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE) | 127 | #define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE) |
128 | 128 | ||
129 | struct sh4_pci_address_map; | ||
130 | |||
131 | /* arch/sh/drivers/pci/pci-sh7751.c */ | ||
132 | int sh7751_pci_init(struct pci_channel *chan); | ||
133 | int sh7751_pcic_init(struct pci_channel *chan, | ||
134 | struct sh4_pci_address_map *map); | ||
135 | |||
136 | #endif /* _PCI_SH7751_H_ */ | 129 | #endif /* _PCI_SH7751_H_ */ |