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-rw-r--r--drivers/gpu/drm/radeon/evergreen.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h4
-rw-r--r--drivers/gpu/drm/radeon/si.c4
3 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 10ccd879df06..0de5b74f0287 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2267,6 +2267,10 @@ static void evergreen_program_watermarks(struct radeon_device *rdev,
2267 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); 2267 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
2268 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); 2268 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
2269 2269
2270 /* save values for DPM */
2271 radeon_crtc->line_time = line_time;
2272 radeon_crtc->wm_high = latency_watermark_a;
2273 radeon_crtc->wm_low = latency_watermark_b;
2270} 2274}
2271 2275
2272/** 2276/**
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 7cc13ba8cdc7..0a4b50fa9c59 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -331,6 +331,10 @@ struct radeon_crtc {
331 u32 pll_flags; 331 u32 pll_flags;
332 struct drm_encoder *encoder; 332 struct drm_encoder *encoder;
333 struct drm_connector *connector; 333 struct drm_connector *connector;
334 /* for dpm */
335 u32 line_time;
336 u32 wm_low;
337 u32 wm_high;
334}; 338};
335 339
336struct radeon_encoder_primary_dac { 340struct radeon_encoder_primary_dac {
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 6c5cbe0e80b9..660781b3d6d9 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2166,6 +2166,10 @@ static void dce6_program_watermarks(struct radeon_device *rdev,
2166 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); 2166 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
2167 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); 2167 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
2168 2168
2169 /* save values for DPM */
2170 radeon_crtc->line_time = line_time;
2171 radeon_crtc->wm_high = latency_watermark_a;
2172 radeon_crtc->wm_low = latency_watermark_b;
2169} 2173}
2170 2174
2171void dce6_bandwidth_update(struct radeon_device *rdev) 2175void dce6_bandwidth_update(struct radeon_device *rdev)