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-rw-r--r--arch/mips/alchemy/Kconfig10
-rw-r--r--arch/mips/alchemy/Platform9
-rw-r--r--arch/mips/alchemy/devboards/Makefile1
-rw-r--r--arch/mips/alchemy/devboards/db1200.c245
-rw-r--r--arch/mips/alchemy/devboards/pb1200.c471
-rw-r--r--arch/mips/configs/pb1200_defconfig170
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1200.h11
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1200.h139
8 files changed, 238 insertions, 818 deletions
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index a1b995ff517b..e1b3be787f80 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -42,7 +42,7 @@ config MIPS_DB1100
42 select SYS_HAS_EARLY_PRINTK 42 select SYS_HAS_EARLY_PRINTK
43 43
44config MIPS_DB1200 44config MIPS_DB1200
45 bool "Alchemy DB1200 board" 45 bool "Alchemy DB1200/PB1200 board"
46 select ALCHEMY_GPIOINT_AU1000 46 select ALCHEMY_GPIOINT_AU1000
47 select DMA_COHERENT 47 select DMA_COHERENT
48 select MIPS_DISABLE_OBSOLETE_IDE 48 select MIPS_DISABLE_OBSOLETE_IDE
@@ -85,14 +85,6 @@ config MIPS_PB1100
85 select SYS_SUPPORTS_LITTLE_ENDIAN 85 select SYS_SUPPORTS_LITTLE_ENDIAN
86 select SYS_HAS_EARLY_PRINTK 86 select SYS_HAS_EARLY_PRINTK
87 87
88config MIPS_PB1200
89 bool "Alchemy PB1200 board"
90 select ALCHEMY_GPIOINT_AU1000
91 select DMA_NONCOHERENT
92 select MIPS_DISABLE_OBSOLETE_IDE
93 select SYS_SUPPORTS_LITTLE_ENDIAN
94 select SYS_HAS_EARLY_PRINTK
95
96config MIPS_PB1500 88config MIPS_PB1500
97 bool "Alchemy PB1500 board" 89 bool "Alchemy PB1500 board"
98 select ALCHEMY_GPIOINT_AU1000 90 select ALCHEMY_GPIOINT_AU1000
diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform
index c032f5b5f889..bbdcc150d04d 100644
--- a/arch/mips/alchemy/Platform
+++ b/arch/mips/alchemy/Platform
@@ -26,13 +26,6 @@ cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
26load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 26load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000
27 27
28# 28#
29# AMD Alchemy Pb1200 eval board
30#
31platform-$(CONFIG_MIPS_PB1200) += alchemy/devboards/
32cflags-$(CONFIG_MIPS_PB1200) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
33load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000
34
35#
36# AMD Alchemy Db1000 eval board 29# AMD Alchemy Db1000 eval board
37# 30#
38platform-$(CONFIG_MIPS_DB1000) += alchemy/devboards/ 31platform-$(CONFIG_MIPS_DB1000) += alchemy/devboards/
@@ -61,7 +54,7 @@ cflags-$(CONFIG_MIPS_DB1550) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
61load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000 54load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000
62 55
63# 56#
64# AMD Alchemy Db1200 eval board 57# AMD Alchemy Db1200/Pb1200 eval boards
65# 58#
66platform-$(CONFIG_MIPS_DB1200) += alchemy/devboards/ 59platform-$(CONFIG_MIPS_DB1200) += alchemy/devboards/
67cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 60cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index f5628523c694..2fbf17909200 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -5,7 +5,6 @@
5obj-y += prom.o bcsr.o platform.o 5obj-y += prom.o bcsr.o platform.o
6obj-$(CONFIG_PM) += pm.o 6obj-$(CONFIG_PM) += pm.o
7obj-$(CONFIG_MIPS_PB1100) += pb1100.o 7obj-$(CONFIG_MIPS_PB1100) += pb1100.o
8obj-$(CONFIG_MIPS_PB1200) += pb1200.o
9obj-$(CONFIG_MIPS_PB1500) += pb1500.o 8obj-$(CONFIG_MIPS_PB1500) += pb1500.o
10obj-$(CONFIG_MIPS_PB1550) += pb1550.o 9obj-$(CONFIG_MIPS_PB1550) += pb1550.o
11obj-$(CONFIG_MIPS_DB1000) += db1x00.o 10obj-$(CONFIG_MIPS_DB1000) += db1x00.o
diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c
index e2cc5f921538..ec481f33aecc 100644
--- a/arch/mips/alchemy/devboards/db1200.c
+++ b/arch/mips/alchemy/devboards/db1200.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * DBAu1200 board platform device registration 2 * DBAu1200/PBAu1200 board platform device registration
3 * 3 *
4 * Copyright (C) 2008-2011 Manuel Lauss 4 * Copyright (C) 2008-2011 Manuel Lauss
5 * 5 *
@@ -44,10 +44,41 @@
44 44
45#include "platform.h" 45#include "platform.h"
46 46
47static const char *board_type_str(void)
48{
49 switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
50 case BCSR_WHOAMI_PB1200_DDR1:
51 case BCSR_WHOAMI_PB1200_DDR2:
52 return "PB1200";
53 case BCSR_WHOAMI_DB1200:
54 return "DB1200";
55 default:
56 return "(unknown)";
57 }
58}
47 59
48const char *get_system_type(void) 60const char *get_system_type(void)
49{ 61{
50 return "DB1200"; 62 return board_type_str();
63}
64
65static int __init detect_board(void)
66{
67 int bid;
68
69 /* try the PB1200 first */
70 bcsr_init(PB1200_BCSR_PHYS_ADDR,
71 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
72 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
73 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
74 (bid == BCSR_WHOAMI_PB1200_DDR2))
75 return 0;
76
77 /* okay, try the DB1200 then */
78 bcsr_init(DB1200_BCSR_PHYS_ADDR,
79 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
80 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
81 return bid == BCSR_WHOAMI_DB1200 ? 0 : 1;
51} 82}
52 83
53void __init board_setup(void) 84void __init board_setup(void)
@@ -55,12 +86,14 @@ void __init board_setup(void)
55 unsigned long freq0, clksrc, div, pfc; 86 unsigned long freq0, clksrc, div, pfc;
56 unsigned short whoami; 87 unsigned short whoami;
57 88
58 bcsr_init(DB1200_BCSR_PHYS_ADDR, 89 if (detect_board()) {
59 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); 90 printk(KERN_ERR "NOT running on a DB1200/PB1200 board!\n");
91 return;
92 }
60 93
61 whoami = bcsr_read(BCSR_WHOAMI); 94 whoami = bcsr_read(BCSR_WHOAMI);
62 printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d" 95 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
63 " Board-ID %d Daughtercard ID %d\n", 96 " Board-ID %d Daughtercard ID %d\n", board_type_str(),
64 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); 97 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
65 98
66 /* SMBus/SPI on PSC0, Audio on PSC1 */ 99 /* SMBus/SPI on PSC0, Audio on PSC1 */
@@ -96,7 +129,7 @@ void __init board_setup(void)
96 129
97static struct mtd_partition db1200_spiflash_parts[] = { 130static struct mtd_partition db1200_spiflash_parts[] = {
98 { 131 {
99 .name = "DB1200 SPI flash", 132 .name = "spi_flash",
100 .offset = 0, 133 .offset = 0,
101 .size = MTDPART_SIZ_FULL, 134 .size = MTDPART_SIZ_FULL,
102 }, 135 },
@@ -376,12 +409,109 @@ static struct led_classdev db1200_mmc_led = {
376 .brightness_set = db1200_mmcled_set, 409 .brightness_set = db1200_mmcled_set,
377}; 410};
378 411
379static struct au1xmmc_platform_data db1200mmc_platdata = { 412/* -- */
380 .cd_setup = db1200_mmc_cd_setup, 413
381 .set_power = db1200_mmc_set_power, 414static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr)
382 .card_inserted = db1200_mmc_card_inserted, 415{
383 .card_readonly = db1200_mmc_card_readonly, 416 void(*mmc_cd)(struct mmc_host *, unsigned long);
384 .led = &db1200_mmc_led, 417
418 if (irq == PB1200_SD1_INSERT_INT) {
419 disable_irq_nosync(PB1200_SD1_INSERT_INT);
420 enable_irq(PB1200_SD1_EJECT_INT);
421 } else {
422 disable_irq_nosync(PB1200_SD1_EJECT_INT);
423 enable_irq(PB1200_SD1_INSERT_INT);
424 }
425
426 /* link against CONFIG_MMC=m */
427 mmc_cd = symbol_get(mmc_detect_change);
428 if (mmc_cd) {
429 mmc_cd(ptr, msecs_to_jiffies(500));
430 symbol_put(mmc_detect_change);
431 }
432
433 return IRQ_HANDLED;
434}
435
436static int pb1200_mmc1_cd_setup(void *mmc_host, int en)
437{
438 int ret;
439
440 if (en) {
441 ret = request_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 0,
442 "sd1_insert", mmc_host);
443 if (ret)
444 goto out;
445
446 ret = request_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 0,
447 "sd1_eject", mmc_host);
448 if (ret) {
449 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
450 goto out;
451 }
452
453 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT)
454 enable_irq(PB1200_SD1_EJECT_INT);
455 else
456 enable_irq(PB1200_SD1_INSERT_INT);
457
458 } else {
459 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
460 free_irq(PB1200_SD1_EJECT_INT, mmc_host);
461 }
462 ret = 0;
463out:
464 return ret;
465}
466
467static void pb1200_mmc1led_set(struct led_classdev *led,
468 enum led_brightness brightness)
469{
470 if (brightness != LED_OFF)
471 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
472 else
473 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
474}
475
476static struct led_classdev pb1200_mmc1_led = {
477 .brightness_set = pb1200_mmc1led_set,
478};
479
480static void pb1200_mmc1_set_power(void *mmc_host, int state)
481{
482 if (state) {
483 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
484 msleep(400); /* stabilization time */
485 } else
486 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
487}
488
489static int pb1200_mmc1_card_readonly(void *mmc_host)
490{
491 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
492}
493
494static int pb1200_mmc1_card_inserted(void *mmc_host)
495{
496 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
497}
498
499
500static struct au1xmmc_platform_data db1200_mmc_platdata[2] = {
501 [0] = {
502 .cd_setup = db1200_mmc_cd_setup,
503 .set_power = db1200_mmc_set_power,
504 .card_inserted = db1200_mmc_card_inserted,
505 .card_readonly = db1200_mmc_card_readonly,
506 .led = &db1200_mmc_led,
507 },
508 [1] = {
509 .cd_setup = pb1200_mmc1_cd_setup,
510 .set_power = pb1200_mmc1_set_power,
511 .card_inserted = pb1200_mmc1_card_inserted,
512 .card_readonly = pb1200_mmc1_card_readonly,
513 .led = &pb1200_mmc1_led,
514 },
385}; 515};
386 516
387static struct resource au1200_mmc0_resources[] = { 517static struct resource au1200_mmc0_resources[] = {
@@ -415,12 +545,47 @@ static struct platform_device db1200_mmc0_dev = {
415 .dev = { 545 .dev = {
416 .dma_mask = &au1xxx_mmc_dmamask, 546 .dma_mask = &au1xxx_mmc_dmamask,
417 .coherent_dma_mask = DMA_BIT_MASK(32), 547 .coherent_dma_mask = DMA_BIT_MASK(32),
418 .platform_data = &db1200mmc_platdata, 548 .platform_data = &db1200_mmc_platdata[0],
419 }, 549 },
420 .num_resources = ARRAY_SIZE(au1200_mmc0_resources), 550 .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
421 .resource = au1200_mmc0_resources, 551 .resource = au1200_mmc0_resources,
422}; 552};
423 553
554static struct resource au1200_mmc1_res[] = {
555 [0] = {
556 .start = AU1100_SD1_PHYS_ADDR,
557 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
558 .flags = IORESOURCE_MEM,
559 },
560 [1] = {
561 .start = AU1200_SD_INT,
562 .end = AU1200_SD_INT,
563 .flags = IORESOURCE_IRQ,
564 },
565 [2] = {
566 .start = AU1200_DSCR_CMD0_SDMS_TX1,
567 .end = AU1200_DSCR_CMD0_SDMS_TX1,
568 .flags = IORESOURCE_DMA,
569 },
570 [3] = {
571 .start = AU1200_DSCR_CMD0_SDMS_RX1,
572 .end = AU1200_DSCR_CMD0_SDMS_RX1,
573 .flags = IORESOURCE_DMA,
574 }
575};
576
577static struct platform_device pb1200_mmc1_dev = {
578 .name = "au1xxx-mmc",
579 .id = 1,
580 .dev = {
581 .dma_mask = &au1xxx_mmc_dmamask,
582 .coherent_dma_mask = DMA_BIT_MASK(32),
583 .platform_data = &db1200_mmc_platdata[1],
584 },
585 .num_resources = ARRAY_SIZE(au1200_mmc1_res),
586 .resource = au1200_mmc1_res,
587};
588
424/**********************************************************************/ 589/**********************************************************************/
425 590
426static int db1200fb_panel_index(void) 591static int db1200fb_panel_index(void)
@@ -598,14 +763,50 @@ static struct platform_device *db1200_devs[] __initdata = {
598 &db1200_sound_dev, 763 &db1200_sound_dev,
599}; 764};
600 765
766static struct platform_device *pb1200_devs[] __initdata = {
767 &pb1200_mmc1_dev,
768};
769
770/* Some peripheral base addresses differ on the PB1200 */
771static int __init pb1200_res_fixup(void)
772{
773 /* CPLD Revs earlier than 4 cause problems */
774 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
775 printk(KERN_ERR "WARNING!!!\n");
776 printk(KERN_ERR "WARNING!!!\n");
777 printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n");
778 printk(KERN_ERR "the board updated to latest revisions.\n");
779 printk(KERN_ERR "This software will not work reliably\n");
780 printk(KERN_ERR "on anything older than CPLD rev 4.!\n");
781 printk(KERN_ERR "WARNING!!!\n");
782 printk(KERN_ERR "WARNING!!!\n");
783 return 1;
784 }
785
786 db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;
787 db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff;
788 db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;
789 db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;
790 db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;
791 db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff;
792 return 0;
793}
794
601static int __init db1200_dev_init(void) 795static int __init db1200_dev_init(void)
602{ 796{
603 unsigned long pfc; 797 unsigned long pfc;
604 unsigned short sw; 798 unsigned short sw;
605 int swapped; 799 int swapped, bid;
800
801 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
802 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
803 (bid == BCSR_WHOAMI_PB1200_DDR2)) {
804 if (pb1200_res_fixup())
805 return -ENODEV;
806 }
606 807
607 /* GPIO7 is low-level triggered CPLD cascade */ 808 /* GPIO7 is low-level triggered CPLD cascade */
608 irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); 809 irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
609 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); 810 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
610 811
611 /* insert/eject pairs: one of both is always screaming. To avoid 812 /* insert/eject pairs: one of both is always screaming. To avoid
@@ -626,6 +827,7 @@ static int __init db1200_dev_init(void)
626 827
627 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI) 828 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI)
628 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S) 829 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
830 * or S12 on the PB1200.
629 */ 831 */
630 832
631 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however 833 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however
@@ -640,7 +842,7 @@ static int __init db1200_dev_init(void)
640 gpio_request(215, "otg-vbus"); 842 gpio_request(215, "otg-vbus");
641 gpio_direction_output(215, 1); 843 gpio_direction_output(215, 1);
642 844
643 printk(KERN_INFO "DB1200 device configuration:\n"); 845 printk(KERN_INFO "%s device configuration:\n", board_type_str());
644 846
645 sw = bcsr_read(BCSR_SWITCHES); 847 sw = bcsr_read(BCSR_SWITCHES);
646 if (sw & BCSR_SWITCHES_DIP_8) { 848 if (sw & BCSR_SWITCHES_DIP_8) {
@@ -707,6 +909,13 @@ static int __init db1200_dev_init(void)
707 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; 909 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
708 db1x_register_norflash(64 << 20, 2, swapped); 910 db1x_register_norflash(64 << 20, 2, swapped);
709 911
710 return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); 912 platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
913
914 /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */
915 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
916 (bid == BCSR_WHOAMI_PB1200_DDR2))
917 platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs));
918
919 return 0;
711} 920}
712device_initcall(db1200_dev_init); 921device_initcall(db1200_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1200.c b/arch/mips/alchemy/devboards/pb1200.c
deleted file mode 100644
index a2676c95053b..000000000000
--- a/arch/mips/alchemy/devboards/pb1200.c
+++ /dev/null
@@ -1,471 +0,0 @@
1/*
2 * Pb1200/DBAu1200 board platform device registration
3 *
4 * Copyright (C) 2008 MontaVista Software Inc. <source@mvista.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/dma-mapping.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/leds.h>
25#include <linux/platform_device.h>
26#include <linux/smc91x.h>
27#include <asm/mach-au1x00/au1000.h>
28#include <asm/mach-au1x00/au1100_mmc.h>
29#include <asm/mach-au1x00/au1200fb.h>
30#include <asm/mach-au1x00/au1xxx_dbdma.h>
31#include <asm/mach-db1x00/bcsr.h>
32#include <asm/mach-pb1x00/pb1200.h>
33#include <prom.h>
34#include "platform.h"
35
36
37const char *get_system_type(void)
38{
39 return "PB1200";
40}
41
42void __init board_setup(void)
43{
44 printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
45 bcsr_init(PB1200_BCSR_PHYS_ADDR,
46 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
47
48#if 0
49 {
50 u32 pin_func;
51
52 /*
53 * Enable PSC1 SYNC for AC97. Normaly done in audio driver,
54 * but it is board specific code, so put it here.
55 */
56 pin_func = au_readl(SYS_PINFUNC);
57 au_sync();
58 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
59 au_writel(pin_func, SYS_PINFUNC);
60
61 au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */
62 au_sync();
63 }
64#endif
65
66#if defined(CONFIG_I2C_AU1550)
67 {
68 u32 freq0, clksrc;
69 u32 pin_func;
70
71 /* Select SMBus in CPLD */
72 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
73
74 pin_func = au_readl(SYS_PINFUNC);
75 au_sync();
76 pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
77 /* Set GPIOs correctly */
78 pin_func |= 2 << 17;
79 au_writel(pin_func, SYS_PINFUNC);
80 au_sync();
81
82 /* The I2C driver depends on 50 MHz clock */
83 freq0 = au_readl(SYS_FREQCTRL0);
84 au_sync();
85 freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
86 freq0 |= 3 << SYS_FC_FRDIV1_BIT;
87 /* 396 MHz / (3 + 1) * 2 == 49.5 MHz */
88 au_writel(freq0, SYS_FREQCTRL0);
89 au_sync();
90 freq0 |= SYS_FC_FE1;
91 au_writel(freq0, SYS_FREQCTRL0);
92 au_sync();
93
94 clksrc = au_readl(SYS_CLKSRC);
95 au_sync();
96 clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK);
97 /* Bit 22 is EXTCLK0 for PSC0 */
98 clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT;
99 au_writel(clksrc, SYS_CLKSRC);
100 au_sync();
101 }
102#endif
103
104 /*
105 * The Pb1200 development board uses external MUX for PSC0 to
106 * support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI
107 */
108#ifdef CONFIG_I2C_AU1550
109 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
110#endif
111 au_sync();
112}
113
114/******************************************************************************/
115
116static int mmc_activity;
117
118static void pb1200mmc0_set_power(void *mmc_host, int state)
119{
120 if (state)
121 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
122 else
123 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
124
125 msleep(1);
126}
127
128static int pb1200mmc0_card_readonly(void *mmc_host)
129{
130 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
131}
132
133static int pb1200mmc0_card_inserted(void *mmc_host)
134{
135 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
136}
137
138static void pb1200_mmcled_set(struct led_classdev *led,
139 enum led_brightness brightness)
140{
141 if (brightness != LED_OFF) {
142 if (++mmc_activity == 1)
143 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
144 } else {
145 if (--mmc_activity == 0)
146 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
147 }
148}
149
150static struct led_classdev pb1200mmc_led = {
151 .brightness_set = pb1200_mmcled_set,
152};
153
154static void pb1200mmc1_set_power(void *mmc_host, int state)
155{
156 if (state)
157 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
158 else
159 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
160
161 msleep(1);
162}
163
164static int pb1200mmc1_card_readonly(void *mmc_host)
165{
166 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
167}
168
169static int pb1200mmc1_card_inserted(void *mmc_host)
170{
171 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
172}
173
174static struct au1xmmc_platform_data pb1200mmc_platdata[2] = {
175 [0] = {
176 .set_power = pb1200mmc0_set_power,
177 .card_inserted = pb1200mmc0_card_inserted,
178 .card_readonly = pb1200mmc0_card_readonly,
179 .cd_setup = NULL, /* use poll-timer in driver */
180 .led = &pb1200mmc_led,
181 },
182 [1] = {
183 .set_power = pb1200mmc1_set_power,
184 .card_inserted = pb1200mmc1_card_inserted,
185 .card_readonly = pb1200mmc1_card_readonly,
186 .cd_setup = NULL, /* use poll-timer in driver */
187 .led = &pb1200mmc_led,
188 },
189};
190
191static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
192
193static struct resource au1200_mmc0_res[] = {
194 [0] = {
195 .start = AU1100_SD0_PHYS_ADDR,
196 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
197 .flags = IORESOURCE_MEM,
198 },
199 [1] = {
200 .start = AU1200_SD_INT,
201 .end = AU1200_SD_INT,
202 .flags = IORESOURCE_IRQ,
203 },
204 [2] = {
205 .start = AU1200_DSCR_CMD0_SDMS_TX0,
206 .end = AU1200_DSCR_CMD0_SDMS_TX0,
207 .flags = IORESOURCE_DMA,
208 },
209 [3] = {
210 .start = AU1200_DSCR_CMD0_SDMS_RX0,
211 .end = AU1200_DSCR_CMD0_SDMS_RX0,
212 .flags = IORESOURCE_DMA,
213 }
214};
215
216static struct platform_device pb1200_mmc0_dev = {
217 .name = "au1xxx-mmc",
218 .id = 0,
219 .dev = {
220 .dma_mask = &au1xxx_mmc_dmamask,
221 .coherent_dma_mask = DMA_BIT_MASK(32),
222 .platform_data = &pb1200mmc_platdata[0],
223 },
224 .num_resources = ARRAY_SIZE(au1200_mmc0_res),
225 .resource = au1200_mmc0_res,
226};
227
228static struct resource au1200_mmc1_res[] = {
229 [0] = {
230 .start = AU1100_SD1_PHYS_ADDR,
231 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
232 .flags = IORESOURCE_MEM,
233 },
234 [1] = {
235 .start = AU1200_SD_INT,
236 .end = AU1200_SD_INT,
237 .flags = IORESOURCE_IRQ,
238 },
239 [2] = {
240 .start = AU1200_DSCR_CMD0_SDMS_TX1,
241 .end = AU1200_DSCR_CMD0_SDMS_TX1,
242 .flags = IORESOURCE_DMA,
243 },
244 [3] = {
245 .start = AU1200_DSCR_CMD0_SDMS_RX1,
246 .end = AU1200_DSCR_CMD0_SDMS_RX1,
247 .flags = IORESOURCE_DMA,
248 }
249};
250
251static struct platform_device pb1200_mmc1_dev = {
252 .name = "au1xxx-mmc",
253 .id = 1,
254 .dev = {
255 .dma_mask = &au1xxx_mmc_dmamask,
256 .coherent_dma_mask = DMA_BIT_MASK(32),
257 .platform_data = &pb1200mmc_platdata[1],
258 },
259 .num_resources = ARRAY_SIZE(au1200_mmc1_res),
260 .resource = au1200_mmc1_res,
261};
262
263
264static struct resource ide_resources[] = {
265 [0] = {
266 .start = IDE_PHYS_ADDR,
267 .end = IDE_PHYS_ADDR + IDE_PHYS_LEN - 1,
268 .flags = IORESOURCE_MEM
269 },
270 [1] = {
271 .start = IDE_INT,
272 .end = IDE_INT,
273 .flags = IORESOURCE_IRQ
274 },
275 [2] = {
276 .start = AU1200_DSCR_CMD0_DMA_REQ1,
277 .end = AU1200_DSCR_CMD0_DMA_REQ1,
278 .flags = IORESOURCE_DMA,
279 },
280};
281
282static u64 au1200_ide_dmamask = DMA_BIT_MASK(32);
283
284static struct platform_device ide_device = {
285 .name = "au1200-ide",
286 .id = 0,
287 .dev = {
288 .dma_mask = &au1200_ide_dmamask,
289 .coherent_dma_mask = DMA_BIT_MASK(32),
290 },
291 .num_resources = ARRAY_SIZE(ide_resources),
292 .resource = ide_resources
293};
294
295static struct smc91x_platdata smc_data = {
296 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
297 .leda = RPC_LED_100_10,
298 .ledb = RPC_LED_TX_RX,
299};
300
301static struct resource smc91c111_resources[] = {
302 [0] = {
303 .name = "smc91x-regs",
304 .start = SMC91C111_PHYS_ADDR,
305 .end = SMC91C111_PHYS_ADDR + 0xf,
306 .flags = IORESOURCE_MEM
307 },
308 [1] = {
309 .start = SMC91C111_INT,
310 .end = SMC91C111_INT,
311 .flags = IORESOURCE_IRQ
312 },
313};
314
315static struct platform_device smc91c111_device = {
316 .dev = {
317 .platform_data = &smc_data,
318 },
319 .name = "smc91x",
320 .id = -1,
321 .num_resources = ARRAY_SIZE(smc91c111_resources),
322 .resource = smc91c111_resources
323};
324
325static struct resource au1200_psc0_res[] = {
326 [0] = {
327 .start = AU1550_PSC0_PHYS_ADDR,
328 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
329 .flags = IORESOURCE_MEM,
330 },
331 [1] = {
332 .start = AU1200_PSC0_INT,
333 .end = AU1200_PSC0_INT,
334 .flags = IORESOURCE_IRQ,
335 },
336 [2] = {
337 .start = AU1200_DSCR_CMD0_PSC0_TX,
338 .end = AU1200_DSCR_CMD0_PSC0_TX,
339 .flags = IORESOURCE_DMA,
340 },
341 [3] = {
342 .start = AU1200_DSCR_CMD0_PSC0_RX,
343 .end = AU1200_DSCR_CMD0_PSC0_RX,
344 .flags = IORESOURCE_DMA,
345 },
346};
347
348static struct platform_device pb1200_i2c_dev = {
349 .name = "au1xpsc_smbus",
350 .id = 0, /* bus number */
351 .num_resources = ARRAY_SIZE(au1200_psc0_res),
352 .resource = au1200_psc0_res,
353};
354
355static int pb1200fb_panel_index(void)
356{
357 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
358}
359
360static int pb1200fb_panel_init(void)
361{
362 /* Apply power */
363 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
364 BCSR_BOARD_LCDBL);
365 return 0;
366}
367
368static int pb1200fb_panel_shutdown(void)
369{
370 /* Remove power */
371 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
372 BCSR_BOARD_LCDBL, 0);
373 return 0;
374}
375
376static struct au1200fb_platdata pb1200fb_pd = {
377 .panel_index = pb1200fb_panel_index,
378 .panel_init = pb1200fb_panel_init,
379 .panel_shutdown = pb1200fb_panel_shutdown,
380};
381
382static struct resource au1200_lcd_res[] = {
383 [0] = {
384 .start = AU1200_LCD_PHYS_ADDR,
385 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
386 .flags = IORESOURCE_MEM,
387 },
388 [1] = {
389 .start = AU1200_LCD_INT,
390 .end = AU1200_LCD_INT,
391 .flags = IORESOURCE_IRQ,
392 }
393};
394
395static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
396
397static struct platform_device pb1200_lcd_dev = {
398 .name = "au1200-lcd",
399 .id = 0,
400 .dev = {
401 .dma_mask = &au1200_lcd_dmamask,
402 .coherent_dma_mask = DMA_BIT_MASK(32),
403 .platform_data = &pb1200fb_pd,
404 },
405 .num_resources = ARRAY_SIZE(au1200_lcd_res),
406 .resource = au1200_lcd_res,
407};
408
409static struct platform_device *board_platform_devices[] __initdata = {
410 &ide_device,
411 &smc91c111_device,
412 &pb1200_i2c_dev,
413 &pb1200_mmc0_dev,
414 &pb1200_mmc1_dev,
415 &pb1200_lcd_dev,
416};
417
418static int __init board_register_devices(void)
419{
420 int swapped;
421
422 /* We have a problem with CPLD rev 3. */
423 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
424 printk(KERN_ERR "WARNING!!!\n");
425 printk(KERN_ERR "WARNING!!!\n");
426 printk(KERN_ERR "WARNING!!!\n");
427 printk(KERN_ERR "WARNING!!!\n");
428 printk(KERN_ERR "WARNING!!!\n");
429 printk(KERN_ERR "WARNING!!!\n");
430 printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n");
431 printk(KERN_ERR "updated to latest revision. This software will\n");
432 printk(KERN_ERR "not work on anything less than CPLD rev 4.\n");
433 printk(KERN_ERR "WARNING!!!\n");
434 printk(KERN_ERR "WARNING!!!\n");
435 printk(KERN_ERR "WARNING!!!\n");
436 printk(KERN_ERR "WARNING!!!\n");
437 printk(KERN_ERR "WARNING!!!\n");
438 printk(KERN_ERR "WARNING!!!\n");
439 panic("Game over. Your score is 0.");
440 }
441
442 irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
443 bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT);
444
445 db1x_register_pcmcia_socket(
446 AU1000_PCMCIA_ATTR_PHYS_ADDR,
447 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
448 AU1000_PCMCIA_MEM_PHYS_ADDR,
449 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
450 AU1000_PCMCIA_IO_PHYS_ADDR,
451 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
452 PB1200_PC0_INT, PB1200_PC0_INSERT_INT,
453 /*PB1200_PC0_STSCHG_INT*/0, PB1200_PC0_EJECT_INT, 0);
454
455 db1x_register_pcmcia_socket(
456 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
457 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
458 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
459 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
460 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
461 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
462 PB1200_PC1_INT, PB1200_PC1_INSERT_INT,
463 /*PB1200_PC1_STSCHG_INT*/0, PB1200_PC1_EJECT_INT, 1);
464
465 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
466 db1x_register_norflash(128 * 1024 * 1024, 2, swapped);
467
468 return platform_add_devices(board_platform_devices,
469 ARRAY_SIZE(board_platform_devices));
470}
471device_initcall(board_register_devices);
diff --git a/arch/mips/configs/pb1200_defconfig b/arch/mips/configs/pb1200_defconfig
deleted file mode 100644
index dcbe2704e5ed..000000000000
--- a/arch/mips/configs/pb1200_defconfig
+++ /dev/null
@@ -1,170 +0,0 @@
1CONFIG_MIPS_ALCHEMY=y
2CONFIG_MIPS_PB1200=y
3CONFIG_KSM=y
4CONFIG_NO_HZ=y
5CONFIG_HIGH_RES_TIMERS=y
6CONFIG_HZ_100=y
7# CONFIG_SECCOMP is not set
8CONFIG_EXPERIMENTAL=y
9CONFIG_LOCALVERSION="-pb1200"
10CONFIG_KERNEL_LZMA=y
11CONFIG_SYSVIPC=y
12CONFIG_POSIX_MQUEUE=y
13CONFIG_TINY_RCU=y
14CONFIG_LOG_BUF_SHIFT=14
15CONFIG_EXPERT=y
16# CONFIG_SYSCTL_SYSCALL is not set
17# CONFIG_KALLSYMS is not set
18# CONFIG_PCSPKR_PLATFORM is not set
19# CONFIG_VM_EVENT_COUNTERS is not set
20# CONFIG_COMPAT_BRK is not set
21CONFIG_SLAB=y
22CONFIG_MODULES=y
23CONFIG_MODULE_UNLOAD=y
24# CONFIG_LBDAF is not set
25# CONFIG_BLK_DEV_BSG is not set
26# CONFIG_IOSCHED_DEADLINE is not set
27# CONFIG_IOSCHED_CFQ is not set
28CONFIG_PCCARD=y
29CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
30CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
31CONFIG_BINFMT_MISC=y
32CONFIG_NET=y
33CONFIG_PACKET=y
34CONFIG_UNIX=y
35CONFIG_INET=y
36CONFIG_IP_MULTICAST=y
37CONFIG_IP_PNP=y
38# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
39# CONFIG_INET_XFRM_MODE_TUNNEL is not set
40# CONFIG_INET_XFRM_MODE_BEET is not set
41# CONFIG_INET_DIAG is not set
42# CONFIG_IPV6 is not set
43# CONFIG_WIRELESS is not set
44CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
45CONFIG_MTD=y
46CONFIG_MTD_PARTITIONS=y
47CONFIG_MTD_CMDLINE_PARTS=y
48CONFIG_MTD_CHAR=y
49CONFIG_MTD_BLOCK=y
50CONFIG_MTD_CFI=y
51CONFIG_MTD_CFI_AMDSTD=y
52CONFIG_MTD_PHYSMAP=y
53CONFIG_MTD_NAND=y
54CONFIG_MTD_NAND_PLATFORM=y
55CONFIG_BLK_DEV_LOOP=y
56CONFIG_BLK_DEV_UB=y
57# CONFIG_MISC_DEVICES is not set
58CONFIG_IDE=y
59CONFIG_BLK_DEV_IDECS=y
60CONFIG_BLK_DEV_IDECD=y
61CONFIG_IDE_TASK_IOCTL=y
62# CONFIG_IDE_PROC_FS is not set
63CONFIG_BLK_DEV_IDE_AU1XXX=y
64CONFIG_NETDEVICES=y
65CONFIG_NET_ETHERNET=y
66CONFIG_SMC91X=y
67# CONFIG_NETDEV_1000 is not set
68# CONFIG_NETDEV_10000 is not set
69# CONFIG_WLAN is not set
70# CONFIG_INPUT_MOUSEDEV is not set
71CONFIG_INPUT_EVDEV=y
72# CONFIG_INPUT_KEYBOARD is not set
73# CONFIG_INPUT_MOUSE is not set
74# CONFIG_SERIO is not set
75CONFIG_VT_HW_CONSOLE_BINDING=y
76CONFIG_SERIAL_8250=y
77CONFIG_SERIAL_8250_CONSOLE=y
78CONFIG_SERIAL_8250_NR_UARTS=2
79CONFIG_SERIAL_8250_RUNTIME_UARTS=2
80# CONFIG_LEGACY_PTYS is not set
81# CONFIG_HW_RANDOM is not set
82CONFIG_I2C=y
83# CONFIG_I2C_COMPAT is not set
84CONFIG_I2C_CHARDEV=y
85# CONFIG_I2C_HELPER_AUTO is not set
86CONFIG_I2C_AU1550=y
87CONFIG_SPI=y
88CONFIG_SPI_AU1550=y
89CONFIG_GPIOLIB=y
90CONFIG_GPIO_SYSFS=y
91CONFIG_SENSORS_ADM1025=y
92CONFIG_SENSORS_LM70=y
93CONFIG_FB=y
94CONFIG_FB_AU1200=y
95# CONFIG_VGA_CONSOLE is not set
96CONFIG_FRAMEBUFFER_CONSOLE=y
97CONFIG_FONTS=y
98CONFIG_FONT_8x16=y
99CONFIG_SOUND=y
100CONFIG_SND=y
101CONFIG_SND_DYNAMIC_MINORS=y
102# CONFIG_SND_SUPPORT_OLD_API is not set
103# CONFIG_SND_VERBOSE_PROCFS is not set
104# CONFIG_SND_DRIVERS is not set
105# CONFIG_SND_SPI is not set
106# CONFIG_SND_MIPS is not set
107# CONFIG_SND_USB is not set
108# CONFIG_SND_PCMCIA is not set
109CONFIG_SND_SOC=y
110CONFIG_SND_SOC_AU1XPSC=y
111CONFIG_SND_SOC_DB1200=y
112CONFIG_HIDRAW=y
113CONFIG_USB_HIDDEV=y
114CONFIG_USB=y
115CONFIG_USB_DEBUG=y
116CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
117# CONFIG_USB_DEVICE_CLASS is not set
118CONFIG_USB_DYNAMIC_MINORS=y
119CONFIG_USB_EHCI_HCD=y
120CONFIG_USB_EHCI_ROOT_HUB_TT=y
121CONFIG_USB_OHCI_HCD=y
122CONFIG_MMC=y
123# CONFIG_MMC_BLOCK_BOUNCE is not set
124CONFIG_MMC_AU1X=y
125CONFIG_NEW_LEDS=y
126CONFIG_LEDS_CLASS=y
127CONFIG_LEDS_TRIGGERS=y
128CONFIG_RTC_CLASS=y
129CONFIG_RTC_DRV_AU1XXX=y
130CONFIG_EXT2_FS=y
131CONFIG_ISO9660_FS=y
132CONFIG_JOLIET=y
133CONFIG_ZISOFS=y
134CONFIG_UDF_FS=y
135CONFIG_VFAT_FS=y
136# CONFIG_PROC_PAGE_MONITOR is not set
137CONFIG_TMPFS=y
138CONFIG_JFFS2_FS=y
139CONFIG_JFFS2_SUMMARY=y
140CONFIG_JFFS2_COMPRESSION_OPTIONS=y
141CONFIG_JFFS2_LZO=y
142CONFIG_JFFS2_RUBIN=y
143CONFIG_SQUASHFS=y
144CONFIG_NFS_FS=y
145CONFIG_NFS_V3=y
146CONFIG_ROOT_NFS=y
147CONFIG_PARTITION_ADVANCED=y
148CONFIG_EFI_PARTITION=y
149CONFIG_NLS_CODEPAGE_437=y
150CONFIG_NLS_CODEPAGE_850=y
151CONFIG_NLS_CODEPAGE_852=y
152CONFIG_NLS_CODEPAGE_1250=y
153CONFIG_NLS_ASCII=y
154CONFIG_NLS_ISO8859_1=y
155CONFIG_NLS_ISO8859_2=y
156CONFIG_NLS_ISO8859_15=y
157CONFIG_NLS_UTF8=y
158# CONFIG_ENABLE_WARN_DEPRECATED is not set
159# CONFIG_ENABLE_MUST_CHECK is not set
160CONFIG_MAGIC_SYSRQ=y
161CONFIG_STRIP_ASM_SYMS=y
162CONFIG_DEBUG_KERNEL=y
163# CONFIG_SCHED_DEBUG is not set
164# CONFIG_FTRACE is not set
165CONFIG_CMDLINE_BOOL=y
166CONFIG_CMDLINE="console=ttyS0,115200"
167CONFIG_DEBUG_ZBOOT=y
168CONFIG_KEYS=y
169CONFIG_KEYS_DEBUG_PROC_KEYS=y
170CONFIG_SECURITYFS=y
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
index 7a39657108c4..b2a8319521e5 100644
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
@@ -43,15 +43,20 @@
43#define BCSR_INT_PC1EJECT 0x0800 43#define BCSR_INT_PC1EJECT 0x0800
44#define BCSR_INT_SD0INSERT 0x1000 44#define BCSR_INT_SD0INSERT 0x1000
45#define BCSR_INT_SD0EJECT 0x2000 45#define BCSR_INT_SD0EJECT 0x2000
46#define BCSR_INT_SD1INSERT 0x4000
47#define BCSR_INT_SD1EJECT 0x8000
46 48
47#define IDE_PHYS_ADDR 0x18800000
48#define IDE_REG_SHIFT 5 49#define IDE_REG_SHIFT 5
49 50
50#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR 51#define DB1200_IDE_PHYS_ADDR 0x18800000
51#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT) 52#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
52#define DB1200_ETH_PHYS_ADDR 0x19000300 53#define DB1200_ETH_PHYS_ADDR 0x19000300
53#define DB1200_NAND_PHYS_ADDR 0x20000000 54#define DB1200_NAND_PHYS_ADDR 0x20000000
54 55
56#define PB1200_IDE_PHYS_ADDR 0x0C800000
57#define PB1200_ETH_PHYS_ADDR 0x0D000300
58#define PB1200_NAND_PHYS_ADDR 0x1C000000
59
55/* 60/*
56 * External Interrupts for DBAu1200 as of 8/6/2004. 61 * External Interrupts for DBAu1200 as of 8/6/2004.
57 * Bit positions in the CPLD registers can be calculated by taking 62 * Bit positions in the CPLD registers can be calculated by taking
@@ -77,6 +82,8 @@ enum external_db1200_ints {
77 DB1200_PC1_EJECT_INT, 82 DB1200_PC1_EJECT_INT,
78 DB1200_SD0_INSERT_INT, 83 DB1200_SD0_INSERT_INT,
79 DB1200_SD0_EJECT_INT, 84 DB1200_SD0_EJECT_INT,
85 PB1200_SD1_INSERT_INT,
86 PB1200_SD1_EJECT_INT,
80 87
81 DB1200_INT_END = DB1200_INT_BEGIN + 15, 88 DB1200_INT_END = DB1200_INT_BEGIN + 15,
82}; 89};
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
deleted file mode 100644
index 374416adb65b..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ /dev/null
@@ -1,139 +0,0 @@
1/*
2 * AMD Alchemy Pb1200 Reference Board
3 * Board Registers defines.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 *
23 */
24#ifndef __ASM_PB1200_H
25#define __ASM_PB1200_H
26
27#include <linux/types.h>
28#include <asm/mach-au1x00/au1000.h>
29#include <asm/mach-au1x00/au1xxx_psc.h>
30
31#define DBDMA_AC97_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
32#define DBDMA_AC97_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
33#define DBDMA_I2S_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
34#define DBDMA_I2S_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
35
36/*
37 * SPI and SMB are muxed on the Pb1200 board.
38 * Refer to board documentation.
39 */
40#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
41#define SMBUS_PSC_BASE AU1550_PSC0_PHYS_ADDR
42/*
43 * AC97 and I2S are muxed on the Pb1200 board.
44 * Refer to board documentation.
45 */
46#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
47#define I2S_PSC_BASE AU1550_PSC1_PHYS_ADDR
48
49
50#define BCSR_SYSTEM_VDDI 0x001F
51#define BCSR_SYSTEM_POWEROFF 0x4000
52#define BCSR_SYSTEM_RESET 0x8000
53
54/* Bit positions for the different interrupt sources */
55#define BCSR_INT_IDE 0x0001
56#define BCSR_INT_ETH 0x0002
57#define BCSR_INT_PC0 0x0004
58#define BCSR_INT_PC0STSCHG 0x0008
59#define BCSR_INT_PC1 0x0010
60#define BCSR_INT_PC1STSCHG 0x0020
61#define BCSR_INT_DC 0x0040
62#define BCSR_INT_FLASHBUSY 0x0080
63#define BCSR_INT_PC0INSERT 0x0100
64#define BCSR_INT_PC0EJECT 0x0200
65#define BCSR_INT_PC1INSERT 0x0400
66#define BCSR_INT_PC1EJECT 0x0800
67#define BCSR_INT_SD0INSERT 0x1000
68#define BCSR_INT_SD0EJECT 0x2000
69#define BCSR_INT_SD1INSERT 0x4000
70#define BCSR_INT_SD1EJECT 0x8000
71
72#define SMC91C111_PHYS_ADDR 0x0D000300
73#define SMC91C111_INT PB1200_ETH_INT
74
75#define IDE_PHYS_ADDR 0x0C800000
76#define IDE_REG_SHIFT 5
77#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
78#define IDE_INT PB1200_IDE_INT
79
80#define NAND_PHYS_ADDR 0x1C000000
81
82/*
83 * Timing values as described in databook, * ns value stripped of
84 * lower 2 bits.
85 * These defines are here rather than an Au1200 generic file because
86 * the parts chosen on another board may be different and may require
87 * different timings.
88 */
89#define NAND_T_H (18 >> 2)
90#define NAND_T_PUL (30 >> 2)
91#define NAND_T_SU (30 >> 2)
92#define NAND_T_WH (30 >> 2)
93
94/* Bitfield shift amounts */
95#define NAND_T_H_SHIFT 0
96#define NAND_T_PUL_SHIFT 4
97#define NAND_T_SU_SHIFT 8
98#define NAND_T_WH_SHIFT 12
99
100#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
101 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
102 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
103 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
104
105/*
106 * External Interrupts for Pb1200 as of 8/6/2004.
107 * Bit positions in the CPLD registers can be calculated by taking
108 * the interrupt define and subtracting the PB1200_INT_BEGIN value.
109 *
110 * Example: IDE bis pos is = 64 - 64
111 * ETH bit pos is = 65 - 64
112 */
113enum external_pb1200_ints {
114 PB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
115
116 PB1200_IDE_INT = PB1200_INT_BEGIN,
117 PB1200_ETH_INT,
118 PB1200_PC0_INT,
119 PB1200_PC0_STSCHG_INT,
120 PB1200_PC1_INT,
121 PB1200_PC1_STSCHG_INT,
122 PB1200_DC_INT,
123 PB1200_FLASHBUSY_INT,
124 PB1200_PC0_INSERT_INT,
125 PB1200_PC0_EJECT_INT,
126 PB1200_PC1_INSERT_INT,
127 PB1200_PC1_EJECT_INT,
128 PB1200_SD0_INSERT_INT,
129 PB1200_SD0_EJECT_INT,
130 PB1200_SD1_INSERT_INT,
131 PB1200_SD1_EJECT_INT,
132
133 PB1200_INT_END = PB1200_INT_BEGIN + 15
134};
135
136/* NAND chip select */
137#define NAND_CS 1
138
139#endif /* __ASM_PB1200_H */
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