diff options
-rw-r--r-- | arch/blackfin/Kconfig | 57 | ||||
-rw-r--r-- | arch/blackfin/include/asm/cache.h | 4 | ||||
-rw-r--r-- | arch/blackfin/include/asm/cacheflush.h | 10 | ||||
-rw-r--r-- | arch/blackfin/include/asm/cplb.h | 32 | ||||
-rw-r--r-- | arch/blackfin/kernel/cplb-mpu/cplbinit.c | 10 | ||||
-rw-r--r-- | arch/blackfin/kernel/cplb-mpu/cplbmgr.c | 36 | ||||
-rw-r--r-- | arch/blackfin/kernel/setup.c | 96 | ||||
-rw-r--r-- | arch/blackfin/mach-common/arch_checks.c | 4 | ||||
-rw-r--r-- | arch/blackfin/mach-common/cpufreq.c | 2 | ||||
-rw-r--r-- | arch/blackfin/mach-common/pm.c | 4 | ||||
-rw-r--r-- | arch/blackfin/mm/init.c | 2 |
11 files changed, 176 insertions, 81 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 8140a2fc8bbd..220635a1ebdd 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig | |||
@@ -907,23 +907,41 @@ endchoice | |||
907 | 907 | ||
908 | 908 | ||
909 | comment "Cache Support" | 909 | comment "Cache Support" |
910 | |||
910 | config BFIN_ICACHE | 911 | config BFIN_ICACHE |
911 | bool "Enable ICACHE" | 912 | bool "Enable ICACHE" |
913 | default y | ||
914 | config BFIN_ICACHE_LOCK | ||
915 | bool "Enable Instruction Cache Locking" | ||
916 | depends on BFIN_ICACHE | ||
917 | default n | ||
918 | config BFIN_EXTMEM_ICACHEABLE | ||
919 | bool "Enable ICACHE for external memory" | ||
920 | depends on BFIN_ICACHE | ||
921 | default y | ||
922 | config BFIN_L2_ICACHEABLE | ||
923 | bool "Enable ICACHE for L2 SRAM" | ||
924 | depends on BFIN_ICACHE | ||
925 | depends on BF54x || BF561 | ||
926 | default n | ||
927 | |||
912 | config BFIN_DCACHE | 928 | config BFIN_DCACHE |
913 | bool "Enable DCACHE" | 929 | bool "Enable DCACHE" |
930 | default y | ||
914 | config BFIN_DCACHE_BANKA | 931 | config BFIN_DCACHE_BANKA |
915 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" | 932 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
916 | depends on BFIN_DCACHE && !BF531 | 933 | depends on BFIN_DCACHE && !BF531 |
917 | default n | 934 | default n |
918 | config BFIN_ICACHE_LOCK | 935 | config BFIN_EXTMEM_DCACHEABLE |
919 | bool "Enable Instruction Cache Locking" | 936 | bool "Enable DCACHE for external memory" |
920 | |||
921 | choice | ||
922 | prompt "External memory cache policy" | ||
923 | depends on BFIN_DCACHE | 937 | depends on BFIN_DCACHE |
924 | default BFIN_WB if !SMP | 938 | default y |
925 | default BFIN_WT if SMP | 939 | choice |
926 | config BFIN_WB | 940 | prompt "External memory DCACHE policy" |
941 | depends on BFIN_EXTMEM_DCACHEABLE | ||
942 | default BFIN_EXTMEM_WRITEBACK if !SMP | ||
943 | default BFIN_EXTMEM_WRITETHROUGH if SMP | ||
944 | config BFIN_EXTMEM_WRITEBACK | ||
927 | bool "Write back" | 945 | bool "Write back" |
928 | depends on !SMP | 946 | depends on !SMP |
929 | help | 947 | help |
@@ -941,7 +959,7 @@ config BFIN_WB | |||
941 | If you are unsure of the options and you want to be safe, | 959 | If you are unsure of the options and you want to be safe, |
942 | then go with Write Through. | 960 | then go with Write Through. |
943 | 961 | ||
944 | config BFIN_WT | 962 | config BFIN_EXTMEM_WRITETHROUGH |
945 | bool "Write through" | 963 | bool "Write through" |
946 | help | 964 | help |
947 | Write Back Policy: | 965 | Write Back Policy: |
@@ -960,23 +978,26 @@ config BFIN_WT | |||
960 | 978 | ||
961 | endchoice | 979 | endchoice |
962 | 980 | ||
981 | config BFIN_L2_DCACHEABLE | ||
982 | bool "Enable DCACHE for L2 SRAM" | ||
983 | depends on BFIN_DCACHE | ||
984 | depends on BF54x || BF561 | ||
985 | default n | ||
963 | choice | 986 | choice |
964 | prompt "L2 SRAM cache policy" | 987 | prompt "L2 SRAM DCACHE policy" |
965 | depends on (BF54x || BF561) | 988 | depends on BFIN_L2_DCACHEABLE |
966 | default BFIN_L2_WT | 989 | default BFIN_L2_WRITEBACK |
967 | config BFIN_L2_WB | 990 | config BFIN_L2_WRITEBACK |
968 | bool "Write back" | 991 | bool "Write back" |
969 | depends on !SMP | 992 | depends on !SMP |
970 | 993 | ||
971 | config BFIN_L2_WT | 994 | config BFIN_L2_WRITETHROUGH |
972 | bool "Write through" | 995 | bool "Write through" |
973 | depends on !SMP | 996 | depends on !SMP |
974 | |||
975 | config BFIN_L2_NOT_CACHED | ||
976 | bool "Not cached" | ||
977 | |||
978 | endchoice | 997 | endchoice |
979 | 998 | ||
999 | |||
1000 | comment "Memory Protection Unit" | ||
980 | config MPU | 1001 | config MPU |
981 | bool "Enable the memory protection unit (EXPERIMENTAL)" | 1002 | bool "Enable the memory protection unit (EXPERIMENTAL)" |
982 | default n | 1003 | default n |
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h index 2ef669ed9222..477050ad5c53 100644 --- a/arch/blackfin/include/asm/cache.h +++ b/arch/blackfin/include/asm/cache.h | |||
@@ -35,10 +35,10 @@ | |||
35 | 35 | ||
36 | #if defined(CONFIG_SMP) && \ | 36 | #if defined(CONFIG_SMP) && \ |
37 | !defined(CONFIG_BFIN_CACHE_COHERENT) | 37 | !defined(CONFIG_BFIN_CACHE_COHERENT) |
38 | # if defined(CONFIG_BFIN_ICACHE) | 38 | # if defined(CONFIG_BFIN_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE) |
39 | # define __ARCH_SYNC_CORE_ICACHE | 39 | # define __ARCH_SYNC_CORE_ICACHE |
40 | # endif | 40 | # endif |
41 | # if defined(CONFIG_BFIN_DCACHE) | 41 | # if defined(CONFIG_BFIN_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE) |
42 | # define __ARCH_SYNC_CORE_DCACHE | 42 | # define __ARCH_SYNC_CORE_DCACHE |
43 | # endif | 43 | # endif |
44 | #ifndef __ASSEMBLY__ | 44 | #ifndef __ASSEMBLY__ |
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h index 5c17dee53b5d..7e55549e180f 100644 --- a/arch/blackfin/include/asm/cacheflush.h +++ b/arch/blackfin/include/asm/cacheflush.h | |||
@@ -56,7 +56,7 @@ extern void blackfin_invalidate_entire_icache(void); | |||
56 | 56 | ||
57 | static inline void flush_icache_range(unsigned start, unsigned end) | 57 | static inline void flush_icache_range(unsigned start, unsigned end) |
58 | { | 58 | { |
59 | #if defined(CONFIG_BFIN_WB) | 59 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
60 | blackfin_dcache_flush_range(start, end); | 60 | blackfin_dcache_flush_range(start, end); |
61 | #endif | 61 | #endif |
62 | 62 | ||
@@ -87,9 +87,9 @@ do { memcpy(dst, src, len); \ | |||
87 | #else | 87 | #else |
88 | # define invalidate_dcache_range(start,end) do { } while (0) | 88 | # define invalidate_dcache_range(start,end) do { } while (0) |
89 | #endif | 89 | #endif |
90 | #if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB) | 90 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
91 | # define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) | 91 | # define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) |
92 | # define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) | 92 | # define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) |
93 | #else | 93 | #else |
94 | # define flush_dcache_range(start,end) do { } while (0) | 94 | # define flush_dcache_range(start,end) do { } while (0) |
95 | # define flush_dcache_page(page) do { } while (0) | 95 | # define flush_dcache_page(page) do { } while (0) |
@@ -100,7 +100,7 @@ extern unsigned long reserved_mem_icache_on; | |||
100 | 100 | ||
101 | static inline int bfin_addr_dcacheable(unsigned long addr) | 101 | static inline int bfin_addr_dcacheable(unsigned long addr) |
102 | { | 102 | { |
103 | #ifdef CONFIG_BFIN_DCACHE | 103 | #ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE |
104 | if (addr < (_ramend - DMA_UNCACHED_REGION)) | 104 | if (addr < (_ramend - DMA_UNCACHED_REGION)) |
105 | return 1; | 105 | return 1; |
106 | #endif | 106 | #endif |
@@ -109,7 +109,7 @@ static inline int bfin_addr_dcacheable(unsigned long addr) | |||
109 | addr >= _ramend && addr < physical_mem_end) | 109 | addr >= _ramend && addr < physical_mem_end) |
110 | return 1; | 110 | return 1; |
111 | 111 | ||
112 | #ifndef CONFIG_BFIN_L2_NOT_CACHED | 112 | #ifdef CONFIG_BFIN_L2_DCACHEABLE |
113 | if (addr >= L2_START && addr < L2_START + L2_LENGTH) | 113 | if (addr >= L2_START && addr < L2_START + L2_LENGTH) |
114 | return 1; | 114 | return 1; |
115 | #endif | 115 | #endif |
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index a75a6a9f0949..c5dacf8f8cf9 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h | |||
@@ -37,8 +37,6 @@ | |||
37 | #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) | 37 | #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) |
38 | #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) | 38 | #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) |
39 | 39 | ||
40 | /*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/ | ||
41 | |||
42 | #if ANOMALY_05000158 | 40 | #if ANOMALY_05000158 |
43 | #define ANOMALY_05000158_WORKAROUND 0x200 | 41 | #define ANOMALY_05000158_WORKAROUND 0x200 |
44 | #else | 42 | #else |
@@ -47,10 +45,12 @@ | |||
47 | 45 | ||
48 | #define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) | 46 | #define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) |
49 | 47 | ||
50 | #ifdef CONFIG_BFIN_WB /*Write Back Policy */ | 48 | #ifdef CONFIG_BFIN_EXTMEM_WRITEBACK |
51 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON) | 49 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON) |
52 | #else /*Write Through */ | 50 | #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH) |
53 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) | 51 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) |
52 | #else | ||
53 | #define SDRAM_DGENERIC (CPLB_COMMON) | ||
54 | #endif | 54 | #endif |
55 | 55 | ||
56 | #define SDRAM_DNON_CHBL (CPLB_COMMON) | 56 | #define SDRAM_DNON_CHBL (CPLB_COMMON) |
@@ -61,21 +61,23 @@ | |||
61 | 61 | ||
62 | #ifdef CONFIG_SMP | 62 | #ifdef CONFIG_SMP |
63 | #define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) | 63 | #define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) |
64 | #define L2_IMEMORY (CPLB_COMMON) | 64 | #define L2_IMEMORY (CPLB_COMMON | PAGE_SIZE_1MB) |
65 | #define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON) | 65 | #define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB) |
66 | 66 | ||
67 | #else | 67 | #else |
68 | #define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) | 68 | #define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) |
69 | #define L2_IMEMORY (SDRAM_IGENERIC) | 69 | # if defined(CONFIG_BFIN_L2_ICACHEABLE) |
70 | 70 | # define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB) | |
71 | # if defined(CONFIG_BFIN_L2_WB) | 71 | # else |
72 | # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON) | 72 | # define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB) |
73 | # elif defined(CONFIG_BFIN_L2_WT) | 73 | # endif |
74 | # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) | 74 | |
75 | # elif defined(CONFIG_BFIN_L2_NOT_CACHED) | 75 | # if defined(CONFIG_BFIN_L2_WRITEBACK) |
76 | # define L2_DMEMORY (CPLB_COMMON) | 76 | # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB) |
77 | # elif defined(CONFIG_BFIN_L2_WRITETHROUGH) | ||
78 | # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB) | ||
77 | # else | 79 | # else |
78 | # define L2_DMEMORY (0) | 80 | # define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB) |
79 | # endif | 81 | # endif |
80 | #endif /* CONFIG_SMP */ | 82 | #endif /* CONFIG_SMP */ |
81 | 83 | ||
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c index c006a44527bf..36193eed9a1f 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c | |||
@@ -46,13 +46,13 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) | |||
46 | 46 | ||
47 | printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n"); | 47 | printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n"); |
48 | 48 | ||
49 | #ifdef CONFIG_BFIN_ICACHE | 49 | #ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE |
50 | i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; | 50 | i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; |
51 | #endif | 51 | #endif |
52 | 52 | ||
53 | #ifdef CONFIG_BFIN_DCACHE | 53 | #ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE |
54 | d_cache = CPLB_L1_CHBL; | 54 | d_cache = CPLB_L1_CHBL; |
55 | #ifdef CONFIG_BFIN_WT | 55 | #ifdef CONFIG_BFIN_EXTMEM_WRITETROUGH |
56 | d_cache |= CPLB_L1_AOW | CPLB_WT; | 56 | d_cache |= CPLB_L1_AOW | CPLB_WT; |
57 | #endif | 57 | #endif |
58 | #endif | 58 | #endif |
@@ -91,9 +91,9 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) | |||
91 | /* Cover L2 memory */ | 91 | /* Cover L2 memory */ |
92 | #if L2_LENGTH > 0 | 92 | #if L2_LENGTH > 0 |
93 | dcplb_tbl[cpu][i_d].addr = L2_START; | 93 | dcplb_tbl[cpu][i_d].addr = L2_START; |
94 | dcplb_tbl[cpu][i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB; | 94 | dcplb_tbl[cpu][i_d++].data = L2_DMEMORY; |
95 | icplb_tbl[cpu][i_i].addr = L2_START; | 95 | icplb_tbl[cpu][i_i].addr = L2_START; |
96 | icplb_tbl[cpu][i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB; | 96 | icplb_tbl[cpu][i_i++].data = L2_IMEMORY; |
97 | #endif | 97 | #endif |
98 | 98 | ||
99 | first_mask_dcplb = i_d; | 99 | first_mask_dcplb = i_d; |
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index 784923e52a9a..bcdfe9b0b71f 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c | |||
@@ -150,15 +150,19 @@ static noinline int dcplb_miss(unsigned int cpu) | |||
150 | nr_dcplb_miss[cpu]++; | 150 | nr_dcplb_miss[cpu]++; |
151 | 151 | ||
152 | d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; | 152 | d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; |
153 | #ifdef CONFIG_BFIN_DCACHE | 153 | #ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE |
154 | if (bfin_addr_dcacheable(addr)) { | 154 | if (bfin_addr_dcacheable(addr)) { |
155 | d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; | 155 | d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; |
156 | #ifdef CONFIG_BFIN_WT | 156 | # ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH |
157 | d_data |= CPLB_L1_AOW | CPLB_WT; | 157 | d_data |= CPLB_L1_AOW | CPLB_WT; |
158 | #endif | 158 | # endif |
159 | } | 159 | } |
160 | #endif | 160 | #endif |
161 | if (addr >= physical_mem_end) { | 161 | |
162 | if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) { | ||
163 | addr = L2_START; | ||
164 | d_data = L2_DMEMORY; | ||
165 | } else if (addr >= physical_mem_end) { | ||
162 | if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE | 166 | if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE |
163 | && (status & FAULT_USERSUPV)) { | 167 | && (status & FAULT_USERSUPV)) { |
164 | addr &= ~0x3fffff; | 168 | addr &= ~0x3fffff; |
@@ -235,7 +239,7 @@ static noinline int icplb_miss(unsigned int cpu) | |||
235 | 239 | ||
236 | i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB; | 240 | i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB; |
237 | 241 | ||
238 | #ifdef CONFIG_BFIN_ICACHE | 242 | #ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE |
239 | /* | 243 | /* |
240 | * Normal RAM, and possibly the reserved memory area, are | 244 | * Normal RAM, and possibly the reserved memory area, are |
241 | * cacheable. | 245 | * cacheable. |
@@ -245,7 +249,10 @@ static noinline int icplb_miss(unsigned int cpu) | |||
245 | i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; | 249 | i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; |
246 | #endif | 250 | #endif |
247 | 251 | ||
248 | if (addr >= physical_mem_end) { | 252 | if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) { |
253 | addr = L2_START; | ||
254 | i_data = L2_IMEMORY; | ||
255 | } else if (addr >= physical_mem_end) { | ||
249 | if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH | 256 | if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH |
250 | && (status & FAULT_USERSUPV)) { | 257 | && (status & FAULT_USERSUPV)) { |
251 | addr &= ~(1 * 1024 * 1024 - 1); | 258 | addr &= ~(1 * 1024 * 1024 - 1); |
@@ -365,13 +372,18 @@ void set_mask_dcplbs(unsigned long *masks, unsigned int cpu) | |||
365 | local_irq_save_hw(flags); | 372 | local_irq_save_hw(flags); |
366 | current_rwx_mask[cpu] = masks; | 373 | current_rwx_mask[cpu] = masks; |
367 | 374 | ||
368 | d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; | 375 | if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) { |
369 | #ifdef CONFIG_BFIN_DCACHE | 376 | addr = L2_START; |
370 | d_data |= CPLB_L1_CHBL; | 377 | d_data = L2_DMEMORY; |
371 | #ifdef CONFIG_BFIN_WT | 378 | } else { |
372 | d_data |= CPLB_L1_AOW | CPLB_WT; | 379 | d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; |
373 | #endif | 380 | #ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE |
381 | d_data |= CPLB_L1_CHBL; | ||
382 | # ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH | ||
383 | d_data |= CPLB_L1_AOW | CPLB_WT; | ||
384 | # endif | ||
374 | #endif | 385 | #endif |
386 | } | ||
375 | 387 | ||
376 | disable_dcplb(); | 388 | disable_dcplb(); |
377 | for (i = first_mask_dcplb; i < first_switched_dcplb; i++) { | 389 | for (i = first_mask_dcplb; i < first_switched_dcplb; i++) { |
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index b2782eae31e1..8d7892820130 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c | |||
@@ -117,15 +117,49 @@ void __cpuinit bfin_setup_caches(unsigned int cpu) | |||
117 | */ | 117 | */ |
118 | #ifdef CONFIG_BFIN_ICACHE | 118 | #ifdef CONFIG_BFIN_ICACHE |
119 | printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu); | 119 | printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu); |
120 | printk(KERN_INFO " External memory:" | ||
121 | # ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE | ||
122 | " cacheable" | ||
123 | # else | ||
124 | " uncacheable" | ||
125 | # endif | ||
126 | " in instruction cache\n"); | ||
127 | if (L2_LENGTH) | ||
128 | printk(KERN_INFO " L2 SRAM :" | ||
129 | # ifdef CONFIG_BFIN_L2_ICACHEABLE | ||
130 | " cacheable" | ||
131 | # else | ||
132 | " uncacheable" | ||
133 | # endif | ||
134 | " in instruction cache\n"); | ||
135 | |||
136 | #else | ||
137 | printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu); | ||
120 | #endif | 138 | #endif |
139 | |||
121 | #ifdef CONFIG_BFIN_DCACHE | 140 | #ifdef CONFIG_BFIN_DCACHE |
122 | printk(KERN_INFO "Data Cache Enabled for CPU%u" | 141 | printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu); |
123 | # if defined CONFIG_BFIN_WB | 142 | printk(KERN_INFO " External memory:" |
124 | " (write-back)" | 143 | # if defined CONFIG_BFIN_EXTMEM_WRITEBACK |
125 | # elif defined CONFIG_BFIN_WT | 144 | " cacheable (write-back)" |
126 | " (write-through)" | 145 | # elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH |
146 | " cacheable (write-through)" | ||
147 | # else | ||
148 | " uncacheable" | ||
149 | # endif | ||
150 | " in data cache\n"); | ||
151 | if (L2_LENGTH) | ||
152 | printk(KERN_INFO " L2 SRAM :" | ||
153 | # if defined CONFIG_BFIN_L2_WRITEBACK | ||
154 | " cacheable (write-back)" | ||
155 | # elif defined CONFIG_BFIN_L2_WRITETHROUGH | ||
156 | " cacheable (write-through)" | ||
157 | # else | ||
158 | " uncacheable" | ||
127 | # endif | 159 | # endif |
128 | "\n", cpu); | 160 | " in data cache\n"); |
161 | #else | ||
162 | printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu); | ||
129 | #endif | 163 | #endif |
130 | } | 164 | } |
131 | 165 | ||
@@ -516,7 +550,7 @@ static __init void memory_setup(void) | |||
516 | && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) | 550 | && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) |
517 | mtd_size = | 551 | mtd_size = |
518 | PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); | 552 | PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); |
519 | # if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) | 553 | # if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) |
520 | /* Due to a Hardware Anomaly we need to limit the size of usable | 554 | /* Due to a Hardware Anomaly we need to limit the size of usable |
521 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on | 555 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on |
522 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception | 556 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception |
@@ -544,7 +578,7 @@ static __init void memory_setup(void) | |||
544 | dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size); | 578 | dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size); |
545 | #endif /* CONFIG_MTD_UCLINUX */ | 579 | #endif /* CONFIG_MTD_UCLINUX */ |
546 | 580 | ||
547 | #if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) | 581 | #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) |
548 | /* Due to a Hardware Anomaly we need to limit the size of usable | 582 | /* Due to a Hardware Anomaly we need to limit the size of usable |
549 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on | 583 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on |
550 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception | 584 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception |
@@ -1158,16 +1192,25 @@ static int show_cpuinfo(struct seq_file *m, void *v) | |||
1158 | icache_size = 0; | 1192 | icache_size = 0; |
1159 | 1193 | ||
1160 | seq_printf(m, "cache size\t: %d KB(L1 icache) " | 1194 | seq_printf(m, "cache size\t: %d KB(L1 icache) " |
1161 | "%d KB(L1 dcache%s) %d KB(L2 cache)\n", | 1195 | "%d KB(L1 dcache) %d KB(L2 cache)\n", |
1162 | icache_size, dcache_size, | 1196 | icache_size, dcache_size, 0); |
1163 | #if defined CONFIG_BFIN_WB | ||
1164 | "-wb" | ||
1165 | #elif defined CONFIG_BFIN_WT | ||
1166 | "-wt" | ||
1167 | #endif | ||
1168 | "", 0); | ||
1169 | |||
1170 | seq_printf(m, "%s\n", cache); | 1197 | seq_printf(m, "%s\n", cache); |
1198 | seq_printf(m, "external memory\t: " | ||
1199 | #if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) | ||
1200 | "cacheable" | ||
1201 | #else | ||
1202 | "uncacheable" | ||
1203 | #endif | ||
1204 | " in instruction cache\n"); | ||
1205 | seq_printf(m, "external memory\t: " | ||
1206 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) | ||
1207 | "cacheable (write-back)" | ||
1208 | #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH) | ||
1209 | "cacheable (write-through)" | ||
1210 | #else | ||
1211 | "uncacheable" | ||
1212 | #endif | ||
1213 | " in data cache\n"); | ||
1171 | 1214 | ||
1172 | if (icache_size) | 1215 | if (icache_size) |
1173 | seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n", | 1216 | seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n", |
@@ -1240,8 +1283,25 @@ static int show_cpuinfo(struct seq_file *m, void *v) | |||
1240 | if (cpu_num != num_possible_cpus() - 1) | 1283 | if (cpu_num != num_possible_cpus() - 1) |
1241 | return 0; | 1284 | return 0; |
1242 | 1285 | ||
1243 | if (L2_LENGTH) | 1286 | if (L2_LENGTH) { |
1244 | seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400); | 1287 | seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400); |
1288 | seq_printf(m, "L2 SRAM\t\t: " | ||
1289 | #if defined(CONFIG_BFIN_L2_ICACHEABLE) | ||
1290 | "cacheable" | ||
1291 | #else | ||
1292 | "uncacheable" | ||
1293 | #endif | ||
1294 | " in instruction cache\n"); | ||
1295 | seq_printf(m, "L2 SRAM\t\t: " | ||
1296 | #if defined(CONFIG_BFIN_L2_WRITEBACK) | ||
1297 | "cacheable (write-back)" | ||
1298 | #elif defined(CONFIG_BFIN_L2_WRITETHROUGH) | ||
1299 | "cacheable (write-through)" | ||
1300 | #else | ||
1301 | "uncacheable" | ||
1302 | #endif | ||
1303 | " in data cache\n"); | ||
1304 | } | ||
1245 | seq_printf(m, "board name\t: %s\n", bfin_board_name); | 1305 | seq_printf(m, "board name\t: %s\n", bfin_board_name); |
1246 | seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n", | 1306 | seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n", |
1247 | physical_mem_end >> 10, (void *)0, (void *)physical_mem_end); | 1307 | physical_mem_end >> 10, (void *)0, (void *)physical_mem_end); |
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c index da93d9207165..5998d8632a73 100644 --- a/arch/blackfin/mach-common/arch_checks.c +++ b/arch/blackfin/mach-common/arch_checks.c | |||
@@ -74,7 +74,7 @@ | |||
74 | 74 | ||
75 | /* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */ | 75 | /* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */ |
76 | #if ANOMALY_05000220 && \ | 76 | #if ANOMALY_05000220 && \ |
77 | ((defined(CONFIG_BFIN_WB) && defined(CONFIG_BFIN_L2_NOT_CACHED)) || \ | 77 | ((defined(CONFIG_BFIN_EXTMEM_WRITEBACK) && !defined(CONFIG_BFIN_L2_DCACHEABLE)) || \ |
78 | (!defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_L2_WB))) | 78 | (!defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) && defined(CONFIG_BFIN_L2_WRITEBACK))) |
79 | # error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB. | 79 | # error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB. |
80 | #endif | 80 | #endif |
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c index 70e3411f558c..85c658083279 100644 --- a/arch/blackfin/mach-common/cpufreq.c +++ b/arch/blackfin/mach-common/cpufreq.c | |||
@@ -141,7 +141,7 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy) | |||
141 | sclk = get_sclk() / 1000; | 141 | sclk = get_sclk() / 1000; |
142 | 142 | ||
143 | #if ANOMALY_05000273 || ANOMALY_05000274 || \ | 143 | #if ANOMALY_05000273 || ANOMALY_05000274 || \ |
144 | (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE)) | 144 | (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE)) |
145 | min_cclk = sclk * 2; | 145 | min_cclk = sclk * 2; |
146 | #else | 146 | #else |
147 | min_cclk = sclk; | 147 | min_cclk = sclk; |
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index bce5a84be49f..9e7e27b7fc8d 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c | |||
@@ -132,7 +132,7 @@ int bf53x_resume_l1_mem(unsigned char *memptr) | |||
132 | return 0; | 132 | return 0; |
133 | } | 133 | } |
134 | 134 | ||
135 | #ifdef CONFIG_BFIN_WB | 135 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
136 | static void flushinv_all_dcache(void) | 136 | static void flushinv_all_dcache(void) |
137 | { | 137 | { |
138 | u32 way, bank, subbank, set; | 138 | u32 way, bank, subbank, set; |
@@ -175,7 +175,7 @@ static inline void dcache_disable(void) | |||
175 | #ifdef CONFIG_BFIN_DCACHE | 175 | #ifdef CONFIG_BFIN_DCACHE |
176 | unsigned long ctrl; | 176 | unsigned long ctrl; |
177 | 177 | ||
178 | #ifdef CONFIG_BFIN_WB | 178 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
179 | flushinv_all_dcache(); | 179 | flushinv_all_dcache(); |
180 | #endif | 180 | #endif |
181 | SSYNC(); | 181 | SSYNC(); |
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c index 014a55abd09a..68bd0bd680cd 100644 --- a/arch/blackfin/mm/init.c +++ b/arch/blackfin/mm/init.c | |||
@@ -160,7 +160,7 @@ void __init mem_init(void) | |||
160 | 160 | ||
161 | /* do not count in kernel image between _rambase and _ramstart */ | 161 | /* do not count in kernel image between _rambase and _ramstart */ |
162 | reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT; | 162 | reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT; |
163 | #if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) | 163 | #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) |
164 | reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >> PAGE_SHIFT; | 164 | reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >> PAGE_SHIFT; |
165 | #endif | 165 | #endif |
166 | 166 | ||