3 files changed, 37 insertions, 37 deletions
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
index 11a3c1e9801f..461fd69a10ae 100644
--- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h
+++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -13,27 +13,27 @@
 #include <mach/orion5x.h>
-#define CPU_CONF                (ORION5X_BRIDGE_VIRT_BASE | 0x100)
+#define CPU_CONF                (ORION5X_BRIDGE_VIRT_BASE + 0x100)
-#define CPU_CTRL                (ORION5X_BRIDGE_VIRT_BASE | 0x104)
+#define CPU_CTRL                (ORION5X_BRIDGE_VIRT_BASE + 0x104)
-#define RSTOUTn_MASK            (ORION5X_BRIDGE_VIRT_BASE | 0x108)
+#define RSTOUTn_MASK            (ORION5X_BRIDGE_VIRT_BASE + 0x108)
 #define WDT_RESET_OUT_EN        0x0002
-#define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
+#define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
-#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE | 0x110)
+#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE + 0x110)
-#define POWER_MNG_CTRL_REG      (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
+#define POWER_MNG_CTRL_REG      (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
 #define WDT_INT_REQ             0x0008
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
-#define MAIN_IRQ_CAUSE          (ORION5X_BRIDGE_VIRT_BASE | 0x200)
+#define MAIN_IRQ_CAUSE          (ORION5X_BRIDGE_VIRT_BASE + 0x200)
-#define MAIN_IRQ_MASK           (ORION5X_BRIDGE_VIRT_BASE | 0x204)
+#define MAIN_IRQ_MASK           (ORION5X_BRIDGE_VIRT_BASE + 0x204)
-#define TIMER_VIRT_BASE         (ORION5X_BRIDGE_VIRT_BASE | 0x300)
+#define TIMER_VIRT_BASE         (ORION5X_BRIDGE_VIRT_BASE + 0x300)
-#define TIMER_PHYS_BASE         (ORION5X_BRIDGE_PHYS_BASE | 0x300)
+#define TIMER_PHYS_BASE         (ORION5X_BRIDGE_PHYS_BASE + 0x300)
 #endif
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 683e085ce162..87bd378b8203 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -68,42 +68,42 @@
 * Orion Registers Map
 ******************************************************************************/
-#define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x00000)
+#define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x00000)
-#define  ORION5X_DDR_WINDOW_CPU_BASE    (ORION5X_DDR_VIRT_BASE | 0x1500)
+#define  ORION5X_DDR_WINDOW_CPU_BASE    (ORION5X_DDR_VIRT_BASE + 0x1500)
-#define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
+#define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE + 0x10000)
-#define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
+#define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE + 0x10000)
-#define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
+#define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE + (x))
 #define  GPIO_VIRT_BASE                 ORION5X_DEV_BUS_REG(0x0100)
-#define  SPI_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
+#define  SPI_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE + 0x0600)
-#define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
+#define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE + 0x1000)
-#define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE + 0x2000)
-#define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE + 0x2000)
-#define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE + 0x2100)
-#define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
+#define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE + 0x2100)
-#define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE | 0x20000)
+#define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE + 0x20000)
-#define ORION5X_BRIDGE_PHYS_BASE        (ORION5X_REGS_PHYS_BASE | 0x20000)
+#define ORION5X_BRIDGE_PHYS_BASE        (ORION5X_REGS_PHYS_BASE + 0x20000)
-#define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x30000)
+#define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x30000)
-#define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x40000)
+#define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x40000)
-#define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x50000)
+#define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0x50000)
-#define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x50000)
+#define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x50000)
-#define ORION5X_XOR_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x60900)
+#define ORION5X_XOR_PHYS_BASE           (ORION5X_REGS_PHYS_BASE + 0x60900)
-#define ORION5X_XOR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x60900)
+#define ORION5X_XOR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x60900)
-#define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x70000)
+#define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE + 0x70000)
-#define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x70000)
+#define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x70000)
-#define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x80000)
+#define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0x80000)
-#define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x80000)
+#define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x80000)
-#define ORION5X_CRYPTO_PHYS_BASE        (ORION5X_REGS_PHYS_BASE | 0x90000)
+#define ORION5X_CRYPTO_PHYS_BASE        (ORION5X_REGS_PHYS_BASE + 0x90000)
-#define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0xa0000)
+#define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0xa0000)
-#define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0xa0000)
+#define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0xa0000)
 /*******************************************************************************
 * Device Bus Registers
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index cb19e1661bb3..b36f928d017c 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -198,7 +198,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
 /*****************************************************************************
 * PCI controller
 ****************************************************************************/
-#define ORION5X_PCI_REG(x)      (ORION5X_PCI_VIRT_BASE | (x))
+#define ORION5X_PCI_REG(x)      (ORION5X_PCI_VIRT_BASE + (x))
 #define PCI_MODE                ORION5X_PCI_REG(0xd00)
 #define PCI_CMD                 ORION5X_PCI_REG(0xc00)
 #define PCI_P2P_CONF            ORION5X_PCI_REG(0x1d14)

diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h index 11a3c1e9801f..461fd69a10ae 100644 --- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h +++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -13,27 +13,27 @@
13		13
14	#include <mach/orion5x.h>	14	#include <mach/orion5x.h>
15		15
16	#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE \| 0x100)	16	#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
17		17
18	#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE \| 0x104)	18	#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
19		19
20	#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE \| 0x108)	20	#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
21	#define WDT_RESET_OUT_EN 0x0002	21	#define WDT_RESET_OUT_EN 0x0002
22		22
23	#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE \| 0x10c)	23	#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
24		24
25	#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE \| 0x110)	25	#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
26		26
27	#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE \| 0x11C)	27	#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
28		28
29	#define WDT_INT_REQ 0x0008	29	#define WDT_INT_REQ 0x0008
30		30
31	#define BRIDGE_INT_TIMER1_CLR (~0x0004)	31	#define BRIDGE_INT_TIMER1_CLR (~0x0004)
32		32
33	#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE \| 0x200)	33	#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
34		34
35	#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE \| 0x204)	35	#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
36		36
37	#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE \| 0x300)	37	#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300)
38	#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE \| 0x300)	38	#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300)
39	#endif	39	#endif


diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 683e085ce162..87bd378b8203 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -68,42 +68,42 @@
68	* Orion Registers Map	68	* Orion Registers Map
69	******************************************************************************/	69	******************************************************************************/
70		70
71	#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x00000)	71	#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000)
72	#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE \| 0x1500)	72	#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE + 0x1500)
73	#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE \| 0x10000)	73	#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000)
74	#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x10000)	74	#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000)
75	#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE \| (x))	75	#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x))
76	#define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100)	76	#define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100)
77	#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE \| 0x0600)	77	#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x0600)
78	#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE \| 0x1000)	78	#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x1000)
79	#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE \| 0x2000)	79	#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2000)
80	#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE \| 0x2000)	80	#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2000)
81	#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE \| 0x2100)	81	#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2100)
82	#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE \| 0x2100)	82	#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2100)
83		83
84	#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x20000)	84	#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000)
85	#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE \| 0x20000)	85	#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000)
86		86
87	#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x30000)	87	#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000)
88		88
89	#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x40000)	89	#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x40000)
90		90
91	#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE \| 0x50000)	91	#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x50000)
92	#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x50000)	92	#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x50000)
93		93
94	#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE \| 0x60900)	94	#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x60900)
95	#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x60900)	95	#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x60900)
96		96
97	#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE \| 0x70000)	97	#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x70000)
98	#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x70000)	98	#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x70000)
99		99
100	#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE \| 0x80000)	100	#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x80000)
101	#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x80000)	101	#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x80000)
102		102
103	#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE \| 0x90000)	103	#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x90000)
104		104
105	#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE \| 0xa0000)	105	#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0xa0000)
106	#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0xa0000)	106	#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0xa0000)
107		107
108	/*******************************************************************************	108	/*******************************************************************************
109	* Device Bus Registers	109	* Device Bus Registers


diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index cb19e1661bb3..b36f928d017c 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c
@@ -198,7 +198,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
198	/*****************************************************************************	198	/*****************************************************************************
199	* PCI controller	199	* PCI controller
200	****************************************************************************/	200	****************************************************************************/
201	#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE \| (x))	201	#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x))
202	#define PCI_MODE ORION5X_PCI_REG(0xd00)	202	#define PCI_MODE ORION5X_PCI_REG(0xd00)
203	#define PCI_CMD ORION5X_PCI_REG(0xc00)	203	#define PCI_CMD ORION5X_PCI_REG(0xc00)
204	#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)	204	#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)