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-rw-r--r--drivers/clk/tegra/clk-tegra114.c37
-rw-r--r--drivers/clk/tegra/clk.h2
2 files changed, 39 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index ccfff33e00b7..fdf14c1abd14 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -29,6 +29,7 @@
29#define RST_DEVICES_L 0x004 29#define RST_DEVICES_L 0x004
30#define RST_DEVICES_H 0x008 30#define RST_DEVICES_H 0x008
31#define RST_DEVICES_U 0x00C 31#define RST_DEVICES_U 0x00C
32#define RST_DFLL_DVCO 0x2F4
32#define RST_DEVICES_V 0x358 33#define RST_DEVICES_V 0x358
33#define RST_DEVICES_W 0x35C 34#define RST_DEVICES_W 0x35C
34#define RST_DEVICES_X 0x28C 35#define RST_DEVICES_X 0x28C
@@ -47,6 +48,9 @@
47#define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */ 48#define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */
48#define RST_DEVICES_NUM 5 49#define RST_DEVICES_NUM 5
49 50
51/* RST_DFLL_DVCO bitfields */
52#define DVFS_DFLL_RESET_SHIFT 0
53
50/* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */ 54/* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */
51#define CPU_FINETRIM_1_FCPU_1 BIT(0) /* fcpu0 */ 55#define CPU_FINETRIM_1_FCPU_1 BIT(0) /* fcpu0 */
52#define CPU_FINETRIM_1_FCPU_2 BIT(1) /* fcpu1 */ 56#define CPU_FINETRIM_1_FCPU_2 BIT(1) /* fcpu1 */
@@ -2248,6 +2252,39 @@ void tegra114_clock_tune_cpu_trimmers_init(void)
2248} 2252}
2249EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init); 2253EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
2250 2254
2255/**
2256 * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
2257 *
2258 * Assert the reset line of the DFLL's DVCO. No return value.
2259 */
2260void tegra114_clock_assert_dfll_dvco_reset(void)
2261{
2262 u32 v;
2263
2264 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
2265 v |= (1 << DVFS_DFLL_RESET_SHIFT);
2266 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
2267 tegra114_car_barrier();
2268}
2269EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
2270
2271/**
2272 * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
2273 *
2274 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
2275 * operate. No return value.
2276 */
2277void tegra114_clock_deassert_dfll_dvco_reset(void)
2278{
2279 u32 v;
2280
2281 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
2282 v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
2283 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
2284 tegra114_car_barrier();
2285}
2286EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
2287
2251static void __init tegra114_clock_init(struct device_node *np) 2288static void __init tegra114_clock_init(struct device_node *np)
2252{ 2289{
2253 struct device_node *node; 2290 struct device_node *node;
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 554814c67825..07cfacd91686 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -590,6 +590,8 @@ void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
590void tegra114_clock_tune_cpu_trimmers_high(void); 590void tegra114_clock_tune_cpu_trimmers_high(void);
591void tegra114_clock_tune_cpu_trimmers_low(void); 591void tegra114_clock_tune_cpu_trimmers_low(void);
592void tegra114_clock_tune_cpu_trimmers_init(void); 592void tegra114_clock_tune_cpu_trimmers_init(void);
593void tegra114_clock_assert_dfll_dvco_reset(void);
594void tegra114_clock_deassert_dfll_dvco_reset(void);
593 595
594typedef void (*tegra_clk_apply_init_table_func)(void); 596typedef void (*tegra_clk_apply_init_table_func)(void);
595extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 597extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;