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-rw-r--r--arch/m68k/include/asm/m5206sim.h16
-rw-r--r--arch/m68k/include/asm/m5249sim.h13
-rw-r--r--arch/m68k/include/asm/m5307sim.h17
-rw-r--r--arch/m68k/include/asm/m5407sim.h13
-rw-r--r--arch/m68k/include/asm/mcfintc.h73
-rw-r--r--arch/m68knommu/platform/5206/config.c11
-rw-r--r--arch/m68knommu/platform/5206e/config.c12
-rw-r--r--arch/m68knommu/platform/5249/config.c11
-rw-r--r--arch/m68knommu/platform/5307/config.c12
-rw-r--r--arch/m68knommu/platform/5407/config.c12
-rw-r--r--arch/m68knommu/platform/coldfire/intc.c59
11 files changed, 109 insertions, 140 deletions
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 7be8a2d3e659..b50061aaf8f0 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -117,21 +117,11 @@
117#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */ 117#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
118#endif 118#endif
119 119
120#if defined(CONFIG_M5206e)
121#define MCFSIM_IMR_MASKALL 0xfffe /* All SIM intr sources */
122#endif
123
124/* 120/*
125 * Macro to get and set IMR register. It is 16 bits on the 5206. 121 * Let the common interrupt handler code know that the ColdFire 5206*
122 * family of CPU's only has a 16bit sized IMR register.
126 */ 123 */
127#define mcf_getimr() \ 124#define MCFSIM_IMR_IS_16BITS
128 *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR))
129
130#define mcf_setimr(imr) \
131 *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR)) = (imr)
132
133#define mcf_getipr() \
134 *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IPR))
135 125
136/****************************************************************************/ 126/****************************************************************************/
137#endif /* m5206sim_h */ 127#endif /* m5206sim_h */
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 2c23a83512a4..36ed31bbf6cb 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -106,19 +106,6 @@
106#define MCFGPIO_PIN_MAX 64 106#define MCFGPIO_PIN_MAX 64
107#define MCFGPIO_IRQ_MAX -1 107#define MCFGPIO_IRQ_MAX -1
108#define MCFGPIO_IRQ_VECBASE -1 108#define MCFGPIO_IRQ_VECBASE -1
109/*
110 * Macro to set IMR register. It is 32 bits on the 5249.
111 */
112#define MCFSIM_IMR_MASKALL 0x7fffe /* All SIM intr sources */
113
114#define mcf_getimr() \
115 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
116
117#define mcf_setimr(imr) \
118 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
119
120#define mcf_getipr() \
121 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
122 109
123/****************************************************************************/ 110/****************************************************************************/
124 111
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 6a1870c925a6..60946225699d 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -124,23 +124,6 @@
124#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ 124#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
125#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 125#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
126 126
127#if defined(CONFIG_M5307)
128#define MCFSIM_IMR_MASKALL 0x3fffe /* All SIM intr sources */
129#endif
130
131/*
132 * Macro to set IMR register. It is 32 bits on the 5307.
133 */
134#define mcf_getimr() \
135 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
136
137#define mcf_setimr(imr) \
138 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
139
140#define mcf_getipr() \
141 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
142
143
144/* 127/*
145 * Some symbol defines for the Parallel Port Pin Assignment Register 128 * Some symbol defines for the Parallel Port Pin Assignment Register
146 */ 129 */
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 25194756b432..3c4bd5f08cde 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -97,19 +97,6 @@
97#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 97#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
98 98
99/* 99/*
100 * Macro to set IMR register. It is 32 bits on the 5407.
101 */
102#define mcf_getimr() \
103 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
104
105#define mcf_setimr(imr) \
106 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
107
108#define mcf_getipr() \
109 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
110
111
112/*
113 * Some symbol defines for the Parallel Port Pin Assignment Register 100 * Some symbol defines for the Parallel Port Pin Assignment Register
114 */ 101 */
115#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */ 102#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */
diff --git a/arch/m68k/include/asm/mcfintc.h b/arch/m68k/include/asm/mcfintc.h
index a75a001e773a..213aa6c68abb 100644
--- a/arch/m68k/include/asm/mcfintc.h
+++ b/arch/m68k/include/asm/mcfintc.h
@@ -48,59 +48,32 @@
48#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ 48#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
49 49
50/* 50/*
51 * Bit definitions for the ICR family of registers. 51 * IMR bit position definitions.
52 */ 52 */
53#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ 53#define MCFINTC_EINT1 1 /* External int #1 */
54#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ 54#define MCFINTC_EINT2 2 /* External int #2 */
55#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ 55#define MCFINTC_EINT3 3 /* External int #3 */
56#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ 56#define MCFINTC_EINT4 4 /* External int #4 */
57#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ 57#define MCFINTC_EINT5 5 /* External int #5 */
58#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ 58#define MCFINTC_EINT6 6 /* External int #6 */
59#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ 59#define MCFINTC_EINT7 7 /* External int #7 */
60#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ 60#define MCFINTC_SWT 8 /* Software Watchdog */
61#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ 61#define MCFINTC_TIMER1 9
62#define MCFINTC_TIMER2 10
63#define MCFINTC_I2C 11 /* I2C / MBUS */
64#define MCFINTC_UART0 12
65#define MCFINTC_UART1 13
66#define MCFINTC_DMA0 14
67#define MCFINTC_DMA1 15
68#define MCFINTC_DMA2 16
69#define MCFINTC_DMA3 17
70#define MCFINTC_QSPI 18
62 71
63#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ 72#ifndef __ASSEMBLER__
64#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ 73void mcf_autovector(int irq);
65#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ 74void mcf_setimr(int index);
66#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ 75void mcf_clrimr(int index);
67
68/*
69 * Bit definitions for the Interrupt Mask register (IMR).
70 */
71#define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */
72#define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */
73#define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */
74#define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */
75#define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */
76#define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */
77#define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */
78
79#define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */
80#define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */
81#define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */
82#define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */
83#define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */
84#define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */
85
86#if defined(CONFIG_M5206e)
87#define MCFSIM_IMR_DMA1 0x4000 /* DMA 1 intr */
88#define MCFSIM_IMR_DMA2 0x8000 /* DMA 2 intr */
89#elif defined(CONFIG_M5249) || defined(CONFIG_M5307)
90#define MCFSIM_IMR_DMA0 0x4000 /* DMA 0 intr */
91#define MCFSIM_IMR_DMA1 0x8000 /* DMA 1 intr */
92#define MCFSIM_IMR_DMA2 0x10000 /* DMA 2 intr */
93#define MCFSIM_IMR_DMA3 0x20000 /* DMA 3 intr */
94#endif 76#endif
95 77
96/*
97 * Mask for all of the SIM devices. Some parts have more or less
98 * SIM devices. This is a catchall for the sandard set.
99 */
100#ifndef MCFSIM_IMR_MASKALL
101#define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */
102#endif
103
104
105/****************************************************************************/ 78/****************************************************************************/
106#endif /* mcfintc_h */ 79#endif /* mcfintc_h */
diff --git a/arch/m68knommu/platform/5206/config.c b/arch/m68knommu/platform/5206/config.c
index 481617a23d09..0dce2383320d 100644
--- a/arch/m68knommu/platform/5206/config.c
+++ b/arch/m68knommu/platform/5206/config.c
@@ -49,11 +49,11 @@ static void __init m5206_uart_init_line(int line, int irq)
49 if (line == 0) { 49 if (line == 0) {
50 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 50 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
51 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR); 51 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
52 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); 52 mcf_clrimr(MCFINTC_UART0);
53 } else if (line == 1) { 53 } else if (line == 1) {
54 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 54 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
55 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR); 55 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
56 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); 56 mcf_clrimr(MCFINTC_UART1);
57 } 57 }
58} 58}
59 59
@@ -75,13 +75,13 @@ void mcf_settimericr(unsigned int timer, unsigned int level)
75 75
76 if (timer <= 2) { 76 if (timer <= 2) {
77 switch (timer) { 77 switch (timer) {
78 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break; 78 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
79 default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break; 79 default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
80 } 80 }
81 81
82 icrp = (volatile unsigned char *) (MCF_MBAR + icr); 82 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
83 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3; 83 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
84 mcf_setimr(mcf_getimr() & ~imr); 84 mcf_clrimr(imr);
85 } 85 }
86} 86}
87 87
@@ -100,7 +100,6 @@ void m5206_cpu_reset(void)
100 100
101void __init config_BSP(char *commandp, int size) 101void __init config_BSP(char *commandp, int size)
102{ 102{
103 mcf_setimr(MCFSIM_IMR_MASKALL);
104 mach_reset = m5206_cpu_reset; 103 mach_reset = m5206_cpu_reset;
105} 104}
106 105
diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68knommu/platform/5206e/config.c
index 29e565a44431..08ef7e268989 100644
--- a/arch/m68knommu/platform/5206e/config.c
+++ b/arch/m68knommu/platform/5206e/config.c
@@ -50,11 +50,11 @@ static void __init m5206e_uart_init_line(int line, int irq)
50 if (line == 0) { 50 if (line == 0) {
51 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 51 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
52 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR); 52 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
53 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); 53 mcf_clrimr(MCFINTC_UART0);
54 } else if (line == 1) { 54 } else if (line == 1) {
55 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 55 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
56 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR); 56 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
57 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); 57 mcf_clrimr(MCFINTC_UART1);
58 } 58 }
59} 59}
60 60
@@ -76,13 +76,13 @@ void mcf_settimericr(unsigned int timer, unsigned int level)
76 76
77 if (timer <= 2) { 77 if (timer <= 2) {
78 switch (timer) { 78 switch (timer) {
79 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break; 79 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
80 default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break; 80 default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
81 } 81 }
82 82
83 icrp = (volatile unsigned char *) (MCF_MBAR + icr); 83 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
84 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3; 84 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
85 mcf_setimr(mcf_getimr() & ~imr); 85 mcf_clrimr(imr);
86 } 86 }
87} 87}
88 88
@@ -101,8 +101,6 @@ void m5206e_cpu_reset(void)
101 101
102void __init config_BSP(char *commandp, int size) 102void __init config_BSP(char *commandp, int size)
103{ 103{
104 mcf_setimr(MCFSIM_IMR_MASKALL);
105
106#if defined(CONFIG_NETtel) 104#if defined(CONFIG_NETtel)
107 /* Copy command line from FLASH to local buffer... */ 105 /* Copy command line from FLASH to local buffer... */
108 memcpy(commandp, (char *) 0xf0004000, size); 106 memcpy(commandp, (char *) 0xf0004000, size);
diff --git a/arch/m68knommu/platform/5249/config.c b/arch/m68knommu/platform/5249/config.c
index 365fb6c52700..7261a3d28adc 100644
--- a/arch/m68knommu/platform/5249/config.c
+++ b/arch/m68knommu/platform/5249/config.c
@@ -48,11 +48,11 @@ static void __init m5249_uart_init_line(int line, int irq)
48 if (line == 0) { 48 if (line == 0) {
49 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 49 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
50 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR); 50 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
51 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); 51 mcf_clrimr(MCFINTC_UART0);
52 } else if (line == 1) { 52 } else if (line == 1) {
53 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 53 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
54 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR); 54 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
55 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); 55 mcf_clrimr(MCFINTC_UART1);
56 } 56 }
57} 57}
58 58
@@ -75,13 +75,13 @@ void mcf_settimericr(unsigned int timer, unsigned int level)
75 75
76 if (timer <= 2) { 76 if (timer <= 2) {
77 switch (timer) { 77 switch (timer) {
78 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break; 78 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
79 default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break; 79 default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
80 } 80 }
81 81
82 icrp = (volatile unsigned char *) (MCF_MBAR + icr); 82 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
83 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3; 83 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
84 mcf_setimr(mcf_getimr() & ~imr); 84 mcf_clrimr(imr);
85 } 85 }
86} 86}
87 87
@@ -100,7 +100,6 @@ void m5249_cpu_reset(void)
100 100
101void __init config_BSP(char *commandp, int size) 101void __init config_BSP(char *commandp, int size)
102{ 102{
103 mcf_setimr(MCFSIM_IMR_MASKALL);
104 mach_reset = m5249_cpu_reset; 103 mach_reset = m5249_cpu_reset;
105} 104}
106 105
diff --git a/arch/m68knommu/platform/5307/config.c b/arch/m68knommu/platform/5307/config.c
index 60fe45d51391..3e27d2ec03f0 100644
--- a/arch/m68knommu/platform/5307/config.c
+++ b/arch/m68knommu/platform/5307/config.c
@@ -64,11 +64,11 @@ static void __init m5307_uart_init_line(int line, int irq)
64 if (line == 0) { 64 if (line == 0) {
65 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 65 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
66 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR); 66 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
67 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); 67 mcf_clrimr(MCFINTC_UART0);
68 } else if (line == 1) { 68 } else if (line == 1) {
69 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 69 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
70 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR); 70 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
71 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); 71 mcf_clrimr(MCFINTC_UART1);
72 } 72 }
73} 73}
74 74
@@ -90,13 +90,13 @@ void mcf_settimericr(unsigned int timer, unsigned int level)
90 90
91 if (timer <= 2) { 91 if (timer <= 2) {
92 switch (timer) { 92 switch (timer) {
93 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break; 93 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
94 default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break; 94 default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
95 } 95 }
96 96
97 icrp = (volatile unsigned char *) (MCF_MBAR + icr); 97 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
98 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3; 98 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
99 mcf_setimr(mcf_getimr() & ~imr); 99 mcf_clrimr(imr);
100 } 100 }
101} 101}
102 102
@@ -115,8 +115,6 @@ void m5307_cpu_reset(void)
115 115
116void __init config_BSP(char *commandp, int size) 116void __init config_BSP(char *commandp, int size)
117{ 117{
118 mcf_setimr(MCFSIM_IMR_MASKALL);
119
120#if defined(CONFIG_NETtel) || \ 118#if defined(CONFIG_NETtel) || \
121 defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA) 119 defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
122 /* Copy command line from FLASH to local buffer... */ 120 /* Copy command line from FLASH to local buffer... */
diff --git a/arch/m68knommu/platform/5407/config.c b/arch/m68knommu/platform/5407/config.c
index 1e8ef74ea156..8aa94837bbc3 100644
--- a/arch/m68knommu/platform/5407/config.c
+++ b/arch/m68knommu/platform/5407/config.c
@@ -55,11 +55,11 @@ static void __init m5407_uart_init_line(int line, int irq)
55 if (line == 0) { 55 if (line == 0) {
56 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 56 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
57 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR); 57 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
58 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); 58 mcf_clrimr(MCFINTC_UART0);
59 } else if (line == 1) { 59 } else if (line == 1) {
60 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 60 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
61 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR); 61 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
62 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); 62 mcf_clrimr(MCFINTC_UART1);
63 } 63 }
64} 64}
65 65
@@ -81,13 +81,13 @@ void mcf_settimericr(unsigned int timer, unsigned int level)
81 81
82 if (timer <= 2) { 82 if (timer <= 2) {
83 switch (timer) { 83 switch (timer) {
84 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break; 84 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
85 default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break; 85 default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
86 } 86 }
87 87
88 icrp = (volatile unsigned char *) (MCF_MBAR + icr); 88 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
89 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3; 89 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
90 mcf_setimr(mcf_getimr() & ~imr); 90 mcf_clrimr(imr);
91 } 91 }
92} 92}
93 93
@@ -106,8 +106,6 @@ void m5407_cpu_reset(void)
106 106
107void __init config_BSP(char *commandp, int size) 107void __init config_BSP(char *commandp, int size)
108{ 108{
109 mcf_setimr(MCFSIM_IMR_MASKALL);
110
111#if defined(CONFIG_CLEOPATRA) 109#if defined(CONFIG_CLEOPATRA)
112 /* Different timer setup - to prevent device clash */ 110 /* Different timer setup - to prevent device clash */
113 mcf_timervector = 30; 111 mcf_timervector = 30;
diff --git a/arch/m68knommu/platform/coldfire/intc.c b/arch/m68knommu/platform/coldfire/intc.c
index f7a61346ee25..88bffac50c67 100644
--- a/arch/m68knommu/platform/coldfire/intc.c
+++ b/arch/m68knommu/platform/coldfire/intc.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * intc.c 2 * intc.c -- support for the old ColdFire interrupt controller
3 * 3 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> 4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 * 5 *
@@ -27,6 +27,62 @@
27#define EIRQ7 31 27#define EIRQ7 31
28 28
29/* 29/*
30 * In the early version 2 core ColdFire parts the IMR register was 16 bits
31 * in size. Version 3 (and later version 2) core parts have a 32 bit
32 * sized IMR register. Provide some size independant methods to access the
33 * IMR register.
34 */
35#ifdef MCFSIM_IMR_IS_16BITS
36
37void mcf_setimr(int index)
38{
39 u16 imr;
40 imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
41 __raw_writew(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
42}
43
44void mcf_clrimr(int index)
45{
46 u16 imr;
47 imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
48 __raw_writew(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
49}
50
51void mcf_maskimr(unsigned int mask)
52{
53 u16 imr;
54 imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
55 imr |= mask;
56 __raw_writew(imr, MCF_MBAR + MCFSIM_IMR);
57}
58
59#else
60
61void mcf_setimr(int index)
62{
63 u32 imr;
64 imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
65 __raw_writel(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
66}
67
68void mcf_clrimr(int index)
69{
70 u32 imr;
71 imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
72 __raw_writel(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
73}
74
75void mcf_maskimr(unsigned int mask)
76{
77 u32 imr;
78 imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
79 imr |= mask;
80 __raw_writel(imr, MCF_MBAR + MCFSIM_IMR);
81}
82
83#endif
84
85/*
30 * Interrupts can be "vectored" on the ColdFire cores that support this old 86 * Interrupts can be "vectored" on the ColdFire cores that support this old
31 * interrupt controller. That is, the device raising the interrupt can also 87 * interrupt controller. That is, the device raising the interrupt can also
32 * supply the vector number to interrupt through. The AVR register of the 88 * supply the vector number to interrupt through. The AVR register of the
@@ -70,6 +126,7 @@ void __init init_IRQ(void)
70 int irq; 126 int irq;
71 127
72 init_vectors(); 128 init_vectors();
129 mcf_maskimr(0xffffffff);
73 130
74 for (irq = 0; (irq < NR_IRQS); irq++) { 131 for (irq = 0; (irq < NR_IRQS); irq++) {
75 irq_desc[irq].status = IRQ_DISABLED; 132 irq_desc[irq].status = IRQ_DISABLED;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 18:13:49 -0500