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-rw-r--r--arch/arm/Kconfig13
-rw-r--r--arch/arm/kernel/calls.S13
-rw-r--r--arch/arm/kernel/head.S19
-rw-r--r--arch/arm/kernel/setup.c3
-rw-r--r--arch/arm/mach-at91rm9200/at91sam9260_devices.c1
-rw-r--r--arch/arm/mach-at91rm9200/board-sam9260ek.c1
-rw-r--r--arch/arm/mach-imx/Makefile2
-rw-r--r--arch/arm/mach-imx/cpufreq.c287
-rw-r--r--arch/arm/mach-netx/time.c42
-rw-r--r--arch/arm/mach-pxa/time.c45
-rw-r--r--arch/arm/mach-pxa/trizeps4.c5
-rw-r--r--arch/arm/mach-sa1100/jornada720.c229
-rw-r--r--arch/arm/mm/consistent.c2
-rw-r--r--arch/arm/mm/copypage-v4mc.c2
-rw-r--r--arch/arm/mm/copypage-v6.c6
-rw-r--r--arch/arm/mm/copypage-xscale.c2
-rw-r--r--arch/arm/mm/fault-armv.c2
-rw-r--r--arch/arm/mm/flush.c2
-rw-r--r--arch/arm/mm/ioremap.c100
-rw-r--r--arch/arm/mm/mmu.c8
-rw-r--r--arch/arm/mm/pgd.c2
-rw-r--r--arch/arm/mm/proc-arm1020.S4
-rw-r--r--arch/arm/mm/proc-arm1020e.S4
-rw-r--r--arch/arm/mm/proc-arm1022.S6
-rw-r--r--arch/arm/mm/proc-arm1026.S6
-rw-r--r--arch/arm/mm/proc-arm6_7.S10
-rw-r--r--arch/arm/mm/proc-arm720.S6
-rw-r--r--arch/arm/mm/proc-arm920.S6
-rw-r--r--arch/arm/mm/proc-arm922.S6
-rw-r--r--arch/arm/mm/proc-arm925.S6
-rw-r--r--arch/arm/mm/proc-arm926.S8
-rw-r--r--arch/arm/mm/proc-sa110.S6
-rw-r--r--arch/arm/mm/proc-sa1100.S6
-rw-r--r--arch/arm/mm/proc-syms.c2
-rw-r--r--arch/arm/mm/proc-v6.S39
-rw-r--r--arch/arm/mm/proc-xsc3.S6
-rw-r--r--arch/arm/mm/proc-xscale.S6
-rw-r--r--arch/arm/vfp/vfpmodule.c26
-rw-r--r--include/asm-arm/arch-imx/imx-regs.h10
-rw-r--r--include/asm-arm/arch-s3c2410/regs-udc.h7
-rw-r--r--include/asm-arm/cpu-multi32.h7
-rw-r--r--include/asm-arm/cpu-single.h4
-rw-r--r--include/asm-arm/pgtable.h11
-rw-r--r--include/asm-arm/processor.h16
-rw-r--r--include/asm-arm/system.h63
-rw-r--r--include/asm-arm/unistd.h13
46 files changed, 815 insertions, 255 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index aa1d400d721a..6783c2e5512d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -740,7 +740,7 @@ config XIP_PHYS_ADDR
740 740
741endmenu 741endmenu
742 742
743if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP) 743if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX )
744 744
745menu "CPU Frequency scaling" 745menu "CPU Frequency scaling"
746 746
@@ -767,6 +767,15 @@ config CPU_FREQ_INTEGRATOR
767 767
768 If in doubt, say Y. 768 If in doubt, say Y.
769 769
770config CPU_FREQ_IMX
771 tristate "CPUfreq driver for i.MX CPUs"
772 depends on ARCH_IMX && CPU_FREQ
773 default n
774 help
775 This enables the CPUfreq driver for i.MX CPUs.
776
777 If in doubt, say N.
778
770endmenu 779endmenu
771 780
772endif 781endif
@@ -945,6 +954,8 @@ source "drivers/video/Kconfig"
945 954
946source "sound/Kconfig" 955source "sound/Kconfig"
947 956
957source "drivers/hid/Kconfig"
958
948source "drivers/usb/Kconfig" 959source "drivers/usb/Kconfig"
949 960
950source "drivers/mmc/Kconfig" 961source "drivers/mmc/Kconfig"
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index 3173924a9b60..e8f74363328c 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -331,6 +331,19 @@
331 CALL(sys_mbind) 331 CALL(sys_mbind)
332/* 320 */ CALL(sys_get_mempolicy) 332/* 320 */ CALL(sys_get_mempolicy)
333 CALL(sys_set_mempolicy) 333 CALL(sys_set_mempolicy)
334 CALL(sys_openat)
335 CALL(sys_mkdirat)
336 CALL(sys_mknodat)
337/* 325 */ CALL(sys_fchownat)
338 CALL(sys_futimesat)
339 CALL(sys_fstatat64)
340 CALL(sys_unlinkat)
341 CALL(sys_renameat)
342/* 330 */ CALL(sys_linkat)
343 CALL(sys_symlinkat)
344 CALL(sys_readlinkat)
345 CALL(sys_fchmodat)
346 CALL(sys_faccessat)
334#ifndef syscalls_counted 347#ifndef syscalls_counted
335.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls 348.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
336#define syscalls_counted 349#define syscalls_counted
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index bda0748ffb00..d994561816a1 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -22,30 +22,31 @@
22#include <asm/thread_info.h> 22#include <asm/thread_info.h>
23#include <asm/system.h> 23#include <asm/system.h>
24 24
25#define KERNEL_RAM_ADDR (PAGE_OFFSET + TEXT_OFFSET) 25#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
26#define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET)
26 27
27/* 28/*
28 * swapper_pg_dir is the virtual address of the initial page table. 29 * swapper_pg_dir is the virtual address of the initial page table.
29 * We place the page tables 16K below KERNEL_RAM_ADDR. Therefore, we must 30 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
30 * make sure that KERNEL_RAM_ADDR is correctly set. Currently, we expect 31 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
31 * the least significant 16 bits to be 0x8000, but we could probably 32 * the least significant 16 bits to be 0x8000, but we could probably
32 * relax this restriction to KERNEL_RAM_ADDR >= PAGE_OFFSET + 0x4000. 33 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
33 */ 34 */
34#if (KERNEL_RAM_ADDR & 0xffff) != 0x8000 35#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
35#error KERNEL_RAM_ADDR must start at 0xXXXX8000 36#error KERNEL_RAM_VADDR must start at 0xXXXX8000
36#endif 37#endif
37 38
38 .globl swapper_pg_dir 39 .globl swapper_pg_dir
39 .equ swapper_pg_dir, KERNEL_RAM_ADDR - 0x4000 40 .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
40 41
41 .macro pgtbl, rd 42 .macro pgtbl, rd
42 ldr \rd, =(__virt_to_phys(KERNEL_RAM_ADDR - 0x4000)) 43 ldr \rd, =(KERNEL_RAM_PADDR - 0x4000)
43 .endm 44 .endm
44 45
45#ifdef CONFIG_XIP_KERNEL 46#ifdef CONFIG_XIP_KERNEL
46#define TEXTADDR XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 47#define TEXTADDR XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
47#else 48#else
48#define TEXTADDR KERNEL_RAM_ADDR 49#define TEXTADDR KERNEL_RAM_VADDR
49#endif 50#endif
50 51
51/* 52/*
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 238dd9b6db84..cf2bd4242803 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -354,9 +354,6 @@ static void __init setup_processor(void)
354#ifndef CONFIG_ARM_THUMB 354#ifndef CONFIG_ARM_THUMB
355 elf_hwcap &= ~HWCAP_THUMB; 355 elf_hwcap &= ~HWCAP_THUMB;
356#endif 356#endif
357#ifndef CONFIG_VFP
358 elf_hwcap &= ~HWCAP_VFP;
359#endif
360 357
361 cpu_proc_init(); 358 cpu_proc_init();
362} 359}
diff --git a/arch/arm/mach-at91rm9200/at91sam9260_devices.c b/arch/arm/mach-at91rm9200/at91sam9260_devices.c
index a6c596dc4516..f42d3a40ec3c 100644
--- a/arch/arm/mach-at91rm9200/at91sam9260_devices.c
+++ b/arch/arm/mach-at91rm9200/at91sam9260_devices.c
@@ -18,6 +18,7 @@
18#include <asm/arch/gpio.h> 18#include <asm/arch/gpio.h>
19#include <asm/arch/at91sam9260.h> 19#include <asm/arch/at91sam9260.h>
20#include <asm/arch/at91sam926x_mc.h> 20#include <asm/arch/at91sam926x_mc.h>
21#include <asm/arch/at91sam9260_matrix.h>
21 22
22#include "generic.h" 23#include "generic.h"
23 24
diff --git a/arch/arm/mach-at91rm9200/board-sam9260ek.c b/arch/arm/mach-at91rm9200/board-sam9260ek.c
index ffca9bdec37b..da5d58ac870b 100644
--- a/arch/arm/mach-at91rm9200/board-sam9260ek.c
+++ b/arch/arm/mach-at91rm9200/board-sam9260ek.c
@@ -119,6 +119,7 @@ static struct spi_board_info ek_spi_devices[] = {
119 * MACB Ethernet device 119 * MACB Ethernet device
120 */ 120 */
121static struct __initdata eth_platform_data ek_macb_data = { 121static struct __initdata eth_platform_data ek_macb_data = {
122 .phy_irq_pin = AT91_PIN_PA7,
122 .is_rmii = 1, 123 .is_rmii = 1,
123}; 124};
124 125
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 0b27d79f2efd..02272aa36e90 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -9,6 +9,8 @@
9 9
10obj-y += irq.o time.o dma.o generic.o 10obj-y += irq.o time.o dma.o generic.o
11 11
12obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o
13
12# Specific board support 14# Specific board support
13obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o 15obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o
14 16
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
new file mode 100644
index 000000000000..ac5f99895660
--- /dev/null
+++ b/arch/arm/mach-imx/cpufreq.c
@@ -0,0 +1,287 @@
1/*
2 * cpu.c: clock scaling for the iMX
3 *
4 * Copyright (C) 2000 2001, The Delft University of Technology
5 * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
6 * Copyright (C) 2006 Inky Lung <ilung@cwlinux.com>
7 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
8 *
9 * Based on SA1100 version written by:
10 * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version
11 * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 *
27 */
28
29/*#define DEBUG*/
30
31#include <linux/kernel.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/cpufreq.h>
35#include <asm/system.h>
36
37#include <asm/hardware.h>
38
39#include "generic.h"
40
41#ifndef __val2mfld
42#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
43#endif
44#ifndef __mfld2val
45#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
46#endif
47
48#define CR_920T_CLOCK_MODE 0xC0000000
49#define CR_920T_FASTBUS_MODE 0x00000000
50#define CR_920T_ASYNC_MODE 0xC0000000
51
52static u32 mpctl0_at_boot;
53
54static void imx_set_async_mode(void)
55{
56 adjust_cr(CR_920T_CLOCK_MODE, CR_920T_ASYNC_MODE);
57}
58
59static void imx_set_fastbus_mode(void)
60{
61 adjust_cr(CR_920T_CLOCK_MODE, CR_920T_FASTBUS_MODE);
62}
63
64static void imx_set_mpctl0(u32 mpctl0)
65{
66 unsigned long flags;
67
68 if (mpctl0 == 0) {
69 local_irq_save(flags);
70 CSCR &= ~CSCR_MPEN;
71 local_irq_restore(flags);
72 return;
73 }
74
75 local_irq_save(flags);
76 MPCTL0 = mpctl0;
77 CSCR |= CSCR_MPEN;
78 local_irq_restore(flags);
79}
80
81/**
82 * imx_compute_mpctl - compute new PLL parameters
83 * @new_mpctl: pointer to location assigned by new PLL control register value
84 * @cur_mpctl: current PLL control register parameters
85 * @freq: required frequency in Hz
86 * @relation: is one of %CPUFREQ_RELATION_L (supremum)
87 * and %CPUFREQ_RELATION_H (infimum)
88 */
89long imx_compute_mpctl(u32 *new_mpctl, u32 cur_mpctl, unsigned long freq, int relation)
90{
91 u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
92 u32 mfi;
93 u32 mfn;
94 u32 mfd;
95 u32 pd;
96 unsigned long long ll;
97 long l;
98 long quot;
99
100 /* Fdppl=2*Fref*(MFI+MFN/(MFD+1))/(PD+1) */
101 /* PD=<0,15>, MFD=<1,1023>, MFI=<5,15> MFN=<0,1022> */
102
103 if (cur_mpctl) {
104 mfd = ((cur_mpctl >> 16) & 0x3ff) + 1;
105 pd = ((cur_mpctl >> 26) & 0xf) + 1;
106 } else {
107 pd=2; mfd=313;
108 }
109
110 /* pd=2; mfd=313; mfi=8; mfn=183; */
111 /* (MFI+MFN/(MFD)) = Fdppl / (2*Fref) * (PD); */
112
113 quot = (f_ref + (1 << 9)) >> 10;
114 l = (freq * pd + quot) / (2 * quot);
115 mfi = l >> 10;
116 mfn = ((l & ((1 << 10) - 1)) * mfd + (1 << 9)) >> 10;
117
118 mfd -= 1;
119 pd -= 1;
120
121 *new_mpctl = ((mfi & 0xf) << 10) | (mfn & 0x3ff) | ((mfd & 0x3ff) << 16)
122 | ((pd & 0xf) << 26);
123
124 ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) );
125 quot = (pd+1) * (1<<16);
126 ll += quot / 2;
127 do_div(ll, quot);
128 freq = ll;
129
130 pr_debug(KERN_DEBUG "imx: new PLL parameters pd=%d mfd=%d mfi=%d mfn=%d, freq=%ld\n",
131 pd, mfd, mfi, mfn, freq);
132
133 return freq;
134}
135
136
137static int imx_verify_speed(struct cpufreq_policy *policy)
138{
139 if (policy->cpu != 0)
140 return -EINVAL;
141
142 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
143
144 return 0;
145}
146
147static unsigned int imx_get_speed(unsigned int cpu)
148{
149 unsigned int freq;
150 unsigned int cr;
151 unsigned int cscr;
152 unsigned int bclk_div;
153
154 if (cpu)
155 return 0;
156
157 cscr = CSCR;
158 bclk_div = __mfld2val(CSCR_BCLK_DIV, cscr) + 1;
159 cr = get_cr();
160
161 if((cr & CR_920T_CLOCK_MODE) == CR_920T_FASTBUS_MODE) {
162 freq = imx_get_system_clk();
163 freq = (freq + bclk_div/2) / bclk_div;
164 } else {
165 freq = imx_get_mcu_clk();
166 if (cscr & CSCR_MPU_PRESC)
167 freq /= 2;
168 }
169
170 freq = (freq + 500) / 1000;
171
172 return freq;
173}
174
175static int imx_set_target(struct cpufreq_policy *policy,
176 unsigned int target_freq,
177 unsigned int relation)
178{
179 struct cpufreq_freqs freqs;
180 u32 mpctl0 = 0;
181 u32 cscr;
182 unsigned long flags;
183 long freq;
184 long sysclk;
185 unsigned int bclk_div = 1;
186
187 freq = target_freq * 1000;
188
189 pr_debug(KERN_DEBUG "imx: requested frequency %ld Hz, mpctl0 at boot 0x%08x\n",
190 freq, mpctl0_at_boot);
191
192 sysclk = imx_get_system_clk();
193
194 if (freq > sysclk + 1000000) {
195 freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, freq, relation);
196 if (freq < 0) {
197 printk(KERN_WARNING "imx: target frequency %ld Hz cannot be set\n", freq);
198 return -EINVAL;
199 }
200 } else {
201 if(freq + 1000 < sysclk) {
202 if (relation == CPUFREQ_RELATION_L)
203 bclk_div = (sysclk - 1000) / freq;
204 else
205 bclk_div = (sysclk + freq + 1000) / freq;
206
207 if(bclk_div > 16)
208 bclk_div = 16;
209 }
210 freq = (sysclk + bclk_div / 2) / bclk_div;
211 }
212
213 freqs.old = imx_get_speed(0);
214 freqs.new = (freq + 500) / 1000;
215 freqs.cpu = 0;
216 freqs.flags = 0;
217
218 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
219
220 local_irq_save(flags);
221
222 imx_set_fastbus_mode();
223
224 imx_set_mpctl0(mpctl0);
225
226 cscr = CSCR;
227 cscr &= ~CSCR_BCLK_DIV;
228 cscr |= __val2mfld(CSCR_BCLK_DIV, bclk_div - 1);
229 CSCR = cscr;
230
231 if(mpctl0) {
232 CSCR |= CSCR_MPLL_RESTART;
233
234 /* Wait until MPLL is stablized */
235 while( CSCR & CSCR_MPLL_RESTART );
236
237 imx_set_async_mode();
238 }
239
240 local_irq_restore(flags);
241
242 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
243
244 pr_debug(KERN_INFO "imx: set frequency %ld Hz, running from %s\n",
245 freq, mpctl0? "MPLL": "SPLL");
246
247 return 0;
248}
249
250static int __init imx_cpufreq_driver_init(struct cpufreq_policy *policy)
251{
252 printk(KERN_INFO "i.MX cpu freq change driver v1.0\n");
253
254 if (policy->cpu != 0)
255 return -EINVAL;
256
257 policy->cur = policy->min = policy->max = imx_get_speed(0);
258 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
259 policy->cpuinfo.min_freq = 8000;
260 policy->cpuinfo.max_freq = 200000;
261 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
262 return 0;
263}
264
265static struct cpufreq_driver imx_driver = {
266 .flags = CPUFREQ_STICKY,
267 .verify = imx_verify_speed,
268 .target = imx_set_target,
269 .get = imx_get_speed,
270 .init = imx_cpufreq_driver_init,
271 .name = "imx",
272};
273
274static int __init imx_cpufreq_init(void)
275{
276
277 mpctl0_at_boot = 0;
278
279 if((CSCR & CSCR_MPEN) &&
280 ((get_cr() & CR_920T_CLOCK_MODE) != CR_920T_FASTBUS_MODE))
281 mpctl0_at_boot = MPCTL0;
282
283 return cpufreq_register_driver(&imx_driver);
284}
285
286arch_initcall(imx_cpufreq_init);
287
diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c
index 0993336c0b55..5773b55ef4a6 100644
--- a/arch/arm/mach-netx/time.c
+++ b/arch/arm/mach-netx/time.c
@@ -19,6 +19,8 @@
19 19
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/clocksource.h>
22 24
23#include <asm/hardware.h> 25#include <asm/hardware.h>
24#include <asm/io.h> 26#include <asm/io.h>
@@ -26,15 +28,6 @@
26#include <asm/arch/netx-regs.h> 28#include <asm/arch/netx-regs.h>
27 29
28/* 30/*
29 * Returns number of us since last clock interrupt. Note that interrupts
30 * will have been disabled by do_gettimeoffset()
31 */
32static unsigned long netx_gettimeoffset(void)
33{
34 return readl(NETX_GPIO_COUNTER_CURRENT(0)) / 100;
35}
36
37/*
38 * IRQ handler for the timer 31 * IRQ handler for the timer
39 */ 32 */
40static irqreturn_t 33static irqreturn_t
@@ -43,6 +36,7 @@ netx_timer_interrupt(int irq, void *dev_id)
43 write_seqlock(&xtime_lock); 36 write_seqlock(&xtime_lock);
44 37
45 timer_tick(); 38 timer_tick();
39
46 write_sequnlock(&xtime_lock); 40 write_sequnlock(&xtime_lock);
47 41
48 /* acknowledge interrupt */ 42 /* acknowledge interrupt */
@@ -51,13 +45,26 @@ netx_timer_interrupt(int irq, void *dev_id)
51 return IRQ_HANDLED; 45 return IRQ_HANDLED;
52} 46}
53 47
54
55static struct irqaction netx_timer_irq = { 48static struct irqaction netx_timer_irq = {
56 .name = "NetX Timer Tick", 49 .name = "NetX Timer Tick",
57 .flags = IRQF_DISABLED | IRQF_TIMER, 50 .flags = IRQF_DISABLED | IRQF_TIMER,
58 .handler = netx_timer_interrupt, 51 .handler = netx_timer_interrupt,
59}; 52};
60 53
54cycle_t netx_get_cycles(void)
55{
56 return readl(NETX_GPIO_COUNTER_CURRENT(1));
57}
58
59static struct clocksource clocksource_netx = {
60 .name = "netx_timer",
61 .rating = 200,
62 .read = netx_get_cycles,
63 .mask = CLOCKSOURCE_MASK(32),
64 .shift = 20,
65 .is_continuous = 1,
66};
67
61/* 68/*
62 * Set up timer interrupt 69 * Set up timer interrupt
63 */ 70 */
@@ -80,9 +87,20 @@ static void __init netx_timer_init(void)
80 NETX_GPIO_COUNTER_CTRL(0)); 87 NETX_GPIO_COUNTER_CTRL(0));
81 88
82 setup_irq(NETX_IRQ_TIMER0, &netx_timer_irq); 89 setup_irq(NETX_IRQ_TIMER0, &netx_timer_irq);
90
91 /* Setup timer one for clocksource */
92 writel(0, NETX_GPIO_COUNTER_CTRL(1));
93 writel(0, NETX_GPIO_COUNTER_CURRENT(1));
94 writel(0xFFFFFFFF, NETX_GPIO_COUNTER_MAX(1));
95
96 writel(NETX_GPIO_COUNTER_CTRL_RUN,
97 NETX_GPIO_COUNTER_CTRL(1));
98
99 clocksource_netx.mult =
100 clocksource_hz2mult(CLOCK_TICK_RATE, clocksource_netx.shift);
101 clocksource_register(&clocksource_netx);
83} 102}
84 103
85struct sys_timer netx_timer = { 104struct sys_timer netx_timer = {
86 .init = netx_timer_init, 105 .init = netx_timer_init,
87 .offset = netx_gettimeoffset,
88}; 106};
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index b91466861029..3775b8f38429 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -18,6 +18,7 @@
18#include <linux/signal.h> 18#include <linux/signal.h>
19#include <linux/errno.h> 19#include <linux/errno.h>
20#include <linux/sched.h> 20#include <linux/sched.h>
21#include <linux/clocksource.h>
21 22
22#include <asm/system.h> 23#include <asm/system.h>
23#include <asm/hardware.h> 24#include <asm/hardware.h>
@@ -48,27 +49,6 @@ static int pxa_set_rtc(void)
48 return 0; 49 return 0;
49} 50}
50 51
51/* IRQs are disabled before entering here from do_gettimeofday() */
52static unsigned long pxa_gettimeoffset (void)
53{
54 long ticks_to_match, elapsed, usec;
55
56 /* Get ticks before next timer match */
57 ticks_to_match = OSMR0 - OSCR;
58
59 /* We need elapsed ticks since last match */
60 elapsed = LATCH - ticks_to_match;
61
62 /* don't get fooled by the workaround in pxa_timer_interrupt() */
63 if (elapsed <= 0)
64 return 0;
65
66 /* Now convert them to usec */
67 usec = (unsigned long)(elapsed * (tick_nsec / 1000))/LATCH;
68
69 return usec;
70}
71
72#ifdef CONFIG_NO_IDLE_HZ 52#ifdef CONFIG_NO_IDLE_HZ
73static unsigned long initial_match; 53static unsigned long initial_match;
74static int match_posponed; 54static int match_posponed;
@@ -121,6 +101,20 @@ static struct irqaction pxa_timer_irq = {
121 .handler = pxa_timer_interrupt, 101 .handler = pxa_timer_interrupt,
122}; 102};
123 103
104cycle_t pxa_get_cycles(void)
105{
106 return OSCR;
107}
108
109static struct clocksource clocksource_pxa = {
110 .name = "pxa_timer",
111 .rating = 200,
112 .read = pxa_get_cycles,
113 .mask = CLOCKSOURCE_MASK(32),
114 .shift = 20,
115 .is_continuous = 1,
116};
117
124static void __init pxa_timer_init(void) 118static void __init pxa_timer_init(void)
125{ 119{
126 struct timespec tv; 120 struct timespec tv;
@@ -139,6 +133,14 @@ static void __init pxa_timer_init(void)
139 OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */ 133 OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */
140 OSMR0 = OSCR + LATCH; /* set initial match */ 134 OSMR0 = OSCR + LATCH; /* set initial match */
141 local_irq_restore(flags); 135 local_irq_restore(flags);
136
137 /* on PXA OSCR runs continiously and is not written to, so we can use it
138 * as clock source directly.
139 */
140 clocksource_pxa.mult =
141 clocksource_hz2mult(CLOCK_TICK_RATE, clocksource_pxa.shift);
142 clocksource_register(&clocksource_pxa);
143
142} 144}
143 145
144#ifdef CONFIG_NO_IDLE_HZ 146#ifdef CONFIG_NO_IDLE_HZ
@@ -211,7 +213,6 @@ struct sys_timer pxa_timer = {
211 .init = pxa_timer_init, 213 .init = pxa_timer_init,
212 .suspend = pxa_timer_suspend, 214 .suspend = pxa_timer_suspend,
213 .resume = pxa_timer_resume, 215 .resume = pxa_timer_resume,
214 .offset = pxa_gettimeoffset,
215#ifdef CONFIG_NO_IDLE_HZ 216#ifdef CONFIG_NO_IDLE_HZ
216 .dyn_tick = &pxa_dyn_tick, 217 .dyn_tick = &pxa_dyn_tick,
217#endif 218#endif
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index c1827d021ba8..119c64b7223f 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -393,10 +393,6 @@ static struct pxafb_mach_info sharp_lcd = {
393 .pxafb_backlight_power = board_backlight_power, 393 .pxafb_backlight_power = board_backlight_power,
394}; 394};
395 395
396static void __init trizeps4_fixup(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi)
397{
398}
399
400static void __init trizeps4_init(void) 396static void __init trizeps4_init(void)
401{ 397{
402 platform_add_devices(trizeps4_devices, ARRAY_SIZE(trizeps4_devices)); 398 platform_add_devices(trizeps4_devices, ARRAY_SIZE(trizeps4_devices));
@@ -469,7 +465,6 @@ MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
469 .phys_io = 0x40000000, 465 .phys_io = 0x40000000,
470 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, 466 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
471 .boot_params = TRIZEPS4_SDRAM_BASE + 0x100, 467 .boot_params = TRIZEPS4_SDRAM_BASE + 0x100,
472 .fixup = trizeps4_fixup,
473 .init_machine = trizeps4_init, 468 .init_machine = trizeps4_init,
474 .map_io = trizeps4_map_io, 469 .map_io = trizeps4_map_io,
475 .init_irq = pxa_init_irq, 470 .init_irq = pxa_init_irq,
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
index 17f5a43acdb7..54ecdaa373d6 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -1,5 +1,15 @@
1/* 1/*
2 * linux/arch/arm/mach-sa1100/jornada720.c 2 * linux/arch/arm/mach-sa1100/jornada720.c
3 *
4 * HP Jornada720 init code
5 *
6 * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
7 * Copyright (C) 2005 Michael Gernoth <michael@gernoth.net>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
3 */ 13 */
4 14
5#include <linux/init.h> 15#include <linux/init.h>
@@ -10,13 +20,13 @@
10#include <linux/ioport.h> 20#include <linux/ioport.h>
11#include <linux/mtd/mtd.h> 21#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h> 22#include <linux/mtd/partitions.h>
23#include <video/s1d13xxxfb.h>
13 24
14#include <asm/hardware.h> 25#include <asm/hardware.h>
15#include <asm/hardware/sa1111.h> 26#include <asm/hardware/sa1111.h>
16#include <asm/irq.h> 27#include <asm/irq.h>
17#include <asm/mach-types.h> 28#include <asm/mach-types.h>
18#include <asm/setup.h> 29#include <asm/setup.h>
19
20#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
21#include <asm/mach/flash.h> 31#include <asm/mach/flash.h>
22#include <asm/mach/map.h> 32#include <asm/mach/map.h>
@@ -24,13 +34,170 @@
24 34
25#include "generic.h" 35#include "generic.h"
26 36
37/*
38 * HP Documentation referred in this file:
39 * http://www.jlime.com/downloads/development/docs/jornada7xx/jornada720.txt
40 */
41
42/* line 110 of HP's doc */
43#define TUCR_VAL 0x20000400
44
45/* memory space (line 52 of HP's doc) */
46#define SA1111REGSTART 0x40000000
47#define SA1111REGLEN 0x00001fff
48#define EPSONREGSTART 0x48000000
49#define EPSONREGLEN 0x00100000
50#define EPSONFBSTART 0x48200000
51/* 512kB framebuffer */
52#define EPSONFBLEN 512*1024
53
54static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
55 /* line 344 of HP's doc */
56 {0x0001,0x00}, // Miscellaneous Register
57 {0x01FC,0x00}, // Display Mode Register
58 {0x0004,0x00}, // General IO Pins Configuration Register 0
59 {0x0005,0x00}, // General IO Pins Configuration Register 1
60 {0x0008,0x00}, // General IO Pins Control Register 0
61 {0x0009,0x00}, // General IO Pins Control Register 1
62 {0x0010,0x01}, // Memory Clock Configuration Register
63 {0x0014,0x11}, // LCD Pixel Clock Configuration Register
64 {0x0018,0x01}, // CRT/TV Pixel Clock Configuration Register
65 {0x001C,0x01}, // MediaPlug Clock Configuration Register
66 {0x001E,0x01}, // CPU To Memory Wait State Select Register
67 {0x0020,0x00}, // Memory Configuration Register
68 {0x0021,0x45}, // DRAM Refresh Rate Register
69 {0x002A,0x01}, // DRAM Timings Control Register 0
70 {0x002B,0x03}, // DRAM Timings Control Register 1
71 {0x0030,0x1c}, // Panel Type Register
72 {0x0031,0x00}, // MOD Rate Register
73 {0x0032,0x4F}, // LCD Horizontal Display Width Register
74 {0x0034,0x07}, // LCD Horizontal Non-Display Period Register
75 {0x0035,0x01}, // TFT FPLINE Start Position Register
76 {0x0036,0x0B}, // TFT FPLINE Pulse Width Register
77 {0x0038,0xEF}, // LCD Vertical Display Height Register 0
78 {0x0039,0x00}, // LCD Vertical Display Height Register 1
79 {0x003A,0x13}, // LCD Vertical Non-Display Period Register
80 {0x003B,0x0B}, // TFT FPFRAME Start Position Register
81 {0x003C,0x01}, // TFT FPFRAME Pulse Width Register
82 {0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
83 {0x0041,0x00}, // LCD Miscellaneous Register
84 {0x0042,0x00}, // LCD Display Start Address Register 0
85 {0x0043,0x00}, // LCD Display Start Address Register 1
86 {0x0044,0x00}, // LCD Display Start Address Register 2
87 {0x0046,0x80}, // LCD Memory Address Offset Register 0
88 {0x0047,0x02}, // LCD Memory Address Offset Register 1
89 {0x0048,0x00}, // LCD Pixel Panning Register
90 {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
91 {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
92 {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
93 {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
94 {0x0053,0x01}, // CRT/TV HRTC Start Position Register
95 {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
96 {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
97 {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
98 {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
99 {0x0059,0x09}, // CRT/TV VRTC Start Position Register
100 {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
101 {0x005B,0x10}, // TV Output Control Register
102 {0x0060,0x03}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
103 {0x0062,0x00}, // CRT/TV Display Start Address Register 0
104 {0x0063,0x00}, // CRT/TV Display Start Address Register 1
105 {0x0064,0x00}, // CRT/TV Display Start Address Register 2
106 {0x0066,0x40}, // CRT/TV Memory Address Offset Register 0
107 {0x0067,0x01}, // CRT/TV Memory Address Offset Register 1
108 {0x0068,0x00}, // CRT/TV Pixel Panning Register
109 {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
110 {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
111 {0x0070,0x00}, // LCD Ink/Cursor Control Register
112 {0x0071,0x01}, // LCD Ink/Cursor Start Address Register
113 {0x0072,0x00}, // LCD Cursor X Position Register 0
114 {0x0073,0x00}, // LCD Cursor X Position Register 1
115 {0x0074,0x00}, // LCD Cursor Y Position Register 0
116 {0x0075,0x00}, // LCD Cursor Y Position Register 1
117 {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
118 {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
119 {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
120 {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
121 {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
122 {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
123 {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
124 {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
125 {0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register
126 {0x0082,0x00}, // CRT/TV Cursor X Position Register 0
127 {0x0083,0x00}, // CRT/TV Cursor X Position Register 1
128 {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
129 {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
130 {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
131 {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
132 {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
133 {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
134 {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
135 {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
136 {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
137 {0x0100,0x00}, // BitBlt Control Register 0
138 {0x0101,0x00}, // BitBlt Control Register 1
139 {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
140 {0x0103,0x00}, // BitBlt Operation Register
141 {0x0104,0x00}, // BitBlt Source Start Address Register 0
142 {0x0105,0x00}, // BitBlt Source Start Address Register 1
143 {0x0106,0x00}, // BitBlt Source Start Address Register 2
144 {0x0108,0x00}, // BitBlt Destination Start Address Register 0
145 {0x0109,0x00}, // BitBlt Destination Start Address Register 1
146 {0x010A,0x00}, // BitBlt Destination Start Address Register 2
147 {0x010C,0x00}, // BitBlt Memory Address Offset Register 0
148 {0x010D,0x00}, // BitBlt Memory Address Offset Register 1
149 {0x0110,0x00}, // BitBlt Width Register 0
150 {0x0111,0x00}, // BitBlt Width Register 1
151 {0x0112,0x00}, // BitBlt Height Register 0
152 {0x0113,0x00}, // BitBlt Height Register 1
153 {0x0114,0x00}, // BitBlt Background Color Register 0
154 {0x0115,0x00}, // BitBlt Background Color Register 1
155 {0x0118,0x00}, // BitBlt Foreground Color Register 0
156 {0x0119,0x00}, // BitBlt Foreground Color Register 1
157 {0x01E0,0x00}, // Look-Up Table Mode Register
158 {0x01E2,0x00}, // Look-Up Table Address Register
159 /* not sure, wouldn't like to mess with the driver */
160 {0x01E4,0x00}, // Look-Up Table Data Register
161 /* jornada doc says 0x00, but I trust the driver */
162 {0x01F0,0x10}, // Power Save Configuration Register
163 {0x01F1,0x00}, // Power Save Status Register
164 {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
165 {0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
166};
167
168static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
169 .initregs = s1d13xxxfb_initregs,
170 .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
171 .platform_init_video = NULL
172};
27 173
28#define JORTUCR_VAL 0x20000400 174static struct resource s1d13xxxfb_resources[] = {
175 [0] = {
176 .start = EPSONFBSTART,
177 .end = EPSONFBSTART + EPSONFBLEN,
178 .flags = IORESOURCE_MEM,
179 },
180 [1] = {
181 .start = EPSONREGSTART,
182 .end = EPSONREGSTART + EPSONREGLEN,
183 .flags = IORESOURCE_MEM,
184 }
185};
186
187static struct platform_device s1d13xxxfb_device = {
188 .name = S1D_DEVICENAME,
189 .id = 0,
190 .dev = {
191 .platform_data = &s1d13xxxfb_data,
192 },
193 .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
194 .resource = s1d13xxxfb_resources,
195};
29 196
30static struct resource sa1111_resources[] = { 197static struct resource sa1111_resources[] = {
31 [0] = { 198 [0] = {
32 .start = 0x40000000, 199 .start = SA1111REGSTART,
33 .end = 0x40001fff, 200 .end = SA1111REGSTART + SA1111REGLEN,
34 .flags = IORESOURCE_MEM, 201 .flags = IORESOURCE_MEM,
35 }, 202 },
36 [1] = { 203 [1] = {
@@ -53,18 +220,32 @@ static struct platform_device sa1111_device = {
53 .resource = sa1111_resources, 220 .resource = sa1111_resources,
54}; 221};
55 222
223static struct platform_device jornada720_mcu_device = {
224 .name = "jornada720_mcu",
225 .id = -1,
226};
227
56static struct platform_device *devices[] __initdata = { 228static struct platform_device *devices[] __initdata = {
57 &sa1111_device, 229 &sa1111_device,
230 &jornada720_mcu_device,
231 &s1d13xxxfb_device,
58}; 232};
59 233
234/* a stub for now, we theoretically cannot suspend without a flashboard */
235int pm_suspend(suspend_state_t state)
236{
237 return -1;
238}
239
60static int __init jornada720_init(void) 240static int __init jornada720_init(void)
61{ 241{
62 int ret = -ENODEV; 242 int ret = -ENODEV;
63 243
64 if (machine_is_jornada720()) { 244 if (machine_is_jornada720()) {
65 GPDR |= GPIO_GPIO20; 245 GPDR |= GPIO_GPIO20;
66 TUCR = JORTUCR_VAL; /* set the oscillator out to the SA-1101 */ 246 /* oscillator setup (line 116 of HP's doc) */
67 247 TUCR = TUCR_VAL;
248 /* resetting SA1111 (line 118 of HP's doc) */
68 GPSR = GPIO_GPIO20; 249 GPSR = GPIO_GPIO20;
69 udelay(1); 250 udelay(1);
70 GPCR = GPIO_GPIO20; 251 GPCR = GPIO_GPIO20;
@@ -72,10 +253,6 @@ static int __init jornada720_init(void)
72 GPSR = GPIO_GPIO20; 253 GPSR = GPIO_GPIO20;
73 udelay(20); 254 udelay(20);
74 255
75 /* LDD4 is speaker, LDD3 is microphone */
76 PPSR &= ~(PPC_LDD3 | PPC_LDD4);
77 PPDR |= PPC_LDD3 | PPC_LDD4;
78
79 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 256 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
80 } 257 }
81 return ret; 258 return ret;
@@ -85,19 +262,19 @@ arch_initcall(jornada720_init);
85 262
86static struct map_desc jornada720_io_desc[] __initdata = { 263static struct map_desc jornada720_io_desc[] __initdata = {
87 { /* Epson registers */ 264 { /* Epson registers */
88 .virtual = 0xf0000000, 265 .virtual = 0xf0000000,
89 .pfn = __phys_to_pfn(0x48000000), 266 .pfn = __phys_to_pfn(EPSONREGSTART),
90 .length = 0x00100000, 267 .length = EPSONREGLEN,
91 .type = MT_DEVICE 268 .type = MT_DEVICE
92 }, { /* Epson frame buffer */ 269 }, { /* Epson frame buffer */
93 .virtual = 0xf1000000, 270 .virtual = 0xf1000000,
94 .pfn = __phys_to_pfn(0x48200000), 271 .pfn = __phys_to_pfn(EPSONFBSTART),
95 .length = 0x00100000, 272 .length = EPSONFBLEN,
96 .type = MT_DEVICE 273 .type = MT_DEVICE
97 }, { /* SA-1111 */ 274 }, { /* SA-1111 */
98 .virtual = 0xf4000000, 275 .virtual = 0xf4000000,
99 .pfn = __phys_to_pfn(0x40000000), 276 .pfn = __phys_to_pfn(SA1111REGSTART),
100 .length = 0x00100000, 277 .length = SA1111REGLEN,
101 .type = MT_DEVICE 278 .type = MT_DEVICE
102 } 279 }
103}; 280};
@@ -106,7 +283,7 @@ static void __init jornada720_map_io(void)
106{ 283{
107 sa1100_map_io(); 284 sa1100_map_io();
108 iotable_init(jornada720_io_desc, ARRAY_SIZE(jornada720_io_desc)); 285 iotable_init(jornada720_io_desc, ARRAY_SIZE(jornada720_io_desc));
109 286
110 sa1100_register_uart(0, 3); 287 sa1100_register_uart(0, 3);
111 sa1100_register_uart(1, 1); 288 sa1100_register_uart(1, 1);
112} 289}
@@ -116,7 +293,7 @@ static struct mtd_partition jornada720_partitions[] = {
116 .name = "JORNADA720 boot firmware", 293 .name = "JORNADA720 boot firmware",
117 .size = 0x00040000, 294 .size = 0x00040000,
118 .offset = 0, 295 .offset = 0,
119 .mask_flags = MTD_WRITEABLE, /* force read-only */ 296 .mask_flags = MTD_WRITEABLE, /* force read-only */
120 }, { 297 }, {
121 .name = "JORNADA720 kernel", 298 .name = "JORNADA720 kernel",
122 .size = 0x000c0000, 299 .size = 0x000c0000,
@@ -139,7 +316,7 @@ static struct mtd_partition jornada720_partitions[] = {
139 .offset = 0x00540000, 316 .offset = 0x00540000,
140 }, { 317 }, {
141 .name = "JORNADA720 usr local", 318 .name = "JORNADA720 usr local",
142 .size = 0, /* will expand to the end of the flash */ 319 .size = 0, /* will expand to the end of the flash */
143 .offset = 0x00d00000, 320 .offset = 0x00d00000,
144 } 321 }
145}; 322};
@@ -147,10 +324,12 @@ static struct mtd_partition jornada720_partitions[] = {
147static void jornada720_set_vpp(int vpp) 324static void jornada720_set_vpp(int vpp)
148{ 325{
149 if (vpp) 326 if (vpp)
150 PPSR |= 0x80; 327 /* enabling flash write (line 470 of HP's doc) */
328 PPSR |= PPC_LDD7;
151 else 329 else
152 PPSR &= ~0x80; 330 /* disabling flash write (line 470 of HP's doc) */
153 PPDR |= 0x80; 331 PPSR &= ~PPC_LDD7;
332 PPDR |= PPC_LDD7;
154} 333}
155 334
156static struct flash_platform_data jornada720_flash_data = { 335static struct flash_platform_data jornada720_flash_data = {
diff --git a/arch/arm/mm/consistent.c b/arch/arm/mm/consistent.c
index b797217e82be..6a9c362fef5e 100644
--- a/arch/arm/mm/consistent.c
+++ b/arch/arm/mm/consistent.c
@@ -238,7 +238,7 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
238 * x86 does not mark the pages reserved... 238 * x86 does not mark the pages reserved...
239 */ 239 */
240 SetPageReserved(page); 240 SetPageReserved(page);
241 set_pte(pte, mk_pte(page, prot)); 241 set_pte_ext(pte, mk_pte(page, prot), 0);
242 page++; 242 page++;
243 pte++; 243 pte++;
244 off++; 244 off++;
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index df1645e14b4c..408b05ae6b9b 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -71,7 +71,7 @@ void v4_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr)
71{ 71{
72 spin_lock(&minicache_lock); 72 spin_lock(&minicache_lock);
73 73
74 set_pte(TOP_PTE(0xffff8000), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot)); 74 set_pte_ext(TOP_PTE(0xffff8000), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot), 0);
75 flush_tlb_kernel_page(0xffff8000); 75 flush_tlb_kernel_page(0xffff8000);
76 76
77 mc_copy_user_page((void *)0xffff8000, kto); 77 mc_copy_user_page((void *)0xffff8000, kto);
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index 3d0d3a963d20..865777dec161 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -70,8 +70,8 @@ static void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned lo
70 */ 70 */
71 spin_lock(&v6_lock); 71 spin_lock(&v6_lock);
72 72
73 set_pte(TOP_PTE(from_address) + offset, pfn_pte(__pa(kfrom) >> PAGE_SHIFT, PAGE_KERNEL)); 73 set_pte_ext(TOP_PTE(from_address) + offset, pfn_pte(__pa(kfrom) >> PAGE_SHIFT, PAGE_KERNEL), 0);
74 set_pte(TOP_PTE(to_address) + offset, pfn_pte(__pa(kto) >> PAGE_SHIFT, PAGE_KERNEL)); 74 set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(__pa(kto) >> PAGE_SHIFT, PAGE_KERNEL), 0);
75 75
76 from = from_address + (offset << PAGE_SHIFT); 76 from = from_address + (offset << PAGE_SHIFT);
77 to = to_address + (offset << PAGE_SHIFT); 77 to = to_address + (offset << PAGE_SHIFT);
@@ -110,7 +110,7 @@ static void v6_clear_user_page_aliasing(void *kaddr, unsigned long vaddr)
110 */ 110 */
111 spin_lock(&v6_lock); 111 spin_lock(&v6_lock);
112 112
113 set_pte(TOP_PTE(to_address) + offset, pfn_pte(__pa(kaddr) >> PAGE_SHIFT, PAGE_KERNEL)); 113 set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(__pa(kaddr) >> PAGE_SHIFT, PAGE_KERNEL), 0);
114 flush_tlb_kernel_page(to); 114 flush_tlb_kernel_page(to);
115 clear_page((void *)to); 115 clear_page((void *)to);
116 116
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 84ebe0aa379e..aea5da723596 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -93,7 +93,7 @@ void xscale_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr)
93{ 93{
94 spin_lock(&minicache_lock); 94 spin_lock(&minicache_lock);
95 95
96 set_pte(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot)); 96 set_pte_ext(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot), 0);
97 flush_tlb_kernel_page(COPYPAGE_MINICACHE); 97 flush_tlb_kernel_page(COPYPAGE_MINICACHE);
98 98
99 mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto); 99 mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto);
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 7fc1b35a6746..cf95c5d0ce4c 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -61,7 +61,7 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
61 if (pte_present(entry) && pte_val(entry) & shared_pte_mask) { 61 if (pte_present(entry) && pte_val(entry) & shared_pte_mask) {
62 flush_cache_page(vma, address, pte_pfn(entry)); 62 flush_cache_page(vma, address, pte_pfn(entry));
63 pte_val(entry) &= ~shared_pte_mask; 63 pte_val(entry) &= ~shared_pte_mask;
64 set_pte(pte, entry); 64 set_pte_at(vma->vm_mm, address, pte, entry);
65 flush_tlb_page(vma, address); 65 flush_tlb_page(vma, address);
66 ret = 1; 66 ret = 1;
67 } 67 }
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 454205b789d5..628348c9f6c5 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -26,7 +26,7 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
26 unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT); 26 unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
27 const int zero = 0; 27 const int zero = 0;
28 28
29 set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL)); 29 set_pte_ext(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL), 0);
30 flush_tlb_kernel_page(to); 30 flush_tlb_kernel_page(to);
31 31
32 asm( "mcrr p15, 0, %1, %0, c14\n" 32 asm( "mcrr p15, 0, %1, %0, c14\n"
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 465440592791..3bb3951920bc 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -38,89 +38,71 @@
38 */ 38 */
39#define VM_ARM_SECTION_MAPPING 0x80000000 39#define VM_ARM_SECTION_MAPPING 0x80000000
40 40
41static inline void 41static int remap_area_pte(pmd_t *pmd, unsigned long addr, unsigned long end,
42remap_area_pte(pte_t * pte, unsigned long address, unsigned long size, 42 unsigned long phys_addr, pgprot_t prot)
43 unsigned long phys_addr, pgprot_t pgprot)
44{ 43{
45 unsigned long end; 44 pte_t *pte;
45
46 pte = pte_alloc_kernel(pmd, addr);
47 if (!pte)
48 return -ENOMEM;
46 49
47 address &= ~PMD_MASK;
48 end = address + size;
49 if (end > PMD_SIZE)
50 end = PMD_SIZE;
51 BUG_ON(address >= end);
52 do { 50 do {
53 if (!pte_none(*pte)) 51 if (!pte_none(*pte))
54 goto bad; 52 goto bad;
55 53
56 set_pte(pte, pfn_pte(phys_addr >> PAGE_SHIFT, pgprot)); 54 set_pte_ext(pte, pfn_pte(phys_addr >> PAGE_SHIFT, prot), 0);
57 address += PAGE_SIZE;
58 phys_addr += PAGE_SIZE; 55 phys_addr += PAGE_SIZE;
59 pte++; 56 } while (pte++, addr += PAGE_SIZE, addr != end);
60 } while (address && (address < end)); 57 return 0;
61 return;
62 58
63 bad: 59 bad:
64 printk("remap_area_pte: page already exists\n"); 60 printk(KERN_CRIT "remap_area_pte: page already exists\n");
65 BUG(); 61 BUG();
66} 62}
67 63
68static inline int 64static inline int remap_area_pmd(pgd_t *pgd, unsigned long addr,
69remap_area_pmd(pmd_t * pmd, unsigned long address, unsigned long size, 65 unsigned long end, unsigned long phys_addr,
70 unsigned long phys_addr, unsigned long flags) 66 pgprot_t prot)
71{ 67{
72 unsigned long end; 68 unsigned long next;
73 pgprot_t pgprot; 69 pmd_t *pmd;
74 70 int ret = 0;
75 address &= ~PGDIR_MASK;
76 end = address + size;
77 71
78 if (end > PGDIR_SIZE) 72 pmd = pmd_alloc(&init_mm, pgd, addr);
79 end = PGDIR_SIZE; 73 if (!pmd)
74 return -ENOMEM;
80 75
81 phys_addr -= address;
82 BUG_ON(address >= end);
83
84 pgprot = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_WRITE | flags);
85 do { 76 do {
86 pte_t * pte = pte_alloc_kernel(pmd, address); 77 next = pmd_addr_end(addr, end);
87 if (!pte) 78 ret = remap_area_pte(pmd, addr, next, phys_addr, prot);
88 return -ENOMEM; 79 if (ret)
89 remap_area_pte(pte, address, end - address, address + phys_addr, pgprot); 80 return ret;
90 address = (address + PMD_SIZE) & PMD_MASK; 81 phys_addr += next - addr;
91 pmd++; 82 } while (pmd++, addr = next, addr != end);
92 } while (address && (address < end)); 83 return ret;
93 return 0;
94} 84}
95 85
96static int 86static int remap_area_pages(unsigned long start, unsigned long pfn,
97remap_area_pages(unsigned long start, unsigned long pfn, 87 unsigned long size, unsigned long flags)
98 unsigned long size, unsigned long flags)
99{ 88{
100 unsigned long address = start; 89 unsigned long addr = start;
101 unsigned long end = start + size; 90 unsigned long next, end = start + size;
102 unsigned long phys_addr = __pfn_to_phys(pfn); 91 unsigned long phys_addr = __pfn_to_phys(pfn);
92 pgprot_t prot = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
93 L_PTE_DIRTY | L_PTE_WRITE | flags);
94 pgd_t *pgd;
103 int err = 0; 95 int err = 0;
104 pgd_t * dir;
105 96
106 phys_addr -= address; 97 BUG_ON(addr >= end);
107 dir = pgd_offset(&init_mm, address); 98 pgd = pgd_offset_k(addr);
108 BUG_ON(address >= end);
109 do { 99 do {
110 pmd_t *pmd = pmd_alloc(&init_mm, dir, address); 100 next = pgd_addr_end(addr, end);
111 if (!pmd) { 101 err = remap_area_pmd(pgd, addr, next, phys_addr, prot);
112 err = -ENOMEM; 102 if (err)
113 break;
114 }
115 if (remap_area_pmd(pmd, address, end - address,
116 phys_addr + address, flags)) {
117 err = -ENOMEM;
118 break; 103 break;
119 } 104 phys_addr += next - addr;
120 105 } while (pgd++, addr = next, addr != end);
121 address = (address + PGDIR_SIZE) & PGDIR_MASK;
122 dir++;
123 } while (address && (address < end));
124 106
125 return err; 107 return err;
126} 108}
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index b7f194af20b4..f028aef9a861 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -294,12 +294,6 @@ static void __init build_mem_type_table(void)
294 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE; 294 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
295 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; 295 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
296 296
297 /*
298 * User pages need to be mapped with the ASID
299 * (iow, non-global)
300 */
301 user_pgprot |= L_PTE_ASID;
302
303#ifdef CONFIG_SMP 297#ifdef CONFIG_SMP
304 /* 298 /*
305 * Mark memory with the "shared" attribute for SMP systems 299 * Mark memory with the "shared" attribute for SMP systems
@@ -408,7 +402,7 @@ alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pg
408 } 402 }
409 ptep = pte_offset_kernel(pmdp, virt); 403 ptep = pte_offset_kernel(pmdp, virt);
410 404
411 set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot)); 405 set_pte_ext(ptep, pfn_pte(phys >> PAGE_SHIFT, prot), 0);
412} 406}
413 407
414/* 408/*
diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c
index 20c1b0df75f2..50b9aed6000d 100644
--- a/arch/arm/mm/pgd.c
+++ b/arch/arm/mm/pgd.c
@@ -57,7 +57,7 @@ pgd_t *get_pgd_slow(struct mm_struct *mm)
57 57
58 init_pmd = pmd_offset(init_pgd, 0); 58 init_pmd = pmd_offset(init_pgd, 0);
59 init_pte = pte_offset_map_nested(init_pmd, 0); 59 init_pte = pte_offset_map_nested(init_pmd, 0);
60 set_pte(new_pte, *init_pte); 60 set_pte_ext(new_pte, *init_pte, 0);
61 pte_unmap_nested(init_pte); 61 pte_unmap_nested(init_pte);
62 pte_unmap(new_pte); 62 pte_unmap(new_pte);
63 } 63 }
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 289b8e6f504d..700c04d6996e 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -397,7 +397,7 @@ ENTRY(cpu_arm1020_switch_mm)
397 * Set a PTE and flush it out 397 * Set a PTE and flush it out
398 */ 398 */
399 .align 5 399 .align 5
400ENTRY(cpu_arm1020_set_pte) 400ENTRY(cpu_arm1020_set_pte_ext)
401#ifdef CONFIG_MMU 401#ifdef CONFIG_MMU
402 str r1, [r0], #-2048 @ linux version 402 str r1, [r0], #-2048 @ linux version
403 403
@@ -477,7 +477,7 @@ arm1020_processor_functions:
477 .word cpu_arm1020_do_idle 477 .word cpu_arm1020_do_idle
478 .word cpu_arm1020_dcache_clean_area 478 .word cpu_arm1020_dcache_clean_area
479 .word cpu_arm1020_switch_mm 479 .word cpu_arm1020_switch_mm
480 .word cpu_arm1020_set_pte 480 .word cpu_arm1020_set_pte_ext
481 .size arm1020_processor_functions, . - arm1020_processor_functions 481 .size arm1020_processor_functions, . - arm1020_processor_functions
482 482
483 .section ".rodata" 483 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index bed9db6ba582..1cc206ab5eae 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -381,7 +381,7 @@ ENTRY(cpu_arm1020e_switch_mm)
381 * Set a PTE and flush it out 381 * Set a PTE and flush it out
382 */ 382 */
383 .align 5 383 .align 5
384ENTRY(cpu_arm1020e_set_pte) 384ENTRY(cpu_arm1020e_set_pte_ext)
385#ifdef CONFIG_MMU 385#ifdef CONFIG_MMU
386 str r1, [r0], #-2048 @ linux version 386 str r1, [r0], #-2048 @ linux version
387 387
@@ -458,7 +458,7 @@ arm1020e_processor_functions:
458 .word cpu_arm1020e_do_idle 458 .word cpu_arm1020e_do_idle
459 .word cpu_arm1020e_dcache_clean_area 459 .word cpu_arm1020e_dcache_clean_area
460 .word cpu_arm1020e_switch_mm 460 .word cpu_arm1020e_switch_mm
461 .word cpu_arm1020e_set_pte 461 .word cpu_arm1020e_set_pte_ext
462 .size arm1020e_processor_functions, . - arm1020e_processor_functions 462 .size arm1020e_processor_functions, . - arm1020e_processor_functions
463 463
464 .section ".rodata" 464 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index d2a7c1b9cab9..aff0ea08e2f8 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -358,12 +358,12 @@ ENTRY(cpu_arm1022_switch_mm)
358 mov pc, lr 358 mov pc, lr
359 359
360/* 360/*
361 * cpu_arm1022_set_pte(ptep, pte) 361 * cpu_arm1022_set_pte_ext(ptep, pte, ext)
362 * 362 *
363 * Set a PTE and flush it out 363 * Set a PTE and flush it out
364 */ 364 */
365 .align 5 365 .align 5
366ENTRY(cpu_arm1022_set_pte) 366ENTRY(cpu_arm1022_set_pte_ext)
367#ifdef CONFIG_MMU 367#ifdef CONFIG_MMU
368 str r1, [r0], #-2048 @ linux version 368 str r1, [r0], #-2048 @ linux version
369 369
@@ -441,7 +441,7 @@ arm1022_processor_functions:
441 .word cpu_arm1022_do_idle 441 .word cpu_arm1022_do_idle
442 .word cpu_arm1022_dcache_clean_area 442 .word cpu_arm1022_dcache_clean_area
443 .word cpu_arm1022_switch_mm 443 .word cpu_arm1022_switch_mm
444 .word cpu_arm1022_set_pte 444 .word cpu_arm1022_set_pte_ext
445 .size arm1022_processor_functions, . - arm1022_processor_functions 445 .size arm1022_processor_functions, . - arm1022_processor_functions
446 446
447 .section ".rodata" 447 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 3247ce5c0177..65e43a109085 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -347,12 +347,12 @@ ENTRY(cpu_arm1026_switch_mm)
347 mov pc, lr 347 mov pc, lr
348 348
349/* 349/*
350 * cpu_arm1026_set_pte(ptep, pte) 350 * cpu_arm1026_set_pte_ext(ptep, pte, ext)
351 * 351 *
352 * Set a PTE and flush it out 352 * Set a PTE and flush it out
353 */ 353 */
354 .align 5 354 .align 5
355ENTRY(cpu_arm1026_set_pte) 355ENTRY(cpu_arm1026_set_pte_ext)
356#ifdef CONFIG_MMU 356#ifdef CONFIG_MMU
357 str r1, [r0], #-2048 @ linux version 357 str r1, [r0], #-2048 @ linux version
358 358
@@ -436,7 +436,7 @@ arm1026_processor_functions:
436 .word cpu_arm1026_do_idle 436 .word cpu_arm1026_do_idle
437 .word cpu_arm1026_dcache_clean_area 437 .word cpu_arm1026_dcache_clean_area
438 .word cpu_arm1026_switch_mm 438 .word cpu_arm1026_switch_mm
439 .word cpu_arm1026_set_pte 439 .word cpu_arm1026_set_pte_ext
440 .size arm1026_processor_functions, . - arm1026_processor_functions 440 .size arm1026_processor_functions, . - arm1026_processor_functions
441 441
442 .section .rodata 442 .section .rodata
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index ce4f9eef763c..123a7dc7a433 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -209,14 +209,14 @@ ENTRY(cpu_arm7_switch_mm)
209 mov pc, lr 209 mov pc, lr
210 210
211/* 211/*
212 * Function: arm6_7_set_pte(pte_t *ptep, pte_t pte) 212 * Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
213 * Params : r0 = Address to set 213 * Params : r0 = Address to set
214 * : r1 = value to set 214 * : r1 = value to set
215 * Purpose : Set a PTE and flush it out of any WB cache 215 * Purpose : Set a PTE and flush it out of any WB cache
216 */ 216 */
217 .align 5 217 .align 5
218ENTRY(cpu_arm6_set_pte) 218ENTRY(cpu_arm6_set_pte_ext)
219ENTRY(cpu_arm7_set_pte) 219ENTRY(cpu_arm7_set_pte_ext)
220#ifdef CONFIG_MMU 220#ifdef CONFIG_MMU
221 str r1, [r0], #-2048 @ linux version 221 str r1, [r0], #-2048 @ linux version
222 222
@@ -299,7 +299,7 @@ ENTRY(arm6_processor_functions)
299 .word cpu_arm6_do_idle 299 .word cpu_arm6_do_idle
300 .word cpu_arm6_dcache_clean_area 300 .word cpu_arm6_dcache_clean_area
301 .word cpu_arm6_switch_mm 301 .word cpu_arm6_switch_mm
302 .word cpu_arm6_set_pte 302 .word cpu_arm6_set_pte_ext
303 .size arm6_processor_functions, . - arm6_processor_functions 303 .size arm6_processor_functions, . - arm6_processor_functions
304 304
305/* 305/*
@@ -315,7 +315,7 @@ ENTRY(arm7_processor_functions)
315 .word cpu_arm7_do_idle 315 .word cpu_arm7_do_idle
316 .word cpu_arm7_dcache_clean_area 316 .word cpu_arm7_dcache_clean_area
317 .word cpu_arm7_switch_mm 317 .word cpu_arm7_switch_mm
318 .word cpu_arm7_set_pte 318 .word cpu_arm7_set_pte_ext
319 .size arm7_processor_functions, . - arm7_processor_functions 319 .size arm7_processor_functions, . - arm7_processor_functions
320 320
321 .section ".rodata" 321 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index c04c194da785..dc763be43362 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -88,13 +88,13 @@ ENTRY(cpu_arm720_switch_mm)
88 mov pc, lr 88 mov pc, lr
89 89
90/* 90/*
91 * Function: arm720_set_pte(pte_t *ptep, pte_t pte) 91 * Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
92 * Params : r0 = Address to set 92 * Params : r0 = Address to set
93 * : r1 = value to set 93 * : r1 = value to set
94 * Purpose : Set a PTE and flush it out of any WB cache 94 * Purpose : Set a PTE and flush it out of any WB cache
95 */ 95 */
96 .align 5 96 .align 5
97ENTRY(cpu_arm720_set_pte) 97ENTRY(cpu_arm720_set_pte_ext)
98#ifdef CONFIG_MMU 98#ifdef CONFIG_MMU
99 str r1, [r0], #-2048 @ linux version 99 str r1, [r0], #-2048 @ linux version
100 100
@@ -204,7 +204,7 @@ ENTRY(arm720_processor_functions)
204 .word cpu_arm720_do_idle 204 .word cpu_arm720_do_idle
205 .word cpu_arm720_dcache_clean_area 205 .word cpu_arm720_dcache_clean_area
206 .word cpu_arm720_switch_mm 206 .word cpu_arm720_switch_mm
207 .word cpu_arm720_set_pte 207 .word cpu_arm720_set_pte_ext
208 .size arm720_processor_functions, . - arm720_processor_functions 208 .size arm720_processor_functions, . - arm720_processor_functions
209 209
210 .section ".rodata" 210 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 65cbb2851bff..75c945ed6c4d 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -344,12 +344,12 @@ ENTRY(cpu_arm920_switch_mm)
344 mov pc, lr 344 mov pc, lr
345 345
346/* 346/*
347 * cpu_arm920_set_pte(ptep, pte) 347 * cpu_arm920_set_pte(ptep, pte, ext)
348 * 348 *
349 * Set a PTE and flush it out 349 * Set a PTE and flush it out
350 */ 350 */
351 .align 5 351 .align 5
352ENTRY(cpu_arm920_set_pte) 352ENTRY(cpu_arm920_set_pte_ext)
353#ifdef CONFIG_MMU 353#ifdef CONFIG_MMU
354 str r1, [r0], #-2048 @ linux version 354 str r1, [r0], #-2048 @ linux version
355 355
@@ -423,7 +423,7 @@ arm920_processor_functions:
423 .word cpu_arm920_do_idle 423 .word cpu_arm920_do_idle
424 .word cpu_arm920_dcache_clean_area 424 .word cpu_arm920_dcache_clean_area
425 .word cpu_arm920_switch_mm 425 .word cpu_arm920_switch_mm
426 .word cpu_arm920_set_pte 426 .word cpu_arm920_set_pte_ext
427 .size arm920_processor_functions, . - arm920_processor_functions 427 .size arm920_processor_functions, . - arm920_processor_functions
428 428
429 .section ".rodata" 429 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 52761b70d735..ffb751b877ff 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -348,12 +348,12 @@ ENTRY(cpu_arm922_switch_mm)
348 mov pc, lr 348 mov pc, lr
349 349
350/* 350/*
351 * cpu_arm922_set_pte(ptep, pte) 351 * cpu_arm922_set_pte_ext(ptep, pte, ext)
352 * 352 *
353 * Set a PTE and flush it out 353 * Set a PTE and flush it out
354 */ 354 */
355 .align 5 355 .align 5
356ENTRY(cpu_arm922_set_pte) 356ENTRY(cpu_arm922_set_pte_ext)
357#ifdef CONFIG_MMU 357#ifdef CONFIG_MMU
358 str r1, [r0], #-2048 @ linux version 358 str r1, [r0], #-2048 @ linux version
359 359
@@ -427,7 +427,7 @@ arm922_processor_functions:
427 .word cpu_arm922_do_idle 427 .word cpu_arm922_do_idle
428 .word cpu_arm922_dcache_clean_area 428 .word cpu_arm922_dcache_clean_area
429 .word cpu_arm922_switch_mm 429 .word cpu_arm922_switch_mm
430 .word cpu_arm922_set_pte 430 .word cpu_arm922_set_pte_ext
431 .size arm922_processor_functions, . - arm922_processor_functions 431 .size arm922_processor_functions, . - arm922_processor_functions
432 432
433 .section ".rodata" 433 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 5b74339d1588..44c2c997819f 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -391,12 +391,12 @@ ENTRY(cpu_arm925_switch_mm)
391 mov pc, lr 391 mov pc, lr
392 392
393/* 393/*
394 * cpu_arm925_set_pte(ptep, pte) 394 * cpu_arm925_set_pte_ext(ptep, pte, ext)
395 * 395 *
396 * Set a PTE and flush it out 396 * Set a PTE and flush it out
397 */ 397 */
398 .align 5 398 .align 5
399ENTRY(cpu_arm925_set_pte) 399ENTRY(cpu_arm925_set_pte_ext)
400#ifdef CONFIG_MMU 400#ifdef CONFIG_MMU
401 str r1, [r0], #-2048 @ linux version 401 str r1, [r0], #-2048 @ linux version
402 402
@@ -490,7 +490,7 @@ arm925_processor_functions:
490 .word cpu_arm925_do_idle 490 .word cpu_arm925_do_idle
491 .word cpu_arm925_dcache_clean_area 491 .word cpu_arm925_dcache_clean_area
492 .word cpu_arm925_switch_mm 492 .word cpu_arm925_switch_mm
493 .word cpu_arm925_set_pte 493 .word cpu_arm925_set_pte_ext
494 .size arm925_processor_functions, . - arm925_processor_functions 494 .size arm925_processor_functions, . - arm925_processor_functions
495 495
496 .section ".rodata" 496 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 8628ed29a955..5b80b6bdd0cb 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -348,12 +348,12 @@ ENTRY(cpu_arm926_switch_mm)
348 mov pc, lr 348 mov pc, lr
349 349
350/* 350/*
351 * cpu_arm926_set_pte(ptep, pte) 351 * cpu_arm926_set_pte_ext(ptep, pte, ext)
352 * 352 *
353 * Set a PTE and flush it out 353 * Set a PTE and flush it out
354 */ 354 */
355 .align 5 355 .align 5
356ENTRY(cpu_arm926_set_pte) 356ENTRY(cpu_arm926_set_pte_ext)
357#ifdef CONFIG_MMU 357#ifdef CONFIG_MMU
358 str r1, [r0], #-2048 @ linux version 358 str r1, [r0], #-2048 @ linux version
359 359
@@ -439,7 +439,7 @@ arm926_processor_functions:
439 .word cpu_arm926_do_idle 439 .word cpu_arm926_do_idle
440 .word cpu_arm926_dcache_clean_area 440 .word cpu_arm926_dcache_clean_area
441 .word cpu_arm926_switch_mm 441 .word cpu_arm926_switch_mm
442 .word cpu_arm926_set_pte 442 .word cpu_arm926_set_pte_ext
443 .size arm926_processor_functions, . - arm926_processor_functions 443 .size arm926_processor_functions, . - arm926_processor_functions
444 444
445 .section ".rodata" 445 .section ".rodata"
@@ -480,7 +480,7 @@ __arm926_proc_info:
480 b __arm926_setup 480 b __arm926_setup
481 .long cpu_arch_name 481 .long cpu_arch_name
482 .long cpu_elf_name 482 .long cpu_elf_name
483 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_VFP|HWCAP_EDSP|HWCAP_JAVA 483 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
484 .long cpu_arm926_name 484 .long cpu_arm926_name
485 .long arm926_processor_functions 485 .long arm926_processor_functions
486 .long v4wbi_tlb_fns 486 .long v4wbi_tlb_fns
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index cd7d865c9d19..6e226e12989f 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -146,12 +146,12 @@ ENTRY(cpu_sa110_switch_mm)
146#endif 146#endif
147 147
148/* 148/*
149 * cpu_sa110_set_pte(ptep, pte) 149 * cpu_sa110_set_pte_ext(ptep, pte, ext)
150 * 150 *
151 * Set a PTE and flush it out 151 * Set a PTE and flush it out
152 */ 152 */
153 .align 5 153 .align 5
154ENTRY(cpu_sa110_set_pte) 154ENTRY(cpu_sa110_set_pte_ext)
155#ifdef CONFIG_MMU 155#ifdef CONFIG_MMU
156 str r1, [r0], #-2048 @ linux version 156 str r1, [r0], #-2048 @ linux version
157 157
@@ -222,7 +222,7 @@ ENTRY(sa110_processor_functions)
222 .word cpu_sa110_do_idle 222 .word cpu_sa110_do_idle
223 .word cpu_sa110_dcache_clean_area 223 .word cpu_sa110_dcache_clean_area
224 .word cpu_sa110_switch_mm 224 .word cpu_sa110_switch_mm
225 .word cpu_sa110_set_pte 225 .word cpu_sa110_set_pte_ext
226 .size sa110_processor_functions, . - sa110_processor_functions 226 .size sa110_processor_functions, . - sa110_processor_functions
227 227
228 .section ".rodata" 228 .section ".rodata"
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index b776653cc31c..9afb11d089fe 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -159,12 +159,12 @@ ENTRY(cpu_sa1100_switch_mm)
159#endif 159#endif
160 160
161/* 161/*
162 * cpu_sa1100_set_pte(ptep, pte) 162 * cpu_sa1100_set_pte_ext(ptep, pte, ext)
163 * 163 *
164 * Set a PTE and flush it out 164 * Set a PTE and flush it out
165 */ 165 */
166 .align 5 166 .align 5
167ENTRY(cpu_sa1100_set_pte) 167ENTRY(cpu_sa1100_set_pte_ext)
168#ifdef CONFIG_MMU 168#ifdef CONFIG_MMU
169 str r1, [r0], #-2048 @ linux version 169 str r1, [r0], #-2048 @ linux version
170 170
@@ -237,7 +237,7 @@ ENTRY(sa1100_processor_functions)
237 .word cpu_sa1100_do_idle 237 .word cpu_sa1100_do_idle
238 .word cpu_sa1100_dcache_clean_area 238 .word cpu_sa1100_dcache_clean_area
239 .word cpu_sa1100_switch_mm 239 .word cpu_sa1100_switch_mm
240 .word cpu_sa1100_set_pte 240 .word cpu_sa1100_set_pte_ext
241 .size sa1100_processor_functions, . - sa1100_processor_functions 241 .size sa1100_processor_functions, . - sa1100_processor_functions
242 242
243 .section ".rodata" 243 .section ".rodata"
diff --git a/arch/arm/mm/proc-syms.c b/arch/arm/mm/proc-syms.c
index ab143557e688..9f396b4fa0b7 100644
--- a/arch/arm/mm/proc-syms.c
+++ b/arch/arm/mm/proc-syms.c
@@ -17,7 +17,7 @@
17 17
18#ifndef MULTI_CPU 18#ifndef MULTI_CPU
19EXPORT_SYMBOL(cpu_dcache_clean_area); 19EXPORT_SYMBOL(cpu_dcache_clean_area);
20EXPORT_SYMBOL(cpu_set_pte); 20EXPORT_SYMBOL(cpu_set_pte_ext);
21#else 21#else
22EXPORT_SYMBOL(processor); 22EXPORT_SYMBOL(processor);
23#endif 23#endif
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index b440c8a1d345..7b1843befb9c 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -103,13 +103,14 @@ ENTRY(cpu_v6_switch_mm)
103 mov pc, lr 103 mov pc, lr
104 104
105/* 105/*
106 * cpu_v6_set_pte(ptep, pte) 106 * cpu_v6_set_pte_ext(ptep, pte, ext)
107 * 107 *
108 * Set a level 2 translation table entry. 108 * Set a level 2 translation table entry.
109 * 109 *
110 * - ptep - pointer to level 2 translation table entry 110 * - ptep - pointer to level 2 translation table entry
111 * (hardware version is stored at -1024 bytes) 111 * (hardware version is stored at -1024 bytes)
112 * - pte - PTE value to store 112 * - pte - PTE value to store
113 * - ext - value for extended PTE bits
113 * 114 *
114 * Permissions: 115 * Permissions:
115 * YUWD APX AP1 AP0 SVC User 116 * YUWD APX AP1 AP0 SVC User
@@ -121,33 +122,34 @@ ENTRY(cpu_v6_switch_mm)
121 * 11x0 0 1 0 r/w r/o 122 * 11x0 0 1 0 r/w r/o
122 * 1111 0 1 1 r/w r/w 123 * 1111 0 1 1 r/w r/w
123 */ 124 */
124ENTRY(cpu_v6_set_pte) 125ENTRY(cpu_v6_set_pte_ext)
125#ifdef CONFIG_MMU 126#ifdef CONFIG_MMU
126 str r1, [r0], #-2048 @ linux version 127 str r1, [r0], #-2048 @ linux version
127 128
128 bic r2, r1, #0x000003f0 129 bic r3, r1, #0x000003f0
129 bic r2, r2, #0x00000003 130 bic r3, r3, #0x00000003
130 orr r2, r2, #PTE_EXT_AP0 | 2 131 orr r3, r3, r2
132 orr r3, r3, #PTE_EXT_AP0 | 2
131 133
132 tst r1, #L_PTE_WRITE 134 tst r1, #L_PTE_WRITE
133 tstne r1, #L_PTE_DIRTY 135 tstne r1, #L_PTE_DIRTY
134 orreq r2, r2, #PTE_EXT_APX 136 orreq r3, r3, #PTE_EXT_APX
135 137
136 tst r1, #L_PTE_USER 138 tst r1, #L_PTE_USER
137 orrne r2, r2, #PTE_EXT_AP1 139 orrne r3, r3, #PTE_EXT_AP1
138 tstne r2, #PTE_EXT_APX 140 tstne r3, #PTE_EXT_APX
139 bicne r2, r2, #PTE_EXT_APX | PTE_EXT_AP0 141 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
140 142
141 tst r1, #L_PTE_YOUNG 143 tst r1, #L_PTE_YOUNG
142 biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK 144 biceq r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
143 145
144 tst r1, #L_PTE_EXEC 146 tst r1, #L_PTE_EXEC
145 orreq r2, r2, #PTE_EXT_XN 147 orreq r3, r3, #PTE_EXT_XN
146 148
147 tst r1, #L_PTE_PRESENT 149 tst r1, #L_PTE_PRESENT
148 moveq r2, #0 150 moveq r3, #0
149 151
150 str r2, [r0] 152 str r3, [r0]
151 mcr p15, 0, r0, c7, c10, 1 @ flush_pte 153 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
152#endif 154#endif
153 mov pc, lr 155 mov pc, lr
@@ -156,7 +158,7 @@ ENTRY(cpu_v6_set_pte)
156 158
157 159
158cpu_v6_name: 160cpu_v6_name:
159 .asciz "Some Random V6 Processor" 161 .asciz "ARMv6-compatible processor"
160 .align 162 .align
161 163
162 .section ".text.init", #alloc, #execinstr 164 .section ".text.init", #alloc, #execinstr
@@ -207,11 +209,6 @@ __v6_setup:
207#endif 209#endif
208 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 210 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
209#endif /* CONFIG_MMU */ 211#endif /* CONFIG_MMU */
210#ifdef CONFIG_VFP
211 mrc p15, 0, r0, c1, c0, 2
212 orr r0, r0, #(0xf << 20)
213 mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP
214#endif
215 adr r5, v6_crval 212 adr r5, v6_crval
216 ldmia r5, {r5, r6} 213 ldmia r5, {r5, r6}
217 mrc p15, 0, r0, c1, c0, 0 @ read control register 214 mrc p15, 0, r0, c1, c0, 0 @ read control register
@@ -238,7 +235,7 @@ ENTRY(v6_processor_functions)
238 .word cpu_v6_do_idle 235 .word cpu_v6_do_idle
239 .word cpu_v6_dcache_clean_area 236 .word cpu_v6_dcache_clean_area
240 .word cpu_v6_switch_mm 237 .word cpu_v6_switch_mm
241 .word cpu_v6_set_pte 238 .word cpu_v6_set_pte_ext
242 .size v6_processor_functions, . - v6_processor_functions 239 .size v6_processor_functions, . - v6_processor_functions
243 240
244 .type cpu_arch_name, #object 241 .type cpu_arch_name, #object
@@ -273,7 +270,7 @@ __v6_proc_info:
273 b __v6_setup 270 b __v6_setup
274 .long cpu_arch_name 271 .long cpu_arch_name
275 .long cpu_elf_name 272 .long cpu_elf_name
276 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_VFP|HWCAP_EDSP|HWCAP_JAVA 273 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
277 .long cpu_v6_name 274 .long cpu_v6_name
278 .long v6_processor_functions 275 .long v6_processor_functions
279 .long v6wbi_tlb_fns 276 .long v6wbi_tlb_fns
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 1ef564d0957f..43494ae8f01a 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -357,13 +357,13 @@ ENTRY(cpu_xsc3_switch_mm)
357 cpwait_ret lr, ip 357 cpwait_ret lr, ip
358 358
359/* 359/*
360 * cpu_xsc3_set_pte(ptep, pte) 360 * cpu_xsc3_set_pte_ext(ptep, pte, ext)
361 * 361 *
362 * Set a PTE and flush it out 362 * Set a PTE and flush it out
363 * 363 *
364 */ 364 */
365 .align 5 365 .align 5
366ENTRY(cpu_xsc3_set_pte) 366ENTRY(cpu_xsc3_set_pte_ext)
367 str r1, [r0], #-2048 @ linux version 367 str r1, [r0], #-2048 @ linux version
368 368
369 bic r2, r1, #0xff0 @ Keep C, B bits 369 bic r2, r1, #0xff0 @ Keep C, B bits
@@ -457,7 +457,7 @@ ENTRY(xsc3_processor_functions)
457 .word cpu_xsc3_do_idle 457 .word cpu_xsc3_do_idle
458 .word cpu_xsc3_dcache_clean_area 458 .word cpu_xsc3_dcache_clean_area
459 .word cpu_xsc3_switch_mm 459 .word cpu_xsc3_switch_mm
460 .word cpu_xsc3_set_pte 460 .word cpu_xsc3_set_pte_ext
461 .size xsc3_processor_functions, . - xsc3_processor_functions 461 .size xsc3_processor_functions, . - xsc3_processor_functions
462 462
463 .section ".rodata" 463 .section ".rodata"
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index cc1004b3e511..490e11b34231 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -421,14 +421,14 @@ ENTRY(cpu_xscale_switch_mm)
421 cpwait_ret lr, ip 421 cpwait_ret lr, ip
422 422
423/* 423/*
424 * cpu_xscale_set_pte(ptep, pte) 424 * cpu_xscale_set_pte_ext(ptep, pte, ext)
425 * 425 *
426 * Set a PTE and flush it out 426 * Set a PTE and flush it out
427 * 427 *
428 * Errata 40: must set memory to write-through for user read-only pages. 428 * Errata 40: must set memory to write-through for user read-only pages.
429 */ 429 */
430 .align 5 430 .align 5
431ENTRY(cpu_xscale_set_pte) 431ENTRY(cpu_xscale_set_pte_ext)
432 str r1, [r0], #-2048 @ linux version 432 str r1, [r0], #-2048 @ linux version
433 433
434 bic r2, r1, #0xff0 434 bic r2, r1, #0xff0
@@ -529,7 +529,7 @@ ENTRY(xscale_processor_functions)
529 .word cpu_xscale_do_idle 529 .word cpu_xscale_do_idle
530 .word cpu_xscale_dcache_clean_area 530 .word cpu_xscale_dcache_clean_area
531 .word cpu_xscale_switch_mm 531 .word cpu_xscale_switch_mm
532 .word cpu_xscale_set_pte 532 .word cpu_xscale_set_pte_ext
533 .size xscale_processor_functions, . - xscale_processor_functions 533 .size xscale_processor_functions, . - xscale_processor_functions
534 534
535 .section ".rodata" 535 .section ".rodata"
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index f08eafbddcc1..e26cc1f59948 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -263,13 +263,24 @@ void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
263 if (exceptions) 263 if (exceptions)
264 vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs); 264 vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs);
265} 265}
266 266
267/* 267/*
268 * VFP support code initialisation. 268 * VFP support code initialisation.
269 */ 269 */
270static int __init vfp_init(void) 270static int __init vfp_init(void)
271{ 271{
272 unsigned int vfpsid; 272 unsigned int vfpsid;
273 unsigned int cpu_arch = cpu_architecture();
274 u32 access = 0;
275
276 if (cpu_arch >= CPU_ARCH_ARMv6) {
277 access = get_copro_access();
278
279 /*
280 * Enable full access to VFP (cp10 and cp11)
281 */
282 set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11));
283 }
273 284
274 /* 285 /*
275 * First check that there is a VFP that we can use. 286 * First check that there is a VFP that we can use.
@@ -281,6 +292,12 @@ static int __init vfp_init(void)
281 printk(KERN_INFO "VFP support v0.3: "); 292 printk(KERN_INFO "VFP support v0.3: ");
282 if (VFP_arch) { 293 if (VFP_arch) {
283 printk("not present\n"); 294 printk("not present\n");
295
296 /*
297 * Restore the copro access register.
298 */
299 if (cpu_arch >= CPU_ARCH_ARMv6)
300 set_copro_access(access);
284 } else if (vfpsid & FPSID_NODOUBLE) { 301 } else if (vfpsid & FPSID_NODOUBLE) {
285 printk("no double precision support\n"); 302 printk("no double precision support\n");
286 } else { 303 } else {
@@ -291,9 +308,16 @@ static int __init vfp_init(void)
291 (vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT, 308 (vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT,
292 (vfpsid & FPSID_VARIANT_MASK) >> FPSID_VARIANT_BIT, 309 (vfpsid & FPSID_VARIANT_MASK) >> FPSID_VARIANT_BIT,
293 (vfpsid & FPSID_REV_MASK) >> FPSID_REV_BIT); 310 (vfpsid & FPSID_REV_MASK) >> FPSID_REV_BIT);
311
294 vfp_vector = vfp_support_entry; 312 vfp_vector = vfp_support_entry;
295 313
296 thread_register_notifier(&vfp_notifier_block); 314 thread_register_notifier(&vfp_notifier_block);
315
316 /*
317 * We detected VFP, and the support code is
318 * in place; report VFP support to userspace.
319 */
320 elf_hwcap |= HWCAP_VFP;
297 } 321 }
298 return 0; 322 return 0;
299} 323}
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h
index a6912b3d8671..e56a4e247d62 100644
--- a/include/asm-arm/arch-imx/imx-regs.h
+++ b/include/asm-arm/arch-imx/imx-regs.h
@@ -41,7 +41,13 @@
41 41
42/* PLL registers */ 42/* PLL registers */
43#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ 43#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
44#define CSCR_SYSTEM_SEL (1<<16) 44#define CSCR_SPLL_RESTART (1<<22)
45#define CSCR_MPLL_RESTART (1<<21)
46#define CSCR_SYSTEM_SEL (1<<16)
47#define CSCR_BCLK_DIV (0xf<<10)
48#define CSCR_MPU_PRESC (1<<15)
49#define CSCR_SPEN (1<<1)
50#define CSCR_MPEN (1<<0)
45 51
46#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ 52#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
47#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ 53#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
@@ -49,8 +55,6 @@
49#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ 55#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
50#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ 56#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
51 57
52#define CSCR_MPLL_RESTART (1<<21)
53
54/* 58/*
55 * GPIO Module and I/O Multiplexer 59 * GPIO Module and I/O Multiplexer
56 * x = 0..3 for reg_A, reg_B, reg_C, reg_D 60 * x = 0..3 for reg_A, reg_B, reg_C, reg_D
diff --git a/include/asm-arm/arch-s3c2410/regs-udc.h b/include/asm-arm/arch-s3c2410/regs-udc.h
index 487861d5b49a..3c8354619b60 100644
--- a/include/asm-arm/arch-s3c2410/regs-udc.h
+++ b/include/asm-arm/arch-s3c2410/regs-udc.h
@@ -11,8 +11,7 @@
11#ifndef __ASM_ARCH_REGS_UDC_H 11#ifndef __ASM_ARCH_REGS_UDC_H
12#define __ASM_ARCH_REGS_UDC_H 12#define __ASM_ARCH_REGS_UDC_H
13 13
14 14#define S3C2410_USBDREG(x) (x)
15#define S3C2410_USBDREG(x) ((x) + S3C24XX_VA_USBDEV)
16 15
17#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140) 16#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)
18#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144) 17#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)
@@ -136,8 +135,8 @@
136#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W 135#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W
137#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W 136#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W
138 137
139#define S3C2410_UDC_SETIX(x) \ 138#define S3C2410_UDC_SETIX(base,x) \
140 __raw_writel(S3C2410_UDC_INDEX_ ## x, S3C2410_UDC_INDEX_REG); 139 writel(S3C2410_UDC_INDEX_ ## x, base+S3C2410_UDC_INDEX_REG);
141 140
142 141
143#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0) 142#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0)
diff --git a/include/asm-arm/cpu-multi32.h b/include/asm-arm/cpu-multi32.h
index 4679f63688e9..715e18a4add1 100644
--- a/include/asm-arm/cpu-multi32.h
+++ b/include/asm-arm/cpu-multi32.h
@@ -50,9 +50,10 @@ extern struct processor {
50 */ 50 */
51 void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm); 51 void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm);
52 /* 52 /*
53 * Set a PTE 53 * Set a possibly extended PTE. Non-extended PTEs should
54 * ignore 'ext'.
54 */ 55 */
55 void (*set_pte)(pte_t *ptep, pte_t pte); 56 void (*set_pte_ext)(pte_t *ptep, pte_t pte, unsigned int ext);
56} processor; 57} processor;
57 58
58#define cpu_proc_init() processor._proc_init() 59#define cpu_proc_init() processor._proc_init()
@@ -60,5 +61,5 @@ extern struct processor {
60#define cpu_reset(addr) processor.reset(addr) 61#define cpu_reset(addr) processor.reset(addr)
61#define cpu_do_idle() processor._do_idle() 62#define cpu_do_idle() processor._do_idle()
62#define cpu_dcache_clean_area(addr,sz) processor.dcache_clean_area(addr,sz) 63#define cpu_dcache_clean_area(addr,sz) processor.dcache_clean_area(addr,sz)
63#define cpu_set_pte(ptep, pte) processor.set_pte(ptep, pte) 64#define cpu_set_pte_ext(ptep,pte,ext) processor.set_pte_ext(ptep,pte,ext)
64#define cpu_do_switch_mm(pgd,mm) processor.switch_mm(pgd,mm) 65#define cpu_do_switch_mm(pgd,mm) processor.switch_mm(pgd,mm)
diff --git a/include/asm-arm/cpu-single.h b/include/asm-arm/cpu-single.h
index 6723e67244fa..0b120ee36091 100644
--- a/include/asm-arm/cpu-single.h
+++ b/include/asm-arm/cpu-single.h
@@ -28,7 +28,7 @@
28#define cpu_do_idle __cpu_fn(CPU_NAME,_do_idle) 28#define cpu_do_idle __cpu_fn(CPU_NAME,_do_idle)
29#define cpu_dcache_clean_area __cpu_fn(CPU_NAME,_dcache_clean_area) 29#define cpu_dcache_clean_area __cpu_fn(CPU_NAME,_dcache_clean_area)
30#define cpu_do_switch_mm __cpu_fn(CPU_NAME,_switch_mm) 30#define cpu_do_switch_mm __cpu_fn(CPU_NAME,_switch_mm)
31#define cpu_set_pte __cpu_fn(CPU_NAME,_set_pte) 31#define cpu_set_pte_ext __cpu_fn(CPU_NAME,_set_pte_ext)
32 32
33#include <asm/page.h> 33#include <asm/page.h>
34 34
@@ -40,5 +40,5 @@ extern void cpu_proc_fin(void);
40extern int cpu_do_idle(void); 40extern int cpu_do_idle(void);
41extern void cpu_dcache_clean_area(void *, int); 41extern void cpu_dcache_clean_area(void *, int);
42extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm); 42extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
43extern void cpu_set_pte(pte_t *ptep, pte_t pte); 43extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext);
44extern void cpu_reset(unsigned long addr) __attribute__((noreturn)); 44extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index 88cd5c784ef0..b8cf2d5ec304 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -21,6 +21,7 @@
21 21
22#include <asm/memory.h> 22#include <asm/memory.h>
23#include <asm/arch/vmalloc.h> 23#include <asm/arch/vmalloc.h>
24#include <asm/pgtable-hwdef.h>
24 25
25/* 26/*
26 * Just any arbitrary offset to the start of the vmalloc VM area: the 27 * Just any arbitrary offset to the start of the vmalloc VM area: the
@@ -170,7 +171,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
170#define L_PTE_EXEC (1 << 6) 171#define L_PTE_EXEC (1 << 6)
171#define L_PTE_DIRTY (1 << 7) 172#define L_PTE_DIRTY (1 << 7)
172#define L_PTE_SHARED (1 << 10) /* shared(v6), coherent(xsc3) */ 173#define L_PTE_SHARED (1 << 10) /* shared(v6), coherent(xsc3) */
173#define L_PTE_ASID (1 << 11) /* non-global (use ASID, v6) */
174 174
175#ifndef __ASSEMBLY__ 175#ifndef __ASSEMBLY__
176 176
@@ -228,7 +228,7 @@ extern struct page *empty_zero_page;
228#define pfn_pte(pfn,prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))) 228#define pfn_pte(pfn,prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)))
229 229
230#define pte_none(pte) (!pte_val(pte)) 230#define pte_none(pte) (!pte_val(pte))
231#define pte_clear(mm,addr,ptep) set_pte_at((mm),(addr),(ptep), __pte(0)) 231#define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0)
232#define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 232#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
233#define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr)) 233#define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr))
234#define pte_offset_map(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr)) 234#define pte_offset_map(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr))
@@ -236,8 +236,11 @@ extern struct page *empty_zero_page;
236#define pte_unmap(pte) do { } while (0) 236#define pte_unmap(pte) do { } while (0)
237#define pte_unmap_nested(pte) do { } while (0) 237#define pte_unmap_nested(pte) do { } while (0)
238 238
239#define set_pte(ptep, pte) cpu_set_pte(ptep,pte) 239#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
240#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) 240
241#define set_pte_at(mm,addr,ptep,pteval) do { \
242 set_pte_ext(ptep, pteval, (addr) >= PAGE_OFFSET ? 0 : PTE_EXT_NG); \
243 } while (0)
241 244
242/* 245/*
243 * The following only work if pte_present() is true. 246 * The following only work if pte_present() is true.
diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h
index b442e8e2a809..1bbf16182d62 100644
--- a/include/asm-arm/processor.h
+++ b/include/asm-arm/processor.h
@@ -103,14 +103,14 @@ extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
103#if __LINUX_ARM_ARCH__ >= 5 103#if __LINUX_ARM_ARCH__ >= 5
104 104
105#define ARCH_HAS_PREFETCH 105#define ARCH_HAS_PREFETCH
106#define prefetch(ptr) \ 106static inline void prefetch(const void *ptr)
107 ({ \ 107{
108 __asm__ __volatile__( \ 108 __asm__ __volatile__(
109 "pld\t%0" \ 109 "pld\t%0"
110 : \ 110 :
111 : "o" (*(char *)(ptr)) \ 111 : "o" (*(char *)ptr)
112 : "cc"); \ 112 : "cc");
113 }) 113}
114 114
115#define ARCH_HAS_PREFETCHW 115#define ARCH_HAS_PREFETCHW
116#define prefetchw(ptr) prefetch(ptr) 116#define prefetchw(ptr) prefetch(ptr)
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index f05fbe31576c..e160aeb0138d 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -139,23 +139,60 @@ static inline int cpu_is_xsc3(void)
139#define cpu_is_xscale() 1 139#define cpu_is_xscale() 1
140#endif 140#endif
141 141
142#define set_cr(x) \ 142static inline unsigned int get_cr(void)
143 __asm__ __volatile__( \ 143{
144 "mcr p15, 0, %0, c1, c0, 0 @ set CR" \ 144 unsigned int val;
145 : : "r" (x) : "cc") 145 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
146 146 return val;
147#define get_cr() \ 147}
148 ({ \ 148
149 unsigned int __val; \ 149static inline void set_cr(unsigned int val)
150 __asm__ __volatile__( \ 150{
151 "mrc p15, 0, %0, c1, c0, 0 @ get CR" \ 151 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
152 : "=r" (__val) : : "cc"); \ 152 : : "r" (val) : "cc");
153 __val; \ 153}
154 }) 154
155#define CPACC_FULL(n) (3 << (n * 2))
156#define CPACC_SVC(n) (1 << (n * 2))
157#define CPACC_DISABLE(n) (0 << (n * 2))
158
159static inline unsigned int get_copro_access(void)
160{
161 unsigned int val;
162 asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
163 : "=r" (val) : : "cc");
164 return val;
165}
166
167static inline void set_copro_access(unsigned int val)
168{
169 asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
170 : : "r" (val) : "cc");
171}
155 172
156extern unsigned long cr_no_alignment; /* defined in entry-armv.S */ 173extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
157extern unsigned long cr_alignment; /* defined in entry-armv.S */ 174extern unsigned long cr_alignment; /* defined in entry-armv.S */
158 175
176#ifndef CONFIG_SMP
177static inline void adjust_cr(unsigned long mask, unsigned long set)
178{
179 unsigned long flags, cr;
180
181 mask &= ~CR_A;
182
183 set &= mask;
184
185 local_irq_save(flags);
186
187 cr_no_alignment = (cr_no_alignment & ~mask) | set;
188 cr_alignment = (cr_alignment & ~mask) | set;
189
190 set_cr((get_cr() & ~mask) | set);
191
192 local_irq_restore(flags);
193}
194#endif
195
159#define UDBG_UNDEFINED (1 << 0) 196#define UDBG_UNDEFINED (1 << 0)
160#define UDBG_SYSCALL (1 << 1) 197#define UDBG_SYSCALL (1 << 1)
161#define UDBG_BADABORT (1 << 2) 198#define UDBG_BADABORT (1 << 2)
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index d44c629d8424..32b06eb52819 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -347,6 +347,19 @@
347#define __NR_mbind (__NR_SYSCALL_BASE+319) 347#define __NR_mbind (__NR_SYSCALL_BASE+319)
348#define __NR_get_mempolicy (__NR_SYSCALL_BASE+320) 348#define __NR_get_mempolicy (__NR_SYSCALL_BASE+320)
349#define __NR_set_mempolicy (__NR_SYSCALL_BASE+321) 349#define __NR_set_mempolicy (__NR_SYSCALL_BASE+321)
350#define __NR_openat (__NR_SYSCALL_BASE+322)
351#define __NR_mkdirat (__NR_SYSCALL_BASE+323)
352#define __NR_mknodat (__NR_SYSCALL_BASE+324)
353#define __NR_fchownat (__NR_SYSCALL_BASE+325)
354#define __NR_futimesat (__NR_SYSCALL_BASE+326)
355#define __NR_fstatat64 (__NR_SYSCALL_BASE+327)
356#define __NR_unlinkat (__NR_SYSCALL_BASE+328)
357#define __NR_renameat (__NR_SYSCALL_BASE+329)
358#define __NR_linkat (__NR_SYSCALL_BASE+330)
359#define __NR_symlinkat (__NR_SYSCALL_BASE+331)
360#define __NR_readlinkat (__NR_SYSCALL_BASE+332)
361#define __NR_fchmodat (__NR_SYSCALL_BASE+333)
362#define __NR_faccessat (__NR_SYSCALL_BASE+334)
350 363
351/* 364/*
352 * The following SWIs are ARM private. 365 * The following SWIs are ARM private.
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 07:36:17 -0500