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-rw-r--r--arch/sh/Kconfig2
-rw-r--r--arch/sh/boards/sh03/setup.c26
-rw-r--r--arch/sh/boards/snapgear/setup.c30
-rw-r--r--arch/sh/boards/titan/setup.c30
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c14
-rw-r--r--include/asm-sh/hw_irq.h5
-rw-r--r--include/asm-sh/sh03/io.h9
-rw-r--r--include/asm-sh/snapgear.h12
8 files changed, 19 insertions, 109 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index ceceb05f9dc9..6553325fa437 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -308,7 +308,7 @@ config SH_MPC1211
308 308
309config SH_SH03 309config SH_SH03
310 bool "Interface CTP/PCI-SH03" 310 bool "Interface CTP/PCI-SH03"
311 depends on CPU_SUBTYPE_SH7751 && BROKEN 311 depends on CPU_SUBTYPE_SH7751
312 select CPU_HAS_IPR_IRQ 312 select CPU_HAS_IPR_IRQ
313 select SYS_SUPPORTS_PCI 313 select SYS_SUPPORTS_PCI
314 help 314 help
diff --git a/arch/sh/boards/sh03/setup.c b/arch/sh/boards/sh03/setup.c
index 9c031a8c0a1c..df96312efd45 100644
--- a/arch/sh/boards/sh03/setup.c
+++ b/arch/sh/boards/sh03/setup.c
@@ -15,33 +15,9 @@
15#include <asm/sh03/sh03.h> 15#include <asm/sh03/sh03.h>
16#include <asm/addrspace.h> 16#include <asm/addrspace.h>
17 17
18static struct ipr_data ipr_irq_table[] = {
19 { IRL0_IRQ, 0, IRL0_IPR_POS, IRL0_PRIORITY },
20 { IRL1_IRQ, 0, IRL1_IPR_POS, IRL1_PRIORITY },
21 { IRL2_IRQ, 0, IRL2_IPR_POS, IRL2_PRIORITY },
22 { IRL3_IRQ, 0, IRL3_IPR_POS, IRL3_PRIORITY },
23};
24
25static unsigned long ipr_offsets[] = {
26 INTC_IPRD,
27};
28
29static struct ipr_desc ipr_irq_desc = {
30 .ipr_offsets = ipr_offsets,
31 .nr_offsets = ARRAY_SIZE(ipr_offsets),
32
33 .ipr_data = ipr_irq_table,
34 .nr_irqs = ARRAY_SIZE(ipr_irq_table),
35
36 .chip = {
37 .name = "IPR-sh03",
38 },
39};
40
41static void __init init_sh03_IRQ(void) 18static void __init init_sh03_IRQ(void)
42{ 19{
43 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 20 plat_irq_setup_pins(IRQ_MODE_IRQ);
44 register_ipr_controller(&ipr_irq_desc);
45} 21}
46 22
47extern void *cf_io_base; 23extern void *cf_io_base;
diff --git a/arch/sh/boards/snapgear/setup.c b/arch/sh/boards/snapgear/setup.c
index 84271d85a8dd..2b594f600002 100644
--- a/arch/sh/boards/snapgear/setup.c
+++ b/arch/sh/boards/snapgear/setup.c
@@ -68,37 +68,11 @@ module_init(eraseconfig_init);
68 * IRL3 = crypto 68 * IRL3 = crypto
69 */ 69 */
70 70
71static struct ipr_data ipr_irq_table[] = {
72 { IRL0_IRQ, 0, IRL0_IPR_POS, IRL0_PRIORITY },
73 { IRL1_IRQ, 0, IRL1_IPR_POS, IRL1_PRIORITY },
74 { IRL2_IRQ, 0, IRL2_IPR_POS, IRL2_PRIORITY },
75 { IRL3_IRQ, 0, IRL3_IPR_POS, IRL3_PRIORITY },
76};
77
78static unsigned long ipr_offsets[] = {
79 INTC_IPRD,
80};
81
82static struct ipr_desc ipr_irq_desc = {
83 .ipr_offsets = ipr_offsets,
84 .nr_offsets = ARRAY_SIZE(ipr_offsets),
85
86 .ipr_data = ipr_irq_table,
87 .nr_irqs = ARRAY_SIZE(ipr_irq_table),
88
89 .chip = {
90 .name = "IPR-snapgear",
91 },
92};
93
94static void __init init_snapgear_IRQ(void) 71static void __init init_snapgear_IRQ(void)
95{ 72{
96 /* enable individual interrupt mode for externals */
97 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
98
99 printk("Setup SnapGear IRQ/IPR ...\n"); 73 printk("Setup SnapGear IRQ/IPR ...\n");
100 74 /* enable individual interrupt mode for externals */
101 register_ipr_controller(&ipr_irq_desc); 75 plat_irq_setup_pins(IRQ_MODE_IRQ);
102} 76}
103 77
104/* 78/*
diff --git a/arch/sh/boards/titan/setup.c b/arch/sh/boards/titan/setup.c
index 606d25a4b870..5de3b2ad71af 100644
--- a/arch/sh/boards/titan/setup.c
+++ b/arch/sh/boards/titan/setup.c
@@ -12,38 +12,10 @@
12#include <asm/titan.h> 12#include <asm/titan.h>
13#include <asm/io.h> 13#include <asm/io.h>
14 14
15static struct ipr_data ipr_irq_table[] = {
16 /* IRQ, IPR idx, shift, prio */
17 { TITAN_IRQ_WAN, 3, 12, 8 }, /* eth0 (WAN) */
18 { TITAN_IRQ_LAN, 3, 8, 8 }, /* eth1 (LAN) */
19 { TITAN_IRQ_MPCIA, 3, 4, 8 }, /* mPCI A (top) */
20 { TITAN_IRQ_USB, 3, 0, 8 }, /* mPCI B (bottom), USB */
21};
22
23static unsigned long ipr_offsets[] = { /* stolen from setup-sh7750.c */
24 0xffd00004UL, /* 0: IPRA */
25 0xffd00008UL, /* 1: IPRB */
26 0xffd0000cUL, /* 2: IPRC */
27 0xffd00010UL, /* 3: IPRD */
28};
29
30static struct ipr_desc ipr_irq_desc = {
31 .ipr_offsets = ipr_offsets,
32 .nr_offsets = ARRAY_SIZE(ipr_offsets),
33
34 .ipr_data = ipr_irq_table,
35 .nr_irqs = ARRAY_SIZE(ipr_irq_table),
36
37 .chip = {
38 .name = "IPR-titan",
39 },
40};
41static void __init init_titan_irq(void) 15static void __init init_titan_irq(void)
42{ 16{
43 /* enable individual interrupt mode for externals */ 17 /* enable individual interrupt mode for externals */
44 ipr_irq_enable_irlm(); 18 plat_irq_setup_pins(IRQ_MODE_IRQ);
45 /* register ipr irqs */
46 register_ipr_controller(&ipr_irq_desc);
47} 19}
48 20
49static struct sh_machine_vector mv_titan __initmv = { 21static struct sh_machine_vector mv_titan __initmv = {
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index f2286de22bd5..e313be249840 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -282,13 +282,19 @@ void __init plat_irq_setup(void)
282#define INTC_ICR 0xffd00000UL 282#define INTC_ICR 0xffd00000UL
283#define INTC_ICR_IRLM (1<<7) 283#define INTC_ICR_IRLM (1<<7)
284 284
285/* enable individual interrupt mode for external interupts */ 285void __init plat_irq_setup_pins(int mode)
286void __init ipr_irq_enable_irlm(void)
287{ 286{
288#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091) 287#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
289 BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */ 288 BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
289 return;
290#endif 290#endif
291 register_intc_controller(&intc_desc_irlm);
292 291
293 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 292 switch (mode) {
293 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
294 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
295 register_intc_controller(&intc_desc_irlm);
296 break;
297 default:
298 BUG();
299 }
294} 300}
diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index 921ddec6ccf4..8f5bf98d053e 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -41,11 +41,6 @@ struct ipr_desc {
41 41
42void register_ipr_controller(struct ipr_desc *); 42void register_ipr_controller(struct ipr_desc *);
43 43
44/*
45 * Enable individual interrupt mode for external IPR IRQs.
46 */
47void __init ipr_irq_enable_irlm(void);
48
49typedef unsigned char intc_enum; 44typedef unsigned char intc_enum;
50 45
51struct intc_vect { 46struct intc_vect {
diff --git a/include/asm-sh/sh03/io.h b/include/asm-sh/sh03/io.h
index 4ff1eb900301..c39c785bba94 100644
--- a/include/asm-sh/sh03/io.h
+++ b/include/asm-sh/sh03/io.h
@@ -11,22 +11,13 @@
11 11
12#include <linux/time.h> 12#include <linux/time.h>
13 13
14#define INTC_IPRD 0xffd00010UL
15
16#define IRL0_IRQ 2 14#define IRL0_IRQ 2
17#define IRL0_IPR_POS 3
18#define IRL0_PRIORITY 13 15#define IRL0_PRIORITY 13
19
20#define IRL1_IRQ 5 16#define IRL1_IRQ 5
21#define IRL1_IPR_POS 2
22#define IRL1_PRIORITY 10 17#define IRL1_PRIORITY 10
23
24#define IRL2_IRQ 8 18#define IRL2_IRQ 8
25#define IRL2_IPR_POS 1
26#define IRL2_PRIORITY 7 19#define IRL2_PRIORITY 7
27
28#define IRL3_IRQ 11 20#define IRL3_IRQ 11
29#define IRL3_IPR_POS 0
30#define IRL3_PRIORITY 4 21#define IRL3_PRIORITY 4
31 22
32void heartbeat_sh03(void); 23void heartbeat_sh03(void);
diff --git a/include/asm-sh/snapgear.h b/include/asm-sh/snapgear.h
index 3554e3a74e99..042d95f51c4d 100644
--- a/include/asm-sh/snapgear.h
+++ b/include/asm-sh/snapgear.h
@@ -19,20 +19,16 @@
19 * is the interrupt :-) 19 * is the interrupt :-)
20 */ 20 */
21 21
22#define IRL0_IRQ 2 22#define IRL0_IRQ 2
23#define IRL0_IPR_POS 3
24#define IRL0_PRIORITY 13 23#define IRL0_PRIORITY 13
25 24
26#define IRL1_IRQ 5 25#define IRL1_IRQ 5
27#define IRL1_IPR_POS 2
28#define IRL1_PRIORITY 10 26#define IRL1_PRIORITY 10
29 27
30#define IRL2_IRQ 8 28#define IRL2_IRQ 8
31#define IRL2_IPR_POS 1
32#define IRL2_PRIORITY 7 29#define IRL2_PRIORITY 7
33 30
34#define IRL3_IRQ 11 31#define IRL3_IRQ 11
35#define IRL3_IPR_POS 0
36#define IRL3_PRIORITY 4 32#define IRL3_PRIORITY 4
37#endif 33#endif
38 34