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-rw-r--r--arch/sh/kernel/cpu/sh2/probe.c19
-rw-r--r--arch/sh/kernel/cpu/sh2a/probe.c18
-rw-r--r--arch/sh/kernel/cpu/sh3/probe.c47
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c171
-rw-r--r--include/asm-sh/processor.h1
5 files changed, 126 insertions, 130 deletions
diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c
index abbf17427e52..5916d9096b99 100644
--- a/arch/sh/kernel/cpu/sh2/probe.c
+++ b/arch/sh/kernel/cpu/sh2/probe.c
@@ -10,26 +10,25 @@
10 * for more details. 10 * for more details.
11 */ 11 */
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/smp.h>
14#include <asm/processor.h> 13#include <asm/processor.h>
15#include <asm/cache.h> 14#include <asm/cache.h>
16 15
17int __init detect_cpu_and_cache_system(void) 16int __init detect_cpu_and_cache_system(void)
18{ 17{
19#if defined(CONFIG_CPU_SUBTYPE_SH7619) 18#if defined(CONFIG_CPU_SUBTYPE_SH7619)
20 current_cpu_data.type = CPU_SH7619; 19 boot_cpu_data.type = CPU_SH7619;
21 current_cpu_data.dcache.ways = 4; 20 boot_cpu_data.dcache.ways = 4;
22 current_cpu_data.dcache.way_incr = (1<<12); 21 boot_cpu_data.dcache.way_incr = (1<<12);
23 current_cpu_data.dcache.sets = 256; 22 boot_cpu_data.dcache.sets = 256;
24 current_cpu_data.dcache.entry_shift = 4; 23 boot_cpu_data.dcache.entry_shift = 4;
25 current_cpu_data.dcache.linesz = L1_CACHE_BYTES; 24 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
26 current_cpu_data.dcache.flags = 0; 25 boot_cpu_data.dcache.flags = 0;
27#endif 26#endif
28 /* 27 /*
29 * SH-2 doesn't have separate caches 28 * SH-2 doesn't have separate caches
30 */ 29 */
31 current_cpu_data.dcache.flags |= SH_CACHE_COMBINED; 30 boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
32 current_cpu_data.icache = current_cpu_data.dcache; 31 boot_cpu_data.icache = boot_cpu_data.dcache;
33 32
34 return 0; 33 return 0;
35} 34}
diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c
index f455c3509789..6d02465704b9 100644
--- a/arch/sh/kernel/cpu/sh2a/probe.c
+++ b/arch/sh/kernel/cpu/sh2a/probe.c
@@ -17,15 +17,15 @@
17int __init detect_cpu_and_cache_system(void) 17int __init detect_cpu_and_cache_system(void)
18{ 18{
19 /* Just SH7206 for now .. */ 19 /* Just SH7206 for now .. */
20 current_cpu_data.type = CPU_SH7206; 20 boot_cpu_data.type = CPU_SH7206;
21 current_cpu_data.flags |= CPU_HAS_OP32; 21 boot_cpu_data.flags |= CPU_HAS_OP32;
22 22
23 current_cpu_data.dcache.ways = 4; 23 boot_cpu_data.dcache.ways = 4;
24 current_cpu_data.dcache.way_incr = (1 << 11); 24 boot_cpu_data.dcache.way_incr = (1 << 11);
25 current_cpu_data.dcache.sets = 128; 25 boot_cpu_data.dcache.sets = 128;
26 current_cpu_data.dcache.entry_shift = 4; 26 boot_cpu_data.dcache.entry_shift = 4;
27 current_cpu_data.dcache.linesz = L1_CACHE_BYTES; 27 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
28 current_cpu_data.dcache.flags = 0; 28 boot_cpu_data.dcache.flags = 0;
29 29
30 /* 30 /*
31 * The icache is the same as the dcache as far as this setup is 31 * The icache is the same as the dcache as far as this setup is
@@ -33,7 +33,7 @@ int __init detect_cpu_and_cache_system(void)
33 * lacks the U bit that the dcache has, none of this has any bearing 33 * lacks the U bit that the dcache has, none of this has any bearing
34 * on the cache info. 34 * on the cache info.
35 */ 35 */
36 current_cpu_data.icache = current_cpu_data.dcache; 36 boot_cpu_data.icache = boot_cpu_data.dcache;
37 37
38 return 0; 38 return 0;
39} 39}
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index 1a66cf636a9d..bf579e061e09 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -50,47 +50,47 @@ int __init detect_cpu_and_cache_system(void)
50 50
51 back_to_P1(); 51 back_to_P1();
52 52
53 current_cpu_data.dcache.ways = 4; 53 boot_cpu_data.dcache.ways = 4;
54 current_cpu_data.dcache.entry_shift = 4; 54 boot_cpu_data.dcache.entry_shift = 4;
55 current_cpu_data.dcache.linesz = L1_CACHE_BYTES; 55 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
56 current_cpu_data.dcache.flags = 0; 56 boot_cpu_data.dcache.flags = 0;
57 57
58 /* 58 /*
59 * 7709A/7729 has 16K cache (256-entry), while 7702 has only 59 * 7709A/7729 has 16K cache (256-entry), while 7702 has only
60 * 2K(direct) 7702 is not supported (yet) 60 * 2K(direct) 7702 is not supported (yet)
61 */ 61 */
62 if (data0 == data1 && data2 == data3) { /* Shadow */ 62 if (data0 == data1 && data2 == data3) { /* Shadow */
63 current_cpu_data.dcache.way_incr = (1 << 11); 63 boot_cpu_data.dcache.way_incr = (1 << 11);
64 current_cpu_data.dcache.entry_mask = 0x7f0; 64 boot_cpu_data.dcache.entry_mask = 0x7f0;
65 current_cpu_data.dcache.sets = 128; 65 boot_cpu_data.dcache.sets = 128;
66 current_cpu_data.type = CPU_SH7708; 66 boot_cpu_data.type = CPU_SH7708;
67 67
68 current_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC; 68 boot_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC;
69 } else { /* 7709A or 7729 */ 69 } else { /* 7709A or 7729 */
70 current_cpu_data.dcache.way_incr = (1 << 12); 70 boot_cpu_data.dcache.way_incr = (1 << 12);
71 current_cpu_data.dcache.entry_mask = 0xff0; 71 boot_cpu_data.dcache.entry_mask = 0xff0;
72 current_cpu_data.dcache.sets = 256; 72 boot_cpu_data.dcache.sets = 256;
73 current_cpu_data.type = CPU_SH7729; 73 boot_cpu_data.type = CPU_SH7729;
74 74
75#if defined(CONFIG_CPU_SUBTYPE_SH7706) 75#if defined(CONFIG_CPU_SUBTYPE_SH7706)
76 current_cpu_data.type = CPU_SH7706; 76 boot_cpu_data.type = CPU_SH7706;
77#endif 77#endif
78#if defined(CONFIG_CPU_SUBTYPE_SH7710) 78#if defined(CONFIG_CPU_SUBTYPE_SH7710)
79 current_cpu_data.type = CPU_SH7710; 79 boot_cpu_data.type = CPU_SH7710;
80#endif 80#endif
81#if defined(CONFIG_CPU_SUBTYPE_SH7712) 81#if defined(CONFIG_CPU_SUBTYPE_SH7712)
82 current_cpu_data.type = CPU_SH7712; 82 boot_cpu_data.type = CPU_SH7712;
83#endif 83#endif
84#if defined(CONFIG_CPU_SUBTYPE_SH7720) 84#if defined(CONFIG_CPU_SUBTYPE_SH7720)
85 current_cpu_data.type = CPU_SH7720; 85 boot_cpu_data.type = CPU_SH7720;
86#endif 86#endif
87#if defined(CONFIG_CPU_SUBTYPE_SH7705) 87#if defined(CONFIG_CPU_SUBTYPE_SH7705)
88 current_cpu_data.type = CPU_SH7705; 88 boot_cpu_data.type = CPU_SH7705;
89 89
90#if defined(CONFIG_SH7705_CACHE_32KB) 90#if defined(CONFIG_SH7705_CACHE_32KB)
91 current_cpu_data.dcache.way_incr = (1 << 13); 91 boot_cpu_data.dcache.way_incr = (1 << 13);
92 current_cpu_data.dcache.entry_mask = 0x1ff0; 92 boot_cpu_data.dcache.entry_mask = 0x1ff0;
93 current_cpu_data.dcache.sets = 512; 93 boot_cpu_data.dcache.sets = 512;
94 ctrl_outl(CCR_CACHE_32KB, CCR3); 94 ctrl_outl(CCR_CACHE_32KB, CCR3);
95#else 95#else
96 ctrl_outl(CCR_CACHE_16KB, CCR3); 96 ctrl_outl(CCR_CACHE_16KB, CCR3);
@@ -101,9 +101,8 @@ int __init detect_cpu_and_cache_system(void)
101 /* 101 /*
102 * SH-3 doesn't have separate caches 102 * SH-3 doesn't have separate caches
103 */ 103 */
104 current_cpu_data.dcache.flags |= SH_CACHE_COMBINED; 104 boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
105 current_cpu_data.icache = current_cpu_data.dcache; 105 boot_cpu_data.icache = boot_cpu_data.dcache;
106 106
107 return 0; 107 return 0;
108} 108}
109
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 8f318a4fe722..21375d777e99 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -12,7 +12,6 @@
12 */ 12 */
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/smp.h>
16#include <asm/processor.h> 15#include <asm/processor.h>
17#include <asm/cache.h> 16#include <asm/cache.h>
18 17
@@ -36,34 +35,34 @@ int __init detect_cpu_and_cache_system(void)
36 /* 35 /*
37 * Setup some sane SH-4 defaults for the icache 36 * Setup some sane SH-4 defaults for the icache
38 */ 37 */
39 current_cpu_data.icache.way_incr = (1 << 13); 38 boot_cpu_data.icache.way_incr = (1 << 13);
40 current_cpu_data.icache.entry_shift = 5; 39 boot_cpu_data.icache.entry_shift = 5;
41 current_cpu_data.icache.sets = 256; 40 boot_cpu_data.icache.sets = 256;
42 current_cpu_data.icache.ways = 1; 41 boot_cpu_data.icache.ways = 1;
43 current_cpu_data.icache.linesz = L1_CACHE_BYTES; 42 boot_cpu_data.icache.linesz = L1_CACHE_BYTES;
44 43
45 /* 44 /*
46 * And again for the dcache .. 45 * And again for the dcache ..
47 */ 46 */
48 current_cpu_data.dcache.way_incr = (1 << 14); 47 boot_cpu_data.dcache.way_incr = (1 << 14);
49 current_cpu_data.dcache.entry_shift = 5; 48 boot_cpu_data.dcache.entry_shift = 5;
50 current_cpu_data.dcache.sets = 512; 49 boot_cpu_data.dcache.sets = 512;
51 current_cpu_data.dcache.ways = 1; 50 boot_cpu_data.dcache.ways = 1;
52 current_cpu_data.dcache.linesz = L1_CACHE_BYTES; 51 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
53 52
54 /* 53 /*
55 * Setup some generic flags we can probe on SH-4A parts 54 * Setup some generic flags we can probe on SH-4A parts
56 */ 55 */
57 if (((pvr >> 16) & 0xff) == 0x10) { 56 if (((pvr >> 16) & 0xff) == 0x10) {
58 if ((cvr & 0x10000000) == 0) 57 if ((cvr & 0x10000000) == 0)
59 current_cpu_data.flags |= CPU_HAS_DSP; 58 boot_cpu_data.flags |= CPU_HAS_DSP;
60 59
61 current_cpu_data.flags |= CPU_HAS_LLSC; 60 boot_cpu_data.flags |= CPU_HAS_LLSC;
62 } 61 }
63 62
64 /* FPU detection works for everyone */ 63 /* FPU detection works for everyone */
65 if ((cvr & 0x20000000) == 1) 64 if ((cvr & 0x20000000) == 1)
66 current_cpu_data.flags |= CPU_HAS_FPU; 65 boot_cpu_data.flags |= CPU_HAS_FPU;
67 66
68 /* Mask off the upper chip ID */ 67 /* Mask off the upper chip ID */
69 pvr &= 0xffff; 68 pvr &= 0xffff;
@@ -74,140 +73,140 @@ int __init detect_cpu_and_cache_system(void)
74 */ 73 */
75 switch (pvr) { 74 switch (pvr) {
76 case 0x205: 75 case 0x205:
77 current_cpu_data.type = CPU_SH7750; 76 boot_cpu_data.type = CPU_SH7750;
78 current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | 77 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
79 CPU_HAS_PERF_COUNTER; 78 CPU_HAS_PERF_COUNTER;
80 break; 79 break;
81 case 0x206: 80 case 0x206:
82 current_cpu_data.type = CPU_SH7750S; 81 boot_cpu_data.type = CPU_SH7750S;
83 current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | 82 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
84 CPU_HAS_PERF_COUNTER; 83 CPU_HAS_PERF_COUNTER;
85 break; 84 break;
86 case 0x1100: 85 case 0x1100:
87 current_cpu_data.type = CPU_SH7751; 86 boot_cpu_data.type = CPU_SH7751;
88 current_cpu_data.flags |= CPU_HAS_FPU; 87 boot_cpu_data.flags |= CPU_HAS_FPU;
89 break; 88 break;
90 case 0x2001: 89 case 0x2001:
91 case 0x2004: 90 case 0x2004:
92 current_cpu_data.type = CPU_SH7770; 91 boot_cpu_data.type = CPU_SH7770;
93 current_cpu_data.icache.ways = 4; 92 boot_cpu_data.icache.ways = 4;
94 current_cpu_data.dcache.ways = 4; 93 boot_cpu_data.dcache.ways = 4;
95 94
96 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC; 95 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
97 break; 96 break;
98 case 0x2006: 97 case 0x2006:
99 case 0x200A: 98 case 0x200A:
100 if (prr == 0x61) 99 if (prr == 0x61)
101 current_cpu_data.type = CPU_SH7781; 100 boot_cpu_data.type = CPU_SH7781;
102 else 101 else
103 current_cpu_data.type = CPU_SH7780; 102 boot_cpu_data.type = CPU_SH7780;
104 103
105 current_cpu_data.icache.ways = 4; 104 boot_cpu_data.icache.ways = 4;
106 current_cpu_data.dcache.ways = 4; 105 boot_cpu_data.dcache.ways = 4;
107 106
108 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | 107 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
109 CPU_HAS_LLSC; 108 CPU_HAS_LLSC;
110 break; 109 break;
111 case 0x3000: 110 case 0x3000:
112 case 0x3003: 111 case 0x3003:
113 case 0x3009: 112 case 0x3009:
114 current_cpu_data.type = CPU_SH7343; 113 boot_cpu_data.type = CPU_SH7343;
115 current_cpu_data.icache.ways = 4; 114 boot_cpu_data.icache.ways = 4;
116 current_cpu_data.dcache.ways = 4; 115 boot_cpu_data.dcache.ways = 4;
117 current_cpu_data.flags |= CPU_HAS_LLSC; 116 boot_cpu_data.flags |= CPU_HAS_LLSC;
118 break; 117 break;
119 case 0x3004: 118 case 0x3004:
120 case 0x3007: 119 case 0x3007:
121 current_cpu_data.type = CPU_SH7785; 120 boot_cpu_data.type = CPU_SH7785;
122 current_cpu_data.icache.ways = 4; 121 boot_cpu_data.icache.ways = 4;
123 current_cpu_data.dcache.ways = 4; 122 boot_cpu_data.dcache.ways = 4;
124 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | 123 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
125 CPU_HAS_LLSC; 124 CPU_HAS_LLSC;
126 break; 125 break;
127 case 0x3008: 126 case 0x3008:
128 if (prr == 0xa0) { 127 if (prr == 0xa0) {
129 current_cpu_data.type = CPU_SH7722; 128 boot_cpu_data.type = CPU_SH7722;
130 current_cpu_data.icache.ways = 4; 129 boot_cpu_data.icache.ways = 4;
131 current_cpu_data.dcache.ways = 4; 130 boot_cpu_data.dcache.ways = 4;
132 current_cpu_data.flags |= CPU_HAS_LLSC; 131 boot_cpu_data.flags |= CPU_HAS_LLSC;
133 } 132 }
134 break; 133 break;
135 case 0x4000: /* 1st cut */ 134 case 0x4000: /* 1st cut */
136 case 0x4001: /* 2nd cut */ 135 case 0x4001: /* 2nd cut */
137 current_cpu_data.type = CPU_SHX3; 136 boot_cpu_data.type = CPU_SHX3;
138 current_cpu_data.icache.ways = 4; 137 boot_cpu_data.icache.ways = 4;
139 current_cpu_data.dcache.ways = 4; 138 boot_cpu_data.dcache.ways = 4;
140 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | 139 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
141 CPU_HAS_LLSC; 140 CPU_HAS_LLSC;
142 break; 141 break;
143 case 0x8000: 142 case 0x8000:
144 current_cpu_data.type = CPU_ST40RA; 143 boot_cpu_data.type = CPU_ST40RA;
145 current_cpu_data.flags |= CPU_HAS_FPU; 144 boot_cpu_data.flags |= CPU_HAS_FPU;
146 break; 145 break;
147 case 0x8100: 146 case 0x8100:
148 current_cpu_data.type = CPU_ST40GX1; 147 boot_cpu_data.type = CPU_ST40GX1;
149 current_cpu_data.flags |= CPU_HAS_FPU; 148 boot_cpu_data.flags |= CPU_HAS_FPU;
150 break; 149 break;
151 case 0x700: 150 case 0x700:
152 current_cpu_data.type = CPU_SH4_501; 151 boot_cpu_data.type = CPU_SH4_501;
153 current_cpu_data.icache.ways = 2; 152 boot_cpu_data.icache.ways = 2;
154 current_cpu_data.dcache.ways = 2; 153 boot_cpu_data.dcache.ways = 2;
155 break; 154 break;
156 case 0x600: 155 case 0x600:
157 current_cpu_data.type = CPU_SH4_202; 156 boot_cpu_data.type = CPU_SH4_202;
158 current_cpu_data.icache.ways = 2; 157 boot_cpu_data.icache.ways = 2;
159 current_cpu_data.dcache.ways = 2; 158 boot_cpu_data.dcache.ways = 2;
160 current_cpu_data.flags |= CPU_HAS_FPU; 159 boot_cpu_data.flags |= CPU_HAS_FPU;
161 break; 160 break;
162 case 0x500 ... 0x501: 161 case 0x500 ... 0x501:
163 switch (prr) { 162 switch (prr) {
164 case 0x10: 163 case 0x10:
165 current_cpu_data.type = CPU_SH7750R; 164 boot_cpu_data.type = CPU_SH7750R;
166 break; 165 break;
167 case 0x11: 166 case 0x11:
168 current_cpu_data.type = CPU_SH7751R; 167 boot_cpu_data.type = CPU_SH7751R;
169 break; 168 break;
170 case 0x50 ... 0x5f: 169 case 0x50 ... 0x5f:
171 current_cpu_data.type = CPU_SH7760; 170 boot_cpu_data.type = CPU_SH7760;
172 break; 171 break;
173 } 172 }
174 173
175 current_cpu_data.icache.ways = 2; 174 boot_cpu_data.icache.ways = 2;
176 current_cpu_data.dcache.ways = 2; 175 boot_cpu_data.dcache.ways = 2;
177 176
178 current_cpu_data.flags |= CPU_HAS_FPU; 177 boot_cpu_data.flags |= CPU_HAS_FPU;
179 178
180 break; 179 break;
181 default: 180 default:
182 current_cpu_data.type = CPU_SH_NONE; 181 boot_cpu_data.type = CPU_SH_NONE;
183 break; 182 break;
184 } 183 }
185 184
186#ifdef CONFIG_SH_DIRECT_MAPPED 185#ifdef CONFIG_SH_DIRECT_MAPPED
187 current_cpu_data.icache.ways = 1; 186 boot_cpu_data.icache.ways = 1;
188 current_cpu_data.dcache.ways = 1; 187 boot_cpu_data.dcache.ways = 1;
189#endif 188#endif
190 189
191#ifdef CONFIG_CPU_HAS_PTEA 190#ifdef CONFIG_CPU_HAS_PTEA
192 current_cpu_data.flags |= CPU_HAS_PTEA; 191 boot_cpu_data.flags |= CPU_HAS_PTEA;
193#endif 192#endif
194 193
195 /* 194 /*
196 * On anything that's not a direct-mapped cache, look to the CVR 195 * On anything that's not a direct-mapped cache, look to the CVR
197 * for I/D-cache specifics. 196 * for I/D-cache specifics.
198 */ 197 */
199 if (current_cpu_data.icache.ways > 1) { 198 if (boot_cpu_data.icache.ways > 1) {
200 size = sizes[(cvr >> 20) & 0xf]; 199 size = sizes[(cvr >> 20) & 0xf];
201 current_cpu_data.icache.way_incr = (size >> 1); 200 boot_cpu_data.icache.way_incr = (size >> 1);
202 current_cpu_data.icache.sets = (size >> 6); 201 boot_cpu_data.icache.sets = (size >> 6);
203 202
204 } 203 }
205 204
206 /* And the rest of the D-cache */ 205 /* And the rest of the D-cache */
207 if (current_cpu_data.dcache.ways > 1) { 206 if (boot_cpu_data.dcache.ways > 1) {
208 size = sizes[(cvr >> 16) & 0xf]; 207 size = sizes[(cvr >> 16) & 0xf];
209 current_cpu_data.dcache.way_incr = (size >> 1); 208 boot_cpu_data.dcache.way_incr = (size >> 1);
210 current_cpu_data.dcache.sets = (size >> 6); 209 boot_cpu_data.dcache.sets = (size >> 6);
211 } 210 }
212 211
213 /* 212 /*
@@ -215,7 +214,7 @@ int __init detect_cpu_and_cache_system(void)
215 * 214 *
216 * SH-4A's have an optional PIPT L2. 215 * SH-4A's have an optional PIPT L2.
217 */ 216 */
218 if (current_cpu_data.flags & CPU_HAS_L2_CACHE) { 217 if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
219 /* 218 /*
220 * Size calculation is much more sensible 219 * Size calculation is much more sensible
221 * than it is for the L1. 220 * than it is for the L1.
@@ -226,22 +225,22 @@ int __init detect_cpu_and_cache_system(void)
226 225
227 BUG_ON(!size); 226 BUG_ON(!size);
228 227
229 current_cpu_data.scache.way_incr = (1 << 16); 228 boot_cpu_data.scache.way_incr = (1 << 16);
230 current_cpu_data.scache.entry_shift = 5; 229 boot_cpu_data.scache.entry_shift = 5;
231 current_cpu_data.scache.ways = 4; 230 boot_cpu_data.scache.ways = 4;
232 current_cpu_data.scache.linesz = L1_CACHE_BYTES; 231 boot_cpu_data.scache.linesz = L1_CACHE_BYTES;
233 232
234 current_cpu_data.scache.entry_mask = 233 boot_cpu_data.scache.entry_mask =
235 (current_cpu_data.scache.way_incr - 234 (boot_cpu_data.scache.way_incr -
236 current_cpu_data.scache.linesz); 235 boot_cpu_data.scache.linesz);
237 236
238 current_cpu_data.scache.sets = size / 237 boot_cpu_data.scache.sets = size /
239 (current_cpu_data.scache.linesz * 238 (boot_cpu_data.scache.linesz *
240 current_cpu_data.scache.ways); 239 boot_cpu_data.scache.ways);
241 240
242 current_cpu_data.scache.way_size = 241 boot_cpu_data.scache.way_size =
243 (current_cpu_data.scache.sets * 242 (boot_cpu_data.scache.sets *
244 current_cpu_data.scache.linesz); 243 boot_cpu_data.scache.linesz);
245 } 244 }
246 245
247 return 0; 246 return 0;
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 9f3ee775fe13..4f2922a1979c 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -10,7 +10,6 @@
10#ifdef __KERNEL__ 10#ifdef __KERNEL__
11 11
12#include <linux/compiler.h> 12#include <linux/compiler.h>
13#include <linux/smp.h>
14#include <asm/page.h> 13#include <asm/page.h>
15#include <asm/types.h> 14#include <asm/types.h>
16#include <asm/cache.h> 15#include <asm/cache.h>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 14:28:45 -0500