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-rw-r--r--arch/arm/mach-omap1/sram.S6
-rw-r--r--arch/arm/mach-omap2/Makefile6
-rw-r--r--arch/arm/mach-omap2/clock.c3
-rw-r--r--arch/arm/mach-omap2/prcm-common.h1
-rw-r--r--arch/arm/mach-omap2/prm.h18
-rw-r--r--arch/arm/mach-omap2/sram242x.S105
-rw-r--r--arch/arm/mach-omap2/sram243x.S321
-rw-r--r--arch/arm/plat-omap/sram.c211
-rw-r--r--include/asm-arm/arch-omap/sram.h37
9 files changed, 604 insertions, 104 deletions
diff --git a/arch/arm/mach-omap1/sram.S b/arch/arm/mach-omap1/sram.S
index 9e1813c77e05..126d252062d7 100644
--- a/arch/arm/mach-omap1/sram.S
+++ b/arch/arm/mach-omap1/sram.S
@@ -18,7 +18,7 @@
18/* 18/*
19 * Reprograms ULPD and CKCTL. 19 * Reprograms ULPD and CKCTL.
20 */ 20 */
21ENTRY(sram_reprogram_clock) 21ENTRY(omap1_sram_reprogram_clock)
22 stmfd sp!, {r0 - r12, lr} @ save registers on stack 22 stmfd sp!, {r0 - r12, lr} @ save registers on stack
23 23
24 mov r2, #IO_ADDRESS(DPLL_CTL) & 0xff000000 24 mov r2, #IO_ADDRESS(DPLL_CTL) & 0xff000000
@@ -53,5 +53,5 @@ lock: ldrh r4, [r2], #0 @ read back dpll value
53 53
54out: 54out:
55 ldmfd sp!, {r0 - r12, pc} @ restore regs and return 55 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
56ENTRY(sram_reprogram_clock_sz) 56ENTRY(omap1_sram_reprogram_clock_sz)
57 .word . - sram_reprogram_clock 57 .word . - omap1_sram_reprogram_clock
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 6c59b267105d..c2477428e351 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,9 +3,13 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := irq.o id.o io.o sram242x.o memory.o control.o prcm.o clock.o mux.o \ 6obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \
7 devices.o serial.o gpmc.o timer-gp.o 7 devices.o serial.o gpmc.o timer-gp.o
8 8
9# Functions loaded to SRAM
10obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
11obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
12
9# Power Management 13# Power Management
10obj-$(CONFIG_PM) += pm.o sleep.o 14obj-$(CONFIG_PM) += pm.o sleep.o
11 15
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ab9fc57d25f1..0243480e8bfe 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -603,7 +603,8 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
603 clk->rate = clk->parent->rate / new_div; 603 clk->rate = clk->parent->rate / new_div;
604 604
605 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { 605 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
606 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); 606 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
607 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
607 wmb(); 608 wmb();
608 } 609 }
609 610
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index cacb34086e35..54c32f482131 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -32,6 +32,7 @@
32 32
33 33
34/* Chip-specific module offsets */ 34/* Chip-specific module offsets */
35#define OMAP24XX_GR_MOD OCP_MOD
35#define OMAP24XX_DSP_MOD 0x800 36#define OMAP24XX_DSP_MOD 0x800
36 37
37#define OMAP2430_MDM_MOD 0xc00 38#define OMAP2430_MDM_MOD 0xc00
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 618f8111658a..dcdb35bfa0c0 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -38,13 +38,29 @@
38 * 38 *
39 */ 39 */
40 40
41/* Global 24xx registers in GR_MOD (Same as OCP_MOD for 24xx) */
42#define OMAP24XX_PRCM_VOLTCTRL_OFFSET 0x0050
43#define OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET 0x0080
44
45/* 242x GR_MOD registers, use these only for assembly code */
46#define OMAP242X_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \
47 OMAP24XX_PRCM_VOLTCTRL_OFFSET)
48#define OMAP242X_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \
49 OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET)
50
51/* 243x GR_MOD registers, use these only for assembly code */
52#define OMAP243X_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \
53 OMAP24XX_PRCM_VOLTCTRL_OFFSET)
54#define OMAP243X_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \
55 OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET)
56
57/* These will disappear */
41#define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000) 58#define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000)
42#define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010) 59#define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010)
43 60
44#define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) 61#define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
45#define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) 62#define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
46 63
47#define OMAP24XX_PRCM_VOLTCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0050)
48#define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054) 64#define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054)
49#define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060) 65#define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060)
50#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070) 66#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070)
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index 4a9e49140716..4c274510f3e9 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/sram-fn.S 2 * linux/arch/arm/mach-omap2/sram242x.S
3 * 3 *
4 * Omap2 specific functions that need to be run in internal SRAM 4 * Omap2 specific functions that need to be run in internal SRAM
5 * 5 *
@@ -27,22 +27,20 @@
27#include <asm/arch/io.h> 27#include <asm/arch/io.h>
28#include <asm/hardware.h> 28#include <asm/hardware.h>
29 29
30#include "sdrc.h"
31#include "prm.h" 30#include "prm.h"
32#include "cm.h" 31#include "cm.h"
33 32#include "sdrc.h"
34#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
35 33
36 .text 34 .text
37 35
38ENTRY(sram_ddr_init) 36ENTRY(omap242x_sram_ddr_init)
39 stmfd sp!, {r0 - r12, lr} @ save registers on stack 37 stmfd sp!, {r0 - r12, lr} @ save registers on stack
40 38
41 mov r12, r2 @ capture CS1 vs CS0 39 mov r12, r2 @ capture CS1 vs CS0
42 mov r8, r3 @ capture force parameter 40 mov r8, r3 @ capture force parameter
43 41
44 /* frequency shift down */ 42 /* frequency shift down */
45 ldr r2, cm_clksel2_pll @ get address of dpllout reg 43 ldr r2, omap242x_sdi_cm_clksel2_pll @ get address of dpllout reg
46 mov r3, #0x1 @ value for 1x operation 44 mov r3, #0x1 @ value for 1x operation
47 str r3, [r2] @ go to L1-freq operation 45 str r3, [r2] @ go to L1-freq operation
48 46
@@ -51,7 +49,7 @@ ENTRY(sram_ddr_init)
51 bl voltage_shift @ go drop voltage 49 bl voltage_shift @ go drop voltage
52 50
53 /* dll lock mode */ 51 /* dll lock mode */
54 ldr r11, sdrc_dlla_ctrl @ addr of dlla ctrl 52 ldr r11, omap242x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
55 ldr r10, [r11] @ get current val 53 ldr r10, [r11] @ get current val
56 cmp r12, #0x1 @ cs1 base (2422 es2.05/1) 54 cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
57 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB 55 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
@@ -102,7 +100,7 @@ i_dll_delay:
102 * wait for it to finish, use 32k sync counter, 1tick=31uS. 100 * wait for it to finish, use 32k sync counter, 1tick=31uS.
103 */ 101 */
104voltage_shift: 102voltage_shift:
105 ldr r4, prcm_voltctrl @ get addr of volt ctrl. 103 ldr r4, omap242x_sdi_prcm_voltctrl @ get addr of volt ctrl.
106 ldr r5, [r4] @ get value. 104 ldr r5, [r4] @ get value.
107 ldr r6, prcm_mask_val @ get value of mask 105 ldr r6, prcm_mask_val @ get value of mask
108 and r5, r5, r6 @ apply mask to clear bits 106 and r5, r5, r6 @ apply mask to clear bits
@@ -112,7 +110,7 @@ voltage_shift:
112 orr r5, r5, r3 @ build value for force 110 orr r5, r5, r3 @ build value for force
113 str r5, [r4] @ Force transition to L1 111 str r5, [r4] @ Force transition to L1
114 112
115 ldr r3, timer_32ksynct_cr @ get addr of counter 113 ldr r3, omap242x_sdi_timer_32ksynct_cr @ get addr of counter
116 ldr r5, [r3] @ get value 114 ldr r5, [r3] @ get value
117 add r5, r5, #0x3 @ give it at most 93uS 115 add r5, r5, #0x3 @ give it at most 93uS
118volt_delay: 116volt_delay:
@@ -121,32 +119,31 @@ volt_delay:
121 bhi volt_delay @ not yet->branch 119 bhi volt_delay @ not yet->branch
122 mov pc, lr @ back to caller. 120 mov pc, lr @ back to caller.
123 121
124/* relative load constants */ 122omap242x_sdi_cm_clksel2_pll:
125cm_clksel2_pll:
126 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2) 123 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
127sdrc_dlla_ctrl: 124omap242x_sdi_sdrc_dlla_ctrl:
128 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) 125 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
129prcm_voltctrl: 126omap242x_sdi_prcm_voltctrl:
130 .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50) 127 .word OMAP242X_PRCM_VOLTCTRL
131prcm_mask_val: 128prcm_mask_val:
132 .word 0xFFFF3FFC 129 .word 0xFFFF3FFC
133timer_32ksynct_cr: 130omap242x_sdi_timer_32ksynct_cr:
134 .word TIMER_32KSYNCT_CR_V 131 .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
135ENTRY(sram_ddr_init_sz) 132ENTRY(omap242x_sram_ddr_init_sz)
136 .word . - sram_ddr_init 133 .word . - omap242x_sram_ddr_init
137 134
138/* 135/*
139 * Reprograms memory timings. 136 * Reprograms memory timings.
140 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR] 137 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
141 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0 138 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
142 */ 139 */
143ENTRY(sram_reprogram_sdrc) 140ENTRY(omap242x_sram_reprogram_sdrc)
144 stmfd sp!, {r0 - r10, lr} @ save registers on stack 141 stmfd sp!, {r0 - r10, lr} @ save registers on stack
145 mov r3, #0x0 @ clear for mrc call 142 mov r3, #0x0 @ clear for mrc call
146 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR 143 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
147 nop 144 nop
148 nop 145 nop
149 ldr r6, ddr_sdrc_rfr_ctrl @ get addr of refresh reg 146 ldr r6, omap242x_srs_sdrc_rfr_ctrl @ get addr of refresh reg
150 ldr r5, [r6] @ get value 147 ldr r5, [r6] @ get value
151 mov r5, r5, lsr #8 @ isolate rfr field and drop burst 148 mov r5, r5, lsr #8 @ isolate rfr field and drop burst
152 149
@@ -160,7 +157,7 @@ ENTRY(sram_reprogram_sdrc)
160 movne r5, r5, lsl #1 @ mult by 2 if to full 157 movne r5, r5, lsl #1 @ mult by 2 if to full
161 mov r5, r5, lsl #8 @ put rfr field back into place 158 mov r5, r5, lsl #8 @ put rfr field back into place
162 add r5, r5, #0x1 @ turn on burst of 1 159 add r5, r5, #0x1 @ turn on burst of 1
163 ldr r4, ddr_cm_clksel2_pll @ get address of out reg 160 ldr r4, omap242x_srs_cm_clksel2_pll @ get address of out reg
164 ldr r3, [r4] @ get curr value 161 ldr r3, [r4] @ get curr value
165 orr r3, r3, #0x3 162 orr r3, r3, #0x3
166 bic r3, r3, #0x3 @ clear lower bits 163 bic r3, r3, #0x3 @ clear lower bits
@@ -181,7 +178,7 @@ ENTRY(sram_reprogram_sdrc)
181 bne freq_out @ leave if SDR, no DLL function 178 bne freq_out @ leave if SDR, no DLL function
182 179
183 /* With DDR, we need to take care of the DLL for the frequency change */ 180 /* With DDR, we need to take care of the DLL for the frequency change */
184 ldr r2, ddr_sdrc_dlla_ctrl @ addr of dlla ctrl 181 ldr r2, omap242x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
185 str r1, [r2] @ write out new SDRC_DLLA_CTRL 182 str r1, [r2] @ write out new SDRC_DLLA_CTRL
186 add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL 183 add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
187 str r1, [r2] @ commit to SDRC_DLLB_CTRL 184 str r1, [r2] @ commit to SDRC_DLLB_CTRL
@@ -197,7 +194,7 @@ freq_out:
197 * wait for it to finish, use 32k sync counter, 1tick=31uS. 194 * wait for it to finish, use 32k sync counter, 1tick=31uS.
198 */ 195 */
199voltage_shift_c: 196voltage_shift_c:
200 ldr r10, ddr_prcm_voltctrl @ get addr of volt ctrl 197 ldr r10, omap242x_srs_prcm_voltctrl @ get addr of volt ctrl
201 ldr r8, [r10] @ get value 198 ldr r8, [r10] @ get value
202 ldr r7, ddr_prcm_mask_val @ get value of mask 199 ldr r7, ddr_prcm_mask_val @ get value of mask
203 and r8, r8, r7 @ apply mask to clear bits 200 and r8, r8, r7 @ apply mask to clear bits
@@ -207,7 +204,7 @@ voltage_shift_c:
207 orr r8, r8, r7 @ build value for force 204 orr r8, r8, r7 @ build value for force
208 str r8, [r10] @ Force transition to L1 205 str r8, [r10] @ Force transition to L1
209 206
210 ldr r10, ddr_timer_32ksynct @ get addr of counter 207 ldr r10, omap242x_srs_timer_32ksynct @ get addr of counter
211 ldr r8, [r10] @ get value 208 ldr r8, [r10] @ get value
212 add r8, r8, #0x2 @ give it at most 62uS (min 31+) 209 add r8, r8, #0x2 @ give it at most 62uS (min 31+)
213volt_delay_c: 210volt_delay_c:
@@ -216,39 +213,39 @@ volt_delay_c:
216 bhi volt_delay_c @ not yet->branch 213 bhi volt_delay_c @ not yet->branch
217 mov pc, lr @ back to caller 214 mov pc, lr @ back to caller
218 215
219ddr_cm_clksel2_pll: 216omap242x_srs_cm_clksel2_pll:
220 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2) 217 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
221ddr_sdrc_dlla_ctrl: 218omap242x_srs_sdrc_dlla_ctrl:
222 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) 219 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
223ddr_sdrc_rfr_ctrl: 220omap242x_srs_sdrc_rfr_ctrl:
224 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0) 221 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
225ddr_prcm_voltctrl: 222omap242x_srs_prcm_voltctrl:
226 .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50) 223 .word OMAP242X_PRCM_VOLTCTRL
227ddr_prcm_mask_val: 224ddr_prcm_mask_val:
228 .word 0xFFFF3FFC 225 .word 0xFFFF3FFC
229ddr_timer_32ksynct: 226omap242x_srs_timer_32ksynct:
230 .word TIMER_32KSYNCT_CR_V 227 .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
231 228
232ENTRY(sram_reprogram_sdrc_sz) 229ENTRY(omap242x_sram_reprogram_sdrc_sz)
233 .word . - sram_reprogram_sdrc 230 .word . - omap242x_sram_reprogram_sdrc
234 231
235/* 232/*
236 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode. 233 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
237 */ 234 */
238ENTRY(sram_set_prcm) 235ENTRY(omap242x_sram_set_prcm)
239 stmfd sp!, {r0-r12, lr} @ regs to stack 236 stmfd sp!, {r0-r12, lr} @ regs to stack
240 adr r4, pbegin @ addr of preload start 237 adr r4, pbegin @ addr of preload start
241 adr r8, pend @ addr of preload end 238 adr r8, pend @ addr of preload end
242 mcrr p15, 1, r8, r4, c12 @ preload into icache 239 mcrr p15, 1, r8, r4, c12 @ preload into icache
243pbegin: 240pbegin:
244 /* move into fast relock bypass */ 241 /* move into fast relock bypass */
245 ldr r8, pll_ctl @ get addr 242 ldr r8, omap242x_ssp_pll_ctl @ get addr
246 ldr r5, [r8] @ get val 243 ldr r5, [r8] @ get val
247 mvn r6, #0x3 @ clear mask 244 mvn r6, #0x3 @ clear mask
248 and r5, r5, r6 @ clear field 245 and r5, r5, r6 @ clear field
249 orr r7, r5, #0x2 @ fast relock val 246 orr r7, r5, #0x2 @ fast relock val
250 str r7, [r8] @ go to fast relock 247 str r7, [r8] @ go to fast relock
251 ldr r4, pll_stat @ addr of stat 248 ldr r4, omap242x_ssp_pll_stat @ addr of stat
252block: 249block:
253 /* wait for bypass */ 250 /* wait for bypass */
254 ldr r8, [r4] @ stat value 251 ldr r8, [r4] @ stat value
@@ -257,10 +254,10 @@ block:
257 bne block @ loop if not 254 bne block @ loop if not
258 255
259 /* set new dpll dividers _after_ in bypass */ 256 /* set new dpll dividers _after_ in bypass */
260 ldr r4, pll_div @ get addr 257 ldr r4, omap242x_ssp_pll_div @ get addr
261 str r0, [r4] @ set dpll ctrl val 258 str r0, [r4] @ set dpll ctrl val
262 259
263 ldr r4, set_config @ get addr 260 ldr r4, omap242x_ssp_set_config @ get addr
264 mov r8, #1 @ valid cfg msk 261 mov r8, #1 @ valid cfg msk
265 str r8, [r4] @ make dividers take 262 str r8, [r4] @ make dividers take
266 263
@@ -274,8 +271,8 @@ wait_a_bit:
274 beq pend @ jump over dpll relock 271 beq pend @ jump over dpll relock
275 272
276 /* relock DPLL with new vals */ 273 /* relock DPLL with new vals */
277 ldr r5, pll_stat @ get addr 274 ldr r5, omap242x_ssp_pll_stat @ get addr
278 ldr r4, pll_ctl @ get addr 275 ldr r4, omap242x_ssp_pll_ctl @ get addr
279 orr r8, r7, #0x3 @ val for lock dpll 276 orr r8, r7, #0x3 @ val for lock dpll
280 str r8, [r4] @ set val 277 str r8, [r4] @ set val
281 mov r0, #1000 @ dead spin a bit 278 mov r0, #1000 @ dead spin a bit
@@ -289,9 +286,9 @@ wait_lock:
289 bne wait_lock @ wait if not 286 bne wait_lock @ wait if not
290pend: 287pend:
291 /* update memory timings & briefly lock dll */ 288 /* update memory timings & briefly lock dll */
292 ldr r4, sdrc_rfr @ get addr 289 ldr r4, omap242x_ssp_sdrc_rfr @ get addr
293 str r1, [r4] @ update refresh timing 290 str r1, [r4] @ update refresh timing
294 ldr r11, dlla_ctrl @ get addr of DLLA ctrl 291 ldr r11, omap242x_ssp_dlla_ctrl @ get addr of DLLA ctrl
295 ldr r10, [r11] @ get current val 292 ldr r10, [r11] @ get current val
296 mvn r9, #0x4 @ mask to get clear bit2 293 mvn r9, #0x4 @ mask to get clear bit2
297 and r10, r10, r9 @ clear bit2 for lock mode 294 and r10, r10, r9 @ clear bit2 for lock mode
@@ -307,18 +304,18 @@ wait_dll_lock:
307 nop 304 nop
308 ldmfd sp!, {r0-r12, pc} @ restore regs and return 305 ldmfd sp!, {r0-r12, pc} @ restore regs and return
309 306
310set_config: 307omap242x_ssp_set_config:
311 .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x80) 308 .word OMAP242X_PRCM_CLKCFG_CTRL
312pll_ctl: 309omap242x_ssp_pll_ctl:
313 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_FCLKEN1) 310 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
314pll_stat: 311omap242x_ssp_pll_stat:
315 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST1) 312 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST)
316pll_div: 313omap242x_ssp_pll_div:
317 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL) 314 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
318sdrc_rfr: 315omap242x_ssp_sdrc_rfr:
319 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0) 316 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
320dlla_ctrl: 317omap242x_ssp_dlla_ctrl:
321 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) 318 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
322 319
323ENTRY(sram_set_prcm_sz) 320ENTRY(omap242x_sram_set_prcm_sz)
324 .word . - sram_set_prcm 321 .word . - omap242x_sram_set_prcm
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
new file mode 100644
index 000000000000..a3fa48dc08cd
--- /dev/null
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -0,0 +1,321 @@
1/*
2 * linux/arch/arm/mach-omap2/sram243x.S
3 *
4 * Omap2 specific functions that need to be run in internal SRAM
5 *
6 * (C) Copyright 2004
7 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25#include <linux/linkage.h>
26#include <asm/assembler.h>
27#include <asm/arch/io.h>
28#include <asm/hardware.h>
29
30#include "prm.h"
31#include "cm.h"
32#include "sdrc.h"
33
34 .text
35
36ENTRY(omap243x_sram_ddr_init)
37 stmfd sp!, {r0 - r12, lr} @ save registers on stack
38
39 mov r12, r2 @ capture CS1 vs CS0
40 mov r8, r3 @ capture force parameter
41
42 /* frequency shift down */
43 ldr r2, omap243x_sdi_cm_clksel2_pll @ get address of dpllout reg
44 mov r3, #0x1 @ value for 1x operation
45 str r3, [r2] @ go to L1-freq operation
46
47 /* voltage shift down */
48 mov r9, #0x1 @ set up for L1 voltage call
49 bl voltage_shift @ go drop voltage
50
51 /* dll lock mode */
52 ldr r11, omap243x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
53 ldr r10, [r11] @ get current val
54 cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
55 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
56 mvn r9, #0x4 @ mask to get clear bit2
57 and r10, r10, r9 @ clear bit2 for lock mode.
58 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
59 orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz
60 str r10, [r11] @ commit to DLLA_CTRL
61 bl i_dll_wait @ wait for dll to lock
62
63 /* get dll value */
64 add r11, r11, #0x4 @ get addr of status reg
65 ldr r10, [r11] @ get locked value
66
67 /* voltage shift up */
68 mov r9, #0x0 @ shift back to L0-voltage
69 bl voltage_shift @ go raise voltage
70
71 /* frequency shift up */
72 mov r3, #0x2 @ value for 2x operation
73 str r3, [r2] @ go to L0-freq operation
74
75 /* reset entry mode for dllctrl */
76 sub r11, r11, #0x4 @ move from status to ctrl
77 cmp r12, #0x1 @ normalize if cs1 based
78 subeq r11, r11, #0x8 @ possibly back to DLLA
79 cmp r8, #0x1 @ if forced unlock exit
80 orreq r1, r1, #0x4 @ make sure exit with unlocked value
81 str r1, [r11] @ restore DLLA_CTRL high value
82 add r11, r11, #0x8 @ move to DLLB_CTRL addr
83 str r1, [r11] @ set value DLLB_CTRL
84 bl i_dll_wait @ wait for possible lock
85
86 /* set up for return, DDR should be good */
87 str r10, [r0] @ write dll_status and return counter
88 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
89
90 /* ensure the DLL has relocked */
91i_dll_wait:
92 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
93i_dll_delay:
94 subs r4, r4, #0x1
95 bne i_dll_delay
96 mov pc, lr
97
98 /*
99 * shift up or down voltage, use R9 as input to tell level.
100 * wait for it to finish, use 32k sync counter, 1tick=31uS.
101 */
102voltage_shift:
103 ldr r4, omap243x_sdi_prcm_voltctrl @ get addr of volt ctrl.
104 ldr r5, [r4] @ get value.
105 ldr r6, prcm_mask_val @ get value of mask
106 and r5, r5, r6 @ apply mask to clear bits
107 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
108 str r5, [r4] @ set up for change.
109 mov r3, #0x4000 @ get val for force
110 orr r5, r5, r3 @ build value for force
111 str r5, [r4] @ Force transition to L1
112
113 ldr r3, omap243x_sdi_timer_32ksynct_cr @ get addr of counter
114 ldr r5, [r3] @ get value
115 add r5, r5, #0x3 @ give it at most 93uS
116volt_delay:
117 ldr r7, [r3] @ get timer value
118 cmp r5, r7 @ time up?
119 bhi volt_delay @ not yet->branch
120 mov pc, lr @ back to caller.
121
122omap243x_sdi_cm_clksel2_pll:
123 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
124omap243x_sdi_sdrc_dlla_ctrl:
125 .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
126omap243x_sdi_prcm_voltctrl:
127 .word OMAP243X_PRCM_VOLTCTRL
128prcm_mask_val:
129 .word 0xFFFF3FFC
130omap243x_sdi_timer_32ksynct_cr:
131 .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
132ENTRY(omap243x_sram_ddr_init_sz)
133 .word . - omap243x_sram_ddr_init
134
135/*
136 * Reprograms memory timings.
137 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
138 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
139 */
140ENTRY(omap243x_sram_reprogram_sdrc)
141 stmfd sp!, {r0 - r10, lr} @ save registers on stack
142 mov r3, #0x0 @ clear for mrc call
143 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
144 nop
145 nop
146 ldr r6, omap243x_srs_sdrc_rfr_ctrl @ get addr of refresh reg
147 ldr r5, [r6] @ get value
148 mov r5, r5, lsr #8 @ isolate rfr field and drop burst
149
150 cmp r0, #0x1 @ going to half speed?
151 movne r9, #0x0 @ if up set flag up for pre up, hi volt
152
153 blne voltage_shift_c @ adjust voltage
154
155 cmp r0, #0x1 @ going to half speed (post branch link)
156 moveq r5, r5, lsr #1 @ divide by 2 if to half
157 movne r5, r5, lsl #1 @ mult by 2 if to full
158 mov r5, r5, lsl #8 @ put rfr field back into place
159 add r5, r5, #0x1 @ turn on burst of 1
160 ldr r4, omap243x_srs_cm_clksel2_pll @ get address of out reg
161 ldr r3, [r4] @ get curr value
162 orr r3, r3, #0x3
163 bic r3, r3, #0x3 @ clear lower bits
164 orr r3, r3, r0 @ new state value
165 str r3, [r4] @ set new state (pll/x, x=1 or 2)
166 nop
167 nop
168
169 moveq r9, #0x1 @ if speed down, post down, drop volt
170 bleq voltage_shift_c
171
172 mcr p15, 0, r3, c7, c10, 4 @ memory barrier
173 str r5, [r6] @ set new RFR_1 value
174 add r6, r6, #0x30 @ get RFR_2 addr
175 str r5, [r6] @ set RFR_2
176 nop
177 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
178 bne freq_out @ leave if SDR, no DLL function
179
180 /* With DDR, we need to take care of the DLL for the frequency change */
181 ldr r2, omap243x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
182 str r1, [r2] @ write out new SDRC_DLLA_CTRL
183 add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
184 str r1, [r2] @ commit to SDRC_DLLB_CTRL
185 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
186dll_wait:
187 subs r1, r1, #0x1
188 bne dll_wait
189freq_out:
190 ldmfd sp!, {r0 - r10, pc} @ restore regs and return
191
192 /*
193 * shift up or down voltage, use R9 as input to tell level.
194 * wait for it to finish, use 32k sync counter, 1tick=31uS.
195 */
196voltage_shift_c:
197 ldr r10, omap243x_srs_prcm_voltctrl @ get addr of volt ctrl
198 ldr r8, [r10] @ get value
199 ldr r7, ddr_prcm_mask_val @ get value of mask
200 and r8, r8, r7 @ apply mask to clear bits
201 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
202 str r8, [r10] @ set up for change.
203 mov r7, #0x4000 @ get val for force
204 orr r8, r8, r7 @ build value for force
205 str r8, [r10] @ Force transition to L1
206
207 ldr r10, omap243x_srs_timer_32ksynct @ get addr of counter
208 ldr r8, [r10] @ get value
209 add r8, r8, #0x2 @ give it at most 62uS (min 31+)
210volt_delay_c:
211 ldr r7, [r10] @ get timer value
212 cmp r8, r7 @ time up?
213 bhi volt_delay_c @ not yet->branch
214 mov pc, lr @ back to caller
215
216omap243x_srs_cm_clksel2_pll:
217 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
218omap243x_srs_sdrc_dlla_ctrl:
219 .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
220omap243x_srs_sdrc_rfr_ctrl:
221 .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
222omap243x_srs_prcm_voltctrl:
223 .word OMAP243X_PRCM_VOLTCTRL
224ddr_prcm_mask_val:
225 .word 0xFFFF3FFC
226omap243x_srs_timer_32ksynct:
227 .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
228
229ENTRY(omap243x_sram_reprogram_sdrc_sz)
230 .word . - omap243x_sram_reprogram_sdrc
231
232/*
233 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
234 */
235ENTRY(omap243x_sram_set_prcm)
236 stmfd sp!, {r0-r12, lr} @ regs to stack
237 adr r4, pbegin @ addr of preload start
238 adr r8, pend @ addr of preload end
239 mcrr p15, 1, r8, r4, c12 @ preload into icache
240pbegin:
241 /* move into fast relock bypass */
242 ldr r8, omap243x_ssp_pll_ctl @ get addr
243 ldr r5, [r8] @ get val
244 mvn r6, #0x3 @ clear mask
245 and r5, r5, r6 @ clear field
246 orr r7, r5, #0x2 @ fast relock val
247 str r7, [r8] @ go to fast relock
248 ldr r4, omap243x_ssp_pll_stat @ addr of stat
249block:
250 /* wait for bypass */
251 ldr r8, [r4] @ stat value
252 and r8, r8, #0x3 @ mask for stat
253 cmp r8, #0x1 @ there yet
254 bne block @ loop if not
255
256 /* set new dpll dividers _after_ in bypass */
257 ldr r4, omap243x_ssp_pll_div @ get addr
258 str r0, [r4] @ set dpll ctrl val
259
260 ldr r4, omap243x_ssp_set_config @ get addr
261 mov r8, #1 @ valid cfg msk
262 str r8, [r4] @ make dividers take
263
264 mov r4, #100 @ dead spin a bit
265wait_a_bit:
266 subs r4, r4, #1 @ dec loop
267 bne wait_a_bit @ delay done?
268
269 /* check if staying in bypass */
270 cmp r2, #0x1 @ stay in bypass?
271 beq pend @ jump over dpll relock
272
273 /* relock DPLL with new vals */
274 ldr r5, omap243x_ssp_pll_stat @ get addr
275 ldr r4, omap243x_ssp_pll_ctl @ get addr
276 orr r8, r7, #0x3 @ val for lock dpll
277 str r8, [r4] @ set val
278 mov r0, #1000 @ dead spin a bit
279wait_more:
280 subs r0, r0, #1 @ dec loop
281 bne wait_more @ delay done?
282wait_lock:
283 ldr r8, [r5] @ get lock val
284 and r8, r8, #3 @ isolate field
285 cmp r8, #2 @ locked?
286 bne wait_lock @ wait if not
287pend:
288 /* update memory timings & briefly lock dll */
289 ldr r4, omap243x_ssp_sdrc_rfr @ get addr
290 str r1, [r4] @ update refresh timing
291 ldr r11, omap243x_ssp_dlla_ctrl @ get addr of DLLA ctrl
292 ldr r10, [r11] @ get current val
293 mvn r9, #0x4 @ mask to get clear bit2
294 and r10, r10, r9 @ clear bit2 for lock mode
295 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
296 str r10, [r11] @ commit to DLLA_CTRL
297 add r11, r11, #0x8 @ move to dllb
298 str r10, [r11] @ hit DLLB also
299
300 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
301wait_dll_lock:
302 subs r4, r4, #0x1
303 bne wait_dll_lock
304 nop
305 ldmfd sp!, {r0-r12, pc} @ restore regs and return
306
307omap243x_ssp_set_config:
308 .word OMAP243X_PRCM_CLKCFG_CTRL
309omap243x_ssp_pll_ctl:
310 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
311omap243x_ssp_pll_stat:
312 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST)
313omap243x_ssp_pll_div:
314 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
315omap243x_ssp_sdrc_rfr:
316 .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
317omap243x_ssp_dlla_ctrl:
318 .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
319
320ENTRY(omap243x_sram_set_prcm_sz)
321 .word . - omap243x_sram_set_prcm
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 1f23f0459e5f..554ee58e1294 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -10,6 +10,7 @@
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13#undef DEBUG
13 14
14#include <linux/module.h> 15#include <linux/module.h>
15#include <linux/kernel.h> 16#include <linux/kernel.h>
@@ -24,25 +25,43 @@
24#include <asm/arch/sram.h> 25#include <asm/arch/sram.h>
25#include <asm/arch/board.h> 26#include <asm/arch/board.h>
26 27
28#include <asm/arch/control.h>
29
30#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
31# include "../mach-omap2/prm.h"
32# include "../mach-omap2/cm.h"
33# include "../mach-omap2/sdrc.h"
34#endif
35
27#define OMAP1_SRAM_PA 0x20000000 36#define OMAP1_SRAM_PA 0x20000000
28#define OMAP1_SRAM_VA 0xd0000000 37#define OMAP1_SRAM_VA VMALLOC_END
29#define OMAP2_SRAM_PA 0x40200000 38#define OMAP2_SRAM_PA 0x40200000
30#define OMAP2_SRAM_PUB_PA 0x4020f800 39#define OMAP2_SRAM_PUB_PA 0x4020f800
31#define OMAP2_SRAM_VA 0xd0000000 40#define OMAP2_SRAM_VA VMALLOC_END
32#define OMAP2_SRAM_PUB_VA 0xd0000800 41#define OMAP2_SRAM_PUB_VA (VMALLOC_END + 0x800)
33 42#define OMAP3_SRAM_PA 0x40200000
34#if defined(CONFIG_ARCH_OMAP24XX) 43#define OMAP3_SRAM_VA 0xd7000000
44#define OMAP3_SRAM_PUB_PA 0x40208000
45#define OMAP3_SRAM_PUB_VA 0xd7008000
46
47#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
35#define SRAM_BOOTLOADER_SZ 0x00 48#define SRAM_BOOTLOADER_SZ 0x00
36#else 49#else
37#define SRAM_BOOTLOADER_SZ 0x80 50#define SRAM_BOOTLOADER_SZ 0x80
38#endif 51#endif
39 52
40#define VA_REQINFOPERM0 IO_ADDRESS(0x68005048) 53#define OMAP24XX_VA_REQINFOPERM0 IO_ADDRESS(0x68005048)
41#define VA_READPERM0 IO_ADDRESS(0x68005050) 54#define OMAP24XX_VA_READPERM0 IO_ADDRESS(0x68005050)
42#define VA_WRITEPERM0 IO_ADDRESS(0x68005058) 55#define OMAP24XX_VA_WRITEPERM0 IO_ADDRESS(0x68005058)
43#define VA_CONTROL_STAT IO_ADDRESS(0x480002F8) 56
57#define OMAP34XX_VA_REQINFOPERM0 IO_ADDRESS(0x68012848)
58#define OMAP34XX_VA_READPERM0 IO_ADDRESS(0x68012850)
59#define OMAP34XX_VA_WRITEPERM0 IO_ADDRESS(0x68012858)
60#define OMAP34XX_VA_ADDR_MATCH2 IO_ADDRESS(0x68012880)
61#define OMAP34XX_VA_SMS_RG_ATT0 IO_ADDRESS(0x6C000048)
62#define OMAP34XX_VA_CONTROL_STAT IO_ADDRESS(0x480022F0)
63
44#define GP_DEVICE 0x300 64#define GP_DEVICE 0x300
45#define TYPE_MASK 0x700
46 65
47#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) 66#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
48 67
@@ -68,14 +87,21 @@ static int is_sram_locked(void)
68 int type = 0; 87 int type = 0;
69 88
70 if (cpu_is_omap242x()) 89 if (cpu_is_omap242x())
71 type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK; 90 type = system_rev & OMAP2_DEVICETYPE_MASK;
72 91
73 if (type == GP_DEVICE) { 92 if (type == GP_DEVICE) {
74 /* RAMFW: R/W access to all initiators for all qualifier sets */ 93 /* RAMFW: R/W access to all initiators for all qualifier sets */
75 if (cpu_is_omap242x()) { 94 if (cpu_is_omap242x()) {
76 __raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */ 95 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
77 __raw_writel(0xCFDE, VA_READPERM0); /* all i-read */ 96 __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
78 __raw_writel(0xCFDE, VA_WRITEPERM0); /* all i-write */ 97 __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
98 }
99 if (cpu_is_omap34xx()) {
100 __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
101 __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
102 __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
103 __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
104 __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
79 } 105 }
80 return 0; 106 return 0;
81 } else 107 } else
@@ -92,18 +118,30 @@ void __init omap_detect_sram(void)
92{ 118{
93 unsigned long reserved; 119 unsigned long reserved;
94 120
95 if (cpu_is_omap24xx()) { 121 if (cpu_class_is_omap2()) {
96 if (is_sram_locked()) { 122 if (is_sram_locked()) {
97 omap_sram_base = OMAP2_SRAM_PUB_VA; 123 if (cpu_is_omap34xx()) {
98 omap_sram_start = OMAP2_SRAM_PUB_PA; 124 omap_sram_base = OMAP3_SRAM_PUB_VA;
99 omap_sram_size = 0x800; /* 2K */ 125 omap_sram_start = OMAP3_SRAM_PUB_PA;
126 omap_sram_size = 0x8000; /* 32K */
127 } else {
128 omap_sram_base = OMAP2_SRAM_PUB_VA;
129 omap_sram_start = OMAP2_SRAM_PUB_PA;
130 omap_sram_size = 0x800; /* 2K */
131 }
100 } else { 132 } else {
101 omap_sram_base = OMAP2_SRAM_VA; 133 if (cpu_is_omap34xx()) {
102 omap_sram_start = OMAP2_SRAM_PA; 134 omap_sram_base = OMAP3_SRAM_VA;
103 if (cpu_is_omap242x()) 135 omap_sram_start = OMAP3_SRAM_PA;
104 omap_sram_size = 0xa0000; /* 640K */
105 else if (cpu_is_omap243x())
106 omap_sram_size = 0x10000; /* 64K */ 136 omap_sram_size = 0x10000; /* 64K */
137 } else {
138 omap_sram_base = OMAP2_SRAM_VA;
139 omap_sram_start = OMAP2_SRAM_PA;
140 if (cpu_is_omap242x())
141 omap_sram_size = 0xa0000; /* 640K */
142 else if (cpu_is_omap243x())
143 omap_sram_size = 0x10000; /* 64K */
144 }
107 } 145 }
108 } else { 146 } else {
109 omap_sram_base = OMAP1_SRAM_VA; 147 omap_sram_base = OMAP1_SRAM_VA;
@@ -157,6 +195,13 @@ void __init omap_map_sram(void)
157 omap_sram_io_desc[0].pfn = __phys_to_pfn(base); 195 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
158 } 196 }
159 197
198 if (cpu_is_omap34xx()) {
199 omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
200 base = OMAP3_SRAM_PA;
201 base = ROUND_DOWN(base, PAGE_SIZE);
202 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
203 }
204
160 omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */ 205 omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
161 iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); 206 iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
162 207
@@ -191,6 +236,7 @@ void * omap_sram_push(void * start, unsigned long size)
191 omap_sram_ceil -= size; 236 omap_sram_ceil -= size;
192 omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *)); 237 omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
193 memcpy((void *)omap_sram_ceil, start, size); 238 memcpy((void *)omap_sram_ceil, start, size);
239 flush_icache_range((unsigned long)start, (unsigned long)(start + size));
194 240
195 return (void *)omap_sram_ceil; 241 return (void *)omap_sram_ceil;
196} 242}
@@ -214,8 +260,9 @@ void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
214 260
215int __init omap1_sram_init(void) 261int __init omap1_sram_init(void)
216{ 262{
217 _omap_sram_reprogram_clock = omap_sram_push(sram_reprogram_clock, 263 _omap_sram_reprogram_clock =
218 sram_reprogram_clock_sz); 264 omap_sram_push(omap1_sram_reprogram_clock,
265 omap1_sram_reprogram_clock_sz);
219 266
220 return 0; 267 return 0;
221} 268}
@@ -224,7 +271,7 @@ int __init omap1_sram_init(void)
224#define omap1_sram_init() do {} while (0) 271#define omap1_sram_init() do {} while (0)
225#endif 272#endif
226 273
227#ifdef CONFIG_ARCH_OMAP2 274#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
228 275
229static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 276static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
230 u32 base_cs, u32 force_unlock); 277 u32 base_cs, u32 force_unlock);
@@ -259,19 +306,109 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
259 306
260 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass); 307 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
261} 308}
309#endif
310
311#ifdef CONFIG_ARCH_OMAP2420
312int __init omap242x_sram_init(void)
313{
314 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
315 omap242x_sram_ddr_init_sz);
316
317 _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
318 omap242x_sram_reprogram_sdrc_sz);
319
320 _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
321 omap242x_sram_set_prcm_sz);
322
323 return 0;
324}
325#else
326static inline int omap242x_sram_init(void)
327{
328 return 0;
329}
330#endif
331
332#ifdef CONFIG_ARCH_OMAP2430
333int __init omap243x_sram_init(void)
334{
335 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
336 omap243x_sram_ddr_init_sz);
337
338 _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
339 omap243x_sram_reprogram_sdrc_sz);
340
341 _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
342 omap243x_sram_set_prcm_sz);
343
344 return 0;
345}
346#else
347static inline int omap243x_sram_init(void)
348{
349 return 0;
350}
351#endif
352
353#ifdef CONFIG_ARCH_OMAP3
354
355static u32 (*_omap2_sram_reprogram_gpmc)(u32 perf_level);
356u32 omap2_sram_reprogram_gpmc(u32 perf_level)
357{
358 if (!_omap2_sram_reprogram_gpmc)
359 omap_sram_error();
360
361 return _omap2_sram_reprogram_gpmc(perf_level);
362}
363
364static u32 (*_omap2_sram_configure_core_dpll)(u32 m, u32 n,
365 u32 freqsel, u32 m2);
366u32 omap2_sram_configure_core_dpll(u32 m, u32 n, u32 freqsel, u32 m2)
367{
368 if (!_omap2_sram_configure_core_dpll)
369 omap_sram_error();
370
371 return _omap2_sram_configure_core_dpll(m, n, freqsel, m2);
372}
262 373
263int __init omap2_sram_init(void) 374/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
375void restore_sram_functions(void)
264{ 376{
265 _omap2_sram_ddr_init = omap_sram_push(sram_ddr_init, sram_ddr_init_sz); 377 omap_sram_ceil = omap_sram_base + omap_sram_size;
266 378
267 _omap2_sram_reprogram_sdrc = omap_sram_push(sram_reprogram_sdrc, 379 _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
268 sram_reprogram_sdrc_sz); 380 omap34xx_sram_reprogram_gpmc_sz);
269 _omap2_set_prcm = omap_sram_push(sram_set_prcm, sram_set_prcm_sz); 381
382 _omap2_sram_configure_core_dpll =
383 omap_sram_push(omap34xx_sram_configure_core_dpll,
384 omap34xx_sram_configure_core_dpll_sz);
385}
386
387int __init omap34xx_sram_init(void)
388{
389 _omap2_sram_ddr_init = omap_sram_push(omap34xx_sram_ddr_init,
390 omap34xx_sram_ddr_init_sz);
391
392 _omap2_sram_reprogram_sdrc = omap_sram_push(omap34xx_sram_reprogram_sdrc,
393 omap34xx_sram_reprogram_sdrc_sz);
394
395 _omap2_set_prcm = omap_sram_push(omap34xx_sram_set_prcm,
396 omap34xx_sram_set_prcm_sz);
397
398 _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
399 omap34xx_sram_reprogram_gpmc_sz);
400
401 _omap2_sram_configure_core_dpll =
402 omap_sram_push(omap34xx_sram_configure_core_dpll,
403 omap34xx_sram_configure_core_dpll_sz);
270 404
271 return 0; 405 return 0;
272} 406}
273#else 407#else
274#define omap2_sram_init() do {} while (0) 408static inline int omap34xx_sram_init(void)
409{
410 return 0;
411}
275#endif 412#endif
276 413
277int __init omap_sram_init(void) 414int __init omap_sram_init(void)
@@ -279,10 +416,14 @@ int __init omap_sram_init(void)
279 omap_detect_sram(); 416 omap_detect_sram();
280 omap_map_sram(); 417 omap_map_sram();
281 418
282 if (!cpu_is_omap24xx()) 419 if (!(cpu_class_is_omap2()))
283 omap1_sram_init(); 420 omap1_sram_init();
284 else 421 else if (cpu_is_omap242x())
285 omap2_sram_init(); 422 omap242x_sram_init();
423 else if (cpu_is_omap2430())
424 omap243x_sram_init();
425 else if (cpu_is_omap34xx())
426 omap34xx_sram_init();
286 427
287 return 0; 428 return 0;
288} 429}
diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h
index bb9bb3fd532f..be59f4a9828b 100644
--- a/include/asm-arm/arch-omap/sram.h
+++ b/include/asm-arm/arch-omap/sram.h
@@ -11,6 +11,7 @@
11#ifndef __ARCH_ARM_OMAP_SRAM_H 11#ifndef __ARCH_ARM_OMAP_SRAM_H
12#define __ARCH_ARM_OMAP_SRAM_H 12#define __ARCH_ARM_OMAP_SRAM_H
13 13
14extern int __init omap_sram_init(void);
14extern void * omap_sram_push(void * start, unsigned long size); 15extern void * omap_sram_push(void * start, unsigned long size);
15extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); 16extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
16 17
@@ -21,17 +22,35 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
21extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 22extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
22 23
23/* Do not use these */ 24/* Do not use these */
24extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl); 25extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
25extern unsigned long sram_reprogram_clock_sz; 26extern unsigned long omap1_sram_reprogram_clock_sz;
26 27
27extern void sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 28extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
28 u32 base_cs, u32 force_unlock); 29extern unsigned long omap24xx_sram_reprogram_clock_sz;
29extern unsigned long sram_ddr_init_sz;
30 30
31extern u32 sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 31extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
32extern unsigned long sram_set_prcm_sz; 32 u32 base_cs, u32 force_unlock);
33extern unsigned long omap242x_sram_ddr_init_sz;
33 34
34extern void sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type); 35extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
35extern unsigned long sram_reprogram_sdrc_sz; 36 int bypass);
37extern unsigned long omap242x_sram_set_prcm_sz;
38
39extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
40 u32 mem_type);
41extern unsigned long omap242x_sram_reprogram_sdrc_sz;
42
43
44extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
45 u32 base_cs, u32 force_unlock);
46extern unsigned long omap243x_sram_ddr_init_sz;
47
48extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
49 int bypass);
50extern unsigned long omap243x_sram_set_prcm_sz;
51
52extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
53 u32 mem_type);
54extern unsigned long omap243x_sram_reprogram_sdrc_sz;
36 55
37#endif 56#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 15:38:02 -0500